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/drivers/net/ethernet/ti/davinci_emac.c

http://github.com/mirrors/linux
C | 2070 lines | 1390 code | 284 blank | 396 comment | 196 complexity | 88dadc01b8c91ad207206d3e647f7d17 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DaVinci Ethernet Medium Access Controller
  4. *
  5. * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
  6. *
  7. * Copyright (C) 2009 Texas Instruments.
  8. *
  9. * ---------------------------------------------------------------------------
  10. * History:
  11. * 0-5 A number of folks worked on this driver in bits and pieces but the major
  12. * contribution came from Suraj Iyer and Anant Gole
  13. * 6.0 Anant Gole - rewrote the driver as per Linux conventions
  14. * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
  15. * PHY layer usage
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/sched.h>
  20. #include <linux/string.h>
  21. #include <linux/timer.h>
  22. #include <linux/errno.h>
  23. #include <linux/in.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/mm.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/init.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/highmem.h>
  34. #include <linux/proc_fs.h>
  35. #include <linux/ctype.h>
  36. #include <linux/spinlock.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/clk.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/regmap.h>
  41. #include <linux/semaphore.h>
  42. #include <linux/phy.h>
  43. #include <linux/bitops.h>
  44. #include <linux/io.h>
  45. #include <linux/uaccess.h>
  46. #include <linux/pm_runtime.h>
  47. #include <linux/davinci_emac.h>
  48. #include <linux/of.h>
  49. #include <linux/of_address.h>
  50. #include <linux/of_device.h>
  51. #include <linux/of_mdio.h>
  52. #include <linux/of_irq.h>
  53. #include <linux/of_net.h>
  54. #include <linux/mfd/syscon.h>
  55. #include <asm/irq.h>
  56. #include <asm/page.h>
  57. #include "cpsw.h"
  58. #include "davinci_cpdma.h"
  59. static int debug_level;
  60. module_param(debug_level, int, 0);
  61. MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
  62. /* Netif debug messages possible */
  63. #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
  64. NETIF_MSG_PROBE | \
  65. NETIF_MSG_LINK | \
  66. NETIF_MSG_TIMER | \
  67. NETIF_MSG_IFDOWN | \
  68. NETIF_MSG_IFUP | \
  69. NETIF_MSG_RX_ERR | \
  70. NETIF_MSG_TX_ERR | \
  71. NETIF_MSG_TX_QUEUED | \
  72. NETIF_MSG_INTR | \
  73. NETIF_MSG_TX_DONE | \
  74. NETIF_MSG_RX_STATUS | \
  75. NETIF_MSG_PKTDATA | \
  76. NETIF_MSG_HW | \
  77. NETIF_MSG_WOL)
  78. /* version info */
  79. #define EMAC_MAJOR_VERSION 6
  80. #define EMAC_MINOR_VERSION 1
  81. #define EMAC_MODULE_VERSION "6.1"
  82. MODULE_VERSION(EMAC_MODULE_VERSION);
  83. static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
  84. /* Configuration items */
  85. #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
  86. #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
  87. #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
  88. #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
  89. #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
  90. #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
  91. #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
  92. #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
  93. #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
  94. #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
  95. #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
  96. #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
  97. #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
  98. #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
  99. #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
  100. #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
  101. #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
  102. #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
  103. #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
  104. #define EMAC_DEF_RX_NUM_DESC (128)
  105. #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
  106. #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
  107. #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
  108. /* Buffer descriptor parameters */
  109. #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
  110. #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
  111. /* EMAC register related defines */
  112. #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
  113. #define EMAC_NUM_MULTICAST_BITS (64)
  114. #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
  115. #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
  116. #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
  117. #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
  118. #define EMAC_INT_MASK_CLEAR (0xFF)
  119. /* RX MBP register bit positions */
  120. #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
  121. #define EMAC_RXMBP_QOSEN_MASK BIT(29)
  122. #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
  123. #define EMAC_RXMBP_CMFEN_MASK BIT(24)
  124. #define EMAC_RXMBP_CSFEN_MASK BIT(23)
  125. #define EMAC_RXMBP_CEFEN_MASK BIT(22)
  126. #define EMAC_RXMBP_CAFEN_MASK BIT(21)
  127. #define EMAC_RXMBP_PROMCH_SHIFT (16)
  128. #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
  129. #define EMAC_RXMBP_BROADEN_MASK BIT(13)
  130. #define EMAC_RXMBP_BROADCH_SHIFT (8)
  131. #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
  132. #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
  133. #define EMAC_RXMBP_MULTICH_SHIFT (0)
  134. #define EMAC_RXMBP_MULTICH_MASK (0x7)
  135. #define EMAC_RXMBP_CHMASK (0x7)
  136. /* EMAC register definitions/bit maps used */
  137. # define EMAC_MBP_RXPROMISC (0x00200000)
  138. # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
  139. # define EMAC_MBP_RXBCAST (0x00002000)
  140. # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
  141. # define EMAC_MBP_RXMCAST (0x00000020)
  142. # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
  143. /* EMAC mac_control register */
  144. #define EMAC_MACCONTROL_TXPTYPE BIT(9)
  145. #define EMAC_MACCONTROL_TXPACEEN BIT(6)
  146. #define EMAC_MACCONTROL_GMIIEN BIT(5)
  147. #define EMAC_MACCONTROL_GIGABITEN BIT(7)
  148. #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
  149. #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
  150. /* GIGABIT MODE related bits */
  151. #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
  152. #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
  153. /* EMAC mac_status register */
  154. #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
  155. #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
  156. #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
  157. #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
  158. #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
  159. #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
  160. #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
  161. #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
  162. /* EMAC RX register masks */
  163. #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
  164. #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
  165. /* MAC_IN_VECTOR (0x180) register bit fields */
  166. #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
  167. #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
  168. #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
  169. #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
  170. /** NOTE:: For DM646x the IN_VECTOR has changed */
  171. #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
  172. #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
  173. #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
  174. #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
  175. /* CPPI bit positions */
  176. #define EMAC_CPPI_SOP_BIT BIT(31)
  177. #define EMAC_CPPI_EOP_BIT BIT(30)
  178. #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
  179. #define EMAC_CPPI_EOQ_BIT BIT(28)
  180. #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
  181. #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
  182. #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
  183. #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
  184. #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
  185. /* Max hardware defines */
  186. #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
  187. #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
  188. /* EMAC Peripheral Device Register Memory Layout structure */
  189. #define EMAC_MACINVECTOR 0x90
  190. #define EMAC_DM646X_MACEOIVECTOR 0x94
  191. #define EMAC_MACINTSTATRAW 0xB0
  192. #define EMAC_MACINTSTATMASKED 0xB4
  193. #define EMAC_MACINTMASKSET 0xB8
  194. #define EMAC_MACINTMASKCLEAR 0xBC
  195. #define EMAC_RXMBPENABLE 0x100
  196. #define EMAC_RXUNICASTSET 0x104
  197. #define EMAC_RXUNICASTCLEAR 0x108
  198. #define EMAC_RXMAXLEN 0x10C
  199. #define EMAC_RXBUFFEROFFSET 0x110
  200. #define EMAC_RXFILTERLOWTHRESH 0x114
  201. #define EMAC_MACCONTROL 0x160
  202. #define EMAC_MACSTATUS 0x164
  203. #define EMAC_EMCONTROL 0x168
  204. #define EMAC_FIFOCONTROL 0x16C
  205. #define EMAC_MACCONFIG 0x170
  206. #define EMAC_SOFTRESET 0x174
  207. #define EMAC_MACSRCADDRLO 0x1D0
  208. #define EMAC_MACSRCADDRHI 0x1D4
  209. #define EMAC_MACHASH1 0x1D8
  210. #define EMAC_MACHASH2 0x1DC
  211. #define EMAC_MACADDRLO 0x500
  212. #define EMAC_MACADDRHI 0x504
  213. #define EMAC_MACINDEX 0x508
  214. /* EMAC statistics registers */
  215. #define EMAC_RXGOODFRAMES 0x200
  216. #define EMAC_RXBCASTFRAMES 0x204
  217. #define EMAC_RXMCASTFRAMES 0x208
  218. #define EMAC_RXPAUSEFRAMES 0x20C
  219. #define EMAC_RXCRCERRORS 0x210
  220. #define EMAC_RXALIGNCODEERRORS 0x214
  221. #define EMAC_RXOVERSIZED 0x218
  222. #define EMAC_RXJABBER 0x21C
  223. #define EMAC_RXUNDERSIZED 0x220
  224. #define EMAC_RXFRAGMENTS 0x224
  225. #define EMAC_RXFILTERED 0x228
  226. #define EMAC_RXQOSFILTERED 0x22C
  227. #define EMAC_RXOCTETS 0x230
  228. #define EMAC_TXGOODFRAMES 0x234
  229. #define EMAC_TXBCASTFRAMES 0x238
  230. #define EMAC_TXMCASTFRAMES 0x23C
  231. #define EMAC_TXPAUSEFRAMES 0x240
  232. #define EMAC_TXDEFERRED 0x244
  233. #define EMAC_TXCOLLISION 0x248
  234. #define EMAC_TXSINGLECOLL 0x24C
  235. #define EMAC_TXMULTICOLL 0x250
  236. #define EMAC_TXEXCESSIVECOLL 0x254
  237. #define EMAC_TXLATECOLL 0x258
  238. #define EMAC_TXUNDERRUN 0x25C
  239. #define EMAC_TXCARRIERSENSE 0x260
  240. #define EMAC_TXOCTETS 0x264
  241. #define EMAC_NETOCTETS 0x280
  242. #define EMAC_RXSOFOVERRUNS 0x284
  243. #define EMAC_RXMOFOVERRUNS 0x288
  244. #define EMAC_RXDMAOVERRUNS 0x28C
  245. /* EMAC DM644x control registers */
  246. #define EMAC_CTRL_EWCTL (0x4)
  247. #define EMAC_CTRL_EWINTTCNT (0x8)
  248. /* EMAC DM644x control module masks */
  249. #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
  250. #define EMAC_DM644X_INTMIN_INTVL 0x1
  251. #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
  252. /* EMAC DM646X control module registers */
  253. #define EMAC_DM646X_CMINTCTRL 0x0C
  254. #define EMAC_DM646X_CMRXINTEN 0x14
  255. #define EMAC_DM646X_CMTXINTEN 0x18
  256. #define EMAC_DM646X_CMRXINTMAX 0x70
  257. #define EMAC_DM646X_CMTXINTMAX 0x74
  258. /* EMAC DM646X control module masks */
  259. #define EMAC_DM646X_INTPACEEN (0x3 << 16)
  260. #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
  261. #define EMAC_DM646X_CMINTMAX_CNT 63
  262. #define EMAC_DM646X_CMINTMIN_CNT 2
  263. #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
  264. #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
  265. /* EMAC EOI codes for C0 */
  266. #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
  267. #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
  268. /* EMAC Stats Clear Mask */
  269. #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
  270. /* emac_priv: EMAC private data structure
  271. *
  272. * EMAC adapter private data structure
  273. */
  274. struct emac_priv {
  275. u32 msg_enable;
  276. struct net_device *ndev;
  277. struct platform_device *pdev;
  278. struct napi_struct napi;
  279. char mac_addr[6];
  280. void __iomem *remap_addr;
  281. u32 emac_base_phys;
  282. void __iomem *emac_base;
  283. void __iomem *ctrl_base;
  284. struct cpdma_ctlr *dma;
  285. struct cpdma_chan *txchan;
  286. struct cpdma_chan *rxchan;
  287. u32 link; /* 1=link on, 0=link off */
  288. u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
  289. u32 duplex; /* Link duplex: 0=Half, 1=Full */
  290. u32 rx_buf_size;
  291. u32 isr_count;
  292. u32 coal_intvl;
  293. u32 bus_freq_mhz;
  294. u8 rmii_en;
  295. u8 version;
  296. u32 mac_hash1;
  297. u32 mac_hash2;
  298. u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
  299. u32 rx_addr_type;
  300. const char *phy_id;
  301. struct device_node *phy_node;
  302. spinlock_t lock;
  303. /*platform specific members*/
  304. void (*int_enable) (void);
  305. void (*int_disable) (void);
  306. };
  307. /* EMAC TX Host Error description strings */
  308. static char *emac_txhost_errcodes[16] = {
  309. "No error", "SOP error", "Ownership bit not set in SOP buffer",
  310. "Zero Next Buffer Descriptor Pointer Without EOP",
  311. "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
  312. "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
  313. "Reserved", "Reserved", "Reserved", "Reserved"
  314. };
  315. /* EMAC RX Host Error description strings */
  316. static char *emac_rxhost_errcodes[16] = {
  317. "No error", "Reserved", "Ownership bit not set in input buffer",
  318. "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
  319. "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
  320. "Reserved", "Reserved", "Reserved", "Reserved"
  321. };
  322. /* Helper macros */
  323. #define emac_read(reg) ioread32(priv->emac_base + (reg))
  324. #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
  325. #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
  326. #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
  327. /**
  328. * emac_get_drvinfo - Get EMAC driver information
  329. * @ndev: The DaVinci EMAC network adapter
  330. * @info: ethtool info structure containing name and version
  331. *
  332. * Returns EMAC driver information (name and version)
  333. *
  334. */
  335. static void emac_get_drvinfo(struct net_device *ndev,
  336. struct ethtool_drvinfo *info)
  337. {
  338. strlcpy(info->driver, emac_version_string, sizeof(info->driver));
  339. strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
  340. }
  341. /**
  342. * emac_get_coalesce - Get interrupt coalesce settings for this device
  343. * @ndev : The DaVinci EMAC network adapter
  344. * @coal : ethtool coalesce settings structure
  345. *
  346. * Fetch the current interrupt coalesce settings
  347. *
  348. */
  349. static int emac_get_coalesce(struct net_device *ndev,
  350. struct ethtool_coalesce *coal)
  351. {
  352. struct emac_priv *priv = netdev_priv(ndev);
  353. coal->rx_coalesce_usecs = priv->coal_intvl;
  354. return 0;
  355. }
  356. /**
  357. * emac_set_coalesce - Set interrupt coalesce settings for this device
  358. * @ndev : The DaVinci EMAC network adapter
  359. * @coal : ethtool coalesce settings structure
  360. *
  361. * Set interrupt coalesce parameters
  362. *
  363. */
  364. static int emac_set_coalesce(struct net_device *ndev,
  365. struct ethtool_coalesce *coal)
  366. {
  367. struct emac_priv *priv = netdev_priv(ndev);
  368. u32 int_ctrl, num_interrupts = 0;
  369. u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
  370. if (!coal->rx_coalesce_usecs)
  371. return -EINVAL;
  372. coal_intvl = coal->rx_coalesce_usecs;
  373. switch (priv->version) {
  374. case EMAC_VERSION_2:
  375. int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
  376. prescale = priv->bus_freq_mhz * 4;
  377. if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
  378. coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
  379. if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
  380. /*
  381. * Interrupt pacer works with 4us Pulse, we can
  382. * throttle further by dilating the 4us pulse.
  383. */
  384. addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
  385. if (addnl_dvdr > 1) {
  386. prescale *= addnl_dvdr;
  387. if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
  388. * addnl_dvdr))
  389. coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
  390. * addnl_dvdr);
  391. } else {
  392. addnl_dvdr = 1;
  393. coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
  394. }
  395. }
  396. num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
  397. int_ctrl |= EMAC_DM646X_INTPACEEN;
  398. int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
  399. int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
  400. emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
  401. emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
  402. emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
  403. break;
  404. default:
  405. int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
  406. int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
  407. prescale = coal_intvl * priv->bus_freq_mhz;
  408. if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
  409. prescale = EMAC_DM644X_EWINTCNT_MASK;
  410. coal_intvl = prescale / priv->bus_freq_mhz;
  411. }
  412. emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
  413. break;
  414. }
  415. printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
  416. priv->coal_intvl = coal_intvl;
  417. return 0;
  418. }
  419. /* ethtool_ops: DaVinci EMAC Ethtool structure
  420. *
  421. * Ethtool support for EMAC adapter
  422. */
  423. static const struct ethtool_ops ethtool_ops = {
  424. .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
  425. .get_drvinfo = emac_get_drvinfo,
  426. .get_link = ethtool_op_get_link,
  427. .get_coalesce = emac_get_coalesce,
  428. .set_coalesce = emac_set_coalesce,
  429. .get_ts_info = ethtool_op_get_ts_info,
  430. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  431. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  432. };
  433. /**
  434. * emac_update_phystatus - Update Phy status
  435. * @priv: The DaVinci EMAC private adapter structure
  436. *
  437. * Updates phy status and takes action for network queue if required
  438. * based upon link status
  439. *
  440. */
  441. static void emac_update_phystatus(struct emac_priv *priv)
  442. {
  443. u32 mac_control;
  444. u32 new_duplex;
  445. u32 cur_duplex;
  446. struct net_device *ndev = priv->ndev;
  447. mac_control = emac_read(EMAC_MACCONTROL);
  448. cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
  449. DUPLEX_FULL : DUPLEX_HALF;
  450. if (ndev->phydev)
  451. new_duplex = ndev->phydev->duplex;
  452. else
  453. new_duplex = DUPLEX_FULL;
  454. /* We get called only if link has changed (speed/duplex/status) */
  455. if ((priv->link) && (new_duplex != cur_duplex)) {
  456. priv->duplex = new_duplex;
  457. if (DUPLEX_FULL == priv->duplex)
  458. mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
  459. else
  460. mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
  461. }
  462. if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
  463. mac_control = emac_read(EMAC_MACCONTROL);
  464. mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
  465. EMAC_DM646X_MACCONTORL_GIGFORCE);
  466. } else {
  467. /* Clear the GIG bit and GIGFORCE bit */
  468. mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
  469. EMAC_DM646X_MACCONTORL_GIG);
  470. if (priv->rmii_en && (priv->speed == SPEED_100))
  471. mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
  472. else
  473. mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
  474. }
  475. /* Update mac_control if changed */
  476. emac_write(EMAC_MACCONTROL, mac_control);
  477. if (priv->link) {
  478. /* link ON */
  479. if (!netif_carrier_ok(ndev))
  480. netif_carrier_on(ndev);
  481. /* reactivate the transmit queue if it is stopped */
  482. if (netif_running(ndev) && netif_queue_stopped(ndev))
  483. netif_wake_queue(ndev);
  484. } else {
  485. /* link OFF */
  486. if (netif_carrier_ok(ndev))
  487. netif_carrier_off(ndev);
  488. if (!netif_queue_stopped(ndev))
  489. netif_stop_queue(ndev);
  490. }
  491. }
  492. /**
  493. * hash_get - Calculate hash value from mac address
  494. * @addr: mac address to delete from hash table
  495. *
  496. * Calculates hash value from mac address
  497. *
  498. */
  499. static u32 hash_get(u8 *addr)
  500. {
  501. u32 hash;
  502. u8 tmpval;
  503. int cnt;
  504. hash = 0;
  505. for (cnt = 0; cnt < 2; cnt++) {
  506. tmpval = *addr++;
  507. hash ^= (tmpval >> 2) ^ (tmpval << 4);
  508. tmpval = *addr++;
  509. hash ^= (tmpval >> 4) ^ (tmpval << 2);
  510. tmpval = *addr++;
  511. hash ^= (tmpval >> 6) ^ (tmpval);
  512. }
  513. return hash & 0x3F;
  514. }
  515. /**
  516. * emac_hash_add - Hash function to add mac addr from hash table
  517. * @priv: The DaVinci EMAC private adapter structure
  518. * @mac_addr: mac address to delete from hash table
  519. *
  520. * Adds mac address to the internal hash table
  521. *
  522. */
  523. static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
  524. {
  525. struct device *emac_dev = &priv->ndev->dev;
  526. u32 rc = 0;
  527. u32 hash_bit;
  528. u32 hash_value = hash_get(mac_addr);
  529. if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
  530. if (netif_msg_drv(priv)) {
  531. dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
  532. "Hash %08x, should not be greater than %08x",
  533. hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
  534. }
  535. return -1;
  536. }
  537. /* set the hash bit only if not previously set */
  538. if (priv->multicast_hash_cnt[hash_value] == 0) {
  539. rc = 1; /* hash value changed */
  540. if (hash_value < 32) {
  541. hash_bit = BIT(hash_value);
  542. priv->mac_hash1 |= hash_bit;
  543. } else {
  544. hash_bit = BIT((hash_value - 32));
  545. priv->mac_hash2 |= hash_bit;
  546. }
  547. }
  548. /* incr counter for num of mcast addr's mapped to "this" hash bit */
  549. ++priv->multicast_hash_cnt[hash_value];
  550. return rc;
  551. }
  552. /**
  553. * emac_hash_del - Hash function to delete mac addr from hash table
  554. * @priv: The DaVinci EMAC private adapter structure
  555. * @mac_addr: mac address to delete from hash table
  556. *
  557. * Removes mac address from the internal hash table
  558. *
  559. */
  560. static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
  561. {
  562. u32 hash_value;
  563. u32 hash_bit;
  564. hash_value = hash_get(mac_addr);
  565. if (priv->multicast_hash_cnt[hash_value] > 0) {
  566. /* dec cntr for num of mcast addr's mapped to this hash bit */
  567. --priv->multicast_hash_cnt[hash_value];
  568. }
  569. /* if counter still > 0, at least one multicast address refers
  570. * to this hash bit. so return 0 */
  571. if (priv->multicast_hash_cnt[hash_value] > 0)
  572. return 0;
  573. if (hash_value < 32) {
  574. hash_bit = BIT(hash_value);
  575. priv->mac_hash1 &= ~hash_bit;
  576. } else {
  577. hash_bit = BIT((hash_value - 32));
  578. priv->mac_hash2 &= ~hash_bit;
  579. }
  580. /* return 1 to indicate change in mac_hash registers reqd */
  581. return 1;
  582. }
  583. /* EMAC multicast operation */
  584. #define EMAC_MULTICAST_ADD 0
  585. #define EMAC_MULTICAST_DEL 1
  586. #define EMAC_ALL_MULTI_SET 2
  587. #define EMAC_ALL_MULTI_CLR 3
  588. /**
  589. * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
  590. * @priv: The DaVinci EMAC private adapter structure
  591. * @action: multicast operation to perform
  592. * mac_addr: mac address to set
  593. *
  594. * Set multicast addresses in EMAC adapter - internal function
  595. *
  596. */
  597. static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
  598. {
  599. struct device *emac_dev = &priv->ndev->dev;
  600. int update = -1;
  601. switch (action) {
  602. case EMAC_MULTICAST_ADD:
  603. update = emac_hash_add(priv, mac_addr);
  604. break;
  605. case EMAC_MULTICAST_DEL:
  606. update = emac_hash_del(priv, mac_addr);
  607. break;
  608. case EMAC_ALL_MULTI_SET:
  609. update = 1;
  610. priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
  611. priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
  612. break;
  613. case EMAC_ALL_MULTI_CLR:
  614. update = 1;
  615. priv->mac_hash1 = 0;
  616. priv->mac_hash2 = 0;
  617. memset(&(priv->multicast_hash_cnt[0]), 0,
  618. sizeof(priv->multicast_hash_cnt[0]) *
  619. EMAC_NUM_MULTICAST_BITS);
  620. break;
  621. default:
  622. if (netif_msg_drv(priv))
  623. dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
  624. ": bad operation %d", action);
  625. break;
  626. }
  627. /* write to the hardware only if the register status chances */
  628. if (update > 0) {
  629. emac_write(EMAC_MACHASH1, priv->mac_hash1);
  630. emac_write(EMAC_MACHASH2, priv->mac_hash2);
  631. }
  632. }
  633. /**
  634. * emac_dev_mcast_set - Set multicast address in the EMAC adapter
  635. * @ndev: The DaVinci EMAC network adapter
  636. *
  637. * Set multicast addresses in EMAC adapter
  638. *
  639. */
  640. static void emac_dev_mcast_set(struct net_device *ndev)
  641. {
  642. u32 mbp_enable;
  643. struct emac_priv *priv = netdev_priv(ndev);
  644. mbp_enable = emac_read(EMAC_RXMBPENABLE);
  645. if (ndev->flags & IFF_PROMISC) {
  646. mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
  647. mbp_enable |= (EMAC_MBP_RXPROMISC);
  648. } else {
  649. mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
  650. if ((ndev->flags & IFF_ALLMULTI) ||
  651. netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
  652. mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
  653. emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
  654. } else if (!netdev_mc_empty(ndev)) {
  655. struct netdev_hw_addr *ha;
  656. mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
  657. emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
  658. /* program multicast address list into EMAC hardware */
  659. netdev_for_each_mc_addr(ha, ndev) {
  660. emac_add_mcast(priv, EMAC_MULTICAST_ADD,
  661. (u8 *) ha->addr);
  662. }
  663. } else {
  664. mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
  665. emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
  666. }
  667. }
  668. /* Set mbp config register */
  669. emac_write(EMAC_RXMBPENABLE, mbp_enable);
  670. }
  671. /*************************************************************************
  672. * EMAC Hardware manipulation
  673. *************************************************************************/
  674. /**
  675. * emac_int_disable - Disable EMAC module interrupt (from adapter)
  676. * @priv: The DaVinci EMAC private adapter structure
  677. *
  678. * Disable EMAC interrupt on the adapter
  679. *
  680. */
  681. static void emac_int_disable(struct emac_priv *priv)
  682. {
  683. if (priv->version == EMAC_VERSION_2) {
  684. unsigned long flags;
  685. local_irq_save(flags);
  686. /* Program C0_Int_En to zero to turn off
  687. * interrupts to the CPU */
  688. emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
  689. emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
  690. /* NOTE: Rx Threshold and Misc interrupts are not disabled */
  691. if (priv->int_disable)
  692. priv->int_disable();
  693. /* NOTE: Rx Threshold and Misc interrupts are not enabled */
  694. /* ack rxen only then a new pulse will be generated */
  695. emac_write(EMAC_DM646X_MACEOIVECTOR,
  696. EMAC_DM646X_MAC_EOI_C0_RXEN);
  697. /* ack txen- only then a new pulse will be generated */
  698. emac_write(EMAC_DM646X_MACEOIVECTOR,
  699. EMAC_DM646X_MAC_EOI_C0_TXEN);
  700. local_irq_restore(flags);
  701. } else {
  702. /* Set DM644x control registers for interrupt control */
  703. emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
  704. }
  705. }
  706. /**
  707. * emac_int_enable - Enable EMAC module interrupt (from adapter)
  708. * @priv: The DaVinci EMAC private adapter structure
  709. *
  710. * Enable EMAC interrupt on the adapter
  711. *
  712. */
  713. static void emac_int_enable(struct emac_priv *priv)
  714. {
  715. if (priv->version == EMAC_VERSION_2) {
  716. if (priv->int_enable)
  717. priv->int_enable();
  718. emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
  719. emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
  720. /* In addition to turning on interrupt Enable, we need
  721. * ack by writing appropriate values to the EOI
  722. * register */
  723. /* NOTE: Rx Threshold and Misc interrupts are not enabled */
  724. } else {
  725. /* Set DM644x control registers for interrupt control */
  726. emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
  727. }
  728. }
  729. /**
  730. * emac_irq - EMAC interrupt handler
  731. * @irq: interrupt number
  732. * @dev_id: EMAC network adapter data structure ptr
  733. *
  734. * EMAC Interrupt handler - we only schedule NAPI and not process any packets
  735. * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
  736. *
  737. * Returns interrupt handled condition
  738. */
  739. static irqreturn_t emac_irq(int irq, void *dev_id)
  740. {
  741. struct net_device *ndev = (struct net_device *)dev_id;
  742. struct emac_priv *priv = netdev_priv(ndev);
  743. ++priv->isr_count;
  744. if (likely(netif_running(priv->ndev))) {
  745. emac_int_disable(priv);
  746. napi_schedule(&priv->napi);
  747. } else {
  748. /* we are closing down, so dont process anything */
  749. }
  750. return IRQ_HANDLED;
  751. }
  752. static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
  753. {
  754. struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
  755. if (WARN_ON(!skb))
  756. return NULL;
  757. skb_reserve(skb, NET_IP_ALIGN);
  758. return skb;
  759. }
  760. static void emac_rx_handler(void *token, int len, int status)
  761. {
  762. struct sk_buff *skb = token;
  763. struct net_device *ndev = skb->dev;
  764. struct emac_priv *priv = netdev_priv(ndev);
  765. struct device *emac_dev = &ndev->dev;
  766. int ret;
  767. /* free and bail if we are shutting down */
  768. if (unlikely(!netif_running(ndev))) {
  769. dev_kfree_skb_any(skb);
  770. return;
  771. }
  772. /* recycle on receive error */
  773. if (status < 0) {
  774. ndev->stats.rx_errors++;
  775. goto recycle;
  776. }
  777. /* feed received packet up the stack */
  778. skb_put(skb, len);
  779. skb->protocol = eth_type_trans(skb, ndev);
  780. netif_receive_skb(skb);
  781. ndev->stats.rx_bytes += len;
  782. ndev->stats.rx_packets++;
  783. /* alloc a new packet for receive */
  784. skb = emac_rx_alloc(priv);
  785. if (!skb) {
  786. if (netif_msg_rx_err(priv) && net_ratelimit())
  787. dev_err(emac_dev, "failed rx buffer alloc\n");
  788. return;
  789. }
  790. recycle:
  791. ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
  792. skb_tailroom(skb), 0);
  793. WARN_ON(ret == -ENOMEM);
  794. if (unlikely(ret < 0))
  795. dev_kfree_skb_any(skb);
  796. }
  797. static void emac_tx_handler(void *token, int len, int status)
  798. {
  799. struct sk_buff *skb = token;
  800. struct net_device *ndev = skb->dev;
  801. /* Check whether the queue is stopped due to stalled tx dma, if the
  802. * queue is stopped then start the queue as we have free desc for tx
  803. */
  804. if (unlikely(netif_queue_stopped(ndev)))
  805. netif_wake_queue(ndev);
  806. ndev->stats.tx_packets++;
  807. ndev->stats.tx_bytes += len;
  808. dev_kfree_skb_any(skb);
  809. }
  810. /**
  811. * emac_dev_xmit - EMAC Transmit function
  812. * @skb: SKB pointer
  813. * @ndev: The DaVinci EMAC network adapter
  814. *
  815. * Called by the system to transmit a packet - we queue the packet in
  816. * EMAC hardware transmit queue
  817. *
  818. * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
  819. */
  820. static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
  821. {
  822. struct device *emac_dev = &ndev->dev;
  823. int ret_code;
  824. struct emac_priv *priv = netdev_priv(ndev);
  825. /* If no link, return */
  826. if (unlikely(!priv->link)) {
  827. if (netif_msg_tx_err(priv) && net_ratelimit())
  828. dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
  829. goto fail_tx;
  830. }
  831. ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
  832. if (unlikely(ret_code < 0)) {
  833. if (netif_msg_tx_err(priv) && net_ratelimit())
  834. dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
  835. goto fail_tx;
  836. }
  837. skb_tx_timestamp(skb);
  838. ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
  839. 0);
  840. if (unlikely(ret_code != 0)) {
  841. if (netif_msg_tx_err(priv) && net_ratelimit())
  842. dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
  843. goto fail_tx;
  844. }
  845. /* If there is no more tx desc left free then we need to
  846. * tell the kernel to stop sending us tx frames.
  847. */
  848. if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
  849. netif_stop_queue(ndev);
  850. return NETDEV_TX_OK;
  851. fail_tx:
  852. ndev->stats.tx_dropped++;
  853. netif_stop_queue(ndev);
  854. return NETDEV_TX_BUSY;
  855. }
  856. /**
  857. * emac_dev_tx_timeout - EMAC Transmit timeout function
  858. * @ndev: The DaVinci EMAC network adapter
  859. *
  860. * Called when system detects that a skb timeout period has expired
  861. * potentially due to a fault in the adapter in not being able to send
  862. * it out on the wire. We teardown the TX channel assuming a hardware
  863. * error and re-initialize the TX channel for hardware operation
  864. *
  865. */
  866. static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
  867. {
  868. struct emac_priv *priv = netdev_priv(ndev);
  869. struct device *emac_dev = &ndev->dev;
  870. if (netif_msg_tx_err(priv))
  871. dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
  872. ndev->stats.tx_errors++;
  873. emac_int_disable(priv);
  874. cpdma_chan_stop(priv->txchan);
  875. cpdma_chan_start(priv->txchan);
  876. emac_int_enable(priv);
  877. }
  878. /**
  879. * emac_set_type0addr - Set EMAC Type0 mac address
  880. * @priv: The DaVinci EMAC private adapter structure
  881. * @ch: RX channel number
  882. * @mac_addr: MAC address to set in device
  883. *
  884. * Called internally to set Type0 mac address of the adapter (Device)
  885. *
  886. * Returns success (0) or appropriate error code (none as of now)
  887. */
  888. static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
  889. {
  890. u32 val;
  891. val = ((mac_addr[5] << 8) | (mac_addr[4]));
  892. emac_write(EMAC_MACSRCADDRLO, val);
  893. val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
  894. (mac_addr[1] << 8) | (mac_addr[0]));
  895. emac_write(EMAC_MACSRCADDRHI, val);
  896. val = emac_read(EMAC_RXUNICASTSET);
  897. val |= BIT(ch);
  898. emac_write(EMAC_RXUNICASTSET, val);
  899. val = emac_read(EMAC_RXUNICASTCLEAR);
  900. val &= ~BIT(ch);
  901. emac_write(EMAC_RXUNICASTCLEAR, val);
  902. }
  903. /**
  904. * emac_set_type1addr - Set EMAC Type1 mac address
  905. * @priv: The DaVinci EMAC private adapter structure
  906. * @ch: RX channel number
  907. * @mac_addr: MAC address to set in device
  908. *
  909. * Called internally to set Type1 mac address of the adapter (Device)
  910. *
  911. * Returns success (0) or appropriate error code (none as of now)
  912. */
  913. static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
  914. {
  915. u32 val;
  916. emac_write(EMAC_MACINDEX, ch);
  917. val = ((mac_addr[5] << 8) | mac_addr[4]);
  918. emac_write(EMAC_MACADDRLO, val);
  919. val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
  920. (mac_addr[1] << 8) | (mac_addr[0]));
  921. emac_write(EMAC_MACADDRHI, val);
  922. emac_set_type0addr(priv, ch, mac_addr);
  923. }
  924. /**
  925. * emac_set_type2addr - Set EMAC Type2 mac address
  926. * @priv: The DaVinci EMAC private adapter structure
  927. * @ch: RX channel number
  928. * @mac_addr: MAC address to set in device
  929. * @index: index into RX address entries
  930. * @match: match parameter for RX address matching logic
  931. *
  932. * Called internally to set Type2 mac address of the adapter (Device)
  933. *
  934. * Returns success (0) or appropriate error code (none as of now)
  935. */
  936. static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
  937. char *mac_addr, int index, int match)
  938. {
  939. u32 val;
  940. emac_write(EMAC_MACINDEX, index);
  941. val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
  942. (mac_addr[1] << 8) | (mac_addr[0]));
  943. emac_write(EMAC_MACADDRHI, val);
  944. val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
  945. (match << 19) | BIT(20));
  946. emac_write(EMAC_MACADDRLO, val);
  947. emac_set_type0addr(priv, ch, mac_addr);
  948. }
  949. /**
  950. * emac_setmac - Set mac address in the adapter (internal function)
  951. * @priv: The DaVinci EMAC private adapter structure
  952. * @ch: RX channel number
  953. * @mac_addr: MAC address to set in device
  954. *
  955. * Called internally to set the mac address of the adapter (Device)
  956. *
  957. * Returns success (0) or appropriate error code (none as of now)
  958. */
  959. static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
  960. {
  961. struct device *emac_dev = &priv->ndev->dev;
  962. if (priv->rx_addr_type == 0) {
  963. emac_set_type0addr(priv, ch, mac_addr);
  964. } else if (priv->rx_addr_type == 1) {
  965. u32 cnt;
  966. for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
  967. emac_set_type1addr(priv, ch, mac_addr);
  968. } else if (priv->rx_addr_type == 2) {
  969. emac_set_type2addr(priv, ch, mac_addr, ch, 1);
  970. emac_set_type0addr(priv, ch, mac_addr);
  971. } else {
  972. if (netif_msg_drv(priv))
  973. dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
  974. }
  975. }
  976. /**
  977. * emac_dev_setmac_addr - Set mac address in the adapter
  978. * @ndev: The DaVinci EMAC network adapter
  979. * @addr: MAC address to set in device
  980. *
  981. * Called by the system to set the mac address of the adapter (Device)
  982. *
  983. * Returns success (0) or appropriate error code (none as of now)
  984. */
  985. static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
  986. {
  987. struct emac_priv *priv = netdev_priv(ndev);
  988. struct device *emac_dev = &priv->ndev->dev;
  989. struct sockaddr *sa = addr;
  990. if (!is_valid_ether_addr(sa->sa_data))
  991. return -EADDRNOTAVAIL;
  992. /* Store mac addr in priv and rx channel and set it in EMAC hw */
  993. memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
  994. memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
  995. /* MAC address is configured only after the interface is enabled. */
  996. if (netif_running(ndev)) {
  997. emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
  998. }
  999. if (netif_msg_drv(priv))
  1000. dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
  1001. priv->mac_addr);
  1002. return 0;
  1003. }
  1004. /**
  1005. * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
  1006. * @priv: The DaVinci EMAC private adapter structure
  1007. *
  1008. * Enables EMAC hardware for packet processing - enables PHY, enables RX
  1009. * for packet reception and enables device interrupts and then NAPI
  1010. *
  1011. * Returns success (0) or appropriate error code (none right now)
  1012. */
  1013. static int emac_hw_enable(struct emac_priv *priv)
  1014. {
  1015. u32 val, mbp_enable, mac_control;
  1016. /* Soft reset */
  1017. emac_write(EMAC_SOFTRESET, 1);
  1018. while (emac_read(EMAC_SOFTRESET))
  1019. cpu_relax();
  1020. /* Disable interrupt & Set pacing for more interrupts initially */
  1021. emac_int_disable(priv);
  1022. /* Full duplex enable bit set when auto negotiation happens */
  1023. mac_control =
  1024. (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
  1025. ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
  1026. ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
  1027. ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
  1028. emac_write(EMAC_MACCONTROL, mac_control);
  1029. mbp_enable =
  1030. (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
  1031. ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
  1032. ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
  1033. ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
  1034. ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
  1035. ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
  1036. ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
  1037. ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
  1038. EMAC_RXMBP_PROMCH_SHIFT) |
  1039. ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
  1040. ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
  1041. EMAC_RXMBP_BROADCH_SHIFT) |
  1042. ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
  1043. ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
  1044. EMAC_RXMBP_MULTICH_SHIFT));
  1045. emac_write(EMAC_RXMBPENABLE, mbp_enable);
  1046. emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
  1047. EMAC_RX_MAX_LEN_MASK));
  1048. emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
  1049. EMAC_RX_BUFFER_OFFSET_MASK));
  1050. emac_write(EMAC_RXFILTERLOWTHRESH, 0);
  1051. emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
  1052. priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
  1053. emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
  1054. emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
  1055. /* Enable MII */
  1056. val = emac_read(EMAC_MACCONTROL);
  1057. val |= (EMAC_MACCONTROL_GMIIEN);
  1058. emac_write(EMAC_MACCONTROL, val);
  1059. /* Enable NAPI and interrupts */
  1060. napi_enable(&priv->napi);
  1061. emac_int_enable(priv);
  1062. return 0;
  1063. }
  1064. /**
  1065. * emac_poll - EMAC NAPI Poll function
  1066. * @ndev: The DaVinci EMAC network adapter
  1067. * @budget: Number of receive packets to process (as told by NAPI layer)
  1068. *
  1069. * NAPI Poll function implemented to process packets as per budget. We check
  1070. * the type of interrupt on the device and accordingly call the TX or RX
  1071. * packet processing functions. We follow the budget for RX processing and
  1072. * also put a cap on number of TX pkts processed through config param. The
  1073. * NAPI schedule function is called if more packets pending.
  1074. *
  1075. * Returns number of packets received (in most cases; else TX pkts - rarely)
  1076. */
  1077. static int emac_poll(struct napi_struct *napi, int budget)
  1078. {
  1079. unsigned int mask;
  1080. struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
  1081. struct net_device *ndev = priv->ndev;
  1082. struct device *emac_dev = &ndev->dev;
  1083. u32 status = 0;
  1084. u32 num_tx_pkts = 0, num_rx_pkts = 0;
  1085. /* Check interrupt vectors and call packet processing */
  1086. status = emac_read(EMAC_MACINVECTOR);
  1087. mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
  1088. if (priv->version == EMAC_VERSION_2)
  1089. mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
  1090. if (status & mask) {
  1091. num_tx_pkts = cpdma_chan_process(priv->txchan,
  1092. EMAC_DEF_TX_MAX_SERVICE);
  1093. } /* TX processing */
  1094. mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
  1095. if (priv->version == EMAC_VERSION_2)
  1096. mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
  1097. if (status & mask) {
  1098. num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
  1099. } /* RX processing */
  1100. mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
  1101. if (priv->version == EMAC_VERSION_2)
  1102. mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
  1103. if (unlikely(status & mask)) {
  1104. u32 ch, cause;
  1105. dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
  1106. netif_stop_queue(ndev);
  1107. napi_disable(&priv->napi);
  1108. status = emac_read(EMAC_MACSTATUS);
  1109. cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
  1110. EMAC_MACSTATUS_TXERRCODE_SHIFT);
  1111. if (cause) {
  1112. ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
  1113. EMAC_MACSTATUS_TXERRCH_SHIFT);
  1114. if (net_ratelimit()) {
  1115. dev_err(emac_dev, "TX Host error %s on ch=%d\n",
  1116. &emac_txhost_errcodes[cause][0], ch);
  1117. }
  1118. }
  1119. cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
  1120. EMAC_MACSTATUS_RXERRCODE_SHIFT);
  1121. if (cause) {
  1122. ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
  1123. EMAC_MACSTATUS_RXERRCH_SHIFT);
  1124. if (netif_msg_hw(priv) && net_ratelimit())
  1125. dev_err(emac_dev, "RX Host error %s on ch=%d\n",
  1126. &emac_rxhost_errcodes[cause][0], ch);
  1127. }
  1128. } else if (num_rx_pkts < budget) {
  1129. napi_complete_done(napi, num_rx_pkts);
  1130. emac_int_enable(priv);
  1131. }
  1132. return num_rx_pkts;
  1133. }
  1134. #ifdef CONFIG_NET_POLL_CONTROLLER
  1135. /**
  1136. * emac_poll_controller - EMAC Poll controller function
  1137. * @ndev: The DaVinci EMAC network adapter
  1138. *
  1139. * Polled functionality used by netconsole and others in non interrupt mode
  1140. *
  1141. */
  1142. static void emac_poll_controller(struct net_device *ndev)
  1143. {
  1144. struct emac_priv *priv = netdev_priv(ndev);
  1145. emac_int_disable(priv);
  1146. emac_irq(ndev->irq, ndev);
  1147. emac_int_enable(priv);
  1148. }
  1149. #endif
  1150. static void emac_adjust_link(struct net_device *ndev)
  1151. {
  1152. struct emac_priv *priv = netdev_priv(ndev);
  1153. struct phy_device *phydev = ndev->phydev;
  1154. unsigned long flags;
  1155. int new_state = 0;
  1156. spin_lock_irqsave(&priv->lock, flags);
  1157. if (phydev->link) {
  1158. /* check the mode of operation - full/half duplex */
  1159. if (phydev->duplex != priv->duplex) {
  1160. new_state = 1;
  1161. priv->duplex = phydev->duplex;
  1162. }
  1163. if (phydev->speed != priv->speed) {
  1164. new_state = 1;
  1165. priv->speed = phydev->speed;
  1166. }
  1167. if (!priv->link) {
  1168. new_state = 1;
  1169. priv->link = 1;
  1170. }
  1171. } else if (priv->link) {
  1172. new_state = 1;
  1173. priv->link = 0;
  1174. priv->speed = 0;
  1175. priv->duplex = ~0;
  1176. }
  1177. if (new_state) {
  1178. emac_update_phystatus(priv);
  1179. phy_print_status(ndev->phydev);
  1180. }
  1181. spin_unlock_irqrestore(&priv->lock, flags);
  1182. }
  1183. /*************************************************************************
  1184. * Linux Driver Model
  1185. *************************************************************************/
  1186. /**
  1187. * emac_devioctl - EMAC adapter ioctl
  1188. * @ndev: The DaVinci EMAC network adapter
  1189. * @ifrq: request parameter
  1190. * @cmd: command parameter
  1191. *
  1192. * EMAC driver ioctl function
  1193. *
  1194. * Returns success(0) or appropriate error code
  1195. */
  1196. static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
  1197. {
  1198. if (!(netif_running(ndev)))
  1199. return -EINVAL;
  1200. /* TODO: Add phy read and write and private statistics get feature */
  1201. if (ndev->phydev)
  1202. return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
  1203. else
  1204. return -EOPNOTSUPP;
  1205. }
  1206. static int match_first_device(struct device *dev, const void *data)
  1207. {
  1208. if (dev->parent && dev->parent->of_node)
  1209. return of_device_is_compatible(dev->parent->of_node,
  1210. "ti,davinci_mdio");
  1211. return !strncmp(dev_name(dev), "davinci_mdio", 12);
  1212. }
  1213. /**
  1214. * emac_dev_open - EMAC device open
  1215. * @ndev: The DaVinci EMAC network adapter
  1216. *
  1217. * Called when system wants to start the interface. We init TX/RX channels
  1218. * and enable the hardware for packet reception/transmission and start the
  1219. * network queue.
  1220. *
  1221. * Returns 0 for a successful open, or appropriate error code
  1222. */
  1223. static int emac_dev_open(struct net_device *ndev)
  1224. {
  1225. struct device *emac_dev = &ndev->dev;
  1226. u32 cnt;
  1227. struct resource *res;
  1228. int q, m, ret;
  1229. int res_num = 0, irq_num = 0;
  1230. int i = 0;
  1231. struct emac_priv *priv = netdev_priv(ndev);
  1232. struct phy_device *phydev = NULL;
  1233. struct device *phy = NULL;
  1234. ret = pm_runtime_get_sync(&priv->pdev->dev);
  1235. if (ret < 0) {
  1236. pm_runtime_put_noidle(&priv->pdev->dev);
  1237. dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
  1238. __func__, ret);
  1239. return ret;
  1240. }
  1241. netif_carrier_off(ndev);
  1242. for (cnt = 0; cnt < ETH_ALEN; cnt++)
  1243. ndev->dev_addr[cnt] = priv->mac_addr[cnt];
  1244. /* Configuration items */
  1245. priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
  1246. priv->mac_hash1 = 0;
  1247. priv->mac_hash2 = 0;
  1248. emac_write(EMAC_MACHASH1, 0);
  1249. emac_write(EMAC_MACHASH2, 0);
  1250. for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
  1251. struct sk_buff *skb = emac_rx_alloc(priv);
  1252. if (!skb)
  1253. break;
  1254. ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
  1255. skb_tailroom(skb), 0);
  1256. if (WARN_ON(ret < 0))
  1257. break;
  1258. }
  1259. /* Request IRQ */
  1260. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
  1261. res_num))) {
  1262. for (irq_num = res->start; irq_num <= res->end; irq_num++) {
  1263. if (request_irq(irq_num, emac_irq, 0, ndev->name,
  1264. ndev)) {
  1265. dev_err(emac_dev,
  1266. "DaVinci EMAC: request_irq() failed\n");
  1267. ret = -EBUSY;
  1268. goto rollback;
  1269. }
  1270. }
  1271. res_num++;
  1272. }
  1273. /* prepare counters for rollback in case of an error */
  1274. res_num--;
  1275. irq_num--;
  1276. /* Start/Enable EMAC hardware */
  1277. emac_hw_enable(priv);
  1278. /* Enable Interrupt pacing if configured */
  1279. if (priv->coal_intvl != 0) {
  1280. struct ethtool_coalesce coal;
  1281. coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
  1282. emac_set_coalesce(ndev, &coal);
  1283. }
  1284. cpdma_ctlr_start(priv->dma);
  1285. if (priv->phy_node) {
  1286. phydev = of_phy_connect(ndev, priv->phy_node,
  1287. &emac_adjust_link, 0, 0);
  1288. if (!phydev) {
  1289. dev_err(emac_dev, "could not connect to phy %pOF\n",
  1290. priv->phy_node);
  1291. ret = -ENODEV;
  1292. goto err;
  1293. }
  1294. }
  1295. /* use the first phy on the bus if pdata did not give us a phy id */
  1296. if (!phydev && !priv->phy_id) {
  1297. /* NOTE: we can't use bus_find_device_by_name() here because
  1298. * the device name is not guaranteed to be 'davinci_mdio'. On
  1299. * some systems it can be 'davinci_mdio.0' so we need to use
  1300. * strncmp() against the first part of the string to correctly
  1301. * match it.
  1302. */
  1303. phy = bus_find_device(&mdio_bus_type, NULL, NULL,
  1304. match_first_device);
  1305. if (phy) {
  1306. priv->phy_id = dev_name(phy);
  1307. if (!priv->phy_id || !*priv->phy_id)
  1308. put_device(phy);
  1309. }
  1310. }
  1311. if (!phydev && priv->phy_id && *priv->phy_id) {
  1312. phydev = phy_connect(ndev, priv->phy_id,
  1313. &emac_adjust_link,
  1314. PHY_INTERFACE_MODE_MII);
  1315. put_device(phy); /* reference taken by bus_find_device */
  1316. if (IS_ERR(phydev)) {
  1317. dev_err(emac_dev, "could not connect to phy %s\n",
  1318. priv->phy_id);
  1319. ret = PTR_ERR(phydev);
  1320. goto err;
  1321. }
  1322. priv->link = 0;
  1323. priv->speed = 0;
  1324. priv->duplex = ~0;
  1325. phy_attached_info(phydev);
  1326. }
  1327. if (!phydev) {
  1328. /* No PHY , fix the link, speed and duplex settings */
  1329. dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
  1330. priv->link = 1;
  1331. priv->speed = SPEED_100;
  1332. priv->duplex = DUPLEX_FULL;
  1333. emac_update_phystatus(priv);
  1334. }
  1335. if (netif_msg_drv(priv))
  1336. dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
  1337. if (phydev)
  1338. phy_start(phydev);
  1339. return 0;
  1340. err:
  1341. emac_int_disable(priv);
  1342. napi_disable(&priv->napi);
  1343. rollback:
  1344. for (q = res_num; q >= 0; q--) {
  1345. res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
  1346. /* at the first iteration, irq_num is already set to the
  1347. * right value
  1348. */
  1349. if (q != res_num)
  1350. irq_num = res->end;
  1351. for (m = irq_num; m >= res->start; m--)
  1352. free_irq(m, ndev);
  1353. }
  1354. cpdma_ctlr_stop(priv->dma);
  1355. pm_runtime_put(&priv->pdev->dev);
  1356. return ret;
  1357. }
  1358. /**
  1359. * emac_dev_stop - EMAC device stop
  1360. * @ndev: The DaVinci EMAC network adapter
  1361. *
  1362. * Called when system wants to stop or down the interface. We stop the network
  1363. * queue, disable interrupts and cleanup TX/RX channels.
  1364. *
  1365. * We return the statistics in net_device_stats structure pulled from emac
  1366. */
  1367. static int emac_dev_stop(struct net_device *ndev)
  1368. {
  1369. struct resource *res;
  1370. int i = 0;
  1371. int irq_num;
  1372. struct emac_priv *priv = netdev_priv(ndev);
  1373. struct device *emac_dev = &ndev->dev;
  1374. /* inform the upper layers. */
  1375. netif_stop_queue(ndev);
  1376. napi_disable(&priv->napi);
  1377. netif_carrier_off(ndev);
  1378. emac_int_disable(priv);
  1379. cpdma_ctlr_stop(priv->dma);
  1380. emac_write(EMAC_SOFTRESET, 1);
  1381. if (ndev->phydev)
  1382. phy_disconnect(ndev->phydev);
  1383. /* Free IRQ */
  1384. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
  1385. for (irq_num = res->start; irq_num <= res->end; irq_num++)
  1386. free_irq(irq_num, priv->ndev);
  1387. i++;
  1388. }
  1389. if (netif_msg_drv(priv))
  1390. dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
  1391. pm_runtime_put(&priv->pdev->dev);
  1392. return 0;
  1393. }
  1394. /**
  1395. * emac_dev_getnetstats - EMAC get statistics function
  1396. * @ndev: The DaVinci EMAC network adapter
  1397. *
  1398. * Called when system wants to get statistics from the device.
  1399. *
  1400. * We return the statistics in net_device_stats structure pulled from emac
  1401. */
  1402. static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
  1403. {
  1404. struct emac_priv *priv = netdev_priv(ndev);
  1405. u32 mac_control;
  1406. u32 stats_clear_mask;
  1407. int err;
  1408. err = pm_runtime_get_sync(&priv->pdev->dev);
  1409. if (err < 0) {
  1410. pm_runtime_put_noidle(&priv->pdev->dev);
  1411. dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
  1412. __func__, err);
  1413. return &ndev->stats;
  1414. }
  1415. /* update emac hardware stats and reset the registers*/
  1416. mac_control = emac_read(EMAC_MACCONTROL);
  1417. if (mac_control & EMAC_MACCONTROL_GMIIEN)
  1418. stats_clear_mask = EMAC_STATS_CLR_MASK;
  1419. else
  1420. stats_clear_mask = 0;
  1421. ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
  1422. emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
  1423. ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
  1424. emac_read(EMAC_TXSINGLECOLL) +
  1425. emac_read(EMAC_TXMULTICOLL));
  1426. emac_write(EMAC_TXCOLLISION, stats_clear_mask);
  1427. emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
  1428. emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
  1429. ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
  1430. emac_read(EMAC_RXJABBER) +
  1431. emac_read(EMAC_RXUNDERSIZED));
  1432. emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
  1433. emac_write(EMAC_RXJABBER, stats_clear_mask);
  1434. emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
  1435. ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
  1436. emac_read(EMAC_RXMOFOVERRUNS));
  1437. emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
  1438. emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
  1439. ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
  1440. emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
  1441. ndev->stats.tx_carrier_errors +=
  1442. emac_read(EMAC_TXCARRIERSENSE);
  1443. emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
  1444. ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
  1445. emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
  1446. pm_runtime_put(&priv->pdev->dev);
  1447. return &ndev->stats;
  1448. }
  1449. static const struct net_device_ops emac_netdev_ops = {
  1450. .ndo_open = emac_dev_open,
  1451. .ndo_stop = emac_dev_stop,
  1452. .ndo_start_xmit = emac_dev_xmit,
  1453. .ndo_set_rx_mode = emac_dev_mcast_set,
  1454. .ndo_set_mac_address = emac_dev_setmac_addr,
  1455. .ndo_do_ioctl = emac_devioctl,
  1456. .ndo_tx_timeout = emac_dev_tx_timeout,
  1457. .ndo_get_stats = emac_dev_getnetstats,
  1458. #ifdef CONFIG_NET_POLL_CONTROLLER
  1459. .ndo_poll_controller = emac_poll_controller,
  1460. #endif
  1461. };
  1462. static const struct of_device_id davinci_emac_of_match[];
  1463. static struct emac_platform_data *
  1464. davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
  1465. {
  1466. struct device_node *np;
  1467. const struct of_device_id *match;
  1468. const struct emac_platform_data *auxdata;
  1469. struct emac_platform_data *pdata = NULL;
  1470. const u8 *mac_addr;
  1471. if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
  1472. return dev_get_platdata(&pdev->dev);
  1473. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  1474. if (!pdata)
  1475. return NULL;
  1476. np = pdev->dev.of_node;
  1477. pdata->version = EMAC_VERSION_2;
  1478. if (!is_valid_ether_addr(pdata->mac_addr)) {
  1479. mac_addr = of_get_mac_address(np);
  1480. if (!IS_ERR(mac_addr))
  1481. ether_addr_copy(pdata->mac_addr, mac_addr);
  1482. }
  1483. of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
  1484. &pdata->ctrl_reg_offset);
  1485. of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
  1486. &pdata->ctrl_mod_reg_offset);
  1487. of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
  1488. &pdata->ctrl_ram_offset);
  1489. of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
  1490. &pdata->ctrl_ram_size);
  1491. of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
  1492. pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
  1493. priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
  1494. if (!priv->phy_node) {
  1495. if (!of_phy_is_fixed_link(np))
  1496. pdata->phy_id = NULL;
  1497. else if (of_phy_register_fixed_link(np) >= 0)
  1498. priv->phy_node = of_node_get(np);
  1499. }
  1500. auxdata = pdev->dev.platform_data;
  1501. if (auxdata) {
  1502. pdata->interrupt_enable = auxdata->interrupt_enable;
  1503. pdata->interrupt_disable = auxdata->interrupt_disable;
  1504. }
  1505. match = of_match_device(davinci_emac_of_match, &pdev->dev);
  1506. if (match && match->data) {
  1507. auxdata = match->data;
  1508. pdata->version = auxdata->version;
  1509. pdata->hw_ram_addr = auxdata->hw_ram_addr;
  1510. }
  1511. return pdata;
  1512. }
  1513. static int davinci_emac_try_get_mac(struct platform_device *pdev,
  1514. int instance, u8 *mac_addr)
  1515. {
  1516. if (!pdev->dev.of_node)
  1517. return -EINVAL;
  1518. return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
  1519. }
  1520. /**
  1521. * davinci_emac_probe - EMAC device probe
  1522. * @pdev: The DaVinci EMAC device that we are removing
  1523. *
  1524. * Called when probing for emac devicesr. We get details of instances and
  1525. * resource information from platform init and register a network device
  1526. * and allocate resources necessary for driver to perform
  1527. */
  1528. static int davinci_emac_probe(struct platform_device *pdev)
  1529. {
  1530. struct device_node *np = pdev->dev.of_node;
  1531. int rc = 0;
  1532. struct resource *res, *res_ctrl;
  1533. struct net_device *ndev;
  1534. struct emac_priv *priv;
  1535. unsigned long hw_ram_addr;
  1536. struct emac_platform_data *pdata;
  1537. struct cpdma_params dma_params;
  1538. struct clk *emac_clk;
  1539. unsigned long emac_bus_frequency;
  1540. /* obtain emac clock from kernel */
  1541. emac_clk = devm_clk_get(&pdev->dev, NULL);
  1542. if (IS_ERR(emac_clk)) {
  1543. dev_err(&pdev->dev, "failed to get EMAC clock\n");
  1544. return -EBUSY;
  1545. }
  1546. emac_bus_frequency = clk_get_rate(emac_clk);
  1547. devm_clk_put(&pdev->dev, emac_clk);
  1548. /* TODO: Probe PHY here if possible */
  1549. ndev = alloc_etherdev(sizeof(struct emac_priv));
  1550. if (!ndev)
  1551. return -ENOMEM;
  1552. platform_set_drvdata(pdev, ndev);
  1553. priv = netdev_priv(ndev);
  1554. priv->pdev = pdev;
  1555. priv->ndev = ndev;
  1556. priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
  1557. spin_lock_init(&priv->lock);
  1558. pdata = davinci_emac_of_get_pdata(pdev, priv);
  1559. if (!pdata) {
  1560. dev_err(&pdev->dev, "no platform data\n");
  1561. rc = -ENODEV;
  1562. goto err_free_netdev;
  1563. }
  1564. /* MAC addr and PHY mask , RMII enable info from platform_data */
  1565. memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
  1566. priv->phy_id = pdata->phy_id;
  1567. priv->rmii_en = pdata->rmii_en;
  1568. priv->version = pdata->version;
  1569. priv->int_enable = pdata->interrupt_enable;
  1570. priv->int_disable = pdata->interrupt_disable;
  1571. priv->coal_intvl = 0;
  1572. priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
  1573. /* Get EMAC platform data */
  1574. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1575. priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
  1576. priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
  1577. if (IS_ERR(priv->remap_addr)) {
  1578. rc = PTR_ERR(priv->remap_addr);
  1579. goto no_pdata;
  1580. }
  1581. res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1582. if (res_ctrl) {
  1583. priv->ctrl_base =
  1584. devm_ioremap_resource(&pdev->dev, res_ctrl);
  1585. if (IS_ERR(priv->ctrl_base)) {
  1586. rc = PTR_ERR(priv->ctrl_base);
  1587. goto no_pdata;
  1588. }
  1589. } else {
  1590. priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
  1591. }
  1592. priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
  1593. ndev->base_addr = (unsigned long)priv->remap_addr;
  1594. hw_ram_addr = pdata->hw_ram_addr;
  1595. if (!hw_ram_addr)
  1596. hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
  1597. memset(&dma_params, 0, sizeof(dma_params));
  1598. dma_params.dev = &pdev->dev;
  1599. dma_params.dmaregs = priv->emac_base;
  1600. dma_params.rxthresh = priv->emac_base + 0x120;
  1601. dma_params.rxfree = priv->emac_base + 0x140;
  1602. dma_params.txhdp = priv->emac_base + 0x600;
  1603. dma_params.rxhdp = priv->emac_base + 0x620;
  1604. dma_params.txcp = priv->emac_base + 0x640;
  1605. dma_params.rxcp = priv->emac_base + 0x660;
  1606. dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
  1607. dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
  1608. dma_params.desc_hw_addr = hw_ram_addr;
  1609. dma_params.desc_mem_size = pdata->ctrl_ram_size;
  1610. dma_params.desc_align = 16;
  1611. dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
  1612. (u32 __force)res->start + pdata->ctrl_ram_offset;
  1613. priv->dma = cpdma_ctlr_create(&dma_params);
  1614. if (!priv->dma) {
  1615. dev_err(&pdev->dev, "error initializing DMA\n");
  1616. rc = -ENOMEM;
  1617. goto no_pdata;
  1618. }
  1619. priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
  1620. emac_tx_handler, 0);
  1621. if (IS_ERR(priv->txchan)) {
  1622. dev_err(&pdev->dev, "error initializing tx dma channel\n");
  1623. rc = PTR_ERR(priv->txchan);
  1624. goto err_free_dma;
  1625. }
  1626. priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
  1627. emac_rx_handler, 1);
  1628. if (IS_ERR(priv->rxchan)) {
  1629. dev_err(&pdev->dev, "error initializing rx dma channel\n");
  1630. rc = PTR_ERR(priv->rxchan);
  1631. goto err_free_txchan;
  1632. }
  1633. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1634. if (!res) {
  1635. dev_err(&pdev->dev, "error getting irq res\n");
  1636. rc = -ENOENT;
  1637. goto err_free_rxchan;
  1638. }
  1639. ndev->irq = res->start;
  1640. rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
  1641. if (!rc)
  1642. ether_addr_copy(ndev->dev_addr, priv->mac_addr);
  1643. if (!is_valid_ether_addr(priv->mac_addr)) {
  1644. /* Use random MAC if still none obtained. */
  1645. eth_hw_addr_random(ndev);
  1646. memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
  1647. dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
  1648. priv->mac_addr);
  1649. }
  1650. ndev->netdev_ops = &emac_netdev_ops;
  1651. ndev->ethtool_ops = &ethtool_ops;
  1652. netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
  1653. pm_runtime_enable(&pdev->dev);
  1654. rc = pm_runtime_get_sync(&pdev->dev);
  1655. if (rc < 0) {
  1656. pm_runtime_put_noidle(&pdev->dev);
  1657. dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
  1658. __func__, rc);
  1659. goto err_napi_del;
  1660. }
  1661. /* register the network device */
  1662. SET_NETDEV_DEV(ndev, &pdev->dev);
  1663. rc = register_netdev(ndev);
  1664. if (rc) {
  1665. dev_err(&pdev->dev, "error in register_netdev\n");
  1666. rc = -ENODEV;
  1667. pm_runtime_put(&pdev->dev);
  1668. goto err_napi_del;
  1669. }
  1670. if (netif_msg_probe(priv)) {
  1671. dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
  1672. "(regs: %pa, irq: %d)\n",
  1673. &priv->emac_base_phys, ndev->irq);
  1674. }
  1675. pm_runtime_put(&pdev->dev);
  1676. return 0;
  1677. err_napi_del:
  1678. netif_napi_del(&priv->napi);
  1679. err_free_rxchan:
  1680. cpdma_chan_destroy(priv->rxchan);
  1681. err_free_txchan:
  1682. cpdma_chan_destroy(priv->txchan);
  1683. err_free_dma:
  1684. cpdma_ctlr_destroy(priv->dma);
  1685. no_pdata:
  1686. if (of_phy_is_fixed_link(np))
  1687. of_phy_deregister_fixed_link(np);
  1688. of_node_put(priv->phy_node);
  1689. err_free_netdev:
  1690. free_netdev(ndev);
  1691. return rc;
  1692. }
  1693. /**
  1694. * davinci_emac_remove - EMAC device remove
  1695. * @pdev: The DaVinci EMAC device that we are removing
  1696. *
  1697. * Called when removing the device driver. We disable clock usage and release
  1698. * the resources taken up by the driver and unregister network device
  1699. */
  1700. static int davinci_emac_remove(struct platform_device *pdev)
  1701. {
  1702. struct net_device *ndev = platform_get_drvdata(pdev);
  1703. struct emac_priv *priv = netdev_priv(ndev);
  1704. struct device_node *np = pdev->dev.of_node;
  1705. dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
  1706. if (priv->txchan)
  1707. cpdma_chan_destroy(priv->txchan);
  1708. if (priv->rxchan)
  1709. cpdma_chan_destroy(priv->rxchan);
  1710. cpdma_ctlr_destroy(priv->dma);
  1711. unregister_netdev(ndev);
  1712. of_node_put(priv->phy_node);
  1713. pm_runtime_disable(&pdev->dev);
  1714. if (of_phy_is_fixed_link(np))
  1715. of_phy_deregister_fixed_link(np);
  1716. free_netdev(ndev);
  1717. return 0;
  1718. }
  1719. static int davinci_emac_suspend(struct device *dev)
  1720. {
  1721. struct net_device *ndev = dev_get_drvdata(dev);
  1722. if (netif_running(ndev))
  1723. emac_dev_stop(ndev);
  1724. return 0;
  1725. }
  1726. static int davinci_emac_resume(struct device *dev)
  1727. {
  1728. struct net_device *ndev = dev_get_drvdata(dev);
  1729. if (netif_running(ndev))
  1730. emac_dev_open(ndev);
  1731. return 0;
  1732. }
  1733. static const struct dev_pm_ops davinci_emac_pm_ops = {
  1734. .suspend = davinci_emac_suspend,
  1735. .resume = davinci_emac_resume,
  1736. };
  1737. static const struct emac_platform_data am3517_emac_data = {
  1738. .version = EMAC_VERSION_2,
  1739. .hw_ram_addr = 0x01e20000,
  1740. };
  1741. static const struct emac_platform_data dm816_emac_data = {
  1742. .version = EMAC_VERSION_2,
  1743. };
  1744. static const struct of_device_id davinci_emac_of_match[] = {
  1745. {.compatible = "ti,davinci-dm6467-emac", },
  1746. {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
  1747. {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
  1748. {},
  1749. };
  1750. MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
  1751. /* davinci_emac_driver: EMAC platform driver structure */
  1752. static struct platform_driver davinci_emac_driver = {
  1753. .driver = {
  1754. .name = "davinci_emac",
  1755. .pm = &davinci_emac_pm_ops,
  1756. .of_match_table = davinci_emac_of_match,
  1757. },
  1758. .probe = davinci_emac_probe,
  1759. .remove = davinci_emac_remove,
  1760. };
  1761. /**
  1762. * davinci_emac_init - EMAC driver module init
  1763. *
  1764. * Called when initializing the driver. We register the driver with
  1765. * the platform.
  1766. */
  1767. static int __init davinci_emac_init(void)
  1768. {
  1769. return platform_driver_register(&davinci_emac_driver);
  1770. }
  1771. late_initcall(davinci_emac_init);
  1772. /**
  1773. * davinci_emac_exit - EMAC driver module exit
  1774. *
  1775. * Called when exiting the driver completely. We unregister the driver with
  1776. * the platform and exit
  1777. */
  1778. static void __exit davinci_emac_exit(void)
  1779. {
  1780. platform_driver_unregister(&davinci_emac_driver);
  1781. }
  1782. module_exit(davinci_emac_exit);
  1783. MODULE_LICENSE("GPL");
  1784. MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
  1785. MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
  1786. MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");