PageRenderTime 28ms CodeModel.GetById 15ms RepoModel.GetById 0ms app.codeStats 1ms

/drivers/net/wireless/adm8211.c

http://github.com/mirrors/linux
C | 1996 lines | 1538 code | 340 blank | 118 comment | 205 complexity | 1500db511de567126f07803bba23bcf5 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /*
  2. * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
  3. *
  4. * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
  5. * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
  6. * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
  7. * and used with permission.
  8. *
  9. * Much thanks to Infineon-ADMtek for their support of this driver.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation. See README and COPYING for
  14. * more details.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/if.h>
  19. #include <linux/skbuff.h>
  20. #include <linux/slab.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/pci.h>
  23. #include <linux/delay.h>
  24. #include <linux/crc32.h>
  25. #include <linux/eeprom_93cx6.h>
  26. #include <linux/module.h>
  27. #include <net/mac80211.h>
  28. #include "adm8211.h"
  29. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  30. MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  31. MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  32. MODULE_SUPPORTED_DEVICE("ADM8211");
  33. MODULE_LICENSE("GPL");
  34. static unsigned int tx_ring_size __read_mostly = 16;
  35. static unsigned int rx_ring_size __read_mostly = 16;
  36. module_param(tx_ring_size, uint, 0);
  37. module_param(rx_ring_size, uint, 0);
  38. static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
  39. /* ADMtek ADM8211 */
  40. { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  41. { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  42. { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  43. { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  44. { 0 }
  45. };
  46. static struct ieee80211_rate adm8211_rates[] = {
  47. { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  48. { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  49. { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  50. { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  51. { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  52. };
  53. static const struct ieee80211_channel adm8211_channels[] = {
  54. { .center_freq = 2412},
  55. { .center_freq = 2417},
  56. { .center_freq = 2422},
  57. { .center_freq = 2427},
  58. { .center_freq = 2432},
  59. { .center_freq = 2437},
  60. { .center_freq = 2442},
  61. { .center_freq = 2447},
  62. { .center_freq = 2452},
  63. { .center_freq = 2457},
  64. { .center_freq = 2462},
  65. { .center_freq = 2467},
  66. { .center_freq = 2472},
  67. { .center_freq = 2484},
  68. };
  69. static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  70. {
  71. struct adm8211_priv *priv = eeprom->data;
  72. u32 reg = ADM8211_CSR_READ(SPR);
  73. eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  74. eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  75. eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  76. eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  77. }
  78. static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  79. {
  80. struct adm8211_priv *priv = eeprom->data;
  81. u32 reg = 0x4000 | ADM8211_SPR_SRS;
  82. if (eeprom->reg_data_in)
  83. reg |= ADM8211_SPR_SDI;
  84. if (eeprom->reg_data_out)
  85. reg |= ADM8211_SPR_SDO;
  86. if (eeprom->reg_data_clock)
  87. reg |= ADM8211_SPR_SCLK;
  88. if (eeprom->reg_chip_select)
  89. reg |= ADM8211_SPR_SCS;
  90. ADM8211_CSR_WRITE(SPR, reg);
  91. ADM8211_CSR_READ(SPR); /* eeprom_delay */
  92. }
  93. static int adm8211_read_eeprom(struct ieee80211_hw *dev)
  94. {
  95. struct adm8211_priv *priv = dev->priv;
  96. unsigned int words, i;
  97. struct ieee80211_chan_range chan_range;
  98. u16 cr49;
  99. struct eeprom_93cx6 eeprom = {
  100. .data = priv,
  101. .register_read = adm8211_eeprom_register_read,
  102. .register_write = adm8211_eeprom_register_write
  103. };
  104. if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
  105. /* 256 * 16-bit = 512 bytes */
  106. eeprom.width = PCI_EEPROM_WIDTH_93C66;
  107. words = 256;
  108. } else {
  109. /* 64 * 16-bit = 128 bytes */
  110. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  111. words = 64;
  112. }
  113. priv->eeprom_len = words * 2;
  114. priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
  115. if (!priv->eeprom)
  116. return -ENOMEM;
  117. eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
  118. cr49 = le16_to_cpu(priv->eeprom->cr49);
  119. priv->rf_type = (cr49 >> 3) & 0x7;
  120. switch (priv->rf_type) {
  121. case ADM8211_TYPE_INTERSIL:
  122. case ADM8211_TYPE_RFMD:
  123. case ADM8211_TYPE_MARVEL:
  124. case ADM8211_TYPE_AIROHA:
  125. case ADM8211_TYPE_ADMTEK:
  126. break;
  127. default:
  128. if (priv->pdev->revision < ADM8211_REV_CA)
  129. priv->rf_type = ADM8211_TYPE_RFMD;
  130. else
  131. priv->rf_type = ADM8211_TYPE_AIROHA;
  132. printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
  133. pci_name(priv->pdev), (cr49 >> 3) & 0x7);
  134. }
  135. priv->bbp_type = cr49 & 0x7;
  136. switch (priv->bbp_type) {
  137. case ADM8211_TYPE_INTERSIL:
  138. case ADM8211_TYPE_RFMD:
  139. case ADM8211_TYPE_MARVEL:
  140. case ADM8211_TYPE_AIROHA:
  141. case ADM8211_TYPE_ADMTEK:
  142. break;
  143. default:
  144. if (priv->pdev->revision < ADM8211_REV_CA)
  145. priv->bbp_type = ADM8211_TYPE_RFMD;
  146. else
  147. priv->bbp_type = ADM8211_TYPE_ADMTEK;
  148. printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
  149. pci_name(priv->pdev), cr49 >> 3);
  150. }
  151. if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
  152. printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
  153. pci_name(priv->pdev), priv->eeprom->country_code);
  154. chan_range = cranges[2];
  155. } else
  156. chan_range = cranges[priv->eeprom->country_code];
  157. printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
  158. pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
  159. BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
  160. memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
  161. priv->band.channels = priv->channels;
  162. priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
  163. priv->band.bitrates = adm8211_rates;
  164. priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
  165. for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
  166. if (i < chan_range.min || i > chan_range.max)
  167. priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
  168. switch (priv->eeprom->specific_bbptype) {
  169. case ADM8211_BBP_RFMD3000:
  170. case ADM8211_BBP_RFMD3002:
  171. case ADM8211_BBP_ADM8011:
  172. priv->specific_bbptype = priv->eeprom->specific_bbptype;
  173. break;
  174. default:
  175. if (priv->pdev->revision < ADM8211_REV_CA)
  176. priv->specific_bbptype = ADM8211_BBP_RFMD3000;
  177. else
  178. priv->specific_bbptype = ADM8211_BBP_ADM8011;
  179. printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
  180. pci_name(priv->pdev), priv->eeprom->specific_bbptype);
  181. }
  182. switch (priv->eeprom->specific_rftype) {
  183. case ADM8211_RFMD2948:
  184. case ADM8211_RFMD2958:
  185. case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
  186. case ADM8211_MAX2820:
  187. case ADM8211_AL2210L:
  188. priv->transceiver_type = priv->eeprom->specific_rftype;
  189. break;
  190. default:
  191. if (priv->pdev->revision == ADM8211_REV_BA)
  192. priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
  193. else if (priv->pdev->revision == ADM8211_REV_CA)
  194. priv->transceiver_type = ADM8211_AL2210L;
  195. else if (priv->pdev->revision == ADM8211_REV_AB)
  196. priv->transceiver_type = ADM8211_RFMD2948;
  197. printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
  198. pci_name(priv->pdev), priv->eeprom->specific_rftype);
  199. break;
  200. }
  201. printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
  202. "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
  203. priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
  204. return 0;
  205. }
  206. static inline void adm8211_write_sram(struct ieee80211_hw *dev,
  207. u32 addr, u32 data)
  208. {
  209. struct adm8211_priv *priv = dev->priv;
  210. ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
  211. (priv->pdev->revision < ADM8211_REV_BA ?
  212. 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
  213. ADM8211_CSR_READ(WEPCTL);
  214. msleep(1);
  215. ADM8211_CSR_WRITE(WESK, data);
  216. ADM8211_CSR_READ(WESK);
  217. msleep(1);
  218. }
  219. static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
  220. unsigned int addr, u8 *buf,
  221. unsigned int len)
  222. {
  223. struct adm8211_priv *priv = dev->priv;
  224. u32 reg = ADM8211_CSR_READ(WEPCTL);
  225. unsigned int i;
  226. if (priv->pdev->revision < ADM8211_REV_BA) {
  227. for (i = 0; i < len; i += 2) {
  228. u16 val = buf[i] | (buf[i + 1] << 8);
  229. adm8211_write_sram(dev, addr + i / 2, val);
  230. }
  231. } else {
  232. for (i = 0; i < len; i += 4) {
  233. u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
  234. (buf[i + 2] << 16) | (buf[i + 3] << 24);
  235. adm8211_write_sram(dev, addr + i / 4, val);
  236. }
  237. }
  238. ADM8211_CSR_WRITE(WEPCTL, reg);
  239. }
  240. static void adm8211_clear_sram(struct ieee80211_hw *dev)
  241. {
  242. struct adm8211_priv *priv = dev->priv;
  243. u32 reg = ADM8211_CSR_READ(WEPCTL);
  244. unsigned int addr;
  245. for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
  246. adm8211_write_sram(dev, addr, 0);
  247. ADM8211_CSR_WRITE(WEPCTL, reg);
  248. }
  249. static int adm8211_get_stats(struct ieee80211_hw *dev,
  250. struct ieee80211_low_level_stats *stats)
  251. {
  252. struct adm8211_priv *priv = dev->priv;
  253. memcpy(stats, &priv->stats, sizeof(*stats));
  254. return 0;
  255. }
  256. static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
  257. {
  258. struct adm8211_priv *priv = dev->priv;
  259. unsigned int dirty_tx;
  260. spin_lock(&priv->lock);
  261. for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
  262. unsigned int entry = dirty_tx % priv->tx_ring_size;
  263. u32 status = le32_to_cpu(priv->tx_ring[entry].status);
  264. struct ieee80211_tx_info *txi;
  265. struct adm8211_tx_ring_info *info;
  266. struct sk_buff *skb;
  267. if (status & TDES0_CONTROL_OWN ||
  268. !(status & TDES0_CONTROL_DONE))
  269. break;
  270. info = &priv->tx_buffers[entry];
  271. skb = info->skb;
  272. txi = IEEE80211_SKB_CB(skb);
  273. /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
  274. pci_unmap_single(priv->pdev, info->mapping,
  275. info->skb->len, PCI_DMA_TODEVICE);
  276. ieee80211_tx_info_clear_status(txi);
  277. skb_pull(skb, sizeof(struct adm8211_tx_hdr));
  278. memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
  279. if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
  280. !(status & TDES0_STATUS_ES))
  281. txi->flags |= IEEE80211_TX_STAT_ACK;
  282. ieee80211_tx_status_irqsafe(dev, skb);
  283. info->skb = NULL;
  284. }
  285. if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
  286. ieee80211_wake_queue(dev, 0);
  287. priv->dirty_tx = dirty_tx;
  288. spin_unlock(&priv->lock);
  289. }
  290. static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
  291. {
  292. struct adm8211_priv *priv = dev->priv;
  293. unsigned int entry = priv->cur_rx % priv->rx_ring_size;
  294. u32 status;
  295. unsigned int pktlen;
  296. struct sk_buff *skb, *newskb;
  297. unsigned int limit = priv->rx_ring_size;
  298. u8 rssi, rate;
  299. while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
  300. if (!limit--)
  301. break;
  302. status = le32_to_cpu(priv->rx_ring[entry].status);
  303. rate = (status & RDES0_STATUS_RXDR) >> 12;
  304. rssi = le32_to_cpu(priv->rx_ring[entry].length) &
  305. RDES1_STATUS_RSSI;
  306. pktlen = status & RDES0_STATUS_FL;
  307. if (pktlen > RX_PKT_SIZE) {
  308. if (net_ratelimit())
  309. wiphy_debug(dev->wiphy, "frame too long (%d)\n",
  310. pktlen);
  311. pktlen = RX_PKT_SIZE;
  312. }
  313. if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
  314. skb = NULL; /* old buffer will be reused */
  315. /* TODO: update RX error stats */
  316. /* TODO: check RDES0_STATUS_CRC*E */
  317. } else if (pktlen < RX_COPY_BREAK) {
  318. skb = dev_alloc_skb(pktlen);
  319. if (skb) {
  320. pci_dma_sync_single_for_cpu(
  321. priv->pdev,
  322. priv->rx_buffers[entry].mapping,
  323. pktlen, PCI_DMA_FROMDEVICE);
  324. memcpy(skb_put(skb, pktlen),
  325. skb_tail_pointer(priv->rx_buffers[entry].skb),
  326. pktlen);
  327. pci_dma_sync_single_for_device(
  328. priv->pdev,
  329. priv->rx_buffers[entry].mapping,
  330. RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
  331. }
  332. } else {
  333. newskb = dev_alloc_skb(RX_PKT_SIZE);
  334. if (newskb) {
  335. skb = priv->rx_buffers[entry].skb;
  336. skb_put(skb, pktlen);
  337. pci_unmap_single(
  338. priv->pdev,
  339. priv->rx_buffers[entry].mapping,
  340. RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
  341. priv->rx_buffers[entry].skb = newskb;
  342. priv->rx_buffers[entry].mapping =
  343. pci_map_single(priv->pdev,
  344. skb_tail_pointer(newskb),
  345. RX_PKT_SIZE,
  346. PCI_DMA_FROMDEVICE);
  347. } else {
  348. skb = NULL;
  349. /* TODO: update rx dropped stats */
  350. }
  351. priv->rx_ring[entry].buffer1 =
  352. cpu_to_le32(priv->rx_buffers[entry].mapping);
  353. }
  354. priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
  355. RDES0_STATUS_SQL);
  356. priv->rx_ring[entry].length =
  357. cpu_to_le32(RX_PKT_SIZE |
  358. (entry == priv->rx_ring_size - 1 ?
  359. RDES1_CONTROL_RER : 0));
  360. if (skb) {
  361. struct ieee80211_rx_status rx_status = {0};
  362. if (priv->pdev->revision < ADM8211_REV_CA)
  363. rx_status.signal = rssi;
  364. else
  365. rx_status.signal = 100 - rssi;
  366. rx_status.rate_idx = rate;
  367. rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
  368. rx_status.band = IEEE80211_BAND_2GHZ;
  369. memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
  370. ieee80211_rx_irqsafe(dev, skb);
  371. }
  372. entry = (++priv->cur_rx) % priv->rx_ring_size;
  373. }
  374. /* TODO: check LPC and update stats? */
  375. }
  376. static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
  377. {
  378. #define ADM8211_INT(x) \
  379. do { \
  380. if (unlikely(stsr & ADM8211_STSR_ ## x)) \
  381. wiphy_debug(dev->wiphy, "%s\n", #x); \
  382. } while (0)
  383. struct ieee80211_hw *dev = dev_id;
  384. struct adm8211_priv *priv = dev->priv;
  385. u32 stsr = ADM8211_CSR_READ(STSR);
  386. ADM8211_CSR_WRITE(STSR, stsr);
  387. if (stsr == 0xffffffff)
  388. return IRQ_HANDLED;
  389. if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
  390. return IRQ_HANDLED;
  391. if (stsr & ADM8211_STSR_RCI)
  392. adm8211_interrupt_rci(dev);
  393. if (stsr & ADM8211_STSR_TCI)
  394. adm8211_interrupt_tci(dev);
  395. ADM8211_INT(PCF);
  396. ADM8211_INT(BCNTC);
  397. ADM8211_INT(GPINT);
  398. ADM8211_INT(ATIMTC);
  399. ADM8211_INT(TSFTF);
  400. ADM8211_INT(TSCZ);
  401. ADM8211_INT(SQL);
  402. ADM8211_INT(WEPTD);
  403. ADM8211_INT(ATIME);
  404. ADM8211_INT(TEIS);
  405. ADM8211_INT(FBE);
  406. ADM8211_INT(REIS);
  407. ADM8211_INT(GPTT);
  408. ADM8211_INT(RPS);
  409. ADM8211_INT(RDU);
  410. ADM8211_INT(TUF);
  411. ADM8211_INT(TPS);
  412. return IRQ_HANDLED;
  413. #undef ADM8211_INT
  414. }
  415. #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
  416. static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
  417. u16 addr, u32 value) { \
  418. struct adm8211_priv *priv = dev->priv; \
  419. unsigned int i; \
  420. u32 reg, bitbuf; \
  421. \
  422. value &= v_mask; \
  423. addr &= a_mask; \
  424. bitbuf = (value << v_shift) | (addr << a_shift); \
  425. \
  426. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
  427. ADM8211_CSR_READ(SYNRF); \
  428. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
  429. ADM8211_CSR_READ(SYNRF); \
  430. \
  431. if (prewrite) { \
  432. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
  433. ADM8211_CSR_READ(SYNRF); \
  434. } \
  435. \
  436. for (i = 0; i <= bits; i++) { \
  437. if (bitbuf & (1 << (bits - i))) \
  438. reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
  439. else \
  440. reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
  441. \
  442. ADM8211_CSR_WRITE(SYNRF, reg); \
  443. ADM8211_CSR_READ(SYNRF); \
  444. \
  445. ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
  446. ADM8211_CSR_READ(SYNRF); \
  447. ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
  448. ADM8211_CSR_READ(SYNRF); \
  449. } \
  450. \
  451. if (postwrite == 1) { \
  452. ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
  453. ADM8211_CSR_READ(SYNRF); \
  454. } \
  455. if (postwrite == 2) { \
  456. ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
  457. ADM8211_CSR_READ(SYNRF); \
  458. } \
  459. \
  460. ADM8211_CSR_WRITE(SYNRF, 0); \
  461. ADM8211_CSR_READ(SYNRF); \
  462. }
  463. WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
  464. WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
  465. WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
  466. WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
  467. #undef WRITE_SYN
  468. static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
  469. {
  470. struct adm8211_priv *priv = dev->priv;
  471. unsigned int timeout;
  472. u32 reg;
  473. timeout = 10;
  474. while (timeout > 0) {
  475. reg = ADM8211_CSR_READ(BBPCTL);
  476. if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
  477. break;
  478. timeout--;
  479. msleep(2);
  480. }
  481. if (timeout == 0) {
  482. wiphy_debug(dev->wiphy,
  483. "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
  484. addr, data, reg);
  485. return -ETIMEDOUT;
  486. }
  487. switch (priv->bbp_type) {
  488. case ADM8211_TYPE_INTERSIL:
  489. reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
  490. break;
  491. case ADM8211_TYPE_RFMD:
  492. reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
  493. (0x01 << 18);
  494. break;
  495. case ADM8211_TYPE_ADMTEK:
  496. reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
  497. (0x05 << 18);
  498. break;
  499. }
  500. reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
  501. ADM8211_CSR_WRITE(BBPCTL, reg);
  502. timeout = 10;
  503. while (timeout > 0) {
  504. reg = ADM8211_CSR_READ(BBPCTL);
  505. if (!(reg & ADM8211_BBPCTL_WR))
  506. break;
  507. timeout--;
  508. msleep(2);
  509. }
  510. if (timeout == 0) {
  511. ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
  512. ~ADM8211_BBPCTL_WR);
  513. wiphy_debug(dev->wiphy,
  514. "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
  515. addr, data, reg);
  516. return -ETIMEDOUT;
  517. }
  518. return 0;
  519. }
  520. static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
  521. {
  522. static const u32 adm8211_rfmd2958_reg5[] =
  523. {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
  524. 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
  525. static const u32 adm8211_rfmd2958_reg6[] =
  526. {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
  527. 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
  528. struct adm8211_priv *priv = dev->priv;
  529. u8 ant_power = priv->ant_power > 0x3F ?
  530. priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
  531. u8 tx_power = priv->tx_power > 0x3F ?
  532. priv->eeprom->tx_power[chan - 1] : priv->tx_power;
  533. u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
  534. priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
  535. u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
  536. priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
  537. u32 reg;
  538. ADM8211_IDLE();
  539. /* Program synthesizer to new channel */
  540. switch (priv->transceiver_type) {
  541. case ADM8211_RFMD2958:
  542. case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
  543. adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
  544. adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
  545. adm8211_rf_write_syn_rfmd2958(dev, 0x05,
  546. adm8211_rfmd2958_reg5[chan - 1]);
  547. adm8211_rf_write_syn_rfmd2958(dev, 0x06,
  548. adm8211_rfmd2958_reg6[chan - 1]);
  549. break;
  550. case ADM8211_RFMD2948:
  551. adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
  552. SI4126_MAIN_XINDIV2);
  553. adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
  554. SI4126_POWERDOWN_PDIB |
  555. SI4126_POWERDOWN_PDRB);
  556. adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
  557. adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
  558. (chan == 14 ?
  559. 2110 : (2033 + (chan * 5))));
  560. adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
  561. adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
  562. adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
  563. break;
  564. case ADM8211_MAX2820:
  565. adm8211_rf_write_syn_max2820(dev, 0x3,
  566. (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
  567. break;
  568. case ADM8211_AL2210L:
  569. adm8211_rf_write_syn_al2210l(dev, 0x0,
  570. (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
  571. break;
  572. default:
  573. wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
  574. priv->transceiver_type);
  575. break;
  576. }
  577. /* write BBP regs */
  578. if (priv->bbp_type == ADM8211_TYPE_RFMD) {
  579. /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
  580. /* TODO: remove if SMC 2635W doesn't need this */
  581. if (priv->transceiver_type == ADM8211_RFMD2948) {
  582. reg = ADM8211_CSR_READ(GPIO);
  583. reg &= 0xfffc0000;
  584. reg |= ADM8211_CSR_GPIO_EN0;
  585. if (chan != 14)
  586. reg |= ADM8211_CSR_GPIO_O0;
  587. ADM8211_CSR_WRITE(GPIO, reg);
  588. }
  589. if (priv->transceiver_type == ADM8211_RFMD2958) {
  590. /* set PCNT2 */
  591. adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
  592. /* set PCNT1 P_DESIRED/MID_BIAS */
  593. reg = le16_to_cpu(priv->eeprom->cr49);
  594. reg >>= 13;
  595. reg <<= 15;
  596. reg |= ant_power << 9;
  597. adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
  598. /* set TXRX TX_GAIN */
  599. adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
  600. (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
  601. } else {
  602. reg = ADM8211_CSR_READ(PLCPHD);
  603. reg &= 0xff00ffff;
  604. reg |= tx_power << 18;
  605. ADM8211_CSR_WRITE(PLCPHD, reg);
  606. }
  607. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
  608. ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
  609. ADM8211_CSR_READ(SYNRF);
  610. msleep(30);
  611. /* RF3000 BBP */
  612. if (priv->transceiver_type != ADM8211_RFMD2958)
  613. adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
  614. tx_power<<2);
  615. adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
  616. adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
  617. adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
  618. priv->eeprom->cr28 : 0);
  619. adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
  620. ADM8211_CSR_WRITE(SYNRF, 0);
  621. /* Nothing to do for ADMtek BBP */
  622. } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
  623. wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
  624. priv->bbp_type);
  625. ADM8211_RESTORE();
  626. /* update current channel for adhoc (and maybe AP mode) */
  627. reg = ADM8211_CSR_READ(CAP0);
  628. reg &= ~0xF;
  629. reg |= chan;
  630. ADM8211_CSR_WRITE(CAP0, reg);
  631. return 0;
  632. }
  633. static void adm8211_update_mode(struct ieee80211_hw *dev)
  634. {
  635. struct adm8211_priv *priv = dev->priv;
  636. ADM8211_IDLE();
  637. priv->soft_rx_crc = 0;
  638. switch (priv->mode) {
  639. case NL80211_IFTYPE_STATION:
  640. priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
  641. priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
  642. break;
  643. case NL80211_IFTYPE_ADHOC:
  644. priv->nar &= ~ADM8211_NAR_PR;
  645. priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
  646. /* don't trust the error bits on rev 0x20 and up in adhoc */
  647. if (priv->pdev->revision >= ADM8211_REV_BA)
  648. priv->soft_rx_crc = 1;
  649. break;
  650. case NL80211_IFTYPE_MONITOR:
  651. priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
  652. priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
  653. break;
  654. }
  655. ADM8211_RESTORE();
  656. }
  657. static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
  658. {
  659. struct adm8211_priv *priv = dev->priv;
  660. switch (priv->transceiver_type) {
  661. case ADM8211_RFMD2958:
  662. case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
  663. /* comments taken from ADMtek vendor driver */
  664. /* Reset RF2958 after power on */
  665. adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
  666. /* Initialize RF VCO Core Bias to maximum */
  667. adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
  668. /* Initialize IF PLL */
  669. adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
  670. /* Initialize IF PLL Coarse Tuning */
  671. adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
  672. /* Initialize RF PLL */
  673. adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
  674. /* Initialize RF PLL Coarse Tuning */
  675. adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
  676. /* Initialize TX gain and filter BW (R9) */
  677. adm8211_rf_write_syn_rfmd2958(dev, 0x09,
  678. (priv->transceiver_type == ADM8211_RFMD2958 ?
  679. 0x10050 : 0x00050));
  680. /* Initialize CAL register */
  681. adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
  682. break;
  683. case ADM8211_MAX2820:
  684. adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
  685. adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
  686. adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
  687. adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
  688. adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
  689. break;
  690. case ADM8211_AL2210L:
  691. adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
  692. adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
  693. adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
  694. adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
  695. adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
  696. adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
  697. adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
  698. adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
  699. adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
  700. adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
  701. adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
  702. adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
  703. break;
  704. case ADM8211_RFMD2948:
  705. default:
  706. break;
  707. }
  708. }
  709. static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
  710. {
  711. struct adm8211_priv *priv = dev->priv;
  712. u32 reg;
  713. /* write addresses */
  714. if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
  715. ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
  716. ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
  717. ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
  718. } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
  719. priv->bbp_type == ADM8211_TYPE_ADMTEK) {
  720. /* check specific BBP type */
  721. switch (priv->specific_bbptype) {
  722. case ADM8211_BBP_RFMD3000:
  723. case ADM8211_BBP_RFMD3002:
  724. ADM8211_CSR_WRITE(MMIWA, 0x00009101);
  725. ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
  726. break;
  727. case ADM8211_BBP_ADM8011:
  728. ADM8211_CSR_WRITE(MMIWA, 0x00008903);
  729. ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
  730. reg = ADM8211_CSR_READ(BBPCTL);
  731. reg &= ~ADM8211_BBPCTL_TYPE;
  732. reg |= 0x5 << 18;
  733. ADM8211_CSR_WRITE(BBPCTL, reg);
  734. break;
  735. }
  736. switch (priv->pdev->revision) {
  737. case ADM8211_REV_CA:
  738. if (priv->transceiver_type == ADM8211_RFMD2958 ||
  739. priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
  740. priv->transceiver_type == ADM8211_RFMD2948)
  741. ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
  742. else if (priv->transceiver_type == ADM8211_MAX2820 ||
  743. priv->transceiver_type == ADM8211_AL2210L)
  744. ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
  745. break;
  746. case ADM8211_REV_BA:
  747. reg = ADM8211_CSR_READ(MMIRD1);
  748. reg &= 0x0000FFFF;
  749. reg |= 0x7e100000;
  750. ADM8211_CSR_WRITE(MMIRD1, reg);
  751. break;
  752. case ADM8211_REV_AB:
  753. case ADM8211_REV_AF:
  754. default:
  755. ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
  756. break;
  757. }
  758. /* For RFMD */
  759. ADM8211_CSR_WRITE(MACTEST, 0x800);
  760. }
  761. adm8211_hw_init_syn(dev);
  762. /* Set RF Power control IF pin to PE1+PHYRST# */
  763. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
  764. ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
  765. ADM8211_CSR_READ(SYNRF);
  766. msleep(20);
  767. /* write BBP regs */
  768. if (priv->bbp_type == ADM8211_TYPE_RFMD) {
  769. /* RF3000 BBP */
  770. /* another set:
  771. * 11: c8
  772. * 14: 14
  773. * 15: 50 (chan 1..13; chan 14: d0)
  774. * 1c: 00
  775. * 1d: 84
  776. */
  777. adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
  778. /* antenna selection: diversity */
  779. adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
  780. adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
  781. adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
  782. adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
  783. if (priv->eeprom->major_version < 2) {
  784. adm8211_write_bbp(dev, 0x1c, 0x00);
  785. adm8211_write_bbp(dev, 0x1d, 0x80);
  786. } else {
  787. if (priv->pdev->revision == ADM8211_REV_BA)
  788. adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
  789. else
  790. adm8211_write_bbp(dev, 0x1c, 0x00);
  791. adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
  792. }
  793. } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
  794. /* reset baseband */
  795. adm8211_write_bbp(dev, 0x00, 0xFF);
  796. /* antenna selection: diversity */
  797. adm8211_write_bbp(dev, 0x07, 0x0A);
  798. /* TODO: find documentation for this */
  799. switch (priv->transceiver_type) {
  800. case ADM8211_RFMD2958:
  801. case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
  802. adm8211_write_bbp(dev, 0x00, 0x00);
  803. adm8211_write_bbp(dev, 0x01, 0x00);
  804. adm8211_write_bbp(dev, 0x02, 0x00);
  805. adm8211_write_bbp(dev, 0x03, 0x00);
  806. adm8211_write_bbp(dev, 0x06, 0x0f);
  807. adm8211_write_bbp(dev, 0x09, 0x00);
  808. adm8211_write_bbp(dev, 0x0a, 0x00);
  809. adm8211_write_bbp(dev, 0x0b, 0x00);
  810. adm8211_write_bbp(dev, 0x0c, 0x00);
  811. adm8211_write_bbp(dev, 0x0f, 0xAA);
  812. adm8211_write_bbp(dev, 0x10, 0x8c);
  813. adm8211_write_bbp(dev, 0x11, 0x43);
  814. adm8211_write_bbp(dev, 0x18, 0x40);
  815. adm8211_write_bbp(dev, 0x20, 0x23);
  816. adm8211_write_bbp(dev, 0x21, 0x02);
  817. adm8211_write_bbp(dev, 0x22, 0x28);
  818. adm8211_write_bbp(dev, 0x23, 0x30);
  819. adm8211_write_bbp(dev, 0x24, 0x2d);
  820. adm8211_write_bbp(dev, 0x28, 0x35);
  821. adm8211_write_bbp(dev, 0x2a, 0x8c);
  822. adm8211_write_bbp(dev, 0x2b, 0x81);
  823. adm8211_write_bbp(dev, 0x2c, 0x44);
  824. adm8211_write_bbp(dev, 0x2d, 0x0A);
  825. adm8211_write_bbp(dev, 0x29, 0x40);
  826. adm8211_write_bbp(dev, 0x60, 0x08);
  827. adm8211_write_bbp(dev, 0x64, 0x01);
  828. break;
  829. case ADM8211_MAX2820:
  830. adm8211_write_bbp(dev, 0x00, 0x00);
  831. adm8211_write_bbp(dev, 0x01, 0x00);
  832. adm8211_write_bbp(dev, 0x02, 0x00);
  833. adm8211_write_bbp(dev, 0x03, 0x00);
  834. adm8211_write_bbp(dev, 0x06, 0x0f);
  835. adm8211_write_bbp(dev, 0x09, 0x05);
  836. adm8211_write_bbp(dev, 0x0a, 0x02);
  837. adm8211_write_bbp(dev, 0x0b, 0x00);
  838. adm8211_write_bbp(dev, 0x0c, 0x0f);
  839. adm8211_write_bbp(dev, 0x0f, 0x55);
  840. adm8211_write_bbp(dev, 0x10, 0x8d);
  841. adm8211_write_bbp(dev, 0x11, 0x43);
  842. adm8211_write_bbp(dev, 0x18, 0x4a);
  843. adm8211_write_bbp(dev, 0x20, 0x20);
  844. adm8211_write_bbp(dev, 0x21, 0x02);
  845. adm8211_write_bbp(dev, 0x22, 0x23);
  846. adm8211_write_bbp(dev, 0x23, 0x30);
  847. adm8211_write_bbp(dev, 0x24, 0x2d);
  848. adm8211_write_bbp(dev, 0x2a, 0x8c);
  849. adm8211_write_bbp(dev, 0x2b, 0x81);
  850. adm8211_write_bbp(dev, 0x2c, 0x44);
  851. adm8211_write_bbp(dev, 0x29, 0x4a);
  852. adm8211_write_bbp(dev, 0x60, 0x2b);
  853. adm8211_write_bbp(dev, 0x64, 0x01);
  854. break;
  855. case ADM8211_AL2210L:
  856. adm8211_write_bbp(dev, 0x00, 0x00);
  857. adm8211_write_bbp(dev, 0x01, 0x00);
  858. adm8211_write_bbp(dev, 0x02, 0x00);
  859. adm8211_write_bbp(dev, 0x03, 0x00);
  860. adm8211_write_bbp(dev, 0x06, 0x0f);
  861. adm8211_write_bbp(dev, 0x07, 0x05);
  862. adm8211_write_bbp(dev, 0x08, 0x03);
  863. adm8211_write_bbp(dev, 0x09, 0x00);
  864. adm8211_write_bbp(dev, 0x0a, 0x00);
  865. adm8211_write_bbp(dev, 0x0b, 0x00);
  866. adm8211_write_bbp(dev, 0x0c, 0x10);
  867. adm8211_write_bbp(dev, 0x0f, 0x55);
  868. adm8211_write_bbp(dev, 0x10, 0x8d);
  869. adm8211_write_bbp(dev, 0x11, 0x43);
  870. adm8211_write_bbp(dev, 0x18, 0x4a);
  871. adm8211_write_bbp(dev, 0x20, 0x20);
  872. adm8211_write_bbp(dev, 0x21, 0x02);
  873. adm8211_write_bbp(dev, 0x22, 0x23);
  874. adm8211_write_bbp(dev, 0x23, 0x30);
  875. adm8211_write_bbp(dev, 0x24, 0x2d);
  876. adm8211_write_bbp(dev, 0x2a, 0xaa);
  877. adm8211_write_bbp(dev, 0x2b, 0x81);
  878. adm8211_write_bbp(dev, 0x2c, 0x44);
  879. adm8211_write_bbp(dev, 0x29, 0xfa);
  880. adm8211_write_bbp(dev, 0x60, 0x2d);
  881. adm8211_write_bbp(dev, 0x64, 0x01);
  882. break;
  883. case ADM8211_RFMD2948:
  884. break;
  885. default:
  886. wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
  887. priv->transceiver_type);
  888. break;
  889. }
  890. } else
  891. wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
  892. ADM8211_CSR_WRITE(SYNRF, 0);
  893. /* Set RF CAL control source to MAC control */
  894. reg = ADM8211_CSR_READ(SYNCTL);
  895. reg |= ADM8211_SYNCTL_SELCAL;
  896. ADM8211_CSR_WRITE(SYNCTL, reg);
  897. return 0;
  898. }
  899. /* configures hw beacons/probe responses */
  900. static int adm8211_set_rate(struct ieee80211_hw *dev)
  901. {
  902. struct adm8211_priv *priv = dev->priv;
  903. u32 reg;
  904. int i = 0;
  905. u8 rate_buf[12] = {0};
  906. /* write supported rates */
  907. if (priv->pdev->revision != ADM8211_REV_BA) {
  908. rate_buf[0] = ARRAY_SIZE(adm8211_rates);
  909. for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
  910. rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
  911. } else {
  912. /* workaround for rev BA specific bug */
  913. rate_buf[0] = 0x04;
  914. rate_buf[1] = 0x82;
  915. rate_buf[2] = 0x04;
  916. rate_buf[3] = 0x0b;
  917. rate_buf[4] = 0x16;
  918. }
  919. adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
  920. ARRAY_SIZE(adm8211_rates) + 1);
  921. reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
  922. reg |= 1 << 15; /* short preamble */
  923. reg |= 110 << 24;
  924. ADM8211_CSR_WRITE(PLCPHD, reg);
  925. /* MTMLT = 512 TU (max TX MSDU lifetime)
  926. * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
  927. * SRTYLIM = 224 (short retry limit, TX header value is default) */
  928. ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
  929. return 0;
  930. }
  931. static void adm8211_hw_init(struct ieee80211_hw *dev)
  932. {
  933. struct adm8211_priv *priv = dev->priv;
  934. u32 reg;
  935. u8 cline;
  936. reg = ADM8211_CSR_READ(PAR);
  937. reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
  938. reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
  939. if (!pci_set_mwi(priv->pdev)) {
  940. reg |= 0x1 << 24;
  941. pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
  942. switch (cline) {
  943. case 0x8: reg |= (0x1 << 14);
  944. break;
  945. case 0x16: reg |= (0x2 << 14);
  946. break;
  947. case 0x32: reg |= (0x3 << 14);
  948. break;
  949. default: reg |= (0x0 << 14);
  950. break;
  951. }
  952. }
  953. ADM8211_CSR_WRITE(PAR, reg);
  954. reg = ADM8211_CSR_READ(CSR_TEST1);
  955. reg &= ~(0xF << 28);
  956. reg |= (1 << 28) | (1 << 31);
  957. ADM8211_CSR_WRITE(CSR_TEST1, reg);
  958. /* lose link after 4 lost beacons */
  959. reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
  960. ADM8211_CSR_WRITE(WCSR, reg);
  961. /* Disable APM, enable receive FIFO threshold, and set drain receive
  962. * threshold to store-and-forward */
  963. reg = ADM8211_CSR_READ(CMDR);
  964. reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
  965. reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
  966. ADM8211_CSR_WRITE(CMDR, reg);
  967. adm8211_set_rate(dev);
  968. /* 4-bit values:
  969. * PWR1UP = 8 * 2 ms
  970. * PWR0PAPE = 8 us or 5 us
  971. * PWR1PAPE = 1 us or 3 us
  972. * PWR0TRSW = 5 us
  973. * PWR1TRSW = 12 us
  974. * PWR0PE2 = 13 us
  975. * PWR1PE2 = 1 us
  976. * PWR0TXPE = 8 or 6 */
  977. if (priv->pdev->revision < ADM8211_REV_CA)
  978. ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
  979. else
  980. ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
  981. /* Enable store and forward for transmit */
  982. priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
  983. ADM8211_CSR_WRITE(NAR, priv->nar);
  984. /* Reset RF */
  985. ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
  986. ADM8211_CSR_READ(SYNRF);
  987. msleep(10);
  988. ADM8211_CSR_WRITE(SYNRF, 0);
  989. ADM8211_CSR_READ(SYNRF);
  990. msleep(5);
  991. /* Set CFP Max Duration to 0x10 TU */
  992. reg = ADM8211_CSR_READ(CFPP);
  993. reg &= ~(0xffff << 8);
  994. reg |= 0x0010 << 8;
  995. ADM8211_CSR_WRITE(CFPP, reg);
  996. /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
  997. * TUCNT = 0x3ff - Tu counter 1024 us */
  998. ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
  999. /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
  1000. * DIFS=50 us, EIFS=100 us */
  1001. if (priv->pdev->revision < ADM8211_REV_CA)
  1002. ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
  1003. (50 << 9) | 100);
  1004. else
  1005. ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
  1006. (50 << 9) | 100);
  1007. /* PCNT = 1 (MAC idle time awake/sleep, unit S)
  1008. * RMRD = 2346 * 8 + 1 us (max RX duration) */
  1009. ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
  1010. /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
  1011. ADM8211_CSR_WRITE(RSPT, 0xffffff00);
  1012. /* Initialize BBP (and SYN) */
  1013. adm8211_hw_init_bbp(dev);
  1014. /* make sure interrupts are off */
  1015. ADM8211_CSR_WRITE(IER, 0);
  1016. /* ACK interrupts */
  1017. ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
  1018. /* Setup WEP (turns it off for now) */
  1019. reg = ADM8211_CSR_READ(MACTEST);
  1020. reg &= ~(7 << 20);
  1021. ADM8211_CSR_WRITE(MACTEST, reg);
  1022. reg = ADM8211_CSR_READ(WEPCTL);
  1023. reg &= ~ADM8211_WEPCTL_WEPENABLE;
  1024. reg |= ADM8211_WEPCTL_WEPRXBYP;
  1025. ADM8211_CSR_WRITE(WEPCTL, reg);
  1026. /* Clear the missed-packet counter. */
  1027. ADM8211_CSR_READ(LPC);
  1028. }
  1029. static int adm8211_hw_reset(struct ieee80211_hw *dev)
  1030. {
  1031. struct adm8211_priv *priv = dev->priv;
  1032. u32 reg, tmp;
  1033. int timeout = 100;
  1034. /* Power-on issue */
  1035. /* TODO: check if this is necessary */
  1036. ADM8211_CSR_WRITE(FRCTL, 0);
  1037. /* Reset the chip */
  1038. tmp = ADM8211_CSR_READ(PAR);
  1039. ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
  1040. while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
  1041. msleep(50);
  1042. if (timeout <= 0)
  1043. return -ETIMEDOUT;
  1044. ADM8211_CSR_WRITE(PAR, tmp);
  1045. if (priv->pdev->revision == ADM8211_REV_BA &&
  1046. (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
  1047. priv->transceiver_type == ADM8211_RFMD2958)) {
  1048. reg = ADM8211_CSR_READ(CSR_TEST1);
  1049. reg |= (1 << 4) | (1 << 5);
  1050. ADM8211_CSR_WRITE(CSR_TEST1, reg);
  1051. } else if (priv->pdev->revision == ADM8211_REV_CA) {
  1052. reg = ADM8211_CSR_READ(CSR_TEST1);
  1053. reg &= ~((1 << 4) | (1 << 5));
  1054. ADM8211_CSR_WRITE(CSR_TEST1, reg);
  1055. }
  1056. ADM8211_CSR_WRITE(FRCTL, 0);
  1057. reg = ADM8211_CSR_READ(CSR_TEST0);
  1058. reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
  1059. ADM8211_CSR_WRITE(CSR_TEST0, reg);
  1060. adm8211_clear_sram(dev);
  1061. return 0;
  1062. }
  1063. static u64 adm8211_get_tsft(struct ieee80211_hw *dev,
  1064. struct ieee80211_vif *vif)
  1065. {
  1066. struct adm8211_priv *priv = dev->priv;
  1067. u32 tsftl;
  1068. u64 tsft;
  1069. tsftl = ADM8211_CSR_READ(TSFTL);
  1070. tsft = ADM8211_CSR_READ(TSFTH);
  1071. tsft <<= 32;
  1072. tsft |= tsftl;
  1073. return tsft;
  1074. }
  1075. static void adm8211_set_interval(struct ieee80211_hw *dev,
  1076. unsigned short bi, unsigned short li)
  1077. {
  1078. struct adm8211_priv *priv = dev->priv;
  1079. u32 reg;
  1080. /* BP (beacon interval) = data->beacon_interval
  1081. * LI (listen interval) = data->listen_interval (in beacon intervals) */
  1082. reg = (bi << 16) | li;
  1083. ADM8211_CSR_WRITE(BPLI, reg);
  1084. }
  1085. static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
  1086. {
  1087. struct adm8211_priv *priv = dev->priv;
  1088. u32 reg;
  1089. ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
  1090. reg = ADM8211_CSR_READ(ABDA1);
  1091. reg &= 0x0000ffff;
  1092. reg |= (bssid[4] << 16) | (bssid[5] << 24);
  1093. ADM8211_CSR_WRITE(ABDA1, reg);
  1094. }
  1095. static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
  1096. {
  1097. struct adm8211_priv *priv = dev->priv;
  1098. struct ieee80211_conf *conf = &dev->conf;
  1099. int channel =
  1100. ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
  1101. if (channel != priv->channel) {
  1102. priv->channel = channel;
  1103. adm8211_rf_set_channel(dev, priv->channel);
  1104. }
  1105. return 0;
  1106. }
  1107. static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
  1108. struct ieee80211_vif *vif,
  1109. struct ieee80211_bss_conf *conf,
  1110. u32 changes)
  1111. {
  1112. struct adm8211_priv *priv = dev->priv;
  1113. if (!(changes & BSS_CHANGED_BSSID))
  1114. return;
  1115. if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
  1116. adm8211_set_bssid(dev, conf->bssid);
  1117. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  1118. }
  1119. }
  1120. static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
  1121. struct netdev_hw_addr_list *mc_list)
  1122. {
  1123. unsigned int bit_nr;
  1124. u32 mc_filter[2];
  1125. struct netdev_hw_addr *ha;
  1126. mc_filter[1] = mc_filter[0] = 0;
  1127. netdev_hw_addr_list_for_each(ha, mc_list) {
  1128. bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1129. bit_nr &= 0x3F;
  1130. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1131. }
  1132. return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
  1133. }
  1134. static void adm8211_configure_filter(struct ieee80211_hw *dev,
  1135. unsigned int changed_flags,
  1136. unsigned int *total_flags,
  1137. u64 multicast)
  1138. {
  1139. static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  1140. struct adm8211_priv *priv = dev->priv;
  1141. unsigned int new_flags;
  1142. u32 mc_filter[2];
  1143. mc_filter[0] = multicast;
  1144. mc_filter[1] = multicast >> 32;
  1145. new_flags = 0;
  1146. if (*total_flags & FIF_PROMISC_IN_BSS) {
  1147. new_flags |= FIF_PROMISC_IN_BSS;
  1148. priv->nar |= ADM8211_NAR_PR;
  1149. priv->nar &= ~ADM8211_NAR_MM;
  1150. mc_filter[1] = mc_filter[0] = ~0;
  1151. } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
  1152. new_flags |= FIF_ALLMULTI;
  1153. priv->nar &= ~ADM8211_NAR_PR;
  1154. priv->nar |= ADM8211_NAR_MM;
  1155. mc_filter[1] = mc_filter[0] = ~0;
  1156. } else {
  1157. priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
  1158. }
  1159. ADM8211_IDLE_RX();
  1160. ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
  1161. ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
  1162. ADM8211_CSR_READ(NAR);
  1163. if (priv->nar & ADM8211_NAR_PR)
  1164. dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
  1165. else
  1166. dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
  1167. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1168. adm8211_set_bssid(dev, bcast);
  1169. else
  1170. adm8211_set_bssid(dev, priv->bssid);
  1171. ADM8211_RESTORE();
  1172. *total_flags = new_flags;
  1173. }
  1174. static int adm8211_add_interface(struct ieee80211_hw *dev,
  1175. struct ieee80211_vif *vif)
  1176. {
  1177. struct adm8211_priv *priv = dev->priv;
  1178. if (priv->mode != NL80211_IFTYPE_MONITOR)
  1179. return -EOPNOTSUPP;
  1180. switch (vif->type) {
  1181. case NL80211_IFTYPE_STATION:
  1182. priv->mode = vif->type;
  1183. break;
  1184. default:
  1185. return -EOPNOTSUPP;
  1186. }
  1187. ADM8211_IDLE();
  1188. ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
  1189. ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
  1190. adm8211_update_mode(dev);
  1191. ADM8211_RESTORE();
  1192. return 0;
  1193. }
  1194. static void adm8211_remove_interface(struct ieee80211_hw *dev,
  1195. struct ieee80211_vif *vif)
  1196. {
  1197. struct adm8211_priv *priv = dev->priv;
  1198. priv->mode = NL80211_IFTYPE_MONITOR;
  1199. }
  1200. static int adm8211_init_rings(struct ieee80211_hw *dev)
  1201. {
  1202. struct adm8211_priv *priv = dev->priv;
  1203. struct adm8211_desc *desc = NULL;
  1204. struct adm8211_rx_ring_info *rx_info;
  1205. struct adm8211_tx_ring_info *tx_info;
  1206. unsigned int i;
  1207. for (i = 0; i < priv->rx_ring_size; i++) {
  1208. desc = &priv->rx_ring[i];
  1209. desc->status = 0;
  1210. desc->length = cpu_to_le32(RX_PKT_SIZE);
  1211. priv->rx_buffers[i].skb = NULL;
  1212. }
  1213. /* Mark the end of RX ring; hw returns to base address after this
  1214. * descriptor */
  1215. desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
  1216. for (i = 0; i < priv->rx_ring_size; i++) {
  1217. desc = &priv->rx_ring[i];
  1218. rx_info = &priv->rx_buffers[i];
  1219. rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
  1220. if (rx_info->skb == NULL)
  1221. break;
  1222. rx_info->mapping = pci_map_single(priv->pdev,
  1223. skb_tail_pointer(rx_info->skb),
  1224. RX_PKT_SIZE,
  1225. PCI_DMA_FROMDEVICE);
  1226. desc->buffer1 = cpu_to_le32(rx_info->mapping);
  1227. desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
  1228. }
  1229. /* Setup TX ring. TX buffers descriptors will be filled in as needed */
  1230. for (i = 0; i < priv->tx_ring_size; i++) {
  1231. desc = &priv->tx_ring[i];
  1232. tx_info = &priv->tx_buffers[i];
  1233. tx_info->skb = NULL;
  1234. tx_info->mapping = 0;
  1235. desc->status = 0;
  1236. }
  1237. desc->length = cpu_to_le32(TDES1_CONTROL_TER);
  1238. priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
  1239. ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
  1240. ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
  1241. return 0;
  1242. }
  1243. static void adm8211_free_rings(struct ieee80211_hw *dev)
  1244. {
  1245. struct adm8211_priv *priv = dev->priv;
  1246. unsigned int i;
  1247. for (i = 0; i < priv->rx_ring_size; i++) {
  1248. if (!priv->rx_buffers[i].skb)
  1249. continue;
  1250. pci_unmap_single(
  1251. priv->pdev,
  1252. priv->rx_buffers[i].mapping,
  1253. RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
  1254. dev_kfree_skb(priv->rx_buffers[i].skb);
  1255. }
  1256. for (i = 0; i < priv->tx_ring_size; i++) {
  1257. if (!priv->tx_buffers[i].skb)
  1258. continue;
  1259. pci_unmap_single(priv->pdev,
  1260. priv->tx_buffers[i].mapping,
  1261. priv->tx_buffers[i].skb->len,
  1262. PCI_DMA_TODEVICE);
  1263. dev_kfree_skb(priv->tx_buffers[i].skb);
  1264. }
  1265. }
  1266. static int adm8211_start(struct ieee80211_hw *dev)
  1267. {
  1268. struct adm8211_priv *priv = dev->priv;
  1269. int retval;
  1270. /* Power up MAC and RF chips */
  1271. retval = adm8211_hw_reset(dev);
  1272. if (retval) {
  1273. wiphy_err(dev->wiphy, "hardware reset failed\n");
  1274. goto fail;
  1275. }
  1276. retval = adm8211_init_rings(dev);
  1277. if (retval) {
  1278. wiphy_err(dev->wiphy, "failed to initialize rings\n");
  1279. goto fail;
  1280. }
  1281. /* Init hardware */
  1282. adm8211_hw_init(dev);
  1283. adm8211_rf_set_channel(dev, priv->channel);
  1284. retval = request_irq(priv->pdev->irq, adm8211_interrupt,
  1285. IRQF_SHARED, "adm8211", dev);
  1286. if (retval) {
  1287. wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
  1288. goto fail;
  1289. }
  1290. ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
  1291. ADM8211_IER_RCIE | ADM8211_IER_TCIE |
  1292. ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
  1293. priv->mode = NL80211_IFTYPE_MONITOR;
  1294. adm8211_update_mode(dev);
  1295. ADM8211_CSR_WRITE(RDR, 0);
  1296. adm8211_set_interval(dev, 100, 10);
  1297. return 0;
  1298. fail:
  1299. return retval;
  1300. }
  1301. static void adm8211_stop(struct ieee80211_hw *dev)
  1302. {
  1303. struct adm8211_priv *priv = dev->priv;
  1304. priv->mode = NL80211_IFTYPE_UNSPECIFIED;
  1305. priv->nar = 0;
  1306. ADM8211_CSR_WRITE(NAR, 0);
  1307. ADM8211_CSR_WRITE(IER, 0);
  1308. ADM8211_CSR_READ(NAR);
  1309. free_irq(priv->pdev->irq, dev);
  1310. adm8211_free_rings(dev);
  1311. }
  1312. static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
  1313. int plcp_signal, int short_preamble)
  1314. {
  1315. /* Alternative calculation from NetBSD: */
  1316. /* IEEE 802.11b durations for DSSS PHY in microseconds */
  1317. #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
  1318. #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
  1319. #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
  1320. #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
  1321. #define IEEE80211_DUR_DS_SLOW_ACK 112
  1322. #define IEEE80211_DUR_DS_FAST_ACK 56
  1323. #define IEEE80211_DUR_DS_SLOW_CTS 112
  1324. #define IEEE80211_DUR_DS_FAST_CTS 56
  1325. #define IEEE80211_DUR_DS_SLOT 20
  1326. #define IEEE80211_DUR_DS_SIFS 10
  1327. int remainder;
  1328. *dur = (80 * (24 + payload_len) + plcp_signal - 1)
  1329. / plcp_signal;
  1330. if (plcp_signal <= PLCP_SIGNAL_2M)
  1331. /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
  1332. *dur += 3 * (IEEE80211_DUR_DS_SIFS +
  1333. IEEE80211_DUR_DS_SHORT_PREAMBLE +
  1334. IEEE80211_DUR_DS_FAST_PLCPHDR) +
  1335. IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
  1336. else
  1337. /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
  1338. *dur += 3 * (IEEE80211_DUR_DS_SIFS +
  1339. IEEE80211_DUR_DS_SHORT_PREAMBLE +
  1340. IEEE80211_DUR_DS_FAST_PLCPHDR) +
  1341. IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
  1342. /* lengthen duration if long preamble */
  1343. if (!short_preamble)
  1344. *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
  1345. IEEE80211_DUR_DS_SHORT_PREAMBLE) +
  1346. 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
  1347. IEEE80211_DUR_DS_FAST_PLCPHDR);
  1348. *plcp = (80 * len) / plcp_signal;
  1349. remainder = (80 * len) % plcp_signal;
  1350. if (plcp_signal == PLCP_SIGNAL_11M &&
  1351. remainder <= 30 && remainder > 0)
  1352. *plcp = (*plcp | 0x8000) + 1;
  1353. else if (remainder)
  1354. (*plcp)++;
  1355. }
  1356. /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
  1357. static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
  1358. u16 plcp_signal,
  1359. size_t hdrlen)
  1360. {
  1361. struct adm8211_priv *priv = dev->priv;
  1362. unsigned long flags;
  1363. dma_addr_t mapping;
  1364. unsigned int entry;
  1365. u32 flag;
  1366. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  1367. PCI_DMA_TODEVICE);
  1368. spin_lock_irqsave(&priv->lock, flags);
  1369. if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
  1370. flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
  1371. else
  1372. flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
  1373. if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
  1374. ieee80211_stop_queue(dev, 0);
  1375. entry = priv->cur_tx % priv->tx_ring_size;
  1376. priv->tx_buffers[entry].skb = skb;
  1377. priv->tx_buffers[entry].mapping = mapping;
  1378. priv->tx_buffers[entry].hdrlen = hdrlen;
  1379. priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
  1380. if (entry == priv->tx_ring_size - 1)
  1381. flag |= TDES1_CONTROL_TER;
  1382. priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
  1383. /* Set TX rate (SIGNAL field in PLCP PPDU format) */
  1384. flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
  1385. priv->tx_ring[entry].status = cpu_to_le32(flag);
  1386. priv->cur_tx++;
  1387. spin_unlock_irqrestore(&priv->lock, flags);
  1388. /* Trigger transmit poll */
  1389. ADM8211_CSR_WRITE(TDR, 0);
  1390. }
  1391. /* Put adm8211_tx_hdr on skb and transmit */
  1392. static void adm8211_tx(struct ieee80211_hw *dev,
  1393. struct ieee80211_tx_control *control,
  1394. struct sk_buff *skb)
  1395. {
  1396. struct adm8211_tx_hdr *txhdr;
  1397. size_t payload_len, hdrlen;
  1398. int plcp, dur, len, plcp_signal, short_preamble;
  1399. struct ieee80211_hdr *hdr;
  1400. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1401. struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
  1402. u8 rc_flags;
  1403. rc_flags = info->control.rates[0].flags;
  1404. short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
  1405. plcp_signal = txrate->bitrate;
  1406. hdr = (struct ieee80211_hdr *)skb->data;
  1407. hdrlen = ieee80211_hdrlen(hdr->frame_control);
  1408. memcpy(skb->cb, skb->data, hdrlen);
  1409. hdr = (struct ieee80211_hdr *)skb->cb;
  1410. skb_pull(skb, hdrlen);
  1411. payload_len = skb->len;
  1412. txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
  1413. memset(txhdr, 0, sizeof(*txhdr));
  1414. memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
  1415. txhdr->signal = plcp_signal;
  1416. txhdr->frame_body_size = cpu_to_le16(payload_len);
  1417. txhdr->frame_control = hdr->frame_control;
  1418. len = hdrlen + payload_len + FCS_LEN;
  1419. txhdr->frag = cpu_to_le16(0x0FFF);
  1420. adm8211_calc_durations(&dur, &plcp, payload_len,
  1421. len, plcp_signal, short_preamble);
  1422. txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
  1423. txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
  1424. txhdr->dur_frag_head = cpu_to_le16(dur);
  1425. txhdr->dur_frag_tail = cpu_to_le16(dur);
  1426. txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
  1427. if (short_preamble)
  1428. txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
  1429. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
  1430. txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
  1431. txhdr->retry_limit = info->control.rates[0].count;
  1432. adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
  1433. }
  1434. static int adm8211_alloc_rings(struct ieee80211_hw *dev)
  1435. {
  1436. struct adm8211_priv *priv = dev->priv;
  1437. unsigned int ring_size;
  1438. priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
  1439. sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
  1440. if (!priv->rx_buffers)
  1441. return -ENOMEM;
  1442. priv->tx_buffers = (void *)priv->rx_buffers +
  1443. sizeof(*priv->rx_buffers) * priv->rx_ring_size;
  1444. /* Allocate TX/RX descriptors */
  1445. ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
  1446. sizeof(struct adm8211_desc) * priv->tx_ring_size;
  1447. priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
  1448. &priv->rx_ring_dma);
  1449. if (!priv->rx_ring) {
  1450. kfree(priv->rx_buffers);
  1451. priv->rx_buffers = NULL;
  1452. priv->tx_buffers = NULL;
  1453. return -ENOMEM;
  1454. }
  1455. priv->tx_ring = priv->rx_ring + priv->rx_ring_size;
  1456. priv->tx_ring_dma = priv->rx_ring_dma +
  1457. sizeof(struct adm8211_desc) * priv->rx_ring_size;
  1458. return 0;
  1459. }
  1460. static const struct ieee80211_ops adm8211_ops = {
  1461. .tx = adm8211_tx,
  1462. .start = adm8211_start,
  1463. .stop = adm8211_stop,
  1464. .add_interface = adm8211_add_interface,
  1465. .remove_interface = adm8211_remove_interface,
  1466. .config = adm8211_config,
  1467. .bss_info_changed = adm8211_bss_info_changed,
  1468. .prepare_multicast = adm8211_prepare_multicast,
  1469. .configure_filter = adm8211_configure_filter,
  1470. .get_stats = adm8211_get_stats,
  1471. .get_tsf = adm8211_get_tsft
  1472. };
  1473. static int adm8211_probe(struct pci_dev *pdev,
  1474. const struct pci_device_id *id)
  1475. {
  1476. struct ieee80211_hw *dev;
  1477. struct adm8211_priv *priv;
  1478. unsigned long mem_addr, mem_len;
  1479. unsigned int io_addr, io_len;
  1480. int err;
  1481. u32 reg;
  1482. u8 perm_addr[ETH_ALEN];
  1483. err = pci_enable_device(pdev);
  1484. if (err) {
  1485. printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
  1486. pci_name(pdev));
  1487. return err;
  1488. }
  1489. io_addr = pci_resource_start(pdev, 0);
  1490. io_len = pci_resource_len(pdev, 0);
  1491. mem_addr = pci_resource_start(pdev, 1);
  1492. mem_len = pci_resource_len(pdev, 1);
  1493. if (io_len < 256 || mem_len < 1024) {
  1494. printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
  1495. pci_name(pdev));
  1496. goto err_disable_pdev;
  1497. }
  1498. /* check signature */
  1499. pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
  1500. if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
  1501. printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
  1502. pci_name(pdev), reg);
  1503. goto err_disable_pdev;
  1504. }
  1505. err = pci_request_regions(pdev, "adm8211");
  1506. if (err) {
  1507. printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
  1508. pci_name(pdev));
  1509. return err; /* someone else grabbed it? don't disable it */
  1510. }
  1511. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  1512. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1513. printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
  1514. pci_name(pdev));
  1515. goto err_free_reg;
  1516. }
  1517. pci_set_master(pdev);
  1518. dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
  1519. if (!dev) {
  1520. printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
  1521. pci_name(pdev));
  1522. err = -ENOMEM;
  1523. goto err_free_reg;
  1524. }
  1525. priv = dev->priv;
  1526. priv->pdev = pdev;
  1527. spin_lock_init(&priv->lock);
  1528. SET_IEEE80211_DEV(dev, &pdev->dev);
  1529. pci_set_drvdata(pdev, dev);
  1530. priv->map = pci_iomap(pdev, 1, mem_len);
  1531. if (!priv->map)
  1532. priv->map = pci_iomap(pdev, 0, io_len);
  1533. if (!priv->map) {
  1534. printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
  1535. pci_name(pdev));
  1536. goto err_free_dev;
  1537. }
  1538. priv->rx_ring_size = rx_ring_size;
  1539. priv->tx_ring_size = tx_ring_size;
  1540. if (adm8211_alloc_rings(dev)) {
  1541. printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
  1542. pci_name(pdev));
  1543. goto err_iounmap;
  1544. }
  1545. *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
  1546. *(__le16 *)&perm_addr[4] =
  1547. cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
  1548. if (!is_valid_ether_addr(perm_addr)) {
  1549. printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
  1550. pci_name(pdev));
  1551. eth_random_addr(perm_addr);
  1552. }
  1553. SET_IEEE80211_PERM_ADDR(dev, perm_addr);
  1554. dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
  1555. /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
  1556. dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
  1557. dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  1558. dev->channel_change_time = 1000;
  1559. dev->max_signal = 100; /* FIXME: find better value */
  1560. dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
  1561. priv->retry_limit = 3;
  1562. priv->ant_power = 0x40;
  1563. priv->tx_power = 0x40;
  1564. priv->lpf_cutoff = 0xFF;
  1565. priv->lnags_threshold = 0xFF;
  1566. priv->mode = NL80211_IFTYPE_UNSPECIFIED;
  1567. /* Power-on issue. EEPROM won't read correctly without */
  1568. if (pdev->revision >= ADM8211_REV_BA) {
  1569. ADM8211_CSR_WRITE(FRCTL, 0);
  1570. ADM8211_CSR_READ(FRCTL);
  1571. ADM8211_CSR_WRITE(FRCTL, 1);
  1572. ADM8211_CSR_READ(FRCTL);
  1573. msleep(100);
  1574. }
  1575. err = adm8211_read_eeprom(dev);
  1576. if (err) {
  1577. printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
  1578. pci_name(pdev));
  1579. goto err_free_desc;
  1580. }
  1581. priv->channel = 1;
  1582. dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  1583. err = ieee80211_register_hw(dev);
  1584. if (err) {
  1585. printk(KERN_ERR "%s (adm8211): Cannot register device\n",
  1586. pci_name(pdev));
  1587. goto err_free_eeprom;
  1588. }
  1589. wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n",
  1590. dev->wiphy->perm_addr, pdev->revision);
  1591. return 0;
  1592. err_free_eeprom:
  1593. kfree(priv->eeprom);
  1594. err_free_desc:
  1595. pci_free_consistent(pdev,
  1596. sizeof(struct adm8211_desc) * priv->rx_ring_size +
  1597. sizeof(struct adm8211_desc) * priv->tx_ring_size,
  1598. priv->rx_ring, priv->rx_ring_dma);
  1599. kfree(priv->rx_buffers);
  1600. err_iounmap:
  1601. pci_iounmap(pdev, priv->map);
  1602. err_free_dev:
  1603. pci_set_drvdata(pdev, NULL);
  1604. ieee80211_free_hw(dev);
  1605. err_free_reg:
  1606. pci_release_regions(pdev);
  1607. err_disable_pdev:
  1608. pci_disable_device(pdev);
  1609. return err;
  1610. }
  1611. static void adm8211_remove(struct pci_dev *pdev)
  1612. {
  1613. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  1614. struct adm8211_priv *priv;
  1615. if (!dev)
  1616. return;
  1617. ieee80211_unregister_hw(dev);
  1618. priv = dev->priv;
  1619. pci_free_consistent(pdev,
  1620. sizeof(struct adm8211_desc) * priv->rx_ring_size +
  1621. sizeof(struct adm8211_desc) * priv->tx_ring_size,
  1622. priv->rx_ring, priv->rx_ring_dma);
  1623. kfree(priv->rx_buffers);
  1624. kfree(priv->eeprom);
  1625. pci_iounmap(pdev, priv->map);
  1626. pci_release_regions(pdev);
  1627. pci_disable_device(pdev);
  1628. ieee80211_free_hw(dev);
  1629. }
  1630. #ifdef CONFIG_PM
  1631. static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
  1632. {
  1633. pci_save_state(pdev);
  1634. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  1635. return 0;
  1636. }
  1637. static int adm8211_resume(struct pci_dev *pdev)
  1638. {
  1639. pci_set_power_state(pdev, PCI_D0);
  1640. pci_restore_state(pdev);
  1641. return 0;
  1642. }
  1643. #endif /* CONFIG_PM */
  1644. MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
  1645. /* TODO: implement enable_wake */
  1646. static struct pci_driver adm8211_driver = {
  1647. .name = "adm8211",
  1648. .id_table = adm8211_pci_id_table,
  1649. .probe = adm8211_probe,
  1650. .remove = adm8211_remove,
  1651. #ifdef CONFIG_PM
  1652. .suspend = adm8211_suspend,
  1653. .resume = adm8211_resume,
  1654. #endif /* CONFIG_PM */
  1655. };
  1656. module_pci_driver(adm8211_driver);