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/drivers/net/wireless/rt2x00/rt2400pci.c

http://github.com/mirrors/linux
C | 1855 lines | 1277 code | 267 blank | 311 comment | 116 complexity | 88c6c4c71e6ce1bc677dd39fe61786b6 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0
  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2400pci
  19. Abstract: rt2400pci device specific routines.
  20. Supported chipsets: RT2460.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/eeprom_93cx6.h>
  29. #include <linux/slab.h>
  30. #include "rt2x00.h"
  31. #include "rt2x00mmio.h"
  32. #include "rt2x00pci.h"
  33. #include "rt2400pci.h"
  34. /*
  35. * Register access.
  36. * All access to the CSR registers will go through the methods
  37. * rt2x00mmio_register_read and rt2x00mmio_register_write.
  38. * BBP and RF register require indirect register access,
  39. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  40. * These indirect registers work with busy bits,
  41. * and we will try maximal REGISTER_BUSY_COUNT times to access
  42. * the register while taking a REGISTER_BUSY_DELAY us delay
  43. * between each attempt. When the busy bit is still set at that time,
  44. * the access attempt is considered to have failed,
  45. * and we will print an error.
  46. */
  47. #define WAIT_FOR_BBP(__dev, __reg) \
  48. rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  49. #define WAIT_FOR_RF(__dev, __reg) \
  50. rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  51. static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  52. const unsigned int word, const u8 value)
  53. {
  54. u32 reg;
  55. mutex_lock(&rt2x00dev->csr_mutex);
  56. /*
  57. * Wait until the BBP becomes available, afterwards we
  58. * can safely write the new data into the register.
  59. */
  60. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  61. reg = 0;
  62. rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  63. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  64. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  65. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  66. rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  67. }
  68. mutex_unlock(&rt2x00dev->csr_mutex);
  69. }
  70. static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  71. const unsigned int word, u8 *value)
  72. {
  73. u32 reg;
  74. mutex_lock(&rt2x00dev->csr_mutex);
  75. /*
  76. * Wait until the BBP becomes available, afterwards we
  77. * can safely write the read request into the register.
  78. * After the data has been written, we wait until hardware
  79. * returns the correct value, if at any time the register
  80. * doesn't become available in time, reg will be 0xffffffff
  81. * which means we return 0xff to the caller.
  82. */
  83. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  84. reg = 0;
  85. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  86. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  87. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  88. rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  89. WAIT_FOR_BBP(rt2x00dev, &reg);
  90. }
  91. *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  92. mutex_unlock(&rt2x00dev->csr_mutex);
  93. }
  94. static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
  95. const unsigned int word, const u32 value)
  96. {
  97. u32 reg;
  98. mutex_lock(&rt2x00dev->csr_mutex);
  99. /*
  100. * Wait until the RF becomes available, afterwards we
  101. * can safely write the new data into the register.
  102. */
  103. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  104. reg = 0;
  105. rt2x00_set_field32(&reg, RFCSR_VALUE, value);
  106. rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
  107. rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
  108. rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
  109. rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
  110. rt2x00_rf_write(rt2x00dev, word, value);
  111. }
  112. mutex_unlock(&rt2x00dev->csr_mutex);
  113. }
  114. static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  115. {
  116. struct rt2x00_dev *rt2x00dev = eeprom->data;
  117. u32 reg;
  118. rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
  119. eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
  120. eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
  121. eeprom->reg_data_clock =
  122. !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
  123. eeprom->reg_chip_select =
  124. !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
  125. }
  126. static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  127. {
  128. struct rt2x00_dev *rt2x00dev = eeprom->data;
  129. u32 reg = 0;
  130. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
  131. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
  132. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
  133. !!eeprom->reg_data_clock);
  134. rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
  135. !!eeprom->reg_chip_select);
  136. rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
  137. }
  138. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  139. static const struct rt2x00debug rt2400pci_rt2x00debug = {
  140. .owner = THIS_MODULE,
  141. .csr = {
  142. .read = rt2x00mmio_register_read,
  143. .write = rt2x00mmio_register_write,
  144. .flags = RT2X00DEBUGFS_OFFSET,
  145. .word_base = CSR_REG_BASE,
  146. .word_size = sizeof(u32),
  147. .word_count = CSR_REG_SIZE / sizeof(u32),
  148. },
  149. .eeprom = {
  150. .read = rt2x00_eeprom_read,
  151. .write = rt2x00_eeprom_write,
  152. .word_base = EEPROM_BASE,
  153. .word_size = sizeof(u16),
  154. .word_count = EEPROM_SIZE / sizeof(u16),
  155. },
  156. .bbp = {
  157. .read = rt2400pci_bbp_read,
  158. .write = rt2400pci_bbp_write,
  159. .word_base = BBP_BASE,
  160. .word_size = sizeof(u8),
  161. .word_count = BBP_SIZE / sizeof(u8),
  162. },
  163. .rf = {
  164. .read = rt2x00_rf_read,
  165. .write = rt2400pci_rf_write,
  166. .word_base = RF_BASE,
  167. .word_size = sizeof(u32),
  168. .word_count = RF_SIZE / sizeof(u32),
  169. },
  170. };
  171. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  172. static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  173. {
  174. u32 reg;
  175. rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
  176. return rt2x00_get_field32(reg, GPIOCSR_VAL0);
  177. }
  178. #ifdef CONFIG_RT2X00_LIB_LEDS
  179. static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
  180. enum led_brightness brightness)
  181. {
  182. struct rt2x00_led *led =
  183. container_of(led_cdev, struct rt2x00_led, led_dev);
  184. unsigned int enabled = brightness != LED_OFF;
  185. u32 reg;
  186. rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
  187. if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
  188. rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
  189. else if (led->type == LED_TYPE_ACTIVITY)
  190. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
  191. rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
  192. }
  193. static int rt2400pci_blink_set(struct led_classdev *led_cdev,
  194. unsigned long *delay_on,
  195. unsigned long *delay_off)
  196. {
  197. struct rt2x00_led *led =
  198. container_of(led_cdev, struct rt2x00_led, led_dev);
  199. u32 reg;
  200. rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
  201. rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
  202. rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
  203. rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
  204. return 0;
  205. }
  206. static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
  207. struct rt2x00_led *led,
  208. enum led_type type)
  209. {
  210. led->rt2x00dev = rt2x00dev;
  211. led->type = type;
  212. led->led_dev.brightness_set = rt2400pci_brightness_set;
  213. led->led_dev.blink_set = rt2400pci_blink_set;
  214. led->flags = LED_INITIALIZED;
  215. }
  216. #endif /* CONFIG_RT2X00_LIB_LEDS */
  217. /*
  218. * Configuration handlers.
  219. */
  220. static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
  221. const unsigned int filter_flags)
  222. {
  223. u32 reg;
  224. /*
  225. * Start configuration steps.
  226. * Note that the version error will always be dropped
  227. * since there is no filter for it at this time.
  228. */
  229. rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
  230. rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
  231. !(filter_flags & FIF_FCSFAIL));
  232. rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
  233. !(filter_flags & FIF_PLCPFAIL));
  234. rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
  235. !(filter_flags & FIF_CONTROL));
  236. rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
  237. !(filter_flags & FIF_PROMISC_IN_BSS));
  238. rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
  239. !(filter_flags & FIF_PROMISC_IN_BSS) &&
  240. !rt2x00dev->intf_ap_count);
  241. rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
  242. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  243. }
  244. static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
  245. struct rt2x00_intf *intf,
  246. struct rt2x00intf_conf *conf,
  247. const unsigned int flags)
  248. {
  249. unsigned int bcn_preload;
  250. u32 reg;
  251. if (flags & CONFIG_UPDATE_TYPE) {
  252. /*
  253. * Enable beacon config
  254. */
  255. bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
  256. rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
  257. rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
  258. rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
  259. /*
  260. * Enable synchronisation.
  261. */
  262. rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
  263. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
  264. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  265. }
  266. if (flags & CONFIG_UPDATE_MAC)
  267. rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
  268. conf->mac, sizeof(conf->mac));
  269. if (flags & CONFIG_UPDATE_BSSID)
  270. rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
  271. conf->bssid,
  272. sizeof(conf->bssid));
  273. }
  274. static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
  275. struct rt2x00lib_erp *erp,
  276. u32 changed)
  277. {
  278. int preamble_mask;
  279. u32 reg;
  280. /*
  281. * When short preamble is enabled, we should set bit 0x08
  282. */
  283. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  284. preamble_mask = erp->short_preamble << 3;
  285. rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
  286. rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
  287. rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
  288. rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
  289. rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
  290. rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
  291. rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
  292. rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
  293. rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
  294. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  295. GET_DURATION(ACK_SIZE, 10));
  296. rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
  297. rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
  298. rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
  299. rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
  300. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  301. GET_DURATION(ACK_SIZE, 20));
  302. rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
  303. rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
  304. rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
  305. rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
  306. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  307. GET_DURATION(ACK_SIZE, 55));
  308. rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
  309. rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
  310. rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
  311. rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
  312. rt2x00_set_field32(&reg, ARCSR2_LENGTH,
  313. GET_DURATION(ACK_SIZE, 110));
  314. rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
  315. }
  316. if (changed & BSS_CHANGED_BASIC_RATES)
  317. rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
  318. if (changed & BSS_CHANGED_ERP_SLOT) {
  319. rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
  320. rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
  321. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  322. rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
  323. rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
  324. rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
  325. rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
  326. rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
  327. rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
  328. rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
  329. rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
  330. }
  331. if (changed & BSS_CHANGED_BEACON_INT) {
  332. rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
  333. rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
  334. erp->beacon_int * 16);
  335. rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
  336. erp->beacon_int * 16);
  337. rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
  338. }
  339. }
  340. static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
  341. struct antenna_setup *ant)
  342. {
  343. u8 r1;
  344. u8 r4;
  345. /*
  346. * We should never come here because rt2x00lib is supposed
  347. * to catch this and send us the correct antenna explicitely.
  348. */
  349. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  350. ant->tx == ANTENNA_SW_DIVERSITY);
  351. rt2400pci_bbp_read(rt2x00dev, 4, &r4);
  352. rt2400pci_bbp_read(rt2x00dev, 1, &r1);
  353. /*
  354. * Configure the TX antenna.
  355. */
  356. switch (ant->tx) {
  357. case ANTENNA_HW_DIVERSITY:
  358. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
  359. break;
  360. case ANTENNA_A:
  361. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
  362. break;
  363. case ANTENNA_B:
  364. default:
  365. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
  366. break;
  367. }
  368. /*
  369. * Configure the RX antenna.
  370. */
  371. switch (ant->rx) {
  372. case ANTENNA_HW_DIVERSITY:
  373. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  374. break;
  375. case ANTENNA_A:
  376. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
  377. break;
  378. case ANTENNA_B:
  379. default:
  380. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  381. break;
  382. }
  383. rt2400pci_bbp_write(rt2x00dev, 4, r4);
  384. rt2400pci_bbp_write(rt2x00dev, 1, r1);
  385. }
  386. static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
  387. struct rf_channel *rf)
  388. {
  389. /*
  390. * Switch on tuning bits.
  391. */
  392. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
  393. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
  394. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  395. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  396. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  397. /*
  398. * RF2420 chipset don't need any additional actions.
  399. */
  400. if (rt2x00_rf(rt2x00dev, RF2420))
  401. return;
  402. /*
  403. * For the RT2421 chipsets we need to write an invalid
  404. * reference clock rate to activate auto_tune.
  405. * After that we set the value back to the correct channel.
  406. */
  407. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  408. rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
  409. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  410. msleep(1);
  411. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  412. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  413. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  414. msleep(1);
  415. /*
  416. * Switch off tuning bits.
  417. */
  418. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
  419. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
  420. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  421. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  422. /*
  423. * Clear false CRC during channel switch.
  424. */
  425. rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
  426. }
  427. static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
  428. {
  429. rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
  430. }
  431. static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  432. struct rt2x00lib_conf *libconf)
  433. {
  434. u32 reg;
  435. rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
  436. rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
  437. libconf->conf->long_frame_max_tx_count);
  438. rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
  439. libconf->conf->short_frame_max_tx_count);
  440. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  441. }
  442. static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
  443. struct rt2x00lib_conf *libconf)
  444. {
  445. enum dev_state state =
  446. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  447. STATE_SLEEP : STATE_AWAKE;
  448. u32 reg;
  449. if (state == STATE_SLEEP) {
  450. rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
  451. rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
  452. (rt2x00dev->beacon_int - 20) * 16);
  453. rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
  454. libconf->conf->listen_interval - 1);
  455. /* We must first disable autowake before it can be enabled */
  456. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  457. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  458. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
  459. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  460. } else {
  461. rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
  462. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  463. rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
  464. }
  465. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  466. }
  467. static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
  468. struct rt2x00lib_conf *libconf,
  469. const unsigned int flags)
  470. {
  471. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  472. rt2400pci_config_channel(rt2x00dev, &libconf->rf);
  473. if (flags & IEEE80211_CONF_CHANGE_POWER)
  474. rt2400pci_config_txpower(rt2x00dev,
  475. libconf->conf->power_level);
  476. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  477. rt2400pci_config_retry_limit(rt2x00dev, libconf);
  478. if (flags & IEEE80211_CONF_CHANGE_PS)
  479. rt2400pci_config_ps(rt2x00dev, libconf);
  480. }
  481. static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
  482. const int cw_min, const int cw_max)
  483. {
  484. u32 reg;
  485. rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
  486. rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
  487. rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
  488. rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
  489. }
  490. /*
  491. * Link tuning
  492. */
  493. static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
  494. struct link_qual *qual)
  495. {
  496. u32 reg;
  497. u8 bbp;
  498. /*
  499. * Update FCS error count from register.
  500. */
  501. rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
  502. qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
  503. /*
  504. * Update False CCA count from register.
  505. */
  506. rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
  507. qual->false_cca = bbp;
  508. }
  509. static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
  510. struct link_qual *qual, u8 vgc_level)
  511. {
  512. if (qual->vgc_level_reg != vgc_level) {
  513. rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
  514. qual->vgc_level = vgc_level;
  515. qual->vgc_level_reg = vgc_level;
  516. }
  517. }
  518. static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
  519. struct link_qual *qual)
  520. {
  521. rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
  522. }
  523. static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
  524. struct link_qual *qual, const u32 count)
  525. {
  526. /*
  527. * The link tuner should not run longer then 60 seconds,
  528. * and should run once every 2 seconds.
  529. */
  530. if (count > 60 || !(count & 1))
  531. return;
  532. /*
  533. * Base r13 link tuning on the false cca count.
  534. */
  535. if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
  536. rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
  537. else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
  538. rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
  539. }
  540. /*
  541. * Queue handlers.
  542. */
  543. static void rt2400pci_start_queue(struct data_queue *queue)
  544. {
  545. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  546. u32 reg;
  547. switch (queue->qid) {
  548. case QID_RX:
  549. rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
  550. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
  551. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  552. break;
  553. case QID_BEACON:
  554. rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
  555. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  556. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  557. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  558. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  559. break;
  560. default:
  561. break;
  562. }
  563. }
  564. static void rt2400pci_kick_queue(struct data_queue *queue)
  565. {
  566. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  567. u32 reg;
  568. switch (queue->qid) {
  569. case QID_AC_VO:
  570. rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
  571. rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
  572. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  573. break;
  574. case QID_AC_VI:
  575. rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
  576. rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
  577. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  578. break;
  579. case QID_ATIM:
  580. rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
  581. rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
  582. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  583. break;
  584. default:
  585. break;
  586. }
  587. }
  588. static void rt2400pci_stop_queue(struct data_queue *queue)
  589. {
  590. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  591. u32 reg;
  592. switch (queue->qid) {
  593. case QID_AC_VO:
  594. case QID_AC_VI:
  595. case QID_ATIM:
  596. rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
  597. rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
  598. rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
  599. break;
  600. case QID_RX:
  601. rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
  602. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
  603. rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
  604. break;
  605. case QID_BEACON:
  606. rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
  607. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
  608. rt2x00_set_field32(&reg, CSR14_TBCN, 0);
  609. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  610. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  611. /*
  612. * Wait for possibly running tbtt tasklets.
  613. */
  614. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  615. break;
  616. default:
  617. break;
  618. }
  619. }
  620. /*
  621. * Initialization functions.
  622. */
  623. static bool rt2400pci_get_entry_state(struct queue_entry *entry)
  624. {
  625. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  626. u32 word;
  627. if (entry->queue->qid == QID_RX) {
  628. rt2x00_desc_read(entry_priv->desc, 0, &word);
  629. return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
  630. } else {
  631. rt2x00_desc_read(entry_priv->desc, 0, &word);
  632. return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  633. rt2x00_get_field32(word, TXD_W0_VALID));
  634. }
  635. }
  636. static void rt2400pci_clear_entry(struct queue_entry *entry)
  637. {
  638. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  639. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  640. u32 word;
  641. if (entry->queue->qid == QID_RX) {
  642. rt2x00_desc_read(entry_priv->desc, 2, &word);
  643. rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
  644. rt2x00_desc_write(entry_priv->desc, 2, word);
  645. rt2x00_desc_read(entry_priv->desc, 1, &word);
  646. rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  647. rt2x00_desc_write(entry_priv->desc, 1, word);
  648. rt2x00_desc_read(entry_priv->desc, 0, &word);
  649. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  650. rt2x00_desc_write(entry_priv->desc, 0, word);
  651. } else {
  652. rt2x00_desc_read(entry_priv->desc, 0, &word);
  653. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  654. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  655. rt2x00_desc_write(entry_priv->desc, 0, word);
  656. }
  657. }
  658. static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
  659. {
  660. struct queue_entry_priv_mmio *entry_priv;
  661. u32 reg;
  662. /*
  663. * Initialize registers.
  664. */
  665. rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
  666. rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
  667. rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
  668. rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
  669. rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
  670. rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
  671. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  672. rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
  673. rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
  674. entry_priv->desc_dma);
  675. rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
  676. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  677. rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
  678. rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
  679. entry_priv->desc_dma);
  680. rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
  681. entry_priv = rt2x00dev->atim->entries[0].priv_data;
  682. rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
  683. rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
  684. entry_priv->desc_dma);
  685. rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
  686. entry_priv = rt2x00dev->bcn->entries[0].priv_data;
  687. rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
  688. rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
  689. entry_priv->desc_dma);
  690. rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
  691. rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
  692. rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
  693. rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
  694. rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
  695. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  696. rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
  697. rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
  698. entry_priv->desc_dma);
  699. rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
  700. return 0;
  701. }
  702. static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
  703. {
  704. u32 reg;
  705. rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
  706. rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
  707. rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
  708. rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
  709. rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
  710. rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
  711. rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
  712. rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
  713. rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
  714. rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
  715. rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
  716. (rt2x00dev->rx->data_size / 128));
  717. rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
  718. rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
  719. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
  720. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
  721. rt2x00_set_field32(&reg, CSR14_TBCN, 0);
  722. rt2x00_set_field32(&reg, CSR14_TCFP, 0);
  723. rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
  724. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  725. rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
  726. rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
  727. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  728. rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
  729. rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);
  730. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
  731. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
  732. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
  733. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
  734. rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
  735. rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
  736. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
  737. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
  738. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
  739. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
  740. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
  741. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
  742. rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
  743. rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
  744. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  745. return -EBUSY;
  746. rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
  747. rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
  748. rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
  749. rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
  750. rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
  751. rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
  752. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
  753. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
  754. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
  755. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
  756. rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
  757. rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
  758. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
  759. rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
  760. rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
  761. rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
  762. rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
  763. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
  764. rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
  765. rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
  766. /*
  767. * We must clear the FCS and FIFO error count.
  768. * These registers are cleared on read,
  769. * so we may pass a useless variable to store the value.
  770. */
  771. rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
  772. rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
  773. return 0;
  774. }
  775. static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  776. {
  777. unsigned int i;
  778. u8 value;
  779. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  780. rt2400pci_bbp_read(rt2x00dev, 0, &value);
  781. if ((value != 0xff) && (value != 0x00))
  782. return 0;
  783. udelay(REGISTER_BUSY_DELAY);
  784. }
  785. rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
  786. return -EACCES;
  787. }
  788. static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  789. {
  790. unsigned int i;
  791. u16 eeprom;
  792. u8 reg_id;
  793. u8 value;
  794. if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
  795. return -EACCES;
  796. rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
  797. rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
  798. rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
  799. rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
  800. rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
  801. rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
  802. rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
  803. rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
  804. rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
  805. rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
  806. rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
  807. rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
  808. rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
  809. rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
  810. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  811. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  812. if (eeprom != 0xffff && eeprom != 0x0000) {
  813. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  814. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  815. rt2400pci_bbp_write(rt2x00dev, reg_id, value);
  816. }
  817. }
  818. return 0;
  819. }
  820. /*
  821. * Device state switch handlers.
  822. */
  823. static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  824. enum dev_state state)
  825. {
  826. int mask = (state == STATE_RADIO_IRQ_OFF);
  827. u32 reg;
  828. unsigned long flags;
  829. /*
  830. * When interrupts are being enabled, the interrupt registers
  831. * should clear the register to assure a clean state.
  832. */
  833. if (state == STATE_RADIO_IRQ_ON) {
  834. rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
  835. rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
  836. }
  837. /*
  838. * Only toggle the interrupts bits we are going to use.
  839. * Non-checked interrupt bits are disabled by default.
  840. */
  841. spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
  842. rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
  843. rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
  844. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
  845. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
  846. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
  847. rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
  848. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  849. spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
  850. if (state == STATE_RADIO_IRQ_OFF) {
  851. /*
  852. * Ensure that all tasklets are finished before
  853. * disabling the interrupts.
  854. */
  855. tasklet_kill(&rt2x00dev->txstatus_tasklet);
  856. tasklet_kill(&rt2x00dev->rxdone_tasklet);
  857. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  858. }
  859. }
  860. static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  861. {
  862. /*
  863. * Initialize all registers.
  864. */
  865. if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
  866. rt2400pci_init_registers(rt2x00dev) ||
  867. rt2400pci_init_bbp(rt2x00dev)))
  868. return -EIO;
  869. return 0;
  870. }
  871. static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  872. {
  873. /*
  874. * Disable power
  875. */
  876. rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
  877. }
  878. static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
  879. enum dev_state state)
  880. {
  881. u32 reg, reg2;
  882. unsigned int i;
  883. char put_to_sleep;
  884. char bbp_state;
  885. char rf_state;
  886. put_to_sleep = (state != STATE_AWAKE);
  887. rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
  888. rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
  889. rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
  890. rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
  891. rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
  892. rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
  893. /*
  894. * Device is not guaranteed to be in the requested state yet.
  895. * We must wait until the register indicates that the
  896. * device has entered the correct state.
  897. */
  898. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  899. rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
  900. bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
  901. rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
  902. if (bbp_state == state && rf_state == state)
  903. return 0;
  904. rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
  905. msleep(10);
  906. }
  907. return -EBUSY;
  908. }
  909. static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  910. enum dev_state state)
  911. {
  912. int retval = 0;
  913. switch (state) {
  914. case STATE_RADIO_ON:
  915. retval = rt2400pci_enable_radio(rt2x00dev);
  916. break;
  917. case STATE_RADIO_OFF:
  918. rt2400pci_disable_radio(rt2x00dev);
  919. break;
  920. case STATE_RADIO_IRQ_ON:
  921. case STATE_RADIO_IRQ_OFF:
  922. rt2400pci_toggle_irq(rt2x00dev, state);
  923. break;
  924. case STATE_DEEP_SLEEP:
  925. case STATE_SLEEP:
  926. case STATE_STANDBY:
  927. case STATE_AWAKE:
  928. retval = rt2400pci_set_state(rt2x00dev, state);
  929. break;
  930. default:
  931. retval = -ENOTSUPP;
  932. break;
  933. }
  934. if (unlikely(retval))
  935. rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
  936. state, retval);
  937. return retval;
  938. }
  939. /*
  940. * TX descriptor initialization
  941. */
  942. static void rt2400pci_write_tx_desc(struct queue_entry *entry,
  943. struct txentry_desc *txdesc)
  944. {
  945. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  946. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  947. __le32 *txd = entry_priv->desc;
  948. u32 word;
  949. /*
  950. * Start writing the descriptor words.
  951. */
  952. rt2x00_desc_read(txd, 1, &word);
  953. rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  954. rt2x00_desc_write(txd, 1, word);
  955. rt2x00_desc_read(txd, 2, &word);
  956. rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
  957. rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
  958. rt2x00_desc_write(txd, 2, word);
  959. rt2x00_desc_read(txd, 3, &word);
  960. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
  961. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
  962. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
  963. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
  964. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
  965. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
  966. rt2x00_desc_write(txd, 3, word);
  967. rt2x00_desc_read(txd, 4, &word);
  968. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
  969. txdesc->u.plcp.length_low);
  970. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
  971. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
  972. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
  973. txdesc->u.plcp.length_high);
  974. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
  975. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
  976. rt2x00_desc_write(txd, 4, word);
  977. /*
  978. * Writing TXD word 0 must the last to prevent a race condition with
  979. * the device, whereby the device may take hold of the TXD before we
  980. * finished updating it.
  981. */
  982. rt2x00_desc_read(txd, 0, &word);
  983. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  984. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  985. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  986. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  987. rt2x00_set_field32(&word, TXD_W0_ACK,
  988. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  989. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  990. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  991. rt2x00_set_field32(&word, TXD_W0_RTS,
  992. test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
  993. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
  994. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  995. test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
  996. rt2x00_desc_write(txd, 0, word);
  997. /*
  998. * Register descriptor details in skb frame descriptor.
  999. */
  1000. skbdesc->desc = txd;
  1001. skbdesc->desc_len = TXD_DESC_SIZE;
  1002. }
  1003. /*
  1004. * TX data initialization
  1005. */
  1006. static void rt2400pci_write_beacon(struct queue_entry *entry,
  1007. struct txentry_desc *txdesc)
  1008. {
  1009. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1010. u32 reg;
  1011. /*
  1012. * Disable beaconing while we are reloading the beacon data,
  1013. * otherwise we might be sending out invalid data.
  1014. */
  1015. rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
  1016. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  1017. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  1018. if (rt2x00queue_map_txskb(entry)) {
  1019. rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
  1020. goto out;
  1021. }
  1022. /*
  1023. * Enable beaconing again.
  1024. */
  1025. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1026. /*
  1027. * Write the TX descriptor for the beacon.
  1028. */
  1029. rt2400pci_write_tx_desc(entry, txdesc);
  1030. /*
  1031. * Dump beacon to userspace through debugfs.
  1032. */
  1033. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
  1034. out:
  1035. /*
  1036. * Enable beaconing again.
  1037. */
  1038. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1039. rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
  1040. }
  1041. /*
  1042. * RX control handlers
  1043. */
  1044. static void rt2400pci_fill_rxdone(struct queue_entry *entry,
  1045. struct rxdone_entry_desc *rxdesc)
  1046. {
  1047. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1048. struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
  1049. u32 word0;
  1050. u32 word2;
  1051. u32 word3;
  1052. u32 word4;
  1053. u64 tsf;
  1054. u32 rx_low;
  1055. u32 rx_high;
  1056. rt2x00_desc_read(entry_priv->desc, 0, &word0);
  1057. rt2x00_desc_read(entry_priv->desc, 2, &word2);
  1058. rt2x00_desc_read(entry_priv->desc, 3, &word3);
  1059. rt2x00_desc_read(entry_priv->desc, 4, &word4);
  1060. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1061. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1062. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  1063. rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  1064. /*
  1065. * We only get the lower 32bits from the timestamp,
  1066. * to get the full 64bits we must complement it with
  1067. * the timestamp from get_tsf().
  1068. * Note that when a wraparound of the lower 32bits
  1069. * has occurred between the frame arrival and the get_tsf()
  1070. * call, we must decrease the higher 32bits with 1 to get
  1071. * to correct value.
  1072. */
  1073. tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
  1074. rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
  1075. rx_high = upper_32_bits(tsf);
  1076. if ((u32)tsf <= rx_low)
  1077. rx_high--;
  1078. /*
  1079. * Obtain the status about this packet.
  1080. * The signal is the PLCP value, and needs to be stripped
  1081. * of the preamble bit (0x08).
  1082. */
  1083. rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
  1084. rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
  1085. rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
  1086. entry->queue->rt2x00dev->rssi_offset;
  1087. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1088. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1089. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1090. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1091. }
  1092. /*
  1093. * Interrupt functions.
  1094. */
  1095. static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
  1096. const enum data_queue_qid queue_idx)
  1097. {
  1098. struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
  1099. struct queue_entry_priv_mmio *entry_priv;
  1100. struct queue_entry *entry;
  1101. struct txdone_entry_desc txdesc;
  1102. u32 word;
  1103. while (!rt2x00queue_empty(queue)) {
  1104. entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1105. entry_priv = entry->priv_data;
  1106. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1107. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1108. !rt2x00_get_field32(word, TXD_W0_VALID))
  1109. break;
  1110. /*
  1111. * Obtain the status about this packet.
  1112. */
  1113. txdesc.flags = 0;
  1114. switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
  1115. case 0: /* Success */
  1116. case 1: /* Success with retry */
  1117. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  1118. break;
  1119. case 2: /* Failure, excessive retries */
  1120. __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
  1121. /* Don't break, this is a failed frame! */
  1122. default: /* Failure */
  1123. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  1124. }
  1125. txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
  1126. rt2x00lib_txdone(entry, &txdesc);
  1127. }
  1128. }
  1129. static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
  1130. struct rt2x00_field32 irq_field)
  1131. {
  1132. u32 reg;
  1133. /*
  1134. * Enable a single interrupt. The interrupt mask register
  1135. * access needs locking.
  1136. */
  1137. spin_lock_irq(&rt2x00dev->irqmask_lock);
  1138. rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
  1139. rt2x00_set_field32(&reg, irq_field, 0);
  1140. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1141. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  1142. }
  1143. static void rt2400pci_txstatus_tasklet(unsigned long data)
  1144. {
  1145. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  1146. u32 reg;
  1147. /*
  1148. * Handle all tx queues.
  1149. */
  1150. rt2400pci_txdone(rt2x00dev, QID_ATIM);
  1151. rt2400pci_txdone(rt2x00dev, QID_AC_VO);
  1152. rt2400pci_txdone(rt2x00dev, QID_AC_VI);
  1153. /*
  1154. * Enable all TXDONE interrupts again.
  1155. */
  1156. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
  1157. spin_lock_irq(&rt2x00dev->irqmask_lock);
  1158. rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
  1159. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
  1160. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
  1161. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
  1162. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1163. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  1164. }
  1165. }
  1166. static void rt2400pci_tbtt_tasklet(unsigned long data)
  1167. {
  1168. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  1169. rt2x00lib_beacondone(rt2x00dev);
  1170. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1171. rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
  1172. }
  1173. static void rt2400pci_rxdone_tasklet(unsigned long data)
  1174. {
  1175. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  1176. if (rt2x00mmio_rxdone(rt2x00dev))
  1177. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  1178. else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1179. rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
  1180. }
  1181. static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
  1182. {
  1183. struct rt2x00_dev *rt2x00dev = dev_instance;
  1184. u32 reg, mask;
  1185. /*
  1186. * Get the interrupt sources & saved to local variable.
  1187. * Write register value back to clear pending interrupts.
  1188. */
  1189. rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
  1190. rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
  1191. if (!reg)
  1192. return IRQ_NONE;
  1193. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1194. return IRQ_HANDLED;
  1195. mask = reg;
  1196. /*
  1197. * Schedule tasklets for interrupt handling.
  1198. */
  1199. if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
  1200. tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
  1201. if (rt2x00_get_field32(reg, CSR7_RXDONE))
  1202. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  1203. if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
  1204. rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
  1205. rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
  1206. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  1207. /*
  1208. * Mask out all txdone interrupts.
  1209. */
  1210. rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
  1211. rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
  1212. rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
  1213. }
  1214. /*
  1215. * Disable all interrupts for which a tasklet was scheduled right now,
  1216. * the tasklet will reenable the appropriate interrupts.
  1217. */
  1218. spin_lock(&rt2x00dev->irqmask_lock);
  1219. rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
  1220. reg |= mask;
  1221. rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
  1222. spin_unlock(&rt2x00dev->irqmask_lock);
  1223. return IRQ_HANDLED;
  1224. }
  1225. /*
  1226. * Device probe functions.
  1227. */
  1228. static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1229. {
  1230. struct eeprom_93cx6 eeprom;
  1231. u32 reg;
  1232. u16 word;
  1233. u8 *mac;
  1234. rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
  1235. eeprom.data = rt2x00dev;
  1236. eeprom.register_read = rt2400pci_eepromregister_read;
  1237. eeprom.register_write = rt2400pci_eepromregister_write;
  1238. eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
  1239. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1240. eeprom.reg_data_in = 0;
  1241. eeprom.reg_data_out = 0;
  1242. eeprom.reg_data_clock = 0;
  1243. eeprom.reg_chip_select = 0;
  1244. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1245. EEPROM_SIZE / sizeof(u16));
  1246. /*
  1247. * Start validation of the data that has been read.
  1248. */
  1249. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1250. if (!is_valid_ether_addr(mac)) {
  1251. eth_random_addr(mac);
  1252. rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
  1253. }
  1254. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1255. if (word == 0xffff) {
  1256. rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
  1257. return -EINVAL;
  1258. }
  1259. return 0;
  1260. }
  1261. static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1262. {
  1263. u32 reg;
  1264. u16 value;
  1265. u16 eeprom;
  1266. /*
  1267. * Read EEPROM word for configuration.
  1268. */
  1269. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1270. /*
  1271. * Identify RF chipset.
  1272. */
  1273. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1274. rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
  1275. rt2x00_set_chip(rt2x00dev, RT2460, value,
  1276. rt2x00_get_field32(reg, CSR0_REVISION));
  1277. if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
  1278. rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
  1279. return -ENODEV;
  1280. }
  1281. /*
  1282. * Identify default antenna configuration.
  1283. */
  1284. rt2x00dev->default_ant.tx =
  1285. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1286. rt2x00dev->default_ant.rx =
  1287. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1288. /*
  1289. * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
  1290. * I am not 100% sure about this, but the legacy drivers do not
  1291. * indicate antenna swapping in software is required when
  1292. * diversity is enabled.
  1293. */
  1294. if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
  1295. rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
  1296. if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
  1297. rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
  1298. /*
  1299. * Store led mode, for correct led behaviour.
  1300. */
  1301. #ifdef CONFIG_RT2X00_LIB_LEDS
  1302. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1303. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1304. if (value == LED_MODE_TXRX_ACTIVITY ||
  1305. value == LED_MODE_DEFAULT ||
  1306. value == LED_MODE_ASUS)
  1307. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
  1308. LED_TYPE_ACTIVITY);
  1309. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1310. /*
  1311. * Detect if this device has an hardware controlled radio.
  1312. */
  1313. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1314. __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
  1315. /*
  1316. * Check if the BBP tuning should be enabled.
  1317. */
  1318. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
  1319. __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
  1320. return 0;
  1321. }
  1322. /*
  1323. * RF value list for RF2420 & RF2421
  1324. * Supports: 2.4 GHz
  1325. */
  1326. static const struct rf_channel rf_vals_b[] = {
  1327. { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
  1328. { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
  1329. { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
  1330. { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
  1331. { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
  1332. { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
  1333. { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
  1334. { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
  1335. { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
  1336. { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
  1337. { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
  1338. { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
  1339. { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
  1340. { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
  1341. };
  1342. static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1343. {
  1344. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1345. struct channel_info *info;
  1346. char *tx_power;
  1347. unsigned int i;
  1348. /*
  1349. * Initialize all hw fields.
  1350. */
  1351. rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1352. IEEE80211_HW_SIGNAL_DBM |
  1353. IEEE80211_HW_SUPPORTS_PS |
  1354. IEEE80211_HW_PS_NULLFUNC_STACK;
  1355. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  1356. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1357. rt2x00_eeprom_addr(rt2x00dev,
  1358. EEPROM_MAC_ADDR_0));
  1359. /*
  1360. * Initialize hw_mode information.
  1361. */
  1362. spec->supported_bands = SUPPORT_BAND_2GHZ;
  1363. spec->supported_rates = SUPPORT_RATE_CCK;
  1364. spec->num_channels = ARRAY_SIZE(rf_vals_b);
  1365. spec->channels = rf_vals_b;
  1366. /*
  1367. * Create channel information array
  1368. */
  1369. info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
  1370. if (!info)
  1371. return -ENOMEM;
  1372. spec->channels_info = info;
  1373. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1374. for (i = 0; i < 14; i++) {
  1375. info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
  1376. info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  1377. }
  1378. return 0;
  1379. }
  1380. static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1381. {
  1382. int retval;
  1383. u32 reg;
  1384. /*
  1385. * Allocate eeprom data.
  1386. */
  1387. retval = rt2400pci_validate_eeprom(rt2x00dev);
  1388. if (retval)
  1389. return retval;
  1390. retval = rt2400pci_init_eeprom(rt2x00dev);
  1391. if (retval)
  1392. return retval;
  1393. /*
  1394. * Enable rfkill polling by setting GPIO direction of the
  1395. * rfkill switch GPIO pin correctly.
  1396. */
  1397. rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
  1398. rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
  1399. rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
  1400. /*
  1401. * Initialize hw specifications.
  1402. */
  1403. retval = rt2400pci_probe_hw_mode(rt2x00dev);
  1404. if (retval)
  1405. return retval;
  1406. /*
  1407. * This device requires the atim queue and DMA-mapped skbs.
  1408. */
  1409. __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
  1410. __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
  1411. __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
  1412. /*
  1413. * Set the rssi offset.
  1414. */
  1415. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1416. return 0;
  1417. }
  1418. /*
  1419. * IEEE80211 stack callback functions.
  1420. */
  1421. static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
  1422. struct ieee80211_vif *vif, u16 queue,
  1423. const struct ieee80211_tx_queue_params *params)
  1424. {
  1425. struct rt2x00_dev *rt2x00dev = hw->priv;
  1426. /*
  1427. * We don't support variating cw_min and cw_max variables
  1428. * per queue. So by default we only configure the TX queue,
  1429. * and ignore all other configurations.
  1430. */
  1431. if (queue != 0)
  1432. return -EINVAL;
  1433. if (rt2x00mac_conf_tx(hw, vif, queue, params))
  1434. return -EINVAL;
  1435. /*
  1436. * Write configuration to register.
  1437. */
  1438. rt2400pci_config_cw(rt2x00dev,
  1439. rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
  1440. return 0;
  1441. }
  1442. static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
  1443. struct ieee80211_vif *vif)
  1444. {
  1445. struct rt2x00_dev *rt2x00dev = hw->priv;
  1446. u64 tsf;
  1447. u32 reg;
  1448. rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
  1449. tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
  1450. rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
  1451. tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
  1452. return tsf;
  1453. }
  1454. static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
  1455. {
  1456. struct rt2x00_dev *rt2x00dev = hw->priv;
  1457. u32 reg;
  1458. rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
  1459. return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
  1460. }
  1461. static const struct ieee80211_ops rt2400pci_mac80211_ops = {
  1462. .tx = rt2x00mac_tx,
  1463. .start = rt2x00mac_start,
  1464. .stop = rt2x00mac_stop,
  1465. .add_interface = rt2x00mac_add_interface,
  1466. .remove_interface = rt2x00mac_remove_interface,
  1467. .config = rt2x00mac_config,
  1468. .configure_filter = rt2x00mac_configure_filter,
  1469. .sw_scan_start = rt2x00mac_sw_scan_start,
  1470. .sw_scan_complete = rt2x00mac_sw_scan_complete,
  1471. .get_stats = rt2x00mac_get_stats,
  1472. .bss_info_changed = rt2x00mac_bss_info_changed,
  1473. .conf_tx = rt2400pci_conf_tx,
  1474. .get_tsf = rt2400pci_get_tsf,
  1475. .tx_last_beacon = rt2400pci_tx_last_beacon,
  1476. .rfkill_poll = rt2x00mac_rfkill_poll,
  1477. .flush = rt2x00mac_flush,
  1478. .set_antenna = rt2x00mac_set_antenna,
  1479. .get_antenna = rt2x00mac_get_antenna,
  1480. .get_ringparam = rt2x00mac_get_ringparam,
  1481. .tx_frames_pending = rt2x00mac_tx_frames_pending,
  1482. };
  1483. static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
  1484. .irq_handler = rt2400pci_interrupt,
  1485. .txstatus_tasklet = rt2400pci_txstatus_tasklet,
  1486. .tbtt_tasklet = rt2400pci_tbtt_tasklet,
  1487. .rxdone_tasklet = rt2400pci_rxdone_tasklet,
  1488. .probe_hw = rt2400pci_probe_hw,
  1489. .initialize = rt2x00mmio_initialize,
  1490. .uninitialize = rt2x00mmio_uninitialize,
  1491. .get_entry_state = rt2400pci_get_entry_state,
  1492. .clear_entry = rt2400pci_clear_entry,
  1493. .set_device_state = rt2400pci_set_device_state,
  1494. .rfkill_poll = rt2400pci_rfkill_poll,
  1495. .link_stats = rt2400pci_link_stats,
  1496. .reset_tuner = rt2400pci_reset_tuner,
  1497. .link_tuner = rt2400pci_link_tuner,
  1498. .start_queue = rt2400pci_start_queue,
  1499. .kick_queue = rt2400pci_kick_queue,
  1500. .stop_queue = rt2400pci_stop_queue,
  1501. .flush_queue = rt2x00mmio_flush_queue,
  1502. .write_tx_desc = rt2400pci_write_tx_desc,
  1503. .write_beacon = rt2400pci_write_beacon,
  1504. .fill_rxdone = rt2400pci_fill_rxdone,
  1505. .config_filter = rt2400pci_config_filter,
  1506. .config_intf = rt2400pci_config_intf,
  1507. .config_erp = rt2400pci_config_erp,
  1508. .config_ant = rt2400pci_config_ant,
  1509. .config = rt2400pci_config,
  1510. };
  1511. static void rt2400pci_queue_init(struct data_queue *queue)
  1512. {
  1513. switch (queue->qid) {
  1514. case QID_RX:
  1515. queue->limit = 24;
  1516. queue->data_size = DATA_FRAME_SIZE;
  1517. queue->desc_size = RXD_DESC_SIZE;
  1518. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1519. break;
  1520. case QID_AC_VO:
  1521. case QID_AC_VI:
  1522. case QID_AC_BE:
  1523. case QID_AC_BK:
  1524. queue->limit = 24;
  1525. queue->data_size = DATA_FRAME_SIZE;
  1526. queue->desc_size = TXD_DESC_SIZE;
  1527. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1528. break;
  1529. case QID_BEACON:
  1530. queue->limit = 1;
  1531. queue->data_size = MGMT_FRAME_SIZE;
  1532. queue->desc_size = TXD_DESC_SIZE;
  1533. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1534. break;
  1535. case QID_ATIM:
  1536. queue->limit = 8;
  1537. queue->data_size = DATA_FRAME_SIZE;
  1538. queue->desc_size = TXD_DESC_SIZE;
  1539. queue->priv_size = sizeof(struct queue_entry_priv_mmio);
  1540. break;
  1541. default:
  1542. BUG();
  1543. break;
  1544. }
  1545. }
  1546. static const struct rt2x00_ops rt2400pci_ops = {
  1547. .name = KBUILD_MODNAME,
  1548. .max_ap_intf = 1,
  1549. .eeprom_size = EEPROM_SIZE,
  1550. .rf_size = RF_SIZE,
  1551. .tx_queues = NUM_TX_QUEUES,
  1552. .queue_init = rt2400pci_queue_init,
  1553. .lib = &rt2400pci_rt2x00_ops,
  1554. .hw = &rt2400pci_mac80211_ops,
  1555. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1556. .debugfs = &rt2400pci_rt2x00debug,
  1557. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1558. };
  1559. /*
  1560. * RT2400pci module information.
  1561. */
  1562. static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
  1563. { PCI_DEVICE(0x1814, 0x0101) },
  1564. { 0, }
  1565. };
  1566. MODULE_AUTHOR(DRV_PROJECT);
  1567. MODULE_VERSION(DRV_VERSION);
  1568. MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
  1569. MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
  1570. MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
  1571. MODULE_LICENSE("GPL");
  1572. static int rt2400pci_probe(struct pci_dev *pci_dev,
  1573. const struct pci_device_id *id)
  1574. {
  1575. return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
  1576. }
  1577. static struct pci_driver rt2400pci_driver = {
  1578. .name = KBUILD_MODNAME,
  1579. .id_table = rt2400pci_device_table,
  1580. .probe = rt2400pci_probe,
  1581. .remove = rt2x00pci_remove,
  1582. .suspend = rt2x00pci_suspend,
  1583. .resume = rt2x00pci_resume,
  1584. };
  1585. module_pci_driver(rt2400pci_driver);