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/compiler/aarch64/aasmcpu.pas

https://github.com/slibre/freepascal
Pascal | 2178 lines | 656 code | 157 blank | 1365 comment | 24 complexity | ecb4854ef356f8e9d9ed85b01a664947 MD5 | raw file
Possible License(s): LGPL-2.0, LGPL-2.1, LGPL-3.0
  1. {
  2. Copyright (c) 2003-2012 by Florian Klaempfl and others
  3. Contains the assembler object for ARM64
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aasmcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. cclasses,globtype,globals,verbose,
  22. aasmbase,aasmtai,aasmdata,aasmsym,
  23. ogbase,
  24. symtype,
  25. cpubase,cpuinfo,cgbase,cgutils;
  26. const
  27. { "mov reg,reg" source operand number }
  28. O_MOV_SOURCE = 1;
  29. { "mov reg,reg" source operand number }
  30. O_MOV_DEST = 0;
  31. { Operand types }
  32. OT_NONE = $00000000;
  33. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  34. OT_BITS16 = $00000002;
  35. OT_BITS32 = $00000004;
  36. OT_BITS64 = $00000008; { FPU only }
  37. OT_BITS80 = $00000010;
  38. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  39. OT_NEAR = $00000040;
  40. OT_SHORT = $00000080;
  41. OT_BITSTINY = $00000100; { fpu constant }
  42. OT_BITSSHIFTER =
  43. $00000200;
  44. OT_SIZE_MASK = $000003FF; { all the size attributes }
  45. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  46. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  47. OT_TO = $00000200; { operand is followed by a colon }
  48. { reverse effect in FADD, FSUB &c }
  49. OT_COLON = $00000400;
  50. OT_SHIFTEROP = $00000800;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_REGLIST = $00008000;
  54. OT_IMM8 = $00002001;
  55. OT_IMM24 = $00002002;
  56. OT_IMM32 = $00002004;
  57. OT_IMM64 = $00002008;
  58. OT_IMM80 = $00002010;
  59. OT_IMMTINY = $00002100;
  60. OT_IMMSHIFTER= $00002200;
  61. OT_IMMEDIATE24 = OT_IMM24;
  62. OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
  63. OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
  64. OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
  65. OT_IMMEDIATEFPU = OT_IMMTINY;
  66. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  67. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  68. OT_REG8 = $00201001;
  69. OT_REG16 = $00201002;
  70. OT_REG32 = $00201004;
  71. OT_REG64 = $00201008;
  72. OT_VREG = $00201010; { vector register }
  73. OT_REGF = $00201020; { coproc register }
  74. OT_MEMORY = $00204000; { register number in 'basereg' }
  75. OT_MEM8 = $00204001;
  76. OT_MEM16 = $00204002;
  77. OT_MEM32 = $00204004;
  78. OT_MEM64 = $00204008;
  79. OT_MEM80 = $00204010;
  80. { word/byte load/store }
  81. OT_AM2 = $00010000;
  82. { misc ld/st operations }
  83. OT_AM3 = $00020000;
  84. { multiple ld/st operations }
  85. OT_AM4 = $00040000;
  86. { co proc. ld/st operations }
  87. OT_AM5 = $00080000;
  88. OT_AMMASK = $000f0000;
  89. { IT instruction }
  90. OT_CONDITION = $00100000;
  91. OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
  92. OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
  93. OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
  94. OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
  95. OT_FPUREG = $01000000; { floating point stack registers }
  96. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  97. { a mask for the following }
  98. OT_MEM_OFFS = $00604000; { special type of EA }
  99. { simple [address] offset }
  100. OT_ONENESS = $00800000; { special type of immediate operand }
  101. { so UNITY == IMMEDIATE | ONENESS }
  102. OT_UNITY = $00802000; { for shift/rotate instructions }
  103. instabentries = {$i a64nop.inc}
  104. maxinfolen = 5;
  105. IF_NONE = $00000000;
  106. IF_ARMMASK = $000F0000;
  107. IF_ARM7 = $00070000;
  108. IF_FPMASK = $00F00000;
  109. IF_FPA = $00100000;
  110. { if the instruction can change in a second pass }
  111. IF_PASS2 = longint($80000000);
  112. type
  113. TInsTabCache=array[TasmOp] of longint;
  114. PInsTabCache=^TInsTabCache;
  115. tinsentry = record
  116. opcode : tasmop;
  117. ops : byte;
  118. optypes : array[0..3] of longint;
  119. code : array[0..maxinfolen] of char;
  120. flags : longint;
  121. end;
  122. pinsentry=^tinsentry;
  123. { const
  124. InsTab : array[0..instabentries-1] of TInsEntry={$i a64tab.inc} }
  125. var
  126. InsTabCache : PInsTabCache;
  127. type
  128. taicpu = class(tai_cpu_abstract_sym)
  129. oppostfix : TOpPostfix;
  130. procedure loadshifterop(opidx:longint;const so:tshifterop);
  131. constructor op_none(op : tasmop);
  132. constructor op_reg(op : tasmop;_op1 : tregister);
  133. constructor op_ref(op : tasmop;const _op1 : treference);
  134. constructor op_const(op : tasmop;_op1 : longint);
  135. constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  136. constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  137. constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  138. constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  139. constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  140. constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  141. constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  142. constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  143. constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  144. constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  145. { this is for Jmp instructions }
  146. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  147. constructor op_sym(op : tasmop;_op1 : tasmsymbol);
  148. constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  149. constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  150. constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  151. function is_same_reg_move(regtype: Tregistertype):boolean; override;
  152. function spilling_get_operation_type(opnr: longint): topertype;override;
  153. { assembler }
  154. public
  155. { the next will reset all instructions that can change in pass 2 }
  156. procedure ResetPass1;override;
  157. procedure ResetPass2;override;
  158. function CheckIfValid:boolean;
  159. function GetString:string;
  160. function Pass1(objdata:TObjData):longint;override;
  161. procedure Pass2(objdata:TObjData);override;
  162. protected
  163. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  164. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  165. procedure ppubuildderefimploper(var o:toper);override;
  166. procedure ppuderefoper(var o:toper);override;
  167. private
  168. { next fields are filled in pass1, so pass2 is faster }
  169. inssize : shortint;
  170. insoffset : longint;
  171. LastInsOffset : longint; { need to be public to be reset }
  172. insentry : PInsEntry;
  173. function InsEnd:longint;
  174. procedure create_ot(objdata:TObjData);
  175. function Matches(p:PInsEntry):longint;
  176. function calcsize(p:PInsEntry):shortint;
  177. procedure gencode(objdata:TObjData);
  178. function NeedAddrPrefix(opidx:byte):boolean;
  179. procedure Swapoperands;
  180. function FindInsentry(objdata:TObjData):boolean;
  181. end;
  182. tai_align = class(tai_align_abstract)
  183. { nothing to add }
  184. end;
  185. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  186. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  187. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  188. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  189. { inserts pc relative symbols at places where they are reachable
  190. and transforms special instructions to valid instruction encodings }
  191. procedure finalizearmcode(list,listtoinsert : TAsmList);
  192. { inserts .pdata section and dummy function prolog needed for arm-wince exception handling }
  193. procedure InsertPData;
  194. procedure InitAsm;
  195. procedure DoneAsm;
  196. implementation
  197. uses
  198. cutils,rgobj,itcpugas,aoptcpu;
  199. procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
  200. begin
  201. allocate_oper(opidx+1);
  202. with oper[opidx]^ do
  203. begin
  204. if typ<>top_shifterop then
  205. begin
  206. clearop(opidx);
  207. new(shifterop);
  208. end;
  209. shifterop^:=so;
  210. typ:=top_shifterop;
  211. end;
  212. end;
  213. {*****************************************************************************
  214. taicpu Constructors
  215. *****************************************************************************}
  216. constructor taicpu.op_none(op : tasmop);
  217. begin
  218. inherited create(op);
  219. end;
  220. { for pld }
  221. constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
  222. begin
  223. inherited create(op);
  224. ops:=1;
  225. loadref(0,_op1);
  226. end;
  227. constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
  228. begin
  229. inherited create(op);
  230. ops:=1;
  231. loadreg(0,_op1);
  232. end;
  233. constructor taicpu.op_const(op : tasmop;_op1 : longint);
  234. begin
  235. inherited create(op);
  236. ops:=1;
  237. loadconst(0,aint(_op1));
  238. end;
  239. constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  240. begin
  241. inherited create(op);
  242. ops:=2;
  243. loadreg(0,_op1);
  244. loadreg(1,_op2);
  245. end;
  246. constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  247. begin
  248. inherited create(op);
  249. ops:=2;
  250. loadreg(0,_op1);
  251. loadconst(1,aint(_op2));
  252. end;
  253. constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  254. begin
  255. inherited create(op);
  256. ops:=2;
  257. loadreg(0,_op1);
  258. loadref(1,_op2);
  259. end;
  260. constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  261. begin
  262. inherited create(op);
  263. ops:=3;
  264. loadreg(0,_op1);
  265. loadreg(1,_op2);
  266. loadreg(2,_op3);
  267. end;
  268. constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  269. begin
  270. inherited create(op);
  271. ops:=4;
  272. loadreg(0,_op1);
  273. loadreg(1,_op2);
  274. loadreg(2,_op3);
  275. loadreg(3,_op4);
  276. end;
  277. constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  278. begin
  279. inherited create(op);
  280. ops:=3;
  281. loadreg(0,_op1);
  282. loadreg(1,_op2);
  283. loadconst(2,aint(_op3));
  284. end;
  285. constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  286. begin
  287. inherited create(op);
  288. ops:=3;
  289. loadreg(0,_op1);
  290. loadreg(1,_op2);
  291. loadsymbol(0,_op3,_op3ofs);
  292. end;
  293. constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  294. begin
  295. inherited create(op);
  296. ops:=3;
  297. loadreg(0,_op1);
  298. loadreg(1,_op2);
  299. loadref(2,_op3);
  300. end;
  301. constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  302. begin
  303. inherited create(op);
  304. ops:=3;
  305. loadreg(0,_op1);
  306. loadreg(1,_op2);
  307. loadshifterop(2,_op3);
  308. end;
  309. constructor taicpu.op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  310. begin
  311. inherited create(op);
  312. ops:=4;
  313. loadreg(0,_op1);
  314. loadreg(1,_op2);
  315. loadreg(2,_op3);
  316. loadshifterop(3,_op4);
  317. end;
  318. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  319. begin
  320. inherited create(op);
  321. condition:=cond;
  322. ops:=1;
  323. loadsymbol(0,_op1,0);
  324. end;
  325. constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
  326. begin
  327. inherited create(op);
  328. ops:=1;
  329. loadsymbol(0,_op1,0);
  330. end;
  331. constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  332. begin
  333. inherited create(op);
  334. ops:=1;
  335. loadsymbol(0,_op1,_op1ofs);
  336. end;
  337. constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  338. begin
  339. inherited create(op);
  340. ops:=2;
  341. loadreg(0,_op1);
  342. loadsymbol(1,_op2,_op2ofs);
  343. end;
  344. constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  345. begin
  346. inherited create(op);
  347. ops:=2;
  348. loadsymbol(0,_op1,_op1ofs);
  349. loadref(1,_op2);
  350. end;
  351. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  352. begin
  353. { allow the register allocator to remove unnecessary moves }
  354. result:=(
  355. ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
  356. ((opcode=A_FMOV) and (regtype = R_MMREGISTER))
  357. ) and
  358. (oppostfix in [PF_None]) and
  359. (condition=C_None) and
  360. (ops=2) and
  361. (oper[0]^.typ=top_reg) and
  362. (oper[1]^.typ=top_reg) and
  363. (oper[0]^.reg=oper[1]^.reg);
  364. end;
  365. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  366. var
  367. op: tasmop;
  368. begin
  369. case getregtype(r) of
  370. R_INTREGISTER :
  371. result:=taicpu.op_reg_ref(A_LDR,r,ref);
  372. R_MMREGISTER :
  373. begin
  374. case getsubreg(r) of
  375. R_SUBFD:
  376. op:=A_LDR;
  377. R_SUBFS:
  378. op:=A_LDR;
  379. else
  380. internalerror(2009112905);
  381. end;
  382. result:=taicpu.op_reg_ref(op,r,ref);
  383. end;
  384. else
  385. internalerror(200401041);
  386. end;
  387. end;
  388. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  389. var
  390. op: tasmop;
  391. begin
  392. case getregtype(r) of
  393. R_INTREGISTER :
  394. result:=taicpu.op_reg_ref(A_STR,r,ref);
  395. R_MMREGISTER :
  396. begin
  397. case getsubreg(r) of
  398. R_SUBFD:
  399. op:=A_STR;
  400. R_SUBFS:
  401. op:=A_STR;
  402. else
  403. internalerror(2009112904);
  404. end;
  405. result:=taicpu.op_reg_ref(op,r,ref);
  406. end;
  407. else
  408. internalerror(200401041);
  409. end;
  410. end;
  411. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  412. begin
  413. case opcode of
  414. A_ADC,A_ADD,A_AND,A_BIC,
  415. A_EOR,A_CLZ,A_RBIT,
  416. A_LDR,
  417. A_MOV,A_MVN,A_MUL,
  418. A_ORR,A_SBC,A_SUB,
  419. A_UXT,A_SXT:
  420. if opnr=0 then
  421. result:=operand_write
  422. else
  423. result:=operand_read;
  424. A_B,A_BL,
  425. A_CMN,A_CMP,A_TST:
  426. result:=operand_read;
  427. A_STR:
  428. { important is what happens with the involved registers }
  429. if opnr=0 then
  430. result := operand_read
  431. else
  432. { check for pre/post indexed }
  433. result := operand_read;
  434. else
  435. internalerror(200403151);
  436. end;
  437. end;
  438. procedure BuildInsTabCache;
  439. var
  440. i : longint;
  441. begin
  442. (* new(instabcache);
  443. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  444. i:=0;
  445. while (i<InsTabEntries) do
  446. begin
  447. if InsTabCache^[InsTab[i].Opcode]=-1 then
  448. InsTabCache^[InsTab[i].Opcode]:=i;
  449. inc(i);
  450. end; *)
  451. end;
  452. procedure InitAsm;
  453. begin
  454. if not assigned(instabcache) then
  455. BuildInsTabCache;
  456. end;
  457. procedure DoneAsm;
  458. begin
  459. if assigned(instabcache) then
  460. begin
  461. dispose(instabcache);
  462. instabcache:=nil;
  463. end;
  464. end;
  465. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  466. begin
  467. i.oppostfix:=pf;
  468. result:=i;
  469. end;
  470. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  471. begin
  472. i.condition:=c;
  473. result:=i;
  474. end;
  475. Function SimpleGetNextInstruction(Current: tai; Var Next: tai): Boolean;
  476. Begin
  477. Current:=tai(Current.Next);
  478. While Assigned(Current) And (Current.typ In SkipInstr) Do
  479. Current:=tai(Current.Next);
  480. Next:=Current;
  481. If Assigned(Next) And Not(Next.typ In SkipInstr) Then
  482. Result:=True
  483. Else
  484. Begin
  485. Next:=Nil;
  486. Result:=False;
  487. End;
  488. End;
  489. (*
  490. function armconstequal(hp1,hp2: tai): boolean;
  491. begin
  492. result:=false;
  493. if hp1.typ<>hp2.typ then
  494. exit;
  495. case hp1.typ of
  496. tai_const:
  497. result:=
  498. (tai_const(hp2).sym=tai_const(hp).sym) and
  499. (tai_const(hp2).value=tai_const(hp).value) and
  500. (tai(hp2.previous).typ=ait_label);
  501. tai_const:
  502. result:=
  503. (tai_const(hp2).sym=tai_const(hp).sym) and
  504. (tai_const(hp2).value=tai_const(hp).value) and
  505. (tai(hp2.previous).typ=ait_label);
  506. end;
  507. end;
  508. *)
  509. procedure insertpcrelativedata(list,listtoinsert : TAsmList);
  510. var
  511. curinspos,
  512. penalty,
  513. lastinspos,
  514. { increased for every data element > 4 bytes inserted }
  515. currentsize,
  516. extradataoffset,
  517. limit: longint;
  518. curop : longint;
  519. curtai : tai;
  520. curdatatai,hp,hp2 : tai;
  521. curdata : TAsmList;
  522. l : tasmlabel;
  523. doinsert,
  524. removeref : boolean;
  525. begin
  526. (*
  527. curdata:=TAsmList.create;
  528. lastinspos:=-1;
  529. curinspos:=0;
  530. extradataoffset:=0;
  531. limit:=1016;
  532. curtai:=tai(list.first);
  533. doinsert:=false;
  534. while assigned(curtai) do
  535. begin
  536. { instruction? }
  537. case curtai.typ of
  538. ait_instruction:
  539. begin
  540. { walk through all operand of the instruction }
  541. for curop:=0 to taicpu(curtai).ops-1 do
  542. begin
  543. { reference? }
  544. if (taicpu(curtai).oper[curop]^.typ=top_ref) then
  545. begin
  546. { pc relative symbol? }
  547. curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
  548. if assigned(curdatatai) and
  549. { move only if we're at the first reference of a label }
  550. not(tai_label(curdatatai).moved) then
  551. begin
  552. tai_label(curdatatai).moved:=true;
  553. { check if symbol already used. }
  554. { if yes, reuse the symbol }
  555. hp:=tai(curdatatai.next);
  556. removeref:=false;
  557. if assigned(hp) then
  558. begin
  559. case hp.typ of
  560. ait_const:
  561. begin
  562. if (tai_const(hp).consttype=aitconst_64bit) then
  563. inc(extradataoffset);
  564. end;
  565. ait_comp_64bit,
  566. ait_real_64bit:
  567. begin
  568. inc(extradataoffset);
  569. end;
  570. ait_real_80bit:
  571. begin
  572. inc(extradataoffset,2);
  573. end;
  574. end;
  575. if (hp.typ=ait_const) then
  576. begin
  577. hp2:=tai(curdata.first);
  578. while assigned(hp2) do
  579. begin
  580. { if armconstequal(hp2,hp) then }
  581. if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
  582. and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
  583. then
  584. begin
  585. with taicpu(curtai).oper[curop]^.ref^ do
  586. begin
  587. symboldata:=hp2.previous;
  588. symbol:=tai_label(hp2.previous).labsym;
  589. end;
  590. removeref:=true;
  591. break;
  592. end;
  593. hp2:=tai(hp2.next);
  594. end;
  595. end;
  596. end;
  597. { move or remove symbol reference }
  598. repeat
  599. hp:=tai(curdatatai.next);
  600. listtoinsert.remove(curdatatai);
  601. if removeref then
  602. curdatatai.free
  603. else
  604. curdata.concat(curdatatai);
  605. curdatatai:=hp;
  606. until (curdatatai=nil) or (curdatatai.typ=ait_label);
  607. if lastinspos=-1 then
  608. lastinspos:=curinspos;
  609. end;
  610. end;
  611. end;
  612. inc(curinspos);
  613. end;
  614. ait_align:
  615. begin
  616. { code is always 4 byte aligned, so we don't have to take care of .align 2 which would
  617. requires also incrementing curinspos by 1 }
  618. inc(curinspos,(tai_align(curtai).aligntype div 4));
  619. end;
  620. ait_const:
  621. begin
  622. inc(curinspos);
  623. if (tai_const(curtai).consttype=aitconst_64bit) then
  624. inc(curinspos);
  625. end;
  626. ait_real_32bit:
  627. begin
  628. inc(curinspos);
  629. end;
  630. ait_comp_64bit,
  631. ait_real_64bit:
  632. begin
  633. inc(curinspos,2);
  634. end;
  635. ait_real_80bit:
  636. begin
  637. inc(curinspos,3);
  638. end;
  639. end;
  640. { special case for case jump tables }
  641. if SimpleGetNextInstruction(curtai,hp) and
  642. (tai(hp).typ=ait_instruction) and
  643. (taicpu(hp).opcode=A_LDR) and
  644. (taicpu(hp).oper[0]^.typ=top_reg) and
  645. (taicpu(hp).oper[0]^.reg=NR_PC) then
  646. begin
  647. penalty:=1;
  648. hp:=tai(hp.next);
  649. { skip register allocations and comments inserted by the optimizer }
  650. while assigned(hp) and (hp.typ in [ait_comment,ait_regalloc]) do
  651. hp:=tai(hp.next);
  652. while assigned(hp) and (hp.typ=ait_const) do
  653. begin
  654. inc(penalty);
  655. hp:=tai(hp.next);
  656. end;
  657. end
  658. else
  659. penalty:=0;
  660. { FLD/FST VFP instructions have a limit of +/- 1024, not 4096 }
  661. if SimpleGetNextInstruction(curtai,hp) and
  662. (tai(hp).typ=ait_instruction) and
  663. ((taicpu(hp).opcode=A_FLDS) or
  664. (taicpu(hp).opcode=A_FLDD)) then
  665. limit:=254;
  666. { don't miss an insert }
  667. doinsert:=doinsert or
  668. (not(curdata.empty) and
  669. (curinspos-lastinspos+penalty+extradataoffset>limit));
  670. { split only at real instructions else the test below fails }
  671. if doinsert and (curtai.typ=ait_instruction) and
  672. (
  673. { don't split loads of pc to lr and the following move }
  674. not(
  675. (taicpu(curtai).opcode=A_MOV) and
  676. (taicpu(curtai).oper[0]^.typ=top_reg) and
  677. (taicpu(curtai).oper[0]^.reg=NR_R14) and
  678. (taicpu(curtai).oper[1]^.typ=top_reg) and
  679. (taicpu(curtai).oper[1]^.reg=NR_PC)
  680. )
  681. ) then
  682. begin
  683. lastinspos:=-1;
  684. extradataoffset:=0;
  685. limit:=1016;
  686. doinsert:=false;
  687. hp:=tai(curtai.next);
  688. current_asmdata.getjumplabel(l);
  689. curdata.insert(taicpu.op_sym(A_B,l));
  690. curdata.concat(tai_label.create(l));
  691. list.insertlistafter(curtai,curdata);
  692. curtai:=hp;
  693. end
  694. else
  695. curtai:=tai(curtai.next);
  696. end;
  697. list.concatlist(curdata);
  698. curdata.free;
  699. *)
  700. end;
  701. procedure finalizearmcode(list, listtoinsert: TAsmList);
  702. begin
  703. insertpcrelativedata(list, listtoinsert);
  704. end;
  705. procedure InsertPData;
  706. var
  707. prolog: TAsmList;
  708. begin
  709. prolog:=TAsmList.create;
  710. new_section(prolog,sec_code,'FPC_EH_PROLOG',sizeof(pint),secorder_begin);
  711. prolog.concat(Tai_const.Createname('_ARM_ExceptionHandler', 0));
  712. prolog.concat(Tai_const.Create_32bit(0));
  713. prolog.concat(Tai_symbol.Createname_global('FPC_EH_CODE_START',AT_DATA,0));
  714. { dummy function }
  715. prolog.concat(taicpu.op_reg(A_BR,NR_X29));
  716. current_asmdata.asmlists[al_start].insertList(prolog);
  717. prolog.Free;
  718. new_section(current_asmdata.asmlists[al_end],sec_pdata,'',sizeof(pint));
  719. current_asmdata.asmlists[al_end].concat(Tai_const.Createname('FPC_EH_CODE_START', 0));
  720. current_asmdata.asmlists[al_end].concat(Tai_const.Create_32bit(longint($ffffff01)));
  721. end;
  722. (*
  723. Floating point instruction format information, taken from the linux kernel
  724. ARM Floating Point Instruction Classes
  725. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  726. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  727. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  728. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  729. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  730. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  731. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  732. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  733. CPDT data transfer instructions
  734. LDF, STF, LFM (copro 2), SFM (copro 2)
  735. CPDO dyadic arithmetic instructions
  736. ADF, MUF, SUF, RSF, DVF, RDF,
  737. POW, RPW, RMF, FML, FDV, FRD, POL
  738. CPDO monadic arithmetic instructions
  739. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  740. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  741. CPRT joint arithmetic/data transfer instructions
  742. FIX (arithmetic followed by load/store)
  743. FLT (load/store followed by arithmetic)
  744. CMF, CNF CMFE, CNFE (comparisons)
  745. WFS, RFS (write/read floating point status register)
  746. WFC, RFC (write/read floating point control register)
  747. cond condition codes
  748. P pre/post index bit: 0 = postindex, 1 = preindex
  749. U up/down bit: 0 = stack grows down, 1 = stack grows up
  750. W write back bit: 1 = update base register (Rn)
  751. L load/store bit: 0 = store, 1 = load
  752. Rn base register
  753. Rd destination/source register
  754. Fd floating point destination register
  755. Fn floating point source register
  756. Fm floating point source register or floating point constant
  757. uv transfer length (TABLE 1)
  758. wx register count (TABLE 2)
  759. abcd arithmetic opcode (TABLES 3 & 4)
  760. ef destination size (rounding precision) (TABLE 5)
  761. gh rounding mode (TABLE 6)
  762. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  763. i constant bit: 1 = constant (TABLE 6)
  764. */
  765. /*
  766. TABLE 1
  767. +-------------------------+---+---+---------+---------+
  768. | Precision | u | v | FPSR.EP | length |
  769. +-------------------------+---+---+---------+---------+
  770. | Single | 0 | 0 | x | 1 words |
  771. | Double | 1 | 1 | x | 2 words |
  772. | Extended | 1 | 1 | x | 3 words |
  773. | Packed decimal | 1 | 1 | 0 | 3 words |
  774. | Expanded packed decimal | 1 | 1 | 1 | 4 words |
  775. +-------------------------+---+---+---------+---------+
  776. Note: x = don't care
  777. */
  778. /*
  779. TABLE 2
  780. +---+---+---------------------------------+
  781. | w | x | Number of registers to transfer |
  782. +---+---+---------------------------------+
  783. | 0 | 1 | 1 |
  784. | 1 | 0 | 2 |
  785. | 1 | 1 | 3 |
  786. | 0 | 0 | 4 |
  787. +---+---+---------------------------------+
  788. */
  789. /*
  790. TABLE 3: Dyadic Floating Point Opcodes
  791. +---+---+---+---+----------+-----------------------+-----------------------+
  792. | a | b | c | d | Mnemonic | Description | Operation |
  793. +---+---+---+---+----------+-----------------------+-----------------------+
  794. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  795. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  796. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  797. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  798. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  799. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  800. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  801. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  802. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  803. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  804. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  805. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  806. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  807. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  808. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  809. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  810. +---+---+---+---+----------+-----------------------+-----------------------+
  811. Note: POW, RPW, POL are deprecated, and are available for backwards
  812. compatibility only.
  813. */
  814. /*
  815. TABLE 4: Monadic Floating Point Opcodes
  816. +---+---+---+---+----------+-----------------------+-----------------------+
  817. | a | b | c | d | Mnemonic | Description | Operation |
  818. +---+---+---+---+----------+-----------------------+-----------------------+
  819. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  820. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  821. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  822. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  823. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  824. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  825. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  826. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  827. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  828. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  829. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  830. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  831. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  832. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  833. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  834. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  835. +---+---+---+---+----------+-----------------------+-----------------------+
  836. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  837. available for backwards compatibility only.
  838. */
  839. /*
  840. TABLE 5
  841. +-------------------------+---+---+
  842. | Rounding Precision | e | f |
  843. +-------------------------+---+---+
  844. | IEEE Single precision | 0 | 0 |
  845. | IEEE Double precision | 0 | 1 |
  846. | IEEE Extended precision | 1 | 0 |
  847. | undefined (trap) | 1 | 1 |
  848. +-------------------------+---+---+
  849. */
  850. /*
  851. TABLE 5
  852. +---------------------------------+---+---+
  853. | Rounding Mode | g | h |
  854. +---------------------------------+---+---+
  855. | Round to nearest (default) | 0 | 0 |
  856. | Round toward plus infinity | 0 | 1 |
  857. | Round toward negative infinity | 1 | 0 |
  858. | Round toward zero | 1 | 1 |
  859. +---------------------------------+---+---+
  860. *)
  861. function taicpu.GetString:string;
  862. var
  863. i : longint;
  864. s : string;
  865. addsize : boolean;
  866. begin
  867. s:='['+gas_op2str[opcode];
  868. for i:=0 to ops-1 do
  869. begin
  870. with oper[i]^ do
  871. begin
  872. if i=0 then
  873. s:=s+' '
  874. else
  875. s:=s+',';
  876. { type }
  877. addsize:=false;
  878. if (ot and OT_VREG)=OT_VREG then
  879. s:=s+'vreg'
  880. else
  881. if (ot and OT_FPUREG)=OT_FPUREG then
  882. s:=s+'fpureg'
  883. else
  884. if (ot and OT_REGISTER)=OT_REGISTER then
  885. begin
  886. s:=s+'reg';
  887. addsize:=true;
  888. end
  889. else
  890. if (ot and OT_REGLIST)=OT_REGLIST then
  891. begin
  892. s:=s+'reglist';
  893. addsize:=false;
  894. end
  895. else
  896. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  897. begin
  898. s:=s+'imm';
  899. addsize:=true;
  900. end
  901. else
  902. if (ot and OT_MEMORY)=OT_MEMORY then
  903. begin
  904. s:=s+'mem';
  905. addsize:=true;
  906. if (ot and OT_AM2)<>0 then
  907. s:=s+' am2 ';
  908. end
  909. else
  910. s:=s+'???';
  911. { size }
  912. if addsize then
  913. begin
  914. if (ot and OT_BITS8)<>0 then
  915. s:=s+'8'
  916. else
  917. if (ot and OT_BITS16)<>0 then
  918. s:=s+'24'
  919. else
  920. if (ot and OT_BITS32)<>0 then
  921. s:=s+'32'
  922. else
  923. if (ot and OT_BITSSHIFTER)<>0 then
  924. s:=s+'shifter'
  925. else
  926. s:=s+'??';
  927. { signed }
  928. if (ot and OT_SIGNED)<>0 then
  929. s:=s+'s';
  930. end;
  931. end;
  932. end;
  933. GetString:=s+']';
  934. end;
  935. procedure taicpu.ResetPass1;
  936. begin
  937. { we need to reset everything here, because the choosen insentry
  938. can be invalid for a new situation where the previously optimized
  939. insentry is not correct }
  940. InsEntry:=nil;
  941. InsSize:=0;
  942. LastInsOffset:=-1;
  943. end;
  944. procedure taicpu.ResetPass2;
  945. begin
  946. { we are here in a second pass, check if the instruction can be optimized }
  947. if assigned(InsEntry) and
  948. ((InsEntry^.flags and IF_PASS2)<>0) then
  949. begin
  950. InsEntry:=nil;
  951. InsSize:=0;
  952. end;
  953. LastInsOffset:=-1;
  954. end;
  955. function taicpu.CheckIfValid:boolean;
  956. begin
  957. Result:=False; { unimplemented }
  958. end;
  959. function taicpu.Pass1(objdata:TObjData):longint;
  960. begin
  961. Pass1:=0;
  962. LastInsOffset:=-1;
  963. end;
  964. procedure taicpu.Pass2(objdata:TObjData);
  965. begin
  966. { error in pass1 ? }
  967. if insentry=nil then
  968. exit;
  969. current_filepos:=fileinfo;
  970. { Generate the instruction }
  971. GenCode(objdata);
  972. end;
  973. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  974. begin
  975. end;
  976. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  977. begin
  978. end;
  979. procedure taicpu.ppubuildderefimploper(var o:toper);
  980. begin
  981. end;
  982. procedure taicpu.ppuderefoper(var o:toper);
  983. begin
  984. end;
  985. function taicpu.InsEnd:longint;
  986. begin
  987. Result:=0; { unimplemented }
  988. end;
  989. procedure taicpu.create_ot(objdata:TObjData);
  990. begin
  991. end;
  992. function taicpu.Matches(p:PInsEntry):longint;
  993. begin
  994. end;
  995. function taicpu.calcsize(p:PInsEntry):shortint;
  996. begin
  997. result:=4;
  998. end;
  999. function taicpu.NeedAddrPrefix(opidx:byte):boolean;
  1000. begin
  1001. Result:=False; { unimplemented }
  1002. end;
  1003. procedure taicpu.Swapoperands;
  1004. begin
  1005. end;
  1006. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1007. begin
  1008. end;
  1009. procedure taicpu.gencode(objdata:TObjData);
  1010. var
  1011. bytes : dword;
  1012. i_field : byte;
  1013. procedure setshifterop(op : byte);
  1014. begin
  1015. case oper[op]^.typ of
  1016. top_const:
  1017. begin
  1018. i_field:=1;
  1019. bytes:=bytes or dword(oper[op]^.val and $fff);
  1020. end;
  1021. top_reg:
  1022. begin
  1023. i_field:=0;
  1024. bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
  1025. { does a real shifter op follow? }
  1026. if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
  1027. begin
  1028. end;
  1029. end;
  1030. else
  1031. internalerror(2005091103);
  1032. end;
  1033. end;
  1034. begin
  1035. bytes:=$0;
  1036. { evaluate and set condition code }
  1037. { condition code allowed? }
  1038. { setup rest of the instruction }
  1039. case insentry^.code[0] of
  1040. #$08:
  1041. begin
  1042. { set instruction code }
  1043. bytes:=bytes or (ord(insentry^.code[1]) shl 26);
  1044. bytes:=bytes or (ord(insentry^.code[2]) shl 21);
  1045. { set destination }
  1046. bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
  1047. { create shifter op }
  1048. setshifterop(1);
  1049. { set i field }
  1050. bytes:=bytes or (i_field shl 25);
  1051. { set s if necessary }
  1052. if oppostfix=PF_S then
  1053. bytes:=bytes or (1 shl 20);
  1054. end;
  1055. #$ff:
  1056. internalerror(2005091101);
  1057. else
  1058. internalerror(2005091102);
  1059. end;
  1060. { we're finished, write code }
  1061. objdata.writebytes(bytes,sizeof(bytes));
  1062. end;
  1063. {$ifdef dummy}
  1064. (*
  1065. static void gencode (long segment, long offset, int bits,
  1066. insn *ins, char *codes, long insn_end)
  1067. {
  1068. int has_S_code; /* S - setflag */
  1069. int has_B_code; /* B - setflag */
  1070. int has_T_code; /* T - setflag */
  1071. int has_W_code; /* ! => W flag */
  1072. int has_F_code; /* ^ => S flag */
  1073. int keep;
  1074. unsigned char c;
  1075. unsigned char bytes[4];
  1076. long data, size;
  1077. static int cc_code[] = /* bit pattern of cc */
  1078. { /* order as enum in */
  1079. 0x0E, 0x03, 0x02, 0x00, /* nasm.h */
  1080. 0x0A, 0x0C, 0x08, 0x0D,
  1081. 0x09, 0x0B, 0x04, 0x01,
  1082. 0x05, 0x07, 0x06,
  1083. };
  1084. #ifdef DEBUG
  1085. static char *CC[] =
  1086. { /* condition code names */
  1087. "AL", "CC", "CS", "EQ",
  1088. "GE", "GT", "HI", "LE",
  1089. "LS", "LT", "MI", "NE",
  1090. "PL", "VC", "VS", "",
  1091. "S"
  1092. };
  1093. has_S_code = (ins->condition & C_SSETFLAG);
  1094. has_B_code = (ins->condition & C_BSETFLAG);
  1095. has_T_code = (ins->condition & C_TSETFLAG);
  1096. has_W_code = (ins->condition & C_EXSETFLAG);
  1097. has_F_code = (ins->condition & C_FSETFLAG);
  1098. ins->condition = (ins->condition & 0x0F);
  1099. if (rt_debug)
  1100. {
  1101. printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
  1102. CC[ins->condition & 0x0F]);
  1103. if (has_S_code)
  1104. printf ("S");
  1105. if (has_B_code)
  1106. printf ("B");
  1107. if (has_T_code)
  1108. printf ("T");
  1109. if (has_W_code)
  1110. printf ("!");
  1111. if (has_F_code)
  1112. printf ("^");
  1113. printf ("\n");
  1114. c = *codes;
  1115. printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
  1116. bytes[0] = 0xB;
  1117. bytes[1] = 0xE;
  1118. bytes[2] = 0xE;
  1119. bytes[3] = 0xF;
  1120. }
  1121. // First condition code in upper nibble
  1122. if (ins->condition < C_NONE)
  1123. {
  1124. c = cc_code[ins->condition] << 4;
  1125. }
  1126. else
  1127. {
  1128. c = cc_code[C_AL] << 4; // is often ALWAYS but not always
  1129. }
  1130. switch (keep = *codes)
  1131. {
  1132. case 1:
  1133. // B, BL
  1134. ++codes;
  1135. c |= *codes++;
  1136. bytes[0] = c;
  1137. if (ins->oprs[0].segment != segment)
  1138. {
  1139. // fais une relocation
  1140. c = 1;
  1141. data = 0; // Let the linker locate ??
  1142. }
  1143. else
  1144. {
  1145. c = 0;
  1146. data = ins->oprs[0].offset - (offset + 8);
  1147. if (data % 4)
  1148. {
  1149. errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
  1150. }
  1151. }
  1152. if (data >= 0x1000)
  1153. {
  1154. errfunc (ERR_NONFATAL, "too long offset");
  1155. }
  1156. data = data >> 2;
  1157. bytes[1] = (data >> 16) & 0xFF;
  1158. bytes[2] = (data >> 8) & 0xFF;
  1159. bytes[3] = (data ) & 0xFF;
  1160. if (c == 1)
  1161. {
  1162. // out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
  1163. out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
  1164. }
  1165. else
  1166. {
  1167. out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1168. }
  1169. return;
  1170. case 2:
  1171. // SWI
  1172. ++codes;
  1173. c |= *codes++;
  1174. bytes[0] = c;
  1175. data = ins->oprs[0].offset;
  1176. bytes[1] = (data >> 16) & 0xFF;
  1177. bytes[2] = (data >> 8) & 0xFF;
  1178. bytes[3] = (data) & 0xFF;
  1179. out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1180. return;
  1181. case 3:
  1182. // BX
  1183. ++codes;
  1184. c |= *codes++;
  1185. bytes[0] = c;
  1186. bytes[1] = *codes++;
  1187. bytes[2] = *codes++;
  1188. bytes[3] = *codes++;
  1189. c = regval (&ins->oprs[0],1);
  1190. if (c == 15) // PC
  1191. {
  1192. errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
  1193. }
  1194. else if (c > 15)
  1195. {
  1196. errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
  1197. }
  1198. bytes[3] |= (c & 0x0F);
  1199. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1200. return;
  1201. case 4: // AND Rd,Rn,Rm
  1202. case 5: // AND Rd,Rn,Rm,<shift>Rs
  1203. case 6: // AND Rd,Rn,Rm,<shift>imm
  1204. case 7: // AND Rd,Rn,<shift>imm
  1205. ++codes;
  1206. #ifdef DEBUG
  1207. if (rt_debug)
  1208. {
  1209. printf (" decode - '0x%02X'\n", keep);
  1210. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1211. }
  1212. #endif
  1213. bytes[0] = c | *codes;
  1214. ++codes;
  1215. bytes[1] = *codes;
  1216. if (has_S_code)
  1217. bytes[1] |= 0x10;
  1218. c = regval (&ins->oprs[1],1);
  1219. // Rn in low nibble
  1220. bytes[1] |= c;
  1221. // Rd in high nibble
  1222. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1223. if (keep != 7)
  1224. {
  1225. // Rm in low nibble
  1226. bytes[3] = regval (&ins->oprs[2],1);
  1227. }
  1228. // Shifts if any
  1229. if (keep == 5 || keep == 6)
  1230. {
  1231. // Shift in bytes 2 and 3
  1232. if (keep == 5)
  1233. {
  1234. // Rs
  1235. c = regval (&ins->oprs[3],1);
  1236. bytes[2] |= c;
  1237. c = 0x10; // Set bit 4 in byte[3]
  1238. }
  1239. if (keep == 6)
  1240. {
  1241. c = (ins->oprs[3].offset) & 0x1F;
  1242. // #imm
  1243. bytes[2] |= c >> 1;
  1244. if (c & 0x01)
  1245. {
  1246. bytes[3] |= 0x80;
  1247. }
  1248. c = 0; // Clr bit 4 in byte[3]
  1249. }
  1250. // <shift>
  1251. c |= shiftval (&ins->oprs[3]) << 5;
  1252. bytes[3] |= c;
  1253. }
  1254. // reg,reg,imm
  1255. if (keep == 7)
  1256. {
  1257. int shimm;
  1258. shimm = imm_shift (ins->oprs[2].offset);
  1259. if (shimm == -1)
  1260. {
  1261. errfunc (ERR_NONFATAL, "cannot create that constant");
  1262. }
  1263. bytes[3] = shimm & 0xFF;
  1264. bytes[2] |= (shimm & 0xF00) >> 8;
  1265. }
  1266. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1267. return;
  1268. case 8: // MOV Rd,Rm
  1269. case 9: // MOV Rd,Rm,<shift>Rs
  1270. case 0xA: // MOV Rd,Rm,<shift>imm
  1271. case 0xB: // MOV Rd,<shift>imm
  1272. ++codes;
  1273. #ifdef DEBUG
  1274. if (rt_debug)
  1275. {
  1276. printf (" decode - '0x%02X'\n", keep);
  1277. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1278. }
  1279. #endif
  1280. bytes[0] = c | *codes;
  1281. ++codes;
  1282. bytes[1] = *codes;
  1283. if (has_S_code)
  1284. bytes[1] |= 0x10;
  1285. // Rd in high nibble
  1286. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1287. if (keep != 0x0B)
  1288. {
  1289. // Rm in low nibble
  1290. bytes[3] = regval (&ins->oprs[1],1);
  1291. }
  1292. // Shifts if any
  1293. if (keep == 0x09 || keep == 0x0A)
  1294. {
  1295. // Shift in bytes 2 and 3
  1296. if (keep == 0x09)
  1297. {
  1298. // Rs
  1299. c = regval (&ins->oprs[2],1);
  1300. bytes[2] |= c;
  1301. c = 0x10; // Set bit 4 in byte[3]
  1302. }
  1303. if (keep == 0x0A)
  1304. {
  1305. c = (ins->oprs[2].offset) & 0x1F;
  1306. // #imm
  1307. bytes[2] |= c >> 1;
  1308. if (c & 0x01)
  1309. {
  1310. bytes[3] |= 0x80;
  1311. }
  1312. c = 0; // Clr bit 4 in byte[3]
  1313. }
  1314. // <shift>
  1315. c |= shiftval (&ins->oprs[2]) << 5;
  1316. bytes[3] |= c;
  1317. }
  1318. // reg,imm
  1319. if (keep == 0x0B)
  1320. {
  1321. int shimm;
  1322. shimm = imm_shift (ins->oprs[1].offset);
  1323. if (shimm == -1)
  1324. {
  1325. errfunc (ERR_NONFATAL, "cannot create that constant");
  1326. }
  1327. bytes[3] = shimm & 0xFF;
  1328. bytes[2] |= (shimm & 0xF00) >> 8;
  1329. }
  1330. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1331. return;
  1332. case 0xC: // CMP Rn,Rm
  1333. case 0xD: // CMP Rn,Rm,<shift>Rs
  1334. case 0xE: // CMP Rn,Rm,<shift>imm
  1335. case 0xF: // CMP Rn,<shift>imm
  1336. ++codes;
  1337. bytes[0] = c | *codes++;
  1338. bytes[1] = *codes;
  1339. // Implicit S code
  1340. bytes[1] |= 0x10;
  1341. c = regval (&ins->oprs[0],1);
  1342. // Rn in low nibble
  1343. bytes[1] |= c;
  1344. // No destination
  1345. bytes[2] = 0;
  1346. if (keep != 0x0B)
  1347. {
  1348. // Rm in low nibble
  1349. bytes[3] = regval (&ins->oprs[1],1);
  1350. }
  1351. // Shifts if any
  1352. if (keep == 0x0D || keep == 0x0E)
  1353. {
  1354. // Shift in bytes 2 and 3
  1355. if (keep == 0x0D)
  1356. {
  1357. // Rs
  1358. c = regval (&ins->oprs[2],1);
  1359. bytes[2] |= c;
  1360. c = 0x10; // Set bit 4 in byte[3]
  1361. }
  1362. if (keep == 0x0E)
  1363. {
  1364. c = (ins->oprs[2].offset) & 0x1F;
  1365. // #imm
  1366. bytes[2] |= c >> 1;
  1367. if (c & 0x01)
  1368. {
  1369. bytes[3] |= 0x80;
  1370. }
  1371. c = 0; // Clr bit 4 in byte[3]
  1372. }
  1373. // <shift>
  1374. c |= shiftval (&ins->oprs[2]) << 5;
  1375. bytes[3] |= c;
  1376. }
  1377. // reg,imm
  1378. if (keep == 0x0F)
  1379. {
  1380. int shimm;
  1381. shimm = imm_shift (ins->oprs[1].offset);
  1382. if (shimm == -1)
  1383. {
  1384. errfunc (ERR_NONFATAL, "cannot create that constant");
  1385. }
  1386. bytes[3] = shimm & 0xFF;
  1387. bytes[2] |= (shimm & 0xF00) >> 8;
  1388. }
  1389. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1390. return;
  1391. case 0x10: // MRS Rd,<psr>
  1392. ++codes;
  1393. bytes[0] = c | *codes++;
  1394. bytes[1] = *codes++;
  1395. // Rd
  1396. c = regval (&ins->oprs[0],1);
  1397. bytes[2] = c << 4;
  1398. bytes[3] = 0;
  1399. c = ins->oprs[1].basereg;
  1400. if (c == R_CPSR || c == R_SPSR)
  1401. {
  1402. if (c == R_SPSR)
  1403. {
  1404. bytes[1] |= 0x40;
  1405. }
  1406. }
  1407. else
  1408. {
  1409. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1410. }
  1411. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1412. return;
  1413. case 0x11: // MSR <psr>,Rm
  1414. case 0x12: // MSR <psrf>,Rm
  1415. case 0x13: // MSR <psrf>,#expression
  1416. ++codes;
  1417. bytes[0] = c | *codes++;
  1418. bytes[1] = *codes++;
  1419. bytes[2] = *codes;
  1420. if (keep == 0x11 || keep == 0x12)
  1421. {
  1422. // Rm
  1423. c = regval (&ins->oprs[1],1);
  1424. bytes[3] = c;
  1425. }
  1426. else
  1427. {
  1428. int shimm;
  1429. shimm = imm_shift (ins->oprs[1].offset);
  1430. if (shimm == -1)
  1431. {
  1432. errfunc (ERR_NONFATAL, "cannot create that constant");
  1433. }
  1434. bytes[3] = shimm & 0xFF;
  1435. bytes[2] |= (shimm & 0xF00) >> 8;
  1436. }
  1437. c = ins->oprs[0].basereg;
  1438. if ( keep == 0x11)
  1439. {
  1440. if ( c == R_CPSR || c == R_SPSR)
  1441. {
  1442. if ( c== R_SPSR)
  1443. {
  1444. bytes[1] |= 0x40;
  1445. }
  1446. }
  1447. else
  1448. {
  1449. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1450. }
  1451. }
  1452. else
  1453. {
  1454. if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
  1455. {
  1456. if ( c== R_SPSR_FLG)
  1457. {
  1458. bytes[1] |= 0x40;
  1459. }
  1460. }
  1461. else
  1462. {
  1463. errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
  1464. }
  1465. }
  1466. break;
  1467. case 0x14: // MUL Rd,Rm,Rs
  1468. case 0x15: // MULA Rd,Rm,Rs,Rn
  1469. ++codes;
  1470. bytes[0] = c | *codes++;
  1471. bytes[1] = *codes++;
  1472. bytes[3] = *codes;
  1473. // Rd
  1474. bytes[1] |= regval (&ins->oprs[0],1);
  1475. if (has_S_code)
  1476. bytes[1] |= 0x10;
  1477. // Rm
  1478. bytes[3] |= regval (&ins->oprs[1],1);
  1479. // Rs
  1480. bytes[2] = regval (&ins->oprs[2],1);
  1481. if (keep == 0x15)
  1482. {
  1483. bytes[2] |= regval (&ins->oprs[3],1) << 4;
  1484. }
  1485. break;
  1486. case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
  1487. ++codes;
  1488. bytes[0] = c | *codes++;
  1489. bytes[1] = *codes++;
  1490. bytes[3] = *codes;
  1491. // RdHi
  1492. bytes[1] |= regval (&ins->oprs[1],1);
  1493. if (has_S_code)
  1494. bytes[1] |= 0x10;
  1495. // RdLo
  1496. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1497. // Rm
  1498. bytes[3] |= regval (&ins->oprs[2],1);
  1499. // Rs
  1500. bytes[2] |= regval (&ins->oprs[3],1);
  1501. break;
  1502. case 0x17: // LDR Rd, expression
  1503. ++codes;
  1504. bytes[0] = c | *codes++;
  1505. bytes[1] = *codes++;
  1506. // Rd
  1507. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1508. if (has_B_code)
  1509. bytes[1] |= 0x40;
  1510. if (has_T_code)
  1511. {
  1512. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  1513. }
  1514. if (has_W_code)
  1515. {
  1516. errfunc (ERR_NONFATAL, "'!' not allowed");
  1517. }
  1518. // Rn - implicit R15
  1519. bytes[1] |= 0xF;
  1520. if (ins->oprs[1].segment != segment)
  1521. {
  1522. errfunc (ERR_NONFATAL, "label not in same segment");
  1523. }
  1524. data = ins->oprs[1].offset - (offset + 8);
  1525. if (data < 0)
  1526. {
  1527. data = -data;
  1528. }
  1529. else
  1530. {
  1531. bytes[1] |= 0x80;
  1532. }
  1533. if (data >= 0x1000)
  1534. {
  1535. errfunc (ERR_NONFATAL, "too long offset");
  1536. }
  1537. bytes[2] |= ((data & 0xF00) >> 8);
  1538. bytes[3] = data & 0xFF;
  1539. break;
  1540. case 0x18: // LDR Rd, [Rn]
  1541. ++codes;
  1542. bytes[0] = c | *codes++;
  1543. bytes[1] = *codes++;
  1544. // Rd
  1545. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1546. if (has_B_code)
  1547. bytes[1] |= 0x40;
  1548. if (has_T_code)
  1549. {
  1550. bytes[1] |= 0x20; // write-back
  1551. }
  1552. else
  1553. {
  1554. bytes[0] |= 0x01; // implicit pre-index mode
  1555. }
  1556. if (has_W_code)
  1557. {
  1558. bytes[1] |= 0x20; // write-back
  1559. }
  1560. // Rn
  1561. c = regval (&ins->oprs[1],1);
  1562. bytes[1] |= c;
  1563. if (c == 0x15) // R15
  1564. data = -8;
  1565. else
  1566. data = 0;
  1567. if (data < 0)
  1568. {
  1569. data = -data;
  1570. }
  1571. else
  1572. {
  1573. bytes[1] |= 0x80;
  1574. }
  1575. bytes[2] |= ((data & 0xF00) >> 8);
  1576. bytes[3] = data & 0xFF;
  1577. break;
  1578. case 0x19: // LDR Rd, [Rn,#expression]
  1579. case 0x20: // LDR Rd, [Rn,Rm]
  1580. case 0x21: // LDR Rd, [Rn,Rm,shift]
  1581. ++codes;
  1582. bytes[0] = c | *codes++;
  1583. bytes[1] = *codes++;
  1584. // Rd
  1585. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1586. if (has_B_code)
  1587. bytes[1] |= 0x40;
  1588. // Rn
  1589. c = regval (&ins->oprs[1],1);
  1590. bytes[1] |= c;
  1591. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  1592. {
  1593. bytes[0] |= 0x01; // pre-index mode
  1594. if (has_W_code)
  1595. {
  1596. bytes[1] |= 0x20;
  1597. }
  1598. if (has_T_code)
  1599. {
  1600. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  1601. }
  1602. }
  1603. else
  1604. {
  1605. if (has_T_code) // Forced write-back in post-index mode
  1606. {
  1607. bytes[1] |= 0x20;
  1608. }
  1609. if (has_W_code)
  1610. {
  1611. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  1612. }
  1613. }
  1614. if (keep == 0x19)
  1615. {
  1616. data = ins->oprs[2].offset;
  1617. if (data < 0)
  1618. {
  1619. data = -data;
  1620. }
  1621. else
  1622. {
  1623. bytes[1] |= 0x80;
  1624. }
  1625. if (data >= 0x1000)
  1626. {
  1627. errfunc (ERR_NONFATAL, "too long offset");
  1628. }
  1629. bytes[2] |= ((data & 0xF00) >> 8);
  1630. bytes[3] = data & 0xFF;
  1631. }
  1632. else
  1633. {
  1634. if (ins->oprs[2].minus == 0)
  1635. {
  1636. bytes[1] |= 0x80;
  1637. }
  1638. c = regval (&ins->oprs[2],1);
  1639. bytes[3] = c;
  1640. if (keep == 0x21)
  1641. {
  1642. c = ins->oprs[3].offset;
  1643. if (c > 0x1F)
  1644. {
  1645. errfunc (ERR_NONFATAL, "too large shiftvalue");
  1646. c = c & 0x1F;
  1647. }
  1648. bytes[2] |= c >> 1;
  1649. if (c & 0x01)
  1650. {
  1651. bytes[3] |= 0x80;
  1652. }
  1653. bytes[3] |= shiftval (&ins->oprs[3]) << 5;
  1654. }
  1655. }
  1656. break;
  1657. case 0x22: // LDRH Rd, expression
  1658. ++codes;
  1659. bytes[0] = c | 0x01; // Implicit pre-index
  1660. bytes[1] = *codes++;
  1661. // Rd
  1662. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1663. // Rn - implicit R15
  1664. bytes[1] |= 0xF;
  1665. if (ins->oprs[1].segment != segment)
  1666. {
  1667. errfunc (ERR_NONFATAL, "label not in same segment");
  1668. }
  1669. data = ins->oprs[1].offset - (offset + 8);
  1670. if (data < 0)
  1671. {
  1672. data = -data;
  1673. }
  1674. else
  1675. {
  1676. bytes[1] |= 0x80;
  1677. }
  1678. if (data >= 0x100)
  1679. {
  1680. errfunc (ERR_NONFATAL, "too long offset");
  1681. }
  1682. bytes[3] = *codes++;
  1683. bytes[2] |= ((data & 0xF0) >> 4);
  1684. bytes[3] |= data & 0xF;
  1685. break;
  1686. case 0x23: // LDRH Rd, Rn
  1687. ++codes;
  1688. bytes[0] = c | 0x01; // Implicit pre-index
  1689. bytes[1] = *codes++;
  1690. // Rd
  1691. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1692. // Rn
  1693. c = regval (&ins->oprs[1],1);
  1694. bytes[1] |= c;
  1695. if (c == 0x15) // R15
  1696. data = -8;
  1697. else
  1698. data = 0;
  1699. if (data < 0)
  1700. {
  1701. data = -data;
  1702. }
  1703. else
  1704. {
  1705. bytes[1] |= 0x80;
  1706. }
  1707. if (data >= 0x100)
  1708. {
  1709. errfunc (ERR_NONFATAL, "too long offset");
  1710. }
  1711. bytes[3] = *codes++;
  1712. bytes[2] |= ((data & 0xF0) >> 4);
  1713. bytes[3] |= data & 0xF;
  1714. break;
  1715. case 0x24: // LDRH Rd, Rn, expression
  1716. case 0x25: // LDRH Rd, Rn, Rm
  1717. ++codes;
  1718. bytes[0] = c;
  1719. bytes[1] = *codes++;
  1720. // Rd
  1721. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1722. // Rn
  1723. c = regval (&ins->oprs[1],1);
  1724. bytes[1] |= c;
  1725. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  1726. {
  1727. bytes[0] |= 0x01; // pre-index mode
  1728. if (has_W_code)
  1729. {
  1730. bytes[1] |= 0x20;
  1731. }
  1732. }
  1733. else
  1734. {
  1735. if (has_W_code)
  1736. {
  1737. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  1738. }
  1739. }
  1740. bytes[3] = *codes++;
  1741. if (keep == 0x24)
  1742. {
  1743. data = ins->oprs[2].offset;
  1744. if (data < 0)
  1745. {
  1746. data = -data;
  1747. }
  1748. else
  1749. {
  1750. bytes[1] |= 0x80;
  1751. }
  1752. if (data >= 0x100)
  1753. {
  1754. errfunc (ERR_NONFATAL, "too long offset");
  1755. }
  1756. bytes[2] |= ((data & 0xF0) >> 4);
  1757. bytes[3] |= data & 0xF;
  1758. }
  1759. else
  1760. {
  1761. if (ins->oprs[2].minus == 0)
  1762. {
  1763. bytes[1] |= 0x80;
  1764. }
  1765. c = regval (&ins->oprs[2],1);
  1766. bytes[3] |= c;
  1767. }
  1768. break;
  1769. case 0x26: // LDM/STM Rn, {reg-list}
  1770. ++codes;
  1771. bytes[0] = c;
  1772. bytes[0] |= ( *codes >> 4) & 0xF;
  1773. bytes[1] = ( *codes << 4) & 0xF0;
  1774. ++codes;
  1775. if (has_W_code)
  1776. {
  1777. bytes[1] |= 0x20;
  1778. }
  1779. if (has_F_code)
  1780. {
  1781. bytes[1] |= 0x40;
  1782. }
  1783. // Rn
  1784. bytes[1] |= regval (&ins->oprs[0],1);
  1785. data = ins->oprs[1].basereg;
  1786. bytes[2] = ((data >> 8) & 0xFF);
  1787. bytes[3] = (data & 0xFF);
  1788. break;
  1789. case 0x27: // SWP Rd, Rm, [Rn]
  1790. ++codes;
  1791. bytes[0] = c;
  1792. bytes[0] |= *codes++;
  1793. bytes[1] = regval (&ins->oprs[2],1);
  1794. if (has_B_code)
  1795. {
  1796. bytes[1] |= 0x40;
  1797. }
  1798. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1799. bytes[3] = *codes++;
  1800. bytes[3] |= regval (&ins->oprs[1],1);
  1801. break;
  1802. default:
  1803. errfunc (ERR_FATAL, "unknown decoding of instruction");
  1804. bytes[0] = c;
  1805. // And a fix nibble
  1806. ++codes;
  1807. bytes[0] |= *codes++;
  1808. if ( *codes == 0x01) // An I bit
  1809. {
  1810. }
  1811. if ( *codes == 0x02) // An I bit
  1812. {
  1813. }
  1814. ++codes;
  1815. }
  1816. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1817. }
  1818. *)
  1819. {$endif dummy}
  1820. begin
  1821. cai_align:=tai_align;
  1822. end.