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/Ethereal-msm8939-beta9/arch/metag/include/asm/tbx.h

https://bitbucket.org/MilosStamenkovic95/etherealos
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Possible License(s): GPL-2.0
  1. /*
  2. * asm/tbx.h
  3. *
  4. * Copyright (C) 2000-2012 Imagination Technologies.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it under
  7. * the terms of the GNU General Public License version 2 as published by the
  8. * Free Software Foundation.
  9. *
  10. * Thread binary interface header
  11. */
  12. #ifndef _ASM_METAG_TBX_H_
  13. #define _ASM_METAG_TBX_H_
  14. /* for CACHEW_* values */
  15. #include <asm/metag_isa.h>
  16. /* for LINSYSEVENT_* addresses */
  17. #include <asm/metag_mem.h>
  18. #ifdef TBI_1_4
  19. #ifndef TBI_MUTEXES_1_4
  20. #define TBI_MUTEXES_1_4
  21. #endif
  22. #ifndef TBI_SEMAPHORES_1_4
  23. #define TBI_SEMAPHORES_1_4
  24. #endif
  25. #ifndef TBI_ASYNC_SWITCH_1_4
  26. #define TBI_ASYNC_SWITCH_1_4
  27. #endif
  28. #ifndef TBI_FASTINT_1_4
  29. #define TBI_FASTINT_1_4
  30. #endif
  31. #endif
  32. /* Id values in the TBI system describe a segment using an arbitrary
  33. integer value and flags in the bottom 8 bits, the SIGPOLL value is
  34. used in cases where control over blocking or polling behaviour is
  35. needed. */
  36. #define TBID_SIGPOLL_BIT 0x02 /* Set bit in an Id value to poll vs block */
  37. /* Extended segment identifiers use strings in the string table */
  38. #define TBID_IS_SEGSTR( Id ) (((Id) & (TBID_SEGTYPE_BITS>>1)) == 0)
  39. /* Segment identifiers contain the following related bit-fields */
  40. #define TBID_SEGTYPE_BITS 0x0F /* One of the predefined segment types */
  41. #define TBID_SEGTYPE_S 0
  42. #define TBID_SEGSCOPE_BITS 0x30 /* Indicates the scope of the segment */
  43. #define TBID_SEGSCOPE_S 4
  44. #define TBID_SEGGADDR_BITS 0xC0 /* Indicates access possible via pGAddr */
  45. #define TBID_SEGGADDR_S 6
  46. /* Segments of memory can only really contain a few types of data */
  47. #define TBID_SEGTYPE_TEXT 0x02 /* Code segment */
  48. #define TBID_SEGTYPE_DATA 0x04 /* Data segment */
  49. #define TBID_SEGTYPE_STACK 0x06 /* Stack segment */
  50. #define TBID_SEGTYPE_HEAP 0x0A /* Heap segment */
  51. #define TBID_SEGTYPE_ROOT 0x0C /* Root block segments */
  52. #define TBID_SEGTYPE_STRING 0x0E /* String table segment */
  53. /* Segments have one of three possible scopes */
  54. #define TBID_SEGSCOPE_INIT 0 /* Temporary area for initialisation phase */
  55. #define TBID_SEGSCOPE_LOCAL 1 /* Private to this thread */
  56. #define TBID_SEGSCOPE_GLOBAL 2 /* Shared globally throughout the system */
  57. #define TBID_SEGSCOPE_SHARED 3 /* Limited sharing between local/global */
  58. /* For segment specifier a further field in two of the remaining bits
  59. indicates the usefulness of the pGAddr field in the segment descriptor
  60. descriptor. */
  61. #define TBID_SEGGADDR_NULL 0 /* pGAddr is NULL -> SEGSCOPE_(LOCAL|INIT) */
  62. #define TBID_SEGGADDR_READ 1 /* Only read via pGAddr */
  63. #define TBID_SEGGADDR_WRITE 2 /* Full access via pGAddr */
  64. #define TBID_SEGGADDR_EXEC 3 /* Only execute via pGAddr */
  65. /* The following values are common to both segment and signal Id value and
  66. live in the top 8 bits of the Id values. */
  67. /* The ISTAT bit indicates if segments are related to interrupt vs
  68. background level interfaces a thread can still handle all triggers at
  69. either level, but can also split these up if it wants to. */
  70. #define TBID_ISTAT_BIT 0x01000000
  71. #define TBID_ISTAT_S 24
  72. /* Privilege needed to access a segment is indicated by the next bit.
  73. This bit is set to mirror the current privilege level when starting a
  74. search for a segment - setting it yourself toggles the automatically
  75. generated state which is only useful to emulate unprivileged behaviour
  76. or access unprivileged areas of memory while at privileged level. */
  77. #define TBID_PSTAT_BIT 0x02000000
  78. #define TBID_PSTAT_S 25
  79. /* The top six bits of a signal/segment specifier identifies a thread within
  80. the system. This represents a segments owner. */
  81. #define TBID_THREAD_BITS 0xFC000000
  82. #define TBID_THREAD_S 26
  83. /* Special thread id values */
  84. #define TBID_THREAD_NULL (-32) /* Never matches any thread/segment id used */
  85. #define TBID_THREAD_GLOBAL (-31) /* Things global to all threads */
  86. #define TBID_THREAD_HOST ( -1) /* Host interface */
  87. #define TBID_THREAD_EXTIO (TBID_THREAD_HOST) /* Host based ExtIO i/f */
  88. /* Virtual Id's are used for external thread interface structures or the
  89. above special Id's */
  90. #define TBID_IS_VIRTTHREAD( Id ) ((Id) < 0)
  91. /* Real Id's are used for actual hardware threads that are local */
  92. #define TBID_IS_REALTHREAD( Id ) ((Id) >= 0)
  93. /* Generate a segment Id given Thread, Scope, and Type */
  94. #define TBID_SEG( Thread, Scope, Type ) (\
  95. ((Thread)<<TBID_THREAD_S) + ((Scope)<<TBID_SEGSCOPE_S) + (Type))
  96. /* Generate a signal Id given Thread and SigNum */
  97. #define TBID_SIG( Thread, SigNum ) (\
  98. ((Thread)<<TBID_THREAD_S) + ((SigNum)<<TBID_SIGNUM_S) + TBID_SIGNAL_BIT)
  99. /* Generate an Id that solely represents a thread - useful for cache ops */
  100. #define TBID_THD( Thread ) ((Thread)<<TBID_THREAD_S)
  101. #define TBID_THD_NULL ((TBID_THREAD_NULL) <<TBID_THREAD_S)
  102. #define TBID_THD_GLOBAL ((TBID_THREAD_GLOBAL)<<TBID_THREAD_S)
  103. /* Common exception handler (see TBID_SIGNUM_XXF below) receives hardware
  104. generated fault codes TBIXXF_SIGNUM_xxF in it's SigNum parameter */
  105. #define TBIXXF_SIGNUM_IIF 0x01 /* General instruction fault */
  106. #define TBIXXF_SIGNUM_PGF 0x02 /* Privilege general fault */
  107. #define TBIXXF_SIGNUM_DHF 0x03 /* Data access watchpoint HIT */
  108. #define TBIXXF_SIGNUM_IGF 0x05 /* Code fetch general read failure */
  109. #define TBIXXF_SIGNUM_DGF 0x07 /* Data access general read/write fault */
  110. #define TBIXXF_SIGNUM_IPF 0x09 /* Code fetch page fault */
  111. #define TBIXXF_SIGNUM_DPF 0x0B /* Data access page fault */
  112. #define TBIXXF_SIGNUM_IHF 0x0D /* Instruction breakpoint HIT */
  113. #define TBIXXF_SIGNUM_DWF 0x0F /* Data access read-only fault */
  114. /* Hardware signals communicate events between processing levels within a
  115. single thread all the _xxF cases are exceptions and are routed via a
  116. common exception handler, _SWx are software trap events and kicks including
  117. __TBISignal generated kicks, and finally _TRx are hardware triggers */
  118. #define TBID_SIGNUM_SW0 0x00 /* SWITCH GROUP 0 - Per thread user */
  119. #define TBID_SIGNUM_SW1 0x01 /* SWITCH GROUP 1 - Per thread system */
  120. #define TBID_SIGNUM_SW2 0x02 /* SWITCH GROUP 2 - Internal global request */
  121. #define TBID_SIGNUM_SW3 0x03 /* SWITCH GROUP 3 - External global request */
  122. #ifdef TBI_1_4
  123. #define TBID_SIGNUM_FPE 0x04 /* Deferred exception - Any IEEE 754 exception */
  124. #define TBID_SIGNUM_FPD 0x05 /* Deferred exception - Denormal exception */
  125. /* Reserved 0x6 for a reserved deferred exception */
  126. #define TBID_SIGNUM_BUS 0x07 /* Deferred exception - Bus Error */
  127. /* Reserved 0x08-0x09 */
  128. #else
  129. /* Reserved 0x04-0x09 */
  130. #endif
  131. #define TBID_SIGNUM_SWS 0x0A /* KICK received with SigMask != 0 */
  132. #define TBID_SIGNUM_SWK 0x0B /* KICK received with SigMask == 0 */
  133. /* Reserved 0x0C-0x0F */
  134. #define TBID_SIGNUM_TRT 0x10 /* Timer trigger */
  135. #define TBID_SIGNUM_LWK 0x11 /* Low level kick (handler provided by TBI) */
  136. #define TBID_SIGNUM_XXF 0x12 /* Fault handler - receives ALL _xxF sigs */
  137. #ifdef TBI_1_4
  138. #define TBID_SIGNUM_DFR 0x13 /* Deferred Exception handler */
  139. #else
  140. #define TBID_SIGNUM_FPE 0x13 /* FPE Exception handler */
  141. #endif
  142. /* External trigger one group 0x14 to 0x17 - per thread */
  143. #define TBID_SIGNUM_TR1(Thread) (0x14+(Thread))
  144. #define TBID_SIGNUM_T10 0x14
  145. #define TBID_SIGNUM_T11 0x15
  146. #define TBID_SIGNUM_T12 0x16
  147. #define TBID_SIGNUM_T13 0x17
  148. /* External trigger two group 0x18 to 0x1b - per thread */
  149. #define TBID_SIGNUM_TR2(Thread) (0x18+(Thread))
  150. #define TBID_SIGNUM_T20 0x18
  151. #define TBID_SIGNUM_T21 0x19
  152. #define TBID_SIGNUM_T22 0x1A
  153. #define TBID_SIGNUM_T23 0x1B
  154. #define TBID_SIGNUM_TR3 0x1C /* External trigger N-4 (global) */
  155. #define TBID_SIGNUM_TR4 0x1D /* External trigger N-3 (global) */
  156. #define TBID_SIGNUM_TR5 0x1E /* External trigger N-2 (global) */
  157. #define TBID_SIGNUM_TR6 0x1F /* External trigger N-1 (global) */
  158. #define TBID_SIGNUM_MAX 0x1F
  159. /* Return the trigger register(TXMASK[I]/TXSTAT[I]) bits related to
  160. each hardware signal, sometimes this is a many-to-one relationship. */
  161. #define TBI_TRIG_BIT(SigNum) (\
  162. ((SigNum) >= TBID_SIGNUM_TRT) ? 1<<((SigNum)-TBID_SIGNUM_TRT) :\
  163. ( ((SigNum) == TBID_SIGNUM_SWS) || \
  164. ((SigNum) == TBID_SIGNUM_SWK) ) ? \
  165. TXSTAT_KICK_BIT : TXSTATI_BGNDHALT_BIT )
  166. /* Return the hardware trigger vector number for entries in the
  167. HWVEC0EXT table that will generate the required internal trigger. */
  168. #define TBI_TRIG_VEC(SigNum) (\
  169. ((SigNum) >= TBID_SIGNUM_T10) ? ((SigNum)-TBID_SIGNUM_TRT) : -1)
  170. /* Default trigger masks for each thread at background/interrupt level */
  171. #define TBI_TRIGS_INIT( Thread ) (\
  172. TXSTAT_KICK_BIT + TBI_TRIG_BIT(TBID_SIGNUM_TR1(Thread)) )
  173. #define TBI_INTS_INIT( Thread ) (\
  174. TXSTAT_KICK_BIT + TXSTATI_BGNDHALT_BIT \
  175. + TBI_TRIG_BIT(TBID_SIGNUM_TR2(Thread)) )
  176. #ifndef __ASSEMBLY__
  177. /* A spin-lock location is a zero-initialised location in memory */
  178. typedef volatile int TBISPIN, *PTBISPIN;
  179. /* A kick location is a hardware location you can write to
  180. * in order to cause a kick
  181. */
  182. typedef volatile int *PTBIKICK;
  183. #if defined(METAC_1_0) || defined(METAC_1_1)
  184. /* Macro to perform a kick */
  185. #define TBI_KICK( pKick ) do { pKick[0] = 1; } while (0)
  186. #else
  187. /* #define METAG_LIN_VALUES before including machine.h if required */
  188. #ifdef LINSYSEVENT_WR_COMBINE_FLUSH
  189. /* Macro to perform a kick - write combiners must be flushed */
  190. #define TBI_KICK( pKick ) do {\
  191. volatile int *pFlush = (volatile int *) LINSYSEVENT_WR_COMBINE_FLUSH; \
  192. pFlush[0] = 0; \
  193. pKick[0] = 1; } while (0)
  194. #endif
  195. #endif /* if defined(METAC_1_0) || defined(METAC_1_1) */
  196. #endif /* ifndef __ASSEMBLY__ */
  197. #ifndef __ASSEMBLY__
  198. /* 64-bit dual unit state value */
  199. typedef struct _tbidual_tag_ {
  200. /* 32-bit value from a pair of registers in data or address units */
  201. int U0, U1;
  202. } TBIDUAL, *PTBIDUAL;
  203. #endif /* ifndef __ASSEMBLY__ */
  204. /* Byte offsets of fields within TBIDUAL */
  205. #define TBIDUAL_U0 (0)
  206. #define TBIDUAL_U1 (4)
  207. #define TBIDUAL_BYTES (8)
  208. #define TBICTX_CRIT_BIT 0x0001 /* ASync state saved in TBICTX */
  209. #define TBICTX_SOFT_BIT 0x0002 /* Sync state saved in TBICTX (other bits 0) */
  210. #ifdef TBI_FASTINT_1_4
  211. #define TBICTX_FINT_BIT 0x0004 /* Using Fast Interrupts */
  212. #endif
  213. #define TBICTX_FPAC_BIT 0x0010 /* FPU state in TBICTX, FPU active on entry */
  214. #define TBICTX_XMCC_BIT 0x0020 /* Bit to identify a MECC task */
  215. #define TBICTX_CBUF_BIT 0x0040 /* Hardware catch buffer flag from TXSTATUS */
  216. #define TBICTX_CBRP_BIT 0x0080 /* Read pipeline dirty from TXDIVTIME */
  217. #define TBICTX_XDX8_BIT 0x0100 /* Saved DX.8 to DX.15 too */
  218. #define TBICTX_XAXX_BIT 0x0200 /* Save remaining AX registers to AX.7 */
  219. #define TBICTX_XHL2_BIT 0x0400 /* Saved hardware loop registers too */
  220. #define TBICTX_XTDP_BIT 0x0800 /* Saved DSP registers too */
  221. #define TBICTX_XEXT_BIT 0x1000 /* Set if TBICTX.Ext.Ctx contains extended
  222. state save area, otherwise TBICTX.Ext.AX2
  223. just holds normal A0.2 and A1.2 states */
  224. #define TBICTX_WAIT_BIT 0x2000 /* Causes wait for trigger - sticky toggle */
  225. #define TBICTX_XCBF_BIT 0x4000 /* Catch buffer or RD extracted into TBICTX */
  226. #define TBICTX_PRIV_BIT 0x8000 /* Set if system uses 'privileged' model */
  227. #ifdef METAC_1_0
  228. #define TBICTX_XAX3_BIT 0x0200 /* Saved AX.5 to AX.7 for XAXX */
  229. #define TBICTX_AX_REGS 5 /* Ax.0 to Ax.4 are core GP regs on CHORUS */
  230. #else
  231. #define TBICTX_XAX4_BIT 0x0200 /* Saved AX.4 to AX.7 for XAXX */
  232. #define TBICTX_AX_REGS 4 /* Default is Ax.0 to Ax.3 */
  233. #endif
  234. #ifdef TBI_1_4
  235. #define TBICTX_CFGFPU_FX16_BIT 0x00010000 /* Save FX.8 to FX.15 too */
  236. /* The METAC_CORE_ID_CONFIG field indicates omitted DSP resources */
  237. #define METAC_COREID_CFGXCTX_MASK( Value ) (\
  238. ( (((Value & METAC_COREID_CFGDSP_BITS)>> \
  239. METAC_COREID_CFGDSP_S ) == METAC_COREID_CFGDSP_MIN) ? \
  240. ~(TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+ \
  241. TBICTX_XAXX_BIT+TBICTX_XDX8_BIT ) : ~0U ) )
  242. #endif
  243. /* Extended context state provides a standardised method for registering the
  244. arguments required by __TBICtxSave to save the additional register states
  245. currently in use by non general purpose code. The state of the __TBIExtCtx
  246. variable in the static space of the thread forms an extension of the base
  247. context of the thread.
  248. If ( __TBIExtCtx.Ctx.SaveMask == 0 ) then pExt is assumed to be NULL and
  249. the empty state of __TBIExtCtx is represented by the fact that
  250. TBICTX.SaveMask does not have the bit TBICTX_XEXT_BIT set.
  251. If ( __TBIExtCtx.Ctx.SaveMask != 0 ) then pExt should point at a suitably
  252. sized extended context save area (usually at the end of the stack space
  253. allocated by the current routine). This space should allow for the
  254. displaced state of A0.2 and A1.2 to be saved along with the other extended
  255. states indicated via __TBIExtCtx.Ctx.SaveMask. */
  256. #ifndef __ASSEMBLY__
  257. typedef union _tbiextctx_tag_ {
  258. long long Val;
  259. TBIDUAL AX2;
  260. struct _tbiextctxext_tag {
  261. #ifdef TBI_1_4
  262. short DspramSizes; /* DSPRAM sizes. Encoding varies between
  263. TBICtxAlloc and the ECH scheme. */
  264. #else
  265. short Reserved0;
  266. #endif
  267. short SaveMask; /* Flag bits for state saved */
  268. PTBIDUAL pExt; /* AX[2] state saved first plus Xxxx state */
  269. } Ctx;
  270. } TBIEXTCTX, *PTBIEXTCTX;
  271. /* Automatic registration of extended context save for __TBINestInts */
  272. extern TBIEXTCTX __TBIExtCtx;
  273. #endif /* ifndef __ASSEMBLY__ */
  274. /* Byte offsets of fields within TBIEXTCTX */
  275. #define TBIEXTCTX_AX2 (0)
  276. #define TBIEXTCTX_Ctx (0)
  277. #define TBIEXTCTX_Ctx_SaveMask (TBIEXTCTX_Ctx + 2)
  278. #define TBIEXTCTX_Ctx_pExt (TBIEXTCTX_Ctx + 2 + 2)
  279. /* Extended context data size calculation constants */
  280. #define TBICTXEXT_BYTES (8)
  281. #define TBICTXEXTBB8_BYTES (8*8)
  282. #define TBICTXEXTAX3_BYTES (3*8)
  283. #define TBICTXEXTAX4_BYTES (4*8)
  284. #ifdef METAC_1_0
  285. #define TBICTXEXTAXX_BYTES TBICTXEXTAX3_BYTES
  286. #else
  287. #define TBICTXEXTAXX_BYTES TBICTXEXTAX4_BYTES
  288. #endif
  289. #define TBICTXEXTHL2_BYTES (3*8)
  290. #define TBICTXEXTTDR_BYTES (27*8)
  291. #define TBICTXEXTTDP_BYTES TBICTXEXTTDR_BYTES
  292. #ifdef TBI_1_4
  293. #define TBICTXEXTFX8_BYTES (4*8)
  294. #define TBICTXEXTFPAC_BYTES (1*4 + 2*2 + 4*8)
  295. #define TBICTXEXTFACF_BYTES (3*8)
  296. #endif
  297. /* Maximum flag bits to be set via the TBICTX_EXTSET macro */
  298. #define TBICTXEXT_MAXBITS (TBICTX_XEXT_BIT| \
  299. TBICTX_XDX8_BIT|TBICTX_XAXX_BIT|\
  300. TBICTX_XHL2_BIT|TBICTX_XTDP_BIT )
  301. /* Maximum size of the extended context save area for current variant */
  302. #define TBICTXEXT_MAXBYTES (TBICTXEXT_BYTES+TBICTXEXTBB8_BYTES+\
  303. TBICTXEXTAXX_BYTES+TBICTXEXTHL2_BYTES+\
  304. TBICTXEXTTDP_BYTES )
  305. #ifdef TBI_FASTINT_1_4
  306. /* Maximum flag bits to be set via the TBICTX_EXTSET macro */
  307. #define TBICTX2EXT_MAXBITS (TBICTX_XDX8_BIT|TBICTX_XAXX_BIT|\
  308. TBICTX_XHL2_BIT|TBICTX_XTDP_BIT )
  309. /* Maximum size of the extended context save area for current variant */
  310. #define TBICTX2EXT_MAXBYTES (TBICTXEXTBB8_BYTES+TBICTXEXTAXX_BYTES\
  311. +TBICTXEXTHL2_BYTES+TBICTXEXTTDP_BYTES )
  312. #endif
  313. /* Specify extended resources being used by current routine, code must be
  314. assembler generated to utilise extended resources-
  315. MOV D0xxx,A0StP ; Perform alloca - routine should
  316. ADD A0StP,A0StP,#SaveSize ; setup/use A0FrP to access locals
  317. MOVT D1xxx,#SaveMask ; TBICTX_XEXT_BIT MUST be set
  318. SETL [A1GbP+#OG(___TBIExtCtx)],D0xxx,D1xxx
  319. NB: OG(___TBIExtCtx) is a special case supported for SETL/GETL operations
  320. on 64-bit sizes structures only, other accesses must be based on use
  321. of OGA(___TBIExtCtx).
  322. At exit of routine-
  323. MOV D0xxx,#0 ; Clear extended context save state
  324. MOV D1xxx,#0
  325. SETL [A1GbP+#OG(___TBIExtCtx)],D0xxx,D1xxx
  326. SUB A0StP,A0StP,#SaveSize ; If original A0StP required
  327. NB: Both the setting and clearing of the whole __TBIExtCtx MUST be done
  328. atomically in one 64-bit write operation.
  329. For simple interrupt handling only via __TBINestInts there should be no
  330. impact of the __TBIExtCtx system. If pre-emptive scheduling is being
  331. performed however (assuming __TBINestInts has already been called earlier
  332. on) then the following logic will correctly call __TBICtxSave if required
  333. and clear out the currently selected background task-
  334. if ( __TBIExtCtx.Ctx.SaveMask & TBICTX_XEXT_BIT )
  335. {
  336. / * Store extended states in pCtx * /
  337. State.Sig.SaveMask |= __TBIExtCtx.Ctx.SaveMask;
  338. (void) __TBICtxSave( State, (void *) __TBIExtCtx.Ctx.pExt );
  339. __TBIExtCtx.Val = 0;
  340. }
  341. and when restoring task states call __TBICtxRestore-
  342. / * Restore state from pCtx * /
  343. State.Sig.pCtx = pCtx;
  344. State.Sig.SaveMask = pCtx->SaveMask;
  345. if ( State.Sig.SaveMask & TBICTX_XEXT_BIT )
  346. {
  347. / * Restore extended states from pCtx * /
  348. __TBIExtCtx.Val = pCtx->Ext.Val;
  349. (void) __TBICtxRestore( State, (void *) __TBIExtCtx.Ctx.pExt );
  350. }
  351. */
  352. /* Critical thread state save area */
  353. #ifndef __ASSEMBLY__
  354. typedef struct _tbictx_tag_ {
  355. /* TXSTATUS_FLAG_BITS and TXSTATUS_LSM_STEP_BITS from TXSTATUS */
  356. short Flags;
  357. /* Mask indicates any extended context state saved; 0 -> Never run */
  358. short SaveMask;
  359. /* Saved PC value */
  360. int CurrPC;
  361. /* Saved critical register states */
  362. TBIDUAL DX[8];
  363. /* Background control register states - for cores without catch buffer
  364. base in DIVTIME the TXSTATUS bits RPVALID and RPMASK are stored with
  365. the real state TXDIVTIME in CurrDIVTIME */
  366. int CurrRPT, CurrBPOBITS, CurrMODE, CurrDIVTIME;
  367. /* Saved AX register states */
  368. TBIDUAL AX[2];
  369. TBIEXTCTX Ext;
  370. TBIDUAL AX3[TBICTX_AX_REGS-3];
  371. /* Any CBUF state to be restored by a handler return must be stored here.
  372. Other extended state can be stored anywhere - see __TBICtxSave and
  373. __TBICtxRestore. */
  374. } TBICTX, *PTBICTX;
  375. #ifdef TBI_FASTINT_1_4
  376. typedef struct _tbictx2_tag_ {
  377. TBIDUAL AX[2]; /* AU.0, AU.1 */
  378. TBIDUAL DX[2]; /* DU.0, DU.4 */
  379. int CurrMODE;
  380. int CurrRPT;
  381. int CurrSTATUS;
  382. void *CurrPC; /* PC in PC address space */
  383. } TBICTX2, *PTBICTX2;
  384. /* TBICTX2 is followed by:
  385. * TBICTXEXTCB0 if TXSTATUS.CBMarker
  386. * TBIDUAL * TXSTATUS.IRPCount if TXSTATUS.IRPCount > 0
  387. * TBICTXGP if using __TBIStdRootIntHandler or __TBIStdCtxSwitchRootIntHandler
  388. */
  389. typedef struct _tbictxgp_tag_ {
  390. short DspramSizes;
  391. short SaveMask;
  392. void *pExt;
  393. TBIDUAL DX[6]; /* DU.1-DU.3, DU.5-DU.7 */
  394. TBIDUAL AX[2]; /* AU.2-AU.3 */
  395. } TBICTXGP, *PTBICTXGP;
  396. #define TBICTXGP_DspramSizes (0)
  397. #define TBICTXGP_SaveMask (TBICTXGP_DspramSizes + 2)
  398. #define TBICTXGP_MAX_BYTES (2 + 2 + 4 + 8*(6+2))
  399. #endif
  400. #endif /* ifndef __ASSEMBLY__ */
  401. /* Byte offsets of fields within TBICTX */
  402. #define TBICTX_Flags (0)
  403. #define TBICTX_SaveMask (2)
  404. #define TBICTX_CurrPC (4)
  405. #define TBICTX_DX (2 + 2 + 4)
  406. #define TBICTX_CurrRPT (2 + 2 + 4 + 8 * 8)
  407. #define TBICTX_CurrMODE (2 + 2 + 4 + 8 * 8 + 4 + 4)
  408. #define TBICTX_AX (2 + 2 + 4 + 8 * 8 + 4 + 4 + 4 + 4)
  409. #define TBICTX_Ext (2 + 2 + 4 + 8 * 8 + 4 + 4 + 4 + 4 + 2 * 8)
  410. #define TBICTX_Ext_AX2 (TBICTX_Ext + TBIEXTCTX_AX2)
  411. #define TBICTX_Ext_AX2_U0 (TBICTX_Ext + TBIEXTCTX_AX2 + TBIDUAL_U0)
  412. #define TBICTX_Ext_AX2_U1 (TBICTX_Ext + TBIEXTCTX_AX2 + TBIDUAL_U1)
  413. #define TBICTX_Ext_Ctx_pExt (TBICTX_Ext + TBIEXTCTX_Ctx_pExt)
  414. #define TBICTX_Ext_Ctx_SaveMask (TBICTX_Ext + TBIEXTCTX_Ctx_SaveMask)
  415. #ifdef TBI_FASTINT_1_4
  416. #define TBICTX2_BYTES (8 * 2 + 8 * 2 + 4 + 4 + 4 + 4)
  417. #define TBICTXEXTCB0_BYTES (4 + 4 + 8)
  418. #define TBICTX2_CRIT_MAX_BYTES (TBICTX2_BYTES + TBICTXEXTCB0_BYTES + 6 * TBIDUAL_BYTES)
  419. #define TBI_SWITCH_NEXT_PC(PC, EXTRA) ((PC) + (EXTRA & 1) ? 8 : 4)
  420. #endif
  421. #ifndef __ASSEMBLY__
  422. /* Extended thread state save areas - catch buffer state element */
  423. typedef struct _tbictxextcb0_tag_ {
  424. /* Flags data and address value - see METAC_CATCH_VALUES in machine.h */
  425. unsigned long CBFlags, CBAddr;
  426. /* 64-bit data */
  427. TBIDUAL CBData;
  428. } TBICTXEXTCB0, *PTBICTXEXTCB0;
  429. /* Read pipeline state saved on later cores after single catch buffer slot */
  430. typedef struct _tbictxextrp6_tag_ {
  431. /* RPMask is TXSTATUS_RPMASK_BITS only, reserved is undefined */
  432. unsigned long RPMask, Reserved0;
  433. TBIDUAL CBData[6];
  434. } TBICTXEXTRP6, *PTBICTXEXTRP6;
  435. /* Extended thread state save areas - 8 DU register pairs */
  436. typedef struct _tbictxextbb8_tag_ {
  437. /* Remaining Data unit registers in 64-bit pairs */
  438. TBIDUAL UX[8];
  439. } TBICTXEXTBB8, *PTBICTXEXTBB8;
  440. /* Extended thread state save areas - 3 AU register pairs */
  441. typedef struct _tbictxextbb3_tag_ {
  442. /* Remaining Address unit registers in 64-bit pairs */
  443. TBIDUAL UX[3];
  444. } TBICTXEXTBB3, *PTBICTXEXTBB3;
  445. /* Extended thread state save areas - 4 AU register pairs or 4 FX pairs */
  446. typedef struct _tbictxextbb4_tag_ {
  447. /* Remaining Address unit or FPU registers in 64-bit pairs */
  448. TBIDUAL UX[4];
  449. } TBICTXEXTBB4, *PTBICTXEXTBB4;
  450. /* Extended thread state save areas - Hardware loop states (max 2) */
  451. typedef struct _tbictxexthl2_tag_ {
  452. /* Hardware looping register states */
  453. TBIDUAL Start, End, Count;
  454. } TBICTXEXTHL2, *PTBICTXEXTHL2;
  455. /* Extended thread state save areas - DSP register states */
  456. typedef struct _tbictxexttdp_tag_ {
  457. /* DSP 32-bit accumulator register state (Bits 31:0 of ACX.0) */
  458. TBIDUAL Acc32[1];
  459. /* DSP > 32-bit accumulator bits 63:32 of ACX.0 (zero-extended) */
  460. TBIDUAL Acc64[1];
  461. /* Twiddle register state, and three phase increment states */
  462. TBIDUAL PReg[4];
  463. /* Modulo region size, padded to 64-bits */
  464. int CurrMRSIZE, Reserved0;
  465. } TBICTXEXTTDP, *PTBICTXEXTTDP;
  466. /* Extended thread state save areas - DSP register states including DSP RAM */
  467. typedef struct _tbictxexttdpr_tag_ {
  468. /* DSP 32-bit accumulator register state (Bits 31:0 of ACX.0) */
  469. TBIDUAL Acc32[1];
  470. /* DSP 40-bit accumulator register state (Bits 39:8 of ACX.0) */
  471. TBIDUAL Acc40[1];
  472. /* DSP RAM Pointers */
  473. TBIDUAL RP0[2], WP0[2], RP1[2], WP1[2];
  474. /* DSP RAM Increments */
  475. TBIDUAL RPI0[2], WPI0[2], RPI1[2], WPI1[2];
  476. /* Template registers */
  477. unsigned long Tmplt[16];
  478. /* Modulo address region size and DSP RAM module region sizes */
  479. int CurrMRSIZE, CurrDRSIZE;
  480. } TBICTXEXTTDPR, *PTBICTXEXTTDPR;
  481. #ifdef TBI_1_4
  482. /* The METAC_ID_CORE register state is a marker for the FPU
  483. state that is then stored after this core header structure. */
  484. #define TBICTXEXTFPU_CONFIG_MASK ( (METAC_COREID_NOFPACC_BIT+ \
  485. METAC_COREID_CFGFPU_BITS ) << \
  486. METAC_COREID_CONFIG_BITS )
  487. /* Recorded FPU exception state from TXDEFR in DefrFpu */
  488. #define TBICTXEXTFPU_DEFRFPU_MASK (TXDEFR_FPU_FE_BITS)
  489. /* Extended thread state save areas - FPU register states */
  490. typedef struct _tbictxextfpu_tag_ {
  491. /* Stored METAC_CORE_ID CONFIG */
  492. int CfgFpu;
  493. /* Stored deferred TXDEFR bits related to FPU
  494. *
  495. * This is encoded as follows in order to fit into 16-bits:
  496. * DefrFPU:15 - 14 <= 0
  497. * :13 - 8 <= TXDEFR:21-16
  498. * : 7 - 6 <= 0
  499. * : 5 - 0 <= TXDEFR:5-0
  500. */
  501. short DefrFpu;
  502. /* TXMODE bits related to FPU */
  503. short ModeFpu;
  504. /* FPU Even/Odd register states */
  505. TBIDUAL FX[4];
  506. /* if CfgFpu & TBICTX_CFGFPU_FX16_BIT -> 1 then TBICTXEXTBB4 holds FX.8-15 */
  507. /* if CfgFpu & TBICTX_CFGFPU_NOACF_BIT -> 0 then TBICTXEXTFPACC holds state */
  508. } TBICTXEXTFPU, *PTBICTXEXTFPU;
  509. /* Extended thread state save areas - FPU accumulator state */
  510. typedef struct _tbictxextfpacc_tag_ {
  511. /* FPU accumulator register state - three 64-bit parts */
  512. TBIDUAL FAcc32[3];
  513. } TBICTXEXTFPACC, *PTBICTXEXTFPACC;
  514. #endif
  515. /* Prototype TBI structure */
  516. struct _tbi_tag_ ;
  517. /* A 64-bit return value used commonly in the TBI APIs */
  518. typedef union _tbires_tag_ {
  519. /* Save and load this value to get/set the whole result quickly */
  520. long long Val;
  521. /* Parameter of a fnSigs or __TBICtx* call */
  522. struct _tbires_sig_tag_ {
  523. /* TXMASK[I] bits zeroed upto and including current trigger level */
  524. unsigned short TrigMask;
  525. /* Control bits for handlers - see PTBIAPIFN documentation below */
  526. unsigned short SaveMask;
  527. /* Pointer to the base register context save area of the thread */
  528. PTBICTX pCtx;
  529. } Sig;
  530. /* Result of TBIThrdPrivId call */
  531. struct _tbires_thrdprivid_tag_ {
  532. /* Basic thread identifier; just TBID_THREAD_BITS */
  533. int Id;
  534. /* None thread number bits; TBID_ISTAT_BIT+TBID_PSTAT_BIT */
  535. int Priv;
  536. } Thrd;
  537. /* Parameter and Result of a __TBISwitch call */
  538. struct _tbires_switch_tag_ {
  539. /* Parameter passed across context switch */
  540. void *pPara;
  541. /* Thread context of other Thread includng restore flags */
  542. PTBICTX pCtx;
  543. } Switch;
  544. /* For extended S/W events only */
  545. struct _tbires_ccb_tag_ {
  546. void *pCCB;
  547. int COff;
  548. } CCB;
  549. struct _tbires_tlb_tag_ {
  550. int Leaf; /* TLB Leaf data */
  551. int Flags; /* TLB Flags */
  552. } Tlb;
  553. #ifdef TBI_FASTINT_1_4
  554. struct _tbires_intr_tag_ {
  555. short TrigMask;
  556. short SaveMask;
  557. PTBICTX2 pCtx;
  558. } Intr;
  559. #endif
  560. } TBIRES, *PTBIRES;
  561. #endif /* ifndef __ASSEMBLY__ */
  562. #ifndef __ASSEMBLY__
  563. /* Prototype for all signal handler functions, called via ___TBISyncTrigger or
  564. ___TBIASyncTrigger.
  565. State.Sig.TrigMask will indicate the bits set within TXMASKI at
  566. the time of the handler call that have all been cleared to prevent
  567. nested interrupt occuring immediately.
  568. State.Sig.SaveMask is a bit-mask which will be set to Zero when a trigger
  569. occurs at background level and TBICTX_CRIT_BIT and optionally
  570. TBICTX_CBUF_BIT when a trigger occurs at interrupt level.
  571. TBICTX_CBUF_BIT reflects the state of TXSTATUS_CBMARKER_BIT for
  572. the interrupted background thread.
  573. State.Sig.pCtx will point at a TBICTX structure generated to hold the
  574. critical state of the interrupted thread at interrupt level and
  575. should be set to NULL when called at background level.
  576. Triggers will indicate the status of TXSTAT or TXSTATI sampled by the
  577. code that called the handler.
  578. InstOrSWSId is defined firstly as 'Inst' if the SigNum is TBID_SIGNUM_SWx
  579. and hold the actual SWITCH instruction detected, secondly if SigNum
  580. is TBID_SIGNUM_SWS the 'SWSId' is defined to hold the Id of the
  581. software signal detected, in other cases the value of this
  582. parameter is undefined.
  583. pTBI points at the PTBI structure related to the thread and processing
  584. level involved.
  585. TBIRES return value at both processing levels is similar in terms of any
  586. changes that the handler makes. By default the State argument value
  587. passed in should be returned.
  588. Sig.TrigMask value is bits to OR back into TXMASKI when the handler
  589. completes to enable currently disabled interrupts.
  590. Sig.SaveMask value is ignored.
  591. Sig.pCtx is ignored.
  592. */
  593. typedef TBIRES (*PTBIAPIFN)( TBIRES State, int SigNum,
  594. int Triggers, int InstOrSWSId,
  595. volatile struct _tbi_tag_ *pTBI );
  596. #endif /* ifndef __ASSEMBLY__ */
  597. #ifndef __ASSEMBLY__
  598. /* The global memory map is described by a list of segment descriptors */
  599. typedef volatile struct _tbiseg_tag_ {
  600. volatile struct _tbiseg_tag_ *pLink;
  601. int Id; /* Id of the segment */
  602. TBISPIN Lock; /* Spin-lock for struct (normally 0) */
  603. unsigned int Bytes; /* Size of region in bytes */
  604. void *pGAddr; /* Base addr of region in global space */
  605. void *pLAddr; /* Base addr of region in local space */
  606. int Data[2]; /* Segment specific data (may be extended) */
  607. } TBISEG, *PTBISEG;
  608. #endif /* ifndef __ASSEMBLY__ */
  609. /* Offsets of fields in TBISEG structure */
  610. #define TBISEG_pLink ( 0)
  611. #define TBISEG_Id ( 4)
  612. #define TBISEG_Lock ( 8)
  613. #define TBISEG_Bytes (12)
  614. #define TBISEG_pGAddr (16)
  615. #define TBISEG_pLAddr (20)
  616. #define TBISEG_Data (24)
  617. #ifndef __ASSEMBLY__
  618. typedef volatile struct _tbi_tag_ {
  619. int SigMask; /* Bits set to represent S/W events */
  620. PTBIKICK pKick; /* Kick addr for S/W events */
  621. void *pCCB; /* Extended S/W events */
  622. PTBISEG pSeg; /* Related segment structure */
  623. PTBIAPIFN fnSigs[TBID_SIGNUM_MAX+1];/* Signal handler API table */
  624. } *PTBI, TBI;
  625. #endif /* ifndef __ASSEMBLY__ */
  626. /* Byte offsets of fields within TBI */
  627. #define TBI_SigMask (0)
  628. #define TBI_pKick (4)
  629. #define TBI_pCCB (8)
  630. #define TBI_pSeg (12)
  631. #define TBI_fnSigs (16)
  632. #ifdef TBI_1_4
  633. #ifndef __ASSEMBLY__
  634. /* This handler should be used for TBID_SIGNUM_DFR */
  635. extern TBIRES __TBIHandleDFR ( TBIRES State, int SigNum,
  636. int Triggers, int InstOrSWSId,
  637. volatile struct _tbi_tag_ *pTBI );
  638. #endif
  639. #endif
  640. /* String table entry - special values */
  641. #define METAG_TBI_STRS (0x5300) /* Tag : If entry is valid */
  642. #define METAG_TBI_STRE (0x4500) /* Tag : If entry is end of table */
  643. #define METAG_TBI_STRG (0x4700) /* Tag : If entry is a gap */
  644. #define METAG_TBI_STRX (0x5A00) /* TransLen : If no translation present */
  645. #ifndef __ASSEMBLY__
  646. typedef volatile struct _tbistr_tag_ {
  647. short Bytes; /* Length of entry in Bytes */
  648. short Tag; /* Normally METAG_TBI_STRS(0x5300) */
  649. short Len; /* Length of the string entry (incl null) */
  650. short TransLen; /* Normally METAG_TBI_STRX(0x5A00) */
  651. char String[8]; /* Zero terminated (may-be bigger) */
  652. } TBISTR, *PTBISTR;
  653. #endif /* ifndef __ASSEMBLY__ */
  654. /* Cache size information - available as fields of Data[1] of global heap
  655. segment */
  656. #define METAG_TBI_ICACHE_SIZE_S 0 /* see comments below */
  657. #define METAG_TBI_ICACHE_SIZE_BITS 0x0000000F
  658. #define METAG_TBI_ICACHE_FILL_S 4
  659. #define METAG_TBI_ICACHE_FILL_BITS 0x000000F0
  660. #define METAG_TBI_DCACHE_SIZE_S 8
  661. #define METAG_TBI_DCACHE_SIZE_BITS 0x00000F00
  662. #define METAG_TBI_DCACHE_FILL_S 12
  663. #define METAG_TBI_DCACHE_FILL_BITS 0x0000F000
  664. /* METAG_TBI_xCACHE_SIZE
  665. Describes the physical cache size rounded up to the next power of 2
  666. relative to a 16K (2^14) cache. These sizes are encoded as a signed addend
  667. to this base power of 2, for example
  668. 4K -> 2^12 -> -2 (i.e. 12-14)
  669. 8K -> 2^13 -> -1
  670. 16K -> 2^14 -> 0
  671. 32K -> 2^15 -> +1
  672. 64K -> 2^16 -> +2
  673. 128K -> 2^17 -> +3
  674. METAG_TBI_xCACHE_FILL
  675. Describes the physical cache size within the power of 2 area given by
  676. the value above. For example a 10K cache may be represented as having
  677. nearest size 16K with a fill of 10 sixteenths. This is encoded as the
  678. number of unused 1/16ths, for example
  679. 0000 -> 0 -> 16/16
  680. 0001 -> 1 -> 15/16
  681. 0010 -> 2 -> 14/16
  682. ...
  683. 1111 -> 15 -> 1/16
  684. */
  685. #define METAG_TBI_CACHE_SIZE_BASE_LOG2 14
  686. /* Each declaration made by this macro generates a TBISTR entry */
  687. #ifndef __ASSEMBLY__
  688. #define TBISTR_DECL( Name, Str ) \
  689. __attribute__ ((__section__ (".tbistr") )) const char Name[] = #Str
  690. #endif
  691. /* META timer values - see below for Timer support routines */
  692. #define TBI_TIMERWAIT_MIN (-16) /* Minimum 'recommended' period */
  693. #define TBI_TIMERWAIT_MAX (-0x7FFFFFFF) /* Maximum 'recommended' period */
  694. #ifndef __ASSEMBLY__
  695. /* These macros allow direct access from C to any register known to the
  696. assembler or defined in machine.h. Example candidates are TXTACTCYC,
  697. TXIDLECYC, and TXPRIVEXT. Note that when higher level macros and routines
  698. like the timer and trigger handling features below these should be used in
  699. preference to this direct low-level access mechanism. */
  700. #define TBI_GETREG( Reg ) __extension__ ({\
  701. int __GRValue; \
  702. __asm__ volatile ("MOV\t%0," #Reg "\t/* (*TBI_GETREG OK) */" : \
  703. "=r" (__GRValue) ); \
  704. __GRValue; })
  705. #define TBI_SETREG( Reg, Value ) do {\
  706. int __SRValue = Value; \
  707. __asm__ volatile ("MOV\t" #Reg ",%0\t/* (*TBI_SETREG OK) */" : \
  708. : "r" (__SRValue) ); } while (0)
  709. #define TBI_SWAPREG( Reg, Value ) do {\
  710. int __XRValue = (Value); \
  711. __asm__ volatile ("SWAP\t" #Reg ",%0\t/* (*TBI_SWAPREG OK) */" : \
  712. "=r" (__XRValue) : "0" (__XRValue) ); \
  713. Value = __XRValue; } while (0)
  714. /* Obtain and/or release global critical section lock given that interrupts
  715. are already disabled and/or should remain disabled. */
  716. #define TBI_NOINTSCRITON do {\
  717. __asm__ volatile ("LOCK1\t\t/* (*TBI_NOINTSCRITON OK) */");} while (0)
  718. #define TBI_NOINTSCRITOFF do {\
  719. __asm__ volatile ("LOCK0\t\t/* (*TBI_NOINTSCRITOFF OK) */");} while (0)
  720. /* Optimised in-lining versions of the above macros */
  721. #define TBI_LOCK( TrigState ) do {\
  722. int __TRValue; \
  723. int __ALOCKHI = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
  724. __asm__ volatile ("MOV %0,#0\t\t/* (*TBI_LOCK ... */\n\t" \
  725. "SWAP\t%0,TXMASKI\t/* ... */\n\t" \
  726. "LOCK2\t\t/* ... */\n\t" \
  727. "SETD\t[%1+#0x40],D1RtP /* ... OK) */" : \
  728. "=r&" (__TRValue) : "u" (__ALOCKHI) ); \
  729. TrigState = __TRValue; } while (0)
  730. #define TBI_CRITON( TrigState ) do {\
  731. int __TRValue; \
  732. __asm__ volatile ("MOV %0,#0\t\t/* (*TBI_CRITON ... */\n\t" \
  733. "SWAP\t%0,TXMASKI\t/* ... */\n\t" \
  734. "LOCK1\t\t/* ... OK) */" : \
  735. "=r" (__TRValue) ); \
  736. TrigState = __TRValue; } while (0)
  737. #define TBI_INTSX( TrigState ) do {\
  738. int __TRValue = TrigState; \
  739. __asm__ volatile ("SWAP\t%0,TXMASKI\t/* (*TBI_INTSX OK) */" : \
  740. "=r" (__TRValue) : "0" (__TRValue) ); \
  741. TrigState = __TRValue; } while (0)
  742. #define TBI_UNLOCK( TrigState ) do {\
  743. int __TRValue = TrigState; \
  744. int __ALOCKHI = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
  745. __asm__ volatile ("SETD\t[%1+#0x00],D1RtP\t/* (*TBI_UNLOCK ... */\n\t" \
  746. "LOCK0\t\t/* ... */\n\t" \
  747. "MOV\tTXMASKI,%0\t/* ... OK) */" : \
  748. : "r" (__TRValue), "u" (__ALOCKHI) ); } while (0)
  749. #define TBI_CRITOFF( TrigState ) do {\
  750. int __TRValue = TrigState; \
  751. __asm__ volatile ("LOCK0\t\t/* (*TBI_CRITOFF ... */\n\t" \
  752. "MOV\tTXMASKI,%0\t/* ... OK) */" : \
  753. : "r" (__TRValue) ); } while (0)
  754. #define TBI_TRIGSX( SrcDst ) do { TBI_SWAPREG( TXMASK, SrcDst );} while (0)
  755. /* Composite macros to perform logic ops on INTS or TRIGS masks */
  756. #define TBI_INTSOR( Bits ) do {\
  757. int __TT = 0; TBI_INTSX(__TT); \
  758. __TT |= (Bits); TBI_INTSX(__TT); } while (0)
  759. #define TBI_INTSAND( Bits ) do {\
  760. int __TT = 0; TBI_INTSX(__TT); \
  761. __TT &= (Bits); TBI_INTSX(__TT); } while (0)
  762. #ifdef TBI_1_4
  763. #define TBI_DEFRICTRLSOR( Bits ) do {\
  764. int __TT = TBI_GETREG( CT.20 ); \
  765. __TT |= (Bits); TBI_SETREG( CT.20, __TT); } while (0)
  766. #define TBI_DEFRICTRLSAND( Bits ) do {\
  767. int __TT = TBI_GETREG( TXDEFR ); \
  768. __TT &= (Bits); TBI_SETREG( CT.20, __TT); } while (0)
  769. #endif
  770. #define TBI_TRIGSOR( Bits ) do {\
  771. int __TT = TBI_GETREG( TXMASK ); \
  772. __TT |= (Bits); TBI_SETREG( TXMASK, __TT); } while (0)
  773. #define TBI_TRIGSAND( Bits ) do {\
  774. int __TT = TBI_GETREG( TXMASK ); \
  775. __TT &= (Bits); TBI_SETREG( TXMASK, __TT); } while (0)
  776. /* Macros to disable and re-enable interrupts using TBI_INTSX, deliberate
  777. traps and exceptions can still be handled within the critical section. */
  778. #define TBI_STOPINTS( Value ) do {\
  779. int __TT = TBI_GETREG( TXMASKI ); \
  780. __TT &= TXSTATI_BGNDHALT_BIT; TBI_INTSX( __TT ); \
  781. Value = __TT; } while (0)
  782. #define TBI_RESTINTS( Value ) do {\
  783. int __TT = Value; TBI_INTSX( __TT ); } while (0)
  784. /* Return pointer to segment list at current privilege level */
  785. PTBISEG __TBISegList( void );
  786. /* Search the segment list for a match given Id, pStart can be NULL */
  787. PTBISEG __TBIFindSeg( PTBISEG pStart, int Id );
  788. /* Prepare a new segment structure using space from within another */
  789. PTBISEG __TBINewSeg( PTBISEG pFromSeg, int Id, unsigned int Bytes );
  790. /* Prepare a new segment using any global or local heap segments available */
  791. PTBISEG __TBIMakeNewSeg( int Id, unsigned int Bytes );
  792. /* Insert a new segment into the segment list so __TBIFindSeg can locate it */
  793. void __TBIAddSeg( PTBISEG pSeg );
  794. #define __TBIADDSEG_DEF /* Some versions failed to define this */
  795. /* Return Id of current thread; TBID_ISTAT_BIT+TBID_THREAD_BITS */
  796. int __TBIThreadId( void );
  797. /* Return TBIRES.Thrd data for current thread */
  798. TBIRES __TBIThrdPrivId( void );
  799. /* Return pointer to current threads TBI root block.
  800. Id implies whether Int or Background root block is required */
  801. PTBI __TBI( int Id );
  802. /* Try to set Mask bit using the spin-lock protocol, return 0 if fails and
  803. new state if succeeds */
  804. int __TBIPoll( PTBISPIN pLock, int Mask );
  805. /* Set Mask bits via the spin-lock protocol in *pLock, return new state */
  806. int __TBISpin( PTBISPIN pLock, int Mask );
  807. /* Default handler set up for all TBI.fnSigs entries during initialisation */
  808. TBIRES __TBIUnExpXXX( TBIRES State, int SigNum,
  809. int Triggers, int Inst, PTBI pTBI );
  810. /* Call this routine to service triggers at background processing level. The
  811. TBID_POLL_BIT of the Id parameter value will be used to indicate that the
  812. routine should return if no triggers need to be serviced initially. If this
  813. bit is not set the routine will block until one trigger handler is serviced
  814. and then behave like the poll case servicing any remaining triggers
  815. actually outstanding before returning. Normally the State parameter should
  816. be simply initialised to zero and the result should be ignored, other
  817. values/options are for internal use only. */
  818. TBIRES __TBISyncTrigger( TBIRES State, int Id );
  819. /* Call this routine to enable processing of triggers by signal handlers at
  820. interrupt level. The State parameter value passed is returned by this
  821. routine. The State.Sig.TrigMask field also specifies the initial
  822. state of the interrupt mask register TXMASKI to be setup by the call.
  823. The other parts of the State parameter are ignored unless the PRIV bit is
  824. set in the SaveMask field. In this case the State.Sig.pCtx field specifies
  825. the base of the stack to which the interrupt system should switch into
  826. as it saves the state of the previously executing code. In the case the
  827. thread will be unprivileged as it continues execution at the return
  828. point of this routine and it's future state will be effectively never
  829. trusted to be valid. */
  830. TBIRES __TBIASyncTrigger( TBIRES State );
  831. /* Call this to swap soft threads executing at the background processing level.
  832. The TBIRES returned to the new thread will be the same as the NextThread
  833. value specified to the call. The NextThread.Switch.pCtx value specifies
  834. which thread context to restore and the NextThread.Switch.Para value can
  835. hold an arbitrary expression to be passed between the threads. The saved
  836. state of the previous thread will be stored in a TBICTX descriptor created
  837. on it's stack and the address of this will be stored into the *rpSaveCtx
  838. location specified. */
  839. TBIRES __TBISwitch( TBIRES NextThread, PTBICTX *rpSaveCtx );
  840. /* Call this to initialise a stack frame ready for further use, up to four
  841. 32-bit arguments may be specified after the fixed args to be passed via
  842. the new stack pStack to the routine specified via fnMain. If the
  843. main-line routine ever returns the thread will operate as if main itself
  844. had returned and terminate with the return code given. */
  845. typedef int (*PTBIMAINFN)( TBIRES Arg /*, <= 4 additional 32-bit args */ );
  846. PTBICTX __TBISwitchInit( void *pStack, PTBIMAINFN fnMain, ... );
  847. /* Call this to resume a thread from a saved synchronous TBICTX state.
  848. The TBIRES returned to the new thread will be the same as the NextThread
  849. value specified to the call. The NextThread.Switch.pCtx value specifies
  850. which thread context to restore and the NextThread.Switch.Para value can
  851. hold an arbitrary expression to be passed between the threads. The context
  852. of the calling thread is lost and this routine never returns to the
  853. caller. The TrigsMask value supplied is ored into TXMASKI to enable
  854. interrupts after the context of the new thread is established. */
  855. void __TBISyncResume( TBIRES NextThread, int TrigsMask );
  856. /* Call these routines to save and restore the extended states of
  857. scheduled tasks. */
  858. void *__TBICtxSave( TBIRES State, void *pExt );
  859. void *__TBICtxRestore( TBIRES State, void *pExt );
  860. #ifdef TBI_1_4
  861. #ifdef TBI_FASTINT_1_4
  862. /* Call these routines to copy the GP state to a separate buffer
  863. * Only necessary for context switching.
  864. */
  865. PTBICTXGP __TBICtx2SaveCrit( PTBICTX2 pCurrentCtx, PTBICTX2 pSaveCtx );
  866. void *__TBICtx2SaveGP( PTBICTXGP pCurrentCtxGP, PTBICTXGP pSaveCtxGP );
  867. /* Call these routines to save and restore the extended states of
  868. scheduled tasks. */
  869. void *__TBICtx2Save( PTBICTXGP pCtxGP, short SaveMask, void *pExt );
  870. void *__TBICtx2Restore( PTBICTX2 pCtx, short SaveMask, void *pExt );
  871. #endif
  872. /* If FPAC flag is set then significant FPU context exists. Call these routine
  873. to save and restore it */
  874. void *__TBICtxFPUSave( TBIRES State, void *pExt );
  875. void *__TBICtxFPURestore( TBIRES State, void *pExt );
  876. #ifdef TBI_FASTINT_1_4
  877. extern void *__TBICtx2FPUSave (PTBICTXGP, short, void*);
  878. extern void *__TBICtx2FPURestore (PTBICTXGP, short, void*);
  879. #endif
  880. #endif
  881. #ifdef TBI_1_4
  882. /* Call these routines to save and restore DSPRAM. */
  883. void *__TBIDspramSaveA (short DspramSizes, void *pExt);
  884. void *__TBIDspramSaveB (short DspramSizes, void *pExt);
  885. void *__TBIDspramRestoreA (short DspramSizes, void *pExt);
  886. void *__TBIDspramRestoreB (short DspramSizes, void *pExt);
  887. #endif
  888. /* This routine should be used at the entrypoint of interrupt handlers to
  889. re-enable higher priority interrupts and/or save state from the previously
  890. executing background code. State is a TBIRES.Sig parameter with NoNestMask
  891. indicating the triggers (if any) that should remain disabled and SaveMask
  892. CBUF bit indicating the if the hardware catch buffer is dirty. Optionally
  893. any number of extended state bits X??? including XCBF can be specified to
  894. force a nested state save call to __TBICtxSave before the current routine
  895. continues. (In the latter case __TBICtxRestore should be called to restore
  896. any extended states before the background thread of execution is resumed)
  897. By default (no X??? bits specified in SaveMask) this routine performs a
  898. sub-call to __TBICtxSave with the pExt and State parameters specified IF
  899. some triggers could be serviced while the current interrupt handler
  900. executes and the hardware catch buffer is actually dirty. In this case
  901. this routine provides the XCBF bit in State.Sig.SaveMask to force the
  902. __TBICtxSave to extract the current catch state.
  903. The NoNestMask parameter should normally indicate that the same or lower
  904. triggers than those provoking the current handler call should not be
  905. serviced in nested calls, zero may be specified if all possible interrupts
  906. are to be allowed.
  907. The TBIRES.Sig value returned will be similar to the State parameter
  908. specified with the XCBF bit ORed into it's SaveMask if a context save was
  909. required and fewer bits set in it's TrigMask corresponding to the same/lower
  910. priority interrupt triggers still not enabled. */
  911. TBIRES __TBINestInts( TBIRES State, void *pExt, int NoNestMask );
  912. /* This routine causes the TBICTX structure specified in State.Sig.pCtx to
  913. be restored. This implies that execution will not return to the caller.
  914. The State.Sig.TrigMask field will be restored during the context switch
  915. such that any immediately occuring interrupts occur in the context of the
  916. newly specified task. The State.Sig.SaveMask parameter is ignored. */
  917. void __TBIASyncResume( TBIRES State );
  918. /* Call this routine to enable fastest possible processing of one or more
  919. interrupt triggers via a unified signal handler. The handler concerned
  920. must simple return after servicing the related hardware.
  921. The State.Sig.TrigMask parameter indicates the interrupt triggers to be
  922. enabled and the Thin.Thin.fnHandler specifies the routine to call and
  923. the whole Thin parameter value will be passed to this routine unaltered as
  924. it's first parameter. */
  925. void __TBIASyncThin( TBIRES State, TBIRES Thin );
  926. /* Do this before performing your own direct spin-lock access - use TBI_LOCK */
  927. int __TBILock( void );
  928. /* Do this after performing your own direct spin-lock access - use TBI_UNLOCK */
  929. void __TBIUnlock( int TrigState );
  930. /* Obtain and release global critical section lock - only stops execution
  931. of interrupts on this thread and similar critical section code on other
  932. local threads - use TBI_CRITON or TBI_CRITOFF */
  933. int __TBICritOn( void );
  934. void __TBICritOff( int TrigState );
  935. /* Change INTS (TXMASKI) - return old state - use TBI_INTSX */
  936. int __TBIIntsX( int NewMask );
  937. /* Change TRIGS (TXMASK) - return old state - use TBI_TRIGSX */
  938. int __TBITrigsX( int NewMask );
  939. /* This function initialises a timer for first use, only the TBID_ISTAT_BIT
  940. of the Id parameter is used to indicate which timer is to be modified. The
  941. Wait value should either be zero to disable the timer concerned or be in
  942. the recommended TBI_TIMERWAIT_* range to specify the delay required before
  943. the first timer trigger occurs.
  944. The TBID_ISTAT_BIT of the Id parameter similar effects all other timer
  945. support functions (see below). */
  946. void __TBITimerCtrl( int Id, int Wait );
  947. /* This routine returns a 64-bit time stamp value that is initialised to zero
  948. via a __TBITimerCtrl timer enabling call. */
  949. long long __TBITimeStamp( int Id );
  950. /* To manage a periodic timer each period elapsed should be subracted from
  951. the current timer value to attempt to set up the next timer trigger. The
  952. Wait parameter should be a value in the recommended TBI_TIMERWAIT_* range.
  953. The return value is the new aggregate value that the timer was updated to,
  954. if this is less than zero then a timer trigger is guaranteed to be
  955. generated after the number of ticks implied, if a positive result is
  956. returned either itterative or step-wise corrective action must be taken to
  957. resynchronise the timer and hence provoke a future timer trigger. */
  958. int __TBITimerAdd( int Id, int Wait );
  959. /* String table search function, pStart is first entry to check or NULL,
  960. pStr is string data to search for and MatchLen is either length of string
  961. to compare for an exact match or negative length to compare for partial
  962. match. */
  963. const TBISTR *__TBIFindStr( const TBISTR *pStart,
  964. const char *pStr, int MatchLen );
  965. /* String table translate function, pStr is text to translate and Len is
  966. it's length. Value returned may not be a string pointer if the
  967. translation value is really some other type, 64-bit alignment of the return
  968. pointer is guaranteed so almost any type including a structure could be
  969. located with this routine. */
  970. const void *__TBITransStr( const char *pStr, int Len );
  971. /* Arbitrary physical memory access windows, use different Channels to avoid
  972. conflict/thrashing within a single piece of code. */
  973. void *__TBIPhysAccess( int Channel, int PhysAddr, int Bytes );
  974. void __TBIPhysRelease( int Channel, void *pLinAddr );
  975. #ifdef METAC_1_0
  976. /* Data cache function nullified because data cache is off */
  977. #define TBIDCACHE_FLUSH( pAddr )
  978. #define TBIDCACHE_PRELOAD( Type, pAddr ) ((Type) (pAddr))
  979. #define TBIDCACHE_REFRESH( Type, pAddr ) ((Type) (pAddr))
  980. #endif
  981. #ifdef METAC_1_1
  982. /* To flush a single cache line from the data cache using a linear address */
  983. #define TBIDCACHE_FLUSH( pAddr ) ((volatile char *) \
  984. (((unsigned int) (pAddr))>>LINSYSLFLUSH_S))[0] = 0
  985. extern void * __builtin_dcache_preload (void *);
  986. /* Try to ensure that the data at the address concerned is in the cache */
  987. #define TBIDCACHE_PRELOAD( Type, Addr ) \
  988. ((Type) __builtin_dcache_preload ((void *)(Addr)))
  989. extern void * __builtin_dcache_refresh (void *);
  990. /* Flush any old version of data from address and re-load a new copy */
  991. #define TBIDCACHE_REFRESH( Type, Addr ) __extension__ ({ \
  992. Type __addr = (Type)(Addr); \
  993. (void)__builtin_dcache_refresh ((void *)(((unsigned int)(__addr))>>6)); \
  994. __addr; })
  995. #endif
  996. #ifndef METAC_1_0
  997. #ifndef METAC_1_1
  998. /* Support for DCACHE builtin */
  999. extern void __builtin_dcache_flush (void *);
  1000. /* To flush a single cache line from the data cache using a linear address */
  1001. #define TBIDCACHE_FLUSH( Addr ) \
  1002. __builtin_dcache_flush ((void *)(Addr))
  1003. extern void * __builtin_dcache_preload (void *);
  1004. /* Try to ensure that the data at the address concerned is in the cache */
  1005. #define TBIDCACHE_PRELOAD( Type, Addr ) \
  1006. ((Type) __builtin_dcache_preload ((void *)(Addr)))
  1007. extern void * __builtin_dcache_refresh (void *);
  1008. /* Flush any old version of data from address and re-load a new copy */
  1009. #define TBIDCACHE_REFRESH( Type, Addr ) \
  1010. ((Type) __builtin_dcache_refresh ((void *)(Addr)))
  1011. #endif
  1012. #endif
  1013. /* Flush the MMCU cache */
  1014. #define TBIMCACHE_FLUSH() { ((volatile int *) LINSYSCFLUSH_MMCU)[0] = 0; }
  1015. #ifdef METAC_2_1
  1016. /* Obtain the MMU table entry for the specified address */
  1017. #define TBIMTABLE_LEAFDATA(ADDR) TBIXCACHE_RD((int)(ADDR) & (-1<<6))
  1018. #ifndef __ASSEMBLY__
  1019. /* Obtain the full MMU table entry for the specified address */
  1020. #define TBIMTABLE_DATA(ADDR) __extension__ ({ TBIRES __p; \
  1021. __p.Val = TBIXCACHE_RL((int)(ADDR) & (-1<<6)); \
  1022. __p; })
  1023. #endif
  1024. #endif
  1025. /* Combine a physical base address, and a linear address
  1026. * Internal use only
  1027. */
  1028. #define _TBIMTABLE_LIN2PHYS(PHYS, LIN, LMASK) (void*)(((int)(PHYS)&0xFFFFF000)\
  1029. +((int)(LIN)&(LMASK)))
  1030. /* Convert a linear to a physical address */
  1031. #define TBIMTABLE_LIN2PHYS(LEAFDATA, ADDR) \
  1032. (((LEAFDATA) & CRLINPHY0_VAL_BIT) \
  1033. ? _TBIMTABLE_LIN2PHYS(LEAFDATA, ADDR, 0x00000FFF) \
  1034. : 0)
  1035. /* Debug support - using external debugger or host */
  1036. void __TBIDumpSegListEntries( void );
  1037. void __TBILogF( const char *pFmt, ... );
  1038. void __TBIAssert( const char *pFile, int LineNum, const char *pExp );
  1039. void __TBICont( const char *pMsg, ... ); /* TBIAssert -> 'wait for continue' */
  1040. /* Array of signal name data for debug messages */
  1041. extern const char __TBISigNames[];
  1042. #endif /* ifndef __ASSEMBLY__ */
  1043. /* Scale of sub-strings in the __TBISigNames string list */
  1044. #define TBI_SIGNAME_SCALE 4
  1045. #define TBI_SIGNAME_SCALE_S 2
  1046. #define TBI_1_3
  1047. #ifdef TBI_1_3
  1048. #ifndef __ASSEMBLY__
  1049. #define TBIXCACHE_RD(ADDR) __extension__ ({\
  1050. void * __Addr = (void *)(ADDR); \
  1051. int __Data; \
  1052. __asm__ volatile ( "CACHERD\t%0,[%1+#0]" : \
  1053. "=r" (__Data) : "r" (__Addr) ); \
  1054. __Data; })
  1055. #define TBIXCACHE_RL(ADDR) __extension__ ({\
  1056. void * __Addr = (void *)(ADDR); \
  1057. long long __Data; \
  1058. __asm__ volatile ( "CACHERL\t%0,%t0,[%1+#0]" : \
  1059. "=d" (__Data) : "r" (__Addr) ); \
  1060. __Data; })
  1061. #define TBIXCACHE_WD(ADDR, DATA) do {\
  1062. void * __Addr = (void *)(ADDR); \
  1063. int __Data = DATA; \
  1064. __asm__ volatile ( "CACHEWD\t[%0+#0],%1" : \
  1065. : "r" (__Addr), "r" (__Data) ); } while(0)
  1066. #define TBIXCACHE_WL(ADDR, DATA) do {\
  1067. void * __Addr = (void *)(ADDR); \
  1068. long long __Data = DATA; \
  1069. __asm__ volatile ( "CACHEWL\t[%0+#0],%1,%t1" : \
  1070. : "r" (__Addr), "r" (__Data) ); } while(0)
  1071. #ifdef TBI_4_0
  1072. #define TBICACHE_FLUSH_L1D_L2(ADDR) \
  1073. TBIXCACHE_WD(ADDR, CACHEW_FLUSH_L1D_L2)
  1074. #define TBICACHE_WRITEBACK_L1D_L2(ADDR) \
  1075. TBIXCACHE_WD(ADDR, CACHEW_WRITEBACK_L1D_L2)
  1076. #define TBICACHE_INVALIDATE_L1D(ADDR) \
  1077. TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1D)
  1078. #define TBICACHE_INVALIDATE_L1D_L2(ADDR) \
  1079. TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1D_L2)
  1080. #define TBICACHE_INVALIDATE_L1DTLB(ADDR) \
  1081. TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1DTLB)
  1082. #define TBICACHE_INVALIDATE_L1I(ADDR) \
  1083. TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1I)
  1084. #define TBICACHE_INVALIDATE_L1ITLB(ADDR) \
  1085. TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1ITLB)
  1086. #endif /* TBI_4_0 */
  1087. #endif /* ifndef __ASSEMBLY__ */
  1088. /*
  1089. * Calculate linear PC value from real PC and Minim mode control, the LSB of
  1090. * the result returned indicates if address compression has occured.
  1091. */
  1092. #ifndef __ASSEMBLY__
  1093. #define METAG_LINPC( PCVal ) (\
  1094. ( (TBI_GETREG(TXPRIVEXT) & TXPRIVEXT_MINIMON_BIT) != 0 ) ? ( \
  1095. ( ((PCVal) & 0x00900000) == 0x00900000 ) ? \
  1096. (((PCVal) & 0xFFE00000) + (((PCVal) & 0x001FFFFC)>>1) + 1) : \
  1097. ( ((PCVal) & 0x00800000) == 0x00000000 ) ? \
  1098. (((PCVal) & 0xFF800000) + (((PCVal) & 0x007FFFFC)>>1) + 1) : \
  1099. (PCVal) ) \
  1100. : (PCVal) )
  1101. #define METAG_LINPC_X2BIT 0x00000001 /* Make (Size>>1) if compressed */
  1102. /* Convert an arbitrary Linear address into a valid Minim PC or return 0 */
  1103. #define METAG_PCMINIM( LinVal ) (\
  1104. (((LinVal) & 0x00980000) == 0x00880000) ? \
  1105. (((LinVal) & 0xFFE00000) + (((LinVal) & 0x000FFFFE)<<1)) : \
  1106. (((LinVal) & 0x00C00000) == 0x00000000) ? \
  1107. (((LinVal) & 0xFF800000) + (((LinVal) & 0x003FFFFE)<<1)) : 0 )
  1108. /* Reverse a METAG_LINPC conversion step to return the original PCVal */
  1109. #define METAG_PCLIN( LinVal ) ( 0xFFFFFFFC & (\
  1110. ( (LinVal & METAG_LINPC_X2BIT) != 0 ) ? METAG_PCMINIM( LinVal ) : \
  1111. (LinVal) ))
  1112. /*
  1113. * Flush the MMCU Table cache privately for each thread. On cores that do not
  1114. * support per-thread flushing it will flush all threads mapping data.
  1115. */
  1116. #define TBIMCACHE_TFLUSH(Thread) do {\
  1117. ((volatile int *)( LINSYSCFLUSH_TxMMCU_BASE + \
  1118. (LINSYSCFLUSH_TxMMCU_STRIDE*(Thread)) ))[0] = 0; \
  1119. } while(0)
  1120. /*
  1121. * To flush a single linear-matched cache line from the code cache. In
  1122. * cases where Minim is possible the METAC_LINPC operation must be used
  1123. * to pre-process the address being flushed.
  1124. */
  1125. #define TBIICACHE_FLUSH( pAddr ) TBIXCACHE_WD (pAddr, CACHEW_ICACHE_BIT)
  1126. /* To flush a single linear-matched mapping from code/data MMU table cache */
  1127. #define TBIMCACHE_AFLUSH( pAddr, SegType ) \
  1128. TBIXCACHE_WD(pAddr, CACHEW_TLBFLUSH_BIT + ( \
  1129. ((SegType) == TBID_SEGTYPE_TEXT) ? CACHEW_ICACHE_BIT : 0 ))
  1130. /*
  1131. * To flush translation data corresponding to a range of addresses without
  1132. * using TBITCACHE_FLUSH to flush all of this threads translation data. It
  1133. * is necessary to know what stride (>= 4K) must be used to flush a specific
  1134. * region.
  1135. *
  1136. * For example direct mapped regions use the maximum page size (512K) which may
  1137. * mean that only one flush is needed to cover the sub-set of the direct
  1138. * mapped area used since it was setup.
  1139. *
  1140. * The function returns the stride on which flushes should be performed.
  1141. *
  1142. * If 0 is returned then the region is not subject to MMU caching, if -1 is
  1143. * returned then this indicates that only TBIMCACHE_TFLUSH can be used to
  1144. * flush the region concerned rather than TBIMCACHE_AFLUSH which this
  1145. * function is designed to support.
  1146. */
  1147. int __TBIMMUCacheStride( const void *pStart, int Bytes );
  1148. /*
  1149. * This function will use the above lower level functions to achieve a MMU
  1150. * table data flush in an optimal a fashion as possible. On a system that
  1151. * supports linear address based caching this function will also call the
  1152. * code or data cache flush functions to maintain address/data coherency.
  1153. *
  1154. * SegType should be TBID_SEGTYPE_TEXT if the address range is for code or
  1155. * any other value such as TBID_SEGTYPE_DATA for data. If an area is
  1156. * used in both ways then call this function twice; once for each.
  1157. */
  1158. void __TBIMMUCacheFlush( const void *pStart, int Bytes, int SegType );
  1159. /*
  1160. * Cached Core mode setup and flush functions allow one code and one data
  1161. * region of the corresponding global or local cache partion size to be
  1162. * locked into the corresponding cache memory. This prevents normal LRU
  1163. * logic discarding the code or data and avoids write-thru bandwidth in
  1164. * data areas. Code mappings are selected by specifying TBID_SEGTYPE_TEXT
  1165. * for SegType, otherwise data mappings are created.
  1166. *
  1167. * Mode supplied should always contain the VALID bit and WINx selection data.
  1168. * Data areas will be mapped read-only if the WRITE bit is not added.
  1169. *
  1170. * The address returned by the Opt function will either be the same as that
  1171. * passed in (if optimisation cannot be supported) or the base of the new core
  1172. * cached region in linear address space. The returned address must be passed
  1173. * into the End function to remove the mapping when required. If a non-core
  1174. * cached memory address is passed into it the End function has no effect.
  1175. * Note that the region accessed MUST be flushed from the appropriate cache
  1176. * before the End function is called to deliver correct operation.
  1177. */
  1178. void *__TBICoreCacheOpt( const void *pStart, int Bytes, int SegType, int Mode );
  1179. void __TBICoreCacheEnd( const void *pOpt, int Bytes, int SegType );
  1180. /*
  1181. * Optimise physical access channel and flush side effects before releasing
  1182. * the channel. If pStart is NULL the whole region must be flushed and this is
  1183. * done automatically by the channel release function if optimisation is
  1184. * enabled. Flushing the specific region that may have been accessed before
  1185. * release should optimises this process. On physically cached systems we do
  1186. * not flush the code/data caches only the MMU table data needs flushing.
  1187. */
  1188. void __TBIPhysOptim( int Channel, int IMode, int DMode );
  1189. void __TBIPhysFlush( int Channel, const void *pStart, int Bytes );
  1190. #endif
  1191. #endif /* ifdef TBI_1_3 */
  1192. #endif /* _ASM_METAG_TBX_H_ */