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/drivers/scsi/mpt2sas/mpt2sas_base.c

https://bitbucket.org/abioy/linux
C | 3819 lines | 2660 code | 437 blank | 722 comment | 369 complexity | d38806ed30cbbad5f34e536fb2833842 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt2sas/mpt2_base.c
  6. * Copyright (C) 2007-2009 LSI Corporation
  7. * (mailto:DL-MPTFusionLinux@lsi.com)
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * NO WARRANTY
  20. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  21. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  22. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  23. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  24. * solely responsible for determining the appropriateness of using and
  25. * distributing the Program and assumes all risks associated with its
  26. * exercise of rights under this Agreement, including but not limited to
  27. * the risks and costs of program errors, damage to or loss of data,
  28. * programs or equipment, and unavailability or interruption of operations.
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. * You should have received a copy of the GNU General Public License
  38. * along with this program; if not, write to the Free Software
  39. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  40. * USA.
  41. */
  42. #include <linux/version.h>
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/sort.h>
  56. #include <linux/io.h>
  57. #include <linux/time.h>
  58. #include "mpt2sas_base.h"
  59. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  60. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  61. #define MPT2SAS_MAX_REQUEST_QUEUE 600 /* maximum controller queue depth */
  62. static int max_queue_depth = -1;
  63. module_param(max_queue_depth, int, 0);
  64. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  65. static int max_sgl_entries = -1;
  66. module_param(max_sgl_entries, int, 0);
  67. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  68. static int msix_disable = -1;
  69. module_param(msix_disable, int, 0);
  70. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  71. /* diag_buffer_enable is bitwise
  72. * bit 0 set = TRACE
  73. * bit 1 set = SNAPSHOT
  74. * bit 2 set = EXTENDED
  75. *
  76. * Either bit can be set, or both
  77. */
  78. static int diag_buffer_enable;
  79. module_param(diag_buffer_enable, int, 0);
  80. MODULE_PARM_DESC(diag_buffer_enable, " post diag buffers "
  81. "(TRACE=1/SNAPSHOT=2/EXTENDED=4/default=0)");
  82. int mpt2sas_fwfault_debug;
  83. MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
  84. "and halt firmware - (default=0)");
  85. /**
  86. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  87. *
  88. */
  89. static int
  90. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  91. {
  92. int ret = param_set_int(val, kp);
  93. struct MPT2SAS_ADAPTER *ioc;
  94. if (ret)
  95. return ret;
  96. printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
  97. list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
  98. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  99. return 0;
  100. }
  101. module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
  102. param_get_int, &mpt2sas_fwfault_debug, 0644);
  103. /**
  104. * _base_fault_reset_work - workq handling ioc fault conditions
  105. * @work: input argument, used to derive ioc
  106. * Context: sleep.
  107. *
  108. * Return nothing.
  109. */
  110. static void
  111. _base_fault_reset_work(struct work_struct *work)
  112. {
  113. struct MPT2SAS_ADAPTER *ioc =
  114. container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
  115. unsigned long flags;
  116. u32 doorbell;
  117. int rc;
  118. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  119. if (ioc->shost_recovery)
  120. goto rearm_timer;
  121. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  122. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  123. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  124. rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  125. FORCE_BIG_HAMMER);
  126. printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
  127. __func__, (rc == 0) ? "success" : "failed");
  128. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  129. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  130. mpt2sas_base_fault_info(ioc, doorbell &
  131. MPI2_DOORBELL_DATA_MASK);
  132. }
  133. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  134. rearm_timer:
  135. if (ioc->fault_reset_work_q)
  136. queue_delayed_work(ioc->fault_reset_work_q,
  137. &ioc->fault_reset_work,
  138. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  139. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  140. }
  141. /**
  142. * mpt2sas_base_start_watchdog - start the fault_reset_work_q
  143. * @ioc: per adapter object
  144. * Context: sleep.
  145. *
  146. * Return nothing.
  147. */
  148. void
  149. mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
  150. {
  151. unsigned long flags;
  152. if (ioc->fault_reset_work_q)
  153. return;
  154. /* initialize fault polling */
  155. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  156. snprintf(ioc->fault_reset_work_q_name,
  157. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  158. ioc->fault_reset_work_q =
  159. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  160. if (!ioc->fault_reset_work_q) {
  161. printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
  162. ioc->name, __func__, __LINE__);
  163. return;
  164. }
  165. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  166. if (ioc->fault_reset_work_q)
  167. queue_delayed_work(ioc->fault_reset_work_q,
  168. &ioc->fault_reset_work,
  169. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  170. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  171. }
  172. /**
  173. * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q
  174. * @ioc: per adapter object
  175. * Context: sleep.
  176. *
  177. * Return nothing.
  178. */
  179. void
  180. mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
  181. {
  182. unsigned long flags;
  183. struct workqueue_struct *wq;
  184. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  185. wq = ioc->fault_reset_work_q;
  186. ioc->fault_reset_work_q = NULL;
  187. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  188. if (wq) {
  189. if (!cancel_delayed_work(&ioc->fault_reset_work))
  190. flush_workqueue(wq);
  191. destroy_workqueue(wq);
  192. }
  193. }
  194. /**
  195. * mpt2sas_base_fault_info - verbose translation of firmware FAULT code
  196. * @ioc: per adapter object
  197. * @fault_code: fault code
  198. *
  199. * Return nothing.
  200. */
  201. void
  202. mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
  203. {
  204. printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
  205. ioc->name, fault_code);
  206. }
  207. /**
  208. * mpt2sas_halt_firmware - halt's mpt controller firmware
  209. * @ioc: per adapter object
  210. *
  211. * For debugging timeout related issues. Writing 0xCOFFEE00
  212. * to the doorbell register will halt controller firmware. With
  213. * the purpose to stop both driver and firmware, the enduser can
  214. * obtain a ring buffer from controller UART.
  215. */
  216. void
  217. mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
  218. {
  219. u32 doorbell;
  220. if (!ioc->fwfault_debug)
  221. return;
  222. dump_stack();
  223. doorbell = readl(&ioc->chip->Doorbell);
  224. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  225. mpt2sas_base_fault_info(ioc , doorbell);
  226. else {
  227. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  228. printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
  229. "timeout\n", ioc->name);
  230. }
  231. panic("panic in %s\n", __func__);
  232. }
  233. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  234. /**
  235. * _base_sas_ioc_info - verbose translation of the ioc status
  236. * @ioc: per adapter object
  237. * @mpi_reply: reply mf payload returned from firmware
  238. * @request_hdr: request mf
  239. *
  240. * Return nothing.
  241. */
  242. static void
  243. _base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  244. MPI2RequestHeader_t *request_hdr)
  245. {
  246. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  247. MPI2_IOCSTATUS_MASK;
  248. char *desc = NULL;
  249. u16 frame_sz;
  250. char *func_str = NULL;
  251. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  252. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  253. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  254. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  255. return;
  256. switch (ioc_status) {
  257. /****************************************************************************
  258. * Common IOCStatus values for all replies
  259. ****************************************************************************/
  260. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  261. desc = "invalid function";
  262. break;
  263. case MPI2_IOCSTATUS_BUSY:
  264. desc = "busy";
  265. break;
  266. case MPI2_IOCSTATUS_INVALID_SGL:
  267. desc = "invalid sgl";
  268. break;
  269. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  270. desc = "internal error";
  271. break;
  272. case MPI2_IOCSTATUS_INVALID_VPID:
  273. desc = "invalid vpid";
  274. break;
  275. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  276. desc = "insufficient resources";
  277. break;
  278. case MPI2_IOCSTATUS_INVALID_FIELD:
  279. desc = "invalid field";
  280. break;
  281. case MPI2_IOCSTATUS_INVALID_STATE:
  282. desc = "invalid state";
  283. break;
  284. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  285. desc = "op state not supported";
  286. break;
  287. /****************************************************************************
  288. * Config IOCStatus values
  289. ****************************************************************************/
  290. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  291. desc = "config invalid action";
  292. break;
  293. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  294. desc = "config invalid type";
  295. break;
  296. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  297. desc = "config invalid page";
  298. break;
  299. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  300. desc = "config invalid data";
  301. break;
  302. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  303. desc = "config no defaults";
  304. break;
  305. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  306. desc = "config cant commit";
  307. break;
  308. /****************************************************************************
  309. * SCSI IO Reply
  310. ****************************************************************************/
  311. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  312. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  313. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  314. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  315. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  316. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  317. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  318. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  319. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  320. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  321. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  322. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  323. break;
  324. /****************************************************************************
  325. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  326. ****************************************************************************/
  327. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  328. desc = "eedp guard error";
  329. break;
  330. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  331. desc = "eedp ref tag error";
  332. break;
  333. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  334. desc = "eedp app tag error";
  335. break;
  336. /****************************************************************************
  337. * SCSI Target values
  338. ****************************************************************************/
  339. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  340. desc = "target invalid io index";
  341. break;
  342. case MPI2_IOCSTATUS_TARGET_ABORTED:
  343. desc = "target aborted";
  344. break;
  345. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  346. desc = "target no conn retryable";
  347. break;
  348. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  349. desc = "target no connection";
  350. break;
  351. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  352. desc = "target xfer count mismatch";
  353. break;
  354. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  355. desc = "target data offset error";
  356. break;
  357. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  358. desc = "target too much write data";
  359. break;
  360. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  361. desc = "target iu too short";
  362. break;
  363. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  364. desc = "target ack nak timeout";
  365. break;
  366. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  367. desc = "target nak received";
  368. break;
  369. /****************************************************************************
  370. * Serial Attached SCSI values
  371. ****************************************************************************/
  372. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  373. desc = "smp request failed";
  374. break;
  375. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  376. desc = "smp data overrun";
  377. break;
  378. /****************************************************************************
  379. * Diagnostic Buffer Post / Diagnostic Release values
  380. ****************************************************************************/
  381. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  382. desc = "diagnostic released";
  383. break;
  384. default:
  385. break;
  386. }
  387. if (!desc)
  388. return;
  389. switch (request_hdr->Function) {
  390. case MPI2_FUNCTION_CONFIG:
  391. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  392. func_str = "config_page";
  393. break;
  394. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  395. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  396. func_str = "task_mgmt";
  397. break;
  398. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  399. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  400. func_str = "sas_iounit_ctl";
  401. break;
  402. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  403. frame_sz = sizeof(Mpi2SepRequest_t);
  404. func_str = "enclosure";
  405. break;
  406. case MPI2_FUNCTION_IOC_INIT:
  407. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  408. func_str = "ioc_init";
  409. break;
  410. case MPI2_FUNCTION_PORT_ENABLE:
  411. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  412. func_str = "port_enable";
  413. break;
  414. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  415. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  416. func_str = "smp_passthru";
  417. break;
  418. default:
  419. frame_sz = 32;
  420. func_str = "unknown";
  421. break;
  422. }
  423. printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
  424. " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
  425. _debug_dump_mf(request_hdr, frame_sz/4);
  426. }
  427. /**
  428. * _base_display_event_data - verbose translation of firmware asyn events
  429. * @ioc: per adapter object
  430. * @mpi_reply: reply mf payload returned from firmware
  431. *
  432. * Return nothing.
  433. */
  434. static void
  435. _base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
  436. Mpi2EventNotificationReply_t *mpi_reply)
  437. {
  438. char *desc = NULL;
  439. u16 event;
  440. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  441. return;
  442. event = le16_to_cpu(mpi_reply->Event);
  443. switch (event) {
  444. case MPI2_EVENT_LOG_DATA:
  445. desc = "Log Data";
  446. break;
  447. case MPI2_EVENT_STATE_CHANGE:
  448. desc = "Status Change";
  449. break;
  450. case MPI2_EVENT_HARD_RESET_RECEIVED:
  451. desc = "Hard Reset Received";
  452. break;
  453. case MPI2_EVENT_EVENT_CHANGE:
  454. desc = "Event Change";
  455. break;
  456. case MPI2_EVENT_TASK_SET_FULL:
  457. desc = "Task Set Full";
  458. break;
  459. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  460. desc = "Device Status Change";
  461. break;
  462. case MPI2_EVENT_IR_OPERATION_STATUS:
  463. desc = "IR Operation Status";
  464. break;
  465. case MPI2_EVENT_SAS_DISCOVERY:
  466. desc = "Discovery";
  467. break;
  468. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  469. desc = "SAS Broadcast Primitive";
  470. break;
  471. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  472. desc = "SAS Init Device Status Change";
  473. break;
  474. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  475. desc = "SAS Init Table Overflow";
  476. break;
  477. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  478. desc = "SAS Topology Change List";
  479. break;
  480. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  481. desc = "SAS Enclosure Device Status Change";
  482. break;
  483. case MPI2_EVENT_IR_VOLUME:
  484. desc = "IR Volume";
  485. break;
  486. case MPI2_EVENT_IR_PHYSICAL_DISK:
  487. desc = "IR Physical Disk";
  488. break;
  489. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  490. desc = "IR Configuration Change List";
  491. break;
  492. case MPI2_EVENT_LOG_ENTRY_ADDED:
  493. desc = "Log Entry Added";
  494. break;
  495. }
  496. if (!desc)
  497. return;
  498. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
  499. }
  500. #endif
  501. /**
  502. * _base_sas_log_info - verbose translation of firmware log info
  503. * @ioc: per adapter object
  504. * @log_info: log info
  505. *
  506. * Return nothing.
  507. */
  508. static void
  509. _base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
  510. {
  511. union loginfo_type {
  512. u32 loginfo;
  513. struct {
  514. u32 subcode:16;
  515. u32 code:8;
  516. u32 originator:4;
  517. u32 bus_type:4;
  518. } dw;
  519. };
  520. union loginfo_type sas_loginfo;
  521. char *originator_str = NULL;
  522. sas_loginfo.loginfo = log_info;
  523. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  524. return;
  525. /* each nexus loss loginfo */
  526. if (log_info == 0x31170000)
  527. return;
  528. /* eat the loginfos associated with task aborts */
  529. if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
  530. 0x31140000 || log_info == 0x31130000))
  531. return;
  532. switch (sas_loginfo.dw.originator) {
  533. case 0:
  534. originator_str = "IOP";
  535. break;
  536. case 1:
  537. originator_str = "PL";
  538. break;
  539. case 2:
  540. originator_str = "IR";
  541. break;
  542. }
  543. printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
  544. "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
  545. originator_str, sas_loginfo.dw.code,
  546. sas_loginfo.dw.subcode);
  547. }
  548. /**
  549. * _base_display_reply_info -
  550. * @ioc: per adapter object
  551. * @smid: system request message index
  552. * @msix_index: MSIX table index supplied by the OS
  553. * @reply: reply message frame(lower 32bit addr)
  554. *
  555. * Return nothing.
  556. */
  557. static void
  558. _base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  559. u32 reply)
  560. {
  561. MPI2DefaultReply_t *mpi_reply;
  562. u16 ioc_status;
  563. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  564. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  565. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  566. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  567. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  568. _base_sas_ioc_info(ioc , mpi_reply,
  569. mpt2sas_base_get_msg_frame(ioc, smid));
  570. }
  571. #endif
  572. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
  573. _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
  574. }
  575. /**
  576. * mpt2sas_base_done - base internal command completion routine
  577. * @ioc: per adapter object
  578. * @smid: system request message index
  579. * @msix_index: MSIX table index supplied by the OS
  580. * @reply: reply message frame(lower 32bit addr)
  581. *
  582. * Return 1 meaning mf should be freed from _base_interrupt
  583. * 0 means the mf is freed from this function.
  584. */
  585. u8
  586. mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  587. u32 reply)
  588. {
  589. MPI2DefaultReply_t *mpi_reply;
  590. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  591. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  592. return 1;
  593. if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
  594. return 1;
  595. ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
  596. if (mpi_reply) {
  597. ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
  598. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  599. }
  600. ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
  601. complete(&ioc->base_cmds.done);
  602. return 1;
  603. }
  604. /**
  605. * _base_async_event - main callback handler for firmware asyn events
  606. * @ioc: per adapter object
  607. * @msix_index: MSIX table index supplied by the OS
  608. * @reply: reply message frame(lower 32bit addr)
  609. *
  610. * Return 1 meaning mf should be freed from _base_interrupt
  611. * 0 means the mf is freed from this function.
  612. */
  613. static u8
  614. _base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  615. {
  616. Mpi2EventNotificationReply_t *mpi_reply;
  617. Mpi2EventAckRequest_t *ack_request;
  618. u16 smid;
  619. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  620. if (!mpi_reply)
  621. return 1;
  622. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  623. return 1;
  624. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  625. _base_display_event_data(ioc, mpi_reply);
  626. #endif
  627. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  628. goto out;
  629. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  630. if (!smid) {
  631. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  632. ioc->name, __func__);
  633. goto out;
  634. }
  635. ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
  636. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  637. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  638. ack_request->Event = mpi_reply->Event;
  639. ack_request->EventContext = mpi_reply->EventContext;
  640. ack_request->VF_ID = 0; /* TODO */
  641. ack_request->VP_ID = 0;
  642. mpt2sas_base_put_smid_default(ioc, smid);
  643. out:
  644. /* scsih callback handler */
  645. mpt2sas_scsih_event_callback(ioc, msix_index, reply);
  646. /* ctl callback handler */
  647. mpt2sas_ctl_event_callback(ioc, msix_index, reply);
  648. return 1;
  649. }
  650. /**
  651. * _base_get_cb_idx - obtain the callback index
  652. * @ioc: per adapter object
  653. * @smid: system request message index
  654. *
  655. * Return callback index.
  656. */
  657. static u8
  658. _base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  659. {
  660. int i;
  661. u8 cb_idx = 0xFF;
  662. if (smid >= ioc->hi_priority_smid) {
  663. if (smid < ioc->internal_smid) {
  664. i = smid - ioc->hi_priority_smid;
  665. cb_idx = ioc->hpr_lookup[i].cb_idx;
  666. } else {
  667. i = smid - ioc->internal_smid;
  668. cb_idx = ioc->internal_lookup[i].cb_idx;
  669. }
  670. } else {
  671. i = smid - 1;
  672. cb_idx = ioc->scsi_lookup[i].cb_idx;
  673. }
  674. return cb_idx;
  675. }
  676. /**
  677. * _base_mask_interrupts - disable interrupts
  678. * @ioc: per adapter object
  679. *
  680. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  681. *
  682. * Return nothing.
  683. */
  684. static void
  685. _base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  686. {
  687. u32 him_register;
  688. ioc->mask_interrupts = 1;
  689. him_register = readl(&ioc->chip->HostInterruptMask);
  690. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  691. writel(him_register, &ioc->chip->HostInterruptMask);
  692. readl(&ioc->chip->HostInterruptMask);
  693. }
  694. /**
  695. * _base_unmask_interrupts - enable interrupts
  696. * @ioc: per adapter object
  697. *
  698. * Enabling only Reply Interrupts
  699. *
  700. * Return nothing.
  701. */
  702. static void
  703. _base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  704. {
  705. u32 him_register;
  706. him_register = readl(&ioc->chip->HostInterruptMask);
  707. him_register &= ~MPI2_HIM_RIM;
  708. writel(him_register, &ioc->chip->HostInterruptMask);
  709. ioc->mask_interrupts = 0;
  710. }
  711. union reply_descriptor {
  712. u64 word;
  713. struct {
  714. u32 low;
  715. u32 high;
  716. } u;
  717. };
  718. /**
  719. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  720. * @irq: irq number (not used)
  721. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  722. * @r: pt_regs pointer (not used)
  723. *
  724. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  725. */
  726. static irqreturn_t
  727. _base_interrupt(int irq, void *bus_id)
  728. {
  729. union reply_descriptor rd;
  730. u32 completed_cmds;
  731. u8 request_desript_type;
  732. u16 smid;
  733. u8 cb_idx;
  734. u32 reply;
  735. u8 msix_index;
  736. struct MPT2SAS_ADAPTER *ioc = bus_id;
  737. Mpi2ReplyDescriptorsUnion_t *rpf;
  738. u8 rc;
  739. if (ioc->mask_interrupts)
  740. return IRQ_NONE;
  741. rpf = &ioc->reply_post_free[ioc->reply_post_host_index];
  742. request_desript_type = rpf->Default.ReplyFlags
  743. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  744. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  745. return IRQ_NONE;
  746. completed_cmds = 0;
  747. do {
  748. rd.word = rpf->Words;
  749. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  750. goto out;
  751. reply = 0;
  752. cb_idx = 0xFF;
  753. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  754. msix_index = rpf->Default.MSIxIndex;
  755. if (request_desript_type ==
  756. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  757. reply = le32_to_cpu
  758. (rpf->AddressReply.ReplyFrameAddress);
  759. } else if (request_desript_type ==
  760. MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
  761. goto next;
  762. else if (request_desript_type ==
  763. MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
  764. goto next;
  765. if (smid)
  766. cb_idx = _base_get_cb_idx(ioc, smid);
  767. if (smid && cb_idx != 0xFF) {
  768. rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
  769. reply);
  770. if (reply)
  771. _base_display_reply_info(ioc, smid, msix_index,
  772. reply);
  773. if (rc)
  774. mpt2sas_base_free_smid(ioc, smid);
  775. }
  776. if (!smid)
  777. _base_async_event(ioc, msix_index, reply);
  778. /* reply free queue handling */
  779. if (reply) {
  780. ioc->reply_free_host_index =
  781. (ioc->reply_free_host_index ==
  782. (ioc->reply_free_queue_depth - 1)) ?
  783. 0 : ioc->reply_free_host_index + 1;
  784. ioc->reply_free[ioc->reply_free_host_index] =
  785. cpu_to_le32(reply);
  786. wmb();
  787. writel(ioc->reply_free_host_index,
  788. &ioc->chip->ReplyFreeHostIndex);
  789. }
  790. next:
  791. rpf->Words = ULLONG_MAX;
  792. ioc->reply_post_host_index = (ioc->reply_post_host_index ==
  793. (ioc->reply_post_queue_depth - 1)) ? 0 :
  794. ioc->reply_post_host_index + 1;
  795. request_desript_type =
  796. ioc->reply_post_free[ioc->reply_post_host_index].Default.
  797. ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  798. completed_cmds++;
  799. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  800. goto out;
  801. if (!ioc->reply_post_host_index)
  802. rpf = ioc->reply_post_free;
  803. else
  804. rpf++;
  805. } while (1);
  806. out:
  807. if (!completed_cmds)
  808. return IRQ_NONE;
  809. wmb();
  810. writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex);
  811. return IRQ_HANDLED;
  812. }
  813. /**
  814. * mpt2sas_base_release_callback_handler - clear interupt callback handler
  815. * @cb_idx: callback index
  816. *
  817. * Return nothing.
  818. */
  819. void
  820. mpt2sas_base_release_callback_handler(u8 cb_idx)
  821. {
  822. mpt_callbacks[cb_idx] = NULL;
  823. }
  824. /**
  825. * mpt2sas_base_register_callback_handler - obtain index for the interrupt callback handler
  826. * @cb_func: callback function
  827. *
  828. * Returns cb_func.
  829. */
  830. u8
  831. mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  832. {
  833. u8 cb_idx;
  834. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  835. if (mpt_callbacks[cb_idx] == NULL)
  836. break;
  837. mpt_callbacks[cb_idx] = cb_func;
  838. return cb_idx;
  839. }
  840. /**
  841. * mpt2sas_base_initialize_callback_handler - initialize the interrupt callback handler
  842. *
  843. * Return nothing.
  844. */
  845. void
  846. mpt2sas_base_initialize_callback_handler(void)
  847. {
  848. u8 cb_idx;
  849. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  850. mpt2sas_base_release_callback_handler(cb_idx);
  851. }
  852. /**
  853. * mpt2sas_base_build_zero_len_sge - build zero length sg entry
  854. * @ioc: per adapter object
  855. * @paddr: virtual address for SGE
  856. *
  857. * Create a zero length scatter gather entry to insure the IOCs hardware has
  858. * something to use if the target device goes brain dead and tries
  859. * to send data even when none is asked for.
  860. *
  861. * Return nothing.
  862. */
  863. void
  864. mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
  865. {
  866. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  867. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  868. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  869. MPI2_SGE_FLAGS_SHIFT);
  870. ioc->base_add_sg_single(paddr, flags_length, -1);
  871. }
  872. /**
  873. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  874. * @paddr: virtual address for SGE
  875. * @flags_length: SGE flags and data transfer length
  876. * @dma_addr: Physical address
  877. *
  878. * Return nothing.
  879. */
  880. static void
  881. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  882. {
  883. Mpi2SGESimple32_t *sgel = paddr;
  884. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  885. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  886. sgel->FlagsLength = cpu_to_le32(flags_length);
  887. sgel->Address = cpu_to_le32(dma_addr);
  888. }
  889. /**
  890. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  891. * @paddr: virtual address for SGE
  892. * @flags_length: SGE flags and data transfer length
  893. * @dma_addr: Physical address
  894. *
  895. * Return nothing.
  896. */
  897. static void
  898. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  899. {
  900. Mpi2SGESimple64_t *sgel = paddr;
  901. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  902. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  903. sgel->FlagsLength = cpu_to_le32(flags_length);
  904. sgel->Address = cpu_to_le64(dma_addr);
  905. }
  906. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  907. /**
  908. * _base_config_dma_addressing - set dma addressing
  909. * @ioc: per adapter object
  910. * @pdev: PCI device struct
  911. *
  912. * Returns 0 for success, non-zero for failure.
  913. */
  914. static int
  915. _base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
  916. {
  917. struct sysinfo s;
  918. char *desc = NULL;
  919. if (sizeof(dma_addr_t) > 4) {
  920. const uint64_t required_mask =
  921. dma_get_required_mask(&pdev->dev);
  922. if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
  923. DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
  924. DMA_BIT_MASK(64))) {
  925. ioc->base_add_sg_single = &_base_add_sg_single_64;
  926. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  927. desc = "64";
  928. goto out;
  929. }
  930. }
  931. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  932. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  933. ioc->base_add_sg_single = &_base_add_sg_single_32;
  934. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  935. desc = "32";
  936. } else
  937. return -ENODEV;
  938. out:
  939. si_meminfo(&s);
  940. printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
  941. "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
  942. return 0;
  943. }
  944. /**
  945. * _base_save_msix_table - backup msix vector table
  946. * @ioc: per adapter object
  947. *
  948. * This address an errata where diag reset clears out the table
  949. */
  950. static void
  951. _base_save_msix_table(struct MPT2SAS_ADAPTER *ioc)
  952. {
  953. int i;
  954. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  955. return;
  956. for (i = 0; i < ioc->msix_vector_count; i++)
  957. ioc->msix_table_backup[i] = ioc->msix_table[i];
  958. }
  959. /**
  960. * _base_restore_msix_table - this restores the msix vector table
  961. * @ioc: per adapter object
  962. *
  963. */
  964. static void
  965. _base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc)
  966. {
  967. int i;
  968. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  969. return;
  970. for (i = 0; i < ioc->msix_vector_count; i++)
  971. ioc->msix_table[i] = ioc->msix_table_backup[i];
  972. }
  973. /**
  974. * _base_check_enable_msix - checks MSIX capabable.
  975. * @ioc: per adapter object
  976. *
  977. * Check to see if card is capable of MSIX, and set number
  978. * of avaliable msix vectors
  979. */
  980. static int
  981. _base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  982. {
  983. int base;
  984. u16 message_control;
  985. u32 msix_table_offset;
  986. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  987. if (!base) {
  988. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
  989. "supported\n", ioc->name));
  990. return -EINVAL;
  991. }
  992. /* get msix vector count */
  993. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  994. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  995. /* get msix table */
  996. pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset);
  997. msix_table_offset &= 0xFFFFFFF8;
  998. ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset);
  999. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
  1000. "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name,
  1001. ioc->msix_vector_count, msix_table_offset, ioc->msix_table));
  1002. return 0;
  1003. }
  1004. /**
  1005. * _base_disable_msix - disables msix
  1006. * @ioc: per adapter object
  1007. *
  1008. */
  1009. static void
  1010. _base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
  1011. {
  1012. if (ioc->msix_enable) {
  1013. pci_disable_msix(ioc->pdev);
  1014. kfree(ioc->msix_table_backup);
  1015. ioc->msix_table_backup = NULL;
  1016. ioc->msix_enable = 0;
  1017. }
  1018. }
  1019. /**
  1020. * _base_enable_msix - enables msix, failback to io_apic
  1021. * @ioc: per adapter object
  1022. *
  1023. */
  1024. static int
  1025. _base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1026. {
  1027. struct msix_entry entries;
  1028. int r;
  1029. u8 try_msix = 0;
  1030. if (msix_disable == -1 || msix_disable == 0)
  1031. try_msix = 1;
  1032. if (!try_msix)
  1033. goto try_ioapic;
  1034. if (_base_check_enable_msix(ioc) != 0)
  1035. goto try_ioapic;
  1036. ioc->msix_table_backup = kcalloc(ioc->msix_vector_count,
  1037. sizeof(u32), GFP_KERNEL);
  1038. if (!ioc->msix_table_backup) {
  1039. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
  1040. "msix_table_backup failed!!!\n", ioc->name));
  1041. goto try_ioapic;
  1042. }
  1043. memset(&entries, 0, sizeof(struct msix_entry));
  1044. r = pci_enable_msix(ioc->pdev, &entries, 1);
  1045. if (r) {
  1046. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
  1047. "failed (r=%d) !!!\n", ioc->name, r));
  1048. goto try_ioapic;
  1049. }
  1050. r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED,
  1051. ioc->name, ioc);
  1052. if (r) {
  1053. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate "
  1054. "interrupt %d !!!\n", ioc->name, entries.vector));
  1055. pci_disable_msix(ioc->pdev);
  1056. goto try_ioapic;
  1057. }
  1058. ioc->pci_irq = entries.vector;
  1059. ioc->msix_enable = 1;
  1060. return 0;
  1061. /* failback to io_apic interrupt routing */
  1062. try_ioapic:
  1063. r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED,
  1064. ioc->name, ioc);
  1065. if (r) {
  1066. printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
  1067. ioc->name, ioc->pdev->irq);
  1068. r = -EBUSY;
  1069. goto out_fail;
  1070. }
  1071. ioc->pci_irq = ioc->pdev->irq;
  1072. return 0;
  1073. out_fail:
  1074. return r;
  1075. }
  1076. /**
  1077. * mpt2sas_base_map_resources - map in controller resources (io/irq/memap)
  1078. * @ioc: per adapter object
  1079. *
  1080. * Returns 0 for success, non-zero for failure.
  1081. */
  1082. int
  1083. mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
  1084. {
  1085. struct pci_dev *pdev = ioc->pdev;
  1086. u32 memap_sz;
  1087. u32 pio_sz;
  1088. int i, r = 0;
  1089. u64 pio_chip = 0;
  1090. u64 chip_phys = 0;
  1091. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n",
  1092. ioc->name, __func__));
  1093. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1094. if (pci_enable_device_mem(pdev)) {
  1095. printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
  1096. "failed\n", ioc->name);
  1097. return -ENODEV;
  1098. }
  1099. if (pci_request_selected_regions(pdev, ioc->bars,
  1100. MPT2SAS_DRIVER_NAME)) {
  1101. printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
  1102. "failed\n", ioc->name);
  1103. r = -ENODEV;
  1104. goto out_fail;
  1105. }
  1106. pci_set_master(pdev);
  1107. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1108. printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
  1109. ioc->name, pci_name(pdev));
  1110. r = -ENODEV;
  1111. goto out_fail;
  1112. }
  1113. for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
  1114. if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO) {
  1115. if (pio_sz)
  1116. continue;
  1117. pio_chip = (u64)pci_resource_start(pdev, i);
  1118. pio_sz = pci_resource_len(pdev, i);
  1119. } else {
  1120. if (memap_sz)
  1121. continue;
  1122. ioc->chip_phys = pci_resource_start(pdev, i);
  1123. chip_phys = (u64)ioc->chip_phys;
  1124. memap_sz = pci_resource_len(pdev, i);
  1125. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1126. if (ioc->chip == NULL) {
  1127. printk(MPT2SAS_ERR_FMT "unable to map adapter "
  1128. "memory!\n", ioc->name);
  1129. r = -EINVAL;
  1130. goto out_fail;
  1131. }
  1132. }
  1133. }
  1134. _base_mask_interrupts(ioc);
  1135. r = _base_enable_msix(ioc);
  1136. if (r)
  1137. goto out_fail;
  1138. printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
  1139. ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1140. "IO-APIC enabled"), ioc->pci_irq);
  1141. printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1142. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1143. printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
  1144. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1145. return 0;
  1146. out_fail:
  1147. if (ioc->chip_phys)
  1148. iounmap(ioc->chip);
  1149. ioc->chip_phys = 0;
  1150. ioc->pci_irq = -1;
  1151. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1152. pci_disable_device(pdev);
  1153. return r;
  1154. }
  1155. /**
  1156. * mpt2sas_base_get_msg_frame - obtain request mf pointer
  1157. * @ioc: per adapter object
  1158. * @smid: system request message index(smid zero is invalid)
  1159. *
  1160. * Returns virt pointer to message frame.
  1161. */
  1162. void *
  1163. mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1164. {
  1165. return (void *)(ioc->request + (smid * ioc->request_sz));
  1166. }
  1167. /**
  1168. * mpt2sas_base_get_sense_buffer - obtain a sense buffer assigned to a mf request
  1169. * @ioc: per adapter object
  1170. * @smid: system request message index
  1171. *
  1172. * Returns virt pointer to sense buffer.
  1173. */
  1174. void *
  1175. mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1176. {
  1177. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1178. }
  1179. /**
  1180. * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer assigned to a mf request
  1181. * @ioc: per adapter object
  1182. * @smid: system request message index
  1183. *
  1184. * Returns phys pointer to the low 32bit address of the sense buffer.
  1185. */
  1186. __le32
  1187. mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1188. {
  1189. return cpu_to_le32(ioc->sense_dma +
  1190. ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1191. }
  1192. /**
  1193. * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address
  1194. * @ioc: per adapter object
  1195. * @phys_addr: lower 32 physical addr of the reply
  1196. *
  1197. * Converts 32bit lower physical addr into a virt address.
  1198. */
  1199. void *
  1200. mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
  1201. {
  1202. if (!phys_addr)
  1203. return NULL;
  1204. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1205. }
  1206. /**
  1207. * mpt2sas_base_get_smid - obtain a free smid from internal queue
  1208. * @ioc: per adapter object
  1209. * @cb_idx: callback index
  1210. *
  1211. * Returns smid (zero is invalid)
  1212. */
  1213. u16
  1214. mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1215. {
  1216. unsigned long flags;
  1217. struct request_tracker *request;
  1218. u16 smid;
  1219. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1220. if (list_empty(&ioc->internal_free_list)) {
  1221. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1222. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1223. ioc->name, __func__);
  1224. return 0;
  1225. }
  1226. request = list_entry(ioc->internal_free_list.next,
  1227. struct request_tracker, tracker_list);
  1228. request->cb_idx = cb_idx;
  1229. smid = request->smid;
  1230. list_del(&request->tracker_list);
  1231. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1232. return smid;
  1233. }
  1234. /**
  1235. * mpt2sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1236. * @ioc: per adapter object
  1237. * @cb_idx: callback index
  1238. * @scmd: pointer to scsi command object
  1239. *
  1240. * Returns smid (zero is invalid)
  1241. */
  1242. u16
  1243. mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
  1244. struct scsi_cmnd *scmd)
  1245. {
  1246. unsigned long flags;
  1247. struct request_tracker *request;
  1248. u16 smid;
  1249. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1250. if (list_empty(&ioc->free_list)) {
  1251. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1252. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1253. ioc->name, __func__);
  1254. return 0;
  1255. }
  1256. request = list_entry(ioc->free_list.next,
  1257. struct request_tracker, tracker_list);
  1258. request->scmd = scmd;
  1259. request->cb_idx = cb_idx;
  1260. smid = request->smid;
  1261. list_del(&request->tracker_list);
  1262. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1263. return smid;
  1264. }
  1265. /**
  1266. * mpt2sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1267. * @ioc: per adapter object
  1268. * @cb_idx: callback index
  1269. *
  1270. * Returns smid (zero is invalid)
  1271. */
  1272. u16
  1273. mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1274. {
  1275. unsigned long flags;
  1276. struct request_tracker *request;
  1277. u16 smid;
  1278. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1279. if (list_empty(&ioc->hpr_free_list)) {
  1280. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1281. return 0;
  1282. }
  1283. request = list_entry(ioc->hpr_free_list.next,
  1284. struct request_tracker, tracker_list);
  1285. request->cb_idx = cb_idx;
  1286. smid = request->smid;
  1287. list_del(&request->tracker_list);
  1288. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1289. return smid;
  1290. }
  1291. /**
  1292. * mpt2sas_base_free_smid - put smid back on free_list
  1293. * @ioc: per adapter object
  1294. * @smid: system request message index
  1295. *
  1296. * Return nothing.
  1297. */
  1298. void
  1299. mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1300. {
  1301. unsigned long flags;
  1302. int i;
  1303. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1304. if (smid >= ioc->hi_priority_smid) {
  1305. if (smid < ioc->internal_smid) {
  1306. /* hi-priority */
  1307. i = smid - ioc->hi_priority_smid;
  1308. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1309. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  1310. &ioc->hpr_free_list);
  1311. } else {
  1312. /* internal queue */
  1313. i = smid - ioc->internal_smid;
  1314. ioc->internal_lookup[i].cb_idx = 0xFF;
  1315. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  1316. &ioc->internal_free_list);
  1317. }
  1318. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1319. return;
  1320. }
  1321. /* scsiio queue */
  1322. i = smid - 1;
  1323. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1324. ioc->scsi_lookup[i].scmd = NULL;
  1325. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  1326. &ioc->free_list);
  1327. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1328. /*
  1329. * See _wait_for_commands_to_complete() call with regards to this code.
  1330. */
  1331. if (ioc->shost_recovery && ioc->pending_io_count) {
  1332. if (ioc->pending_io_count == 1)
  1333. wake_up(&ioc->reset_wq);
  1334. ioc->pending_io_count--;
  1335. }
  1336. }
  1337. /**
  1338. * _base_writeq - 64 bit write to MMIO
  1339. * @ioc: per adapter object
  1340. * @b: data payload
  1341. * @addr: address in MMIO space
  1342. * @writeq_lock: spin lock
  1343. *
  1344. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1345. * care of 32 bit environment where its not quarenteed to send the entire word
  1346. * in one transfer.
  1347. */
  1348. #ifndef writeq
  1349. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1350. spinlock_t *writeq_lock)
  1351. {
  1352. unsigned long flags;
  1353. __u64 data_out = cpu_to_le64(b);
  1354. spin_lock_irqsave(writeq_lock, flags);
  1355. writel((u32)(data_out), addr);
  1356. writel((u32)(data_out >> 32), (addr + 4));
  1357. spin_unlock_irqrestore(writeq_lock, flags);
  1358. }
  1359. #else
  1360. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1361. spinlock_t *writeq_lock)
  1362. {
  1363. writeq(cpu_to_le64(b), addr);
  1364. }
  1365. #endif
  1366. /**
  1367. * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1368. * @ioc: per adapter object
  1369. * @smid: system request message index
  1370. * @handle: device handle
  1371. *
  1372. * Return nothing.
  1373. */
  1374. void
  1375. mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1376. {
  1377. Mpi2RequestDescriptorUnion_t descriptor;
  1378. u64 *request = (u64 *)&descriptor;
  1379. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1380. descriptor.SCSIIO.MSIxIndex = 0; /* TODO */
  1381. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1382. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1383. descriptor.SCSIIO.LMID = 0;
  1384. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1385. &ioc->scsi_lookup_lock);
  1386. }
  1387. /**
  1388. * mpt2sas_base_put_smid_hi_priority - send Task Managment request to firmware
  1389. * @ioc: per adapter object
  1390. * @smid: system request message index
  1391. *
  1392. * Return nothing.
  1393. */
  1394. void
  1395. mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1396. {
  1397. Mpi2RequestDescriptorUnion_t descriptor;
  1398. u64 *request = (u64 *)&descriptor;
  1399. descriptor.HighPriority.RequestFlags =
  1400. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1401. descriptor.HighPriority.MSIxIndex = 0; /* TODO */
  1402. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1403. descriptor.HighPriority.LMID = 0;
  1404. descriptor.HighPriority.Reserved1 = 0;
  1405. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1406. &ioc->scsi_lookup_lock);
  1407. }
  1408. /**
  1409. * mpt2sas_base_put_smid_default - Default, primarily used for config pages
  1410. * @ioc: per adapter object
  1411. * @smid: system request message index
  1412. *
  1413. * Return nothing.
  1414. */
  1415. void
  1416. mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1417. {
  1418. Mpi2RequestDescriptorUnion_t descriptor;
  1419. u64 *request = (u64 *)&descriptor;
  1420. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1421. descriptor.Default.MSIxIndex = 0; /* TODO */
  1422. descriptor.Default.SMID = cpu_to_le16(smid);
  1423. descriptor.Default.LMID = 0;
  1424. descriptor.Default.DescriptorTypeDependent = 0;
  1425. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1426. &ioc->scsi_lookup_lock);
  1427. }
  1428. /**
  1429. * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware
  1430. * @ioc: per adapter object
  1431. * @smid: system request message index
  1432. * @io_index: value used to track the IO
  1433. *
  1434. * Return nothing.
  1435. */
  1436. void
  1437. mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
  1438. u16 io_index)
  1439. {
  1440. Mpi2RequestDescriptorUnion_t descriptor;
  1441. u64 *request = (u64 *)&descriptor;
  1442. descriptor.SCSITarget.RequestFlags =
  1443. MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
  1444. descriptor.SCSITarget.MSIxIndex = 0; /* TODO */
  1445. descriptor.SCSITarget.SMID = cpu_to_le16(smid);
  1446. descriptor.SCSITarget.LMID = 0;
  1447. descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
  1448. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1449. &ioc->scsi_lookup_lock);
  1450. }
  1451. /**
  1452. * _base_display_dell_branding - Disply branding string
  1453. * @ioc: per adapter object
  1454. *
  1455. * Return nothing.
  1456. */
  1457. static void
  1458. _base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
  1459. {
  1460. char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
  1461. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
  1462. return;
  1463. memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
  1464. switch (ioc->pdev->subsystem_device) {
  1465. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  1466. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
  1467. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1468. break;
  1469. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  1470. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
  1471. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1472. break;
  1473. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  1474. strncpy(dell_branding,
  1475. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
  1476. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1477. break;
  1478. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  1479. strncpy(dell_branding,
  1480. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
  1481. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1482. break;
  1483. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  1484. strncpy(dell_branding,
  1485. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
  1486. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1487. break;
  1488. case MPT2SAS_DELL_PERC_H200_SSDID:
  1489. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
  1490. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1491. break;
  1492. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  1493. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
  1494. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1495. break;
  1496. default:
  1497. sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
  1498. break;
  1499. }
  1500. printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
  1501. " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
  1502. ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
  1503. ioc->pdev->subsystem_device);
  1504. }
  1505. /**
  1506. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1507. * @ioc: per adapter object
  1508. *
  1509. * Return nothing.
  1510. */
  1511. static void
  1512. _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
  1513. {
  1514. int i = 0;
  1515. char desc[16];
  1516. u8 revision;
  1517. u32 iounit_pg1_flags;
  1518. pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
  1519. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1520. printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
  1521. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  1522. ioc->name, desc,
  1523. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  1524. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  1525. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  1526. ioc->facts.FWVersion.Word & 0x000000FF,
  1527. revision,
  1528. (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24,
  1529. (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16,
  1530. (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
  1531. ioc->bios_pg3.BiosVersion & 0x000000FF);
  1532. _base_display_dell_branding(ioc);
  1533. printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
  1534. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  1535. printk("Initiator");
  1536. i++;
  1537. }
  1538. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  1539. printk("%sTarget", i ? "," : "");
  1540. i++;
  1541. }
  1542. i = 0;
  1543. printk("), ");
  1544. printk("Capabilities=(");
  1545. if (ioc->facts.IOCCapabilities &
  1546. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  1547. printk("Raid");
  1548. i++;
  1549. }
  1550. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  1551. printk("%sTLR", i ? "," : "");
  1552. i++;
  1553. }
  1554. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  1555. printk("%sMulticast", i ? "," : "");
  1556. i++;
  1557. }
  1558. if (ioc->facts.IOCCapabilities &
  1559. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  1560. printk("%sBIDI Target", i ? "," : "");
  1561. i++;
  1562. }
  1563. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  1564. printk("%sEEDP", i ? "," : "");
  1565. i++;
  1566. }
  1567. if (ioc->facts.IOCCapabilities &
  1568. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  1569. printk("%sSnapshot Buffer", i ? "," : "");
  1570. i++;
  1571. }
  1572. if (ioc->facts.IOCCapabilities &
  1573. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  1574. printk("%sDiag Trace Buffer", i ? "," : "");
  1575. i++;
  1576. }
  1577. if (ioc->facts.IOCCapabilities &
  1578. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  1579. printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
  1580. i++;
  1581. }
  1582. if (ioc->facts.IOCCapabilities &
  1583. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  1584. printk("%sTask Set Full", i ? "," : "");
  1585. i++;
  1586. }
  1587. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1588. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  1589. printk("%sNCQ", i ? "," : "");
  1590. i++;
  1591. }
  1592. printk(")\n");
  1593. }
  1594. /**
  1595. * _base_static_config_pages - static start of day config pages
  1596. * @ioc: per adapter object
  1597. *
  1598. * Return nothing.
  1599. */
  1600. static void
  1601. _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
  1602. {
  1603. Mpi2ConfigReply_t mpi_reply;
  1604. u32 iounit_pg1_flags;
  1605. mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  1606. if (ioc->ir_firmware)
  1607. mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  1608. &ioc->manu_pg10);
  1609. mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  1610. mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  1611. mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  1612. mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  1613. mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1614. _base_display_ioc_capabilities(ioc);
  1615. /*
  1616. * Enable task_set_full handling in iounit_pg1 when the
  1617. * facts capabilities indicate that its supported.
  1618. */
  1619. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1620. if ((ioc->facts.IOCCapabilities &
  1621. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  1622. iounit_pg1_flags &=
  1623. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1624. else
  1625. iounit_pg1_flags |=
  1626. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1627. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  1628. mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1629. }
  1630. /**
  1631. * _base_release_memory_pools - release memory
  1632. * @ioc: per adapter object
  1633. *
  1634. * Free memory allocated from _base_allocate_memory_pools.
  1635. *
  1636. * Return nothing.
  1637. */
  1638. static void
  1639. _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
  1640. {
  1641. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  1642. __func__));
  1643. if (ioc->request) {
  1644. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  1645. ioc->request, ioc->request_dma);
  1646. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
  1647. ": free\n", ioc->name, ioc->request));
  1648. ioc->request = NULL;
  1649. }
  1650. if (ioc->sense) {
  1651. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  1652. if (ioc->sense_dma_pool)
  1653. pci_pool_destroy(ioc->sense_dma_pool);
  1654. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
  1655. ": free\n", ioc->name, ioc->sense));
  1656. ioc->sense = NULL;
  1657. }
  1658. if (ioc->reply) {
  1659. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  1660. if (ioc->reply_dma_pool)
  1661. pci_pool_destroy(ioc->reply_dma_pool);
  1662. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
  1663. ": free\n", ioc->name, ioc->reply));
  1664. ioc->reply = NULL;
  1665. }
  1666. if (ioc->reply_free) {
  1667. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  1668. ioc->reply_free_dma);
  1669. if (ioc->reply_free_dma_pool)
  1670. pci_pool_destroy(ioc->reply_free_dma_pool);
  1671. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
  1672. "(0x%p): free\n", ioc->name, ioc->reply_free));
  1673. ioc->reply_free = NULL;
  1674. }
  1675. if (ioc->reply_post_free) {
  1676. pci_pool_free(ioc->reply_post_free_dma_pool,
  1677. ioc->reply_post_free, ioc->reply_post_free_dma);
  1678. if (ioc->reply_post_free_dma_pool)
  1679. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  1680. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1681. "reply_post_free_pool(0x%p): free\n", ioc->name,
  1682. ioc->reply_post_free));
  1683. ioc->reply_post_free = NULL;
  1684. }
  1685. if (ioc->config_page) {
  1686. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1687. "config_page(0x%p): free\n", ioc->name,
  1688. ioc->config_page));
  1689. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  1690. ioc->config_page, ioc->config_page_dma);
  1691. }
  1692. kfree(ioc->scsi_lookup);
  1693. kfree(ioc->hpr_lookup);
  1694. kfree(ioc->internal_lookup);
  1695. }
  1696. /**
  1697. * _base_allocate_memory_pools - allocate start of day memory pools
  1698. * @ioc: per adapter object
  1699. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  1700. *
  1701. * Returns 0 success, anything else error
  1702. */
  1703. static int
  1704. _base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  1705. {
  1706. Mpi2IOCFactsReply_t *facts;
  1707. u32 queue_size, queue_diff;
  1708. u16 max_sge_elements;
  1709. u16 num_of_reply_frames;
  1710. u16 chains_needed_per_io;
  1711. u32 sz, total_sz;
  1712. u32 retry_sz;
  1713. u16 max_request_credit;
  1714. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  1715. __func__));
  1716. retry_sz = 0;
  1717. facts = &ioc->facts;
  1718. /* command line tunables for max sgl entries */
  1719. if (max_sgl_entries != -1) {
  1720. ioc->shost->sg_tablesize = (max_sgl_entries <
  1721. MPT2SAS_SG_DEPTH) ? max_sgl_entries :
  1722. MPT2SAS_SG_DEPTH;
  1723. } else {
  1724. ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
  1725. }
  1726. /* command line tunables for max controller queue depth */
  1727. if (max_queue_depth != -1) {
  1728. max_request_credit = (max_queue_depth < facts->RequestCredit)
  1729. ? max_queue_depth : facts->RequestCredit;
  1730. } else {
  1731. max_request_credit = (facts->RequestCredit >
  1732. MPT2SAS_MAX_REQUEST_QUEUE) ? MPT2SAS_MAX_REQUEST_QUEUE :
  1733. facts->RequestCredit;
  1734. }
  1735. ioc->hba_queue_depth = max_request_credit;
  1736. ioc->hi_priority_depth = facts->HighPriorityCredit;
  1737. ioc->internal_depth = ioc->hi_priority_depth + 5;
  1738. /* request frame size */
  1739. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  1740. /* reply frame size */
  1741. ioc->reply_sz = facts->ReplyFrameSize * 4;
  1742. retry_allocation:
  1743. total_sz = 0;
  1744. /* calculate number of sg elements left over in the 1st frame */
  1745. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  1746. sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
  1747. ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
  1748. /* now do the same for a chain buffer */
  1749. max_sge_elements = ioc->request_sz - ioc->sge_size;
  1750. ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
  1751. ioc->chain_offset_value_for_main_message =
  1752. ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
  1753. (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
  1754. /*
  1755. * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  1756. */
  1757. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  1758. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  1759. + 1;
  1760. if (chains_needed_per_io > facts->MaxChainDepth) {
  1761. chains_needed_per_io = facts->MaxChainDepth;
  1762. ioc->shost->sg_tablesize = min_t(u16,
  1763. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  1764. * chains_needed_per_io), ioc->shost->sg_tablesize);
  1765. }
  1766. ioc->chains_needed_per_io = chains_needed_per_io;
  1767. /* reply free queue sizing - taking into account for events */
  1768. num_of_reply_frames = ioc->hba_queue_depth + 32;
  1769. /* number of replies frames can't be a multiple of 16 */
  1770. /* decrease number of reply frames by 1 */
  1771. if (!(num_of_reply_frames % 16))
  1772. num_of_reply_frames--;
  1773. /* calculate number of reply free queue entries
  1774. * (must be multiple of 16)
  1775. */
  1776. /* (we know reply_free_queue_depth is not a multiple of 16) */
  1777. queue_size = num_of_reply_frames;
  1778. queue_size += 16 - (queue_size % 16);
  1779. ioc->reply_free_queue_depth = queue_size;
  1780. /* reply descriptor post queue sizing */
  1781. /* this size should be the number of request frames + number of reply
  1782. * frames
  1783. */
  1784. queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
  1785. /* round up to 16 byte boundary */
  1786. if (queue_size % 16)
  1787. queue_size += 16 - (queue_size % 16);
  1788. /* check against IOC maximum reply post queue depth */
  1789. if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
  1790. queue_diff = queue_size -
  1791. facts->MaxReplyDescriptorPostQueueDepth;
  1792. /* round queue_diff up to multiple of 16 */
  1793. if (queue_diff % 16)
  1794. queue_diff += 16 - (queue_diff % 16);
  1795. /* adjust hba_queue_depth, reply_free_queue_depth,
  1796. * and queue_size
  1797. */
  1798. ioc->hba_queue_depth -= queue_diff;
  1799. ioc->reply_free_queue_depth -= queue_diff;
  1800. queue_size -= queue_diff;
  1801. }
  1802. ioc->reply_post_queue_depth = queue_size;
  1803. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
  1804. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  1805. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  1806. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  1807. ioc->chains_needed_per_io));
  1808. ioc->scsiio_depth = ioc->hba_queue_depth -
  1809. ioc->hi_priority_depth - ioc->internal_depth;
  1810. /* set the scsi host can_queue depth
  1811. * with some internal commands that could be outstanding
  1812. */
  1813. ioc->shost->can_queue = ioc->scsiio_depth - (2);
  1814. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
  1815. "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
  1816. /* contiguous pool for request and chains, 16 byte align, one extra "
  1817. * "frame for smid=0
  1818. */
  1819. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  1820. sz = ((ioc->scsiio_depth + 1 + ioc->chain_depth) * ioc->request_sz);
  1821. /* hi-priority queue */
  1822. sz += (ioc->hi_priority_depth * ioc->request_sz);
  1823. /* internal queue */
  1824. sz += (ioc->internal_depth * ioc->request_sz);
  1825. ioc->request_dma_sz = sz;
  1826. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  1827. if (!ioc->request) {
  1828. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1829. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1830. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  1831. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1832. if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
  1833. goto out;
  1834. retry_sz += 64;
  1835. ioc->hba_queue_depth = max_request_credit - retry_sz;
  1836. goto retry_allocation;
  1837. }
  1838. if (retry_sz)
  1839. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1840. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1841. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  1842. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1843. /* hi-priority queue */
  1844. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  1845. ioc->request_sz);
  1846. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  1847. ioc->request_sz);
  1848. /* internal queue */
  1849. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  1850. ioc->request_sz);
  1851. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  1852. ioc->request_sz);
  1853. ioc->chain = ioc->internal + (ioc->internal_depth *
  1854. ioc->request_sz);
  1855. ioc->chain_dma = ioc->internal_dma + (ioc->internal_depth *
  1856. ioc->request_sz);
  1857. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
  1858. "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  1859. ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  1860. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  1861. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool(0x%p): depth"
  1862. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->chain,
  1863. ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
  1864. ioc->request_sz))/1024));
  1865. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
  1866. ioc->name, (unsigned long long) ioc->request_dma));
  1867. total_sz += sz;
  1868. ioc->scsi_lookup = kcalloc(ioc->scsiio_depth,
  1869. sizeof(struct request_tracker), GFP_KERNEL);
  1870. if (!ioc->scsi_lookup) {
  1871. printk(MPT2SAS_ERR_FMT "scsi_lookup: kcalloc failed\n",
  1872. ioc->name);
  1873. goto out;
  1874. }
  1875. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
  1876. "depth(%d)\n", ioc->name, ioc->request,
  1877. ioc->scsiio_depth));
  1878. /* initialize hi-priority queue smid's */
  1879. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  1880. sizeof(struct request_tracker), GFP_KERNEL);
  1881. if (!ioc->hpr_lookup) {
  1882. printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
  1883. ioc->name);
  1884. goto out;
  1885. }
  1886. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  1887. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
  1888. "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
  1889. ioc->hi_priority_depth, ioc->hi_priority_smid));
  1890. /* initialize internal queue smid's */
  1891. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  1892. sizeof(struct request_tracker), GFP_KERNEL);
  1893. if (!ioc->internal_lookup) {
  1894. printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
  1895. ioc->name);
  1896. goto out;
  1897. }
  1898. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  1899. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
  1900. "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
  1901. ioc->internal_depth, ioc->internal_smid));
  1902. /* sense buffers, 4 byte align */
  1903. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  1904. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  1905. 0);
  1906. if (!ioc->sense_dma_pool) {
  1907. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
  1908. ioc->name);
  1909. goto out;
  1910. }
  1911. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  1912. &ioc->sense_dma);
  1913. if (!ioc->sense) {
  1914. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
  1915. ioc->name);
  1916. goto out;
  1917. }
  1918. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1919. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  1920. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  1921. SCSI_SENSE_BUFFERSIZE, sz/1024));
  1922. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
  1923. ioc->name, (unsigned long long)ioc->sense_dma));
  1924. total_sz += sz;
  1925. /* reply pool, 4 byte align */
  1926. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  1927. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  1928. 0);
  1929. if (!ioc->reply_dma_pool) {
  1930. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
  1931. ioc->name);
  1932. goto out;
  1933. }
  1934. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  1935. &ioc->reply_dma);
  1936. if (!ioc->reply) {
  1937. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
  1938. ioc->name);
  1939. goto out;
  1940. }
  1941. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
  1942. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
  1943. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  1944. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
  1945. ioc->name, (unsigned long long)ioc->reply_dma));
  1946. total_sz += sz;
  1947. /* reply free queue, 16 byte align */
  1948. sz = ioc->reply_free_queue_depth * 4;
  1949. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  1950. ioc->pdev, sz, 16, 0);
  1951. if (!ioc->reply_free_dma_pool) {
  1952. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
  1953. "failed\n", ioc->name);
  1954. goto out;
  1955. }
  1956. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  1957. &ioc->reply_free_dma);
  1958. if (!ioc->reply_free) {
  1959. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
  1960. "failed\n", ioc->name);
  1961. goto out;
  1962. }
  1963. memset(ioc->reply_free, 0, sz);
  1964. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
  1965. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  1966. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  1967. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
  1968. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
  1969. total_sz += sz;
  1970. /* reply post queue, 16 byte align */
  1971. sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t);
  1972. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  1973. ioc->pdev, sz, 16, 0);
  1974. if (!ioc->reply_post_free_dma_pool) {
  1975. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
  1976. "failed\n", ioc->name);
  1977. goto out;
  1978. }
  1979. ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
  1980. GFP_KERNEL, &ioc->reply_post_free_dma);
  1981. if (!ioc->reply_post_free) {
  1982. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
  1983. "failed\n", ioc->name);
  1984. goto out;
  1985. }
  1986. memset(ioc->reply_post_free, 0, sz);
  1987. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
  1988. "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
  1989. ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
  1990. sz/1024));
  1991. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
  1992. "(0x%llx)\n", ioc->name, (unsigned long long)
  1993. ioc->reply_post_free_dma));
  1994. total_sz += sz;
  1995. ioc->config_page_sz = 512;
  1996. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  1997. ioc->config_page_sz, &ioc->config_page_dma);
  1998. if (!ioc->config_page) {
  1999. printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
  2000. "failed\n", ioc->name);
  2001. goto out;
  2002. }
  2003. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
  2004. "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
  2005. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
  2006. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
  2007. total_sz += ioc->config_page_sz;
  2008. printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
  2009. ioc->name, total_sz/1024);
  2010. printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
  2011. "Max Controller Queue Depth(%d)\n",
  2012. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  2013. printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
  2014. ioc->name, ioc->shost->sg_tablesize);
  2015. return 0;
  2016. out:
  2017. _base_release_memory_pools(ioc);
  2018. return -ENOMEM;
  2019. }
  2020. /**
  2021. * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter.
  2022. * @ioc: Pointer to MPT_ADAPTER structure
  2023. * @cooked: Request raw or cooked IOC state
  2024. *
  2025. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2026. * Doorbell bits in MPI_IOC_STATE_MASK.
  2027. */
  2028. u32
  2029. mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
  2030. {
  2031. u32 s, sc;
  2032. s = readl(&ioc->chip->Doorbell);
  2033. sc = s & MPI2_IOC_STATE_MASK;
  2034. return cooked ? sc : s;
  2035. }
  2036. /**
  2037. * _base_wait_on_iocstate - waiting on a particular ioc state
  2038. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  2039. * @timeout: timeout in second
  2040. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2041. *
  2042. * Returns 0 for success, non-zero for failure.
  2043. */
  2044. static int
  2045. _base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  2046. int sleep_flag)
  2047. {
  2048. u32 count, cntdn;
  2049. u32 current_state;
  2050. count = 0;
  2051. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2052. do {
  2053. current_state = mpt2sas_base_get_iocstate(ioc, 1);
  2054. if (current_state == ioc_state)
  2055. return 0;
  2056. if (count && current_state == MPI2_IOC_STATE_FAULT)
  2057. break;
  2058. if (sleep_flag == CAN_SLEEP)
  2059. msleep(1);
  2060. else
  2061. udelay(500);
  2062. count++;
  2063. } while (--cntdn);
  2064. return current_state;
  2065. }
  2066. /**
  2067. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2068. * a write to the doorbell)
  2069. * @ioc: per adapter object
  2070. * @timeout: timeout in second
  2071. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2072. *
  2073. * Returns 0 for success, non-zero for failure.
  2074. *
  2075. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2076. */
  2077. static int
  2078. _base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2079. int sleep_flag)
  2080. {
  2081. u32 cntdn, count;
  2082. u32 int_status;
  2083. count = 0;
  2084. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2085. do {
  2086. int_status = readl(&ioc->chip->HostInterruptStatus);
  2087. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2088. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2089. "successfull count(%d), timeout(%d)\n", ioc->name,
  2090. __func__, count, timeout));
  2091. return 0;
  2092. }
  2093. if (sleep_flag == CAN_SLEEP)
  2094. msleep(1);
  2095. else
  2096. udelay(500);
  2097. count++;
  2098. } while (--cntdn);
  2099. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2100. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2101. return -EFAULT;
  2102. }
  2103. /**
  2104. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2105. * @ioc: per adapter object
  2106. * @timeout: timeout in second
  2107. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2108. *
  2109. * Returns 0 for success, non-zero for failure.
  2110. *
  2111. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2112. * doorbell.
  2113. */
  2114. static int
  2115. _base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2116. int sleep_flag)
  2117. {
  2118. u32 cntdn, count;
  2119. u32 int_status;
  2120. u32 doorbell;
  2121. count = 0;
  2122. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2123. do {
  2124. int_status = readl(&ioc->chip->HostInterruptStatus);
  2125. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2126. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2127. "successfull count(%d), timeout(%d)\n", ioc->name,
  2128. __func__, count, timeout));
  2129. return 0;
  2130. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2131. doorbell = readl(&ioc->chip->Doorbell);
  2132. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2133. MPI2_IOC_STATE_FAULT) {
  2134. mpt2sas_base_fault_info(ioc , doorbell);
  2135. return -EFAULT;
  2136. }
  2137. } else if (int_status == 0xFFFFFFFF)
  2138. goto out;
  2139. if (sleep_flag == CAN_SLEEP)
  2140. msleep(1);
  2141. else
  2142. udelay(500);
  2143. count++;
  2144. } while (--cntdn);
  2145. out:
  2146. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2147. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2148. return -EFAULT;
  2149. }
  2150. /**
  2151. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2152. * @ioc: per adapter object
  2153. * @timeout: timeout in second
  2154. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2155. *
  2156. * Returns 0 for success, non-zero for failure.
  2157. *
  2158. */
  2159. static int
  2160. _base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2161. int sleep_flag)
  2162. {
  2163. u32 cntdn, count;
  2164. u32 doorbell_reg;
  2165. count = 0;
  2166. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2167. do {
  2168. doorbell_reg = readl(&ioc->chip->Doorbell);
  2169. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2170. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2171. "successfull count(%d), timeout(%d)\n", ioc->name,
  2172. __func__, count, timeout));
  2173. return 0;
  2174. }
  2175. if (sleep_flag == CAN_SLEEP)
  2176. msleep(1);
  2177. else
  2178. udelay(500);
  2179. count++;
  2180. } while (--cntdn);
  2181. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2182. "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
  2183. return -EFAULT;
  2184. }
  2185. /**
  2186. * _base_send_ioc_reset - send doorbell reset
  2187. * @ioc: per adapter object
  2188. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2189. * @timeout: timeout in second
  2190. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2191. *
  2192. * Returns 0 for success, non-zero for failure.
  2193. */
  2194. static int
  2195. _base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2196. int sleep_flag)
  2197. {
  2198. u32 ioc_state;
  2199. int r = 0;
  2200. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2201. printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
  2202. ioc->name, __func__);
  2203. return -EFAULT;
  2204. }
  2205. if (!(ioc->facts.IOCCapabilities &
  2206. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2207. return -EFAULT;
  2208. printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
  2209. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2210. &ioc->chip->Doorbell);
  2211. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2212. r = -EFAULT;
  2213. goto out;
  2214. }
  2215. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2216. timeout, sleep_flag);
  2217. if (ioc_state) {
  2218. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2219. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2220. r = -EFAULT;
  2221. goto out;
  2222. }
  2223. out:
  2224. printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
  2225. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2226. return r;
  2227. }
  2228. /**
  2229. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2230. * @ioc: per adapter object
  2231. * @request_bytes: request length
  2232. * @request: pointer having request payload
  2233. * @reply_bytes: reply length
  2234. * @reply: pointer to reply payload
  2235. * @timeout: timeout in second
  2236. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2237. *
  2238. * Returns 0 for success, non-zero for failure.
  2239. */
  2240. static int
  2241. _base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
  2242. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2243. {
  2244. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2245. int i;
  2246. u8 failed;
  2247. u16 dummy;
  2248. u32 *mfp;
  2249. /* make sure doorbell is not in use */
  2250. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2251. printk(MPT2SAS_ERR_FMT "doorbell is in use "
  2252. " (line=%d)\n", ioc->name, __LINE__);
  2253. return -EFAULT;
  2254. }
  2255. /* clear pending doorbell interrupts from previous state changes */
  2256. if (readl(&ioc->chip->HostInterruptStatus) &
  2257. MPI2_HIS_IOC2SYS_DB_STATUS)
  2258. writel(0, &ioc->chip->HostInterruptStatus);
  2259. /* send message to ioc */
  2260. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2261. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2262. &ioc->chip->Doorbell);
  2263. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2264. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2265. "int failed (line=%d)\n", ioc->name, __LINE__);
  2266. return -EFAULT;
  2267. }
  2268. writel(0, &ioc->chip->HostInterruptStatus);
  2269. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2270. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2271. "ack failed (line=%d)\n", ioc->name, __LINE__);
  2272. return -EFAULT;
  2273. }
  2274. /* send message 32-bits at a time */
  2275. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2276. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2277. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2278. failed = 1;
  2279. }
  2280. if (failed) {
  2281. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2282. "sending request failed (line=%d)\n", ioc->name, __LINE__);
  2283. return -EFAULT;
  2284. }
  2285. /* now wait for the reply */
  2286. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2287. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2288. "int failed (line=%d)\n", ioc->name, __LINE__);
  2289. return -EFAULT;
  2290. }
  2291. /* read the first two 16-bits, it gives the total length of the reply */
  2292. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2293. & MPI2_DOORBELL_DATA_MASK);
  2294. writel(0, &ioc->chip->HostInterruptStatus);
  2295. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2296. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2297. "int failed (line=%d)\n", ioc->name, __LINE__);
  2298. return -EFAULT;
  2299. }
  2300. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2301. & MPI2_DOORBELL_DATA_MASK);
  2302. writel(0, &ioc->chip->HostInterruptStatus);
  2303. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2304. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2305. printk(MPT2SAS_ERR_FMT "doorbell "
  2306. "handshake int failed (line=%d)\n", ioc->name,
  2307. __LINE__);
  2308. return -EFAULT;
  2309. }
  2310. if (i >= reply_bytes/2) /* overflow case */
  2311. dummy = readl(&ioc->chip->Doorbell);
  2312. else
  2313. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2314. & MPI2_DOORBELL_DATA_MASK);
  2315. writel(0, &ioc->chip->HostInterruptStatus);
  2316. }
  2317. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2318. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2319. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
  2320. " (line=%d)\n", ioc->name, __LINE__));
  2321. }
  2322. writel(0, &ioc->chip->HostInterruptStatus);
  2323. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2324. mfp = (u32 *)reply;
  2325. printk(KERN_DEBUG "\toffset:data\n");
  2326. for (i = 0; i < reply_bytes/4; i++)
  2327. printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
  2328. le32_to_cpu(mfp[i]));
  2329. }
  2330. return 0;
  2331. }
  2332. /**
  2333. * mpt2sas_base_sas_iounit_control - send sas iounit control to FW
  2334. * @ioc: per adapter object
  2335. * @mpi_reply: the reply payload from FW
  2336. * @mpi_request: the request payload sent to FW
  2337. *
  2338. * The SAS IO Unit Control Request message allows the host to perform low-level
  2339. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2340. * to obtain the IOC assigned device handles for a device if it has other
  2341. * identifying information about the device, in addition allows the host to
  2342. * remove IOC resources associated with the device.
  2343. *
  2344. * Returns 0 for success, non-zero for failure.
  2345. */
  2346. int
  2347. mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
  2348. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2349. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2350. {
  2351. u16 smid;
  2352. u32 ioc_state;
  2353. unsigned long timeleft;
  2354. u8 issue_reset;
  2355. int rc;
  2356. void *request;
  2357. u16 wait_state_count;
  2358. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2359. __func__));
  2360. mutex_lock(&ioc->base_cmds.mutex);
  2361. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2362. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2363. ioc->name, __func__);
  2364. rc = -EAGAIN;
  2365. goto out;
  2366. }
  2367. wait_state_count = 0;
  2368. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2369. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2370. if (wait_state_count++ == 10) {
  2371. printk(MPT2SAS_ERR_FMT
  2372. "%s: failed due to ioc not operational\n",
  2373. ioc->name, __func__);
  2374. rc = -EFAULT;
  2375. goto out;
  2376. }
  2377. ssleep(1);
  2378. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2379. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2380. "operational state(count=%d)\n", ioc->name,
  2381. __func__, wait_state_count);
  2382. }
  2383. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2384. if (!smid) {
  2385. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2386. ioc->name, __func__);
  2387. rc = -EAGAIN;
  2388. goto out;
  2389. }
  2390. rc = 0;
  2391. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2392. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2393. ioc->base_cmds.smid = smid;
  2394. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  2395. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2396. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  2397. ioc->ioc_link_reset_in_progress = 1;
  2398. mpt2sas_base_put_smid_default(ioc, smid);
  2399. init_completion(&ioc->base_cmds.done);
  2400. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2401. msecs_to_jiffies(10000));
  2402. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2403. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  2404. ioc->ioc_link_reset_in_progress)
  2405. ioc->ioc_link_reset_in_progress = 0;
  2406. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2407. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2408. ioc->name, __func__);
  2409. _debug_dump_mf(mpi_request,
  2410. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  2411. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2412. issue_reset = 1;
  2413. goto issue_host_reset;
  2414. }
  2415. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2416. memcpy(mpi_reply, ioc->base_cmds.reply,
  2417. sizeof(Mpi2SasIoUnitControlReply_t));
  2418. else
  2419. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  2420. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2421. goto out;
  2422. issue_host_reset:
  2423. if (issue_reset)
  2424. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2425. FORCE_BIG_HAMMER);
  2426. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2427. rc = -EFAULT;
  2428. out:
  2429. mutex_unlock(&ioc->base_cmds.mutex);
  2430. return rc;
  2431. }
  2432. /**
  2433. * mpt2sas_base_scsi_enclosure_processor - sending request to sep device
  2434. * @ioc: per adapter object
  2435. * @mpi_reply: the reply payload from FW
  2436. * @mpi_request: the request payload sent to FW
  2437. *
  2438. * The SCSI Enclosure Processor request message causes the IOC to
  2439. * communicate with SES devices to control LED status signals.
  2440. *
  2441. * Returns 0 for success, non-zero for failure.
  2442. */
  2443. int
  2444. mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
  2445. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  2446. {
  2447. u16 smid;
  2448. u32 ioc_state;
  2449. unsigned long timeleft;
  2450. u8 issue_reset;
  2451. int rc;
  2452. void *request;
  2453. u16 wait_state_count;
  2454. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2455. __func__));
  2456. mutex_lock(&ioc->base_cmds.mutex);
  2457. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2458. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2459. ioc->name, __func__);
  2460. rc = -EAGAIN;
  2461. goto out;
  2462. }
  2463. wait_state_count = 0;
  2464. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2465. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2466. if (wait_state_count++ == 10) {
  2467. printk(MPT2SAS_ERR_FMT
  2468. "%s: failed due to ioc not operational\n",
  2469. ioc->name, __func__);
  2470. rc = -EFAULT;
  2471. goto out;
  2472. }
  2473. ssleep(1);
  2474. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2475. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2476. "operational state(count=%d)\n", ioc->name,
  2477. __func__, wait_state_count);
  2478. }
  2479. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2480. if (!smid) {
  2481. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2482. ioc->name, __func__);
  2483. rc = -EAGAIN;
  2484. goto out;
  2485. }
  2486. rc = 0;
  2487. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2488. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2489. ioc->base_cmds.smid = smid;
  2490. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  2491. mpt2sas_base_put_smid_default(ioc, smid);
  2492. init_completion(&ioc->base_cmds.done);
  2493. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2494. msecs_to_jiffies(10000));
  2495. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2496. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2497. ioc->name, __func__);
  2498. _debug_dump_mf(mpi_request,
  2499. sizeof(Mpi2SepRequest_t)/4);
  2500. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2501. issue_reset = 1;
  2502. goto issue_host_reset;
  2503. }
  2504. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2505. memcpy(mpi_reply, ioc->base_cmds.reply,
  2506. sizeof(Mpi2SepReply_t));
  2507. else
  2508. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  2509. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2510. goto out;
  2511. issue_host_reset:
  2512. if (issue_reset)
  2513. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2514. FORCE_BIG_HAMMER);
  2515. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2516. rc = -EFAULT;
  2517. out:
  2518. mutex_unlock(&ioc->base_cmds.mutex);
  2519. return rc;
  2520. }
  2521. /**
  2522. * _base_get_port_facts - obtain port facts reply and save in ioc
  2523. * @ioc: per adapter object
  2524. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2525. *
  2526. * Returns 0 for success, non-zero for failure.
  2527. */
  2528. static int
  2529. _base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
  2530. {
  2531. Mpi2PortFactsRequest_t mpi_request;
  2532. Mpi2PortFactsReply_t mpi_reply, *pfacts;
  2533. int mpi_reply_sz, mpi_request_sz, r;
  2534. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2535. __func__));
  2536. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  2537. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  2538. memset(&mpi_request, 0, mpi_request_sz);
  2539. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  2540. mpi_request.PortNumber = port;
  2541. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2542. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2543. if (r != 0) {
  2544. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2545. ioc->name, __func__, r);
  2546. return r;
  2547. }
  2548. pfacts = &ioc->pfacts[port];
  2549. memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
  2550. pfacts->PortNumber = mpi_reply.PortNumber;
  2551. pfacts->VP_ID = mpi_reply.VP_ID;
  2552. pfacts->VF_ID = mpi_reply.VF_ID;
  2553. pfacts->MaxPostedCmdBuffers =
  2554. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  2555. return 0;
  2556. }
  2557. /**
  2558. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  2559. * @ioc: per adapter object
  2560. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2561. *
  2562. * Returns 0 for success, non-zero for failure.
  2563. */
  2564. static int
  2565. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2566. {
  2567. Mpi2IOCFactsRequest_t mpi_request;
  2568. Mpi2IOCFactsReply_t mpi_reply, *facts;
  2569. int mpi_reply_sz, mpi_request_sz, r;
  2570. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2571. __func__));
  2572. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  2573. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  2574. memset(&mpi_request, 0, mpi_request_sz);
  2575. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  2576. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2577. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2578. if (r != 0) {
  2579. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2580. ioc->name, __func__, r);
  2581. return r;
  2582. }
  2583. facts = &ioc->facts;
  2584. memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
  2585. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  2586. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  2587. facts->VP_ID = mpi_reply.VP_ID;
  2588. facts->VF_ID = mpi_reply.VF_ID;
  2589. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  2590. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  2591. facts->WhoInit = mpi_reply.WhoInit;
  2592. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  2593. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  2594. facts->MaxReplyDescriptorPostQueueDepth =
  2595. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  2596. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  2597. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  2598. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  2599. ioc->ir_firmware = 1;
  2600. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  2601. facts->IOCRequestFrameSize =
  2602. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  2603. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  2604. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  2605. ioc->shost->max_id = -1;
  2606. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  2607. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  2608. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  2609. facts->HighPriorityCredit =
  2610. le16_to_cpu(mpi_reply.HighPriorityCredit);
  2611. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  2612. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  2613. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
  2614. "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
  2615. facts->MaxChainDepth));
  2616. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
  2617. "reply frame size(%d)\n", ioc->name,
  2618. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  2619. return 0;
  2620. }
  2621. /**
  2622. * _base_send_ioc_init - send ioc_init to firmware
  2623. * @ioc: per adapter object
  2624. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2625. *
  2626. * Returns 0 for success, non-zero for failure.
  2627. */
  2628. static int
  2629. _base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2630. {
  2631. Mpi2IOCInitRequest_t mpi_request;
  2632. Mpi2IOCInitReply_t mpi_reply;
  2633. int r;
  2634. struct timeval current_time;
  2635. u16 ioc_status;
  2636. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2637. __func__));
  2638. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  2639. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  2640. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  2641. mpi_request.VF_ID = 0; /* TODO */
  2642. mpi_request.VP_ID = 0;
  2643. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  2644. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  2645. /* In MPI Revision I (0xA), the SystemReplyFrameSize(offset 0x18) was
  2646. * removed and made reserved. For those with older firmware will need
  2647. * this fix. It was decided that the Reply and Request frame sizes are
  2648. * the same.
  2649. */
  2650. if ((ioc->facts.HeaderVersion >> 8) < 0xA) {
  2651. mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz);
  2652. /* mpi_request.SystemReplyFrameSize =
  2653. * cpu_to_le16(ioc->reply_sz);
  2654. */
  2655. }
  2656. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  2657. mpi_request.ReplyDescriptorPostQueueDepth =
  2658. cpu_to_le16(ioc->reply_post_queue_depth);
  2659. mpi_request.ReplyFreeQueueDepth =
  2660. cpu_to_le16(ioc->reply_free_queue_depth);
  2661. #if BITS_PER_LONG > 32
  2662. mpi_request.SenseBufferAddressHigh =
  2663. cpu_to_le32(ioc->sense_dma >> 32);
  2664. mpi_request.SystemReplyAddressHigh =
  2665. cpu_to_le32(ioc->reply_dma >> 32);
  2666. mpi_request.SystemRequestFrameBaseAddress =
  2667. cpu_to_le64(ioc->request_dma);
  2668. mpi_request.ReplyFreeQueueAddress =
  2669. cpu_to_le64(ioc->reply_free_dma);
  2670. mpi_request.ReplyDescriptorPostQueueAddress =
  2671. cpu_to_le64(ioc->reply_post_free_dma);
  2672. #else
  2673. mpi_request.SystemRequestFrameBaseAddress =
  2674. cpu_to_le32(ioc->request_dma);
  2675. mpi_request.ReplyFreeQueueAddress =
  2676. cpu_to_le32(ioc->reply_free_dma);
  2677. mpi_request.ReplyDescriptorPostQueueAddress =
  2678. cpu_to_le32(ioc->reply_post_free_dma);
  2679. #endif
  2680. /* This time stamp specifies number of milliseconds
  2681. * since epoch ~ midnight January 1, 1970.
  2682. */
  2683. do_gettimeofday(&current_time);
  2684. mpi_request.TimeStamp = (current_time.tv_sec * 1000) +
  2685. (current_time.tv_usec >> 3);
  2686. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2687. u32 *mfp;
  2688. int i;
  2689. mfp = (u32 *)&mpi_request;
  2690. printk(KERN_DEBUG "\toffset:data\n");
  2691. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  2692. printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
  2693. le32_to_cpu(mfp[i]));
  2694. }
  2695. r = _base_handshake_req_reply_wait(ioc,
  2696. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  2697. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  2698. sleep_flag);
  2699. if (r != 0) {
  2700. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2701. ioc->name, __func__, r);
  2702. return r;
  2703. }
  2704. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  2705. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  2706. mpi_reply.IOCLogInfo) {
  2707. printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
  2708. r = -EIO;
  2709. }
  2710. return 0;
  2711. }
  2712. /**
  2713. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  2714. * @ioc: per adapter object
  2715. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2716. *
  2717. * Returns 0 for success, non-zero for failure.
  2718. */
  2719. static int
  2720. _base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2721. {
  2722. Mpi2PortEnableRequest_t *mpi_request;
  2723. u32 ioc_state;
  2724. unsigned long timeleft;
  2725. int r = 0;
  2726. u16 smid;
  2727. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  2728. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2729. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2730. ioc->name, __func__);
  2731. return -EAGAIN;
  2732. }
  2733. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2734. if (!smid) {
  2735. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2736. ioc->name, __func__);
  2737. return -EAGAIN;
  2738. }
  2739. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2740. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2741. ioc->base_cmds.smid = smid;
  2742. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  2743. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  2744. mpi_request->VF_ID = 0; /* TODO */
  2745. mpi_request->VP_ID = 0;
  2746. mpt2sas_base_put_smid_default(ioc, smid);
  2747. init_completion(&ioc->base_cmds.done);
  2748. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2749. 300*HZ);
  2750. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2751. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2752. ioc->name, __func__);
  2753. _debug_dump_mf(mpi_request,
  2754. sizeof(Mpi2PortEnableRequest_t)/4);
  2755. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2756. r = -EFAULT;
  2757. else
  2758. r = -ETIME;
  2759. goto out;
  2760. } else
  2761. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
  2762. ioc->name, __func__));
  2763. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL,
  2764. 60, sleep_flag);
  2765. if (ioc_state) {
  2766. printk(MPT2SAS_ERR_FMT "%s: failed going to operational state "
  2767. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2768. r = -EFAULT;
  2769. }
  2770. out:
  2771. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2772. printk(MPT2SAS_INFO_FMT "port enable: %s\n",
  2773. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2774. return r;
  2775. }
  2776. /**
  2777. * _base_unmask_events - turn on notification for this event
  2778. * @ioc: per adapter object
  2779. * @event: firmware event
  2780. *
  2781. * The mask is stored in ioc->event_masks.
  2782. */
  2783. static void
  2784. _base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
  2785. {
  2786. u32 desired_event;
  2787. if (event >= 128)
  2788. return;
  2789. desired_event = (1 << (event % 32));
  2790. if (event < 32)
  2791. ioc->event_masks[0] &= ~desired_event;
  2792. else if (event < 64)
  2793. ioc->event_masks[1] &= ~desired_event;
  2794. else if (event < 96)
  2795. ioc->event_masks[2] &= ~desired_event;
  2796. else if (event < 128)
  2797. ioc->event_masks[3] &= ~desired_event;
  2798. }
  2799. /**
  2800. * _base_event_notification - send event notification
  2801. * @ioc: per adapter object
  2802. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2803. *
  2804. * Returns 0 for success, non-zero for failure.
  2805. */
  2806. static int
  2807. _base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2808. {
  2809. Mpi2EventNotificationRequest_t *mpi_request;
  2810. unsigned long timeleft;
  2811. u16 smid;
  2812. int r = 0;
  2813. int i;
  2814. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2815. __func__));
  2816. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2817. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2818. ioc->name, __func__);
  2819. return -EAGAIN;
  2820. }
  2821. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2822. if (!smid) {
  2823. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2824. ioc->name, __func__);
  2825. return -EAGAIN;
  2826. }
  2827. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2828. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2829. ioc->base_cmds.smid = smid;
  2830. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  2831. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  2832. mpi_request->VF_ID = 0; /* TODO */
  2833. mpi_request->VP_ID = 0;
  2834. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  2835. mpi_request->EventMasks[i] =
  2836. le32_to_cpu(ioc->event_masks[i]);
  2837. mpt2sas_base_put_smid_default(ioc, smid);
  2838. init_completion(&ioc->base_cmds.done);
  2839. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  2840. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2841. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2842. ioc->name, __func__);
  2843. _debug_dump_mf(mpi_request,
  2844. sizeof(Mpi2EventNotificationRequest_t)/4);
  2845. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2846. r = -EFAULT;
  2847. else
  2848. r = -ETIME;
  2849. } else
  2850. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
  2851. ioc->name, __func__));
  2852. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2853. return r;
  2854. }
  2855. /**
  2856. * mpt2sas_base_validate_event_type - validating event types
  2857. * @ioc: per adapter object
  2858. * @event: firmware event
  2859. *
  2860. * This will turn on firmware event notification when application
  2861. * ask for that event. We don't mask events that are already enabled.
  2862. */
  2863. void
  2864. mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
  2865. {
  2866. int i, j;
  2867. u32 event_mask, desired_event;
  2868. u8 send_update_to_fw;
  2869. for (i = 0, send_update_to_fw = 0; i <
  2870. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  2871. event_mask = ~event_type[i];
  2872. desired_event = 1;
  2873. for (j = 0; j < 32; j++) {
  2874. if (!(event_mask & desired_event) &&
  2875. (ioc->event_masks[i] & desired_event)) {
  2876. ioc->event_masks[i] &= ~desired_event;
  2877. send_update_to_fw = 1;
  2878. }
  2879. desired_event = (desired_event << 1);
  2880. }
  2881. }
  2882. if (!send_update_to_fw)
  2883. return;
  2884. mutex_lock(&ioc->base_cmds.mutex);
  2885. _base_event_notification(ioc, CAN_SLEEP);
  2886. mutex_unlock(&ioc->base_cmds.mutex);
  2887. }
  2888. /**
  2889. * _base_diag_reset - the "big hammer" start of day reset
  2890. * @ioc: per adapter object
  2891. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2892. *
  2893. * Returns 0 for success, non-zero for failure.
  2894. */
  2895. static int
  2896. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2897. {
  2898. u32 host_diagnostic;
  2899. u32 ioc_state;
  2900. u32 count;
  2901. u32 hcb_size;
  2902. printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
  2903. _base_save_msix_table(ioc);
  2904. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "clear interrupts\n",
  2905. ioc->name));
  2906. count = 0;
  2907. do {
  2908. /* Write magic sequence to WriteSequence register
  2909. * Loop until in diagnostic mode
  2910. */
  2911. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "write magic "
  2912. "sequence\n", ioc->name));
  2913. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2914. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  2915. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  2916. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  2917. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2918. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2919. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2920. /* wait 100 msec */
  2921. if (sleep_flag == CAN_SLEEP)
  2922. msleep(100);
  2923. else
  2924. mdelay(100);
  2925. if (count++ > 20)
  2926. goto out;
  2927. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2928. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "wrote magic "
  2929. "sequence: count(%d), host_diagnostic(0x%08x)\n",
  2930. ioc->name, count, host_diagnostic));
  2931. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  2932. hcb_size = readl(&ioc->chip->HCBSize);
  2933. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "diag reset: issued\n",
  2934. ioc->name));
  2935. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  2936. &ioc->chip->HostDiagnostic);
  2937. /* don't access any registers for 50 milliseconds */
  2938. msleep(50);
  2939. /* 300 second max wait */
  2940. for (count = 0; count < 3000000 ; count++) {
  2941. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2942. if (host_diagnostic == 0xFFFFFFFF)
  2943. goto out;
  2944. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  2945. break;
  2946. /* wait 100 msec */
  2947. if (sleep_flag == CAN_SLEEP)
  2948. msleep(1);
  2949. else
  2950. mdelay(1);
  2951. }
  2952. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  2953. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter "
  2954. "assuming the HCB Address points to good F/W\n",
  2955. ioc->name));
  2956. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  2957. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  2958. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  2959. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT
  2960. "re-enable the HCDW\n", ioc->name));
  2961. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  2962. &ioc->chip->HCBSize);
  2963. }
  2964. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter\n",
  2965. ioc->name));
  2966. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  2967. &ioc->chip->HostDiagnostic);
  2968. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "disable writes to the "
  2969. "diagnostic register\n", ioc->name));
  2970. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2971. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "Wait for FW to go to the "
  2972. "READY state\n", ioc->name));
  2973. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  2974. sleep_flag);
  2975. if (ioc_state) {
  2976. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2977. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2978. goto out;
  2979. }
  2980. _base_restore_msix_table(ioc);
  2981. printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
  2982. return 0;
  2983. out:
  2984. printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
  2985. return -EFAULT;
  2986. }
  2987. /**
  2988. * _base_make_ioc_ready - put controller in READY state
  2989. * @ioc: per adapter object
  2990. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2991. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  2992. *
  2993. * Returns 0 for success, non-zero for failure.
  2994. */
  2995. static int
  2996. _base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  2997. enum reset_type type)
  2998. {
  2999. u32 ioc_state;
  3000. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3001. __func__));
  3002. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3003. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: ioc_state(0x%08x)\n",
  3004. ioc->name, __func__, ioc_state));
  3005. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  3006. return 0;
  3007. if (ioc_state & MPI2_DOORBELL_USED) {
  3008. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "unexpected doorbell "
  3009. "active!\n", ioc->name));
  3010. goto issue_diag_reset;
  3011. }
  3012. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3013. mpt2sas_base_fault_info(ioc, ioc_state &
  3014. MPI2_DOORBELL_DATA_MASK);
  3015. goto issue_diag_reset;
  3016. }
  3017. if (type == FORCE_BIG_HAMMER)
  3018. goto issue_diag_reset;
  3019. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3020. if (!(_base_send_ioc_reset(ioc,
  3021. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP)))
  3022. return 0;
  3023. issue_diag_reset:
  3024. return _base_diag_reset(ioc, CAN_SLEEP);
  3025. }
  3026. /**
  3027. * _base_make_ioc_operational - put controller in OPERATIONAL state
  3028. * @ioc: per adapter object
  3029. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3030. *
  3031. * Returns 0 for success, non-zero for failure.
  3032. */
  3033. static int
  3034. _base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3035. {
  3036. int r, i;
  3037. unsigned long flags;
  3038. u32 reply_address;
  3039. u16 smid;
  3040. struct _tr_list *delayed_tr, *delayed_tr_next;
  3041. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3042. __func__));
  3043. /* clean the delayed target reset list */
  3044. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3045. &ioc->delayed_tr_list, list) {
  3046. list_del(&delayed_tr->list);
  3047. kfree(delayed_tr);
  3048. }
  3049. /* initialize the scsi lookup free list */
  3050. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3051. INIT_LIST_HEAD(&ioc->free_list);
  3052. smid = 1;
  3053. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  3054. ioc->scsi_lookup[i].cb_idx = 0xFF;
  3055. ioc->scsi_lookup[i].smid = smid;
  3056. ioc->scsi_lookup[i].scmd = NULL;
  3057. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  3058. &ioc->free_list);
  3059. }
  3060. /* hi-priority queue */
  3061. INIT_LIST_HEAD(&ioc->hpr_free_list);
  3062. smid = ioc->hi_priority_smid;
  3063. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  3064. ioc->hpr_lookup[i].cb_idx = 0xFF;
  3065. ioc->hpr_lookup[i].smid = smid;
  3066. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  3067. &ioc->hpr_free_list);
  3068. }
  3069. /* internal queue */
  3070. INIT_LIST_HEAD(&ioc->internal_free_list);
  3071. smid = ioc->internal_smid;
  3072. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  3073. ioc->internal_lookup[i].cb_idx = 0xFF;
  3074. ioc->internal_lookup[i].smid = smid;
  3075. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  3076. &ioc->internal_free_list);
  3077. }
  3078. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3079. /* initialize Reply Free Queue */
  3080. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3081. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3082. ioc->reply_sz)
  3083. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3084. /* initialize Reply Post Free Queue */
  3085. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3086. ioc->reply_post_free[i].Words = ULLONG_MAX;
  3087. r = _base_send_ioc_init(ioc, sleep_flag);
  3088. if (r)
  3089. return r;
  3090. /* initialize the index's */
  3091. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3092. ioc->reply_post_host_index = 0;
  3093. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3094. writel(0, &ioc->chip->ReplyPostHostIndex);
  3095. _base_unmask_interrupts(ioc);
  3096. r = _base_event_notification(ioc, sleep_flag);
  3097. if (r)
  3098. return r;
  3099. if (sleep_flag == CAN_SLEEP)
  3100. _base_static_config_pages(ioc);
  3101. r = _base_send_port_enable(ioc, sleep_flag);
  3102. if (r)
  3103. return r;
  3104. return r;
  3105. }
  3106. /**
  3107. * mpt2sas_base_free_resources - free resources controller resources (io/irq/memap)
  3108. * @ioc: per adapter object
  3109. *
  3110. * Return nothing.
  3111. */
  3112. void
  3113. mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
  3114. {
  3115. struct pci_dev *pdev = ioc->pdev;
  3116. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3117. __func__));
  3118. _base_mask_interrupts(ioc);
  3119. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3120. if (ioc->pci_irq) {
  3121. synchronize_irq(pdev->irq);
  3122. free_irq(ioc->pci_irq, ioc);
  3123. }
  3124. _base_disable_msix(ioc);
  3125. if (ioc->chip_phys)
  3126. iounmap(ioc->chip);
  3127. ioc->pci_irq = -1;
  3128. ioc->chip_phys = 0;
  3129. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3130. pci_disable_device(pdev);
  3131. return;
  3132. }
  3133. /**
  3134. * mpt2sas_base_attach - attach controller instance
  3135. * @ioc: per adapter object
  3136. *
  3137. * Returns 0 for success, non-zero for failure.
  3138. */
  3139. int
  3140. mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
  3141. {
  3142. int r, i;
  3143. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3144. __func__));
  3145. r = mpt2sas_base_map_resources(ioc);
  3146. if (r)
  3147. return r;
  3148. pci_set_drvdata(ioc->pdev, ioc->shost);
  3149. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  3150. if (r)
  3151. goto out_free_resources;
  3152. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3153. if (r)
  3154. goto out_free_resources;
  3155. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  3156. sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
  3157. if (!ioc->pfacts)
  3158. goto out_free_resources;
  3159. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  3160. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  3161. if (r)
  3162. goto out_free_resources;
  3163. }
  3164. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  3165. if (r)
  3166. goto out_free_resources;
  3167. init_waitqueue_head(&ioc->reset_wq);
  3168. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  3169. /* base internal command bits */
  3170. mutex_init(&ioc->base_cmds.mutex);
  3171. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3172. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3173. /* transport internal command bits */
  3174. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3175. ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
  3176. mutex_init(&ioc->transport_cmds.mutex);
  3177. /* scsih internal command bits */
  3178. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3179. ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
  3180. mutex_init(&ioc->scsih_cmds.mutex);
  3181. /* task management internal command bits */
  3182. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3183. ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
  3184. mutex_init(&ioc->tm_cmds.mutex);
  3185. /* config page internal command bits */
  3186. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3187. ioc->config_cmds.status = MPT2_CMD_NOT_USED;
  3188. mutex_init(&ioc->config_cmds.mutex);
  3189. /* ctl module internal command bits */
  3190. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3191. ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
  3192. mutex_init(&ioc->ctl_cmds.mutex);
  3193. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3194. ioc->event_masks[i] = -1;
  3195. /* here we enable the events we care about */
  3196. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  3197. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  3198. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  3199. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  3200. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  3201. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  3202. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  3203. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  3204. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  3205. _base_unmask_events(ioc, MPI2_EVENT_TASK_SET_FULL);
  3206. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  3207. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  3208. if (r)
  3209. goto out_free_resources;
  3210. mpt2sas_base_start_watchdog(ioc);
  3211. if (diag_buffer_enable != 0)
  3212. mpt2sas_enable_diag_buffer(ioc, diag_buffer_enable);
  3213. return 0;
  3214. out_free_resources:
  3215. ioc->remove_host = 1;
  3216. mpt2sas_base_free_resources(ioc);
  3217. _base_release_memory_pools(ioc);
  3218. pci_set_drvdata(ioc->pdev, NULL);
  3219. kfree(ioc->tm_cmds.reply);
  3220. kfree(ioc->transport_cmds.reply);
  3221. kfree(ioc->config_cmds.reply);
  3222. kfree(ioc->base_cmds.reply);
  3223. kfree(ioc->ctl_cmds.reply);
  3224. kfree(ioc->pfacts);
  3225. ioc->ctl_cmds.reply = NULL;
  3226. ioc->base_cmds.reply = NULL;
  3227. ioc->tm_cmds.reply = NULL;
  3228. ioc->transport_cmds.reply = NULL;
  3229. ioc->config_cmds.reply = NULL;
  3230. ioc->pfacts = NULL;
  3231. return r;
  3232. }
  3233. /**
  3234. * mpt2sas_base_detach - remove controller instance
  3235. * @ioc: per adapter object
  3236. *
  3237. * Return nothing.
  3238. */
  3239. void
  3240. mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
  3241. {
  3242. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3243. __func__));
  3244. mpt2sas_base_stop_watchdog(ioc);
  3245. mpt2sas_base_free_resources(ioc);
  3246. _base_release_memory_pools(ioc);
  3247. pci_set_drvdata(ioc->pdev, NULL);
  3248. kfree(ioc->pfacts);
  3249. kfree(ioc->ctl_cmds.reply);
  3250. kfree(ioc->base_cmds.reply);
  3251. kfree(ioc->tm_cmds.reply);
  3252. kfree(ioc->transport_cmds.reply);
  3253. kfree(ioc->config_cmds.reply);
  3254. }
  3255. /**
  3256. * _base_reset_handler - reset callback handler (for base)
  3257. * @ioc: per adapter object
  3258. * @reset_phase: phase
  3259. *
  3260. * The handler for doing any required cleanup or initialization.
  3261. *
  3262. * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
  3263. * MPT2_IOC_DONE_RESET
  3264. *
  3265. * Return nothing.
  3266. */
  3267. static void
  3268. _base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
  3269. {
  3270. switch (reset_phase) {
  3271. case MPT2_IOC_PRE_RESET:
  3272. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3273. "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
  3274. break;
  3275. case MPT2_IOC_AFTER_RESET:
  3276. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3277. "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
  3278. if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
  3279. ioc->transport_cmds.status |= MPT2_CMD_RESET;
  3280. mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  3281. complete(&ioc->transport_cmds.done);
  3282. }
  3283. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3284. ioc->base_cmds.status |= MPT2_CMD_RESET;
  3285. mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
  3286. complete(&ioc->base_cmds.done);
  3287. }
  3288. if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
  3289. ioc->config_cmds.status |= MPT2_CMD_RESET;
  3290. mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
  3291. ioc->config_cmds.smid = USHORT_MAX;
  3292. complete(&ioc->config_cmds.done);
  3293. }
  3294. break;
  3295. case MPT2_IOC_DONE_RESET:
  3296. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3297. "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
  3298. break;
  3299. }
  3300. mpt2sas_scsih_reset_handler(ioc, reset_phase);
  3301. mpt2sas_ctl_reset_handler(ioc, reset_phase);
  3302. }
  3303. /**
  3304. * _wait_for_commands_to_complete - reset controller
  3305. * @ioc: Pointer to MPT_ADAPTER structure
  3306. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3307. *
  3308. * This function waiting(3s) for all pending commands to complete
  3309. * prior to putting controller in reset.
  3310. */
  3311. static void
  3312. _wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3313. {
  3314. u32 ioc_state;
  3315. unsigned long flags;
  3316. u16 i;
  3317. ioc->pending_io_count = 0;
  3318. if (sleep_flag != CAN_SLEEP)
  3319. return;
  3320. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3321. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  3322. return;
  3323. /* pending command count */
  3324. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3325. for (i = 0; i < ioc->scsiio_depth; i++)
  3326. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  3327. ioc->pending_io_count++;
  3328. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3329. if (!ioc->pending_io_count)
  3330. return;
  3331. /* wait for pending commands to complete */
  3332. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 3 * HZ);
  3333. }
  3334. /**
  3335. * mpt2sas_base_hard_reset_handler - reset controller
  3336. * @ioc: Pointer to MPT_ADAPTER structure
  3337. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3338. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3339. *
  3340. * Returns 0 for success, non-zero for failure.
  3341. */
  3342. int
  3343. mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3344. enum reset_type type)
  3345. {
  3346. int r;
  3347. unsigned long flags;
  3348. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name,
  3349. __func__));
  3350. if (mpt2sas_fwfault_debug)
  3351. mpt2sas_halt_firmware(ioc);
  3352. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3353. if (ioc->shost_recovery) {
  3354. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3355. printk(MPT2SAS_ERR_FMT "%s: busy\n",
  3356. ioc->name, __func__);
  3357. return -EBUSY;
  3358. }
  3359. ioc->shost_recovery = 1;
  3360. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3361. _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
  3362. _wait_for_commands_to_complete(ioc, sleep_flag);
  3363. _base_mask_interrupts(ioc);
  3364. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  3365. if (r)
  3366. goto out;
  3367. _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
  3368. r = _base_make_ioc_operational(ioc, sleep_flag);
  3369. if (!r)
  3370. _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
  3371. out:
  3372. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: %s\n",
  3373. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  3374. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3375. ioc->shost_recovery = 0;
  3376. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3377. if (!r)
  3378. _base_reset_handler(ioc, MPT2_IOC_RUNNING);
  3379. return r;
  3380. }