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/drivers/crypto/talitos.c

https://bitbucket.org/abioy/linux
C | 1991 lines | 1453 code | 316 blank | 222 comment | 176 complexity | eefbba48d11fc14b7459844447d4d391 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * talitos - Freescale Integrated Security Engine (SEC) device driver
  3. *
  4. * Copyright (c) 2008 Freescale Semiconductor, Inc.
  5. *
  6. * Scatterlist Crypto API glue code copied from files with the following:
  7. * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
  8. *
  9. * Crypto algorithm registration code copied from hifn driver:
  10. * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11. * All rights reserved.
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. */
  27. #include <linux/kernel.h>
  28. #include <linux/module.h>
  29. #include <linux/mod_devicetable.h>
  30. #include <linux/device.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/crypto.h>
  33. #include <linux/hw_random.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/io.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/rtnetlink.h>
  39. #include <linux/slab.h>
  40. #include <crypto/algapi.h>
  41. #include <crypto/aes.h>
  42. #include <crypto/des.h>
  43. #include <crypto/sha.h>
  44. #include <crypto/aead.h>
  45. #include <crypto/authenc.h>
  46. #include <crypto/skcipher.h>
  47. #include <crypto/scatterwalk.h>
  48. #include "talitos.h"
  49. #define TALITOS_TIMEOUT 100000
  50. #define TALITOS_MAX_DATA_LEN 65535
  51. #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  52. #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  53. #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  54. /* descriptor pointer entry */
  55. struct talitos_ptr {
  56. __be16 len; /* length */
  57. u8 j_extent; /* jump to sg link table and/or extent */
  58. u8 eptr; /* extended address */
  59. __be32 ptr; /* address */
  60. };
  61. /* descriptor */
  62. struct talitos_desc {
  63. __be32 hdr; /* header high bits */
  64. __be32 hdr_lo; /* header low bits */
  65. struct talitos_ptr ptr[7]; /* ptr/len pair array */
  66. };
  67. /**
  68. * talitos_request - descriptor submission request
  69. * @desc: descriptor pointer (kernel virtual)
  70. * @dma_desc: descriptor's physical bus address
  71. * @callback: whom to call when descriptor processing is done
  72. * @context: caller context (optional)
  73. */
  74. struct talitos_request {
  75. struct talitos_desc *desc;
  76. dma_addr_t dma_desc;
  77. void (*callback) (struct device *dev, struct talitos_desc *desc,
  78. void *context, int error);
  79. void *context;
  80. };
  81. /* per-channel fifo management */
  82. struct talitos_channel {
  83. /* request fifo */
  84. struct talitos_request *fifo;
  85. /* number of requests pending in channel h/w fifo */
  86. atomic_t submit_count ____cacheline_aligned;
  87. /* request submission (head) lock */
  88. spinlock_t head_lock ____cacheline_aligned;
  89. /* index to next free descriptor request */
  90. int head;
  91. /* request release (tail) lock */
  92. spinlock_t tail_lock ____cacheline_aligned;
  93. /* index to next in-progress/done descriptor request */
  94. int tail;
  95. };
  96. struct talitos_private {
  97. struct device *dev;
  98. struct of_device *ofdev;
  99. void __iomem *reg;
  100. int irq;
  101. /* SEC version geometry (from device tree node) */
  102. unsigned int num_channels;
  103. unsigned int chfifo_len;
  104. unsigned int exec_units;
  105. unsigned int desc_types;
  106. /* SEC Compatibility info */
  107. unsigned long features;
  108. /*
  109. * length of the request fifo
  110. * fifo_len is chfifo_len rounded up to next power of 2
  111. * so we can use bitwise ops to wrap
  112. */
  113. unsigned int fifo_len;
  114. struct talitos_channel *chan;
  115. /* next channel to be assigned next incoming descriptor */
  116. atomic_t last_chan ____cacheline_aligned;
  117. /* request callback tasklet */
  118. struct tasklet_struct done_task;
  119. /* list of registered algorithms */
  120. struct list_head alg_list;
  121. /* hwrng device */
  122. struct hwrng rng;
  123. };
  124. /* .features flag */
  125. #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
  126. #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
  127. static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  128. {
  129. talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  130. talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
  131. }
  132. /*
  133. * map virtual single (contiguous) pointer to h/w descriptor pointer
  134. */
  135. static void map_single_talitos_ptr(struct device *dev,
  136. struct talitos_ptr *talitos_ptr,
  137. unsigned short len, void *data,
  138. unsigned char extent,
  139. enum dma_data_direction dir)
  140. {
  141. dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  142. talitos_ptr->len = cpu_to_be16(len);
  143. to_talitos_ptr(talitos_ptr, dma_addr);
  144. talitos_ptr->j_extent = extent;
  145. }
  146. /*
  147. * unmap bus single (contiguous) h/w descriptor pointer
  148. */
  149. static void unmap_single_talitos_ptr(struct device *dev,
  150. struct talitos_ptr *talitos_ptr,
  151. enum dma_data_direction dir)
  152. {
  153. dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  154. be16_to_cpu(talitos_ptr->len), dir);
  155. }
  156. static int reset_channel(struct device *dev, int ch)
  157. {
  158. struct talitos_private *priv = dev_get_drvdata(dev);
  159. unsigned int timeout = TALITOS_TIMEOUT;
  160. setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
  161. while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
  162. && --timeout)
  163. cpu_relax();
  164. if (timeout == 0) {
  165. dev_err(dev, "failed to reset channel %d\n", ch);
  166. return -EIO;
  167. }
  168. /* set 36-bit addressing, done writeback enable and done IRQ enable */
  169. setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
  170. TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
  171. /* and ICCR writeback, if available */
  172. if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
  173. setbits32(priv->reg + TALITOS_CCCR_LO(ch),
  174. TALITOS_CCCR_LO_IWSE);
  175. return 0;
  176. }
  177. static int reset_device(struct device *dev)
  178. {
  179. struct talitos_private *priv = dev_get_drvdata(dev);
  180. unsigned int timeout = TALITOS_TIMEOUT;
  181. setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
  182. while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
  183. && --timeout)
  184. cpu_relax();
  185. if (timeout == 0) {
  186. dev_err(dev, "failed to reset device\n");
  187. return -EIO;
  188. }
  189. return 0;
  190. }
  191. /*
  192. * Reset and initialize the device
  193. */
  194. static int init_device(struct device *dev)
  195. {
  196. struct talitos_private *priv = dev_get_drvdata(dev);
  197. int ch, err;
  198. /*
  199. * Master reset
  200. * errata documentation: warning: certain SEC interrupts
  201. * are not fully cleared by writing the MCR:SWR bit,
  202. * set bit twice to completely reset
  203. */
  204. err = reset_device(dev);
  205. if (err)
  206. return err;
  207. err = reset_device(dev);
  208. if (err)
  209. return err;
  210. /* reset channels */
  211. for (ch = 0; ch < priv->num_channels; ch++) {
  212. err = reset_channel(dev, ch);
  213. if (err)
  214. return err;
  215. }
  216. /* enable channel done and error interrupts */
  217. setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
  218. setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
  219. /* disable integrity check error interrupts (use writeback instead) */
  220. if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
  221. setbits32(priv->reg + TALITOS_MDEUICR_LO,
  222. TALITOS_MDEUICR_LO_ICE);
  223. return 0;
  224. }
  225. /**
  226. * talitos_submit - submits a descriptor to the device for processing
  227. * @dev: the SEC device to be used
  228. * @desc: the descriptor to be processed by the device
  229. * @callback: whom to call when processing is complete
  230. * @context: a handle for use by caller (optional)
  231. *
  232. * desc must contain valid dma-mapped (bus physical) address pointers.
  233. * callback must check err and feedback in descriptor header
  234. * for device processing status.
  235. */
  236. static int talitos_submit(struct device *dev, struct talitos_desc *desc,
  237. void (*callback)(struct device *dev,
  238. struct talitos_desc *desc,
  239. void *context, int error),
  240. void *context)
  241. {
  242. struct talitos_private *priv = dev_get_drvdata(dev);
  243. struct talitos_request *request;
  244. unsigned long flags, ch;
  245. int head;
  246. /* select done notification */
  247. desc->hdr |= DESC_HDR_DONE_NOTIFY;
  248. /* emulate SEC's round-robin channel fifo polling scheme */
  249. ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
  250. spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
  251. if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
  252. /* h/w fifo is full */
  253. spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
  254. return -EAGAIN;
  255. }
  256. head = priv->chan[ch].head;
  257. request = &priv->chan[ch].fifo[head];
  258. /* map descriptor and save caller data */
  259. request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
  260. DMA_BIDIRECTIONAL);
  261. request->callback = callback;
  262. request->context = context;
  263. /* increment fifo head */
  264. priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
  265. smp_wmb();
  266. request->desc = desc;
  267. /* GO! */
  268. wmb();
  269. out_be32(priv->reg + TALITOS_FF(ch),
  270. cpu_to_be32(upper_32_bits(request->dma_desc)));
  271. out_be32(priv->reg + TALITOS_FF_LO(ch),
  272. cpu_to_be32(lower_32_bits(request->dma_desc)));
  273. spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
  274. return -EINPROGRESS;
  275. }
  276. /*
  277. * process what was done, notify callback of error if not
  278. */
  279. static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
  280. {
  281. struct talitos_private *priv = dev_get_drvdata(dev);
  282. struct talitos_request *request, saved_req;
  283. unsigned long flags;
  284. int tail, status;
  285. spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
  286. tail = priv->chan[ch].tail;
  287. while (priv->chan[ch].fifo[tail].desc) {
  288. request = &priv->chan[ch].fifo[tail];
  289. /* descriptors with their done bits set don't get the error */
  290. rmb();
  291. if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
  292. status = 0;
  293. else
  294. if (!error)
  295. break;
  296. else
  297. status = error;
  298. dma_unmap_single(dev, request->dma_desc,
  299. sizeof(struct talitos_desc),
  300. DMA_BIDIRECTIONAL);
  301. /* copy entries so we can call callback outside lock */
  302. saved_req.desc = request->desc;
  303. saved_req.callback = request->callback;
  304. saved_req.context = request->context;
  305. /* release request entry in fifo */
  306. smp_wmb();
  307. request->desc = NULL;
  308. /* increment fifo tail */
  309. priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
  310. spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
  311. atomic_dec(&priv->chan[ch].submit_count);
  312. saved_req.callback(dev, saved_req.desc, saved_req.context,
  313. status);
  314. /* channel may resume processing in single desc error case */
  315. if (error && !reset_ch && status == error)
  316. return;
  317. spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
  318. tail = priv->chan[ch].tail;
  319. }
  320. spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
  321. }
  322. /*
  323. * process completed requests for channels that have done status
  324. */
  325. static void talitos_done(unsigned long data)
  326. {
  327. struct device *dev = (struct device *)data;
  328. struct talitos_private *priv = dev_get_drvdata(dev);
  329. int ch;
  330. for (ch = 0; ch < priv->num_channels; ch++)
  331. flush_channel(dev, ch, 0, 0);
  332. /* At this point, all completed channels have been processed.
  333. * Unmask done interrupts for channels completed later on.
  334. */
  335. setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
  336. setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
  337. }
  338. /*
  339. * locate current (offending) descriptor
  340. */
  341. static struct talitos_desc *current_desc(struct device *dev, int ch)
  342. {
  343. struct talitos_private *priv = dev_get_drvdata(dev);
  344. int tail = priv->chan[ch].tail;
  345. dma_addr_t cur_desc;
  346. cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
  347. while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
  348. tail = (tail + 1) & (priv->fifo_len - 1);
  349. if (tail == priv->chan[ch].tail) {
  350. dev_err(dev, "couldn't locate current descriptor\n");
  351. return NULL;
  352. }
  353. }
  354. return priv->chan[ch].fifo[tail].desc;
  355. }
  356. /*
  357. * user diagnostics; report root cause of error based on execution unit status
  358. */
  359. static void report_eu_error(struct device *dev, int ch,
  360. struct talitos_desc *desc)
  361. {
  362. struct talitos_private *priv = dev_get_drvdata(dev);
  363. int i;
  364. switch (desc->hdr & DESC_HDR_SEL0_MASK) {
  365. case DESC_HDR_SEL0_AFEU:
  366. dev_err(dev, "AFEUISR 0x%08x_%08x\n",
  367. in_be32(priv->reg + TALITOS_AFEUISR),
  368. in_be32(priv->reg + TALITOS_AFEUISR_LO));
  369. break;
  370. case DESC_HDR_SEL0_DEU:
  371. dev_err(dev, "DEUISR 0x%08x_%08x\n",
  372. in_be32(priv->reg + TALITOS_DEUISR),
  373. in_be32(priv->reg + TALITOS_DEUISR_LO));
  374. break;
  375. case DESC_HDR_SEL0_MDEUA:
  376. case DESC_HDR_SEL0_MDEUB:
  377. dev_err(dev, "MDEUISR 0x%08x_%08x\n",
  378. in_be32(priv->reg + TALITOS_MDEUISR),
  379. in_be32(priv->reg + TALITOS_MDEUISR_LO));
  380. break;
  381. case DESC_HDR_SEL0_RNG:
  382. dev_err(dev, "RNGUISR 0x%08x_%08x\n",
  383. in_be32(priv->reg + TALITOS_RNGUISR),
  384. in_be32(priv->reg + TALITOS_RNGUISR_LO));
  385. break;
  386. case DESC_HDR_SEL0_PKEU:
  387. dev_err(dev, "PKEUISR 0x%08x_%08x\n",
  388. in_be32(priv->reg + TALITOS_PKEUISR),
  389. in_be32(priv->reg + TALITOS_PKEUISR_LO));
  390. break;
  391. case DESC_HDR_SEL0_AESU:
  392. dev_err(dev, "AESUISR 0x%08x_%08x\n",
  393. in_be32(priv->reg + TALITOS_AESUISR),
  394. in_be32(priv->reg + TALITOS_AESUISR_LO));
  395. break;
  396. case DESC_HDR_SEL0_CRCU:
  397. dev_err(dev, "CRCUISR 0x%08x_%08x\n",
  398. in_be32(priv->reg + TALITOS_CRCUISR),
  399. in_be32(priv->reg + TALITOS_CRCUISR_LO));
  400. break;
  401. case DESC_HDR_SEL0_KEU:
  402. dev_err(dev, "KEUISR 0x%08x_%08x\n",
  403. in_be32(priv->reg + TALITOS_KEUISR),
  404. in_be32(priv->reg + TALITOS_KEUISR_LO));
  405. break;
  406. }
  407. switch (desc->hdr & DESC_HDR_SEL1_MASK) {
  408. case DESC_HDR_SEL1_MDEUA:
  409. case DESC_HDR_SEL1_MDEUB:
  410. dev_err(dev, "MDEUISR 0x%08x_%08x\n",
  411. in_be32(priv->reg + TALITOS_MDEUISR),
  412. in_be32(priv->reg + TALITOS_MDEUISR_LO));
  413. break;
  414. case DESC_HDR_SEL1_CRCU:
  415. dev_err(dev, "CRCUISR 0x%08x_%08x\n",
  416. in_be32(priv->reg + TALITOS_CRCUISR),
  417. in_be32(priv->reg + TALITOS_CRCUISR_LO));
  418. break;
  419. }
  420. for (i = 0; i < 8; i++)
  421. dev_err(dev, "DESCBUF 0x%08x_%08x\n",
  422. in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
  423. in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
  424. }
  425. /*
  426. * recover from error interrupts
  427. */
  428. static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
  429. {
  430. struct device *dev = (struct device *)data;
  431. struct talitos_private *priv = dev_get_drvdata(dev);
  432. unsigned int timeout = TALITOS_TIMEOUT;
  433. int ch, error, reset_dev = 0, reset_ch = 0;
  434. u32 v, v_lo;
  435. for (ch = 0; ch < priv->num_channels; ch++) {
  436. /* skip channels without errors */
  437. if (!(isr & (1 << (ch * 2 + 1))))
  438. continue;
  439. error = -EINVAL;
  440. v = in_be32(priv->reg + TALITOS_CCPSR(ch));
  441. v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
  442. if (v_lo & TALITOS_CCPSR_LO_DOF) {
  443. dev_err(dev, "double fetch fifo overflow error\n");
  444. error = -EAGAIN;
  445. reset_ch = 1;
  446. }
  447. if (v_lo & TALITOS_CCPSR_LO_SOF) {
  448. /* h/w dropped descriptor */
  449. dev_err(dev, "single fetch fifo overflow error\n");
  450. error = -EAGAIN;
  451. }
  452. if (v_lo & TALITOS_CCPSR_LO_MDTE)
  453. dev_err(dev, "master data transfer error\n");
  454. if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
  455. dev_err(dev, "s/g data length zero error\n");
  456. if (v_lo & TALITOS_CCPSR_LO_FPZ)
  457. dev_err(dev, "fetch pointer zero error\n");
  458. if (v_lo & TALITOS_CCPSR_LO_IDH)
  459. dev_err(dev, "illegal descriptor header error\n");
  460. if (v_lo & TALITOS_CCPSR_LO_IEU)
  461. dev_err(dev, "invalid execution unit error\n");
  462. if (v_lo & TALITOS_CCPSR_LO_EU)
  463. report_eu_error(dev, ch, current_desc(dev, ch));
  464. if (v_lo & TALITOS_CCPSR_LO_GB)
  465. dev_err(dev, "gather boundary error\n");
  466. if (v_lo & TALITOS_CCPSR_LO_GRL)
  467. dev_err(dev, "gather return/length error\n");
  468. if (v_lo & TALITOS_CCPSR_LO_SB)
  469. dev_err(dev, "scatter boundary error\n");
  470. if (v_lo & TALITOS_CCPSR_LO_SRL)
  471. dev_err(dev, "scatter return/length error\n");
  472. flush_channel(dev, ch, error, reset_ch);
  473. if (reset_ch) {
  474. reset_channel(dev, ch);
  475. } else {
  476. setbits32(priv->reg + TALITOS_CCCR(ch),
  477. TALITOS_CCCR_CONT);
  478. setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
  479. while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
  480. TALITOS_CCCR_CONT) && --timeout)
  481. cpu_relax();
  482. if (timeout == 0) {
  483. dev_err(dev, "failed to restart channel %d\n",
  484. ch);
  485. reset_dev = 1;
  486. }
  487. }
  488. }
  489. if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
  490. dev_err(dev, "done overflow, internal time out, or rngu error: "
  491. "ISR 0x%08x_%08x\n", isr, isr_lo);
  492. /* purge request queues */
  493. for (ch = 0; ch < priv->num_channels; ch++)
  494. flush_channel(dev, ch, -EIO, 1);
  495. /* reset and reinitialize the device */
  496. init_device(dev);
  497. }
  498. }
  499. static irqreturn_t talitos_interrupt(int irq, void *data)
  500. {
  501. struct device *dev = data;
  502. struct talitos_private *priv = dev_get_drvdata(dev);
  503. u32 isr, isr_lo;
  504. isr = in_be32(priv->reg + TALITOS_ISR);
  505. isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
  506. /* Acknowledge interrupt */
  507. out_be32(priv->reg + TALITOS_ICR, isr);
  508. out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
  509. if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
  510. talitos_error((unsigned long)data, isr, isr_lo);
  511. else
  512. if (likely(isr & TALITOS_ISR_CHDONE)) {
  513. /* mask further done interrupts. */
  514. clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
  515. /* done_task will unmask done interrupts at exit */
  516. tasklet_schedule(&priv->done_task);
  517. }
  518. return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
  519. }
  520. /*
  521. * hwrng
  522. */
  523. static int talitos_rng_data_present(struct hwrng *rng, int wait)
  524. {
  525. struct device *dev = (struct device *)rng->priv;
  526. struct talitos_private *priv = dev_get_drvdata(dev);
  527. u32 ofl;
  528. int i;
  529. for (i = 0; i < 20; i++) {
  530. ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
  531. TALITOS_RNGUSR_LO_OFL;
  532. if (ofl || !wait)
  533. break;
  534. udelay(10);
  535. }
  536. return !!ofl;
  537. }
  538. static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
  539. {
  540. struct device *dev = (struct device *)rng->priv;
  541. struct talitos_private *priv = dev_get_drvdata(dev);
  542. /* rng fifo requires 64-bit accesses */
  543. *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
  544. *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
  545. return sizeof(u32);
  546. }
  547. static int talitos_rng_init(struct hwrng *rng)
  548. {
  549. struct device *dev = (struct device *)rng->priv;
  550. struct talitos_private *priv = dev_get_drvdata(dev);
  551. unsigned int timeout = TALITOS_TIMEOUT;
  552. setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
  553. while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
  554. && --timeout)
  555. cpu_relax();
  556. if (timeout == 0) {
  557. dev_err(dev, "failed to reset rng hw\n");
  558. return -ENODEV;
  559. }
  560. /* start generating */
  561. setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
  562. return 0;
  563. }
  564. static int talitos_register_rng(struct device *dev)
  565. {
  566. struct talitos_private *priv = dev_get_drvdata(dev);
  567. priv->rng.name = dev_driver_string(dev),
  568. priv->rng.init = talitos_rng_init,
  569. priv->rng.data_present = talitos_rng_data_present,
  570. priv->rng.data_read = talitos_rng_data_read,
  571. priv->rng.priv = (unsigned long)dev;
  572. return hwrng_register(&priv->rng);
  573. }
  574. static void talitos_unregister_rng(struct device *dev)
  575. {
  576. struct talitos_private *priv = dev_get_drvdata(dev);
  577. hwrng_unregister(&priv->rng);
  578. }
  579. /*
  580. * crypto alg
  581. */
  582. #define TALITOS_CRA_PRIORITY 3000
  583. #define TALITOS_MAX_KEY_SIZE 64
  584. #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
  585. #define MD5_DIGEST_SIZE 16
  586. struct talitos_ctx {
  587. struct device *dev;
  588. __be32 desc_hdr_template;
  589. u8 key[TALITOS_MAX_KEY_SIZE];
  590. u8 iv[TALITOS_MAX_IV_LENGTH];
  591. unsigned int keylen;
  592. unsigned int enckeylen;
  593. unsigned int authkeylen;
  594. unsigned int authsize;
  595. };
  596. static int aead_setauthsize(struct crypto_aead *authenc,
  597. unsigned int authsize)
  598. {
  599. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  600. ctx->authsize = authsize;
  601. return 0;
  602. }
  603. static int aead_setkey(struct crypto_aead *authenc,
  604. const u8 *key, unsigned int keylen)
  605. {
  606. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  607. struct rtattr *rta = (void *)key;
  608. struct crypto_authenc_key_param *param;
  609. unsigned int authkeylen;
  610. unsigned int enckeylen;
  611. if (!RTA_OK(rta, keylen))
  612. goto badkey;
  613. if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
  614. goto badkey;
  615. if (RTA_PAYLOAD(rta) < sizeof(*param))
  616. goto badkey;
  617. param = RTA_DATA(rta);
  618. enckeylen = be32_to_cpu(param->enckeylen);
  619. key += RTA_ALIGN(rta->rta_len);
  620. keylen -= RTA_ALIGN(rta->rta_len);
  621. if (keylen < enckeylen)
  622. goto badkey;
  623. authkeylen = keylen - enckeylen;
  624. if (keylen > TALITOS_MAX_KEY_SIZE)
  625. goto badkey;
  626. memcpy(&ctx->key, key, keylen);
  627. ctx->keylen = keylen;
  628. ctx->enckeylen = enckeylen;
  629. ctx->authkeylen = authkeylen;
  630. return 0;
  631. badkey:
  632. crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
  633. return -EINVAL;
  634. }
  635. /*
  636. * talitos_edesc - s/w-extended descriptor
  637. * @src_nents: number of segments in input scatterlist
  638. * @dst_nents: number of segments in output scatterlist
  639. * @dma_len: length of dma mapped link_tbl space
  640. * @dma_link_tbl: bus physical address of link_tbl
  641. * @desc: h/w descriptor
  642. * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
  643. *
  644. * if decrypting (with authcheck), or either one of src_nents or dst_nents
  645. * is greater than 1, an integrity check value is concatenated to the end
  646. * of link_tbl data
  647. */
  648. struct talitos_edesc {
  649. int src_nents;
  650. int dst_nents;
  651. int src_is_chained;
  652. int dst_is_chained;
  653. int dma_len;
  654. dma_addr_t dma_link_tbl;
  655. struct talitos_desc desc;
  656. struct talitos_ptr link_tbl[0];
  657. };
  658. static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
  659. unsigned int nents, enum dma_data_direction dir,
  660. int chained)
  661. {
  662. if (unlikely(chained))
  663. while (sg) {
  664. dma_map_sg(dev, sg, 1, dir);
  665. sg = scatterwalk_sg_next(sg);
  666. }
  667. else
  668. dma_map_sg(dev, sg, nents, dir);
  669. return nents;
  670. }
  671. static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
  672. enum dma_data_direction dir)
  673. {
  674. while (sg) {
  675. dma_unmap_sg(dev, sg, 1, dir);
  676. sg = scatterwalk_sg_next(sg);
  677. }
  678. }
  679. static void talitos_sg_unmap(struct device *dev,
  680. struct talitos_edesc *edesc,
  681. struct scatterlist *src,
  682. struct scatterlist *dst)
  683. {
  684. unsigned int src_nents = edesc->src_nents ? : 1;
  685. unsigned int dst_nents = edesc->dst_nents ? : 1;
  686. if (src != dst) {
  687. if (edesc->src_is_chained)
  688. talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
  689. else
  690. dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
  691. if (edesc->dst_is_chained)
  692. talitos_unmap_sg_chain(dev, dst, DMA_FROM_DEVICE);
  693. else
  694. dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
  695. } else
  696. if (edesc->src_is_chained)
  697. talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
  698. else
  699. dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
  700. }
  701. static void ipsec_esp_unmap(struct device *dev,
  702. struct talitos_edesc *edesc,
  703. struct aead_request *areq)
  704. {
  705. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
  706. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
  707. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
  708. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
  709. dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
  710. talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
  711. if (edesc->dma_len)
  712. dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
  713. DMA_BIDIRECTIONAL);
  714. }
  715. /*
  716. * ipsec_esp descriptor callbacks
  717. */
  718. static void ipsec_esp_encrypt_done(struct device *dev,
  719. struct talitos_desc *desc, void *context,
  720. int err)
  721. {
  722. struct aead_request *areq = context;
  723. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  724. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  725. struct talitos_edesc *edesc;
  726. struct scatterlist *sg;
  727. void *icvdata;
  728. edesc = container_of(desc, struct talitos_edesc, desc);
  729. ipsec_esp_unmap(dev, edesc, areq);
  730. /* copy the generated ICV to dst */
  731. if (edesc->dma_len) {
  732. icvdata = &edesc->link_tbl[edesc->src_nents +
  733. edesc->dst_nents + 2];
  734. sg = sg_last(areq->dst, edesc->dst_nents);
  735. memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
  736. icvdata, ctx->authsize);
  737. }
  738. kfree(edesc);
  739. aead_request_complete(areq, err);
  740. }
  741. static void ipsec_esp_decrypt_swauth_done(struct device *dev,
  742. struct talitos_desc *desc,
  743. void *context, int err)
  744. {
  745. struct aead_request *req = context;
  746. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  747. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  748. struct talitos_edesc *edesc;
  749. struct scatterlist *sg;
  750. void *icvdata;
  751. edesc = container_of(desc, struct talitos_edesc, desc);
  752. ipsec_esp_unmap(dev, edesc, req);
  753. if (!err) {
  754. /* auth check */
  755. if (edesc->dma_len)
  756. icvdata = &edesc->link_tbl[edesc->src_nents +
  757. edesc->dst_nents + 2];
  758. else
  759. icvdata = &edesc->link_tbl[0];
  760. sg = sg_last(req->dst, edesc->dst_nents ? : 1);
  761. err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
  762. ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
  763. }
  764. kfree(edesc);
  765. aead_request_complete(req, err);
  766. }
  767. static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
  768. struct talitos_desc *desc,
  769. void *context, int err)
  770. {
  771. struct aead_request *req = context;
  772. struct talitos_edesc *edesc;
  773. edesc = container_of(desc, struct talitos_edesc, desc);
  774. ipsec_esp_unmap(dev, edesc, req);
  775. /* check ICV auth status */
  776. if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
  777. DESC_HDR_LO_ICCR1_PASS))
  778. err = -EBADMSG;
  779. kfree(edesc);
  780. aead_request_complete(req, err);
  781. }
  782. /*
  783. * convert scatterlist to SEC h/w link table format
  784. * stop at cryptlen bytes
  785. */
  786. static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
  787. int cryptlen, struct talitos_ptr *link_tbl_ptr)
  788. {
  789. int n_sg = sg_count;
  790. while (n_sg--) {
  791. to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
  792. link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
  793. link_tbl_ptr->j_extent = 0;
  794. link_tbl_ptr++;
  795. cryptlen -= sg_dma_len(sg);
  796. sg = scatterwalk_sg_next(sg);
  797. }
  798. /* adjust (decrease) last one (or two) entry's len to cryptlen */
  799. link_tbl_ptr--;
  800. while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
  801. /* Empty this entry, and move to previous one */
  802. cryptlen += be16_to_cpu(link_tbl_ptr->len);
  803. link_tbl_ptr->len = 0;
  804. sg_count--;
  805. link_tbl_ptr--;
  806. }
  807. link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
  808. + cryptlen);
  809. /* tag end of link table */
  810. link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
  811. return sg_count;
  812. }
  813. /*
  814. * fill in and submit ipsec_esp descriptor
  815. */
  816. static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
  817. u8 *giv, u64 seq,
  818. void (*callback) (struct device *dev,
  819. struct talitos_desc *desc,
  820. void *context, int error))
  821. {
  822. struct crypto_aead *aead = crypto_aead_reqtfm(areq);
  823. struct talitos_ctx *ctx = crypto_aead_ctx(aead);
  824. struct device *dev = ctx->dev;
  825. struct talitos_desc *desc = &edesc->desc;
  826. unsigned int cryptlen = areq->cryptlen;
  827. unsigned int authsize = ctx->authsize;
  828. unsigned int ivsize = crypto_aead_ivsize(aead);
  829. int sg_count, ret;
  830. int sg_link_tbl_len;
  831. /* hmac key */
  832. map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
  833. 0, DMA_TO_DEVICE);
  834. /* hmac data */
  835. map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
  836. sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
  837. /* cipher iv */
  838. map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
  839. DMA_TO_DEVICE);
  840. /* cipher key */
  841. map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
  842. (char *)&ctx->key + ctx->authkeylen, 0,
  843. DMA_TO_DEVICE);
  844. /*
  845. * cipher in
  846. * map and adjust cipher len to aead request cryptlen.
  847. * extent is bytes of HMAC postpended to ciphertext,
  848. * typically 12 for ipsec
  849. */
  850. desc->ptr[4].len = cpu_to_be16(cryptlen);
  851. desc->ptr[4].j_extent = authsize;
  852. sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
  853. (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
  854. : DMA_TO_DEVICE,
  855. edesc->src_is_chained);
  856. if (sg_count == 1) {
  857. to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
  858. } else {
  859. sg_link_tbl_len = cryptlen;
  860. if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
  861. sg_link_tbl_len = cryptlen + authsize;
  862. sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
  863. &edesc->link_tbl[0]);
  864. if (sg_count > 1) {
  865. desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
  866. to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
  867. dma_sync_single_for_device(dev, edesc->dma_link_tbl,
  868. edesc->dma_len,
  869. DMA_BIDIRECTIONAL);
  870. } else {
  871. /* Only one segment now, so no link tbl needed */
  872. to_talitos_ptr(&desc->ptr[4],
  873. sg_dma_address(areq->src));
  874. }
  875. }
  876. /* cipher out */
  877. desc->ptr[5].len = cpu_to_be16(cryptlen);
  878. desc->ptr[5].j_extent = authsize;
  879. if (areq->src != areq->dst)
  880. sg_count = talitos_map_sg(dev, areq->dst,
  881. edesc->dst_nents ? : 1,
  882. DMA_FROM_DEVICE,
  883. edesc->dst_is_chained);
  884. if (sg_count == 1) {
  885. to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
  886. } else {
  887. struct talitos_ptr *link_tbl_ptr =
  888. &edesc->link_tbl[edesc->src_nents + 1];
  889. to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
  890. (edesc->src_nents + 1) *
  891. sizeof(struct talitos_ptr));
  892. sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
  893. link_tbl_ptr);
  894. /* Add an entry to the link table for ICV data */
  895. link_tbl_ptr += sg_count - 1;
  896. link_tbl_ptr->j_extent = 0;
  897. sg_count++;
  898. link_tbl_ptr++;
  899. link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
  900. link_tbl_ptr->len = cpu_to_be16(authsize);
  901. /* icv data follows link tables */
  902. to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
  903. (edesc->src_nents + edesc->dst_nents + 2) *
  904. sizeof(struct talitos_ptr));
  905. desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
  906. dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
  907. edesc->dma_len, DMA_BIDIRECTIONAL);
  908. }
  909. /* iv out */
  910. map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
  911. DMA_FROM_DEVICE);
  912. ret = talitos_submit(dev, desc, callback, areq);
  913. if (ret != -EINPROGRESS) {
  914. ipsec_esp_unmap(dev, edesc, areq);
  915. kfree(edesc);
  916. }
  917. return ret;
  918. }
  919. /*
  920. * derive number of elements in scatterlist
  921. */
  922. static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
  923. {
  924. struct scatterlist *sg = sg_list;
  925. int sg_nents = 0;
  926. *chained = 0;
  927. while (nbytes > 0) {
  928. sg_nents++;
  929. nbytes -= sg->length;
  930. if (!sg_is_last(sg) && (sg + 1)->length == 0)
  931. *chained = 1;
  932. sg = scatterwalk_sg_next(sg);
  933. }
  934. return sg_nents;
  935. }
  936. /*
  937. * allocate and map the extended descriptor
  938. */
  939. static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
  940. struct scatterlist *src,
  941. struct scatterlist *dst,
  942. unsigned int cryptlen,
  943. unsigned int authsize,
  944. int icv_stashing,
  945. u32 cryptoflags)
  946. {
  947. struct talitos_edesc *edesc;
  948. int src_nents, dst_nents, alloc_len, dma_len;
  949. int src_chained, dst_chained = 0;
  950. gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
  951. GFP_ATOMIC;
  952. if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
  953. dev_err(dev, "length exceeds h/w max limit\n");
  954. return ERR_PTR(-EINVAL);
  955. }
  956. src_nents = sg_count(src, cryptlen + authsize, &src_chained);
  957. src_nents = (src_nents == 1) ? 0 : src_nents;
  958. if (dst == src) {
  959. dst_nents = src_nents;
  960. } else {
  961. dst_nents = sg_count(dst, cryptlen + authsize, &dst_chained);
  962. dst_nents = (dst_nents == 1) ? 0 : dst_nents;
  963. }
  964. /*
  965. * allocate space for base edesc plus the link tables,
  966. * allowing for two separate entries for ICV and generated ICV (+ 2),
  967. * and the ICV data itself
  968. */
  969. alloc_len = sizeof(struct talitos_edesc);
  970. if (src_nents || dst_nents) {
  971. dma_len = (src_nents + dst_nents + 2) *
  972. sizeof(struct talitos_ptr) + authsize;
  973. alloc_len += dma_len;
  974. } else {
  975. dma_len = 0;
  976. alloc_len += icv_stashing ? authsize : 0;
  977. }
  978. edesc = kmalloc(alloc_len, GFP_DMA | flags);
  979. if (!edesc) {
  980. dev_err(dev, "could not allocate edescriptor\n");
  981. return ERR_PTR(-ENOMEM);
  982. }
  983. edesc->src_nents = src_nents;
  984. edesc->dst_nents = dst_nents;
  985. edesc->src_is_chained = src_chained;
  986. edesc->dst_is_chained = dst_chained;
  987. edesc->dma_len = dma_len;
  988. edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
  989. edesc->dma_len, DMA_BIDIRECTIONAL);
  990. return edesc;
  991. }
  992. static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
  993. int icv_stashing)
  994. {
  995. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  996. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  997. return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
  998. areq->cryptlen, ctx->authsize, icv_stashing,
  999. areq->base.flags);
  1000. }
  1001. static int aead_encrypt(struct aead_request *req)
  1002. {
  1003. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  1004. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1005. struct talitos_edesc *edesc;
  1006. /* allocate extended descriptor */
  1007. edesc = aead_edesc_alloc(req, 0);
  1008. if (IS_ERR(edesc))
  1009. return PTR_ERR(edesc);
  1010. /* set encrypt */
  1011. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1012. return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
  1013. }
  1014. static int aead_decrypt(struct aead_request *req)
  1015. {
  1016. struct crypto_aead *authenc = crypto_aead_reqtfm(req);
  1017. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1018. unsigned int authsize = ctx->authsize;
  1019. struct talitos_private *priv = dev_get_drvdata(ctx->dev);
  1020. struct talitos_edesc *edesc;
  1021. struct scatterlist *sg;
  1022. void *icvdata;
  1023. req->cryptlen -= authsize;
  1024. /* allocate extended descriptor */
  1025. edesc = aead_edesc_alloc(req, 1);
  1026. if (IS_ERR(edesc))
  1027. return PTR_ERR(edesc);
  1028. if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
  1029. ((!edesc->src_nents && !edesc->dst_nents) ||
  1030. priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
  1031. /* decrypt and check the ICV */
  1032. edesc->desc.hdr = ctx->desc_hdr_template |
  1033. DESC_HDR_DIR_INBOUND |
  1034. DESC_HDR_MODE1_MDEU_CICV;
  1035. /* reset integrity check result bits */
  1036. edesc->desc.hdr_lo = 0;
  1037. return ipsec_esp(edesc, req, NULL, 0,
  1038. ipsec_esp_decrypt_hwauth_done);
  1039. }
  1040. /* Have to check the ICV with software */
  1041. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
  1042. /* stash incoming ICV for later cmp with ICV generated by the h/w */
  1043. if (edesc->dma_len)
  1044. icvdata = &edesc->link_tbl[edesc->src_nents +
  1045. edesc->dst_nents + 2];
  1046. else
  1047. icvdata = &edesc->link_tbl[0];
  1048. sg = sg_last(req->src, edesc->src_nents ? : 1);
  1049. memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
  1050. ctx->authsize);
  1051. return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
  1052. }
  1053. static int aead_givencrypt(struct aead_givcrypt_request *req)
  1054. {
  1055. struct aead_request *areq = &req->areq;
  1056. struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
  1057. struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
  1058. struct talitos_edesc *edesc;
  1059. /* allocate extended descriptor */
  1060. edesc = aead_edesc_alloc(areq, 0);
  1061. if (IS_ERR(edesc))
  1062. return PTR_ERR(edesc);
  1063. /* set encrypt */
  1064. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1065. memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
  1066. /* avoid consecutive packets going out with same IV */
  1067. *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
  1068. return ipsec_esp(edesc, areq, req->giv, req->seq,
  1069. ipsec_esp_encrypt_done);
  1070. }
  1071. static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
  1072. const u8 *key, unsigned int keylen)
  1073. {
  1074. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1075. struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
  1076. if (keylen > TALITOS_MAX_KEY_SIZE)
  1077. goto badkey;
  1078. if (keylen < alg->min_keysize || keylen > alg->max_keysize)
  1079. goto badkey;
  1080. memcpy(&ctx->key, key, keylen);
  1081. ctx->keylen = keylen;
  1082. return 0;
  1083. badkey:
  1084. crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
  1085. return -EINVAL;
  1086. }
  1087. static void common_nonsnoop_unmap(struct device *dev,
  1088. struct talitos_edesc *edesc,
  1089. struct ablkcipher_request *areq)
  1090. {
  1091. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
  1092. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
  1093. unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
  1094. talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
  1095. if (edesc->dma_len)
  1096. dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
  1097. DMA_BIDIRECTIONAL);
  1098. }
  1099. static void ablkcipher_done(struct device *dev,
  1100. struct talitos_desc *desc, void *context,
  1101. int err)
  1102. {
  1103. struct ablkcipher_request *areq = context;
  1104. struct talitos_edesc *edesc;
  1105. edesc = container_of(desc, struct talitos_edesc, desc);
  1106. common_nonsnoop_unmap(dev, edesc, areq);
  1107. kfree(edesc);
  1108. areq->base.complete(&areq->base, err);
  1109. }
  1110. static int common_nonsnoop(struct talitos_edesc *edesc,
  1111. struct ablkcipher_request *areq,
  1112. u8 *giv,
  1113. void (*callback) (struct device *dev,
  1114. struct talitos_desc *desc,
  1115. void *context, int error))
  1116. {
  1117. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1118. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1119. struct device *dev = ctx->dev;
  1120. struct talitos_desc *desc = &edesc->desc;
  1121. unsigned int cryptlen = areq->nbytes;
  1122. unsigned int ivsize;
  1123. int sg_count, ret;
  1124. /* first DWORD empty */
  1125. desc->ptr[0].len = 0;
  1126. to_talitos_ptr(&desc->ptr[0], 0);
  1127. desc->ptr[0].j_extent = 0;
  1128. /* cipher iv */
  1129. ivsize = crypto_ablkcipher_ivsize(cipher);
  1130. map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
  1131. DMA_TO_DEVICE);
  1132. /* cipher key */
  1133. map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
  1134. (char *)&ctx->key, 0, DMA_TO_DEVICE);
  1135. /*
  1136. * cipher in
  1137. */
  1138. desc->ptr[3].len = cpu_to_be16(cryptlen);
  1139. desc->ptr[3].j_extent = 0;
  1140. sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
  1141. (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
  1142. : DMA_TO_DEVICE,
  1143. edesc->src_is_chained);
  1144. if (sg_count == 1) {
  1145. to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
  1146. } else {
  1147. sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
  1148. &edesc->link_tbl[0]);
  1149. if (sg_count > 1) {
  1150. to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
  1151. desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
  1152. dma_sync_single_for_device(dev, edesc->dma_link_tbl,
  1153. edesc->dma_len,
  1154. DMA_BIDIRECTIONAL);
  1155. } else {
  1156. /* Only one segment now, so no link tbl needed */
  1157. to_talitos_ptr(&desc->ptr[3],
  1158. sg_dma_address(areq->src));
  1159. }
  1160. }
  1161. /* cipher out */
  1162. desc->ptr[4].len = cpu_to_be16(cryptlen);
  1163. desc->ptr[4].j_extent = 0;
  1164. if (areq->src != areq->dst)
  1165. sg_count = talitos_map_sg(dev, areq->dst,
  1166. edesc->dst_nents ? : 1,
  1167. DMA_FROM_DEVICE,
  1168. edesc->dst_is_chained);
  1169. if (sg_count == 1) {
  1170. to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
  1171. } else {
  1172. struct talitos_ptr *link_tbl_ptr =
  1173. &edesc->link_tbl[edesc->src_nents + 1];
  1174. to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
  1175. (edesc->src_nents + 1) *
  1176. sizeof(struct talitos_ptr));
  1177. desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
  1178. sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
  1179. link_tbl_ptr);
  1180. dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
  1181. edesc->dma_len, DMA_BIDIRECTIONAL);
  1182. }
  1183. /* iv out */
  1184. map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
  1185. DMA_FROM_DEVICE);
  1186. /* last DWORD empty */
  1187. desc->ptr[6].len = 0;
  1188. to_talitos_ptr(&desc->ptr[6], 0);
  1189. desc->ptr[6].j_extent = 0;
  1190. ret = talitos_submit(dev, desc, callback, areq);
  1191. if (ret != -EINPROGRESS) {
  1192. common_nonsnoop_unmap(dev, edesc, areq);
  1193. kfree(edesc);
  1194. }
  1195. return ret;
  1196. }
  1197. static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
  1198. areq)
  1199. {
  1200. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1201. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1202. return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, areq->nbytes,
  1203. 0, 0, areq->base.flags);
  1204. }
  1205. static int ablkcipher_encrypt(struct ablkcipher_request *areq)
  1206. {
  1207. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1208. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1209. struct talitos_edesc *edesc;
  1210. /* allocate extended descriptor */
  1211. edesc = ablkcipher_edesc_alloc(areq);
  1212. if (IS_ERR(edesc))
  1213. return PTR_ERR(edesc);
  1214. /* set encrypt */
  1215. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
  1216. return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
  1217. }
  1218. static int ablkcipher_decrypt(struct ablkcipher_request *areq)
  1219. {
  1220. struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
  1221. struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
  1222. struct talitos_edesc *edesc;
  1223. /* allocate extended descriptor */
  1224. edesc = ablkcipher_edesc_alloc(areq);
  1225. if (IS_ERR(edesc))
  1226. return PTR_ERR(edesc);
  1227. edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
  1228. return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
  1229. }
  1230. struct talitos_alg_template {
  1231. struct crypto_alg alg;
  1232. __be32 desc_hdr_template;
  1233. };
  1234. static struct talitos_alg_template driver_algs[] = {
  1235. /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
  1236. {
  1237. .alg = {
  1238. .cra_name = "authenc(hmac(sha1),cbc(aes))",
  1239. .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
  1240. .cra_blocksize = AES_BLOCK_SIZE,
  1241. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1242. .cra_type = &crypto_aead_type,
  1243. .cra_aead = {
  1244. .setkey = aead_setkey,
  1245. .setauthsize = aead_setauthsize,
  1246. .encrypt = aead_encrypt,
  1247. .decrypt = aead_decrypt,
  1248. .givencrypt = aead_givencrypt,
  1249. .geniv = "<built-in>",
  1250. .ivsize = AES_BLOCK_SIZE,
  1251. .maxauthsize = SHA1_DIGEST_SIZE,
  1252. }
  1253. },
  1254. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1255. DESC_HDR_SEL0_AESU |
  1256. DESC_HDR_MODE0_AESU_CBC |
  1257. DESC_HDR_SEL1_MDEUA |
  1258. DESC_HDR_MODE1_MDEU_INIT |
  1259. DESC_HDR_MODE1_MDEU_PAD |
  1260. DESC_HDR_MODE1_MDEU_SHA1_HMAC,
  1261. },
  1262. {
  1263. .alg = {
  1264. .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
  1265. .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
  1266. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1267. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1268. .cra_type = &crypto_aead_type,
  1269. .cra_aead = {
  1270. .setkey = aead_setkey,
  1271. .setauthsize = aead_setauthsize,
  1272. .encrypt = aead_encrypt,
  1273. .decrypt = aead_decrypt,
  1274. .givencrypt = aead_givencrypt,
  1275. .geniv = "<built-in>",
  1276. .ivsize = DES3_EDE_BLOCK_SIZE,
  1277. .maxauthsize = SHA1_DIGEST_SIZE,
  1278. }
  1279. },
  1280. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1281. DESC_HDR_SEL0_DEU |
  1282. DESC_HDR_MODE0_DEU_CBC |
  1283. DESC_HDR_MODE0_DEU_3DES |
  1284. DESC_HDR_SEL1_MDEUA |
  1285. DESC_HDR_MODE1_MDEU_INIT |
  1286. DESC_HDR_MODE1_MDEU_PAD |
  1287. DESC_HDR_MODE1_MDEU_SHA1_HMAC,
  1288. },
  1289. {
  1290. .alg = {
  1291. .cra_name = "authenc(hmac(sha256),cbc(aes))",
  1292. .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
  1293. .cra_blocksize = AES_BLOCK_SIZE,
  1294. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1295. .cra_type = &crypto_aead_type,
  1296. .cra_aead = {
  1297. .setkey = aead_setkey,
  1298. .setauthsize = aead_setauthsize,
  1299. .encrypt = aead_encrypt,
  1300. .decrypt = aead_decrypt,
  1301. .givencrypt = aead_givencrypt,
  1302. .geniv = "<built-in>",
  1303. .ivsize = AES_BLOCK_SIZE,
  1304. .maxauthsize = SHA256_DIGEST_SIZE,
  1305. }
  1306. },
  1307. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1308. DESC_HDR_SEL0_AESU |
  1309. DESC_HDR_MODE0_AESU_CBC |
  1310. DESC_HDR_SEL1_MDEUA |
  1311. DESC_HDR_MODE1_MDEU_INIT |
  1312. DESC_HDR_MODE1_MDEU_PAD |
  1313. DESC_HDR_MODE1_MDEU_SHA256_HMAC,
  1314. },
  1315. {
  1316. .alg = {
  1317. .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
  1318. .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
  1319. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1320. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1321. .cra_type = &crypto_aead_type,
  1322. .cra_aead = {
  1323. .setkey = aead_setkey,
  1324. .setauthsize = aead_setauthsize,
  1325. .encrypt = aead_encrypt,
  1326. .decrypt = aead_decrypt,
  1327. .givencrypt = aead_givencrypt,
  1328. .geniv = "<built-in>",
  1329. .ivsize = DES3_EDE_BLOCK_SIZE,
  1330. .maxauthsize = SHA256_DIGEST_SIZE,
  1331. }
  1332. },
  1333. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1334. DESC_HDR_SEL0_DEU |
  1335. DESC_HDR_MODE0_DEU_CBC |
  1336. DESC_HDR_MODE0_DEU_3DES |
  1337. DESC_HDR_SEL1_MDEUA |
  1338. DESC_HDR_MODE1_MDEU_INIT |
  1339. DESC_HDR_MODE1_MDEU_PAD |
  1340. DESC_HDR_MODE1_MDEU_SHA256_HMAC,
  1341. },
  1342. {
  1343. .alg = {
  1344. .cra_name = "authenc(hmac(md5),cbc(aes))",
  1345. .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
  1346. .cra_blocksize = AES_BLOCK_SIZE,
  1347. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1348. .cra_type = &crypto_aead_type,
  1349. .cra_aead = {
  1350. .setkey = aead_setkey,
  1351. .setauthsize = aead_setauthsize,
  1352. .encrypt = aead_encrypt,
  1353. .decrypt = aead_decrypt,
  1354. .givencrypt = aead_givencrypt,
  1355. .geniv = "<built-in>",
  1356. .ivsize = AES_BLOCK_SIZE,
  1357. .maxauthsize = MD5_DIGEST_SIZE,
  1358. }
  1359. },
  1360. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1361. DESC_HDR_SEL0_AESU |
  1362. DESC_HDR_MODE0_AESU_CBC |
  1363. DESC_HDR_SEL1_MDEUA |
  1364. DESC_HDR_MODE1_MDEU_INIT |
  1365. DESC_HDR_MODE1_MDEU_PAD |
  1366. DESC_HDR_MODE1_MDEU_MD5_HMAC,
  1367. },
  1368. {
  1369. .alg = {
  1370. .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
  1371. .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
  1372. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1373. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1374. .cra_type = &crypto_aead_type,
  1375. .cra_aead = {
  1376. .setkey = aead_setkey,
  1377. .setauthsize = aead_setauthsize,
  1378. .encrypt = aead_encrypt,
  1379. .decrypt = aead_decrypt,
  1380. .givencrypt = aead_givencrypt,
  1381. .geniv = "<built-in>",
  1382. .ivsize = DES3_EDE_BLOCK_SIZE,
  1383. .maxauthsize = MD5_DIGEST_SIZE,
  1384. }
  1385. },
  1386. .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
  1387. DESC_HDR_SEL0_DEU |
  1388. DESC_HDR_MODE0_DEU_CBC |
  1389. DESC_HDR_MODE0_DEU_3DES |
  1390. DESC_HDR_SEL1_MDEUA |
  1391. DESC_HDR_MODE1_MDEU_INIT |
  1392. DESC_HDR_MODE1_MDEU_PAD |
  1393. DESC_HDR_MODE1_MDEU_MD5_HMAC,
  1394. },
  1395. /* ABLKCIPHER algorithms. */
  1396. {
  1397. .alg = {
  1398. .cra_name = "cbc(aes)",
  1399. .cra_driver_name = "cbc-aes-talitos",
  1400. .cra_blocksize = AES_BLOCK_SIZE,
  1401. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1402. CRYPTO_ALG_ASYNC,
  1403. .cra_type = &crypto_ablkcipher_type,
  1404. .cra_ablkcipher = {
  1405. .setkey = ablkcipher_setkey,
  1406. .encrypt = ablkcipher_encrypt,
  1407. .decrypt = ablkcipher_decrypt,
  1408. .geniv = "eseqiv",
  1409. .min_keysize = AES_MIN_KEY_SIZE,
  1410. .max_keysize = AES_MAX_KEY_SIZE,
  1411. .ivsize = AES_BLOCK_SIZE,
  1412. }
  1413. },
  1414. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1415. DESC_HDR_SEL0_AESU |
  1416. DESC_HDR_MODE0_AESU_CBC,
  1417. },
  1418. {
  1419. .alg = {
  1420. .cra_name = "cbc(des3_ede)",
  1421. .cra_driver_name = "cbc-3des-talitos",
  1422. .cra_blocksize = DES3_EDE_BLOCK_SIZE,
  1423. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
  1424. CRYPTO_ALG_ASYNC,
  1425. .cra_type = &crypto_ablkcipher_type,
  1426. .cra_ablkcipher = {
  1427. .setkey = ablkcipher_setkey,
  1428. .encrypt = ablkcipher_encrypt,
  1429. .decrypt = ablkcipher_decrypt,
  1430. .geniv = "eseqiv",
  1431. .min_keysize = DES3_EDE_KEY_SIZE,
  1432. .max_keysize = DES3_EDE_KEY_SIZE,
  1433. .ivsize = DES3_EDE_BLOCK_SIZE,
  1434. }
  1435. },
  1436. .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
  1437. DESC_HDR_SEL0_DEU |
  1438. DESC_HDR_MODE0_DEU_CBC |
  1439. DESC_HDR_MODE0_DEU_3DES,
  1440. }
  1441. };
  1442. struct talitos_crypto_alg {
  1443. struct list_head entry;
  1444. struct device *dev;
  1445. __be32 desc_hdr_template;
  1446. struct crypto_alg crypto_alg;
  1447. };
  1448. static int talitos_cra_init(struct crypto_tfm *tfm)
  1449. {
  1450. struct crypto_alg *alg = tfm->__crt_alg;
  1451. struct talitos_crypto_alg *talitos_alg;
  1452. struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
  1453. talitos_alg = container_of(alg, struct talitos_crypto_alg, crypto_alg);
  1454. /* update context with ptr to dev */
  1455. ctx->dev = talitos_alg->dev;
  1456. /* copy descriptor header template value */
  1457. ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
  1458. /* random first IV */
  1459. get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
  1460. return 0;
  1461. }
  1462. /*
  1463. * given the alg's descriptor header template, determine whether descriptor
  1464. * type and primary/secondary execution units required match the hw
  1465. * capabilities description provided in the device tree node.
  1466. */
  1467. static int hw_supports(struct device *dev, __be32 desc_hdr_template)
  1468. {
  1469. struct talitos_private *priv = dev_get_drvdata(dev);
  1470. int ret;
  1471. ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
  1472. (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
  1473. if (SECONDARY_EU(desc_hdr_template))
  1474. ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
  1475. & priv->exec_units);
  1476. return ret;
  1477. }
  1478. static int talitos_remove(struct of_device *ofdev)
  1479. {
  1480. struct device *dev = &ofdev->dev;
  1481. struct talitos_private *priv = dev_get_drvdata(dev);
  1482. struct talitos_crypto_alg *t_alg, *n;
  1483. int i;
  1484. list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
  1485. crypto_unregister_alg(&t_alg->crypto_alg);
  1486. list_del(&t_alg->entry);
  1487. kfree(t_alg);
  1488. }
  1489. if (hw_supports(dev, DESC_HDR_SEL0_RNG))
  1490. talitos_unregister_rng(dev);
  1491. for (i = 0; i < priv->num_channels; i++)
  1492. if (priv->chan[i].fifo)
  1493. kfree(priv->chan[i].fifo);
  1494. kfree(priv->chan);
  1495. if (priv->irq != NO_IRQ) {
  1496. free_irq(priv->irq, dev);
  1497. irq_dispose_mapping(priv->irq);
  1498. }
  1499. tasklet_kill(&priv->done_task);
  1500. iounmap(priv->reg);
  1501. dev_set_drvdata(dev, NULL);
  1502. kfree(priv);
  1503. return 0;
  1504. }
  1505. static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
  1506. struct talitos_alg_template
  1507. *template)
  1508. {
  1509. struct talitos_crypto_alg *t_alg;
  1510. struct crypto_alg *alg;
  1511. t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
  1512. if (!t_alg)
  1513. return ERR_PTR(-ENOMEM);
  1514. alg = &t_alg->crypto_alg;
  1515. *alg = template->alg;
  1516. alg->cra_module = THIS_MODULE;
  1517. alg->cra_init = talitos_cra_init;
  1518. alg->cra_priority = TALITOS_CRA_PRIORITY;
  1519. alg->cra_alignmask = 0;
  1520. alg->cra_ctxsize = sizeof(struct talitos_ctx);
  1521. t_alg->desc_hdr_template = template->desc_hdr_template;
  1522. t_alg->dev = dev;
  1523. return t_alg;
  1524. }
  1525. static int talitos_probe(struct of_device *ofdev,
  1526. const struct of_device_id *match)
  1527. {
  1528. struct device *dev = &ofdev->dev;
  1529. struct device_node *np = ofdev->node;
  1530. struct talitos_private *priv;
  1531. const unsigned int *prop;
  1532. int i, err;
  1533. priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
  1534. if (!priv)
  1535. return -ENOMEM;
  1536. dev_set_drvdata(dev, priv);
  1537. priv->ofdev = ofdev;
  1538. tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
  1539. INIT_LIST_HEAD(&priv->alg_list);
  1540. priv->irq = irq_of_parse_and_map(np, 0);
  1541. if (priv->irq == NO_IRQ) {
  1542. dev_err(dev, "failed to map irq\n");
  1543. err = -EINVAL;
  1544. goto err_out;
  1545. }
  1546. /* get the irq line */
  1547. err = request_irq(priv->irq, talitos_interrupt, 0,
  1548. dev_driver_string(dev), dev);
  1549. if (err) {
  1550. dev_err(dev, "failed to request irq %d\n", priv->irq);
  1551. irq_dispose_mapping(priv->irq);
  1552. priv->irq = NO_IRQ;
  1553. goto err_out;
  1554. }
  1555. priv->reg = of_iomap(np, 0);
  1556. if (!priv->reg) {
  1557. dev_err(dev, "failed to of_iomap\n");
  1558. err = -ENOMEM;
  1559. goto err_out;
  1560. }
  1561. /* get SEC version capabilities from device tree */
  1562. prop = of_get_property(np, "fsl,num-channels", NULL);
  1563. if (prop)
  1564. priv->num_channels = *prop;
  1565. prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
  1566. if (prop)
  1567. priv->chfifo_len = *prop;
  1568. prop = of_get_property(np, "fsl,exec-units-mask", NULL);
  1569. if (prop)
  1570. priv->exec_units = *prop;
  1571. prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
  1572. if (prop)
  1573. priv->desc_types = *prop;
  1574. if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
  1575. !priv->exec_units || !priv->desc_types) {
  1576. dev_err(dev, "invalid property data in device tree node\n");
  1577. err = -EINVAL;
  1578. goto err_out;
  1579. }
  1580. if (of_device_is_compatible(np, "fsl,sec3.0"))
  1581. priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
  1582. if (of_device_is_compatible(np, "fsl,sec2.1"))
  1583. priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
  1584. priv->chan = kzalloc(sizeof(struct talitos_channel) *
  1585. priv->num_channels, GFP_KERNEL);
  1586. if (!priv->chan) {
  1587. dev_err(dev, "failed to allocate channel management space\n");
  1588. err = -ENOMEM;
  1589. goto err_out;
  1590. }
  1591. for (i = 0; i < priv->num_channels; i++) {
  1592. spin_lock_init(&priv->chan[i].head_lock);
  1593. spin_lock_init(&priv->chan[i].tail_lock);
  1594. }
  1595. priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
  1596. for (i = 0; i < priv->num_channels; i++) {
  1597. priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
  1598. priv->fifo_len, GFP_KERNEL);
  1599. if (!priv->chan[i].fifo) {
  1600. dev_err(dev, "failed to allocate request fifo %d\n", i);
  1601. err = -ENOMEM;
  1602. goto err_out;
  1603. }
  1604. }
  1605. for (i = 0; i < priv->num_channels; i++)
  1606. atomic_set(&priv->chan[i].submit_count,
  1607. -(priv->chfifo_len - 1));
  1608. dma_set_mask(dev, DMA_BIT_MASK(36));
  1609. /* reset and initialize the h/w */
  1610. err = init_device(dev);
  1611. if (err) {
  1612. dev_err(dev, "failed to initialize device\n");
  1613. goto err_out;
  1614. }
  1615. /* register the RNG, if available */
  1616. if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
  1617. err = talitos_register_rng(dev);
  1618. if (err) {
  1619. dev_err(dev, "failed to register hwrng: %d\n", err);
  1620. goto err_out;
  1621. } else
  1622. dev_info(dev, "hwrng\n");
  1623. }
  1624. /* register crypto algorithms the device supports */
  1625. for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
  1626. if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
  1627. struct talitos_crypto_alg *t_alg;
  1628. t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
  1629. if (IS_ERR(t_alg)) {
  1630. err = PTR_ERR(t_alg);
  1631. goto err_out;
  1632. }
  1633. err = crypto_register_alg(&t_alg->crypto_alg);
  1634. if (err) {
  1635. dev_err(dev, "%s alg registration failed\n",
  1636. t_alg->crypto_alg.cra_driver_name);
  1637. kfree(t_alg);
  1638. } else {
  1639. list_add_tail(&t_alg->entry, &priv->alg_list);
  1640. dev_info(dev, "%s\n",
  1641. t_alg->crypto_alg.cra_driver_name);
  1642. }
  1643. }
  1644. }
  1645. return 0;
  1646. err_out:
  1647. talitos_remove(ofdev);
  1648. return err;
  1649. }
  1650. static const struct of_device_id talitos_match[] = {
  1651. {
  1652. .compatible = "fsl,sec2.0",
  1653. },
  1654. {},
  1655. };
  1656. MODULE_DEVICE_TABLE(of, talitos_match);
  1657. static struct of_platform_driver talitos_driver = {
  1658. .name = "talitos",
  1659. .match_table = talitos_match,
  1660. .probe = talitos_probe,
  1661. .remove = talitos_remove,
  1662. };
  1663. static int __init talitos_init(void)
  1664. {
  1665. return of_register_platform_driver(&talitos_driver);
  1666. }
  1667. module_init(talitos_init);
  1668. static void __exit talitos_exit(void)
  1669. {
  1670. of_unregister_platform_driver(&talitos_driver);
  1671. }
  1672. module_exit(talitos_exit);
  1673. MODULE_LICENSE("GPL");
  1674. MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
  1675. MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");