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/drivers/media/dvb/frontends/stv0900_sw.c

https://bitbucket.org/abioy/linux
C | 2034 lines | 1664 code | 345 blank | 25 comment | 399 complexity | 0e65f5170ca98714a441cc5d797a7987 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * stv0900_sw.c
  3. *
  4. * Driver for ST STV0900 satellite demodulator IC.
  5. *
  6. * Copyright (C) ST Microelectronics.
  7. * Copyright (C) 2009 NetUP Inc.
  8. * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. *
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include "stv0900.h"
  26. #include "stv0900_reg.h"
  27. #include "stv0900_priv.h"
  28. s32 shiftx(s32 x, int demod, s32 shift)
  29. {
  30. if (demod == 1)
  31. return x - shift;
  32. return x;
  33. }
  34. int stv0900_check_signal_presence(struct stv0900_internal *intp,
  35. enum fe_stv0900_demod_num demod)
  36. {
  37. s32 carr_offset,
  38. agc2_integr,
  39. max_carrier;
  40. int no_signal = FALSE;
  41. carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
  42. | stv0900_read_reg(intp, CFR1);
  43. carr_offset = ge2comp(carr_offset, 16);
  44. agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
  45. | stv0900_read_reg(intp, AGC2I0);
  46. max_carrier = intp->srch_range[demod] / 1000;
  47. max_carrier += (max_carrier / 10);
  48. max_carrier = 65536 * (max_carrier / 2);
  49. max_carrier /= intp->mclk / 1000;
  50. if (max_carrier > 0x4000)
  51. max_carrier = 0x4000;
  52. if ((agc2_integr > 0x2000)
  53. || (carr_offset > (2 * max_carrier))
  54. || (carr_offset < (-2 * max_carrier)))
  55. no_signal = TRUE;
  56. return no_signal;
  57. }
  58. static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
  59. s32 *frequency_inc, s32 *sw_timeout,
  60. s32 *steps,
  61. enum fe_stv0900_demod_num demod)
  62. {
  63. s32 timeout, freq_inc, max_steps, srate, max_carrier;
  64. enum fe_stv0900_search_standard standard;
  65. srate = intp->symbol_rate[demod];
  66. max_carrier = intp->srch_range[demod] / 1000;
  67. max_carrier += max_carrier / 10;
  68. standard = intp->srch_standard[demod];
  69. max_carrier = 65536 * (max_carrier / 2);
  70. max_carrier /= intp->mclk / 1000;
  71. if (max_carrier > 0x4000)
  72. max_carrier = 0x4000;
  73. freq_inc = srate;
  74. freq_inc /= intp->mclk >> 10;
  75. freq_inc = freq_inc << 6;
  76. switch (standard) {
  77. case STV0900_SEARCH_DVBS1:
  78. case STV0900_SEARCH_DSS:
  79. freq_inc *= 3;
  80. timeout = 20;
  81. break;
  82. case STV0900_SEARCH_DVBS2:
  83. freq_inc *= 4;
  84. timeout = 25;
  85. break;
  86. case STV0900_AUTO_SEARCH:
  87. default:
  88. freq_inc *= 3;
  89. timeout = 25;
  90. break;
  91. }
  92. freq_inc /= 100;
  93. if ((freq_inc > max_carrier) || (freq_inc < 0))
  94. freq_inc = max_carrier / 2;
  95. timeout *= 27500;
  96. if (srate > 0)
  97. timeout /= srate / 1000;
  98. if ((timeout > 100) || (timeout < 0))
  99. timeout = 100;
  100. max_steps = (max_carrier / freq_inc) + 1;
  101. if ((max_steps > 100) || (max_steps < 0)) {
  102. max_steps = 100;
  103. freq_inc = max_carrier / max_steps;
  104. }
  105. *frequency_inc = freq_inc;
  106. *sw_timeout = timeout;
  107. *steps = max_steps;
  108. }
  109. static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
  110. s32 FreqIncr, s32 Timeout, int zigzag,
  111. s32 MaxStep, enum fe_stv0900_demod_num demod)
  112. {
  113. int no_signal,
  114. lock = FALSE;
  115. s32 stepCpt,
  116. freqOffset,
  117. max_carrier;
  118. max_carrier = intp->srch_range[demod] / 1000;
  119. max_carrier += (max_carrier / 10);
  120. max_carrier = 65536 * (max_carrier / 2);
  121. max_carrier /= intp->mclk / 1000;
  122. if (max_carrier > 0x4000)
  123. max_carrier = 0x4000;
  124. if (zigzag == TRUE)
  125. freqOffset = 0;
  126. else
  127. freqOffset = -max_carrier + FreqIncr;
  128. stepCpt = 0;
  129. do {
  130. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  131. stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
  132. stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
  133. stv0900_write_reg(intp, DMDISTATE, 0x18);
  134. stv0900_write_bits(intp, ALGOSWRST, 1);
  135. if (intp->chip_id == 0x12) {
  136. stv0900_write_bits(intp, RST_HWARE, 1);
  137. stv0900_write_bits(intp, RST_HWARE, 0);
  138. }
  139. if (zigzag == TRUE) {
  140. if (freqOffset >= 0)
  141. freqOffset = -freqOffset - 2 * FreqIncr;
  142. else
  143. freqOffset = -freqOffset;
  144. } else
  145. freqOffset += + 2 * FreqIncr;
  146. stepCpt++;
  147. lock = stv0900_get_demod_lock(intp, demod, Timeout);
  148. no_signal = stv0900_check_signal_presence(intp, demod);
  149. } while ((lock == FALSE)
  150. && (no_signal == FALSE)
  151. && ((freqOffset - FreqIncr) < max_carrier)
  152. && ((freqOffset + FreqIncr) > -max_carrier)
  153. && (stepCpt < MaxStep));
  154. stv0900_write_bits(intp, ALGOSWRST, 0);
  155. return lock;
  156. }
  157. static int stv0900_sw_algo(struct stv0900_internal *intp,
  158. enum fe_stv0900_demod_num demod)
  159. {
  160. int lock = FALSE,
  161. no_signal,
  162. zigzag;
  163. s32 s2fw,
  164. fqc_inc,
  165. sft_stp_tout,
  166. trial_cntr,
  167. max_steps;
  168. stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
  169. &max_steps, demod);
  170. switch (intp->srch_standard[demod]) {
  171. case STV0900_SEARCH_DVBS1:
  172. case STV0900_SEARCH_DSS:
  173. if (intp->chip_id >= 0x20)
  174. stv0900_write_reg(intp, CARFREQ, 0x3b);
  175. else
  176. stv0900_write_reg(intp, CARFREQ, 0xef);
  177. stv0900_write_reg(intp, DMDCFGMD, 0x49);
  178. zigzag = FALSE;
  179. break;
  180. case STV0900_SEARCH_DVBS2:
  181. if (intp->chip_id >= 0x20)
  182. stv0900_write_reg(intp, CORRELABS, 0x79);
  183. else
  184. stv0900_write_reg(intp, CORRELABS, 0x68);
  185. stv0900_write_reg(intp, DMDCFGMD, 0x89);
  186. zigzag = TRUE;
  187. break;
  188. case STV0900_AUTO_SEARCH:
  189. default:
  190. if (intp->chip_id >= 0x20) {
  191. stv0900_write_reg(intp, CARFREQ, 0x3b);
  192. stv0900_write_reg(intp, CORRELABS, 0x79);
  193. } else {
  194. stv0900_write_reg(intp, CARFREQ, 0xef);
  195. stv0900_write_reg(intp, CORRELABS, 0x68);
  196. }
  197. stv0900_write_reg(intp, DMDCFGMD, 0xc9);
  198. zigzag = FALSE;
  199. break;
  200. }
  201. trial_cntr = 0;
  202. do {
  203. lock = stv0900_search_carr_sw_loop(intp,
  204. fqc_inc,
  205. sft_stp_tout,
  206. zigzag,
  207. max_steps,
  208. demod);
  209. no_signal = stv0900_check_signal_presence(intp, demod);
  210. trial_cntr++;
  211. if ((lock == TRUE)
  212. || (no_signal == TRUE)
  213. || (trial_cntr == 2)) {
  214. if (intp->chip_id >= 0x20) {
  215. stv0900_write_reg(intp, CARFREQ, 0x49);
  216. stv0900_write_reg(intp, CORRELABS, 0x9e);
  217. } else {
  218. stv0900_write_reg(intp, CARFREQ, 0xed);
  219. stv0900_write_reg(intp, CORRELABS, 0x88);
  220. }
  221. if ((stv0900_get_bits(intp, HEADER_MODE) ==
  222. STV0900_DVBS2_FOUND) &&
  223. (lock == TRUE)) {
  224. msleep(sft_stp_tout);
  225. s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
  226. if (s2fw < 0xd) {
  227. msleep(sft_stp_tout);
  228. s2fw = stv0900_get_bits(intp,
  229. FLYWHEEL_CPT);
  230. }
  231. if (s2fw < 0xd) {
  232. lock = FALSE;
  233. if (trial_cntr < 2) {
  234. if (intp->chip_id >= 0x20)
  235. stv0900_write_reg(intp,
  236. CORRELABS,
  237. 0x79);
  238. else
  239. stv0900_write_reg(intp,
  240. CORRELABS,
  241. 0x68);
  242. stv0900_write_reg(intp,
  243. DMDCFGMD,
  244. 0x89);
  245. }
  246. }
  247. }
  248. }
  249. } while ((lock == FALSE)
  250. && (trial_cntr < 2)
  251. && (no_signal == FALSE));
  252. return lock;
  253. }
  254. static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
  255. u32 mclk,
  256. enum fe_stv0900_demod_num demod)
  257. {
  258. s32 rem1, rem2, intval1, intval2, srate;
  259. srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
  260. (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
  261. (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
  262. (stv0900_get_bits(intp, SYMB_FREQ0));
  263. dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
  264. srate, stv0900_get_bits(intp, SYMB_FREQ0),
  265. stv0900_get_bits(intp, SYMB_FREQ1),
  266. stv0900_get_bits(intp, SYMB_FREQ2),
  267. stv0900_get_bits(intp, SYMB_FREQ3));
  268. intval1 = (mclk) >> 16;
  269. intval2 = (srate) >> 16;
  270. rem1 = (mclk) % 0x10000;
  271. rem2 = (srate) % 0x10000;
  272. srate = (intval1 * intval2) +
  273. ((intval1 * rem2) >> 16) +
  274. ((intval2 * rem1) >> 16);
  275. return srate;
  276. }
  277. static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
  278. u32 mclk, u32 srate,
  279. enum fe_stv0900_demod_num demod)
  280. {
  281. u32 symb;
  282. dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
  283. srate, demod);
  284. if (srate > 60000000) {
  285. symb = srate << 4;
  286. symb /= (mclk >> 12);
  287. } else if (srate > 6000000) {
  288. symb = srate << 6;
  289. symb /= (mclk >> 10);
  290. } else {
  291. symb = srate << 9;
  292. symb /= (mclk >> 7);
  293. }
  294. stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
  295. stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
  296. }
  297. static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
  298. u32 mclk, u32 srate,
  299. enum fe_stv0900_demod_num demod)
  300. {
  301. u32 symb;
  302. srate = 105 * (srate / 100);
  303. if (srate > 60000000) {
  304. symb = srate << 4;
  305. symb /= (mclk >> 12);
  306. } else if (srate > 6000000) {
  307. symb = srate << 6;
  308. symb /= (mclk >> 10);
  309. } else {
  310. symb = srate << 9;
  311. symb /= (mclk >> 7);
  312. }
  313. if (symb < 0x7fff) {
  314. stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
  315. stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
  316. } else {
  317. stv0900_write_reg(intp, SFRUP1, 0x7f);
  318. stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
  319. }
  320. }
  321. static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
  322. u32 mclk, u32 srate,
  323. enum fe_stv0900_demod_num demod)
  324. {
  325. u32 symb;
  326. srate = 95 * (srate / 100);
  327. if (srate > 60000000) {
  328. symb = srate << 4;
  329. symb /= (mclk >> 12);
  330. } else if (srate > 6000000) {
  331. symb = srate << 6;
  332. symb /= (mclk >> 10);
  333. } else {
  334. symb = srate << 9;
  335. symb /= (mclk >> 7);
  336. }
  337. stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
  338. stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
  339. }
  340. static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
  341. u32 srate,
  342. enum fe_stv0900_demod_num demod)
  343. {
  344. s32 timingoffset;
  345. timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
  346. (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
  347. (stv0900_read_reg(intp, TMGREG2 + 2));
  348. timingoffset = ge2comp(timingoffset, 24);
  349. if (timingoffset == 0)
  350. timingoffset = 1;
  351. timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
  352. timingoffset /= 320;
  353. return timingoffset;
  354. }
  355. static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
  356. enum fe_stv0900_demod_num demod)
  357. {
  358. s32 rolloff;
  359. if (intp->chip_id == 0x10) {
  360. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  361. rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
  362. stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
  363. } else if (intp->chip_id <= 0x20)
  364. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
  365. else /* cut 3.0 */
  366. stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
  367. }
  368. static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
  369. {
  370. u32 rolloff;
  371. switch (ro) {
  372. case STV0900_20:
  373. rolloff = 20;
  374. break;
  375. case STV0900_25:
  376. rolloff = 25;
  377. break;
  378. case STV0900_35:
  379. default:
  380. rolloff = 35;
  381. break;
  382. }
  383. return srate + (srate * rolloff) / 100;
  384. }
  385. static int stv0900_check_timing_lock(struct stv0900_internal *intp,
  386. enum fe_stv0900_demod_num demod)
  387. {
  388. int timingLock = FALSE;
  389. s32 i,
  390. timingcpt = 0;
  391. u8 car_freq,
  392. tmg_th_high,
  393. tmg_th_low;
  394. car_freq = stv0900_read_reg(intp, CARFREQ);
  395. tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
  396. tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
  397. stv0900_write_reg(intp, TMGTHRISE, 0x20);
  398. stv0900_write_reg(intp, TMGTHFALL, 0x0);
  399. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  400. stv0900_write_reg(intp, RTC, 0x80);
  401. stv0900_write_reg(intp, RTCS2, 0x40);
  402. stv0900_write_reg(intp, CARFREQ, 0x0);
  403. stv0900_write_reg(intp, CFRINIT1, 0x0);
  404. stv0900_write_reg(intp, CFRINIT0, 0x0);
  405. stv0900_write_reg(intp, AGC2REF, 0x65);
  406. stv0900_write_reg(intp, DMDISTATE, 0x18);
  407. msleep(7);
  408. for (i = 0; i < 10; i++) {
  409. if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
  410. timingcpt++;
  411. msleep(1);
  412. }
  413. if (timingcpt >= 3)
  414. timingLock = TRUE;
  415. stv0900_write_reg(intp, AGC2REF, 0x38);
  416. stv0900_write_reg(intp, RTC, 0x88);
  417. stv0900_write_reg(intp, RTCS2, 0x68);
  418. stv0900_write_reg(intp, CARFREQ, car_freq);
  419. stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
  420. stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
  421. return timingLock;
  422. }
  423. static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
  424. s32 demod_timeout)
  425. {
  426. struct stv0900_state *state = fe->demodulator_priv;
  427. struct stv0900_internal *intp = state->internal;
  428. enum fe_stv0900_demod_num demod = state->demod;
  429. int lock = FALSE,
  430. d = demod;
  431. s32 srate,
  432. search_range,
  433. locktimeout,
  434. currier_step,
  435. nb_steps,
  436. current_step,
  437. direction,
  438. tuner_freq,
  439. timeout,
  440. freq;
  441. srate = intp->symbol_rate[d];
  442. search_range = intp->srch_range[d];
  443. if (srate >= 10000000)
  444. locktimeout = demod_timeout / 3;
  445. else
  446. locktimeout = demod_timeout / 2;
  447. lock = stv0900_get_demod_lock(intp, d, locktimeout);
  448. if (lock != FALSE)
  449. return lock;
  450. if (srate >= 10000000) {
  451. if (stv0900_check_timing_lock(intp, d) == TRUE) {
  452. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  453. stv0900_write_reg(intp, DMDISTATE, 0x15);
  454. lock = stv0900_get_demod_lock(intp, d, demod_timeout);
  455. } else
  456. lock = FALSE;
  457. return lock;
  458. }
  459. if (intp->chip_id <= 0x20) {
  460. if (srate <= 1000000)
  461. currier_step = 500;
  462. else if (srate <= 4000000)
  463. currier_step = 1000;
  464. else if (srate <= 7000000)
  465. currier_step = 2000;
  466. else if (srate <= 10000000)
  467. currier_step = 3000;
  468. else
  469. currier_step = 5000;
  470. if (srate >= 2000000) {
  471. timeout = (demod_timeout / 3);
  472. if (timeout > 1000)
  473. timeout = 1000;
  474. } else
  475. timeout = (demod_timeout / 2);
  476. } else {
  477. /*cut 3.0 */
  478. currier_step = srate / 4000;
  479. timeout = (demod_timeout * 3) / 4;
  480. }
  481. nb_steps = ((search_range / 1000) / currier_step);
  482. if ((nb_steps % 2) != 0)
  483. nb_steps += 1;
  484. if (nb_steps <= 0)
  485. nb_steps = 2;
  486. else if (nb_steps > 12)
  487. nb_steps = 12;
  488. current_step = 1;
  489. direction = 1;
  490. if (intp->chip_id <= 0x20) {
  491. tuner_freq = intp->freq[d];
  492. intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
  493. intp->rolloff) + intp->symbol_rate[d];
  494. } else
  495. tuner_freq = 0;
  496. while ((current_step <= nb_steps) && (lock == FALSE)) {
  497. if (direction > 0)
  498. tuner_freq += (current_step * currier_step);
  499. else
  500. tuner_freq -= (current_step * currier_step);
  501. if (intp->chip_id <= 0x20) {
  502. if (intp->tuner_type[d] == 3)
  503. stv0900_set_tuner_auto(intp, tuner_freq,
  504. intp->bw[d], demod);
  505. else
  506. stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
  507. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  508. stv0900_write_reg(intp, CFRINIT1, 0);
  509. stv0900_write_reg(intp, CFRINIT0, 0);
  510. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  511. stv0900_write_reg(intp, DMDISTATE, 0x15);
  512. } else {
  513. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  514. freq = (tuner_freq * 65536) / (intp->mclk / 1000);
  515. stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
  516. stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
  517. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  518. stv0900_write_reg(intp, DMDISTATE, 0x05);
  519. }
  520. lock = stv0900_get_demod_lock(intp, d, timeout);
  521. direction *= -1;
  522. current_step++;
  523. }
  524. return lock;
  525. }
  526. static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
  527. s32 srate,
  528. enum fe_stv0900_search_algo algo)
  529. {
  530. switch (algo) {
  531. case STV0900_BLIND_SEARCH:
  532. if (srate <= 1500000) {
  533. (*demod_timeout) = 1500;
  534. (*fec_timeout) = 400;
  535. } else if (srate <= 5000000) {
  536. (*demod_timeout) = 1000;
  537. (*fec_timeout) = 300;
  538. } else {
  539. (*demod_timeout) = 700;
  540. (*fec_timeout) = 100;
  541. }
  542. break;
  543. case STV0900_COLD_START:
  544. case STV0900_WARM_START:
  545. default:
  546. if (srate <= 1000000) {
  547. (*demod_timeout) = 3000;
  548. (*fec_timeout) = 1700;
  549. } else if (srate <= 2000000) {
  550. (*demod_timeout) = 2500;
  551. (*fec_timeout) = 1100;
  552. } else if (srate <= 5000000) {
  553. (*demod_timeout) = 1000;
  554. (*fec_timeout) = 550;
  555. } else if (srate <= 10000000) {
  556. (*demod_timeout) = 700;
  557. (*fec_timeout) = 250;
  558. } else if (srate <= 20000000) {
  559. (*demod_timeout) = 400;
  560. (*fec_timeout) = 130;
  561. } else {
  562. (*demod_timeout) = 300;
  563. (*fec_timeout) = 100;
  564. }
  565. break;
  566. }
  567. if (algo == STV0900_WARM_START)
  568. (*demod_timeout) /= 2;
  569. }
  570. static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
  571. enum fe_stv0900_demod_num demod)
  572. {
  573. s32 vth_reg = VTH12;
  574. dprintk("%s\n", __func__);
  575. stv0900_write_reg(intp, vth_reg++, 0xd0);
  576. stv0900_write_reg(intp, vth_reg++, 0x7d);
  577. stv0900_write_reg(intp, vth_reg++, 0x53);
  578. stv0900_write_reg(intp, vth_reg++, 0x2f);
  579. stv0900_write_reg(intp, vth_reg++, 0x24);
  580. stv0900_write_reg(intp, vth_reg++, 0x1f);
  581. }
  582. static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
  583. enum fe_stv0900_search_standard standard,
  584. enum fe_stv0900_fec fec,
  585. enum fe_stv0900_demod_num demod)
  586. {
  587. dprintk("%s: ViterbiStandard = ", __func__);
  588. switch (standard) {
  589. case STV0900_AUTO_SEARCH:
  590. dprintk("Auto\n");
  591. stv0900_write_reg(intp, FECM, 0x10);
  592. stv0900_write_reg(intp, PRVIT, 0x3f);
  593. break;
  594. case STV0900_SEARCH_DVBS1:
  595. dprintk("DVBS1\n");
  596. stv0900_write_reg(intp, FECM, 0x00);
  597. switch (fec) {
  598. case STV0900_FEC_UNKNOWN:
  599. default:
  600. stv0900_write_reg(intp, PRVIT, 0x2f);
  601. break;
  602. case STV0900_FEC_1_2:
  603. stv0900_write_reg(intp, PRVIT, 0x01);
  604. break;
  605. case STV0900_FEC_2_3:
  606. stv0900_write_reg(intp, PRVIT, 0x02);
  607. break;
  608. case STV0900_FEC_3_4:
  609. stv0900_write_reg(intp, PRVIT, 0x04);
  610. break;
  611. case STV0900_FEC_5_6:
  612. stv0900_write_reg(intp, PRVIT, 0x08);
  613. break;
  614. case STV0900_FEC_7_8:
  615. stv0900_write_reg(intp, PRVIT, 0x20);
  616. break;
  617. }
  618. break;
  619. case STV0900_SEARCH_DSS:
  620. dprintk("DSS\n");
  621. stv0900_write_reg(intp, FECM, 0x80);
  622. switch (fec) {
  623. case STV0900_FEC_UNKNOWN:
  624. default:
  625. stv0900_write_reg(intp, PRVIT, 0x13);
  626. break;
  627. case STV0900_FEC_1_2:
  628. stv0900_write_reg(intp, PRVIT, 0x01);
  629. break;
  630. case STV0900_FEC_2_3:
  631. stv0900_write_reg(intp, PRVIT, 0x02);
  632. break;
  633. case STV0900_FEC_6_7:
  634. stv0900_write_reg(intp, PRVIT, 0x10);
  635. break;
  636. }
  637. break;
  638. default:
  639. break;
  640. }
  641. }
  642. static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
  643. enum fe_stv0900_demod_num demod)
  644. {
  645. enum fe_stv0900_fec prate;
  646. s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
  647. switch (rate_fld) {
  648. case 13:
  649. prate = STV0900_FEC_1_2;
  650. break;
  651. case 18:
  652. prate = STV0900_FEC_2_3;
  653. break;
  654. case 21:
  655. prate = STV0900_FEC_3_4;
  656. break;
  657. case 24:
  658. prate = STV0900_FEC_5_6;
  659. break;
  660. case 25:
  661. prate = STV0900_FEC_6_7;
  662. break;
  663. case 26:
  664. prate = STV0900_FEC_7_8;
  665. break;
  666. default:
  667. prate = STV0900_FEC_UNKNOWN;
  668. break;
  669. }
  670. return prate;
  671. }
  672. static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
  673. enum fe_stv0900_demod_num demod,
  674. u32 srate)
  675. {
  676. if (intp->chip_id >= 0x30) {
  677. if (srate >= 15000000) {
  678. stv0900_write_reg(intp, ACLC, 0x2b);
  679. stv0900_write_reg(intp, BCLC, 0x1a);
  680. } else if ((srate >= 7000000) && (15000000 > srate)) {
  681. stv0900_write_reg(intp, ACLC, 0x0c);
  682. stv0900_write_reg(intp, BCLC, 0x1b);
  683. } else if (srate < 7000000) {
  684. stv0900_write_reg(intp, ACLC, 0x2c);
  685. stv0900_write_reg(intp, BCLC, 0x1c);
  686. }
  687. } else { /*cut 2.0 and 1.x*/
  688. stv0900_write_reg(intp, ACLC, 0x1a);
  689. stv0900_write_reg(intp, BCLC, 0x09);
  690. }
  691. }
  692. static void stv0900_track_optimization(struct dvb_frontend *fe)
  693. {
  694. struct stv0900_state *state = fe->demodulator_priv;
  695. struct stv0900_internal *intp = state->internal;
  696. enum fe_stv0900_demod_num demod = state->demod;
  697. s32 srate,
  698. pilots,
  699. aclc,
  700. freq1,
  701. freq0,
  702. i = 0,
  703. timed,
  704. timef,
  705. blind_tun_sw = 0,
  706. modulation;
  707. enum fe_stv0900_rolloff rolloff;
  708. enum fe_stv0900_modcode foundModcod;
  709. dprintk("%s\n", __func__);
  710. srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  711. srate += stv0900_get_timing_offst(intp, srate, demod);
  712. switch (intp->result[demod].standard) {
  713. case STV0900_DVBS1_STANDARD:
  714. case STV0900_DSS_STANDARD:
  715. dprintk("%s: found DVB-S or DSS\n", __func__);
  716. if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
  717. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  718. stv0900_write_bits(intp, DVBS2_ENABLE, 0);
  719. }
  720. stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
  721. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  722. if (intp->chip_id < 0x30) {
  723. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  724. break;
  725. }
  726. if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
  727. stv0900_write_reg(intp, GAUSSR0, 0x98);
  728. stv0900_write_reg(intp, CCIR0, 0x18);
  729. } else {
  730. stv0900_write_reg(intp, GAUSSR0, 0x18);
  731. stv0900_write_reg(intp, CCIR0, 0x18);
  732. }
  733. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  734. break;
  735. case STV0900_DVBS2_STANDARD:
  736. dprintk("%s: found DVB-S2\n", __func__);
  737. stv0900_write_bits(intp, DVBS1_ENABLE, 0);
  738. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  739. stv0900_write_reg(intp, ACLC, 0);
  740. stv0900_write_reg(intp, BCLC, 0);
  741. if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
  742. foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
  743. pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
  744. aclc = stv0900_get_optim_carr_loop(srate,
  745. foundModcod,
  746. pilots,
  747. intp->chip_id);
  748. if (foundModcod <= STV0900_QPSK_910)
  749. stv0900_write_reg(intp, ACLC2S2Q, aclc);
  750. else if (foundModcod <= STV0900_8PSK_910) {
  751. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  752. stv0900_write_reg(intp, ACLC2S28, aclc);
  753. }
  754. if ((intp->demod_mode == STV0900_SINGLE) &&
  755. (foundModcod > STV0900_8PSK_910)) {
  756. if (foundModcod <= STV0900_16APSK_910) {
  757. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  758. stv0900_write_reg(intp, ACLC2S216A,
  759. aclc);
  760. } else if (foundModcod <= STV0900_32APSK_910) {
  761. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  762. stv0900_write_reg(intp, ACLC2S232A,
  763. aclc);
  764. }
  765. }
  766. } else {
  767. modulation = intp->result[demod].modulation;
  768. aclc = stv0900_get_optim_short_carr_loop(srate,
  769. modulation, intp->chip_id);
  770. if (modulation == STV0900_QPSK)
  771. stv0900_write_reg(intp, ACLC2S2Q, aclc);
  772. else if (modulation == STV0900_8PSK) {
  773. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  774. stv0900_write_reg(intp, ACLC2S28, aclc);
  775. } else if (modulation == STV0900_16APSK) {
  776. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  777. stv0900_write_reg(intp, ACLC2S216A, aclc);
  778. } else if (modulation == STV0900_32APSK) {
  779. stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
  780. stv0900_write_reg(intp, ACLC2S232A, aclc);
  781. }
  782. }
  783. if (intp->chip_id <= 0x11) {
  784. if (intp->demod_mode != STV0900_SINGLE)
  785. stv0900_activate_s2_modcod(intp, demod);
  786. }
  787. stv0900_write_reg(intp, ERRCTRL1, 0x67);
  788. break;
  789. case STV0900_UNKNOWN_STANDARD:
  790. default:
  791. dprintk("%s: found unknown standard\n", __func__);
  792. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  793. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  794. break;
  795. }
  796. freq1 = stv0900_read_reg(intp, CFR2);
  797. freq0 = stv0900_read_reg(intp, CFR1);
  798. rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
  799. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
  800. stv0900_write_reg(intp, SFRSTEP, 0x00);
  801. stv0900_write_bits(intp, SCAN_ENABLE, 0);
  802. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  803. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  804. stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
  805. blind_tun_sw = 1;
  806. if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
  807. stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
  808. }
  809. if (intp->chip_id >= 0x20) {
  810. if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
  811. (intp->srch_standard[demod] ==
  812. STV0900_SEARCH_DSS) ||
  813. (intp->srch_standard[demod] ==
  814. STV0900_AUTO_SEARCH)) {
  815. stv0900_write_reg(intp, VAVSRVIT, 0x0a);
  816. stv0900_write_reg(intp, VITSCALE, 0x0);
  817. }
  818. }
  819. if (intp->chip_id < 0x20)
  820. stv0900_write_reg(intp, CARHDR, 0x08);
  821. if (intp->chip_id == 0x10)
  822. stv0900_write_reg(intp, CORRELEXP, 0x0a);
  823. stv0900_write_reg(intp, AGC2REF, 0x38);
  824. if ((intp->chip_id >= 0x20) ||
  825. (blind_tun_sw == 1) ||
  826. (intp->symbol_rate[demod] < 10000000)) {
  827. stv0900_write_reg(intp, CFRINIT1, freq1);
  828. stv0900_write_reg(intp, CFRINIT0, freq0);
  829. intp->bw[demod] = stv0900_carrier_width(srate,
  830. intp->rolloff) + 10000000;
  831. if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
  832. if (intp->srch_algo[demod] != STV0900_WARM_START) {
  833. if (intp->tuner_type[demod] == 3)
  834. stv0900_set_tuner_auto(intp,
  835. intp->freq[demod],
  836. intp->bw[demod],
  837. demod);
  838. else
  839. stv0900_set_bandwidth(fe,
  840. intp->bw[demod]);
  841. }
  842. }
  843. if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
  844. (intp->symbol_rate[demod] < 10000000))
  845. msleep(50);
  846. else
  847. msleep(5);
  848. stv0900_get_lock_timeout(&timed, &timef, srate,
  849. STV0900_WARM_START);
  850. if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
  851. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  852. stv0900_write_reg(intp, CFRINIT1, freq1);
  853. stv0900_write_reg(intp, CFRINIT0, freq0);
  854. stv0900_write_reg(intp, DMDISTATE, 0x18);
  855. i = 0;
  856. while ((stv0900_get_demod_lock(intp,
  857. demod,
  858. timed / 2) == FALSE) &&
  859. (i <= 2)) {
  860. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  861. stv0900_write_reg(intp, CFRINIT1, freq1);
  862. stv0900_write_reg(intp, CFRINIT0, freq0);
  863. stv0900_write_reg(intp, DMDISTATE, 0x18);
  864. i++;
  865. }
  866. }
  867. }
  868. if (intp->chip_id >= 0x20)
  869. stv0900_write_reg(intp, CARFREQ, 0x49);
  870. if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
  871. (intp->result[demod].standard == STV0900_DSS_STANDARD))
  872. stv0900_set_viterbi_tracq(intp, demod);
  873. }
  874. static int stv0900_get_fec_lock(struct stv0900_internal *intp,
  875. enum fe_stv0900_demod_num demod, s32 time_out)
  876. {
  877. s32 timer = 0, lock = 0;
  878. enum fe_stv0900_search_state dmd_state;
  879. dprintk("%s\n", __func__);
  880. dmd_state = stv0900_get_bits(intp, HEADER_MODE);
  881. while ((timer < time_out) && (lock == 0)) {
  882. switch (dmd_state) {
  883. case STV0900_SEARCH:
  884. case STV0900_PLH_DETECTED:
  885. default:
  886. lock = 0;
  887. break;
  888. case STV0900_DVBS2_FOUND:
  889. lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
  890. break;
  891. case STV0900_DVBS_FOUND:
  892. lock = stv0900_get_bits(intp, LOCKEDVIT);
  893. break;
  894. }
  895. if (lock == 0) {
  896. msleep(10);
  897. timer += 10;
  898. }
  899. }
  900. if (lock)
  901. dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
  902. else
  903. dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
  904. return lock;
  905. }
  906. static int stv0900_wait_for_lock(struct stv0900_internal *intp,
  907. enum fe_stv0900_demod_num demod,
  908. s32 dmd_timeout, s32 fec_timeout)
  909. {
  910. s32 timer = 0, lock = 0;
  911. dprintk("%s\n", __func__);
  912. lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
  913. if (lock)
  914. lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
  915. if (lock) {
  916. lock = 0;
  917. dprintk("%s: Timer = %d, time_out = %d\n",
  918. __func__, timer, fec_timeout);
  919. while ((timer < fec_timeout) && (lock == 0)) {
  920. lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
  921. msleep(1);
  922. timer++;
  923. }
  924. }
  925. if (lock)
  926. dprintk("%s: DEMOD LOCK OK\n", __func__);
  927. else
  928. dprintk("%s: DEMOD LOCK FAIL\n", __func__);
  929. if (lock)
  930. return TRUE;
  931. else
  932. return FALSE;
  933. }
  934. enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
  935. enum fe_stv0900_demod_num demod)
  936. {
  937. struct stv0900_state *state = fe->demodulator_priv;
  938. struct stv0900_internal *intp = state->internal;
  939. enum fe_stv0900_tracking_standard fnd_standard;
  940. int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
  941. switch (hdr_mode) {
  942. case 2:
  943. fnd_standard = STV0900_DVBS2_STANDARD;
  944. break;
  945. case 3:
  946. if (stv0900_get_bits(intp, DSS_DVB) == 1)
  947. fnd_standard = STV0900_DSS_STANDARD;
  948. else
  949. fnd_standard = STV0900_DVBS1_STANDARD;
  950. break;
  951. default:
  952. fnd_standard = STV0900_UNKNOWN_STANDARD;
  953. }
  954. dprintk("%s: standard %d\n", __func__, fnd_standard);
  955. return fnd_standard;
  956. }
  957. static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
  958. enum fe_stv0900_demod_num demod)
  959. {
  960. s32 derot,
  961. rem1,
  962. rem2,
  963. intval1,
  964. intval2;
  965. derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
  966. (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
  967. (stv0900_get_bits(intp, CAR_FREQ0));
  968. derot = ge2comp(derot, 24);
  969. intval1 = mclk >> 12;
  970. intval2 = derot >> 12;
  971. rem1 = mclk % 0x1000;
  972. rem2 = derot % 0x1000;
  973. derot = (intval1 * intval2) +
  974. ((intval1 * rem2) >> 12) +
  975. ((intval2 * rem1) >> 12);
  976. return derot;
  977. }
  978. static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
  979. {
  980. struct dvb_frontend_ops *frontend_ops = NULL;
  981. struct dvb_tuner_ops *tuner_ops = NULL;
  982. u32 freq = 0;
  983. if (&fe->ops)
  984. frontend_ops = &fe->ops;
  985. if (&frontend_ops->tuner_ops)
  986. tuner_ops = &frontend_ops->tuner_ops;
  987. if (tuner_ops->get_frequency) {
  988. if ((tuner_ops->get_frequency(fe, &freq)) < 0)
  989. dprintk("%s: Invalid parameter\n", __func__);
  990. else
  991. dprintk("%s: Frequency=%d\n", __func__, freq);
  992. }
  993. return freq;
  994. }
  995. static enum
  996. fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
  997. {
  998. struct stv0900_state *state = fe->demodulator_priv;
  999. struct stv0900_internal *intp = state->internal;
  1000. enum fe_stv0900_demod_num demod = state->demod;
  1001. enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
  1002. struct stv0900_signal_info *result = &intp->result[demod];
  1003. s32 offsetFreq,
  1004. srate_offset;
  1005. int i = 0,
  1006. d = demod;
  1007. u8 timing;
  1008. msleep(5);
  1009. if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
  1010. timing = stv0900_read_reg(intp, TMGREG2);
  1011. i = 0;
  1012. stv0900_write_reg(intp, SFRSTEP, 0x5c);
  1013. while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
  1014. timing = stv0900_read_reg(intp, TMGREG2);
  1015. msleep(5);
  1016. i += 5;
  1017. }
  1018. }
  1019. result->standard = stv0900_get_standard(fe, d);
  1020. if (intp->tuner_type[demod] == 3)
  1021. result->frequency = stv0900_get_freq_auto(intp, d);
  1022. else
  1023. result->frequency = stv0900_get_tuner_freq(fe);
  1024. offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
  1025. result->frequency += offsetFreq;
  1026. result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
  1027. srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
  1028. result->symbol_rate += srate_offset;
  1029. result->fec = stv0900_get_vit_fec(intp, d);
  1030. result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
  1031. result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
  1032. result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
  1033. result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
  1034. dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
  1035. switch (result->standard) {
  1036. case STV0900_DVBS2_STANDARD:
  1037. result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
  1038. if (result->modcode <= STV0900_QPSK_910)
  1039. result->modulation = STV0900_QPSK;
  1040. else if (result->modcode <= STV0900_8PSK_910)
  1041. result->modulation = STV0900_8PSK;
  1042. else if (result->modcode <= STV0900_16APSK_910)
  1043. result->modulation = STV0900_16APSK;
  1044. else if (result->modcode <= STV0900_32APSK_910)
  1045. result->modulation = STV0900_32APSK;
  1046. else
  1047. result->modulation = STV0900_UNKNOWN;
  1048. break;
  1049. case STV0900_DVBS1_STANDARD:
  1050. case STV0900_DSS_STANDARD:
  1051. result->spectrum = stv0900_get_bits(intp, IQINV);
  1052. result->modulation = STV0900_QPSK;
  1053. break;
  1054. default:
  1055. break;
  1056. }
  1057. if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
  1058. (intp->symbol_rate[d] < 10000000)) {
  1059. offsetFreq = result->frequency - intp->freq[d];
  1060. if (intp->tuner_type[demod] == 3)
  1061. intp->freq[d] = stv0900_get_freq_auto(intp, d);
  1062. else
  1063. intp->freq[d] = stv0900_get_tuner_freq(fe);
  1064. if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
  1065. range = STV0900_RANGEOK;
  1066. else if (ABS(offsetFreq) <=
  1067. (stv0900_carrier_width(result->symbol_rate,
  1068. result->rolloff) / 2000))
  1069. range = STV0900_RANGEOK;
  1070. } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
  1071. range = STV0900_RANGEOK;
  1072. dprintk("%s: range %d\n", __func__, range);
  1073. return range;
  1074. }
  1075. static enum
  1076. fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
  1077. {
  1078. struct stv0900_state *state = fe->demodulator_priv;
  1079. struct stv0900_internal *intp = state->internal;
  1080. enum fe_stv0900_demod_num demod = state->demod;
  1081. enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
  1082. s32 srate,
  1083. demod_timeout,
  1084. fec_timeout,
  1085. freq1,
  1086. freq0;
  1087. intp->result[demod].locked = FALSE;
  1088. if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
  1089. srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1090. srate += stv0900_get_timing_offst(intp, srate, demod);
  1091. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
  1092. stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
  1093. stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
  1094. srate, STV0900_WARM_START);
  1095. freq1 = stv0900_read_reg(intp, CFR2);
  1096. freq0 = stv0900_read_reg(intp, CFR1);
  1097. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1098. stv0900_write_bits(intp, SPECINV_CONTROL,
  1099. STV0900_IQ_FORCE_SWAPPED);
  1100. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  1101. stv0900_write_reg(intp, CFRINIT1, freq1);
  1102. stv0900_write_reg(intp, CFRINIT0, freq0);
  1103. stv0900_write_reg(intp, DMDISTATE, 0x18);
  1104. if (stv0900_wait_for_lock(intp, demod,
  1105. demod_timeout, fec_timeout) == TRUE) {
  1106. intp->result[demod].locked = TRUE;
  1107. signal_type = stv0900_get_signal_params(fe);
  1108. stv0900_track_optimization(fe);
  1109. } else {
  1110. stv0900_write_bits(intp, SPECINV_CONTROL,
  1111. STV0900_IQ_FORCE_NORMAL);
  1112. stv0900_write_reg(intp, DMDISTATE, 0x1c);
  1113. stv0900_write_reg(intp, CFRINIT1, freq1);
  1114. stv0900_write_reg(intp, CFRINIT0, freq0);
  1115. stv0900_write_reg(intp, DMDISTATE, 0x18);
  1116. if (stv0900_wait_for_lock(intp, demod,
  1117. demod_timeout, fec_timeout) == TRUE) {
  1118. intp->result[demod].locked = TRUE;
  1119. signal_type = stv0900_get_signal_params(fe);
  1120. stv0900_track_optimization(fe);
  1121. }
  1122. }
  1123. } else
  1124. intp->result[demod].locked = FALSE;
  1125. return signal_type;
  1126. }
  1127. static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
  1128. enum fe_stv0900_demod_num demod)
  1129. {
  1130. u32 minagc2level = 0xffff,
  1131. agc2level,
  1132. init_freq, freq_step;
  1133. s32 i, j, nb_steps, direction;
  1134. dprintk("%s\n", __func__);
  1135. stv0900_write_reg(intp, AGC2REF, 0x38);
  1136. stv0900_write_bits(intp, SCAN_ENABLE, 0);
  1137. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1138. stv0900_write_bits(intp, AUTO_GUP, 1);
  1139. stv0900_write_bits(intp, AUTO_GLOW, 1);
  1140. stv0900_write_reg(intp, DMDT0M, 0x0);
  1141. stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
  1142. nb_steps = -1 + (intp->srch_range[demod] / 1000000);
  1143. nb_steps /= 2;
  1144. nb_steps = (2 * nb_steps) + 1;
  1145. if (nb_steps < 0)
  1146. nb_steps = 1;
  1147. direction = 1;
  1148. freq_step = (1000000 << 8) / (intp->mclk >> 8);
  1149. init_freq = 0;
  1150. for (i = 0; i < nb_steps; i++) {
  1151. if (direction > 0)
  1152. init_freq = init_freq + (freq_step * i);
  1153. else
  1154. init_freq = init_freq - (freq_step * i);
  1155. direction *= -1;
  1156. stv0900_write_reg(intp, DMDISTATE, 0x5C);
  1157. stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
  1158. stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
  1159. stv0900_write_reg(intp, DMDISTATE, 0x58);
  1160. msleep(10);
  1161. agc2level = 0;
  1162. for (j = 0; j < 10; j++)
  1163. agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
  1164. | stv0900_read_reg(intp, AGC2I0);
  1165. agc2level /= 10;
  1166. if (agc2level < minagc2level)
  1167. minagc2level = agc2level;
  1168. }
  1169. return (u16)minagc2level;
  1170. }
  1171. static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
  1172. {
  1173. struct stv0900_state *state = fe->demodulator_priv;
  1174. struct stv0900_internal *intp = state->internal;
  1175. enum fe_stv0900_demod_num demod = state->demod;
  1176. int timing_lck = FALSE;
  1177. s32 i, timingcpt = 0,
  1178. direction = 1,
  1179. nb_steps,
  1180. current_step = 0,
  1181. tuner_freq;
  1182. u32 agc2_th,
  1183. coarse_srate = 0,
  1184. agc2_integr = 0,
  1185. currier_step = 1200;
  1186. if (intp->chip_id >= 0x30)
  1187. agc2_th = 0x2e00;
  1188. else
  1189. agc2_th = 0x1f00;
  1190. stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
  1191. stv0900_write_reg(intp, TMGCFG, 0x12);
  1192. stv0900_write_reg(intp, TMGTHRISE, 0xf0);
  1193. stv0900_write_reg(intp, TMGTHFALL, 0xe0);
  1194. stv0900_write_bits(intp, SCAN_ENABLE, 1);
  1195. stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
  1196. stv0900_write_reg(intp, SFRUP1, 0x83);
  1197. stv0900_write_reg(intp, SFRUP0, 0xc0);
  1198. stv0900_write_reg(intp, SFRLOW1, 0x82);
  1199. stv0900_write_reg(intp, SFRLOW0, 0xa0);
  1200. stv0900_write_reg(intp, DMDT0M, 0x0);
  1201. stv0900_write_reg(intp, AGC2REF, 0x50);
  1202. if (intp->chip_id >= 0x30) {
  1203. stv0900_write_reg(intp, CARFREQ, 0x99);
  1204. stv0900_write_reg(intp, SFRSTEP, 0x98);
  1205. } else if (intp->chip_id >= 0x20) {
  1206. stv0900_write_reg(intp, CARFREQ, 0x6a);
  1207. stv0900_write_reg(intp, SFRSTEP, 0x95);
  1208. } else {
  1209. stv0900_write_reg(intp, CARFREQ, 0xed);
  1210. stv0900_write_reg(intp, SFRSTEP, 0x73);
  1211. }
  1212. if (intp->symbol_rate[demod] <= 2000000)
  1213. currier_step = 1000;
  1214. else if (intp->symbol_rate[demod] <= 5000000)
  1215. currier_step = 2000;
  1216. else if (intp->symbol_rate[demod] <= 12000000)
  1217. currier_step = 3000;
  1218. else
  1219. currier_step = 5000;
  1220. nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
  1221. nb_steps /= 2;
  1222. nb_steps = (2 * nb_steps) + 1;
  1223. if (nb_steps < 0)
  1224. nb_steps = 1;
  1225. else if (nb_steps > 10) {
  1226. nb_steps = 11;
  1227. currier_step = (intp->srch_range[demod] / 1000) / 10;
  1228. }
  1229. current_step = 0;
  1230. direction = 1;
  1231. tuner_freq = intp->freq[demod];
  1232. while ((timing_lck == FALSE) && (current_step < nb_steps)) {
  1233. stv0900_write_reg(intp, DMDISTATE, 0x5f);
  1234. stv0900_write_bits(intp, DEMOD_MODE, 0);
  1235. msleep(50);
  1236. for (i = 0; i < 10; i++) {
  1237. if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
  1238. timingcpt++;
  1239. agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
  1240. stv0900_read_reg(intp, AGC2I0);
  1241. }
  1242. agc2_integr /= 10;
  1243. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1244. current_step++;
  1245. direction *= -1;
  1246. dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
  1247. " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
  1248. tuner_freq, agc2_integr, coarse_srate, timingcpt);
  1249. if ((timingcpt >= 5) &&
  1250. (agc2_integr < agc2_th) &&
  1251. (coarse_srate < 55000000) &&
  1252. (coarse_srate > 850000))
  1253. timing_lck = TRUE;
  1254. else if (current_step < nb_steps) {
  1255. if (direction > 0)
  1256. tuner_freq += (current_step * currier_step);
  1257. else
  1258. tuner_freq -= (current_step * currier_step);
  1259. if (intp->tuner_type[demod] == 3)
  1260. stv0900_set_tuner_auto(intp, tuner_freq,
  1261. intp->bw[demod], demod);
  1262. else
  1263. stv0900_set_tuner(fe, tuner_freq,
  1264. intp->bw[demod]);
  1265. }
  1266. }
  1267. if (timing_lck == FALSE)
  1268. coarse_srate = 0;
  1269. else
  1270. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1271. return coarse_srate;
  1272. }
  1273. static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
  1274. {
  1275. struct stv0900_state *state = fe->demodulator_priv;
  1276. struct stv0900_internal *intp = state->internal;
  1277. enum fe_stv0900_demod_num demod = state->demod;
  1278. u32 coarse_srate,
  1279. coarse_freq,
  1280. symb,
  1281. symbmax,
  1282. symbmin,
  1283. symbcomp;
  1284. coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
  1285. if (coarse_srate > 3000000) {
  1286. symbmax = 13 * (coarse_srate / 10);
  1287. symbmax = (symbmax / 1000) * 65536;
  1288. symbmax /= (intp->mclk / 1000);
  1289. symbmin = 10 * (coarse_srate / 13);
  1290. symbmin = (symbmin / 1000)*65536;
  1291. symbmin /= (intp->mclk / 1000);
  1292. symb = (coarse_srate / 1000) * 65536;
  1293. symb /= (intp->mclk / 1000);
  1294. } else {
  1295. symbmax = 13 * (coarse_srate / 10);
  1296. symbmax = (symbmax / 100) * 65536;
  1297. symbmax /= (intp->mclk / 100);
  1298. symbmin = 10 * (coarse_srate / 14);
  1299. symbmin = (symbmin / 100) * 65536;
  1300. symbmin /= (intp->mclk / 100);
  1301. symb = (coarse_srate / 100) * 65536;
  1302. symb /= (intp->mclk / 100);
  1303. }
  1304. symbcomp = 13 * (coarse_srate / 10);
  1305. coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
  1306. | stv0900_read_reg(intp, CFR1);
  1307. if (symbcomp < intp->symbol_rate[demod])
  1308. coarse_srate = 0;
  1309. else {
  1310. stv0900_write_reg(intp, DMDISTATE, 0x1f);
  1311. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  1312. stv0900_write_reg(intp, TMGTHRISE, 0x20);
  1313. stv0900_write_reg(intp, TMGTHFALL, 0x00);
  1314. stv0900_write_reg(intp, TMGCFG, 0xd2);
  1315. stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
  1316. stv0900_write_reg(intp, AGC2REF, 0x38);
  1317. if (intp->chip_id >= 0x30)
  1318. stv0900_write_reg(intp, CARFREQ, 0x79);
  1319. else if (intp->chip_id >= 0x20)
  1320. stv0900_write_reg(intp, CARFREQ, 0x49);
  1321. else
  1322. stv0900_write_reg(intp, CARFREQ, 0xed);
  1323. stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
  1324. stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
  1325. stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
  1326. stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
  1327. stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
  1328. stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
  1329. stv0900_write_reg(intp, DMDT0M, 0x20);
  1330. stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
  1331. stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
  1332. stv0900_write_reg(intp, DMDISTATE, 0x15);
  1333. }
  1334. return coarse_srate;
  1335. }
  1336. static int stv0900_blind_search_algo(struct dvb_frontend *fe)
  1337. {
  1338. struct stv0900_state *state = fe->demodulator_priv;
  1339. struct stv0900_internal *intp = state->internal;
  1340. enum fe_stv0900_demod_num demod = state->demod;
  1341. u8 k_ref_tmg,
  1342. k_ref_tmg_max,
  1343. k_ref_tmg_min;
  1344. u32 coarse_srate,
  1345. agc2_th;
  1346. int lock = FALSE,
  1347. coarse_fail = FALSE;
  1348. s32 demod_timeout = 500,
  1349. fec_timeout = 50,
  1350. fail_cpt,
  1351. i,
  1352. agc2_overflow;
  1353. u16 agc2_int;
  1354. u8 dstatus2;
  1355. dprintk("%s\n", __func__);
  1356. if (intp->chip_id < 0x20) {
  1357. k_ref_tmg_max = 233;
  1358. k_ref_tmg_min = 143;
  1359. } else {
  1360. k_ref_tmg_max = 110;
  1361. k_ref_tmg_min = 10;
  1362. }
  1363. if (intp->chip_id <= 0x20)
  1364. agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
  1365. else
  1366. agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
  1367. agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
  1368. dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
  1369. if (agc2_int > agc2_th)
  1370. return FALSE;
  1371. if (intp->chip_id == 0x10)
  1372. stv0900_write_reg(intp, CORRELEXP, 0xaa);
  1373. if (intp->chip_id < 0x20)
  1374. stv0900_write_reg(intp, CARHDR, 0x55);
  1375. else
  1376. stv0900_write_reg(intp, CARHDR, 0x20);
  1377. if (intp->chip_id <= 0x20)
  1378. stv0900_write_reg(intp, CARCFG, 0xc4);
  1379. else
  1380. stv0900_write_reg(intp, CARCFG, 0x6);
  1381. stv0900_write_reg(intp, RTCS2, 0x44);
  1382. if (intp->chip_id >= 0x20) {
  1383. stv0900_write_reg(intp, EQUALCFG, 0x41);
  1384. stv0900_write_reg(intp, FFECFG, 0x41);
  1385. stv0900_write_reg(intp, VITSCALE, 0x82);
  1386. stv0900_write_reg(intp, VAVSRVIT, 0x0);
  1387. }
  1388. k_ref_tmg = k_ref_tmg_max;
  1389. do {
  1390. stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
  1391. if (stv0900_search_srate_coarse(fe) != 0) {
  1392. coarse_srate = stv0900_search_srate_fine(fe);
  1393. if (coarse_srate != 0) {
  1394. stv0900_get_lock_timeout(&demod_timeout,
  1395. &fec_timeout,
  1396. coarse_srate,
  1397. STV0900_BLIND_SEARCH);
  1398. lock = stv0900_get_demod_lock(intp,
  1399. demod,
  1400. demod_timeout);
  1401. } else
  1402. lock = FALSE;
  1403. } else {
  1404. fail_cpt = 0;
  1405. agc2_overflow = 0;
  1406. for (i = 0; i < 10; i++) {
  1407. agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
  1408. | stv0900_read_reg(intp, AGC2I0);
  1409. if (agc2_int >= 0xff00)
  1410. agc2_overflow++;
  1411. dstatus2 = stv0900_read_reg(intp, DSTATUS2);
  1412. if (((dstatus2 & 0x1) == 0x1) &&
  1413. ((dstatus2 >> 7) == 1))
  1414. fail_cpt++;
  1415. }
  1416. if ((fail_cpt > 7) || (agc2_overflow > 7))
  1417. coarse_fail = TRUE;
  1418. lock = FALSE;
  1419. }
  1420. k_ref_tmg -= 30;
  1421. } while ((k_ref_tmg >= k_ref_tmg_min) &&
  1422. (lock == FALSE) &&
  1423. (coarse_fail == FALSE));
  1424. return lock;
  1425. }
  1426. static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
  1427. enum fe_stv0900_demod_num demod)
  1428. {
  1429. s32 vth_reg = VTH12;
  1430. dprintk("%s\n", __func__);
  1431. stv0900_write_reg(intp, vth_reg++, 0x96);
  1432. stv0900_write_reg(intp, vth_reg++, 0x64);
  1433. stv0900_write_reg(intp, vth_reg++, 0x36);
  1434. stv0900_write_reg(intp, vth_reg++, 0x23);
  1435. stv0900_write_reg(intp, vth_reg++, 0x1e);
  1436. stv0900_write_reg(intp, vth_reg++, 0x19);
  1437. }
  1438. static void stv0900_set_search_standard(struct stv0900_internal *intp,
  1439. enum fe_stv0900_demod_num demod)
  1440. {
  1441. dprintk("%s\n", __func__);
  1442. switch (intp->srch_standard[demod]) {
  1443. case STV0900_SEARCH_DVBS1:
  1444. dprintk("Search Standard = DVBS1\n");
  1445. break;
  1446. case STV0900_SEARCH_DSS:
  1447. dprintk("Search Standard = DSS\n");
  1448. case STV0900_SEARCH_DVBS2:
  1449. break;
  1450. dprintk("Search Standard = DVBS2\n");
  1451. case STV0900_AUTO_SEARCH:
  1452. default:
  1453. dprintk("Search Standard = AUTO\n");
  1454. break;
  1455. }
  1456. switch (intp->srch_standard[demod]) {
  1457. case STV0900_SEARCH_DVBS1:
  1458. case STV0900_SEARCH_DSS:
  1459. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  1460. stv0900_write_bits(intp, DVBS2_ENABLE, 0);
  1461. stv0900_write_bits(intp, STOP_CLKVIT, 0);
  1462. stv0900_set_dvbs1_track_car_loop(intp,
  1463. demod,
  1464. intp->symbol_rate[demod]);
  1465. stv0900_write_reg(intp, CAR2CFG, 0x22);
  1466. stv0900_set_viterbi_acq(intp, demod);
  1467. stv0900_set_viterbi_standard(intp,
  1468. intp->srch_standard[demod],
  1469. intp->fec[demod], demod);
  1470. break;
  1471. case STV0900_SEARCH_DVBS2:
  1472. stv0900_write_bits(intp, DVBS1_ENABLE, 0);
  1473. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  1474. stv0900_write_bits(intp, STOP_CLKVIT, 1);
  1475. stv0900_write_reg(intp, ACLC, 0x1a);
  1476. stv0900_write_reg(intp, BCLC, 0x09);
  1477. if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
  1478. stv0900_write_reg(intp, CAR2CFG, 0x26);
  1479. else
  1480. stv0900_write_reg(intp, CAR2CFG, 0x66);
  1481. if (intp->demod_mode != STV0900_SINGLE) {
  1482. if (intp->chip_id <= 0x11)
  1483. stv0900_stop_all_s2_modcod(intp, demod);
  1484. else
  1485. stv0900_activate_s2_modcod(intp, demod);
  1486. } else
  1487. stv0900_activate_s2_modcod_single(intp, demod);
  1488. stv0900_set_viterbi_tracq(intp, demod);
  1489. break;
  1490. case STV0900_AUTO_SEARCH:
  1491. default:
  1492. stv0900_write_bits(intp, DVBS1_ENABLE, 1);
  1493. stv0900_write_bits(intp, DVBS2_ENABLE, 1);
  1494. stv0900_write_bits(intp, STOP_CLKVIT, 0);
  1495. stv0900_write_reg(intp, ACLC, 0x1a);
  1496. stv0900_write_reg(intp, BCLC, 0x09);
  1497. stv0900_set_dvbs1_track_car_loop(intp,
  1498. demod,
  1499. intp->symbol_rate[demod]);
  1500. if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
  1501. stv0900_write_reg(intp, CAR2CFG, 0x26);
  1502. else
  1503. stv0900_write_reg(intp, CAR2CFG, 0x66);
  1504. if (intp->demod_mode != STV0900_SINGLE) {
  1505. if (intp->chip_id <= 0x11)
  1506. stv0900_stop_all_s2_modcod(intp, demod);
  1507. else
  1508. stv0900_activate_s2_modcod(intp, demod);
  1509. } else
  1510. stv0900_activate_s2_modcod_single(intp, demod);
  1511. stv0900_set_viterbi_tracq(intp, demod);
  1512. stv0900_set_viterbi_standard(intp,
  1513. intp->srch_standard[demod],
  1514. intp->fec[demod], demod);
  1515. break;
  1516. }
  1517. }
  1518. enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
  1519. {
  1520. struct stv0900_state *state = fe->demodulator_priv;
  1521. struct stv0900_internal *intp = state->internal;
  1522. enum fe_stv0900_demod_num demod = state->demod;
  1523. s32 demod_timeout = 500, fec_timeout = 50;
  1524. s32 aq_power, agc1_power, i;
  1525. int lock = FALSE, low_sr = FALSE;
  1526. enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
  1527. enum fe_stv0900_search_algo algo;
  1528. int no_signal = FALSE;
  1529. dprintk("%s\n", __func__);
  1530. algo = intp->srch_algo[demod];
  1531. stv0900_write_bits(intp, RST_HWARE, 1);
  1532. stv0900_write_reg(intp, DMDISTATE, 0x5c);
  1533. if (intp->chip_id >= 0x20) {
  1534. if (intp->symbol_rate[demod] > 5000000)
  1535. stv0900_write_reg(intp, CORRELABS, 0x9e);
  1536. else
  1537. stv0900_write_reg(intp, CORRELABS, 0x82);
  1538. } else
  1539. stv0900_write_reg(intp, CORRELABS, 0x88);
  1540. stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
  1541. intp->symbol_rate[demod],
  1542. intp->srch_algo[demod]);
  1543. if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
  1544. intp->bw[demod] = 2 * 36000000;
  1545. stv0900_write_reg(intp, TMGCFG2, 0xc0);
  1546. stv0900_write_reg(intp, CORRELMANT, 0x70);
  1547. stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
  1548. } else {
  1549. stv0900_write_reg(intp, DMDT0M, 0x20);
  1550. stv0900_write_reg(intp, TMGCFG, 0xd2);
  1551. if (intp->symbol_rate[demod] < 2000000)
  1552. stv0900_write_reg(intp, CORRELMANT, 0x63);
  1553. else
  1554. stv0900_write_reg(intp, CORRELMANT, 0x70);
  1555. stv0900_write_reg(intp, AGC2REF, 0x38);
  1556. intp->bw[demod] =
  1557. stv0900_carrier_width(intp->symbol_rate[demod],
  1558. intp->rolloff);
  1559. if (intp->chip_id >= 0x20) {
  1560. stv0900_write_reg(intp, KREFTMG, 0x5a);
  1561. if (intp->srch_algo[demod] == STV0900_COLD_START) {
  1562. intp->bw[demod] += 10000000;
  1563. intp->bw[demod] *= 15;
  1564. intp->bw[demod] /= 10;
  1565. } else if (intp->srch_algo[demod] == STV0900_WARM_START)
  1566. intp->bw[demod] += 10000000;
  1567. } else {
  1568. stv0900_write_reg(intp, KREFTMG, 0xc1);
  1569. intp->bw[demod] += 10000000;
  1570. intp->bw[demod] *= 15;
  1571. intp->bw[demod] /= 10;
  1572. }
  1573. stv0900_write_reg(intp, TMGCFG2, 0xc1);
  1574. stv0900_set_symbol_rate(intp, intp->mclk,
  1575. intp->symbol_rate[demod], demod);
  1576. stv0900_set_max_symbol_rate(intp, intp->mclk,
  1577. intp->symbol_rate[demod], demod);
  1578. stv0900_set_min_symbol_rate(intp, intp->mclk,
  1579. intp->symbol_rate[demod], demod);
  1580. if (intp->symbol_rate[demod] >= 10000000)
  1581. low_sr = FALSE;
  1582. else
  1583. low_sr = TRUE;
  1584. }
  1585. if (intp->tuner_type[demod] == 3)
  1586. stv0900_set_tuner_auto(intp, intp->freq[demod],
  1587. intp->bw[demod], demod);
  1588. else
  1589. stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
  1590. agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
  1591. stv0900_get_bits(intp, AGCIQ_VALUE0));
  1592. aq_power = 0;
  1593. if (agc1_power == 0) {
  1594. for (i = 0; i < 5; i++)
  1595. aq_power += (stv0900_get_bits(intp, POWER_I) +
  1596. stv0900_get_bits(intp, POWER_Q)) / 2;
  1597. aq_power /= 5;
  1598. }
  1599. if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
  1600. intp->result[demod].locked = FALSE;
  1601. signal_type = STV0900_NOAGC1;
  1602. dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
  1603. } else {
  1604. stv0900_write_bits(intp, SPECINV_CONTROL,
  1605. intp->srch_iq_inv[demod]);
  1606. if (intp->chip_id <= 0x20) /*cut 2.0*/
  1607. stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
  1608. else /*cut 3.0*/
  1609. stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
  1610. stv0900_set_search_standard(intp, demod);
  1611. if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
  1612. stv0900_start_search(intp, demod);
  1613. }
  1614. if (signal_type == STV0900_NOAGC1)
  1615. return signal_type;
  1616. if (intp->chip_id == 0x12) {
  1617. stv0900_write_bits(intp, RST_HWARE, 0);
  1618. msleep(3);
  1619. stv0900_write_bits(intp, RST_HWARE, 1);
  1620. stv0900_write_bits(intp, RST_HWARE, 0);
  1621. }
  1622. if (algo == STV0900_BLIND_SEARCH)
  1623. lock = stv0900_blind_search_algo(fe);
  1624. else if (algo == STV0900_COLD_START)
  1625. lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
  1626. else if (algo == STV0900_WARM_START)
  1627. lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
  1628. if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
  1629. if (low_sr == FALSE) {
  1630. if (stv0900_check_timing_lock(intp, demod) == TRUE)
  1631. lock = stv0900_sw_algo(intp, demod);
  1632. }
  1633. }
  1634. if (lock == TRUE)
  1635. signal_type = stv0900_get_signal_params(fe);
  1636. if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
  1637. stv0900_track_optimization(fe);
  1638. if (intp->chip_id <= 0x11) {
  1639. if ((stv0900_get_standard(fe, 0) ==
  1640. STV0900_DVBS1_STANDARD) &&
  1641. (stv0900_get_standard(fe, 1) ==
  1642. STV0900_DVBS1_STANDARD)) {
  1643. msleep(20);
  1644. stv0900_write_bits(intp, RST_HWARE, 0);
  1645. } else {
  1646. stv0900_write_bits(intp, RST_HWARE, 0);
  1647. msleep(3);
  1648. stv0900_write_bits(intp, RST_HWARE, 1);
  1649. stv0900_write_bits(intp, RST_HWARE, 0);
  1650. }
  1651. } else if (intp->chip_id >= 0x20) {
  1652. stv0900_write_bits(intp, RST_HWARE, 0);
  1653. msleep(3);
  1654. stv0900_write_bits(intp, RST_HWARE, 1);
  1655. stv0900_write_bits(intp, RST_HWARE, 0);
  1656. }
  1657. if (stv0900_wait_for_lock(intp, demod,
  1658. fec_timeout, fec_timeout) == TRUE) {
  1659. lock = TRUE;
  1660. intp->result[demod].locked = TRUE;
  1661. if (intp->result[demod].standard ==
  1662. STV0900_DVBS2_STANDARD) {
  1663. stv0900_set_dvbs2_rolloff(intp, demod);
  1664. stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
  1665. stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
  1666. stv0900_write_reg(intp, ERRCTRL1, 0x67);
  1667. } else {
  1668. stv0900_write_reg(intp, ERRCTRL1, 0x75);
  1669. }
  1670. stv0900_write_reg(intp, FBERCPT4, 0);
  1671. stv0900_write_reg(intp, ERRCTRL2, 0xc1);
  1672. } else {
  1673. lock = FALSE;
  1674. signal_type = STV0900_NODATA;
  1675. no_signal = stv0900_check_signal_presence(intp, demod);
  1676. intp->result[demod].locked = FALSE;
  1677. }
  1678. }
  1679. if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
  1680. return signal_type;
  1681. if (intp->chip_id > 0x11) {
  1682. intp->result[demod].locked = FALSE;
  1683. return signal_type;
  1684. }
  1685. if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
  1686. (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
  1687. signal_type = stv0900_dvbs1_acq_workaround(fe);
  1688. return signal_type;
  1689. }