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/drivers/media/dvb/dvb-usb/af9005.h

https://bitbucket.org/abioy/linux
C Header | 3496 lines | 3429 code | 37 blank | 30 comment | 0 complexity | cef962f98f5af4cceb8a01d2fd22e738 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* Common header-file of the Linux driver for the Afatech 9005
  2. * USB1.1 DVB-T receiver.
  3. *
  4. * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
  5. *
  6. * Thanks to Afatech who kindly provided information.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * see Documentation/dvb/README.dvb-usb for more information
  23. */
  24. #ifndef _DVB_USB_AF9005_H_
  25. #define _DVB_USB_AF9005_H_
  26. #define DVB_USB_LOG_PREFIX "af9005"
  27. #include "dvb-usb.h"
  28. extern int dvb_usb_af9005_debug;
  29. #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
  30. #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
  31. #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
  32. #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
  33. #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
  34. #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args)
  35. extern int dvb_usb_af9005_led;
  36. /* firmware */
  37. #define FW_BULKOUT_SIZE 250
  38. enum {
  39. FW_CONFIG,
  40. FW_CONFIRM,
  41. FW_BOOT
  42. };
  43. /* af9005 commands */
  44. #define AF9005_OFDM_REG 0
  45. #define AF9005_TUNER_REG 1
  46. #define AF9005_REGISTER_RW 0x20
  47. #define AF9005_REGISTER_RW_ACK 0x21
  48. #define AF9005_CMD_OFDM_REG 0x00
  49. #define AF9005_CMD_TUNER 0x80
  50. #define AF9005_CMD_BURST 0x02
  51. #define AF9005_CMD_AUTOINC 0x04
  52. #define AF9005_CMD_READ 0x00
  53. #define AF9005_CMD_WRITE 0x01
  54. /* af9005 registers */
  55. #define APO_REG_RESET 0xAEFF
  56. #define APO_REG_I2C_RW_CAN_TUNER 0xF000
  57. #define APO_REG_I2C_RW_SILICON_TUNER 0xF001
  58. #define APO_REG_GPIO_RW_SILICON_TUNER 0xFFFE /* also for OFSM */
  59. #define APO_REG_TRIGGER_OFSM 0xFFFF /* also for OFSM */
  60. /***********************************************************************
  61. * Apollo Registers from VLSI *
  62. ***********************************************************************/
  63. #define xd_p_reg_aagc_inverted_agc 0xA000
  64. #define reg_aagc_inverted_agc_pos 0
  65. #define reg_aagc_inverted_agc_len 1
  66. #define reg_aagc_inverted_agc_lsb 0
  67. #define xd_p_reg_aagc_sign_only 0xA000
  68. #define reg_aagc_sign_only_pos 1
  69. #define reg_aagc_sign_only_len 1
  70. #define reg_aagc_sign_only_lsb 0
  71. #define xd_p_reg_aagc_slow_adc_en 0xA000
  72. #define reg_aagc_slow_adc_en_pos 2
  73. #define reg_aagc_slow_adc_en_len 1
  74. #define reg_aagc_slow_adc_en_lsb 0
  75. #define xd_p_reg_aagc_slow_adc_scale 0xA000
  76. #define reg_aagc_slow_adc_scale_pos 3
  77. #define reg_aagc_slow_adc_scale_len 5
  78. #define reg_aagc_slow_adc_scale_lsb 0
  79. #define xd_p_reg_aagc_check_slow_adc_lock 0xA001
  80. #define reg_aagc_check_slow_adc_lock_pos 0
  81. #define reg_aagc_check_slow_adc_lock_len 1
  82. #define reg_aagc_check_slow_adc_lock_lsb 0
  83. #define xd_p_reg_aagc_init_control 0xA001
  84. #define reg_aagc_init_control_pos 1
  85. #define reg_aagc_init_control_len 1
  86. #define reg_aagc_init_control_lsb 0
  87. #define xd_p_reg_aagc_total_gain_sel 0xA001
  88. #define reg_aagc_total_gain_sel_pos 2
  89. #define reg_aagc_total_gain_sel_len 2
  90. #define reg_aagc_total_gain_sel_lsb 0
  91. #define xd_p_reg_aagc_out_inv 0xA001
  92. #define reg_aagc_out_inv_pos 5
  93. #define reg_aagc_out_inv_len 1
  94. #define reg_aagc_out_inv_lsb 0
  95. #define xd_p_reg_aagc_int_en 0xA001
  96. #define reg_aagc_int_en_pos 6
  97. #define reg_aagc_int_en_len 1
  98. #define reg_aagc_int_en_lsb 0
  99. #define xd_p_reg_aagc_lock_change_flag 0xA001
  100. #define reg_aagc_lock_change_flag_pos 7
  101. #define reg_aagc_lock_change_flag_len 1
  102. #define reg_aagc_lock_change_flag_lsb 0
  103. #define xd_p_reg_aagc_rf_loop_bw_scale_acquire 0xA002
  104. #define reg_aagc_rf_loop_bw_scale_acquire_pos 0
  105. #define reg_aagc_rf_loop_bw_scale_acquire_len 5
  106. #define reg_aagc_rf_loop_bw_scale_acquire_lsb 0
  107. #define xd_p_reg_aagc_rf_loop_bw_scale_track 0xA003
  108. #define reg_aagc_rf_loop_bw_scale_track_pos 0
  109. #define reg_aagc_rf_loop_bw_scale_track_len 5
  110. #define reg_aagc_rf_loop_bw_scale_track_lsb 0
  111. #define xd_p_reg_aagc_if_loop_bw_scale_acquire 0xA004
  112. #define reg_aagc_if_loop_bw_scale_acquire_pos 0
  113. #define reg_aagc_if_loop_bw_scale_acquire_len 5
  114. #define reg_aagc_if_loop_bw_scale_acquire_lsb 0
  115. #define xd_p_reg_aagc_if_loop_bw_scale_track 0xA005
  116. #define reg_aagc_if_loop_bw_scale_track_pos 0
  117. #define reg_aagc_if_loop_bw_scale_track_len 5
  118. #define reg_aagc_if_loop_bw_scale_track_lsb 0
  119. #define xd_p_reg_aagc_max_rf_agc_7_0 0xA006
  120. #define reg_aagc_max_rf_agc_7_0_pos 0
  121. #define reg_aagc_max_rf_agc_7_0_len 8
  122. #define reg_aagc_max_rf_agc_7_0_lsb 0
  123. #define xd_p_reg_aagc_max_rf_agc_9_8 0xA007
  124. #define reg_aagc_max_rf_agc_9_8_pos 0
  125. #define reg_aagc_max_rf_agc_9_8_len 2
  126. #define reg_aagc_max_rf_agc_9_8_lsb 8
  127. #define xd_p_reg_aagc_min_rf_agc_7_0 0xA008
  128. #define reg_aagc_min_rf_agc_7_0_pos 0
  129. #define reg_aagc_min_rf_agc_7_0_len 8
  130. #define reg_aagc_min_rf_agc_7_0_lsb 0
  131. #define xd_p_reg_aagc_min_rf_agc_9_8 0xA009
  132. #define reg_aagc_min_rf_agc_9_8_pos 0
  133. #define reg_aagc_min_rf_agc_9_8_len 2
  134. #define reg_aagc_min_rf_agc_9_8_lsb 8
  135. #define xd_p_reg_aagc_max_if_agc_7_0 0xA00A
  136. #define reg_aagc_max_if_agc_7_0_pos 0
  137. #define reg_aagc_max_if_agc_7_0_len 8
  138. #define reg_aagc_max_if_agc_7_0_lsb 0
  139. #define xd_p_reg_aagc_max_if_agc_9_8 0xA00B
  140. #define reg_aagc_max_if_agc_9_8_pos 0
  141. #define reg_aagc_max_if_agc_9_8_len 2
  142. #define reg_aagc_max_if_agc_9_8_lsb 8
  143. #define xd_p_reg_aagc_min_if_agc_7_0 0xA00C
  144. #define reg_aagc_min_if_agc_7_0_pos 0
  145. #define reg_aagc_min_if_agc_7_0_len 8
  146. #define reg_aagc_min_if_agc_7_0_lsb 0
  147. #define xd_p_reg_aagc_min_if_agc_9_8 0xA00D
  148. #define reg_aagc_min_if_agc_9_8_pos 0
  149. #define reg_aagc_min_if_agc_9_8_len 2
  150. #define reg_aagc_min_if_agc_9_8_lsb 8
  151. #define xd_p_reg_aagc_lock_sample_scale 0xA00E
  152. #define reg_aagc_lock_sample_scale_pos 0
  153. #define reg_aagc_lock_sample_scale_len 5
  154. #define reg_aagc_lock_sample_scale_lsb 0
  155. #define xd_p_reg_aagc_rf_agc_lock_scale_acquire 0xA00F
  156. #define reg_aagc_rf_agc_lock_scale_acquire_pos 0
  157. #define reg_aagc_rf_agc_lock_scale_acquire_len 3
  158. #define reg_aagc_rf_agc_lock_scale_acquire_lsb 0
  159. #define xd_p_reg_aagc_rf_agc_lock_scale_track 0xA00F
  160. #define reg_aagc_rf_agc_lock_scale_track_pos 3
  161. #define reg_aagc_rf_agc_lock_scale_track_len 3
  162. #define reg_aagc_rf_agc_lock_scale_track_lsb 0
  163. #define xd_p_reg_aagc_if_agc_lock_scale_acquire 0xA010
  164. #define reg_aagc_if_agc_lock_scale_acquire_pos 0
  165. #define reg_aagc_if_agc_lock_scale_acquire_len 3
  166. #define reg_aagc_if_agc_lock_scale_acquire_lsb 0
  167. #define xd_p_reg_aagc_if_agc_lock_scale_track 0xA010
  168. #define reg_aagc_if_agc_lock_scale_track_pos 3
  169. #define reg_aagc_if_agc_lock_scale_track_len 3
  170. #define reg_aagc_if_agc_lock_scale_track_lsb 0
  171. #define xd_p_reg_aagc_rf_top_numerator_7_0 0xA011
  172. #define reg_aagc_rf_top_numerator_7_0_pos 0
  173. #define reg_aagc_rf_top_numerator_7_0_len 8
  174. #define reg_aagc_rf_top_numerator_7_0_lsb 0
  175. #define xd_p_reg_aagc_rf_top_numerator_9_8 0xA012
  176. #define reg_aagc_rf_top_numerator_9_8_pos 0
  177. #define reg_aagc_rf_top_numerator_9_8_len 2
  178. #define reg_aagc_rf_top_numerator_9_8_lsb 8
  179. #define xd_p_reg_aagc_if_top_numerator_7_0 0xA013
  180. #define reg_aagc_if_top_numerator_7_0_pos 0
  181. #define reg_aagc_if_top_numerator_7_0_len 8
  182. #define reg_aagc_if_top_numerator_7_0_lsb 0
  183. #define xd_p_reg_aagc_if_top_numerator_9_8 0xA014
  184. #define reg_aagc_if_top_numerator_9_8_pos 0
  185. #define reg_aagc_if_top_numerator_9_8_len 2
  186. #define reg_aagc_if_top_numerator_9_8_lsb 8
  187. #define xd_p_reg_aagc_adc_out_desired_7_0 0xA015
  188. #define reg_aagc_adc_out_desired_7_0_pos 0
  189. #define reg_aagc_adc_out_desired_7_0_len 8
  190. #define reg_aagc_adc_out_desired_7_0_lsb 0
  191. #define xd_p_reg_aagc_adc_out_desired_8 0xA016
  192. #define reg_aagc_adc_out_desired_8_pos 0
  193. #define reg_aagc_adc_out_desired_8_len 1
  194. #define reg_aagc_adc_out_desired_8_lsb 0
  195. #define xd_p_reg_aagc_fixed_gain 0xA016
  196. #define reg_aagc_fixed_gain_pos 3
  197. #define reg_aagc_fixed_gain_len 1
  198. #define reg_aagc_fixed_gain_lsb 0
  199. #define xd_p_reg_aagc_lock_count_th 0xA016
  200. #define reg_aagc_lock_count_th_pos 4
  201. #define reg_aagc_lock_count_th_len 4
  202. #define reg_aagc_lock_count_th_lsb 0
  203. #define xd_p_reg_aagc_fixed_rf_agc_control_7_0 0xA017
  204. #define reg_aagc_fixed_rf_agc_control_7_0_pos 0
  205. #define reg_aagc_fixed_rf_agc_control_7_0_len 8
  206. #define reg_aagc_fixed_rf_agc_control_7_0_lsb 0
  207. #define xd_p_reg_aagc_fixed_rf_agc_control_15_8 0xA018
  208. #define reg_aagc_fixed_rf_agc_control_15_8_pos 0
  209. #define reg_aagc_fixed_rf_agc_control_15_8_len 8
  210. #define reg_aagc_fixed_rf_agc_control_15_8_lsb 8
  211. #define xd_p_reg_aagc_fixed_rf_agc_control_23_16 0xA019
  212. #define reg_aagc_fixed_rf_agc_control_23_16_pos 0
  213. #define reg_aagc_fixed_rf_agc_control_23_16_len 8
  214. #define reg_aagc_fixed_rf_agc_control_23_16_lsb 16
  215. #define xd_p_reg_aagc_fixed_rf_agc_control_30_24 0xA01A
  216. #define reg_aagc_fixed_rf_agc_control_30_24_pos 0
  217. #define reg_aagc_fixed_rf_agc_control_30_24_len 7
  218. #define reg_aagc_fixed_rf_agc_control_30_24_lsb 24
  219. #define xd_p_reg_aagc_fixed_if_agc_control_7_0 0xA01B
  220. #define reg_aagc_fixed_if_agc_control_7_0_pos 0
  221. #define reg_aagc_fixed_if_agc_control_7_0_len 8
  222. #define reg_aagc_fixed_if_agc_control_7_0_lsb 0
  223. #define xd_p_reg_aagc_fixed_if_agc_control_15_8 0xA01C
  224. #define reg_aagc_fixed_if_agc_control_15_8_pos 0
  225. #define reg_aagc_fixed_if_agc_control_15_8_len 8
  226. #define reg_aagc_fixed_if_agc_control_15_8_lsb 8
  227. #define xd_p_reg_aagc_fixed_if_agc_control_23_16 0xA01D
  228. #define reg_aagc_fixed_if_agc_control_23_16_pos 0
  229. #define reg_aagc_fixed_if_agc_control_23_16_len 8
  230. #define reg_aagc_fixed_if_agc_control_23_16_lsb 16
  231. #define xd_p_reg_aagc_fixed_if_agc_control_30_24 0xA01E
  232. #define reg_aagc_fixed_if_agc_control_30_24_pos 0
  233. #define reg_aagc_fixed_if_agc_control_30_24_len 7
  234. #define reg_aagc_fixed_if_agc_control_30_24_lsb 24
  235. #define xd_p_reg_aagc_rf_agc_unlock_numerator 0xA01F
  236. #define reg_aagc_rf_agc_unlock_numerator_pos 0
  237. #define reg_aagc_rf_agc_unlock_numerator_len 6
  238. #define reg_aagc_rf_agc_unlock_numerator_lsb 0
  239. #define xd_p_reg_aagc_if_agc_unlock_numerator 0xA020
  240. #define reg_aagc_if_agc_unlock_numerator_pos 0
  241. #define reg_aagc_if_agc_unlock_numerator_len 6
  242. #define reg_aagc_if_agc_unlock_numerator_lsb 0
  243. #define xd_p_reg_unplug_th 0xA021
  244. #define reg_unplug_th_pos 0
  245. #define reg_unplug_th_len 8
  246. #define reg_aagc_rf_x0_lsb 0
  247. #define xd_p_reg_weak_signal_rfagc_thr 0xA022
  248. #define reg_weak_signal_rfagc_thr_pos 0
  249. #define reg_weak_signal_rfagc_thr_len 8
  250. #define reg_weak_signal_rfagc_thr_lsb 0
  251. #define xd_p_reg_unplug_rf_gain_th 0xA023
  252. #define reg_unplug_rf_gain_th_pos 0
  253. #define reg_unplug_rf_gain_th_len 8
  254. #define reg_unplug_rf_gain_th_lsb 0
  255. #define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
  256. #define reg_unplug_dtop_rf_gain_th_pos 0
  257. #define reg_unplug_dtop_rf_gain_th_len 8
  258. #define reg_unplug_dtop_rf_gain_th_lsb 0
  259. #define xd_p_reg_unplug_dtop_if_gain_th 0xA025
  260. #define reg_unplug_dtop_if_gain_th_pos 0
  261. #define reg_unplug_dtop_if_gain_th_len 8
  262. #define reg_unplug_dtop_if_gain_th_lsb 0
  263. #define xd_p_reg_top_recover_at_unplug_en 0xA026
  264. #define reg_top_recover_at_unplug_en_pos 0
  265. #define reg_top_recover_at_unplug_en_len 1
  266. #define reg_top_recover_at_unplug_en_lsb 0
  267. #define xd_p_reg_aagc_rf_x6 0xA027
  268. #define reg_aagc_rf_x6_pos 0
  269. #define reg_aagc_rf_x6_len 8
  270. #define reg_aagc_rf_x6_lsb 0
  271. #define xd_p_reg_aagc_rf_x7 0xA028
  272. #define reg_aagc_rf_x7_pos 0
  273. #define reg_aagc_rf_x7_len 8
  274. #define reg_aagc_rf_x7_lsb 0
  275. #define xd_p_reg_aagc_rf_x8 0xA029
  276. #define reg_aagc_rf_x8_pos 0
  277. #define reg_aagc_rf_x8_len 8
  278. #define reg_aagc_rf_x8_lsb 0
  279. #define xd_p_reg_aagc_rf_x9 0xA02A
  280. #define reg_aagc_rf_x9_pos 0
  281. #define reg_aagc_rf_x9_len 8
  282. #define reg_aagc_rf_x9_lsb 0
  283. #define xd_p_reg_aagc_rf_x10 0xA02B
  284. #define reg_aagc_rf_x10_pos 0
  285. #define reg_aagc_rf_x10_len 8
  286. #define reg_aagc_rf_x10_lsb 0
  287. #define xd_p_reg_aagc_rf_x11 0xA02C
  288. #define reg_aagc_rf_x11_pos 0
  289. #define reg_aagc_rf_x11_len 8
  290. #define reg_aagc_rf_x11_lsb 0
  291. #define xd_p_reg_aagc_rf_x12 0xA02D
  292. #define reg_aagc_rf_x12_pos 0
  293. #define reg_aagc_rf_x12_len 8
  294. #define reg_aagc_rf_x12_lsb 0
  295. #define xd_p_reg_aagc_rf_x13 0xA02E
  296. #define reg_aagc_rf_x13_pos 0
  297. #define reg_aagc_rf_x13_len 8
  298. #define reg_aagc_rf_x13_lsb 0
  299. #define xd_p_reg_aagc_if_x0 0xA02F
  300. #define reg_aagc_if_x0_pos 0
  301. #define reg_aagc_if_x0_len 8
  302. #define reg_aagc_if_x0_lsb 0
  303. #define xd_p_reg_aagc_if_x1 0xA030
  304. #define reg_aagc_if_x1_pos 0
  305. #define reg_aagc_if_x1_len 8
  306. #define reg_aagc_if_x1_lsb 0
  307. #define xd_p_reg_aagc_if_x2 0xA031
  308. #define reg_aagc_if_x2_pos 0
  309. #define reg_aagc_if_x2_len 8
  310. #define reg_aagc_if_x2_lsb 0
  311. #define xd_p_reg_aagc_if_x3 0xA032
  312. #define reg_aagc_if_x3_pos 0
  313. #define reg_aagc_if_x3_len 8
  314. #define reg_aagc_if_x3_lsb 0
  315. #define xd_p_reg_aagc_if_x4 0xA033
  316. #define reg_aagc_if_x4_pos 0
  317. #define reg_aagc_if_x4_len 8
  318. #define reg_aagc_if_x4_lsb 0
  319. #define xd_p_reg_aagc_if_x5 0xA034
  320. #define reg_aagc_if_x5_pos 0
  321. #define reg_aagc_if_x5_len 8
  322. #define reg_aagc_if_x5_lsb 0
  323. #define xd_p_reg_aagc_if_x6 0xA035
  324. #define reg_aagc_if_x6_pos 0
  325. #define reg_aagc_if_x6_len 8
  326. #define reg_aagc_if_x6_lsb 0
  327. #define xd_p_reg_aagc_if_x7 0xA036
  328. #define reg_aagc_if_x7_pos 0
  329. #define reg_aagc_if_x7_len 8
  330. #define reg_aagc_if_x7_lsb 0
  331. #define xd_p_reg_aagc_if_x8 0xA037
  332. #define reg_aagc_if_x8_pos 0
  333. #define reg_aagc_if_x8_len 8
  334. #define reg_aagc_if_x8_lsb 0
  335. #define xd_p_reg_aagc_if_x9 0xA038
  336. #define reg_aagc_if_x9_pos 0
  337. #define reg_aagc_if_x9_len 8
  338. #define reg_aagc_if_x9_lsb 0
  339. #define xd_p_reg_aagc_if_x10 0xA039
  340. #define reg_aagc_if_x10_pos 0
  341. #define reg_aagc_if_x10_len 8
  342. #define reg_aagc_if_x10_lsb 0
  343. #define xd_p_reg_aagc_if_x11 0xA03A
  344. #define reg_aagc_if_x11_pos 0
  345. #define reg_aagc_if_x11_len 8
  346. #define reg_aagc_if_x11_lsb 0
  347. #define xd_p_reg_aagc_if_x12 0xA03B
  348. #define reg_aagc_if_x12_pos 0
  349. #define reg_aagc_if_x12_len 8
  350. #define reg_aagc_if_x12_lsb 0
  351. #define xd_p_reg_aagc_if_x13 0xA03C
  352. #define reg_aagc_if_x13_pos 0
  353. #define reg_aagc_if_x13_len 8
  354. #define reg_aagc_if_x13_lsb 0
  355. #define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca 0xA03D
  356. #define reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
  357. #define reg_aagc_min_rf_ctl_8bit_for_dca_len 8
  358. #define reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
  359. #define xd_p_reg_aagc_min_if_ctl_8bit_for_dca 0xA03E
  360. #define reg_aagc_min_if_ctl_8bit_for_dca_pos 0
  361. #define reg_aagc_min_if_ctl_8bit_for_dca_len 8
  362. #define reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
  363. #define xd_r_reg_aagc_total_gain_7_0 0xA070
  364. #define reg_aagc_total_gain_7_0_pos 0
  365. #define reg_aagc_total_gain_7_0_len 8
  366. #define reg_aagc_total_gain_7_0_lsb 0
  367. #define xd_r_reg_aagc_total_gain_15_8 0xA071
  368. #define reg_aagc_total_gain_15_8_pos 0
  369. #define reg_aagc_total_gain_15_8_len 8
  370. #define reg_aagc_total_gain_15_8_lsb 8
  371. #define xd_p_reg_aagc_in_sat_cnt_7_0 0xA074
  372. #define reg_aagc_in_sat_cnt_7_0_pos 0
  373. #define reg_aagc_in_sat_cnt_7_0_len 8
  374. #define reg_aagc_in_sat_cnt_7_0_lsb 0
  375. #define xd_p_reg_aagc_in_sat_cnt_15_8 0xA075
  376. #define reg_aagc_in_sat_cnt_15_8_pos 0
  377. #define reg_aagc_in_sat_cnt_15_8_len 8
  378. #define reg_aagc_in_sat_cnt_15_8_lsb 8
  379. #define xd_p_reg_aagc_in_sat_cnt_23_16 0xA076
  380. #define reg_aagc_in_sat_cnt_23_16_pos 0
  381. #define reg_aagc_in_sat_cnt_23_16_len 8
  382. #define reg_aagc_in_sat_cnt_23_16_lsb 16
  383. #define xd_p_reg_aagc_in_sat_cnt_31_24 0xA077
  384. #define reg_aagc_in_sat_cnt_31_24_pos 0
  385. #define reg_aagc_in_sat_cnt_31_24_len 8
  386. #define reg_aagc_in_sat_cnt_31_24_lsb 24
  387. #define xd_r_reg_aagc_digital_rf_volt_7_0 0xA078
  388. #define reg_aagc_digital_rf_volt_7_0_pos 0
  389. #define reg_aagc_digital_rf_volt_7_0_len 8
  390. #define reg_aagc_digital_rf_volt_7_0_lsb 0
  391. #define xd_r_reg_aagc_digital_rf_volt_9_8 0xA079
  392. #define reg_aagc_digital_rf_volt_9_8_pos 0
  393. #define reg_aagc_digital_rf_volt_9_8_len 2
  394. #define reg_aagc_digital_rf_volt_9_8_lsb 8
  395. #define xd_r_reg_aagc_digital_if_volt_7_0 0xA07A
  396. #define reg_aagc_digital_if_volt_7_0_pos 0
  397. #define reg_aagc_digital_if_volt_7_0_len 8
  398. #define reg_aagc_digital_if_volt_7_0_lsb 0
  399. #define xd_r_reg_aagc_digital_if_volt_9_8 0xA07B
  400. #define reg_aagc_digital_if_volt_9_8_pos 0
  401. #define reg_aagc_digital_if_volt_9_8_len 2
  402. #define reg_aagc_digital_if_volt_9_8_lsb 8
  403. #define xd_r_reg_aagc_rf_gain 0xA07C
  404. #define reg_aagc_rf_gain_pos 0
  405. #define reg_aagc_rf_gain_len 8
  406. #define reg_aagc_rf_gain_lsb 0
  407. #define xd_r_reg_aagc_if_gain 0xA07D
  408. #define reg_aagc_if_gain_pos 0
  409. #define reg_aagc_if_gain_len 8
  410. #define reg_aagc_if_gain_lsb 0
  411. #define xd_p_tinr_imp_indicator 0xA080
  412. #define tinr_imp_indicator_pos 0
  413. #define tinr_imp_indicator_len 2
  414. #define tinr_imp_indicator_lsb 0
  415. #define xd_p_reg_tinr_fifo_size 0xA080
  416. #define reg_tinr_fifo_size_pos 2
  417. #define reg_tinr_fifo_size_len 5
  418. #define reg_tinr_fifo_size_lsb 0
  419. #define xd_p_reg_tinr_saturation_cnt_th 0xA081
  420. #define reg_tinr_saturation_cnt_th_pos 0
  421. #define reg_tinr_saturation_cnt_th_len 4
  422. #define reg_tinr_saturation_cnt_th_lsb 0
  423. #define xd_p_reg_tinr_saturation_th_3_0 0xA081
  424. #define reg_tinr_saturation_th_3_0_pos 4
  425. #define reg_tinr_saturation_th_3_0_len 4
  426. #define reg_tinr_saturation_th_3_0_lsb 0
  427. #define xd_p_reg_tinr_saturation_th_8_4 0xA082
  428. #define reg_tinr_saturation_th_8_4_pos 0
  429. #define reg_tinr_saturation_th_8_4_len 5
  430. #define reg_tinr_saturation_th_8_4_lsb 4
  431. #define xd_p_reg_tinr_imp_duration_th_2k_7_0 0xA083
  432. #define reg_tinr_imp_duration_th_2k_7_0_pos 0
  433. #define reg_tinr_imp_duration_th_2k_7_0_len 8
  434. #define reg_tinr_imp_duration_th_2k_7_0_lsb 0
  435. #define xd_p_reg_tinr_imp_duration_th_2k_8 0xA084
  436. #define reg_tinr_imp_duration_th_2k_8_pos 0
  437. #define reg_tinr_imp_duration_th_2k_8_len 1
  438. #define reg_tinr_imp_duration_th_2k_8_lsb 0
  439. #define xd_p_reg_tinr_imp_duration_th_8k_7_0 0xA085
  440. #define reg_tinr_imp_duration_th_8k_7_0_pos 0
  441. #define reg_tinr_imp_duration_th_8k_7_0_len 8
  442. #define reg_tinr_imp_duration_th_8k_7_0_lsb 0
  443. #define xd_p_reg_tinr_imp_duration_th_8k_10_8 0xA086
  444. #define reg_tinr_imp_duration_th_8k_10_8_pos 0
  445. #define reg_tinr_imp_duration_th_8k_10_8_len 3
  446. #define reg_tinr_imp_duration_th_8k_10_8_lsb 8
  447. #define xd_p_reg_tinr_freq_ratio_6m_7_0 0xA087
  448. #define reg_tinr_freq_ratio_6m_7_0_pos 0
  449. #define reg_tinr_freq_ratio_6m_7_0_len 8
  450. #define reg_tinr_freq_ratio_6m_7_0_lsb 0
  451. #define xd_p_reg_tinr_freq_ratio_6m_12_8 0xA088
  452. #define reg_tinr_freq_ratio_6m_12_8_pos 0
  453. #define reg_tinr_freq_ratio_6m_12_8_len 5
  454. #define reg_tinr_freq_ratio_6m_12_8_lsb 8
  455. #define xd_p_reg_tinr_freq_ratio_7m_7_0 0xA089
  456. #define reg_tinr_freq_ratio_7m_7_0_pos 0
  457. #define reg_tinr_freq_ratio_7m_7_0_len 8
  458. #define reg_tinr_freq_ratio_7m_7_0_lsb 0
  459. #define xd_p_reg_tinr_freq_ratio_7m_12_8 0xA08A
  460. #define reg_tinr_freq_ratio_7m_12_8_pos 0
  461. #define reg_tinr_freq_ratio_7m_12_8_len 5
  462. #define reg_tinr_freq_ratio_7m_12_8_lsb 8
  463. #define xd_p_reg_tinr_freq_ratio_8m_7_0 0xA08B
  464. #define reg_tinr_freq_ratio_8m_7_0_pos 0
  465. #define reg_tinr_freq_ratio_8m_7_0_len 8
  466. #define reg_tinr_freq_ratio_8m_7_0_lsb 0
  467. #define xd_p_reg_tinr_freq_ratio_8m_12_8 0xA08C
  468. #define reg_tinr_freq_ratio_8m_12_8_pos 0
  469. #define reg_tinr_freq_ratio_8m_12_8_len 5
  470. #define reg_tinr_freq_ratio_8m_12_8_lsb 8
  471. #define xd_p_reg_tinr_imp_duration_th_low_2k 0xA08D
  472. #define reg_tinr_imp_duration_th_low_2k_pos 0
  473. #define reg_tinr_imp_duration_th_low_2k_len 8
  474. #define reg_tinr_imp_duration_th_low_2k_lsb 0
  475. #define xd_p_reg_tinr_imp_duration_th_low_8k 0xA08E
  476. #define reg_tinr_imp_duration_th_low_8k_pos 0
  477. #define reg_tinr_imp_duration_th_low_8k_len 8
  478. #define reg_tinr_imp_duration_th_low_8k_lsb 0
  479. #define xd_r_reg_tinr_counter_7_0 0xA090
  480. #define reg_tinr_counter_7_0_pos 0
  481. #define reg_tinr_counter_7_0_len 8
  482. #define reg_tinr_counter_7_0_lsb 0
  483. #define xd_r_reg_tinr_counter_15_8 0xA091
  484. #define reg_tinr_counter_15_8_pos 0
  485. #define reg_tinr_counter_15_8_len 8
  486. #define reg_tinr_counter_15_8_lsb 8
  487. #define xd_p_reg_tinr_adative_tinr_en 0xA093
  488. #define reg_tinr_adative_tinr_en_pos 0
  489. #define reg_tinr_adative_tinr_en_len 1
  490. #define reg_tinr_adative_tinr_en_lsb 0
  491. #define xd_p_reg_tinr_peak_fifo_size 0xA093
  492. #define reg_tinr_peak_fifo_size_pos 1
  493. #define reg_tinr_peak_fifo_size_len 5
  494. #define reg_tinr_peak_fifo_size_lsb 0
  495. #define xd_p_reg_tinr_counter_rst 0xA093
  496. #define reg_tinr_counter_rst_pos 6
  497. #define reg_tinr_counter_rst_len 1
  498. #define reg_tinr_counter_rst_lsb 0
  499. #define xd_p_reg_tinr_search_period_7_0 0xA094
  500. #define reg_tinr_search_period_7_0_pos 0
  501. #define reg_tinr_search_period_7_0_len 8
  502. #define reg_tinr_search_period_7_0_lsb 0
  503. #define xd_p_reg_tinr_search_period_15_8 0xA095
  504. #define reg_tinr_search_period_15_8_pos 0
  505. #define reg_tinr_search_period_15_8_len 8
  506. #define reg_tinr_search_period_15_8_lsb 8
  507. #define xd_p_reg_ccifs_fcw_7_0 0xA0A0
  508. #define reg_ccifs_fcw_7_0_pos 0
  509. #define reg_ccifs_fcw_7_0_len 8
  510. #define reg_ccifs_fcw_7_0_lsb 0
  511. #define xd_p_reg_ccifs_fcw_12_8 0xA0A1
  512. #define reg_ccifs_fcw_12_8_pos 0
  513. #define reg_ccifs_fcw_12_8_len 5
  514. #define reg_ccifs_fcw_12_8_lsb 8
  515. #define xd_p_reg_ccifs_spec_inv 0xA0A1
  516. #define reg_ccifs_spec_inv_pos 5
  517. #define reg_ccifs_spec_inv_len 1
  518. #define reg_ccifs_spec_inv_lsb 0
  519. #define xd_p_reg_gp_trigger 0xA0A2
  520. #define reg_gp_trigger_pos 0
  521. #define reg_gp_trigger_len 1
  522. #define reg_gp_trigger_lsb 0
  523. #define xd_p_reg_trigger_sel 0xA0A2
  524. #define reg_trigger_sel_pos 1
  525. #define reg_trigger_sel_len 2
  526. #define reg_trigger_sel_lsb 0
  527. #define xd_p_reg_debug_ofdm 0xA0A2
  528. #define reg_debug_ofdm_pos 3
  529. #define reg_debug_ofdm_len 2
  530. #define reg_debug_ofdm_lsb 0
  531. #define xd_p_reg_trigger_module_sel 0xA0A3
  532. #define reg_trigger_module_sel_pos 0
  533. #define reg_trigger_module_sel_len 6
  534. #define reg_trigger_module_sel_lsb 0
  535. #define xd_p_reg_trigger_set_sel 0xA0A4
  536. #define reg_trigger_set_sel_pos 0
  537. #define reg_trigger_set_sel_len 6
  538. #define reg_trigger_set_sel_lsb 0
  539. #define xd_p_reg_fw_int_mask_n 0xA0A4
  540. #define reg_fw_int_mask_n_pos 6
  541. #define reg_fw_int_mask_n_len 1
  542. #define reg_fw_int_mask_n_lsb 0
  543. #define xd_p_reg_debug_group 0xA0A5
  544. #define reg_debug_group_pos 0
  545. #define reg_debug_group_len 4
  546. #define reg_debug_group_lsb 0
  547. #define xd_p_reg_odbg_clk_sel 0xA0A5
  548. #define reg_odbg_clk_sel_pos 4
  549. #define reg_odbg_clk_sel_len 2
  550. #define reg_odbg_clk_sel_lsb 0
  551. #define xd_p_reg_ccif_sc 0xA0C0
  552. #define reg_ccif_sc_pos 0
  553. #define reg_ccif_sc_len 4
  554. #define reg_ccif_sc_lsb 0
  555. #define xd_r_reg_ccif_saturate 0xA0C1
  556. #define reg_ccif_saturate_pos 0
  557. #define reg_ccif_saturate_len 2
  558. #define reg_ccif_saturate_lsb 0
  559. #define xd_r_reg_antif_saturate 0xA0C1
  560. #define reg_antif_saturate_pos 2
  561. #define reg_antif_saturate_len 4
  562. #define reg_antif_saturate_lsb 0
  563. #define xd_r_reg_acif_saturate 0xA0C2
  564. #define reg_acif_saturate_pos 0
  565. #define reg_acif_saturate_len 8
  566. #define reg_acif_saturate_lsb 0
  567. #define xd_p_reg_tmr_timer0_threshold_7_0 0xA0C8
  568. #define reg_tmr_timer0_threshold_7_0_pos 0
  569. #define reg_tmr_timer0_threshold_7_0_len 8
  570. #define reg_tmr_timer0_threshold_7_0_lsb 0
  571. #define xd_p_reg_tmr_timer0_threshold_15_8 0xA0C9
  572. #define reg_tmr_timer0_threshold_15_8_pos 0
  573. #define reg_tmr_timer0_threshold_15_8_len 8
  574. #define reg_tmr_timer0_threshold_15_8_lsb 8
  575. #define xd_p_reg_tmr_timer0_enable 0xA0CA
  576. #define reg_tmr_timer0_enable_pos 0
  577. #define reg_tmr_timer0_enable_len 1
  578. #define reg_tmr_timer0_enable_lsb 0
  579. #define xd_p_reg_tmr_timer0_clk_sel 0xA0CA
  580. #define reg_tmr_timer0_clk_sel_pos 1
  581. #define reg_tmr_timer0_clk_sel_len 1
  582. #define reg_tmr_timer0_clk_sel_lsb 0
  583. #define xd_p_reg_tmr_timer0_int 0xA0CA
  584. #define reg_tmr_timer0_int_pos 2
  585. #define reg_tmr_timer0_int_len 1
  586. #define reg_tmr_timer0_int_lsb 0
  587. #define xd_p_reg_tmr_timer0_rst 0xA0CA
  588. #define reg_tmr_timer0_rst_pos 3
  589. #define reg_tmr_timer0_rst_len 1
  590. #define reg_tmr_timer0_rst_lsb 0
  591. #define xd_r_reg_tmr_timer0_count_7_0 0xA0CB
  592. #define reg_tmr_timer0_count_7_0_pos 0
  593. #define reg_tmr_timer0_count_7_0_len 8
  594. #define reg_tmr_timer0_count_7_0_lsb 0
  595. #define xd_r_reg_tmr_timer0_count_15_8 0xA0CC
  596. #define reg_tmr_timer0_count_15_8_pos 0
  597. #define reg_tmr_timer0_count_15_8_len 8
  598. #define reg_tmr_timer0_count_15_8_lsb 8
  599. #define xd_p_reg_suspend 0xA0CD
  600. #define reg_suspend_pos 0
  601. #define reg_suspend_len 1
  602. #define reg_suspend_lsb 0
  603. #define xd_p_reg_suspend_rdy 0xA0CD
  604. #define reg_suspend_rdy_pos 1
  605. #define reg_suspend_rdy_len 1
  606. #define reg_suspend_rdy_lsb 0
  607. #define xd_p_reg_resume 0xA0CD
  608. #define reg_resume_pos 2
  609. #define reg_resume_len 1
  610. #define reg_resume_lsb 0
  611. #define xd_p_reg_resume_rdy 0xA0CD
  612. #define reg_resume_rdy_pos 3
  613. #define reg_resume_rdy_len 1
  614. #define reg_resume_rdy_lsb 0
  615. #define xd_p_reg_fmf 0xA0CE
  616. #define reg_fmf_pos 0
  617. #define reg_fmf_len 8
  618. #define reg_fmf_lsb 0
  619. #define xd_p_ccid_accumulate_num_2k_7_0 0xA100
  620. #define ccid_accumulate_num_2k_7_0_pos 0
  621. #define ccid_accumulate_num_2k_7_0_len 8
  622. #define ccid_accumulate_num_2k_7_0_lsb 0
  623. #define xd_p_ccid_accumulate_num_2k_12_8 0xA101
  624. #define ccid_accumulate_num_2k_12_8_pos 0
  625. #define ccid_accumulate_num_2k_12_8_len 5
  626. #define ccid_accumulate_num_2k_12_8_lsb 8
  627. #define xd_p_ccid_accumulate_num_8k_7_0 0xA102
  628. #define ccid_accumulate_num_8k_7_0_pos 0
  629. #define ccid_accumulate_num_8k_7_0_len 8
  630. #define ccid_accumulate_num_8k_7_0_lsb 0
  631. #define xd_p_ccid_accumulate_num_8k_14_8 0xA103
  632. #define ccid_accumulate_num_8k_14_8_pos 0
  633. #define ccid_accumulate_num_8k_14_8_len 7
  634. #define ccid_accumulate_num_8k_14_8_lsb 8
  635. #define xd_p_ccid_desired_level_0 0xA103
  636. #define ccid_desired_level_0_pos 7
  637. #define ccid_desired_level_0_len 1
  638. #define ccid_desired_level_0_lsb 0
  639. #define xd_p_ccid_desired_level_8_1 0xA104
  640. #define ccid_desired_level_8_1_pos 0
  641. #define ccid_desired_level_8_1_len 8
  642. #define ccid_desired_level_8_1_lsb 1
  643. #define xd_p_ccid_apply_delay 0xA105
  644. #define ccid_apply_delay_pos 0
  645. #define ccid_apply_delay_len 7
  646. #define ccid_apply_delay_lsb 0
  647. #define xd_p_ccid_CCID_Threshold1 0xA106
  648. #define ccid_CCID_Threshold1_pos 0
  649. #define ccid_CCID_Threshold1_len 8
  650. #define ccid_CCID_Threshold1_lsb 0
  651. #define xd_p_ccid_CCID_Threshold2 0xA107
  652. #define ccid_CCID_Threshold2_pos 0
  653. #define ccid_CCID_Threshold2_len 8
  654. #define ccid_CCID_Threshold2_lsb 0
  655. #define xd_p_reg_ccid_gain_scale 0xA108
  656. #define reg_ccid_gain_scale_pos 0
  657. #define reg_ccid_gain_scale_len 4
  658. #define reg_ccid_gain_scale_lsb 0
  659. #define xd_p_reg_ccid2_passband_gain_set 0xA108
  660. #define reg_ccid2_passband_gain_set_pos 4
  661. #define reg_ccid2_passband_gain_set_len 4
  662. #define reg_ccid2_passband_gain_set_lsb 0
  663. #define xd_r_ccid_multiplier_7_0 0xA109
  664. #define ccid_multiplier_7_0_pos 0
  665. #define ccid_multiplier_7_0_len 8
  666. #define ccid_multiplier_7_0_lsb 0
  667. #define xd_r_ccid_multiplier_15_8 0xA10A
  668. #define ccid_multiplier_15_8_pos 0
  669. #define ccid_multiplier_15_8_len 8
  670. #define ccid_multiplier_15_8_lsb 8
  671. #define xd_r_ccid_right_shift_bits 0xA10B
  672. #define ccid_right_shift_bits_pos 0
  673. #define ccid_right_shift_bits_len 4
  674. #define ccid_right_shift_bits_lsb 0
  675. #define xd_r_reg_ccid_sx_7_0 0xA10C
  676. #define reg_ccid_sx_7_0_pos 0
  677. #define reg_ccid_sx_7_0_len 8
  678. #define reg_ccid_sx_7_0_lsb 0
  679. #define xd_r_reg_ccid_sx_15_8 0xA10D
  680. #define reg_ccid_sx_15_8_pos 0
  681. #define reg_ccid_sx_15_8_len 8
  682. #define reg_ccid_sx_15_8_lsb 8
  683. #define xd_r_reg_ccid_sx_21_16 0xA10E
  684. #define reg_ccid_sx_21_16_pos 0
  685. #define reg_ccid_sx_21_16_len 6
  686. #define reg_ccid_sx_21_16_lsb 16
  687. #define xd_r_reg_ccid_sy_7_0 0xA110
  688. #define reg_ccid_sy_7_0_pos 0
  689. #define reg_ccid_sy_7_0_len 8
  690. #define reg_ccid_sy_7_0_lsb 0
  691. #define xd_r_reg_ccid_sy_15_8 0xA111
  692. #define reg_ccid_sy_15_8_pos 0
  693. #define reg_ccid_sy_15_8_len 8
  694. #define reg_ccid_sy_15_8_lsb 8
  695. #define xd_r_reg_ccid_sy_23_16 0xA112
  696. #define reg_ccid_sy_23_16_pos 0
  697. #define reg_ccid_sy_23_16_len 8
  698. #define reg_ccid_sy_23_16_lsb 16
  699. #define xd_r_reg_ccid2_sz_7_0 0xA114
  700. #define reg_ccid2_sz_7_0_pos 0
  701. #define reg_ccid2_sz_7_0_len 8
  702. #define reg_ccid2_sz_7_0_lsb 0
  703. #define xd_r_reg_ccid2_sz_15_8 0xA115
  704. #define reg_ccid2_sz_15_8_pos 0
  705. #define reg_ccid2_sz_15_8_len 8
  706. #define reg_ccid2_sz_15_8_lsb 8
  707. #define xd_r_reg_ccid2_sz_23_16 0xA116
  708. #define reg_ccid2_sz_23_16_pos 0
  709. #define reg_ccid2_sz_23_16_len 8
  710. #define reg_ccid2_sz_23_16_lsb 16
  711. #define xd_r_reg_ccid2_sz_25_24 0xA117
  712. #define reg_ccid2_sz_25_24_pos 0
  713. #define reg_ccid2_sz_25_24_len 2
  714. #define reg_ccid2_sz_25_24_lsb 24
  715. #define xd_r_reg_ccid2_sy_7_0 0xA118
  716. #define reg_ccid2_sy_7_0_pos 0
  717. #define reg_ccid2_sy_7_0_len 8
  718. #define reg_ccid2_sy_7_0_lsb 0
  719. #define xd_r_reg_ccid2_sy_15_8 0xA119
  720. #define reg_ccid2_sy_15_8_pos 0
  721. #define reg_ccid2_sy_15_8_len 8
  722. #define reg_ccid2_sy_15_8_lsb 8
  723. #define xd_r_reg_ccid2_sy_23_16 0xA11A
  724. #define reg_ccid2_sy_23_16_pos 0
  725. #define reg_ccid2_sy_23_16_len 8
  726. #define reg_ccid2_sy_23_16_lsb 16
  727. #define xd_r_reg_ccid2_sy_25_24 0xA11B
  728. #define reg_ccid2_sy_25_24_pos 0
  729. #define reg_ccid2_sy_25_24_len 2
  730. #define reg_ccid2_sy_25_24_lsb 24
  731. #define xd_p_dagc1_accumulate_num_2k_7_0 0xA120
  732. #define dagc1_accumulate_num_2k_7_0_pos 0
  733. #define dagc1_accumulate_num_2k_7_0_len 8
  734. #define dagc1_accumulate_num_2k_7_0_lsb 0
  735. #define xd_p_dagc1_accumulate_num_2k_12_8 0xA121
  736. #define dagc1_accumulate_num_2k_12_8_pos 0
  737. #define dagc1_accumulate_num_2k_12_8_len 5
  738. #define dagc1_accumulate_num_2k_12_8_lsb 8
  739. #define xd_p_dagc1_accumulate_num_8k_7_0 0xA122
  740. #define dagc1_accumulate_num_8k_7_0_pos 0
  741. #define dagc1_accumulate_num_8k_7_0_len 8
  742. #define dagc1_accumulate_num_8k_7_0_lsb 0
  743. #define xd_p_dagc1_accumulate_num_8k_14_8 0xA123
  744. #define dagc1_accumulate_num_8k_14_8_pos 0
  745. #define dagc1_accumulate_num_8k_14_8_len 7
  746. #define dagc1_accumulate_num_8k_14_8_lsb 8
  747. #define xd_p_dagc1_desired_level_0 0xA123
  748. #define dagc1_desired_level_0_pos 7
  749. #define dagc1_desired_level_0_len 1
  750. #define dagc1_desired_level_0_lsb 0
  751. #define xd_p_dagc1_desired_level_8_1 0xA124
  752. #define dagc1_desired_level_8_1_pos 0
  753. #define dagc1_desired_level_8_1_len 8
  754. #define dagc1_desired_level_8_1_lsb 1
  755. #define xd_p_dagc1_apply_delay 0xA125
  756. #define dagc1_apply_delay_pos 0
  757. #define dagc1_apply_delay_len 7
  758. #define dagc1_apply_delay_lsb 0
  759. #define xd_p_dagc1_bypass_scale_ctl 0xA126
  760. #define dagc1_bypass_scale_ctl_pos 0
  761. #define dagc1_bypass_scale_ctl_len 2
  762. #define dagc1_bypass_scale_ctl_lsb 0
  763. #define xd_p_reg_dagc1_in_sat_cnt_7_0 0xA127
  764. #define reg_dagc1_in_sat_cnt_7_0_pos 0
  765. #define reg_dagc1_in_sat_cnt_7_0_len 8
  766. #define reg_dagc1_in_sat_cnt_7_0_lsb 0
  767. #define xd_p_reg_dagc1_in_sat_cnt_15_8 0xA128
  768. #define reg_dagc1_in_sat_cnt_15_8_pos 0
  769. #define reg_dagc1_in_sat_cnt_15_8_len 8
  770. #define reg_dagc1_in_sat_cnt_15_8_lsb 8
  771. #define xd_p_reg_dagc1_in_sat_cnt_23_16 0xA129
  772. #define reg_dagc1_in_sat_cnt_23_16_pos 0
  773. #define reg_dagc1_in_sat_cnt_23_16_len 8
  774. #define reg_dagc1_in_sat_cnt_23_16_lsb 16
  775. #define xd_p_reg_dagc1_in_sat_cnt_31_24 0xA12A
  776. #define reg_dagc1_in_sat_cnt_31_24_pos 0
  777. #define reg_dagc1_in_sat_cnt_31_24_len 8
  778. #define reg_dagc1_in_sat_cnt_31_24_lsb 24
  779. #define xd_p_reg_dagc1_out_sat_cnt_7_0 0xA12B
  780. #define reg_dagc1_out_sat_cnt_7_0_pos 0
  781. #define reg_dagc1_out_sat_cnt_7_0_len 8
  782. #define reg_dagc1_out_sat_cnt_7_0_lsb 0
  783. #define xd_p_reg_dagc1_out_sat_cnt_15_8 0xA12C
  784. #define reg_dagc1_out_sat_cnt_15_8_pos 0
  785. #define reg_dagc1_out_sat_cnt_15_8_len 8
  786. #define reg_dagc1_out_sat_cnt_15_8_lsb 8
  787. #define xd_p_reg_dagc1_out_sat_cnt_23_16 0xA12D
  788. #define reg_dagc1_out_sat_cnt_23_16_pos 0
  789. #define reg_dagc1_out_sat_cnt_23_16_len 8
  790. #define reg_dagc1_out_sat_cnt_23_16_lsb 16
  791. #define xd_p_reg_dagc1_out_sat_cnt_31_24 0xA12E
  792. #define reg_dagc1_out_sat_cnt_31_24_pos 0
  793. #define reg_dagc1_out_sat_cnt_31_24_len 8
  794. #define reg_dagc1_out_sat_cnt_31_24_lsb 24
  795. #define xd_r_dagc1_multiplier_7_0 0xA136
  796. #define dagc1_multiplier_7_0_pos 0
  797. #define dagc1_multiplier_7_0_len 8
  798. #define dagc1_multiplier_7_0_lsb 0
  799. #define xd_r_dagc1_multiplier_15_8 0xA137
  800. #define dagc1_multiplier_15_8_pos 0
  801. #define dagc1_multiplier_15_8_len 8
  802. #define dagc1_multiplier_15_8_lsb 8
  803. #define xd_r_dagc1_right_shift_bits 0xA138
  804. #define dagc1_right_shift_bits_pos 0
  805. #define dagc1_right_shift_bits_len 4
  806. #define dagc1_right_shift_bits_lsb 0
  807. #define xd_p_reg_bfs_fcw_7_0 0xA140
  808. #define reg_bfs_fcw_7_0_pos 0
  809. #define reg_bfs_fcw_7_0_len 8
  810. #define reg_bfs_fcw_7_0_lsb 0
  811. #define xd_p_reg_bfs_fcw_15_8 0xA141
  812. #define reg_bfs_fcw_15_8_pos 0
  813. #define reg_bfs_fcw_15_8_len 8
  814. #define reg_bfs_fcw_15_8_lsb 8
  815. #define xd_p_reg_bfs_fcw_22_16 0xA142
  816. #define reg_bfs_fcw_22_16_pos 0
  817. #define reg_bfs_fcw_22_16_len 7
  818. #define reg_bfs_fcw_22_16_lsb 16
  819. #define xd_p_reg_antif_sf_7_0 0xA144
  820. #define reg_antif_sf_7_0_pos 0
  821. #define reg_antif_sf_7_0_len 8
  822. #define reg_antif_sf_7_0_lsb 0
  823. #define xd_p_reg_antif_sf_11_8 0xA145
  824. #define reg_antif_sf_11_8_pos 0
  825. #define reg_antif_sf_11_8_len 4
  826. #define reg_antif_sf_11_8_lsb 8
  827. #define xd_r_bfs_fcw_q_7_0 0xA150
  828. #define bfs_fcw_q_7_0_pos 0
  829. #define bfs_fcw_q_7_0_len 8
  830. #define bfs_fcw_q_7_0_lsb 0
  831. #define xd_r_bfs_fcw_q_15_8 0xA151
  832. #define bfs_fcw_q_15_8_pos 0
  833. #define bfs_fcw_q_15_8_len 8
  834. #define bfs_fcw_q_15_8_lsb 8
  835. #define xd_r_bfs_fcw_q_22_16 0xA152
  836. #define bfs_fcw_q_22_16_pos 0
  837. #define bfs_fcw_q_22_16_len 7
  838. #define bfs_fcw_q_22_16_lsb 16
  839. #define xd_p_reg_dca_enu 0xA160
  840. #define reg_dca_enu_pos 0
  841. #define reg_dca_enu_len 1
  842. #define reg_dca_enu_lsb 0
  843. #define xd_p_reg_dca_enl 0xA160
  844. #define reg_dca_enl_pos 1
  845. #define reg_dca_enl_len 1
  846. #define reg_dca_enl_lsb 0
  847. #define xd_p_reg_dca_lower_chip 0xA160
  848. #define reg_dca_lower_chip_pos 2
  849. #define reg_dca_lower_chip_len 1
  850. #define reg_dca_lower_chip_lsb 0
  851. #define xd_p_reg_dca_upper_chip 0xA160
  852. #define reg_dca_upper_chip_pos 3
  853. #define reg_dca_upper_chip_len 1
  854. #define reg_dca_upper_chip_lsb 0
  855. #define xd_p_reg_dca_platch 0xA160
  856. #define reg_dca_platch_pos 4
  857. #define reg_dca_platch_len 1
  858. #define reg_dca_platch_lsb 0
  859. #define xd_p_reg_dca_th 0xA161
  860. #define reg_dca_th_pos 0
  861. #define reg_dca_th_len 5
  862. #define reg_dca_th_lsb 0
  863. #define xd_p_reg_dca_scale 0xA162
  864. #define reg_dca_scale_pos 0
  865. #define reg_dca_scale_len 4
  866. #define reg_dca_scale_lsb 0
  867. #define xd_p_reg_dca_tone_7_0 0xA163
  868. #define reg_dca_tone_7_0_pos 0
  869. #define reg_dca_tone_7_0_len 8
  870. #define reg_dca_tone_7_0_lsb 0
  871. #define xd_p_reg_dca_tone_12_8 0xA164
  872. #define reg_dca_tone_12_8_pos 0
  873. #define reg_dca_tone_12_8_len 5
  874. #define reg_dca_tone_12_8_lsb 8
  875. #define xd_p_reg_dca_time_7_0 0xA165
  876. #define reg_dca_time_7_0_pos 0
  877. #define reg_dca_time_7_0_len 8
  878. #define reg_dca_time_7_0_lsb 0
  879. #define xd_p_reg_dca_time_15_8 0xA166
  880. #define reg_dca_time_15_8_pos 0
  881. #define reg_dca_time_15_8_len 8
  882. #define reg_dca_time_15_8_lsb 8
  883. #define xd_r_dcasm 0xA167
  884. #define dcasm_pos 0
  885. #define dcasm_len 3
  886. #define dcasm_lsb 0
  887. #define xd_p_reg_qnt_valuew_7_0 0xA168
  888. #define reg_qnt_valuew_7_0_pos 0
  889. #define reg_qnt_valuew_7_0_len 8
  890. #define reg_qnt_valuew_7_0_lsb 0
  891. #define xd_p_reg_qnt_valuew_10_8 0xA169
  892. #define reg_qnt_valuew_10_8_pos 0
  893. #define reg_qnt_valuew_10_8_len 3
  894. #define reg_qnt_valuew_10_8_lsb 8
  895. #define xd_p_dca_sbx_gain_diff_7_0 0xA16A
  896. #define dca_sbx_gain_diff_7_0_pos 0
  897. #define dca_sbx_gain_diff_7_0_len 8
  898. #define dca_sbx_gain_diff_7_0_lsb 0
  899. #define xd_p_dca_sbx_gain_diff_9_8 0xA16B
  900. #define dca_sbx_gain_diff_9_8_pos 0
  901. #define dca_sbx_gain_diff_9_8_len 2
  902. #define dca_sbx_gain_diff_9_8_lsb 8
  903. #define xd_p_reg_dca_stand_alone 0xA16C
  904. #define reg_dca_stand_alone_pos 0
  905. #define reg_dca_stand_alone_len 1
  906. #define reg_dca_stand_alone_lsb 0
  907. #define xd_p_reg_dca_upper_out_en 0xA16C
  908. #define reg_dca_upper_out_en_pos 1
  909. #define reg_dca_upper_out_en_len 1
  910. #define reg_dca_upper_out_en_lsb 0
  911. #define xd_p_reg_dca_rc_en 0xA16C
  912. #define reg_dca_rc_en_pos 2
  913. #define reg_dca_rc_en_len 1
  914. #define reg_dca_rc_en_lsb 0
  915. #define xd_p_reg_dca_retrain_send 0xA16C
  916. #define reg_dca_retrain_send_pos 3
  917. #define reg_dca_retrain_send_len 1
  918. #define reg_dca_retrain_send_lsb 0
  919. #define xd_p_reg_dca_retrain_rec 0xA16C
  920. #define reg_dca_retrain_rec_pos 4
  921. #define reg_dca_retrain_rec_len 1
  922. #define reg_dca_retrain_rec_lsb 0
  923. #define xd_p_reg_dca_api_tpsrdy 0xA16C
  924. #define reg_dca_api_tpsrdy_pos 5
  925. #define reg_dca_api_tpsrdy_len 1
  926. #define reg_dca_api_tpsrdy_lsb 0
  927. #define xd_p_reg_dca_symbol_gap 0xA16D
  928. #define reg_dca_symbol_gap_pos 0
  929. #define reg_dca_symbol_gap_len 4
  930. #define reg_dca_symbol_gap_lsb 0
  931. #define xd_p_reg_qnt_nfvaluew_7_0 0xA16E
  932. #define reg_qnt_nfvaluew_7_0_pos 0
  933. #define reg_qnt_nfvaluew_7_0_len 8
  934. #define reg_qnt_nfvaluew_7_0_lsb 0
  935. #define xd_p_reg_qnt_nfvaluew_10_8 0xA16F
  936. #define reg_qnt_nfvaluew_10_8_pos 0
  937. #define reg_qnt_nfvaluew_10_8_len 3
  938. #define reg_qnt_nfvaluew_10_8_lsb 8
  939. #define xd_p_reg_qnt_flatness_thr_7_0 0xA170
  940. #define reg_qnt_flatness_thr_7_0_pos 0
  941. #define reg_qnt_flatness_thr_7_0_len 8
  942. #define reg_qnt_flatness_thr_7_0_lsb 0
  943. #define xd_p_reg_qnt_flatness_thr_9_8 0xA171
  944. #define reg_qnt_flatness_thr_9_8_pos 0
  945. #define reg_qnt_flatness_thr_9_8_len 2
  946. #define reg_qnt_flatness_thr_9_8_lsb 8
  947. #define xd_p_reg_dca_tone_idx_5_0 0xA171
  948. #define reg_dca_tone_idx_5_0_pos 2
  949. #define reg_dca_tone_idx_5_0_len 6
  950. #define reg_dca_tone_idx_5_0_lsb 0
  951. #define xd_p_reg_dca_tone_idx_12_6 0xA172
  952. #define reg_dca_tone_idx_12_6_pos 0
  953. #define reg_dca_tone_idx_12_6_len 7
  954. #define reg_dca_tone_idx_12_6_lsb 6
  955. #define xd_p_reg_dca_data_vld 0xA173
  956. #define reg_dca_data_vld_pos 0
  957. #define reg_dca_data_vld_len 1
  958. #define reg_dca_data_vld_lsb 0
  959. #define xd_p_reg_dca_read_update 0xA173
  960. #define reg_dca_read_update_pos 1
  961. #define reg_dca_read_update_len 1
  962. #define reg_dca_read_update_lsb 0
  963. #define xd_r_reg_dca_data_re_5_0 0xA173
  964. #define reg_dca_data_re_5_0_pos 2
  965. #define reg_dca_data_re_5_0_len 6
  966. #define reg_dca_data_re_5_0_lsb 0
  967. #define xd_r_reg_dca_data_re_10_6 0xA174
  968. #define reg_dca_data_re_10_6_pos 0
  969. #define reg_dca_data_re_10_6_len 5
  970. #define reg_dca_data_re_10_6_lsb 6
  971. #define xd_r_reg_dca_data_im_7_0 0xA175
  972. #define reg_dca_data_im_7_0_pos 0
  973. #define reg_dca_data_im_7_0_len 8
  974. #define reg_dca_data_im_7_0_lsb 0
  975. #define xd_r_reg_dca_data_im_10_8 0xA176
  976. #define reg_dca_data_im_10_8_pos 0
  977. #define reg_dca_data_im_10_8_len 3
  978. #define reg_dca_data_im_10_8_lsb 8
  979. #define xd_r_reg_dca_data_h2_7_0 0xA178
  980. #define reg_dca_data_h2_7_0_pos 0
  981. #define reg_dca_data_h2_7_0_len 8
  982. #define reg_dca_data_h2_7_0_lsb 0
  983. #define xd_r_reg_dca_data_h2_9_8 0xA179
  984. #define reg_dca_data_h2_9_8_pos 0
  985. #define reg_dca_data_h2_9_8_len 2
  986. #define reg_dca_data_h2_9_8_lsb 8
  987. #define xd_p_reg_f_adc_7_0 0xA180
  988. #define reg_f_adc_7_0_pos 0
  989. #define reg_f_adc_7_0_len 8
  990. #define reg_f_adc_7_0_lsb 0
  991. #define xd_p_reg_f_adc_15_8 0xA181
  992. #define reg_f_adc_15_8_pos 0
  993. #define reg_f_adc_15_8_len 8
  994. #define reg_f_adc_15_8_lsb 8
  995. #define xd_p_reg_f_adc_23_16 0xA182
  996. #define reg_f_adc_23_16_pos 0
  997. #define reg_f_adc_23_16_len 8
  998. #define reg_f_adc_23_16_lsb 16
  999. #define xd_r_intp_mu_7_0 0xA190
  1000. #define intp_mu_7_0_pos 0
  1001. #define intp_mu_7_0_len 8
  1002. #define intp_mu_7_0_lsb 0
  1003. #define xd_r_intp_mu_15_8 0xA191
  1004. #define intp_mu_15_8_pos 0
  1005. #define intp_mu_15_8_len 8
  1006. #define intp_mu_15_8_lsb 8
  1007. #define xd_r_intp_mu_19_16 0xA192
  1008. #define intp_mu_19_16_pos 0
  1009. #define intp_mu_19_16_len 4
  1010. #define intp_mu_19_16_lsb 16
  1011. #define xd_p_reg_agc_rst 0xA1A0
  1012. #define reg_agc_rst_pos 0
  1013. #define reg_agc_rst_len 1
  1014. #define reg_agc_rst_lsb 0
  1015. #define xd_p_rf_agc_en 0xA1A0
  1016. #define rf_agc_en_pos 1
  1017. #define rf_agc_en_len 1
  1018. #define rf_agc_en_lsb 0
  1019. #define xd_p_rf_agc_dis 0xA1A0
  1020. #define rf_agc_dis_pos 2
  1021. #define rf_agc_dis_len 1
  1022. #define rf_agc_dis_lsb 0
  1023. #define xd_p_if_agc_rst 0xA1A0
  1024. #define if_agc_rst_pos 3
  1025. #define if_agc_rst_len 1
  1026. #define if_agc_rst_lsb 0
  1027. #define xd_p_if_agc_en 0xA1A0
  1028. #define if_agc_en_pos 4
  1029. #define if_agc_en_len 1
  1030. #define if_agc_en_lsb 0
  1031. #define xd_p_if_agc_dis 0xA1A0
  1032. #define if_agc_dis_pos 5
  1033. #define if_agc_dis_len 1
  1034. #define if_agc_dis_lsb 0
  1035. #define xd_p_agc_lock 0xA1A0
  1036. #define agc_lock_pos 6
  1037. #define agc_lock_len 1
  1038. #define agc_lock_lsb 0
  1039. #define xd_p_reg_tinr_rst 0xA1A1
  1040. #define reg_tinr_rst_pos 0
  1041. #define reg_tinr_rst_len 1
  1042. #define reg_tinr_rst_lsb 0
  1043. #define xd_p_reg_tinr_en 0xA1A1
  1044. #define reg_tinr_en_pos 1
  1045. #define reg_tinr_en_len 1
  1046. #define reg_tinr_en_lsb 0
  1047. #define xd_p_reg_ccifs_en 0xA1A2
  1048. #define reg_ccifs_en_pos 0
  1049. #define reg_ccifs_en_len 1
  1050. #define reg_ccifs_en_lsb 0
  1051. #define xd_p_reg_ccifs_dis 0xA1A2
  1052. #define reg_ccifs_dis_pos 1
  1053. #define reg_ccifs_dis_len 1
  1054. #define reg_ccifs_dis_lsb 0
  1055. #define xd_p_reg_ccifs_rst 0xA1A2
  1056. #define reg_ccifs_rst_pos 2
  1057. #define reg_ccifs_rst_len 1
  1058. #define reg_ccifs_rst_lsb 0
  1059. #define xd_p_reg_ccifs_byp 0xA1A2
  1060. #define reg_ccifs_byp_pos 3
  1061. #define reg_ccifs_byp_len 1
  1062. #define reg_ccifs_byp_lsb 0
  1063. #define xd_p_reg_ccif_en 0xA1A3
  1064. #define reg_ccif_en_pos 0
  1065. #define reg_ccif_en_len 1
  1066. #define reg_ccif_en_lsb 0
  1067. #define xd_p_reg_ccif_dis 0xA1A3
  1068. #define reg_ccif_dis_pos 1
  1069. #define reg_ccif_dis_len 1
  1070. #define reg_ccif_dis_lsb 0
  1071. #define xd_p_reg_ccif_rst 0xA1A3
  1072. #define reg_ccif_rst_pos 2
  1073. #define reg_ccif_rst_len 1
  1074. #define reg_ccif_rst_lsb 0
  1075. #define xd_p_reg_ccif_byp 0xA1A3
  1076. #define reg_ccif_byp_pos 3
  1077. #define reg_ccif_byp_len 1
  1078. #define reg_ccif_byp_lsb 0
  1079. #define xd_p_dagc1_rst 0xA1A4
  1080. #define dagc1_rst_pos 0
  1081. #define dagc1_rst_len 1
  1082. #define dagc1_rst_lsb 0
  1083. #define xd_p_dagc1_en 0xA1A4
  1084. #define dagc1_en_pos 1
  1085. #define dagc1_en_len 1
  1086. #define dagc1_en_lsb 0
  1087. #define xd_p_dagc1_mode 0xA1A4
  1088. #define dagc1_mode_pos 2
  1089. #define dagc1_mode_len 2
  1090. #define dagc1_mode_lsb 0
  1091. #define xd_p_dagc1_done 0xA1A4
  1092. #define dagc1_done_pos 4
  1093. #define dagc1_done_len 1
  1094. #define dagc1_done_lsb 0
  1095. #define xd_p_ccid_rst 0xA1A5
  1096. #define ccid_rst_pos 0
  1097. #define ccid_rst_len 1
  1098. #define ccid_rst_lsb 0
  1099. #define xd_p_ccid_en 0xA1A5
  1100. #define ccid_en_pos 1
  1101. #define ccid_en_len 1
  1102. #define ccid_en_lsb 0
  1103. #define xd_p_ccid_mode 0xA1A5
  1104. #define ccid_mode_pos 2
  1105. #define ccid_mode_len 2
  1106. #define ccid_mode_lsb 0
  1107. #define xd_p_ccid_done 0xA1A5
  1108. #define ccid_done_pos 4
  1109. #define ccid_done_len 1
  1110. #define ccid_done_lsb 0
  1111. #define xd_r_ccid_deted 0xA1A5
  1112. #define ccid_deted_pos 5
  1113. #define ccid_deted_len 1
  1114. #define ccid_deted_lsb 0
  1115. #define xd_p_ccid2_en 0xA1A5
  1116. #define ccid2_en_pos 6
  1117. #define ccid2_en_len 1
  1118. #define ccid2_en_lsb 0
  1119. #define xd_p_ccid2_done 0xA1A5
  1120. #define ccid2_done_pos 7
  1121. #define ccid2_done_len 1
  1122. #define ccid2_done_lsb 0
  1123. #define xd_p_reg_bfs_en 0xA1A6
  1124. #define reg_bfs_en_pos 0
  1125. #define reg_bfs_en_len 1
  1126. #define reg_bfs_en_lsb 0
  1127. #define xd_p_reg_bfs_dis 0xA1A6
  1128. #define reg_bfs_dis_pos 1
  1129. #define reg_bfs_dis_len 1
  1130. #define reg_bfs_dis_lsb 0
  1131. #define xd_p_reg_bfs_rst 0xA1A6
  1132. #define reg_bfs_rst_pos 2
  1133. #define reg_bfs_rst_len 1
  1134. #define reg_bfs_rst_lsb 0
  1135. #define xd_p_reg_bfs_byp 0xA1A6
  1136. #define reg_bfs_byp_pos 3
  1137. #define reg_bfs_byp_len 1
  1138. #define reg_bfs_byp_lsb 0
  1139. #define xd_p_reg_antif_en 0xA1A7
  1140. #define reg_antif_en_pos 0
  1141. #define reg_antif_en_len 1
  1142. #define reg_antif_en_lsb 0
  1143. #define xd_p_reg_antif_dis 0xA1A7
  1144. #define reg_antif_dis_pos 1
  1145. #define reg_antif_dis_len 1
  1146. #define reg_antif_dis_lsb 0
  1147. #define xd_p_reg_antif_rst 0xA1A7
  1148. #define reg_antif_rst_pos 2
  1149. #define reg_antif_rst_len 1
  1150. #define reg_antif_rst_lsb 0
  1151. #define xd_p_reg_antif_byp 0xA1A7
  1152. #define reg_antif_byp_pos 3
  1153. #define reg_antif_byp_len 1
  1154. #define reg_antif_byp_lsb 0
  1155. #define xd_p_intp_en 0xA1A8
  1156. #define intp_en_pos 0
  1157. #define intp_en_len 1
  1158. #define intp_en_lsb 0
  1159. #define xd_p_intp_dis 0xA1A8
  1160. #define intp_dis_pos 1
  1161. #define intp_dis_len 1
  1162. #define intp_dis_lsb 0
  1163. #define xd_p_intp_rst 0xA1A8
  1164. #define intp_rst_pos 2
  1165. #define intp_rst_len 1
  1166. #define intp_rst_lsb 0
  1167. #define xd_p_intp_byp 0xA1A8
  1168. #define intp_byp_pos 3
  1169. #define intp_byp_len 1
  1170. #define intp_byp_lsb 0
  1171. #define xd_p_reg_acif_en 0xA1A9
  1172. #define reg_acif_en_pos 0
  1173. #define reg_acif_en_len 1
  1174. #define reg_acif_en_lsb 0
  1175. #define xd_p_reg_acif_dis 0xA1A9
  1176. #define reg_acif_dis_pos 1
  1177. #define reg_acif_dis_len 1
  1178. #define reg_acif_dis_lsb 0
  1179. #define xd_p_reg_acif_rst 0xA1A9
  1180. #define reg_acif_rst_pos 2
  1181. #define reg_acif_rst_len 1
  1182. #define reg_acif_rst_lsb 0
  1183. #define xd_p_reg_acif_byp 0xA1A9
  1184. #define reg_acif_byp_pos 3
  1185. #define reg_acif_byp_len 1
  1186. #define reg_acif_byp_lsb 0
  1187. #define xd_p_reg_acif_sync_mode 0xA1A9
  1188. #define reg_acif_sync_mode_pos 4
  1189. #define reg_acif_sync_mode_len 1
  1190. #define reg_acif_sync_mode_lsb 0
  1191. #define xd_p_dagc2_rst 0xA1AA
  1192. #define dagc2_rst_pos 0
  1193. #define dagc2_rst_len 1
  1194. #define dagc2_rst_lsb 0
  1195. #define xd_p_dagc2_en 0xA1AA
  1196. #define dagc2_en_pos 1
  1197. #define dagc2_en_len 1
  1198. #define dagc2_en_lsb 0
  1199. #define xd_p_dagc2_mode 0xA1AA
  1200. #define dagc2_mode_pos 2
  1201. #define dagc2_mode_len 2
  1202. #define dagc2_mode_lsb 0
  1203. #define xd_p_dagc2_done 0xA1AA
  1204. #define dagc2_done_pos 4
  1205. #define dagc2_done_len 1
  1206. #define dagc2_done_lsb 0
  1207. #define xd_p_reg_dca_en 0xA1AB
  1208. #define reg_dca_en_pos 0
  1209. #define reg_dca_en_len 1
  1210. #define reg_dca_en_lsb 0
  1211. #define xd_p_dagc2_accumulate_num_2k_7_0 0xA1C0
  1212. #define dagc2_accumulate_num_2k_7_0_pos 0
  1213. #define dagc2_accumulate_num_2k_7_0_len 8
  1214. #define dagc2_accumulate_num_2k_7_0_lsb 0
  1215. #define xd_p_dagc2_accumulate_num_2k_12_8 0xA1C1
  1216. #define dagc2_accumulate_num_2k_12_8_pos 0
  1217. #define dagc2_accumulate_num_2k_12_8_len 5
  1218. #define dagc2_accumulate_num_2k_12_8_lsb 8
  1219. #define xd_p_dagc2_accumulate_num_8k_7_0 0xA1C2
  1220. #define dagc2_accumulate_num_8k_7_0_pos 0
  1221. #define dagc2_accumulate_num_8k_7_0_len 8
  1222. #define dagc2_accumulate_num_8k_7_0_lsb 0
  1223. #define xd_p_dagc2_accumulate_num_8k_12_8 0xA1C3
  1224. #define dagc2_accumulate_num_8k_12_8_pos 0
  1225. #define dagc2_accumulate_num_8k_12_8_len 5
  1226. #define dagc2_accumulate_num_8k_12_8_lsb 8
  1227. #define xd_p_dagc2_desired_level_2_0 0xA1C3
  1228. #define dagc2_desired_level_2_0_pos 5
  1229. #define dagc2_desired_level_2_0_len 3
  1230. #define dagc2_desired_level_2_0_lsb 0
  1231. #define xd_p_dagc2_desired_level_8_3 0xA1C4
  1232. #define dagc2_desired_level_8_3_pos 0
  1233. #define dagc2_desired_level_8_3_len 6
  1234. #define dagc2_desired_level_8_3_lsb 3
  1235. #define xd_p_dagc2_apply_delay 0xA1C5
  1236. #define dagc2_apply_delay_pos 0
  1237. #define dagc2_apply_delay_len 7
  1238. #define dagc2_apply_delay_lsb 0
  1239. #define xd_p_dagc2_bypass_scale_ctl 0xA1C6
  1240. #define dagc2_bypass_scale_ctl_pos 0
  1241. #define dagc2_bypass_scale_ctl_len 3
  1242. #define dagc2_bypass_scale_ctl_lsb 0
  1243. #define xd_p_dagc2_programmable_shift1 0xA1C7
  1244. #define dagc2_programmable_shift1_pos 0
  1245. #define dagc2_programmable_shift1_len 8
  1246. #define dagc2_programmable_shift1_lsb 0
  1247. #define xd_p_dagc2_programmable_shift2 0xA1C8
  1248. #define dagc2_programmable_shift2_pos 0
  1249. #define dagc2_programmable_shift2_len 8
  1250. #define dagc2_programmable_shift2_lsb 0
  1251. #define xd_p_reg_dagc2_in_sat_cnt_7_0 0xA1C9
  1252. #define reg_dagc2_in_sat_cnt_7_0_pos 0
  1253. #define reg_dagc2_in_sat_cnt_7_0_len 8
  1254. #define reg_dagc2_in_sat_cnt_7_0_lsb 0
  1255. #define xd_p_reg_dagc2_in_sat_cnt_15_8 0xA1CA
  1256. #define reg_dagc2_in_sat_cnt_15_8_pos 0
  1257. #define reg_dagc2_in_sat_cnt_15_8_len 8
  1258. #define reg_dagc2_in_sat_cnt_15_8_lsb 8
  1259. #define xd_p_reg_dagc2_in_sat_cnt_23_16 0xA1CB
  1260. #define reg_dagc2_in_sat_cnt_23_16_pos 0
  1261. #define reg_dagc2_in_sat_cnt_23_16_len 8
  1262. #define reg_dagc2_in_sat_cnt_23_16_lsb 16
  1263. #define xd_p_reg_dagc2_in_sat_cnt_31_24 0xA1CC
  1264. #define reg_dagc2_in_sat_cnt_31_24_pos 0
  1265. #define reg_dagc2_in_sat_cnt_31_24_len 8
  1266. #define reg_dagc2_in_sat_cnt_31_24_lsb 24
  1267. #define xd_p_reg_dagc2_out_sat_cnt_7_0 0xA1CD
  1268. #define reg_dagc2_out_sat_cnt_7_0_pos 0
  1269. #define reg_dagc2_out_sat_cnt_7_0_len 8
  1270. #define reg_dagc2_out_sat_cnt_7_0_lsb 0
  1271. #define xd_p_reg_dagc2_out_sat_cnt_15_8 0xA1CE
  1272. #define reg_dagc2_out_sat_cnt_15_8_pos 0
  1273. #define reg_dagc2_out_sat_cnt_15_8_len 8
  1274. #define reg_dagc2_out_sat_cnt_15_8_lsb 8
  1275. #define xd_p_reg_dagc2_out_sat_cnt_23_16 0xA1CF
  1276. #define reg_dagc2_out_sat_cnt_23_16_pos 0
  1277. #define reg_dagc2_out_sat_cnt_23_16_len 8
  1278. #define reg_dagc2_out_sat_cnt_23_16_lsb 16
  1279. #define xd_p_reg_dagc2_out_sat_cnt_31_24 0xA1D0
  1280. #define reg_dagc2_out_sat_cnt_31_24_pos 0
  1281. #define reg_dagc2_out_sat_cnt_31_24_len 8
  1282. #define reg_dagc2_out_sat_cnt_31_24_lsb 24
  1283. #define xd_r_dagc2_multiplier_7_0 0xA1D6
  1284. #define dagc2_multiplier_7_0_pos 0
  1285. #define dagc2_multiplier_7_0_len 8
  1286. #define dagc2_multiplier_7_0_lsb 0
  1287. #define xd_r_dagc2_multiplier_15_8 0xA1D7
  1288. #define dagc2_multiplier_15_8_pos 0
  1289. #define dagc2_multiplier_15_8_len 8
  1290. #define dagc2_multiplier_15_8_lsb 8
  1291. #define xd_r_dagc2_right_shift_bits 0xA1D8
  1292. #define dagc2_right_shift_bits_pos 0
  1293. #define dagc2_right_shift_bits_len 4
  1294. #define dagc2_right_shift_bits_lsb 0
  1295. #define xd_p_cfoe_NS_coeff1_7_0 0xA200
  1296. #define cfoe_NS_coeff1_7_0_pos 0
  1297. #define cfoe_NS_coeff1_7_0_len 8
  1298. #define cfoe_NS_coeff1_7_0_lsb 0
  1299. #define xd_p_cfoe_NS_coeff1_15_8 0xA201
  1300. #define cfoe_NS_coeff1_15_8_pos 0
  1301. #define cfoe_NS_coeff1_15_8_len 8
  1302. #define cfoe_NS_coeff1_15_8_lsb 8
  1303. #define xd_p_cfoe_NS_coeff1_23_16 0xA202
  1304. #define cfoe_NS_coeff1_23_16_pos 0
  1305. #define cfoe_NS_coeff1_23_16_len 8
  1306. #define cfoe_NS_coeff1_23_16_lsb 16
  1307. #define xd_p_cfoe_NS_coeff1_25_24 0xA203
  1308. #define cfoe_NS_coeff1_25_24_pos 0
  1309. #define cfoe_NS_coeff1_25_24_len 2
  1310. #define cfoe_NS_coeff1_25_24_lsb 24
  1311. #define xd_p_cfoe_NS_coeff2_5_0 0xA203
  1312. #define cfoe_NS_coeff2_5_0_pos 2
  1313. #define cfoe_NS_coeff2_5_0_len 6
  1314. #define cfoe_NS_coeff2_5_0_lsb 0
  1315. #define xd_p_cfoe_NS_coeff2_13_6 0xA204
  1316. #define cfoe_NS_coeff2_13_6_pos 0
  1317. #define cfoe_NS_coeff2_13_6_len 8
  1318. #define cfoe_NS_coeff2_13_6_lsb 6
  1319. #define xd_p_cfoe_NS_coeff2_21_14 0xA205
  1320. #define cfoe_NS_coeff2_21_14_pos 0
  1321. #define cfoe_NS_coeff2_21_14_len 8
  1322. #define cfoe_NS_coeff2_21_14_lsb 14
  1323. #define xd_p_cfoe_NS_coeff2_24_22 0xA206
  1324. #define cfoe_NS_coeff2_24_22_pos 0
  1325. #define cfoe_NS_coeff2_24_22_len 3
  1326. #define cfoe_NS_coeff2_24_22_lsb 22
  1327. #define xd_p_cfoe_lf_c1_4_0 0xA206
  1328. #define cfoe_lf_c1_4_0_pos 3
  1329. #define cfoe_lf_c1_4_0_len 5
  1330. #define cfoe_lf_c1_4_0_lsb 0
  1331. #define xd_p_cfoe_lf_c1_12_5 0xA207
  1332. #define cfoe_lf_c1_12_5_pos 0
  1333. #define cfoe_lf_c1_12_5_len 8
  1334. #define cfoe_lf_c1_12_5_lsb 5
  1335. #define xd_p_cfoe_lf_c1_20_13 0xA208
  1336. #define cfoe_lf_c1_20_13_pos 0
  1337. #define cfoe_lf_c1_20_13_len 8
  1338. #define cfoe_lf_c1_20_13_lsb 13
  1339. #define xd_p_cfoe_lf_c1_25_21 0xA209
  1340. #define cfoe_lf_c1_25_21_pos 0
  1341. #define cfoe_lf_c1_25_21_len 5
  1342. #define cfoe_lf_c1_25_21_lsb 21
  1343. #define xd_p_cfoe_lf_c2_2_0 0xA209
  1344. #define cfoe_lf_c2_2_0_pos 5
  1345. #define cfoe_lf_c2_2_0_len 3
  1346. #define cfoe_lf_c2_2_0_lsb 0
  1347. #define xd_p_cfoe_lf_c2_10_3 0xA20A
  1348. #define cfoe_lf_c2_10_3_pos 0
  1349. #define cfoe_lf_c2_10_3_len 8
  1350. #define cfoe_lf_c2_10_3_lsb 3
  1351. #define xd_p_cfoe_lf_c2_18_11 0xA20B
  1352. #define cfoe_lf_c2_18_11_pos 0
  1353. #define cfoe_lf_c2_18_11_len 8
  1354. #define cfoe_lf_c2_18_11_lsb 11
  1355. #define xd_p_cfoe_lf_c2_25_19 0xA20C
  1356. #define cfoe_lf_c2_25_19_pos 0
  1357. #define cfoe_lf_c2_25_19_len 7
  1358. #define cfoe_lf_c2_25_19_lsb 19
  1359. #define xd_p_cfoe_ifod_7_0 0xA20D
  1360. #define cfoe_ifod_7_0_pos 0
  1361. #define cfoe_ifod_7_0_len 8
  1362. #define cfoe_ifod_7_0_lsb 0
  1363. #define xd_p_cfoe_ifod_10_8 0xA20E
  1364. #define cfoe_ifod_10_8_pos 0
  1365. #define cfoe_ifod_10_8_len 3
  1366. #define cfoe_ifod_10_8_lsb 8
  1367. #define xd_p_cfoe_Divg_ctr_th 0xA20E
  1368. #define cfoe_Divg_ctr_th_pos 4
  1369. #define cfoe_Divg_ctr_th_len 4
  1370. #define cfoe_Divg_ctr_th_lsb 0
  1371. #define xd_p_cfoe_FOT_divg_th 0xA20F
  1372. #define cfoe_FOT_divg_th_pos 0
  1373. #define cfoe_FOT_divg_th_len 8
  1374. #define cfoe_FOT_divg_th_lsb 0
  1375. #define xd_p_cfoe_FOT_cnvg_th 0xA210
  1376. #define cfoe_FOT_cnvg_th_pos 0
  1377. #define cfoe_FOT_cnvg_th_len 8
  1378. #define cfoe_FOT_cnvg_th_lsb 0
  1379. #define xd_p_reg_cfoe_offset_7_0 0xA211
  1380. #define reg_cfoe_offset_7_0_pos 0
  1381. #define reg_cfoe_offset_7_0_len 8
  1382. #define reg_cfoe_offset_7_0_lsb 0
  1383. #define xd_p_reg_cfoe_offset_9_8 0xA212
  1384. #define reg_cfoe_offset_9_8_pos 0
  1385. #define reg_cfoe_offset_9_8_len 2
  1386. #define reg_cfoe_offset_9_8_lsb 8
  1387. #define xd_p_reg_cfoe_ifoe_sign_corr 0xA212
  1388. #define reg_cfoe_ifoe_sign_corr_pos 2
  1389. #define reg_cfoe_ifoe_sign_corr_len 1
  1390. #define reg_cfoe_ifoe_sign_corr_lsb 0
  1391. #define xd_r_cfoe_fot_LF_output_7_0 0xA218
  1392. #define cfoe_fot_LF_output_7_0_pos 0
  1393. #define cfoe_fot_LF_output_7_0_len 8
  1394. #define cfoe_fot_LF_output_7_0_lsb 0
  1395. #define xd_r_cfoe_fot_LF_output_15_8 0xA219
  1396. #define cfoe_fot_LF_output_15_8_pos 0
  1397. #define cfoe_fot_LF_output_15_8_len 8
  1398. #define cfoe_fot_LF_output_15_8_lsb 8
  1399. #define xd_r_cfoe_ifo_metric_7_0 0xA21A
  1400. #define cfoe_ifo_metric_7_0_pos 0
  1401. #define cfoe_ifo_metric_7_0_len 8
  1402. #define cfoe_ifo_metric_7_0_lsb 0
  1403. #define xd_r_cfoe_ifo_metric_15_8 0xA21B
  1404. #define cfoe_ifo_metric_15_8_pos 0
  1405. #define cfoe_ifo_metric_15_8_len 8
  1406. #define cfoe_ifo_metric_15_8_lsb 8
  1407. #define xd_r_cfoe_ifo_metric_23_16 0xA21C
  1408. #define cfoe_ifo_metric_23_16_pos 0
  1409. #define cfoe_ifo_metric_23_16_len 8
  1410. #define cfoe_ifo_metric_23_16_lsb 16
  1411. #define xd_p_ste_Nu 0xA220
  1412. #define ste_Nu_pos 0
  1413. #define ste_Nu_len 2
  1414. #define ste_Nu_lsb 0
  1415. #define xd_p_ste_GI 0xA220
  1416. #define ste_GI_pos 2
  1417. #define ste_GI_len 3
  1418. #define ste_GI_lsb 0
  1419. #define xd_p_ste_symbol_num 0xA221
  1420. #define ste_symbol_num_pos 0
  1421. #define ste_symbol_num_len 2
  1422. #define ste_symbol_num_lsb 0
  1423. #define xd_p_ste_sample_num 0xA221
  1424. #define ste_sample_num_pos 2
  1425. #define ste_sample_num_len 2
  1426. #define ste_sample_num_lsb 0
  1427. #define xd_p_reg_ste_buf_en 0xA221
  1428. #define reg_ste_buf_en_pos 7
  1429. #define reg_ste_buf_en_len 1
  1430. #define reg_ste_buf_en_lsb 0
  1431. #define xd_p_ste_FFT_offset_7_0 0xA222
  1432. #define ste_FFT_offset_7_0_pos 0
  1433. #define ste_FFT_offset_7_0_len 8
  1434. #define ste_FFT_offset_7_0_lsb 0
  1435. #define xd_p_ste_FFT_offset_11_8 0xA223
  1436. #define ste_FFT_offset_11_8_pos 0
  1437. #define ste_FFT_offset_11_8_len 4
  1438. #define ste_FFT_offset_11_8_lsb 8
  1439. #define xd_p_reg_ste_tstmod 0xA223
  1440. #define reg_ste_tstmod_pos 5
  1441. #define reg_ste_tstmod_len 1
  1442. #define reg_ste_tstmod_lsb 0
  1443. #define xd_p_ste_adv_start_7_0 0xA224
  1444. #define ste_adv_start_7_0_pos 0
  1445. #define ste_adv_start_7_0_len 8
  1446. #define ste_adv_start_7_0_lsb 0
  1447. #define xd_p_ste_adv_start_10_8 0xA225
  1448. #define ste_adv_start_10_8_pos 0
  1449. #define ste_adv_start_10_8_len 3
  1450. #define ste_adv_start_10_8_lsb 8
  1451. #define xd_p_ste_adv_stop 0xA226
  1452. #define ste_adv_stop_pos 0
  1453. #define ste_adv_stop_len 8
  1454. #define ste_adv_stop_lsb 0
  1455. #define xd_r_ste_P_value_7_0 0xA228
  1456. #define ste_P_value_7_0_pos 0
  1457. #define ste_P_value_7_0_len 8
  1458. #define ste_P_value_7_0_lsb 0
  1459. #define xd_r_ste_P_value_10_8 0xA229
  1460. #define ste_P_value_10_8_pos 0
  1461. #define ste_P_value_10_8_len 3
  1462. #define ste_P_value_10_8_lsb 8
  1463. #define xd_r_ste_M_value_7_0 0xA22A
  1464. #define ste_M_value_7_0_pos 0
  1465. #define ste_M_value_7_0_len 8
  1466. #define ste_M_value_7_0_lsb 0
  1467. #define xd_r_ste_M_value_10_8 0xA22B
  1468. #define ste_M_value_10_8_pos 0
  1469. #define ste_M_value_10_8_len 3
  1470. #define ste_M_value_10_8_lsb 8
  1471. #define xd_r_ste_H1 0xA22C
  1472. #define ste_H1_pos 0
  1473. #define ste_H1_len 7
  1474. #define ste_H1_lsb 0
  1475. #define xd_r_ste_H2 0xA22D
  1476. #define ste_H2_pos 0
  1477. #define ste_H2_len 7
  1478. #define ste_H2_lsb 0
  1479. #define xd_r_ste_H3 0xA22E
  1480. #define ste_H3_pos 0
  1481. #define ste_H3_len 7
  1482. #define ste_H3_lsb 0
  1483. #define xd_r_ste_H4 0xA22F
  1484. #define ste_H4_pos 0
  1485. #define ste_H4_len 7
  1486. #define ste_H4_lsb 0
  1487. #define xd_r_ste_Corr_value_I_7_0 0xA230
  1488. #define ste_Corr_value_I_7_0_pos 0
  1489. #define ste_Corr_value_I_7_0_len 8
  1490. #define ste_Corr_value_I_7_0_lsb 0
  1491. #define xd_r_ste_Corr_value_I_15_8 0xA231
  1492. #define ste_Corr_value_I_15_8_pos 0
  1493. #define ste_Corr_value_I_15_8_len 8
  1494. #define ste_Corr_value_I_15_8_lsb 8
  1495. #define xd_r_ste_Corr_value_I_23_16 0xA232
  1496. #define ste_Corr_value_I_23_16_pos 0
  1497. #define ste_Corr_value_I_23_16_len 8
  1498. #define ste_Corr_value_I_23_16_lsb 16
  1499. #define xd_r_ste_Corr_value_I_27_24 0xA233
  1500. #define ste_Corr_value_I_27_24_pos 0
  1501. #define ste_Corr_value_I_27_24_len 4
  1502. #define ste_Corr_value_I_27_24_lsb 24
  1503. #define xd_r_ste_Corr_value_Q_7_0 0xA234
  1504. #define ste_Corr_value_Q_7_0_pos 0
  1505. #define ste_Corr_value_Q_7_0_len 8
  1506. #define ste_Corr_value_Q_7_0_lsb 0
  1507. #define xd_r_ste_Corr_value_Q_15_8 0xA235
  1508. #define ste_Corr_value_Q_15_8_pos 0
  1509. #define ste_Corr_value_Q_15_8_len 8
  1510. #define ste_Corr_value_Q_15_8_lsb 8
  1511. #define xd_r_ste_Corr_value_Q_23_16 0xA236
  1512. #define ste_Corr_value_Q_23_16_pos 0
  1513. #define ste_Corr_value_Q_23_16_len 8
  1514. #define ste_Corr_value_Q_23_16_lsb 16
  1515. #define xd_r_ste_Corr_value_Q_27_24 0xA237
  1516. #define ste_Corr_value_Q_27_24_pos 0
  1517. #define ste_Corr_value_Q_27_24_len 4
  1518. #define ste_Corr_value_Q_27_24_lsb 24
  1519. #define xd_r_ste_J_num_7_0 0xA238
  1520. #define ste_J_num_7_0_pos 0
  1521. #define ste_J_num_7_0_len 8
  1522. #define ste_J_num_7_0_lsb 0
  1523. #define xd_r_ste_J_num_15_8 0xA239
  1524. #define ste_J_num_15_8_pos 0
  1525. #define ste_J_num_15_8_len 8
  1526. #define ste_J_num_15_8_lsb 8
  1527. #define xd_r_ste_J_num_23_16 0xA23A
  1528. #define ste_J_num_23_16_pos 0
  1529. #define ste_J_num_23_16_len 8
  1530. #define ste_J_num_23_16_lsb 16
  1531. #define xd_r_ste_J_num_31_24 0xA23B
  1532. #define ste_J_num_31_24_pos 0
  1533. #define ste_J_num_31_24_len 8
  1534. #define ste_J_num_31_24_lsb 24
  1535. #define xd_r_ste_J_den_7_0 0xA23C
  1536. #define ste_J_den_7_0_pos 0
  1537. #define ste_J_den_7_0_len 8
  1538. #define ste_J_den_7_0_lsb 0
  1539. #define xd_r_ste_J_den_15_8 0xA23D
  1540. #define ste_J_den_15_8_pos 0
  1541. #define ste_J_den_15_8_len 8
  1542. #define ste_J_den_15_8_lsb 8
  1543. #define xd_r_ste_J_den_18_16 0xA23E
  1544. #define ste_J_den_18_16_pos 0
  1545. #define ste_J_den_18_16_len 3
  1546. #define ste_J_den_18_16_lsb 16
  1547. #define xd_r_ste_Beacon_Indicator 0xA23E
  1548. #define ste_Beacon_Indicator_pos 4
  1549. #define ste_Beacon_Indicator_len 1
  1550. #define ste_Beacon_Indicator_lsb 0
  1551. #define xd_r_tpsd_Frame_Num 0xA250
  1552. #define tpsd_Frame_Num_pos 0
  1553. #define tpsd_Frame_Num_len 2
  1554. #define tpsd_Frame_Num_lsb 0
  1555. #define xd_r_tpsd_Constel 0xA250
  1556. #define tpsd_Constel_pos 2
  1557. #define tpsd_Constel_len 2
  1558. #define tpsd_Constel_lsb 0
  1559. #define xd_r_tpsd_GI 0xA250
  1560. #define tpsd_GI_pos 4
  1561. #define tpsd_GI_len 2
  1562. #define tpsd_GI_lsb 0
  1563. #define xd_r_tpsd_Mode 0xA250
  1564. #define tpsd_Mode_pos 6
  1565. #define tpsd_Mode_len 2
  1566. #define tpsd_Mode_lsb 0
  1567. #define xd_r_tpsd_CR_HP 0xA251
  1568. #define tpsd_CR_HP_pos 0
  1569. #define tpsd_CR_HP_len 3
  1570. #define tpsd_CR_HP_lsb 0
  1571. #define xd_r_tpsd_CR_LP 0xA251
  1572. #define tpsd_CR_LP_pos 3
  1573. #define tpsd_CR_LP_len 3
  1574. #define tpsd_CR_LP_lsb 0
  1575. #define xd_r_tpsd_Hie 0xA252
  1576. #define tpsd_Hie_pos 0
  1577. #define tpsd_Hie_len 3
  1578. #define tpsd_Hie_lsb 0
  1579. #define xd_r_tpsd_Res_Bits 0xA252
  1580. #define tpsd_Res_Bits_pos 3
  1581. #define tpsd_Res_Bits_len 5
  1582. #define tpsd_Res_Bits_lsb 0
  1583. #define xd_r_tpsd_Res_Bits_0 0xA253
  1584. #define tpsd_Res_Bits_0_pos 0
  1585. #define tpsd_Res_Bits_0_len 1
  1586. #define tpsd_Res_Bits_0_lsb 0
  1587. #define xd_r_tpsd_LengthInd 0xA253
  1588. #define tpsd_LengthInd_pos 1
  1589. #define tpsd_LengthInd_len 6
  1590. #define tpsd_LengthInd_lsb 0
  1591. #define xd_r_tpsd_Cell_Id_7_0 0xA254
  1592. #define tpsd_Cell_Id_7_0_pos 0
  1593. #define tpsd_Cell_Id_7_0_len 8
  1594. #define tpsd_Cell_Id_7_0_lsb 0
  1595. #define xd_r_tpsd_Cell_Id_15_8 0xA255
  1596. #define tpsd_Cell_Id_15_8_pos 0
  1597. #define tpsd_Cell_Id_15_8_len 8
  1598. #define tpsd_Cell_Id_15_8_lsb 0
  1599. #define xd_p_reg_fft_mask_tone0_7_0 0xA260
  1600. #define reg_fft_mask_tone0_7_0_pos 0
  1601. #define reg_fft_mask_tone0_7_0_len 8
  1602. #define reg_fft_mask_tone0_7_0_lsb 0
  1603. #define xd_p_reg_fft_mask_tone0_12_8 0xA261
  1604. #define reg_fft_mask_tone0_12_8_pos 0
  1605. #define reg_fft_mask_tone0_12_8_len 5
  1606. #define reg_fft_mask_tone0_12_8_lsb 8
  1607. #define xd_p_reg_fft_mask_tone1_7_0 0xA262
  1608. #define reg_fft_mask_tone1_7_0_pos 0
  1609. #define reg_fft_mask_tone1_7_0_len 8
  1610. #define reg_fft_mask_tone1_7_0_lsb 0
  1611. #define xd_p_reg_fft_mask_tone1_12_8 0xA263
  1612. #define reg_fft_mask_tone1_12_8_pos 0
  1613. #define reg_fft_mask_tone1_12_8_len 5
  1614. #define reg_fft_mask_tone1_12_8_lsb 8
  1615. #define xd_p_reg_fft_mask_tone2_7_0 0xA264
  1616. #define reg_fft_mask_tone2_7_0_pos 0
  1617. #define reg_fft_mask_tone2_7_0_len 8
  1618. #define reg_fft_mask_tone2_7_0_lsb 0
  1619. #define xd_p_reg_fft_mask_tone2_12_8 0xA265
  1620. #define reg_fft_mask_tone2_12_8_pos 0
  1621. #define reg_fft_mask_tone2_12_8_len 5
  1622. #define reg_fft_mask_tone2_12_8_lsb 8
  1623. #define xd_p_reg_fft_mask_tone3_7_0 0xA266
  1624. #define reg_fft_mask_tone3_7_0_pos 0
  1625. #define reg_fft_mask_tone3_7_0_len 8
  1626. #define reg_fft_mask_tone3_7_0_lsb 0
  1627. #define xd_p_reg_fft_mask_tone3_12_8 0xA267
  1628. #define reg_fft_mask_tone3_12_8_pos 0
  1629. #define reg_fft_mask_tone3_12_8_len 5
  1630. #define reg_fft_mask_tone3_12_8_lsb 8
  1631. #define xd_p_reg_fft_mask_from0_7_0 0xA268
  1632. #define reg_fft_mask_from0_7_0_pos 0
  1633. #define reg_fft_mask_from0_7_0_len 8
  1634. #define reg_fft_mask_from0_7_0_lsb 0
  1635. #define xd_p_reg_fft_mask_from0_12_8 0xA269
  1636. #define reg_fft_mask_from0_12_8_pos 0
  1637. #define reg_fft_mask_from0_12_8_len 5
  1638. #define reg_fft_mask_from0_12_8_lsb 8
  1639. #define xd_p_reg_fft_mask_to0_7_0 0xA26A
  1640. #define reg_fft_mask_to0_7_0_pos 0
  1641. #define reg_fft_mask_to0_7_0_len 8
  1642. #define reg_fft_mask_to0_7_0_lsb 0
  1643. #define xd_p_reg_fft_mask_to0_12_8 0xA26B
  1644. #define reg_fft_mask_to0_12_8_pos 0
  1645. #define reg_fft_mask_to0_12_8_len 5
  1646. #define reg_fft_mask_to0_12_8_lsb 8
  1647. #define xd_p_reg_fft_mask_from1_7_0 0xA26C
  1648. #define reg_fft_mask_from1_7_0_pos 0
  1649. #define reg_fft_mask_from1_7_0_len 8
  1650. #define reg_fft_mask_from1_7_0_lsb 0
  1651. #define xd_p_reg_fft_mask_from1_12_8 0xA26D
  1652. #define reg_fft_mask_from1_12_8_pos 0
  1653. #define reg_fft_mask_from1_12_8_len 5
  1654. #define reg_fft_mask_from1_12_8_lsb 8
  1655. #define xd_p_reg_fft_mask_to1_7_0 0xA26E
  1656. #define reg_fft_mask_to1_7_0_pos 0
  1657. #define reg_fft_mask_to1_7_0_len 8
  1658. #define reg_fft_mask_to1_7_0_lsb 0
  1659. #define xd_p_reg_fft_mask_to1_12_8 0xA26F
  1660. #define reg_fft_mask_to1_12_8_pos 0
  1661. #define reg_fft_mask_to1_12_8_len 5
  1662. #define reg_fft_mask_to1_12_8_lsb 8
  1663. #define xd_p_reg_cge_idx0_7_0 0xA280
  1664. #define reg_cge_idx0_7_0_pos 0
  1665. #define reg_cge_idx0_7_0_len 8
  1666. #define reg_cge_idx0_7_0_lsb 0
  1667. #define xd_p_reg_cge_idx0_12_8 0xA281
  1668. #define reg_cge_idx0_12_8_pos 0
  1669. #define reg_cge_idx0_12_8_len 5
  1670. #define reg_cge_idx0_12_8_lsb 8
  1671. #define xd_p_reg_cge_idx1_7_0 0xA282
  1672. #define reg_cge_idx1_7_0_pos 0
  1673. #define reg_cge_idx1_7_0_len 8
  1674. #define reg_cge_idx1_7_0_lsb 0
  1675. #define xd_p_reg_cge_idx1_12_8 0xA283
  1676. #define reg_cge_idx1_12_8_pos 0
  1677. #define reg_cge_idx1_12_8_len 5
  1678. #define reg_cge_idx1_12_8_lsb 8
  1679. #define xd_p_reg_cge_idx2_7_0 0xA284
  1680. #define reg_cge_idx2_7_0_pos 0
  1681. #define reg_cge_idx2_7_0_len 8
  1682. #define reg_cge_idx2_7_0_lsb 0
  1683. #define xd_p_reg_cge_idx2_12_8 0xA285
  1684. #define reg_cge_idx2_12_8_pos 0
  1685. #define reg_cge_idx2_12_8_len 5
  1686. #define reg_cge_idx2_12_8_lsb 8
  1687. #define xd_p_reg_cge_idx3_7_0 0xA286
  1688. #define reg_cge_idx3_7_0_pos 0
  1689. #define reg_cge_idx3_7_0_len 8
  1690. #define reg_cge_idx3_7_0_lsb 0
  1691. #define xd_p_reg_cge_idx3_12_8 0xA287
  1692. #define reg_cge_idx3_12_8_pos 0
  1693. #define reg_cge_idx3_12_8_len 5
  1694. #define reg_cge_idx3_12_8_lsb 8
  1695. #define xd_p_reg_cge_idx4_7_0 0xA288
  1696. #define reg_cge_idx4_7_0_pos 0
  1697. #define reg_cge_idx4_7_0_len 8
  1698. #define reg_cge_idx4_7_0_lsb 0
  1699. #define xd_p_reg_cge_idx4_12_8 0xA289
  1700. #define reg_cge_idx4_12_8_pos 0
  1701. #define reg_cge_idx4_12_8_len 5
  1702. #define reg_cge_idx4_12_8_lsb 8
  1703. #define xd_p_reg_cge_idx5_7_0 0xA28A
  1704. #define reg_cge_idx5_7_0_pos 0
  1705. #define reg_cge_idx5_7_0_len 8
  1706. #define reg_cge_idx5_7_0_lsb 0
  1707. #define xd_p_reg_cge_idx5_12_8 0xA28B
  1708. #define reg_cge_idx5_12_8_pos 0
  1709. #define reg_cge_idx5_12_8_len 5
  1710. #define reg_cge_idx5_12_8_lsb 8
  1711. #define xd_p_reg_cge_idx6_7_0 0xA28C
  1712. #define reg_cge_idx6_7_0_pos 0
  1713. #define reg_cge_idx6_7_0_len 8
  1714. #define reg_cge_idx6_7_0_lsb 0
  1715. #define xd_p_reg_cge_idx6_12_8 0xA28D
  1716. #define reg_cge_idx6_12_8_pos 0
  1717. #define reg_cge_idx6_12_8_len 5
  1718. #define reg_cge_idx6_12_8_lsb 8
  1719. #define xd_p_reg_cge_idx7_7_0 0xA28E
  1720. #define reg_cge_idx7_7_0_pos 0
  1721. #define reg_cge_idx7_7_0_len 8
  1722. #define reg_cge_idx7_7_0_lsb 0
  1723. #define xd_p_reg_cge_idx7_12_8 0xA28F
  1724. #define reg_cge_idx7_12_8_pos 0
  1725. #define reg_cge_idx7_12_8_len 5
  1726. #define reg_cge_idx7_12_8_lsb 8
  1727. #define xd_p_reg_cge_idx8_7_0 0xA290
  1728. #define reg_cge_idx8_7_0_pos 0
  1729. #define reg_cge_idx8_7_0_len 8
  1730. #define reg_cge_idx8_7_0_lsb 0
  1731. #define xd_p_reg_cge_idx8_12_8 0xA291
  1732. #define reg_cge_idx8_12_8_pos 0
  1733. #define reg_cge_idx8_12_8_len 5
  1734. #define reg_cge_idx8_12_8_lsb 8
  1735. #define xd_p_reg_cge_idx9_7_0 0xA292
  1736. #define reg_cge_idx9_7_0_pos 0
  1737. #define reg_cge_idx9_7_0_len 8
  1738. #define reg_cge_idx9_7_0_lsb 0
  1739. #define xd_p_reg_cge_idx9_12_8 0xA293
  1740. #define reg_cge_idx9_12_8_pos 0
  1741. #define reg_cge_idx9_12_8_len 5
  1742. #define reg_cge_idx9_12_8_lsb 8
  1743. #define xd_p_reg_cge_idx10_7_0 0xA294
  1744. #define reg_cge_idx10_7_0_pos 0
  1745. #define reg_cge_idx10_7_0_len 8
  1746. #define reg_cge_idx10_7_0_lsb 0
  1747. #define xd_p_reg_cge_idx10_12_8 0xA295
  1748. #define reg_cge_idx10_12_8_pos 0
  1749. #define reg_cge_idx10_12_8_len 5
  1750. #define reg_cge_idx10_12_8_lsb 8
  1751. #define xd_p_reg_cge_idx11_7_0 0xA296
  1752. #define reg_cge_idx11_7_0_pos 0
  1753. #define reg_cge_idx11_7_0_len 8
  1754. #define reg_cge_idx11_7_0_lsb 0
  1755. #define xd_p_reg_cge_idx11_12_8 0xA297
  1756. #define reg_cge_idx11_12_8_pos 0
  1757. #define reg_cge_idx11_12_8_len 5
  1758. #define reg_cge_idx11_12_8_lsb 8
  1759. #define xd_p_reg_cge_idx12_7_0 0xA298
  1760. #define reg_cge_idx12_7_0_pos 0
  1761. #define reg_cge_idx12_7_0_len 8
  1762. #define reg_cge_idx12_7_0_lsb 0
  1763. #define xd_p_reg_cge_idx12_12_8 0xA299
  1764. #define reg_cge_idx12_12_8_pos 0
  1765. #define reg_cge_idx12_12_8_len 5
  1766. #define reg_cge_idx12_12_8_lsb 8
  1767. #define xd_p_reg_cge_idx13_7_0 0xA29A
  1768. #define reg_cge_idx13_7_0_pos 0
  1769. #define reg_cge_idx13_7_0_len 8
  1770. #define reg_cge_idx13_7_0_lsb 0
  1771. #define xd_p_reg_cge_idx13_12_8 0xA29B
  1772. #define reg_cge_idx13_12_8_pos 0
  1773. #define reg_cge_idx13_12_8_len 5
  1774. #define reg_cge_idx13_12_8_lsb 8
  1775. #define xd_p_reg_cge_idx14_7_0 0xA29C
  1776. #define reg_cge_idx14_7_0_pos 0
  1777. #define reg_cge_idx14_7_0_len 8
  1778. #define reg_cge_idx14_7_0_lsb 0
  1779. #define xd_p_reg_cge_idx14_12_8 0xA29D
  1780. #define reg_cge_idx14_12_8_pos 0
  1781. #define reg_cge_idx14_12_8_len 5
  1782. #define reg_cge_idx14_12_8_lsb 8
  1783. #define xd_p_reg_cge_idx15_7_0 0xA29E
  1784. #define reg_cge_idx15_7_0_pos 0
  1785. #define reg_cge_idx15_7_0_len 8
  1786. #define reg_cge_idx15_7_0_lsb 0
  1787. #define xd_p_reg_cge_idx15_12_8 0xA29F
  1788. #define reg_cge_idx15_12_8_pos 0
  1789. #define reg_cge_idx15_12_8_len 5
  1790. #define reg_cge_idx15_12_8_lsb 8
  1791. #define xd_r_reg_fft_crc 0xA2A8
  1792. #define reg_fft_crc_pos 0
  1793. #define reg_fft_crc_len 8
  1794. #define reg_fft_crc_lsb 0
  1795. #define xd_p_fd_fft_shift_max 0xA2A9
  1796. #define fd_fft_shift_max_pos 0
  1797. #define fd_fft_shift_max_len 4
  1798. #define fd_fft_shift_max_lsb 0
  1799. #define xd_r_fd_fft_shift 0xA2A9
  1800. #define fd_fft_shift_pos 4
  1801. #define fd_fft_shift_len 4
  1802. #define fd_fft_shift_lsb 0
  1803. #define xd_r_fd_fft_frame_num 0xA2AA
  1804. #define fd_fft_frame_num_pos 0
  1805. #define fd_fft_frame_num_len 2
  1806. #define fd_fft_frame_num_lsb 0
  1807. #define xd_r_fd_fft_symbol_count 0xA2AB
  1808. #define fd_fft_symbol_count_pos 0
  1809. #define fd_fft_symbol_count_len 7
  1810. #define fd_fft_symbol_count_lsb 0
  1811. #define xd_r_reg_fft_idx_max_7_0 0xA2AC
  1812. #define reg_fft_idx_max_7_0_pos 0
  1813. #define reg_fft_idx_max_7_0_len 8
  1814. #define reg_fft_idx_max_7_0_lsb 0
  1815. #define xd_r_reg_fft_idx_max_12_8 0xA2AD
  1816. #define reg_fft_idx_max_12_8_pos 0
  1817. #define reg_fft_idx_max_12_8_len 5
  1818. #define reg_fft_idx_max_12_8_lsb 8
  1819. #define xd_p_reg_cge_program 0xA2AE
  1820. #define reg_cge_program_pos 0
  1821. #define reg_cge_program_len 1
  1822. #define reg_cge_program_lsb 0
  1823. #define xd_p_reg_cge_fixed 0xA2AE
  1824. #define reg_cge_fixed_pos 1
  1825. #define reg_cge_fixed_len 1
  1826. #define reg_cge_fixed_lsb 0
  1827. #define xd_p_reg_fft_rotate_en 0xA2AE
  1828. #define reg_fft_rotate_en_pos 2
  1829. #define reg_fft_rotate_en_len 1
  1830. #define reg_fft_rotate_en_lsb 0
  1831. #define xd_p_reg_fft_rotate_base_4_0 0xA2AE
  1832. #define reg_fft_rotate_base_4_0_pos 3
  1833. #define reg_fft_rotate_base_4_0_len 5
  1834. #define reg_fft_rotate_base_4_0_lsb 0
  1835. #define xd_p_reg_fft_rotate_base_12_5 0xA2AF
  1836. #define reg_fft_rotate_base_12_5_pos 0
  1837. #define reg_fft_rotate_base_12_5_len 8
  1838. #define reg_fft_rotate_base_12_5_lsb 5
  1839. #define xd_p_reg_gp_trigger_fd 0xA2B8
  1840. #define reg_gp_trigger_fd_pos 0
  1841. #define reg_gp_trigger_fd_len 1
  1842. #define reg_gp_trigger_fd_lsb 0
  1843. #define xd_p_reg_trigger_sel_fd 0xA2B8
  1844. #define reg_trigger_sel_fd_pos 1
  1845. #define reg_trigger_sel_fd_len 2
  1846. #define reg_trigger_sel_fd_lsb 0
  1847. #define xd_p_reg_trigger_module_sel_fd 0xA2B9
  1848. #define reg_trigger_module_sel_fd_pos 0
  1849. #define reg_trigger_module_sel_fd_len 6
  1850. #define reg_trigger_module_sel_fd_lsb 0
  1851. #define xd_p_reg_trigger_set_sel_fd 0xA2BA
  1852. #define reg_trigger_set_sel_fd_pos 0
  1853. #define reg_trigger_set_sel_fd_len 6
  1854. #define reg_trigger_set_sel_fd_lsb 0
  1855. #define xd_p_reg_fd_noname_7_0 0xA2BC
  1856. #define reg_fd_noname_7_0_pos 0
  1857. #define reg_fd_noname_7_0_len 8
  1858. #define reg_fd_noname_7_0_lsb 0
  1859. #define xd_p_reg_fd_noname_15_8 0xA2BD
  1860. #define reg_fd_noname_15_8_pos 0
  1861. #define reg_fd_noname_15_8_len 8
  1862. #define reg_fd_noname_15_8_lsb 8
  1863. #define xd_p_reg_fd_noname_23_16 0xA2BE
  1864. #define reg_fd_noname_23_16_pos 0
  1865. #define reg_fd_noname_23_16_len 8
  1866. #define reg_fd_noname_23_16_lsb 16
  1867. #define xd_p_reg_fd_noname_31_24 0xA2BF
  1868. #define reg_fd_noname_31_24_pos 0
  1869. #define reg_fd_noname_31_24_len 8
  1870. #define reg_fd_noname_31_24_lsb 24
  1871. #define xd_r_fd_fpcc_cp_corr_signn 0xA2C0
  1872. #define fd_fpcc_cp_corr_signn_pos 0
  1873. #define fd_fpcc_cp_corr_signn_len 8
  1874. #define fd_fpcc_cp_corr_signn_lsb 0
  1875. #define xd_p_reg_feq_s1 0xA2C1
  1876. #define reg_feq_s1_pos 0
  1877. #define reg_feq_s1_len 5
  1878. #define reg_feq_s1_lsb 0
  1879. #define xd_p_fd_fpcc_cp_corr_tone_th 0xA2C2
  1880. #define fd_fpcc_cp_corr_tone_th_pos 0
  1881. #define fd_fpcc_cp_corr_tone_th_len 6
  1882. #define fd_fpcc_cp_corr_tone_th_lsb 0
  1883. #define xd_p_fd_fpcc_cp_corr_symbol_log_th 0xA2C3
  1884. #define fd_fpcc_cp_corr_symbol_log_th_pos 0
  1885. #define fd_fpcc_cp_corr_symbol_log_th_len 4
  1886. #define fd_fpcc_cp_corr_symbol_log_th_lsb 0
  1887. #define xd_p_fd_fpcc_cp_corr_int 0xA2C4
  1888. #define fd_fpcc_cp_corr_int_pos 0
  1889. #define fd_fpcc_cp_corr_int_len 1
  1890. #define fd_fpcc_cp_corr_int_lsb 0
  1891. #define xd_p_reg_sfoe_ns_7_0 0xA320
  1892. #define reg_sfoe_ns_7_0_pos 0
  1893. #define reg_sfoe_ns_7_0_len 8
  1894. #define reg_sfoe_ns_7_0_lsb 0
  1895. #define xd_p_reg_sfoe_ns_14_8 0xA321
  1896. #define reg_sfoe_ns_14_8_pos 0
  1897. #define reg_sfoe_ns_14_8_len 7
  1898. #define reg_sfoe_ns_14_8_lsb 8
  1899. #define xd_p_reg_sfoe_c1_7_0 0xA322
  1900. #define reg_sfoe_c1_7_0_pos 0
  1901. #define reg_sfoe_c1_7_0_len 8
  1902. #define reg_sfoe_c1_7_0_lsb 0
  1903. #define xd_p_reg_sfoe_c1_15_8 0xA323
  1904. #define reg_sfoe_c1_15_8_pos 0
  1905. #define reg_sfoe_c1_15_8_len 8
  1906. #define reg_sfoe_c1_15_8_lsb 8
  1907. #define xd_p_reg_sfoe_c1_17_16 0xA324
  1908. #define reg_sfoe_c1_17_16_pos 0
  1909. #define reg_sfoe_c1_17_16_len 2
  1910. #define reg_sfoe_c1_17_16_lsb 16
  1911. #define xd_p_reg_sfoe_c2_7_0 0xA325
  1912. #define reg_sfoe_c2_7_0_pos 0
  1913. #define reg_sfoe_c2_7_0_len 8
  1914. #define reg_sfoe_c2_7_0_lsb 0
  1915. #define xd_p_reg_sfoe_c2_15_8 0xA326
  1916. #define reg_sfoe_c2_15_8_pos 0
  1917. #define reg_sfoe_c2_15_8_len 8
  1918. #define reg_sfoe_c2_15_8_lsb 8
  1919. #define xd_p_reg_sfoe_c2_17_16 0xA327
  1920. #define reg_sfoe_c2_17_16_pos 0
  1921. #define reg_sfoe_c2_17_16_len 2
  1922. #define reg_sfoe_c2_17_16_lsb 16
  1923. #define xd_r_reg_sfoe_out_9_2 0xA328
  1924. #define reg_sfoe_out_9_2_pos 0
  1925. #define reg_sfoe_out_9_2_len 8
  1926. #define reg_sfoe_out_9_2_lsb 0
  1927. #define xd_r_reg_sfoe_out_1_0 0xA329
  1928. #define reg_sfoe_out_1_0_pos 0
  1929. #define reg_sfoe_out_1_0_len 2
  1930. #define reg_sfoe_out_1_0_lsb 0
  1931. #define xd_p_reg_sfoe_lm_counter_th 0xA32A
  1932. #define reg_sfoe_lm_counter_th_pos 0
  1933. #define reg_sfoe_lm_counter_th_len 4
  1934. #define reg_sfoe_lm_counter_th_lsb 0
  1935. #define xd_p_reg_sfoe_convg_th 0xA32B
  1936. #define reg_sfoe_convg_th_pos 0
  1937. #define reg_sfoe_convg_th_len 8
  1938. #define reg_sfoe_convg_th_lsb 0
  1939. #define xd_p_reg_sfoe_divg_th 0xA32C
  1940. #define reg_sfoe_divg_th_pos 0
  1941. #define reg_sfoe_divg_th_len 8
  1942. #define reg_sfoe_divg_th_lsb 0
  1943. #define xd_p_fd_tpsd_en 0xA330
  1944. #define fd_tpsd_en_pos 0
  1945. #define fd_tpsd_en_len 1
  1946. #define fd_tpsd_en_lsb 0
  1947. #define xd_p_fd_tpsd_dis 0xA330
  1948. #define fd_tpsd_dis_pos 1
  1949. #define fd_tpsd_dis_len 1
  1950. #define fd_tpsd_dis_lsb 0
  1951. #define xd_p_fd_tpsd_rst 0xA330
  1952. #define fd_tpsd_rst_pos 2
  1953. #define fd_tpsd_rst_len 1
  1954. #define fd_tpsd_rst_lsb 0
  1955. #define xd_p_fd_tpsd_lock 0xA330
  1956. #define fd_tpsd_lock_pos 3
  1957. #define fd_tpsd_lock_len 1
  1958. #define fd_tpsd_lock_lsb 0
  1959. #define xd_r_fd_tpsd_s19 0xA330
  1960. #define fd_tpsd_s19_pos 4
  1961. #define fd_tpsd_s19_len 1
  1962. #define fd_tpsd_s19_lsb 0
  1963. #define xd_r_fd_tpsd_s17 0xA330
  1964. #define fd_tpsd_s17_pos 5
  1965. #define fd_tpsd_s17_len 1
  1966. #define fd_tpsd_s17_lsb 0
  1967. #define xd_p_fd_sfr_ste_en 0xA331
  1968. #define fd_sfr_ste_en_pos 0
  1969. #define fd_sfr_ste_en_len 1
  1970. #define fd_sfr_ste_en_lsb 0
  1971. #define xd_p_fd_sfr_ste_dis 0xA331
  1972. #define fd_sfr_ste_dis_pos 1
  1973. #define fd_sfr_ste_dis_len 1
  1974. #define fd_sfr_ste_dis_lsb 0
  1975. #define xd_p_fd_sfr_ste_rst 0xA331
  1976. #define fd_sfr_ste_rst_pos 2
  1977. #define fd_sfr_ste_rst_len 1
  1978. #define fd_sfr_ste_rst_lsb 0
  1979. #define xd_p_fd_sfr_ste_mode 0xA331
  1980. #define fd_sfr_ste_mode_pos 3
  1981. #define fd_sfr_ste_mode_len 1
  1982. #define fd_sfr_ste_mode_lsb 0
  1983. #define xd_p_fd_sfr_ste_done 0xA331
  1984. #define fd_sfr_ste_done_pos 4
  1985. #define fd_sfr_ste_done_len 1
  1986. #define fd_sfr_ste_done_lsb 0
  1987. #define xd_p_reg_cfoe_ffoe_en 0xA332
  1988. #define reg_cfoe_ffoe_en_pos 0
  1989. #define reg_cfoe_ffoe_en_len 1
  1990. #define reg_cfoe_ffoe_en_lsb 0
  1991. #define xd_p_reg_cfoe_ffoe_dis 0xA332
  1992. #define reg_cfoe_ffoe_dis_pos 1
  1993. #define reg_cfoe_ffoe_dis_len 1
  1994. #define reg_cfoe_ffoe_dis_lsb 0
  1995. #define xd_p_reg_cfoe_ffoe_rst 0xA332
  1996. #define reg_cfoe_ffoe_rst_pos 2
  1997. #define reg_cfoe_ffoe_rst_len 1
  1998. #define reg_cfoe_ffoe_rst_lsb 0
  1999. #define xd_p_reg_cfoe_ifoe_en 0xA332
  2000. #define reg_cfoe_ifoe_en_pos 3
  2001. #define reg_cfoe_ifoe_en_len 1
  2002. #define reg_cfoe_ifoe_en_lsb 0
  2003. #define xd_p_reg_cfoe_ifoe_dis 0xA332
  2004. #define reg_cfoe_ifoe_dis_pos 4
  2005. #define reg_cfoe_ifoe_dis_len 1
  2006. #define reg_cfoe_ifoe_dis_lsb 0
  2007. #define xd_p_reg_cfoe_ifoe_rst 0xA332
  2008. #define reg_cfoe_ifoe_rst_pos 5
  2009. #define reg_cfoe_ifoe_rst_len 1
  2010. #define reg_cfoe_ifoe_rst_lsb 0
  2011. #define xd_p_reg_cfoe_fot_en 0xA332
  2012. #define reg_cfoe_fot_en_pos 6
  2013. #define reg_cfoe_fot_en_len 1
  2014. #define reg_cfoe_fot_en_lsb 0
  2015. #define xd_p_reg_cfoe_fot_lm_en 0xA332
  2016. #define reg_cfoe_fot_lm_en_pos 7
  2017. #define reg_cfoe_fot_lm_en_len 1
  2018. #define reg_cfoe_fot_lm_en_lsb 0
  2019. #define xd_p_reg_cfoe_fot_rst 0xA333
  2020. #define reg_cfoe_fot_rst_pos 0
  2021. #define reg_cfoe_fot_rst_len 1
  2022. #define reg_cfoe_fot_rst_lsb 0
  2023. #define xd_r_fd_cfoe_ffoe_done 0xA333
  2024. #define fd_cfoe_ffoe_done_pos 1
  2025. #define fd_cfoe_ffoe_done_len 1
  2026. #define fd_cfoe_ffoe_done_lsb 0
  2027. #define xd_p_fd_cfoe_metric_vld 0xA333
  2028. #define fd_cfoe_metric_vld_pos 2
  2029. #define fd_cfoe_metric_vld_len 1
  2030. #define fd_cfoe_metric_vld_lsb 0
  2031. #define xd_p_reg_cfoe_ifod_vld 0xA333
  2032. #define reg_cfoe_ifod_vld_pos 3
  2033. #define reg_cfoe_ifod_vld_len 1
  2034. #define reg_cfoe_ifod_vld_lsb 0
  2035. #define xd_r_fd_cfoe_ifoe_done 0xA333
  2036. #define fd_cfoe_ifoe_done_pos 4
  2037. #define fd_cfoe_ifoe_done_len 1
  2038. #define fd_cfoe_ifoe_done_lsb 0
  2039. #define xd_r_fd_cfoe_fot_valid 0xA333
  2040. #define fd_cfoe_fot_valid_pos 5
  2041. #define fd_cfoe_fot_valid_len 1
  2042. #define fd_cfoe_fot_valid_lsb 0
  2043. #define xd_p_reg_cfoe_divg_int 0xA333
  2044. #define reg_cfoe_divg_int_pos 6
  2045. #define reg_cfoe_divg_int_len 1
  2046. #define reg_cfoe_divg_int_lsb 0
  2047. #define xd_r_reg_cfoe_divg_flag 0xA333
  2048. #define reg_cfoe_divg_flag_pos 7
  2049. #define reg_cfoe_divg_flag_len 1
  2050. #define reg_cfoe_divg_flag_lsb 0
  2051. #define xd_p_reg_sfoe_en 0xA334
  2052. #define reg_sfoe_en_pos 0
  2053. #define reg_sfoe_en_len 1
  2054. #define reg_sfoe_en_lsb 0
  2055. #define xd_p_reg_sfoe_dis 0xA334
  2056. #define reg_sfoe_dis_pos 1
  2057. #define reg_sfoe_dis_len 1
  2058. #define reg_sfoe_dis_lsb 0
  2059. #define xd_p_reg_sfoe_rst 0xA334
  2060. #define reg_sfoe_rst_pos 2
  2061. #define reg_sfoe_rst_len 1
  2062. #define reg_sfoe_rst_lsb 0
  2063. #define xd_p_reg_sfoe_vld_int 0xA334
  2064. #define reg_sfoe_vld_int_pos 3
  2065. #define reg_sfoe_vld_int_len 1
  2066. #define reg_sfoe_vld_int_lsb 0
  2067. #define xd_p_reg_sfoe_lm_en 0xA334
  2068. #define reg_sfoe_lm_en_pos 4
  2069. #define reg_sfoe_lm_en_len 1
  2070. #define reg_sfoe_lm_en_lsb 0
  2071. #define xd_p_reg_sfoe_divg_int 0xA334
  2072. #define reg_sfoe_divg_int_pos 5
  2073. #define reg_sfoe_divg_int_len 1
  2074. #define reg_sfoe_divg_int_lsb 0
  2075. #define xd_r_reg_sfoe_divg_flag 0xA334
  2076. #define reg_sfoe_divg_flag_pos 6
  2077. #define reg_sfoe_divg_flag_len 1
  2078. #define reg_sfoe_divg_flag_lsb 0
  2079. #define xd_p_reg_fft_rst 0xA335
  2080. #define reg_fft_rst_pos 0
  2081. #define reg_fft_rst_len 1
  2082. #define reg_fft_rst_lsb 0
  2083. #define xd_p_reg_fft_fast_beacon 0xA335
  2084. #define reg_fft_fast_beacon_pos 1
  2085. #define reg_fft_fast_beacon_len 1
  2086. #define reg_fft_fast_beacon_lsb 0
  2087. #define xd_p_reg_fft_fast_valid 0xA335
  2088. #define reg_fft_fast_valid_pos 2
  2089. #define reg_fft_fast_valid_len 1
  2090. #define reg_fft_fast_valid_lsb 0
  2091. #define xd_p_reg_fft_mask_en 0xA335
  2092. #define reg_fft_mask_en_pos 3
  2093. #define reg_fft_mask_en_len 1
  2094. #define reg_fft_mask_en_lsb 0
  2095. #define xd_p_reg_fft_crc_en 0xA335
  2096. #define reg_fft_crc_en_pos 4
  2097. #define reg_fft_crc_en_len 1
  2098. #define reg_fft_crc_en_lsb 0
  2099. #define xd_p_reg_finr_en 0xA336
  2100. #define reg_finr_en_pos 0
  2101. #define reg_finr_en_len 1
  2102. #define reg_finr_en_lsb 0
  2103. #define xd_p_fd_fste_en 0xA337
  2104. #define fd_fste_en_pos 1
  2105. #define fd_fste_en_len 1
  2106. #define fd_fste_en_lsb 0
  2107. #define xd_p_fd_sqi_tps_level_shift 0xA338
  2108. #define fd_sqi_tps_level_shift_pos 0
  2109. #define fd_sqi_tps_level_shift_len 8
  2110. #define fd_sqi_tps_level_shift_lsb 0
  2111. #define xd_p_fd_pilot_ma_len 0xA339
  2112. #define fd_pilot_ma_len_pos 0
  2113. #define fd_pilot_ma_len_len 6
  2114. #define fd_pilot_ma_len_lsb 0
  2115. #define xd_p_fd_tps_ma_len 0xA33A
  2116. #define fd_tps_ma_len_pos 0
  2117. #define fd_tps_ma_len_len 6
  2118. #define fd_tps_ma_len_lsb 0
  2119. #define xd_p_fd_sqi_s3 0xA33B
  2120. #define fd_sqi_s3_pos 0
  2121. #define fd_sqi_s3_len 8
  2122. #define fd_sqi_s3_lsb 0
  2123. #define xd_p_fd_sqi_dummy_reg_0 0xA33C
  2124. #define fd_sqi_dummy_reg_0_pos 0
  2125. #define fd_sqi_dummy_reg_0_len 1
  2126. #define fd_sqi_dummy_reg_0_lsb 0
  2127. #define xd_p_fd_sqi_debug_sel 0xA33C
  2128. #define fd_sqi_debug_sel_pos 1
  2129. #define fd_sqi_debug_sel_len 2
  2130. #define fd_sqi_debug_sel_lsb 0
  2131. #define xd_p_fd_sqi_s2 0xA33C
  2132. #define fd_sqi_s2_pos 3
  2133. #define fd_sqi_s2_len 5
  2134. #define fd_sqi_s2_lsb 0
  2135. #define xd_p_fd_sqi_dummy_reg_1 0xA33D
  2136. #define fd_sqi_dummy_reg_1_pos 0
  2137. #define fd_sqi_dummy_reg_1_len 1
  2138. #define fd_sqi_dummy_reg_1_lsb 0
  2139. #define xd_p_fd_inr_ignore 0xA33D
  2140. #define fd_inr_ignore_pos 1
  2141. #define fd_inr_ignore_len 1
  2142. #define fd_inr_ignore_lsb 0
  2143. #define xd_p_fd_pilot_ignore 0xA33D
  2144. #define fd_pilot_ignore_pos 2
  2145. #define fd_pilot_ignore_len 1
  2146. #define fd_pilot_ignore_lsb 0
  2147. #define xd_p_fd_etps_ignore 0xA33D
  2148. #define fd_etps_ignore_pos 3
  2149. #define fd_etps_ignore_len 1
  2150. #define fd_etps_ignore_lsb 0
  2151. #define xd_p_fd_sqi_s1 0xA33D
  2152. #define fd_sqi_s1_pos 4
  2153. #define fd_sqi_s1_len 4
  2154. #define fd_sqi_s1_lsb 0
  2155. #define xd_p_reg_fste_ehw_7_0 0xA33E
  2156. #define reg_fste_ehw_7_0_pos 0
  2157. #define reg_fste_ehw_7_0_len 8
  2158. #define reg_fste_ehw_7_0_lsb 0
  2159. #define xd_p_reg_fste_ehw_9_8 0xA33F
  2160. #define reg_fste_ehw_9_8_pos 0
  2161. #define reg_fste_ehw_9_8_len 2
  2162. #define reg_fste_ehw_9_8_lsb 8
  2163. #define xd_p_reg_fste_i_adj_vld 0xA33F
  2164. #define reg_fste_i_adj_vld_pos 2
  2165. #define reg_fste_i_adj_vld_len 1
  2166. #define reg_fste_i_adj_vld_lsb 0
  2167. #define xd_p_reg_fste_phase_ini_7_0 0xA340
  2168. #define reg_fste_phase_ini_7_0_pos 0
  2169. #define reg_fste_phase_ini_7_0_len 8
  2170. #define reg_fste_phase_ini_7_0_lsb 0
  2171. #define xd_p_reg_fste_phase_ini_11_8 0xA341
  2172. #define reg_fste_phase_ini_11_8_pos 0
  2173. #define reg_fste_phase_ini_11_8_len 4
  2174. #define reg_fste_phase_ini_11_8_lsb 8
  2175. #define xd_p_reg_fste_phase_inc_3_0 0xA341
  2176. #define reg_fste_phase_inc_3_0_pos 4
  2177. #define reg_fste_phase_inc_3_0_len 4
  2178. #define reg_fste_phase_inc_3_0_lsb 0
  2179. #define xd_p_reg_fste_phase_inc_11_4 0xA342
  2180. #define reg_fste_phase_inc_11_4_pos 0
  2181. #define reg_fste_phase_inc_11_4_len 8
  2182. #define reg_fste_phase_inc_11_4_lsb 4
  2183. #define xd_p_reg_fste_acum_cost_cnt_max 0xA343
  2184. #define reg_fste_acum_cost_cnt_max_pos 0
  2185. #define reg_fste_acum_cost_cnt_max_len 4
  2186. #define reg_fste_acum_cost_cnt_max_lsb 0
  2187. #define xd_p_reg_fste_step_size_std 0xA343
  2188. #define reg_fste_step_size_std_pos 4
  2189. #define reg_fste_step_size_std_len 4
  2190. #define reg_fste_step_size_std_lsb 0
  2191. #define xd_p_reg_fste_step_size_max 0xA344
  2192. #define reg_fste_step_size_max_pos 0
  2193. #define reg_fste_step_size_max_len 4
  2194. #define reg_fste_step_size_max_lsb 0
  2195. #define xd_p_reg_fste_step_size_min 0xA344
  2196. #define reg_fste_step_size_min_pos 4
  2197. #define reg_fste_step_size_min_len 4
  2198. #define reg_fste_step_size_min_lsb 0
  2199. #define xd_p_reg_fste_frac_step_size_7_0 0xA345
  2200. #define reg_fste_frac_step_size_7_0_pos 0
  2201. #define reg_fste_frac_step_size_7_0_len 8
  2202. #define reg_fste_frac_step_size_7_0_lsb 0
  2203. #define xd_p_reg_fste_frac_step_size_15_8 0xA346
  2204. #define reg_fste_frac_step_size_15_8_pos 0
  2205. #define reg_fste_frac_step_size_15_8_len 8
  2206. #define reg_fste_frac_step_size_15_8_lsb 8
  2207. #define xd_p_reg_fste_frac_step_size_19_16 0xA347
  2208. #define reg_fste_frac_step_size_19_16_pos 0
  2209. #define reg_fste_frac_step_size_19_16_len 4
  2210. #define reg_fste_frac_step_size_19_16_lsb 16
  2211. #define xd_p_reg_fste_rpd_dir_cnt_max 0xA347
  2212. #define reg_fste_rpd_dir_cnt_max_pos 4
  2213. #define reg_fste_rpd_dir_cnt_max_len 4
  2214. #define reg_fste_rpd_dir_cnt_max_lsb 0
  2215. #define xd_p_reg_fste_ehs 0xA348
  2216. #define reg_fste_ehs_pos 0
  2217. #define reg_fste_ehs_len 4
  2218. #define reg_fste_ehs_lsb 0
  2219. #define xd_p_reg_fste_frac_cost_cnt_max_3_0 0xA348
  2220. #define reg_fste_frac_cost_cnt_max_3_0_pos 4
  2221. #define reg_fste_frac_cost_cnt_max_3_0_len 4
  2222. #define reg_fste_frac_cost_cnt_max_3_0_lsb 0
  2223. #define xd_p_reg_fste_frac_cost_cnt_max_9_4 0xA349
  2224. #define reg_fste_frac_cost_cnt_max_9_4_pos 0
  2225. #define reg_fste_frac_cost_cnt_max_9_4_len 6
  2226. #define reg_fste_frac_cost_cnt_max_9_4_lsb 4
  2227. #define xd_p_reg_fste_w0_7_0 0xA34A
  2228. #define reg_fste_w0_7_0_pos 0
  2229. #define reg_fste_w0_7_0_len 8
  2230. #define reg_fste_w0_7_0_lsb 0
  2231. #define xd_p_reg_fste_w0_11_8 0xA34B
  2232. #define reg_fste_w0_11_8_pos 0
  2233. #define reg_fste_w0_11_8_len 4
  2234. #define reg_fste_w0_11_8_lsb 8
  2235. #define xd_p_reg_fste_w1_3_0 0xA34B
  2236. #define reg_fste_w1_3_0_pos 4
  2237. #define reg_fste_w1_3_0_len 4
  2238. #define reg_fste_w1_3_0_lsb 0
  2239. #define xd_p_reg_fste_w1_11_4 0xA34C
  2240. #define reg_fste_w1_11_4_pos 0
  2241. #define reg_fste_w1_11_4_len 8
  2242. #define reg_fste_w1_11_4_lsb 4
  2243. #define xd_p_reg_fste_w2_7_0 0xA34D
  2244. #define reg_fste_w2_7_0_pos 0
  2245. #define reg_fste_w2_7_0_len 8
  2246. #define reg_fste_w2_7_0_lsb 0
  2247. #define xd_p_reg_fste_w2_11_8 0xA34E
  2248. #define reg_fste_w2_11_8_pos 0
  2249. #define reg_fste_w2_11_8_len 4
  2250. #define reg_fste_w2_11_8_lsb 8
  2251. #define xd_p_reg_fste_w3_3_0 0xA34E
  2252. #define reg_fste_w3_3_0_pos 4
  2253. #define reg_fste_w3_3_0_len 4
  2254. #define reg_fste_w3_3_0_lsb 0
  2255. #define xd_p_reg_fste_w3_11_4 0xA34F
  2256. #define reg_fste_w3_11_4_pos 0
  2257. #define reg_fste_w3_11_4_len 8
  2258. #define reg_fste_w3_11_4_lsb 4
  2259. #define xd_p_reg_fste_w4_7_0 0xA350
  2260. #define reg_fste_w4_7_0_pos 0
  2261. #define reg_fste_w4_7_0_len 8
  2262. #define reg_fste_w4_7_0_lsb 0
  2263. #define xd_p_reg_fste_w4_11_8 0xA351
  2264. #define reg_fste_w4_11_8_pos 0
  2265. #define reg_fste_w4_11_8_len 4
  2266. #define reg_fste_w4_11_8_lsb 8
  2267. #define xd_p_reg_fste_w5_3_0 0xA351
  2268. #define reg_fste_w5_3_0_pos 4
  2269. #define reg_fste_w5_3_0_len 4
  2270. #define reg_fste_w5_3_0_lsb 0
  2271. #define xd_p_reg_fste_w5_11_4 0xA352
  2272. #define reg_fste_w5_11_4_pos 0
  2273. #define reg_fste_w5_11_4_len 8
  2274. #define reg_fste_w5_11_4_lsb 4
  2275. #define xd_p_reg_fste_w6_7_0 0xA353
  2276. #define reg_fste_w6_7_0_pos 0
  2277. #define reg_fste_w6_7_0_len 8
  2278. #define reg_fste_w6_7_0_lsb 0
  2279. #define xd_p_reg_fste_w6_11_8 0xA354
  2280. #define reg_fste_w6_11_8_pos 0
  2281. #define reg_fste_w6_11_8_len 4
  2282. #define reg_fste_w6_11_8_lsb 8
  2283. #define xd_p_reg_fste_w7_3_0 0xA354
  2284. #define reg_fste_w7_3_0_pos 4
  2285. #define reg_fste_w7_3_0_len 4
  2286. #define reg_fste_w7_3_0_lsb 0
  2287. #define xd_p_reg_fste_w7_11_4 0xA355
  2288. #define reg_fste_w7_11_4_pos 0
  2289. #define reg_fste_w7_11_4_len 8
  2290. #define reg_fste_w7_11_4_lsb 4
  2291. #define xd_p_reg_fste_w8_7_0 0xA356
  2292. #define reg_fste_w8_7_0_pos 0
  2293. #define reg_fste_w8_7_0_len 8
  2294. #define reg_fste_w8_7_0_lsb 0
  2295. #define xd_p_reg_fste_w8_11_8 0xA357
  2296. #define reg_fste_w8_11_8_pos 0
  2297. #define reg_fste_w8_11_8_len 4
  2298. #define reg_fste_w8_11_8_lsb 8
  2299. #define xd_p_reg_fste_w9_3_0 0xA357
  2300. #define reg_fste_w9_3_0_pos 4
  2301. #define reg_fste_w9_3_0_len 4
  2302. #define reg_fste_w9_3_0_lsb 0
  2303. #define xd_p_reg_fste_w9_11_4 0xA358
  2304. #define reg_fste_w9_11_4_pos 0
  2305. #define reg_fste_w9_11_4_len 8
  2306. #define reg_fste_w9_11_4_lsb 4
  2307. #define xd_p_reg_fste_wa_7_0 0xA359
  2308. #define reg_fste_wa_7_0_pos 0
  2309. #define reg_fste_wa_7_0_len 8
  2310. #define reg_fste_wa_7_0_lsb 0
  2311. #define xd_p_reg_fste_wa_11_8 0xA35A
  2312. #define reg_fste_wa_11_8_pos 0
  2313. #define reg_fste_wa_11_8_len 4
  2314. #define reg_fste_wa_11_8_lsb 8
  2315. #define xd_p_reg_fste_wb_3_0 0xA35A
  2316. #define reg_fste_wb_3_0_pos 4
  2317. #define reg_fste_wb_3_0_len 4
  2318. #define reg_fste_wb_3_0_lsb 0
  2319. #define xd_p_reg_fste_wb_11_4 0xA35B
  2320. #define reg_fste_wb_11_4_pos 0
  2321. #define reg_fste_wb_11_4_len 8
  2322. #define reg_fste_wb_11_4_lsb 4
  2323. #define xd_r_fd_fste_i_adj 0xA35C
  2324. #define fd_fste_i_adj_pos 0
  2325. #define fd_fste_i_adj_len 5
  2326. #define fd_fste_i_adj_lsb 0
  2327. #define xd_r_fd_fste_f_adj_7_0 0xA35D
  2328. #define fd_fste_f_adj_7_0_pos 0
  2329. #define fd_fste_f_adj_7_0_len 8
  2330. #define fd_fste_f_adj_7_0_lsb 0
  2331. #define xd_r_fd_fste_f_adj_15_8 0xA35E
  2332. #define fd_fste_f_adj_15_8_pos 0
  2333. #define fd_fste_f_adj_15_8_len 8
  2334. #define fd_fste_f_adj_15_8_lsb 8
  2335. #define xd_r_fd_fste_f_adj_19_16 0xA35F
  2336. #define fd_fste_f_adj_19_16_pos 0
  2337. #define fd_fste_f_adj_19_16_len 4
  2338. #define fd_fste_f_adj_19_16_lsb 16
  2339. #define xd_p_reg_feq_Leak_Bypass 0xA366
  2340. #define reg_feq_Leak_Bypass_pos 0
  2341. #define reg_feq_Leak_Bypass_len 1
  2342. #define reg_feq_Leak_Bypass_lsb 0
  2343. #define xd_p_reg_feq_Leak_Mneg1 0xA366
  2344. #define reg_feq_Leak_Mneg1_pos 1
  2345. #define reg_feq_Leak_Mneg1_len 3
  2346. #define reg_feq_Leak_Mneg1_lsb 0
  2347. #define xd_p_reg_feq_Leak_B_ShiftQ 0xA366
  2348. #define reg_feq_Leak_B_ShiftQ_pos 4
  2349. #define reg_feq_Leak_B_ShiftQ_len 4
  2350. #define reg_feq_Leak_B_ShiftQ_lsb 0
  2351. #define xd_p_reg_feq_Leak_B_Float0 0xA367
  2352. #define reg_feq_Leak_B_Float0_pos 0
  2353. #define reg_feq_Leak_B_Float0_len 8
  2354. #define reg_feq_Leak_B_Float0_lsb 0
  2355. #define xd_p_reg_feq_Leak_B_Float1 0xA368
  2356. #define reg_feq_Leak_B_Float1_pos 0
  2357. #define reg_feq_Leak_B_Float1_len 8
  2358. #define reg_feq_Leak_B_Float1_lsb 0
  2359. #define xd_p_reg_feq_Leak_B_Float2 0xA369
  2360. #define reg_feq_Leak_B_Float2_pos 0
  2361. #define reg_feq_Leak_B_Float2_len 8
  2362. #define reg_feq_Leak_B_Float2_lsb 0
  2363. #define xd_p_reg_feq_Leak_B_Float3 0xA36A
  2364. #define reg_feq_Leak_B_Float3_pos 0
  2365. #define reg_feq_Leak_B_Float3_len 8
  2366. #define reg_feq_Leak_B_Float3_lsb 0
  2367. #define xd_p_reg_feq_Leak_B_Float4 0xA36B
  2368. #define reg_feq_Leak_B_Float4_pos 0
  2369. #define reg_feq_Leak_B_Float4_len 8
  2370. #define reg_feq_Leak_B_Float4_lsb 0
  2371. #define xd_p_reg_feq_Leak_B_Float5 0xA36C
  2372. #define reg_feq_Leak_B_Float5_pos 0
  2373. #define reg_feq_Leak_B_Float5_len 8
  2374. #define reg_feq_Leak_B_Float5_lsb 0
  2375. #define xd_p_reg_feq_Leak_B_Float6 0xA36D
  2376. #define reg_feq_Leak_B_Float6_pos 0
  2377. #define reg_feq_Leak_B_Float6_len 8
  2378. #define reg_feq_Leak_B_Float6_lsb 0
  2379. #define xd_p_reg_feq_Leak_B_Float7 0xA36E
  2380. #define reg_feq_Leak_B_Float7_pos 0
  2381. #define reg_feq_Leak_B_Float7_len 8
  2382. #define reg_feq_Leak_B_Float7_lsb 0
  2383. #define xd_r_reg_feq_data_h2_7_0 0xA36F
  2384. #define reg_feq_data_h2_7_0_pos 0
  2385. #define reg_feq_data_h2_7_0_len 8
  2386. #define reg_feq_data_h2_7_0_lsb 0
  2387. #define xd_r_reg_feq_data_h2_9_8 0xA370
  2388. #define reg_feq_data_h2_9_8_pos 0
  2389. #define reg_feq_data_h2_9_8_len 2
  2390. #define reg_feq_data_h2_9_8_lsb 8
  2391. #define xd_p_reg_feq_leak_use_slice_tps 0xA371
  2392. #define reg_feq_leak_use_slice_tps_pos 0
  2393. #define reg_feq_leak_use_slice_tps_len 1
  2394. #define reg_feq_leak_use_slice_tps_lsb 0
  2395. #define xd_p_reg_feq_read_update 0xA371
  2396. #define reg_feq_read_update_pos 1
  2397. #define reg_feq_read_update_len 1
  2398. #define reg_feq_read_update_lsb 0
  2399. #define xd_p_reg_feq_data_vld 0xA371
  2400. #define reg_feq_data_vld_pos 2
  2401. #define reg_feq_data_vld_len 1
  2402. #define reg_feq_data_vld_lsb 0
  2403. #define xd_p_reg_feq_tone_idx_4_0 0xA371
  2404. #define reg_feq_tone_idx_4_0_pos 3
  2405. #define reg_feq_tone_idx_4_0_len 5
  2406. #define reg_feq_tone_idx_4_0_lsb 0
  2407. #define xd_p_reg_feq_tone_idx_12_5 0xA372
  2408. #define reg_feq_tone_idx_12_5_pos 0
  2409. #define reg_feq_tone_idx_12_5_len 8
  2410. #define reg_feq_tone_idx_12_5_lsb 5
  2411. #define xd_r_reg_feq_data_re_7_0 0xA373
  2412. #define reg_feq_data_re_7_0_pos 0
  2413. #define reg_feq_data_re_7_0_len 8
  2414. #define reg_feq_data_re_7_0_lsb 0
  2415. #define xd_r_reg_feq_data_re_10_8 0xA374
  2416. #define reg_feq_data_re_10_8_pos 0
  2417. #define reg_feq_data_re_10_8_len 3
  2418. #define reg_feq_data_re_10_8_lsb 8
  2419. #define xd_r_reg_feq_data_im_7_0 0xA375
  2420. #define reg_feq_data_im_7_0_pos 0
  2421. #define reg_feq_data_im_7_0_len 8
  2422. #define reg_feq_data_im_7_0_lsb 0
  2423. #define xd_r_reg_feq_data_im_10_8 0xA376
  2424. #define reg_feq_data_im_10_8_pos 0
  2425. #define reg_feq_data_im_10_8_len 3
  2426. #define reg_feq_data_im_10_8_lsb 8
  2427. #define xd_r_reg_feq_y_re 0xA377
  2428. #define reg_feq_y_re_pos 0
  2429. #define reg_feq_y_re_len 8
  2430. #define reg_feq_y_re_lsb 0
  2431. #define xd_r_reg_feq_y_im 0xA378
  2432. #define reg_feq_y_im_pos 0
  2433. #define reg_feq_y_im_len 8
  2434. #define reg_feq_y_im_lsb 0
  2435. #define xd_r_reg_feq_h_re_7_0 0xA379
  2436. #define reg_feq_h_re_7_0_pos 0
  2437. #define reg_feq_h_re_7_0_len 8
  2438. #define reg_feq_h_re_7_0_lsb 0
  2439. #define xd_r_reg_feq_h_re_8 0xA37A
  2440. #define reg_feq_h_re_8_pos 0
  2441. #define reg_feq_h_re_8_len 1
  2442. #define reg_feq_h_re_8_lsb 0
  2443. #define xd_r_reg_feq_h_im_7_0 0xA37B
  2444. #define reg_feq_h_im_7_0_pos 0
  2445. #define reg_feq_h_im_7_0_len 8
  2446. #define reg_feq_h_im_7_0_lsb 0
  2447. #define xd_r_reg_feq_h_im_8 0xA37C
  2448. #define reg_feq_h_im_8_pos 0
  2449. #define reg_feq_h_im_8_len 1
  2450. #define reg_feq_h_im_8_lsb 0
  2451. #define xd_p_fec_super_frm_unit_7_0 0xA380
  2452. #define fec_super_frm_unit_7_0_pos 0
  2453. #define fec_super_frm_unit_7_0_len 8
  2454. #define fec_super_frm_unit_7_0_lsb 0
  2455. #define xd_p_fec_super_frm_unit_15_8 0xA381
  2456. #define fec_super_frm_unit_15_8_pos 0
  2457. #define fec_super_frm_unit_15_8_len 8
  2458. #define fec_super_frm_unit_15_8_lsb 8
  2459. #define xd_r_fec_vtb_err_bit_cnt_7_0 0xA382
  2460. #define fec_vtb_err_bit_cnt_7_0_pos 0
  2461. #define fec_vtb_err_bit_cnt_7_0_len 8
  2462. #define fec_vtb_err_bit_cnt_7_0_lsb 0
  2463. #define xd_r_fec_vtb_err_bit_cnt_15_8 0xA383
  2464. #define fec_vtb_err_bit_cnt_15_8_pos 0
  2465. #define fec_vtb_err_bit_cnt_15_8_len 8
  2466. #define fec_vtb_err_bit_cnt_15_8_lsb 8
  2467. #define xd_r_fec_vtb_err_bit_cnt_23_16 0xA384
  2468. #define fec_vtb_err_bit_cnt_23_16_pos 0
  2469. #define fec_vtb_err_bit_cnt_23_16_len 8
  2470. #define fec_vtb_err_bit_cnt_23_16_lsb 16
  2471. #define xd_p_fec_rsd_packet_unit_7_0 0xA385
  2472. #define fec_rsd_packet_unit_7_0_pos 0
  2473. #define fec_rsd_packet_unit_7_0_len 8
  2474. #define fec_rsd_packet_unit_7_0_lsb 0
  2475. #define xd_p_fec_rsd_packet_unit_15_8 0xA386
  2476. #define fec_rsd_packet_unit_15_8_pos 0
  2477. #define fec_rsd_packet_unit_15_8_len 8
  2478. #define fec_rsd_packet_unit_15_8_lsb 8
  2479. #define xd_r_fec_rsd_bit_err_cnt_7_0 0xA387
  2480. #define fec_rsd_bit_err_cnt_7_0_pos 0
  2481. #define fec_rsd_bit_err_cnt_7_0_len 8
  2482. #define fec_rsd_bit_err_cnt_7_0_lsb 0
  2483. #define xd_r_fec_rsd_bit_err_cnt_15_8 0xA388
  2484. #define fec_rsd_bit_err_cnt_15_8_pos 0
  2485. #define fec_rsd_bit_err_cnt_15_8_len 8
  2486. #define fec_rsd_bit_err_cnt_15_8_lsb 8
  2487. #define xd_r_fec_rsd_bit_err_cnt_23_16 0xA389
  2488. #define fec_rsd_bit_err_cnt_23_16_pos 0
  2489. #define fec_rsd_bit_err_cnt_23_16_len 8
  2490. #define fec_rsd_bit_err_cnt_23_16_lsb 16
  2491. #define xd_r_fec_rsd_abort_packet_cnt_7_0 0xA38A
  2492. #define fec_rsd_abort_packet_cnt_7_0_pos 0
  2493. #define fec_rsd_abort_packet_cnt_7_0_len 8
  2494. #define fec_rsd_abort_packet_cnt_7_0_lsb 0
  2495. #define xd_r_fec_rsd_abort_packet_cnt_15_8 0xA38B
  2496. #define fec_rsd_abort_packet_cnt_15_8_pos 0
  2497. #define fec_rsd_abort_packet_cnt_15_8_len 8
  2498. #define fec_rsd_abort_packet_cnt_15_8_lsb 8
  2499. #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xA38C
  2500. #define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
  2501. #define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
  2502. #define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
  2503. #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xA38D
  2504. #define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
  2505. #define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
  2506. #define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
  2507. #define xd_p_fec_RS_TH_1_7_0 0xA38E
  2508. #define fec_RS_TH_1_7_0_pos 0
  2509. #define fec_RS_TH_1_7_0_len 8
  2510. #define fec_RS_TH_1_7_0_lsb 0
  2511. #define xd_p_fec_RS_TH_1_15_8 0xA38F
  2512. #define fec_RS_TH_1_15_8_pos 0
  2513. #define fec_RS_TH_1_15_8_len 8
  2514. #define fec_RS_TH_1_15_8_lsb 8
  2515. #define xd_p_fec_RS_TH_2 0xA390
  2516. #define fec_RS_TH_2_pos 0
  2517. #define fec_RS_TH_2_len 8
  2518. #define fec_RS_TH_2_lsb 0
  2519. #define xd_p_fec_mon_en 0xA391
  2520. #define fec_mon_en_pos 0
  2521. #define fec_mon_en_len 1
  2522. #define fec_mon_en_lsb 0
  2523. #define xd_p_reg_b8to47 0xA391
  2524. #define reg_b8to47_pos 1
  2525. #define reg_b8to47_len 1
  2526. #define reg_b8to47_lsb 0
  2527. #define xd_p_reg_rsd_sync_rep 0xA391
  2528. #define reg_rsd_sync_rep_pos 2
  2529. #define reg_rsd_sync_rep_len 1
  2530. #define reg_rsd_sync_rep_lsb 0
  2531. #define xd_p_fec_rsd_retrain_rst 0xA391
  2532. #define fec_rsd_retrain_rst_pos 3
  2533. #define fec_rsd_retrain_rst_len 1
  2534. #define fec_rsd_retrain_rst_lsb 0
  2535. #define xd_r_fec_rsd_ber_rdy 0xA391
  2536. #define fec_rsd_ber_rdy_pos 4
  2537. #define fec_rsd_ber_rdy_len 1
  2538. #define fec_rsd_ber_rdy_lsb 0
  2539. #define xd_p_fec_rsd_ber_rst 0xA391
  2540. #define fec_rsd_ber_rst_pos 5
  2541. #define fec_rsd_ber_rst_len 1
  2542. #define fec_rsd_ber_rst_lsb 0
  2543. #define xd_r_fec_vtb_ber_rdy 0xA391
  2544. #define fec_vtb_ber_rdy_pos 6
  2545. #define fec_vtb_ber_rdy_len 1
  2546. #define fec_vtb_ber_rdy_lsb 0
  2547. #define xd_p_fec_vtb_ber_rst 0xA391
  2548. #define fec_vtb_ber_rst_pos 7
  2549. #define fec_vtb_ber_rst_len 1
  2550. #define fec_vtb_ber_rst_lsb 0
  2551. #define xd_p_reg_vtb_clk40en 0xA392
  2552. #define reg_vtb_clk40en_pos 0
  2553. #define reg_vtb_clk40en_len 1
  2554. #define reg_vtb_clk40en_lsb 0
  2555. #define xd_p_fec_vtb_rsd_mon_en 0xA392
  2556. #define fec_vtb_rsd_mon_en_pos 1
  2557. #define fec_vtb_rsd_mon_en_len 1
  2558. #define fec_vtb_rsd_mon_en_lsb 0
  2559. #define xd_p_reg_fec_data_en 0xA392
  2560. #define reg_fec_data_en_pos 2
  2561. #define reg_fec_data_en_len 1
  2562. #define reg_fec_data_en_lsb 0
  2563. #define xd_p_fec_dummy_reg_2 0xA392
  2564. #define fec_dummy_reg_2_pos 3
  2565. #define fec_dummy_reg_2_len 3
  2566. #define fec_dummy_reg_2_lsb 0
  2567. #define xd_p_reg_sync_chk 0xA392
  2568. #define reg_sync_chk_pos 6
  2569. #define reg_sync_chk_len 1
  2570. #define reg_sync_chk_lsb 0
  2571. #define xd_p_fec_rsd_bypass 0xA392
  2572. #define fec_rsd_bypass_pos 7
  2573. #define fec_rsd_bypass_len 1
  2574. #define fec_rsd_bypass_lsb 0
  2575. #define xd_p_fec_sw_rst 0xA393
  2576. #define fec_sw_rst_pos 0
  2577. #define fec_sw_rst_len 1
  2578. #define fec_sw_rst_lsb 0
  2579. #define xd_r_fec_vtb_pm_crc 0xA394
  2580. #define fec_vtb_pm_crc_pos 0
  2581. #define fec_vtb_pm_crc_len 8
  2582. #define fec_vtb_pm_crc_lsb 0
  2583. #define xd_r_fec_vtb_tb_7_crc 0xA395
  2584. #define fec_vtb_tb_7_crc_pos 0
  2585. #define fec_vtb_tb_7_crc_len 8
  2586. #define fec_vtb_tb_7_crc_lsb 0
  2587. #define xd_r_fec_vtb_tb_6_crc 0xA396
  2588. #define fec_vtb_tb_6_crc_pos 0
  2589. #define fec_vtb_tb_6_crc_len 8
  2590. #define fec_vtb_tb_6_crc_lsb 0
  2591. #define xd_r_fec_vtb_tb_5_crc 0xA397
  2592. #define fec_vtb_tb_5_crc_pos 0
  2593. #define fec_vtb_tb_5_crc_len 8
  2594. #define fec_vtb_tb_5_crc_lsb 0
  2595. #define xd_r_fec_vtb_tb_4_crc 0xA398
  2596. #define fec_vtb_tb_4_crc_pos 0
  2597. #define fec_vtb_tb_4_crc_len 8
  2598. #define fec_vtb_tb_4_crc_lsb 0
  2599. #define xd_r_fec_vtb_tb_3_crc 0xA399
  2600. #define fec_vtb_tb_3_crc_pos 0
  2601. #define fec_vtb_tb_3_crc_len 8
  2602. #define fec_vtb_tb_3_crc_lsb 0
  2603. #define xd_r_fec_vtb_tb_2_crc 0xA39A
  2604. #define fec_vtb_tb_2_crc_pos 0
  2605. #define fec_vtb_tb_2_crc_len 8
  2606. #define fec_vtb_tb_2_crc_lsb 0
  2607. #define xd_r_fec_vtb_tb_1_crc 0xA39B
  2608. #define fec_vtb_tb_1_crc_pos 0
  2609. #define fec_vtb_tb_1_crc_len 8
  2610. #define fec_vtb_tb_1_crc_lsb 0
  2611. #define xd_r_fec_vtb_tb_0_crc 0xA39C
  2612. #define fec_vtb_tb_0_crc_pos 0
  2613. #define fec_vtb_tb_0_crc_len 8
  2614. #define fec_vtb_tb_0_crc_lsb 0
  2615. #define xd_r_fec_rsd_bank0_crc 0xA39D
  2616. #define fec_rsd_bank0_crc_pos 0
  2617. #define fec_rsd_bank0_crc_len 8
  2618. #define fec_rsd_bank0_crc_lsb 0
  2619. #define xd_r_fec_rsd_bank1_crc 0xA39E
  2620. #define fec_rsd_bank1_crc_pos 0
  2621. #define fec_rsd_bank1_crc_len 8
  2622. #define fec_rsd_bank1_crc_lsb 0
  2623. #define xd_r_fec_idi_vtb_crc 0xA39F
  2624. #define fec_idi_vtb_crc_pos 0
  2625. #define fec_idi_vtb_crc_len 8
  2626. #define fec_idi_vtb_crc_lsb 0
  2627. #define xd_g_reg_tpsd_txmod 0xA3C0
  2628. #define reg_tpsd_txmod_pos 0
  2629. #define reg_tpsd_txmod_len 2
  2630. #define reg_tpsd_txmod_lsb 0
  2631. #define xd_g_reg_tpsd_gi 0xA3C0
  2632. #define reg_tpsd_gi_pos 2
  2633. #define reg_tpsd_gi_len 2
  2634. #define reg_tpsd_gi_lsb 0
  2635. #define xd_g_reg_tpsd_hier 0xA3C0
  2636. #define reg_tpsd_hier_pos 4
  2637. #define reg_tpsd_hier_len 3
  2638. #define reg_tpsd_hier_lsb 0
  2639. #define xd_g_reg_bw 0xA3C1
  2640. #define reg_bw_pos 2
  2641. #define reg_bw_len 2
  2642. #define reg_bw_lsb 0
  2643. #define xd_g_reg_dec_pri 0xA3C1
  2644. #define reg_dec_pri_pos 4
  2645. #define reg_dec_pri_len 1
  2646. #define reg_dec_pri_lsb 0
  2647. #define xd_g_reg_tpsd_const 0xA3C1
  2648. #define reg_tpsd_const_pos 6
  2649. #define reg_tpsd_const_len 2
  2650. #define reg_tpsd_const_lsb 0
  2651. #define xd_g_reg_tpsd_hpcr 0xA3C2
  2652. #define reg_tpsd_hpcr_pos 0
  2653. #define reg_tpsd_hpcr_len 3
  2654. #define reg_tpsd_hpcr_lsb 0
  2655. #define xd_g_reg_tpsd_lpcr 0xA3C2
  2656. #define reg_tpsd_lpcr_pos 3
  2657. #define reg_tpsd_lpcr_len 3
  2658. #define reg_tpsd_lpcr_lsb 0
  2659. #define xd_g_reg_ofsm_clk 0xA3D0
  2660. #define reg_ofsm_clk_pos 0
  2661. #define reg_ofsm_clk_len 3
  2662. #define reg_ofsm_clk_lsb 0
  2663. #define xd_g_reg_fclk_cfg 0xA3D1
  2664. #define reg_fclk_cfg_pos 0
  2665. #define reg_fclk_cfg_len 1
  2666. #define reg_fclk_cfg_lsb 0
  2667. #define xd_g_reg_fclk_idi 0xA3D1
  2668. #define reg_fclk_idi_pos 1
  2669. #define reg_fclk_idi_len 1
  2670. #define reg_fclk_idi_lsb 0
  2671. #define xd_g_reg_fclk_odi 0xA3D1
  2672. #define reg_fclk_odi_pos 2
  2673. #define reg_fclk_odi_len 1
  2674. #define reg_fclk_odi_lsb 0
  2675. #define xd_g_reg_fclk_rsd 0xA3D1
  2676. #define reg_fclk_rsd_pos 3
  2677. #define reg_fclk_rsd_len 1
  2678. #define reg_fclk_rsd_lsb 0
  2679. #define xd_g_reg_fclk_vtb 0xA3D1
  2680. #define reg_fclk_vtb_pos 4
  2681. #define reg_fclk_vtb_len 1
  2682. #define reg_fclk_vtb_lsb 0
  2683. #define xd_g_reg_fclk_cste 0xA3D1
  2684. #define reg_fclk_cste_pos 5
  2685. #define reg_fclk_cste_len 1
  2686. #define reg_fclk_cste_lsb 0
  2687. #define xd_g_reg_fclk_mp2if 0xA3D1
  2688. #define reg_fclk_mp2if_pos 6
  2689. #define reg_fclk_mp2if_len 1
  2690. #define reg_fclk_mp2if_lsb 0
  2691. #define xd_I2C_i2c_m_slave_addr 0xA400
  2692. #define i2c_m_slave_addr_pos 0
  2693. #define i2c_m_slave_addr_len 8
  2694. #define i2c_m_slave_addr_lsb 0
  2695. #define xd_I2C_i2c_m_data1 0xA401
  2696. #define i2c_m_data1_pos 0
  2697. #define i2c_m_data1_len 8
  2698. #define i2c_m_data1_lsb 0
  2699. #define xd_I2C_i2c_m_data2 0xA402
  2700. #define i2c_m_data2_pos 0
  2701. #define i2c_m_data2_len 8
  2702. #define i2c_m_data2_lsb 0
  2703. #define xd_I2C_i2c_m_data3 0xA403
  2704. #define i2c_m_data3_pos 0
  2705. #define i2c_m_data3_len 8
  2706. #define i2c_m_data3_lsb 0
  2707. #define xd_I2C_i2c_m_data4 0xA404
  2708. #define i2c_m_data4_pos 0
  2709. #define i2c_m_data4_len 8
  2710. #define i2c_m_data4_lsb 0
  2711. #define xd_I2C_i2c_m_data5 0xA405
  2712. #define i2c_m_data5_pos 0
  2713. #define i2c_m_data5_len 8
  2714. #define i2c_m_data5_lsb 0
  2715. #define xd_I2C_i2c_m_data6 0xA406
  2716. #define i2c_m_data6_pos 0
  2717. #define i2c_m_data6_len 8
  2718. #define i2c_m_data6_lsb 0
  2719. #define xd_I2C_i2c_m_data7 0xA407
  2720. #define i2c_m_data7_pos 0
  2721. #define i2c_m_data7_len 8
  2722. #define i2c_m_data7_lsb 0
  2723. #define xd_I2C_i2c_m_data8 0xA408
  2724. #define i2c_m_data8_pos 0
  2725. #define i2c_m_data8_len 8
  2726. #define i2c_m_data8_lsb 0
  2727. #define xd_I2C_i2c_m_data9 0xA409
  2728. #define i2c_m_data9_pos 0
  2729. #define i2c_m_data9_len 8
  2730. #define i2c_m_data9_lsb 0
  2731. #define xd_I2C_i2c_m_data10 0xA40A
  2732. #define i2c_m_data10_pos 0
  2733. #define i2c_m_data10_len 8
  2734. #define i2c_m_data10_lsb 0
  2735. #define xd_I2C_i2c_m_data11 0xA40B
  2736. #define i2c_m_data11_pos 0
  2737. #define i2c_m_data11_len 8
  2738. #define i2c_m_data11_lsb 0
  2739. #define xd_I2C_i2c_m_cmd_rw 0xA40C
  2740. #define i2c_m_cmd_rw_pos 0
  2741. #define i2c_m_cmd_rw_len 1
  2742. #define i2c_m_cmd_rw_lsb 0
  2743. #define xd_I2C_i2c_m_cmd_rwlen 0xA40C
  2744. #define i2c_m_cmd_rwlen_pos 3
  2745. #define i2c_m_cmd_rwlen_len 4
  2746. #define i2c_m_cmd_rwlen_lsb 0
  2747. #define xd_I2C_i2c_m_status_cmd_exe 0xA40D
  2748. #define i2c_m_status_cmd_exe_pos 0
  2749. #define i2c_m_status_cmd_exe_len 1
  2750. #define i2c_m_status_cmd_exe_lsb 0
  2751. #define xd_I2C_i2c_m_status_wdat_done 0xA40D
  2752. #define i2c_m_status_wdat_done_pos 1
  2753. #define i2c_m_status_wdat_done_len 1
  2754. #define i2c_m_status_wdat_done_lsb 0
  2755. #define xd_I2C_i2c_m_status_wdat_fail 0xA40D
  2756. #define i2c_m_status_wdat_fail_pos 2
  2757. #define i2c_m_status_wdat_fail_len 1
  2758. #define i2c_m_status_wdat_fail_lsb 0
  2759. #define xd_I2C_i2c_m_period 0xA40E
  2760. #define i2c_m_period_pos 0
  2761. #define i2c_m_period_len 8
  2762. #define i2c_m_period_lsb 0
  2763. #define xd_I2C_i2c_m_reg_msb_lsb 0xA40F
  2764. #define i2c_m_reg_msb_lsb_pos 0
  2765. #define i2c_m_reg_msb_lsb_len 1
  2766. #define i2c_m_reg_msb_lsb_lsb 0
  2767. #define xd_I2C_reg_ofdm_rst 0xA40F
  2768. #define reg_ofdm_rst_pos 1
  2769. #define reg_ofdm_rst_len 1
  2770. #define reg_ofdm_rst_lsb 0
  2771. #define xd_I2C_reg_sample_period_on_tuner 0xA40F
  2772. #define reg_sample_period_on_tuner_pos 2
  2773. #define reg_sample_period_on_tuner_len 1
  2774. #define reg_sample_period_on_tuner_lsb 0
  2775. #define xd_I2C_reg_rst_i2c 0xA40F
  2776. #define reg_rst_i2c_pos 3
  2777. #define reg_rst_i2c_len 1
  2778. #define reg_rst_i2c_lsb 0
  2779. #define xd_I2C_reg_ofdm_rst_en 0xA40F
  2780. #define reg_ofdm_rst_en_pos 4
  2781. #define reg_ofdm_rst_en_len 1
  2782. #define reg_ofdm_rst_en_lsb 0
  2783. #define xd_I2C_reg_tuner_sda_sync_on 0xA40F
  2784. #define reg_tuner_sda_sync_on_pos 5
  2785. #define reg_tuner_sda_sync_on_len 1
  2786. #define reg_tuner_sda_sync_on_lsb 0
  2787. #define xd_p_mp2if_data_access_disable_ofsm 0xA500
  2788. #define mp2if_data_access_disable_ofsm_pos 0
  2789. #define mp2if_data_access_disable_ofsm_len 1
  2790. #define mp2if_data_access_disable_ofsm_lsb 0
  2791. #define xd_p_reg_mp2_sw_rst_ofsm 0xA500
  2792. #define reg_mp2_sw_rst_ofsm_pos 1
  2793. #define reg_mp2_sw_rst_ofsm_len 1
  2794. #define reg_mp2_sw_rst_ofsm_lsb 0
  2795. #define xd_p_reg_mp2if_clk_en_ofsm 0xA500
  2796. #define reg_mp2if_clk_en_ofsm_pos 2
  2797. #define reg_mp2if_clk_en_ofsm_len 1
  2798. #define reg_mp2if_clk_en_ofsm_lsb 0
  2799. #define xd_r_mp2if_sync_byte_locked 0xA500
  2800. #define mp2if_sync_byte_locked_pos 3
  2801. #define mp2if_sync_byte_locked_len 1
  2802. #define mp2if_sync_byte_locked_lsb 0
  2803. #define xd_r_mp2if_ts_not_188 0xA500
  2804. #define mp2if_ts_not_188_pos 4
  2805. #define mp2if_ts_not_188_len 1
  2806. #define mp2if_ts_not_188_lsb 0
  2807. #define xd_r_mp2if_psb_empty 0xA500
  2808. #define mp2if_psb_empty_pos 5
  2809. #define mp2if_psb_empty_len 1
  2810. #define mp2if_psb_empty_lsb 0
  2811. #define xd_r_mp2if_psb_overflow 0xA500
  2812. #define mp2if_psb_overflow_pos 6
  2813. #define mp2if_psb_overflow_len 1
  2814. #define mp2if_psb_overflow_lsb 0
  2815. #define xd_p_mp2if_keep_sf_sync_byte_ofsm 0xA500
  2816. #define mp2if_keep_sf_sync_byte_ofsm_pos 7
  2817. #define mp2if_keep_sf_sync_byte_ofsm_len 1
  2818. #define mp2if_keep_sf_sync_byte_ofsm_lsb 0
  2819. #define xd_r_mp2if_psb_mp2if_num_pkt 0xA501
  2820. #define mp2if_psb_mp2if_num_pkt_pos 0
  2821. #define mp2if_psb_mp2if_num_pkt_len 6
  2822. #define mp2if_psb_mp2if_num_pkt_lsb 0
  2823. #define xd_p_reg_mpeg_full_speed_ofsm 0xA501
  2824. #define reg_mpeg_full_speed_ofsm_pos 6
  2825. #define reg_mpeg_full_speed_ofsm_len 1
  2826. #define reg_mpeg_full_speed_ofsm_lsb 0
  2827. #define xd_p_mp2if_mpeg_ser_mode_ofsm 0xA501
  2828. #define mp2if_mpeg_ser_mode_ofsm_pos 7
  2829. #define mp2if_mpeg_ser_mode_ofsm_len 1
  2830. #define mp2if_mpeg_ser_mode_ofsm_lsb 0
  2831. #define xd_p_reg_sw_mon51 0xA600
  2832. #define reg_sw_mon51_pos 0
  2833. #define reg_sw_mon51_len 8
  2834. #define reg_sw_mon51_lsb 0
  2835. #define xd_p_reg_top_pcsel 0xA601
  2836. #define reg_top_pcsel_pos 0
  2837. #define reg_top_pcsel_len 1
  2838. #define reg_top_pcsel_lsb 0
  2839. #define xd_p_reg_top_rs232 0xA601
  2840. #define reg_top_rs232_pos 1
  2841. #define reg_top_rs232_len 1
  2842. #define reg_top_rs232_lsb 0
  2843. #define xd_p_reg_top_pcout 0xA601
  2844. #define reg_top_pcout_pos 2
  2845. #define reg_top_pcout_len 1
  2846. #define reg_top_pcout_lsb 0
  2847. #define xd_p_reg_top_debug 0xA601
  2848. #define reg_top_debug_pos 3
  2849. #define reg_top_debug_len 1
  2850. #define reg_top_debug_lsb 0
  2851. #define xd_p_reg_top_adcdly 0xA601
  2852. #define reg_top_adcdly_pos 4
  2853. #define reg_top_adcdly_len 2
  2854. #define reg_top_adcdly_lsb 0
  2855. #define xd_p_reg_top_pwrdw 0xA601
  2856. #define reg_top_pwrdw_pos 6
  2857. #define reg_top_pwrdw_len 1
  2858. #define reg_top_pwrdw_lsb 0
  2859. #define xd_p_reg_top_pwrdw_inv 0xA601
  2860. #define reg_top_pwrdw_inv_pos 7
  2861. #define reg_top_pwrdw_inv_len 1
  2862. #define reg_top_pwrdw_inv_lsb 0
  2863. #define xd_p_reg_top_int_inv 0xA602
  2864. #define reg_top_int_inv_pos 0
  2865. #define reg_top_int_inv_len 1
  2866. #define reg_top_int_inv_lsb 0
  2867. #define xd_p_reg_top_dio_sel 0xA602
  2868. #define reg_top_dio_sel_pos 1
  2869. #define reg_top_dio_sel_len 1
  2870. #define reg_top_dio_sel_lsb 0
  2871. #define xd_p_reg_top_gpioon0 0xA603
  2872. #define reg_top_gpioon0_pos 0
  2873. #define reg_top_gpioon0_len 1
  2874. #define reg_top_gpioon0_lsb 0
  2875. #define xd_p_reg_top_gpioon1 0xA603
  2876. #define reg_top_gpioon1_pos 1
  2877. #define reg_top_gpioon1_len 1
  2878. #define reg_top_gpioon1_lsb 0
  2879. #define xd_p_reg_top_gpioon2 0xA603
  2880. #define reg_top_gpioon2_pos 2
  2881. #define reg_top_gpioon2_len 1
  2882. #define reg_top_gpioon2_lsb 0
  2883. #define xd_p_reg_top_gpioon3 0xA603
  2884. #define reg_top_gpioon3_pos 3
  2885. #define reg_top_gpioon3_len 1
  2886. #define reg_top_gpioon3_lsb 0
  2887. #define xd_p_reg_top_lockon1 0xA603
  2888. #define reg_top_lockon1_pos 4
  2889. #define reg_top_lockon1_len 1
  2890. #define reg_top_lockon1_lsb 0
  2891. #define xd_p_reg_top_lockon2 0xA603
  2892. #define reg_top_lockon2_pos 5
  2893. #define reg_top_lockon2_len 1
  2894. #define reg_top_lockon2_lsb 0
  2895. #define xd_p_reg_top_gpioo0 0xA604
  2896. #define reg_top_gpioo0_pos 0
  2897. #define reg_top_gpioo0_len 1
  2898. #define reg_top_gpioo0_lsb 0
  2899. #define xd_p_reg_top_gpioo1 0xA604
  2900. #define reg_top_gpioo1_pos 1
  2901. #define reg_top_gpioo1_len 1
  2902. #define reg_top_gpioo1_lsb 0
  2903. #define xd_p_reg_top_gpioo2 0xA604
  2904. #define reg_top_gpioo2_pos 2
  2905. #define reg_top_gpioo2_len 1
  2906. #define reg_top_gpioo2_lsb 0
  2907. #define xd_p_reg_top_gpioo3 0xA604
  2908. #define reg_top_gpioo3_pos 3
  2909. #define reg_top_gpioo3_len 1
  2910. #define reg_top_gpioo3_lsb 0
  2911. #define xd_p_reg_top_lock1 0xA604
  2912. #define reg_top_lock1_pos 4
  2913. #define reg_top_lock1_len 1
  2914. #define reg_top_lock1_lsb 0
  2915. #define xd_p_reg_top_lock2 0xA604
  2916. #define reg_top_lock2_pos 5
  2917. #define reg_top_lock2_len 1
  2918. #define reg_top_lock2_lsb 0
  2919. #define xd_p_reg_top_gpioen0 0xA605
  2920. #define reg_top_gpioen0_pos 0
  2921. #define reg_top_gpioen0_len 1
  2922. #define reg_top_gpioen0_lsb 0
  2923. #define xd_p_reg_top_gpioen1 0xA605
  2924. #define reg_top_gpioen1_pos 1
  2925. #define reg_top_gpioen1_len 1
  2926. #define reg_top_gpioen1_lsb 0
  2927. #define xd_p_reg_top_gpioen2 0xA605
  2928. #define reg_top_gpioen2_pos 2
  2929. #define reg_top_gpioen2_len 1
  2930. #define reg_top_gpioen2_lsb 0
  2931. #define xd_p_reg_top_gpioen3 0xA605
  2932. #define reg_top_gpioen3_pos 3
  2933. #define reg_top_gpioen3_len 1
  2934. #define reg_top_gpioen3_lsb 0
  2935. #define xd_p_reg_top_locken1 0xA605
  2936. #define reg_top_locken1_pos 4
  2937. #define reg_top_locken1_len 1
  2938. #define reg_top_locken1_lsb 0
  2939. #define xd_p_reg_top_locken2 0xA605
  2940. #define reg_top_locken2_pos 5
  2941. #define reg_top_locken2_len 1
  2942. #define reg_top_locken2_lsb 0
  2943. #define xd_r_reg_top_gpioi0 0xA606
  2944. #define reg_top_gpioi0_pos 0
  2945. #define reg_top_gpioi0_len 1
  2946. #define reg_top_gpioi0_lsb 0
  2947. #define xd_r_reg_top_gpioi1 0xA606
  2948. #define reg_top_gpioi1_pos 1
  2949. #define reg_top_gpioi1_len 1
  2950. #define reg_top_gpioi1_lsb 0
  2951. #define xd_r_reg_top_gpioi2 0xA606
  2952. #define reg_top_gpioi2_pos 2
  2953. #define reg_top_gpioi2_len 1
  2954. #define reg_top_gpioi2_lsb 0
  2955. #define xd_r_reg_top_gpioi3 0xA606
  2956. #define reg_top_gpioi3_pos 3
  2957. #define reg_top_gpioi3_len 1
  2958. #define reg_top_gpioi3_lsb 0
  2959. #define xd_r_reg_top_locki1 0xA606
  2960. #define reg_top_locki1_pos 4
  2961. #define reg_top_locki1_len 1
  2962. #define reg_top_locki1_lsb 0
  2963. #define xd_r_reg_top_locki2 0xA606
  2964. #define reg_top_locki2_pos 5
  2965. #define reg_top_locki2_len 1
  2966. #define reg_top_locki2_lsb 0
  2967. #define xd_p_reg_dummy_7_0 0xA608
  2968. #define reg_dummy_7_0_pos 0
  2969. #define reg_dummy_7_0_len 8
  2970. #define reg_dummy_7_0_lsb 0
  2971. #define xd_p_reg_dummy_15_8 0xA609
  2972. #define reg_dummy_15_8_pos 0
  2973. #define reg_dummy_15_8_len 8
  2974. #define reg_dummy_15_8_lsb 8
  2975. #define xd_p_reg_dummy_23_16 0xA60A
  2976. #define reg_dummy_23_16_pos 0
  2977. #define reg_dummy_23_16_len 8
  2978. #define reg_dummy_23_16_lsb 16
  2979. #define xd_p_reg_dummy_31_24 0xA60B
  2980. #define reg_dummy_31_24_pos 0
  2981. #define reg_dummy_31_24_len 8
  2982. #define reg_dummy_31_24_lsb 24
  2983. #define xd_p_reg_dummy_39_32 0xA60C
  2984. #define reg_dummy_39_32_pos 0
  2985. #define reg_dummy_39_32_len 8
  2986. #define reg_dummy_39_32_lsb 32
  2987. #define xd_p_reg_dummy_47_40 0xA60D
  2988. #define reg_dummy_47_40_pos 0
  2989. #define reg_dummy_47_40_len 8
  2990. #define reg_dummy_47_40_lsb 40
  2991. #define xd_p_reg_dummy_55_48 0xA60E
  2992. #define reg_dummy_55_48_pos 0
  2993. #define reg_dummy_55_48_len 8
  2994. #define reg_dummy_55_48_lsb 48
  2995. #define xd_p_reg_dummy_63_56 0xA60F
  2996. #define reg_dummy_63_56_pos 0
  2997. #define reg_dummy_63_56_len 8
  2998. #define reg_dummy_63_56_lsb 56
  2999. #define xd_p_reg_dummy_71_64 0xA610
  3000. #define reg_dummy_71_64_pos 0
  3001. #define reg_dummy_71_64_len 8
  3002. #define reg_dummy_71_64_lsb 64
  3003. #define xd_p_reg_dummy_79_72 0xA611
  3004. #define reg_dummy_79_72_pos 0
  3005. #define reg_dummy_79_72_len 8
  3006. #define reg_dummy_79_72_lsb 72
  3007. #define xd_p_reg_dummy_87_80 0xA612
  3008. #define reg_dummy_87_80_pos 0
  3009. #define reg_dummy_87_80_len 8
  3010. #define reg_dummy_87_80_lsb 80
  3011. #define xd_p_reg_dummy_95_88 0xA613
  3012. #define reg_dummy_95_88_pos 0
  3013. #define reg_dummy_95_88_len 8
  3014. #define reg_dummy_95_88_lsb 88
  3015. #define xd_p_reg_dummy_103_96 0xA614
  3016. #define reg_dummy_103_96_pos 0
  3017. #define reg_dummy_103_96_len 8
  3018. #define reg_dummy_103_96_lsb 96
  3019. #define xd_p_reg_unplug_flag 0xA615
  3020. #define reg_unplug_flag_pos 0
  3021. #define reg_unplug_flag_len 1
  3022. #define reg_unplug_flag_lsb 104
  3023. #define xd_p_reg_api_dca_stes_request 0xA615
  3024. #define reg_api_dca_stes_request_pos 1
  3025. #define reg_api_dca_stes_request_len 1
  3026. #define reg_api_dca_stes_request_lsb 0
  3027. #define xd_p_reg_back_to_dca_flag 0xA615
  3028. #define reg_back_to_dca_flag_pos 2
  3029. #define reg_back_to_dca_flag_len 1
  3030. #define reg_back_to_dca_flag_lsb 106
  3031. #define xd_p_reg_api_retrain_request 0xA615
  3032. #define reg_api_retrain_request_pos 3
  3033. #define reg_api_retrain_request_len 1
  3034. #define reg_api_retrain_request_lsb 0
  3035. #define xd_p_reg_Dyn_Top_Try_flag 0xA615
  3036. #define reg_Dyn_Top_Try_flag_pos 3
  3037. #define reg_Dyn_Top_Try_flag_len 1
  3038. #define reg_Dyn_Top_Try_flag_lsb 107
  3039. #define xd_p_reg_API_retrain_freeze_flag 0xA615
  3040. #define reg_API_retrain_freeze_flag_pos 4
  3041. #define reg_API_retrain_freeze_flag_len 1
  3042. #define reg_API_retrain_freeze_flag_lsb 108
  3043. #define xd_p_reg_dummy_111_104 0xA615
  3044. #define reg_dummy_111_104_pos 0
  3045. #define reg_dummy_111_104_len 8
  3046. #define reg_dummy_111_104_lsb 104
  3047. #define xd_p_reg_dummy_119_112 0xA616
  3048. #define reg_dummy_119_112_pos 0
  3049. #define reg_dummy_119_112_len 8
  3050. #define reg_dummy_119_112_lsb 112
  3051. #define xd_p_reg_dummy_127_120 0xA617
  3052. #define reg_dummy_127_120_pos 0
  3053. #define reg_dummy_127_120_len 8
  3054. #define reg_dummy_127_120_lsb 120
  3055. #define xd_p_reg_dummy_135_128 0xA618
  3056. #define reg_dummy_135_128_pos 0
  3057. #define reg_dummy_135_128_len 8
  3058. #define reg_dummy_135_128_lsb 128
  3059. #define xd_p_reg_dummy_143_136 0xA619
  3060. #define reg_dummy_143_136_pos 0
  3061. #define reg_dummy_143_136_len 8
  3062. #define reg_dummy_143_136_lsb 136
  3063. #define xd_p_reg_CCIR_dis 0xA619
  3064. #define reg_CCIR_dis_pos 0
  3065. #define reg_CCIR_dis_len 1
  3066. #define reg_CCIR_dis_lsb 0
  3067. #define xd_p_reg_dummy_151_144 0xA61A
  3068. #define reg_dummy_151_144_pos 0
  3069. #define reg_dummy_151_144_len 8
  3070. #define reg_dummy_151_144_lsb 144
  3071. #define xd_p_reg_dummy_159_152 0xA61B
  3072. #define reg_dummy_159_152_pos 0
  3073. #define reg_dummy_159_152_len 8
  3074. #define reg_dummy_159_152_lsb 152
  3075. #define xd_p_reg_dummy_167_160 0xA61C
  3076. #define reg_dummy_167_160_pos 0
  3077. #define reg_dummy_167_160_len 8
  3078. #define reg_dummy_167_160_lsb 160
  3079. #define xd_p_reg_dummy_175_168 0xA61D
  3080. #define reg_dummy_175_168_pos 0
  3081. #define reg_dummy_175_168_len 8
  3082. #define reg_dummy_175_168_lsb 168
  3083. #define xd_p_reg_dummy_183_176 0xA61E
  3084. #define reg_dummy_183_176_pos 0
  3085. #define reg_dummy_183_176_len 8
  3086. #define reg_dummy_183_176_lsb 176
  3087. #define xd_p_reg_ofsm_read_rbc_en 0xA61E
  3088. #define reg_ofsm_read_rbc_en_pos 2
  3089. #define reg_ofsm_read_rbc_en_len 1
  3090. #define reg_ofsm_read_rbc_en_lsb 0
  3091. #define xd_p_reg_ce_filter_selection_dis 0xA61E
  3092. #define reg_ce_filter_selection_dis_pos 1
  3093. #define reg_ce_filter_selection_dis_len 1
  3094. #define reg_ce_filter_selection_dis_lsb 0
  3095. #define xd_p_reg_OFSM_version_control_7_0 0xA611
  3096. #define reg_OFSM_version_control_7_0_pos 0
  3097. #define reg_OFSM_version_control_7_0_len 8
  3098. #define reg_OFSM_version_control_7_0_lsb 0
  3099. #define xd_p_reg_OFSM_version_control_15_8 0xA61F
  3100. #define reg_OFSM_version_control_15_8_pos 0
  3101. #define reg_OFSM_version_control_15_8_len 8
  3102. #define reg_OFSM_version_control_15_8_lsb 0
  3103. #define xd_p_reg_OFSM_version_control_23_16 0xA620
  3104. #define reg_OFSM_version_control_23_16_pos 0
  3105. #define reg_OFSM_version_control_23_16_len 8
  3106. #define reg_OFSM_version_control_23_16_lsb 0
  3107. #define xd_p_reg_dummy_191_184 0xA61F
  3108. #define reg_dummy_191_184_pos 0
  3109. #define reg_dummy_191_184_len 8
  3110. #define reg_dummy_191_184_lsb 184
  3111. #define xd_p_reg_dummy_199_192 0xA620
  3112. #define reg_dummy_199_192_pos 0
  3113. #define reg_dummy_199_192_len 8
  3114. #define reg_dummy_199_192_lsb 192
  3115. #define xd_p_reg_ce_en 0xABC0
  3116. #define reg_ce_en_pos 0
  3117. #define reg_ce_en_len 1
  3118. #define reg_ce_en_lsb 0
  3119. #define xd_p_reg_ce_fctrl_en 0xABC0
  3120. #define reg_ce_fctrl_en_pos 1
  3121. #define reg_ce_fctrl_en_len 1
  3122. #define reg_ce_fctrl_en_lsb 0
  3123. #define xd_p_reg_ce_fste_tdi 0xABC0
  3124. #define reg_ce_fste_tdi_pos 2
  3125. #define reg_ce_fste_tdi_len 1
  3126. #define reg_ce_fste_tdi_lsb 0
  3127. #define xd_p_reg_ce_dynamic 0xABC0
  3128. #define reg_ce_dynamic_pos 3
  3129. #define reg_ce_dynamic_len 1
  3130. #define reg_ce_dynamic_lsb 0
  3131. #define xd_p_reg_ce_conf 0xABC0
  3132. #define reg_ce_conf_pos 4
  3133. #define reg_ce_conf_len 2
  3134. #define reg_ce_conf_lsb 0
  3135. #define xd_p_reg_ce_dyn12 0xABC0
  3136. #define reg_ce_dyn12_pos 6
  3137. #define reg_ce_dyn12_len 1
  3138. #define reg_ce_dyn12_lsb 0
  3139. #define xd_p_reg_ce_derot_en 0xABC0
  3140. #define reg_ce_derot_en_pos 7
  3141. #define reg_ce_derot_en_len 1
  3142. #define reg_ce_derot_en_lsb 0
  3143. #define xd_p_reg_ce_dynamic_th_7_0 0xABC1
  3144. #define reg_ce_dynamic_th_7_0_pos 0
  3145. #define reg_ce_dynamic_th_7_0_len 8
  3146. #define reg_ce_dynamic_th_7_0_lsb 0
  3147. #define xd_p_reg_ce_dynamic_th_15_8 0xABC2
  3148. #define reg_ce_dynamic_th_15_8_pos 0
  3149. #define reg_ce_dynamic_th_15_8_len 8
  3150. #define reg_ce_dynamic_th_15_8_lsb 8
  3151. #define xd_p_reg_ce_s1 0xABC3
  3152. #define reg_ce_s1_pos 0
  3153. #define reg_ce_s1_len 5
  3154. #define reg_ce_s1_lsb 0
  3155. #define xd_p_reg_ce_var_forced_value 0xABC3
  3156. #define reg_ce_var_forced_value_pos 5
  3157. #define reg_ce_var_forced_value_len 3
  3158. #define reg_ce_var_forced_value_lsb 0
  3159. #define xd_p_reg_ce_data_im_7_0 0xABC4
  3160. #define reg_ce_data_im_7_0_pos 0
  3161. #define reg_ce_data_im_7_0_len 8
  3162. #define reg_ce_data_im_7_0_lsb 0
  3163. #define xd_p_reg_ce_data_im_8 0xABC5
  3164. #define reg_ce_data_im_8_pos 0
  3165. #define reg_ce_data_im_8_len 1
  3166. #define reg_ce_data_im_8_lsb 0
  3167. #define xd_p_reg_ce_data_re_6_0 0xABC5
  3168. #define reg_ce_data_re_6_0_pos 1
  3169. #define reg_ce_data_re_6_0_len 7
  3170. #define reg_ce_data_re_6_0_lsb 0
  3171. #define xd_p_reg_ce_data_re_8_7 0xABC6
  3172. #define reg_ce_data_re_8_7_pos 0
  3173. #define reg_ce_data_re_8_7_len 2
  3174. #define reg_ce_data_re_8_7_lsb 7
  3175. #define xd_p_reg_ce_tone_5_0 0xABC6
  3176. #define reg_ce_tone_5_0_pos 2
  3177. #define reg_ce_tone_5_0_len 6
  3178. #define reg_ce_tone_5_0_lsb 0
  3179. #define xd_p_reg_ce_tone_12_6 0xABC7
  3180. #define reg_ce_tone_12_6_pos 0
  3181. #define reg_ce_tone_12_6_len 7
  3182. #define reg_ce_tone_12_6_lsb 6
  3183. #define xd_p_reg_ce_centroid_drift_th 0xABC8
  3184. #define reg_ce_centroid_drift_th_pos 0
  3185. #define reg_ce_centroid_drift_th_len 8
  3186. #define reg_ce_centroid_drift_th_lsb 0
  3187. #define xd_p_reg_ce_centroid_count_max 0xABC9
  3188. #define reg_ce_centroid_count_max_pos 0
  3189. #define reg_ce_centroid_count_max_len 4
  3190. #define reg_ce_centroid_count_max_lsb 0
  3191. #define xd_p_reg_ce_centroid_bias_inc_7_0 0xABCA
  3192. #define reg_ce_centroid_bias_inc_7_0_pos 0
  3193. #define reg_ce_centroid_bias_inc_7_0_len 8
  3194. #define reg_ce_centroid_bias_inc_7_0_lsb 0
  3195. #define xd_p_reg_ce_centroid_bias_inc_8 0xABCB
  3196. #define reg_ce_centroid_bias_inc_8_pos 0
  3197. #define reg_ce_centroid_bias_inc_8_len 1
  3198. #define reg_ce_centroid_bias_inc_8_lsb 0
  3199. #define xd_p_reg_ce_var_th0_7_0 0xABCC
  3200. #define reg_ce_var_th0_7_0_pos 0
  3201. #define reg_ce_var_th0_7_0_len 8
  3202. #define reg_ce_var_th0_7_0_lsb 0
  3203. #define xd_p_reg_ce_var_th0_15_8 0xABCD
  3204. #define reg_ce_var_th0_15_8_pos 0
  3205. #define reg_ce_var_th0_15_8_len 8
  3206. #define reg_ce_var_th0_15_8_lsb 8
  3207. #define xd_p_reg_ce_var_th1_7_0 0xABCE
  3208. #define reg_ce_var_th1_7_0_pos 0
  3209. #define reg_ce_var_th1_7_0_len 8
  3210. #define reg_ce_var_th1_7_0_lsb 0
  3211. #define xd_p_reg_ce_var_th1_15_8 0xABCF
  3212. #define reg_ce_var_th1_15_8_pos 0
  3213. #define reg_ce_var_th1_15_8_len 8
  3214. #define reg_ce_var_th1_15_8_lsb 8
  3215. #define xd_p_reg_ce_var_th2_7_0 0xABD0
  3216. #define reg_ce_var_th2_7_0_pos 0
  3217. #define reg_ce_var_th2_7_0_len 8
  3218. #define reg_ce_var_th2_7_0_lsb 0
  3219. #define xd_p_reg_ce_var_th2_15_8 0xABD1
  3220. #define reg_ce_var_th2_15_8_pos 0
  3221. #define reg_ce_var_th2_15_8_len 8
  3222. #define reg_ce_var_th2_15_8_lsb 8
  3223. #define xd_p_reg_ce_var_th3_7_0 0xABD2
  3224. #define reg_ce_var_th3_7_0_pos 0
  3225. #define reg_ce_var_th3_7_0_len 8
  3226. #define reg_ce_var_th3_7_0_lsb 0
  3227. #define xd_p_reg_ce_var_th3_15_8 0xABD3
  3228. #define reg_ce_var_th3_15_8_pos 0
  3229. #define reg_ce_var_th3_15_8_len 8
  3230. #define reg_ce_var_th3_15_8_lsb 8
  3231. #define xd_p_reg_ce_var_th4_7_0 0xABD4
  3232. #define reg_ce_var_th4_7_0_pos 0
  3233. #define reg_ce_var_th4_7_0_len 8
  3234. #define reg_ce_var_th4_7_0_lsb 0
  3235. #define xd_p_reg_ce_var_th4_15_8 0xABD5
  3236. #define reg_ce_var_th4_15_8_pos 0
  3237. #define reg_ce_var_th4_15_8_len 8
  3238. #define reg_ce_var_th4_15_8_lsb 8
  3239. #define xd_p_reg_ce_var_th5_7_0 0xABD6
  3240. #define reg_ce_var_th5_7_0_pos 0
  3241. #define reg_ce_var_th5_7_0_len 8
  3242. #define reg_ce_var_th5_7_0_lsb 0
  3243. #define xd_p_reg_ce_var_th5_15_8 0xABD7
  3244. #define reg_ce_var_th5_15_8_pos 0
  3245. #define reg_ce_var_th5_15_8_len 8
  3246. #define reg_ce_var_th5_15_8_lsb 8
  3247. #define xd_p_reg_ce_var_th6_7_0 0xABD8
  3248. #define reg_ce_var_th6_7_0_pos 0
  3249. #define reg_ce_var_th6_7_0_len 8
  3250. #define reg_ce_var_th6_7_0_lsb 0
  3251. #define xd_p_reg_ce_var_th6_15_8 0xABD9
  3252. #define reg_ce_var_th6_15_8_pos 0
  3253. #define reg_ce_var_th6_15_8_len 8
  3254. #define reg_ce_var_th6_15_8_lsb 8
  3255. #define xd_p_reg_ce_fctrl_reset 0xABDA
  3256. #define reg_ce_fctrl_reset_pos 0
  3257. #define reg_ce_fctrl_reset_len 1
  3258. #define reg_ce_fctrl_reset_lsb 0
  3259. #define xd_p_reg_ce_cent_auto_clr_en 0xABDA
  3260. #define reg_ce_cent_auto_clr_en_pos 1
  3261. #define reg_ce_cent_auto_clr_en_len 1
  3262. #define reg_ce_cent_auto_clr_en_lsb 0
  3263. #define xd_p_reg_ce_fctrl_auto_reset_en 0xABDA
  3264. #define reg_ce_fctrl_auto_reset_en_pos 2
  3265. #define reg_ce_fctrl_auto_reset_en_len 1
  3266. #define reg_ce_fctrl_auto_reset_en_lsb 0
  3267. #define xd_p_reg_ce_var_forced_en 0xABDA
  3268. #define reg_ce_var_forced_en_pos 3
  3269. #define reg_ce_var_forced_en_len 1
  3270. #define reg_ce_var_forced_en_lsb 0
  3271. #define xd_p_reg_ce_cent_forced_en 0xABDA
  3272. #define reg_ce_cent_forced_en_pos 4
  3273. #define reg_ce_cent_forced_en_len 1
  3274. #define reg_ce_cent_forced_en_lsb 0
  3275. #define xd_p_reg_ce_var_max 0xABDA
  3276. #define reg_ce_var_max_pos 5
  3277. #define reg_ce_var_max_len 3
  3278. #define reg_ce_var_max_lsb 0
  3279. #define xd_p_reg_ce_cent_forced_value_7_0 0xABDB
  3280. #define reg_ce_cent_forced_value_7_0_pos 0
  3281. #define reg_ce_cent_forced_value_7_0_len 8
  3282. #define reg_ce_cent_forced_value_7_0_lsb 0
  3283. #define xd_p_reg_ce_cent_forced_value_11_8 0xABDC
  3284. #define reg_ce_cent_forced_value_11_8_pos 0
  3285. #define reg_ce_cent_forced_value_11_8_len 4
  3286. #define reg_ce_cent_forced_value_11_8_lsb 8
  3287. #define xd_p_reg_ce_fctrl_rd 0xABDD
  3288. #define reg_ce_fctrl_rd_pos 0
  3289. #define reg_ce_fctrl_rd_len 1
  3290. #define reg_ce_fctrl_rd_lsb 0
  3291. #define xd_p_reg_ce_centroid_max_6_0 0xABDD
  3292. #define reg_ce_centroid_max_6_0_pos 1
  3293. #define reg_ce_centroid_max_6_0_len 7
  3294. #define reg_ce_centroid_max_6_0_lsb 0
  3295. #define xd_p_reg_ce_centroid_max_11_7 0xABDE
  3296. #define reg_ce_centroid_max_11_7_pos 0
  3297. #define reg_ce_centroid_max_11_7_len 5
  3298. #define reg_ce_centroid_max_11_7_lsb 7
  3299. #define xd_p_reg_ce_var 0xABDF
  3300. #define reg_ce_var_pos 0
  3301. #define reg_ce_var_len 3
  3302. #define reg_ce_var_lsb 0
  3303. #define xd_p_reg_ce_fctrl_rdy 0xABDF
  3304. #define reg_ce_fctrl_rdy_pos 3
  3305. #define reg_ce_fctrl_rdy_len 1
  3306. #define reg_ce_fctrl_rdy_lsb 0
  3307. #define xd_p_reg_ce_centroid_out_3_0 0xABDF
  3308. #define reg_ce_centroid_out_3_0_pos 4
  3309. #define reg_ce_centroid_out_3_0_len 4
  3310. #define reg_ce_centroid_out_3_0_lsb 0
  3311. #define xd_p_reg_ce_centroid_out_11_4 0xABE0
  3312. #define reg_ce_centroid_out_11_4_pos 0
  3313. #define reg_ce_centroid_out_11_4_len 8
  3314. #define reg_ce_centroid_out_11_4_lsb 4
  3315. #define xd_p_reg_ce_bias_7_0 0xABE1
  3316. #define reg_ce_bias_7_0_pos 0
  3317. #define reg_ce_bias_7_0_len 8
  3318. #define reg_ce_bias_7_0_lsb 0
  3319. #define xd_p_reg_ce_bias_11_8 0xABE2
  3320. #define reg_ce_bias_11_8_pos 0
  3321. #define reg_ce_bias_11_8_len 4
  3322. #define reg_ce_bias_11_8_lsb 8
  3323. #define xd_p_reg_ce_m1_3_0 0xABE2
  3324. #define reg_ce_m1_3_0_pos 4
  3325. #define reg_ce_m1_3_0_len 4
  3326. #define reg_ce_m1_3_0_lsb 0
  3327. #define xd_p_reg_ce_m1_11_4 0xABE3
  3328. #define reg_ce_m1_11_4_pos 0
  3329. #define reg_ce_m1_11_4_len 8
  3330. #define reg_ce_m1_11_4_lsb 4
  3331. #define xd_p_reg_ce_rh0_7_0 0xABE4
  3332. #define reg_ce_rh0_7_0_pos 0
  3333. #define reg_ce_rh0_7_0_len 8
  3334. #define reg_ce_rh0_7_0_lsb 0
  3335. #define xd_p_reg_ce_rh0_15_8 0xABE5
  3336. #define reg_ce_rh0_15_8_pos 0
  3337. #define reg_ce_rh0_15_8_len 8
  3338. #define reg_ce_rh0_15_8_lsb 8
  3339. #define xd_p_reg_ce_rh0_23_16 0xABE6
  3340. #define reg_ce_rh0_23_16_pos 0
  3341. #define reg_ce_rh0_23_16_len 8
  3342. #define reg_ce_rh0_23_16_lsb 16
  3343. #define xd_p_reg_ce_rh0_31_24 0xABE7
  3344. #define reg_ce_rh0_31_24_pos 0
  3345. #define reg_ce_rh0_31_24_len 8
  3346. #define reg_ce_rh0_31_24_lsb 24
  3347. #define xd_p_reg_ce_rh3_real_7_0 0xABE8
  3348. #define reg_ce_rh3_real_7_0_pos 0
  3349. #define reg_ce_rh3_real_7_0_len 8
  3350. #define reg_ce_rh3_real_7_0_lsb 0
  3351. #define xd_p_reg_ce_rh3_real_15_8 0xABE9
  3352. #define reg_ce_rh3_real_15_8_pos 0
  3353. #define reg_ce_rh3_real_15_8_len 8
  3354. #define reg_ce_rh3_real_15_8_lsb 8
  3355. #define xd_p_reg_ce_rh3_real_23_16 0xABEA
  3356. #define reg_ce_rh3_real_23_16_pos 0
  3357. #define reg_ce_rh3_real_23_16_len 8
  3358. #define reg_ce_rh3_real_23_16_lsb 16
  3359. #define xd_p_reg_ce_rh3_real_31_24 0xABEB
  3360. #define reg_ce_rh3_real_31_24_pos 0
  3361. #define reg_ce_rh3_real_31_24_len 8
  3362. #define reg_ce_rh3_real_31_24_lsb 24
  3363. #define xd_p_reg_ce_rh3_imag_7_0 0xABEC
  3364. #define reg_ce_rh3_imag_7_0_pos 0
  3365. #define reg_ce_rh3_imag_7_0_len 8
  3366. #define reg_ce_rh3_imag_7_0_lsb 0
  3367. #define xd_p_reg_ce_rh3_imag_15_8 0xABED
  3368. #define reg_ce_rh3_imag_15_8_pos 0
  3369. #define reg_ce_rh3_imag_15_8_len 8
  3370. #define reg_ce_rh3_imag_15_8_lsb 8
  3371. #define xd_p_reg_ce_rh3_imag_23_16 0xABEE
  3372. #define reg_ce_rh3_imag_23_16_pos 0
  3373. #define reg_ce_rh3_imag_23_16_len 8
  3374. #define reg_ce_rh3_imag_23_16_lsb 16
  3375. #define xd_p_reg_ce_rh3_imag_31_24 0xABEF
  3376. #define reg_ce_rh3_imag_31_24_pos 0
  3377. #define reg_ce_rh3_imag_31_24_len 8
  3378. #define reg_ce_rh3_imag_31_24_lsb 24
  3379. #define xd_p_reg_feq_fix_eh2_7_0 0xABF0
  3380. #define reg_feq_fix_eh2_7_0_pos 0
  3381. #define reg_feq_fix_eh2_7_0_len 8
  3382. #define reg_feq_fix_eh2_7_0_lsb 0
  3383. #define xd_p_reg_feq_fix_eh2_15_8 0xABF1
  3384. #define reg_feq_fix_eh2_15_8_pos 0
  3385. #define reg_feq_fix_eh2_15_8_len 8
  3386. #define reg_feq_fix_eh2_15_8_lsb 8
  3387. #define xd_p_reg_feq_fix_eh2_23_16 0xABF2
  3388. #define reg_feq_fix_eh2_23_16_pos 0
  3389. #define reg_feq_fix_eh2_23_16_len 8
  3390. #define reg_feq_fix_eh2_23_16_lsb 16
  3391. #define xd_p_reg_feq_fix_eh2_31_24 0xABF3
  3392. #define reg_feq_fix_eh2_31_24_pos 0
  3393. #define reg_feq_fix_eh2_31_24_len 8
  3394. #define reg_feq_fix_eh2_31_24_lsb 24
  3395. #define xd_p_reg_ce_m2_central_7_0 0xABF4
  3396. #define reg_ce_m2_central_7_0_pos 0
  3397. #define reg_ce_m2_central_7_0_len 8
  3398. #define reg_ce_m2_central_7_0_lsb 0
  3399. #define xd_p_reg_ce_m2_central_15_8 0xABF5
  3400. #define reg_ce_m2_central_15_8_pos 0
  3401. #define reg_ce_m2_central_15_8_len 8
  3402. #define reg_ce_m2_central_15_8_lsb 8
  3403. #define xd_p_reg_ce_fftshift 0xABF6
  3404. #define reg_ce_fftshift_pos 0
  3405. #define reg_ce_fftshift_len 4
  3406. #define reg_ce_fftshift_lsb 0
  3407. #define xd_p_reg_ce_fftshift1 0xABF6
  3408. #define reg_ce_fftshift1_pos 4
  3409. #define reg_ce_fftshift1_len 4
  3410. #define reg_ce_fftshift1_lsb 0
  3411. #define xd_p_reg_ce_fftshift2 0xABF7
  3412. #define reg_ce_fftshift2_pos 0
  3413. #define reg_ce_fftshift2_len 4
  3414. #define reg_ce_fftshift2_lsb 0
  3415. #define xd_p_reg_ce_top_mobile 0xABF7
  3416. #define reg_ce_top_mobile_pos 4
  3417. #define reg_ce_top_mobile_len 1
  3418. #define reg_ce_top_mobile_lsb 0
  3419. #define xd_p_reg_strong_sginal_detected 0xA2BC
  3420. #define reg_strong_sginal_detected_pos 2
  3421. #define reg_strong_sginal_detected_len 1
  3422. #define reg_strong_sginal_detected_lsb 0
  3423. #define XD_MP2IF_BASE 0xB000
  3424. #define XD_MP2IF_CSR (0x00 + XD_MP2IF_BASE)
  3425. #define XD_MP2IF_DMX_CTRL (0x03 + XD_MP2IF_BASE)
  3426. #define XD_MP2IF_PID_IDX (0x04 + XD_MP2IF_BASE)
  3427. #define XD_MP2IF_PID_DATA_L (0x05 + XD_MP2IF_BASE)
  3428. #define XD_MP2IF_PID_DATA_H (0x06 + XD_MP2IF_BASE)
  3429. #define XD_MP2IF_MISC (0x07 + XD_MP2IF_BASE)
  3430. extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d);
  3431. extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg,
  3432. u8 * value);
  3433. extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  3434. u8 * values, int len);
  3435. extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg,
  3436. u8 value);
  3437. extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  3438. u8 * values, int len);
  3439. extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg,
  3440. u8 addr, u8 * values, int len);
  3441. extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
  3442. u8 * values, int len);
  3443. extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg,
  3444. u8 pos, u8 len, u8 * value);
  3445. extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg,
  3446. u8 pos, u8 len, u8 value);
  3447. extern int af9005_send_command(struct dvb_usb_device *d, u8 command,
  3448. u8 * wbuf, int wlen, u8 * rbuf, int rlen);
  3449. extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address,
  3450. u8 * values, int len);
  3451. extern int af9005_tuner_attach(struct dvb_usb_adapter *adap);
  3452. extern int af9005_led_control(struct dvb_usb_device *d, int onoff);
  3453. extern u8 regmask[8];
  3454. /* remote control decoder */
  3455. extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len,
  3456. u32 * event, int *state);
  3457. extern struct dvb_usb_rc_key af9005_rc_keys[];
  3458. extern int af9005_rc_keys_size;
  3459. #endif