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/drivers/media/video/pvrusb2/pvrusb2-hdw.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 5322 lines | 4253 code | 603 blank | 466 comment | 711 complexity | 7c94954335ac73ba1975e7d8876f4c34 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. *
  3. *
  4. * Copyright (C) 2005 Mike Isely <isely@pobox.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/errno.h>
  21. #include <linux/string.h>
  22. #include <linux/slab.h>
  23. #include <linux/firmware.h>
  24. #include <linux/videodev2.h>
  25. #include <media/v4l2-common.h>
  26. #include <media/tuner.h>
  27. #include "pvrusb2.h"
  28. #include "pvrusb2-std.h"
  29. #include "pvrusb2-util.h"
  30. #include "pvrusb2-hdw.h"
  31. #include "pvrusb2-i2c-core.h"
  32. #include "pvrusb2-eeprom.h"
  33. #include "pvrusb2-hdw-internal.h"
  34. #include "pvrusb2-encoder.h"
  35. #include "pvrusb2-debug.h"
  36. #include "pvrusb2-fx2-cmd.h"
  37. #include "pvrusb2-wm8775.h"
  38. #include "pvrusb2-video-v4l.h"
  39. #include "pvrusb2-cx2584x-v4l.h"
  40. #include "pvrusb2-cs53l32a.h"
  41. #include "pvrusb2-audio.h"
  42. #define TV_MIN_FREQ 55250000L
  43. #define TV_MAX_FREQ 850000000L
  44. /* This defines a minimum interval that the decoder must remain quiet
  45. before we are allowed to start it running. */
  46. #define TIME_MSEC_DECODER_WAIT 50
  47. /* This defines a minimum interval that the decoder must be allowed to run
  48. before we can safely begin using its streaming output. */
  49. #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  50. /* This defines a minimum interval that the encoder must remain quiet
  51. before we are allowed to configure it. */
  52. #define TIME_MSEC_ENCODER_WAIT 50
  53. /* This defines the minimum interval that the encoder must successfully run
  54. before we consider that the encoder has run at least once since its
  55. firmware has been loaded. This measurement is in important for cases
  56. where we can't do something until we know that the encoder has been run
  57. at least once. */
  58. #define TIME_MSEC_ENCODER_OK 250
  59. static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  60. static DEFINE_MUTEX(pvr2_unit_mtx);
  61. static int ctlchg;
  62. static int procreload;
  63. static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  64. static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  65. static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  66. static int init_pause_msec;
  67. module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  68. MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  69. module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  70. MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  71. module_param(procreload, int, S_IRUGO|S_IWUSR);
  72. MODULE_PARM_DESC(procreload,
  73. "Attempt init failure recovery with firmware reload");
  74. module_param_array(tuner, int, NULL, 0444);
  75. MODULE_PARM_DESC(tuner,"specify installed tuner type");
  76. module_param_array(video_std, int, NULL, 0444);
  77. MODULE_PARM_DESC(video_std,"specify initial video standard");
  78. module_param_array(tolerance, int, NULL, 0444);
  79. MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  80. /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  81. static int default_tv_freq = 61250000L;
  82. /* 104.3 MHz, a usable FM station for my area */
  83. static int default_radio_freq = 104300000L;
  84. module_param_named(tv_freq, default_tv_freq, int, 0444);
  85. MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  86. module_param_named(radio_freq, default_radio_freq, int, 0444);
  87. MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  88. #define PVR2_CTL_WRITE_ENDPOINT 0x01
  89. #define PVR2_CTL_READ_ENDPOINT 0x81
  90. #define PVR2_GPIO_IN 0x9008
  91. #define PVR2_GPIO_OUT 0x900c
  92. #define PVR2_GPIO_DIR 0x9020
  93. #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  94. #define PVR2_FIRMWARE_ENDPOINT 0x02
  95. /* size of a firmware chunk */
  96. #define FIRMWARE_CHUNK_SIZE 0x2000
  97. typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
  98. struct v4l2_subdev *);
  99. static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
  100. [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
  101. [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
  102. [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
  103. [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
  104. [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
  105. };
  106. static const char *module_names[] = {
  107. [PVR2_CLIENT_ID_MSP3400] = "msp3400",
  108. [PVR2_CLIENT_ID_CX25840] = "cx25840",
  109. [PVR2_CLIENT_ID_SAA7115] = "saa7115",
  110. [PVR2_CLIENT_ID_TUNER] = "tuner",
  111. [PVR2_CLIENT_ID_DEMOD] = "tuner",
  112. [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
  113. [PVR2_CLIENT_ID_WM8775] = "wm8775",
  114. };
  115. static const unsigned char *module_i2c_addresses[] = {
  116. [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
  117. [PVR2_CLIENT_ID_DEMOD] = "\x43",
  118. [PVR2_CLIENT_ID_MSP3400] = "\x40",
  119. [PVR2_CLIENT_ID_SAA7115] = "\x21",
  120. [PVR2_CLIENT_ID_WM8775] = "\x1b",
  121. [PVR2_CLIENT_ID_CX25840] = "\x44",
  122. [PVR2_CLIENT_ID_CS53L32A] = "\x11",
  123. };
  124. static const char *ir_scheme_names[] = {
  125. [PVR2_IR_SCHEME_NONE] = "none",
  126. [PVR2_IR_SCHEME_29XXX] = "29xxx",
  127. [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
  128. [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
  129. [PVR2_IR_SCHEME_ZILOG] = "Zilog",
  130. };
  131. /* Define the list of additional controls we'll dynamically construct based
  132. on query of the cx2341x module. */
  133. struct pvr2_mpeg_ids {
  134. const char *strid;
  135. int id;
  136. };
  137. static const struct pvr2_mpeg_ids mpeg_ids[] = {
  138. {
  139. .strid = "audio_layer",
  140. .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  141. },{
  142. .strid = "audio_bitrate",
  143. .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  144. },{
  145. /* Already using audio_mode elsewhere :-( */
  146. .strid = "mpeg_audio_mode",
  147. .id = V4L2_CID_MPEG_AUDIO_MODE,
  148. },{
  149. .strid = "mpeg_audio_mode_extension",
  150. .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
  151. },{
  152. .strid = "audio_emphasis",
  153. .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
  154. },{
  155. .strid = "audio_crc",
  156. .id = V4L2_CID_MPEG_AUDIO_CRC,
  157. },{
  158. .strid = "video_aspect",
  159. .id = V4L2_CID_MPEG_VIDEO_ASPECT,
  160. },{
  161. .strid = "video_b_frames",
  162. .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
  163. },{
  164. .strid = "video_gop_size",
  165. .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
  166. },{
  167. .strid = "video_gop_closure",
  168. .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
  169. },{
  170. .strid = "video_bitrate_mode",
  171. .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
  172. },{
  173. .strid = "video_bitrate",
  174. .id = V4L2_CID_MPEG_VIDEO_BITRATE,
  175. },{
  176. .strid = "video_bitrate_peak",
  177. .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
  178. },{
  179. .strid = "video_temporal_decimation",
  180. .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
  181. },{
  182. .strid = "stream_type",
  183. .id = V4L2_CID_MPEG_STREAM_TYPE,
  184. },{
  185. .strid = "video_spatial_filter_mode",
  186. .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
  187. },{
  188. .strid = "video_spatial_filter",
  189. .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
  190. },{
  191. .strid = "video_luma_spatial_filter_type",
  192. .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
  193. },{
  194. .strid = "video_chroma_spatial_filter_type",
  195. .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
  196. },{
  197. .strid = "video_temporal_filter_mode",
  198. .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
  199. },{
  200. .strid = "video_temporal_filter",
  201. .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
  202. },{
  203. .strid = "video_median_filter_type",
  204. .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
  205. },{
  206. .strid = "video_luma_median_filter_top",
  207. .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
  208. },{
  209. .strid = "video_luma_median_filter_bottom",
  210. .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
  211. },{
  212. .strid = "video_chroma_median_filter_top",
  213. .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
  214. },{
  215. .strid = "video_chroma_median_filter_bottom",
  216. .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
  217. }
  218. };
  219. #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
  220. static const char *control_values_srate[] = {
  221. [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
  222. [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
  223. [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
  224. };
  225. static const char *control_values_input[] = {
  226. [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
  227. [PVR2_CVAL_INPUT_DTV] = "dtv",
  228. [PVR2_CVAL_INPUT_RADIO] = "radio",
  229. [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
  230. [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
  231. };
  232. static const char *control_values_audiomode[] = {
  233. [V4L2_TUNER_MODE_MONO] = "Mono",
  234. [V4L2_TUNER_MODE_STEREO] = "Stereo",
  235. [V4L2_TUNER_MODE_LANG1] = "Lang1",
  236. [V4L2_TUNER_MODE_LANG2] = "Lang2",
  237. [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
  238. };
  239. static const char *control_values_hsm[] = {
  240. [PVR2_CVAL_HSM_FAIL] = "Fail",
  241. [PVR2_CVAL_HSM_HIGH] = "High",
  242. [PVR2_CVAL_HSM_FULL] = "Full",
  243. };
  244. static const char *pvr2_state_names[] = {
  245. [PVR2_STATE_NONE] = "none",
  246. [PVR2_STATE_DEAD] = "dead",
  247. [PVR2_STATE_COLD] = "cold",
  248. [PVR2_STATE_WARM] = "warm",
  249. [PVR2_STATE_ERROR] = "error",
  250. [PVR2_STATE_READY] = "ready",
  251. [PVR2_STATE_RUN] = "run",
  252. };
  253. struct pvr2_fx2cmd_descdef {
  254. unsigned char id;
  255. unsigned char *desc;
  256. };
  257. static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
  258. {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
  259. {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
  260. {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
  261. {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
  262. {FX2CMD_REG_WRITE, "write encoder register"},
  263. {FX2CMD_REG_READ, "read encoder register"},
  264. {FX2CMD_MEMSEL, "encoder memsel"},
  265. {FX2CMD_I2C_WRITE, "i2c write"},
  266. {FX2CMD_I2C_READ, "i2c read"},
  267. {FX2CMD_GET_USB_SPEED, "get USB speed"},
  268. {FX2CMD_STREAMING_ON, "stream on"},
  269. {FX2CMD_STREAMING_OFF, "stream off"},
  270. {FX2CMD_FWPOST1, "fwpost1"},
  271. {FX2CMD_POWER_OFF, "power off"},
  272. {FX2CMD_POWER_ON, "power on"},
  273. {FX2CMD_DEEP_RESET, "deep reset"},
  274. {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
  275. {FX2CMD_GET_IR_CODE, "get IR code"},
  276. {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
  277. {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
  278. {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
  279. {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
  280. {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
  281. {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
  282. {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
  283. };
  284. static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
  285. static void pvr2_hdw_state_sched(struct pvr2_hdw *);
  286. static int pvr2_hdw_state_eval(struct pvr2_hdw *);
  287. static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
  288. static void pvr2_hdw_worker_poll(struct work_struct *work);
  289. static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
  290. static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
  291. static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
  292. static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
  293. static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
  294. static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
  295. static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
  296. static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
  297. static void pvr2_hdw_quiescent_timeout(unsigned long);
  298. static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
  299. static void pvr2_hdw_encoder_wait_timeout(unsigned long);
  300. static void pvr2_hdw_encoder_run_timeout(unsigned long);
  301. static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
  302. static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
  303. unsigned int timeout,int probe_fl,
  304. void *write_data,unsigned int write_len,
  305. void *read_data,unsigned int read_len);
  306. static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
  307. static void trace_stbit(const char *name,int val)
  308. {
  309. pvr2_trace(PVR2_TRACE_STBITS,
  310. "State bit %s <-- %s",
  311. name,(val ? "true" : "false"));
  312. }
  313. static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
  314. {
  315. struct pvr2_hdw *hdw = cptr->hdw;
  316. if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
  317. *vp = hdw->freqTable[hdw->freqProgSlot-1];
  318. } else {
  319. *vp = 0;
  320. }
  321. return 0;
  322. }
  323. static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
  324. {
  325. struct pvr2_hdw *hdw = cptr->hdw;
  326. unsigned int slotId = hdw->freqProgSlot;
  327. if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
  328. hdw->freqTable[slotId-1] = v;
  329. /* Handle side effects correctly - if we're tuned to this
  330. slot, then forgot the slot id relation since the stored
  331. frequency has been changed. */
  332. if (hdw->freqSelector) {
  333. if (hdw->freqSlotRadio == slotId) {
  334. hdw->freqSlotRadio = 0;
  335. }
  336. } else {
  337. if (hdw->freqSlotTelevision == slotId) {
  338. hdw->freqSlotTelevision = 0;
  339. }
  340. }
  341. }
  342. return 0;
  343. }
  344. static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
  345. {
  346. *vp = cptr->hdw->freqProgSlot;
  347. return 0;
  348. }
  349. static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
  350. {
  351. struct pvr2_hdw *hdw = cptr->hdw;
  352. if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
  353. hdw->freqProgSlot = v;
  354. }
  355. return 0;
  356. }
  357. static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
  358. {
  359. struct pvr2_hdw *hdw = cptr->hdw;
  360. *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
  361. return 0;
  362. }
  363. static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
  364. {
  365. unsigned freq = 0;
  366. struct pvr2_hdw *hdw = cptr->hdw;
  367. if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
  368. if (slotId > 0) {
  369. freq = hdw->freqTable[slotId-1];
  370. if (!freq) return 0;
  371. pvr2_hdw_set_cur_freq(hdw,freq);
  372. }
  373. if (hdw->freqSelector) {
  374. hdw->freqSlotRadio = slotId;
  375. } else {
  376. hdw->freqSlotTelevision = slotId;
  377. }
  378. return 0;
  379. }
  380. static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
  381. {
  382. *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
  383. return 0;
  384. }
  385. static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
  386. {
  387. return cptr->hdw->freqDirty != 0;
  388. }
  389. static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
  390. {
  391. cptr->hdw->freqDirty = 0;
  392. }
  393. static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
  394. {
  395. pvr2_hdw_set_cur_freq(cptr->hdw,v);
  396. return 0;
  397. }
  398. static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
  399. {
  400. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  401. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  402. if (stat != 0) {
  403. return stat;
  404. }
  405. *left = cap->bounds.left;
  406. return 0;
  407. }
  408. static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
  409. {
  410. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  411. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  412. if (stat != 0) {
  413. return stat;
  414. }
  415. *left = cap->bounds.left;
  416. if (cap->bounds.width > cptr->hdw->cropw_val) {
  417. *left += cap->bounds.width - cptr->hdw->cropw_val;
  418. }
  419. return 0;
  420. }
  421. static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
  422. {
  423. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  424. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  425. if (stat != 0) {
  426. return stat;
  427. }
  428. *top = cap->bounds.top;
  429. return 0;
  430. }
  431. static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
  432. {
  433. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  434. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  435. if (stat != 0) {
  436. return stat;
  437. }
  438. *top = cap->bounds.top;
  439. if (cap->bounds.height > cptr->hdw->croph_val) {
  440. *top += cap->bounds.height - cptr->hdw->croph_val;
  441. }
  442. return 0;
  443. }
  444. static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
  445. {
  446. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  447. int stat, bleftend, cleft;
  448. stat = pvr2_hdw_check_cropcap(cptr->hdw);
  449. if (stat != 0) {
  450. return stat;
  451. }
  452. bleftend = cap->bounds.left+cap->bounds.width;
  453. cleft = cptr->hdw->cropl_val;
  454. *width = cleft < bleftend ? bleftend-cleft : 0;
  455. return 0;
  456. }
  457. static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
  458. {
  459. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  460. int stat, btopend, ctop;
  461. stat = pvr2_hdw_check_cropcap(cptr->hdw);
  462. if (stat != 0) {
  463. return stat;
  464. }
  465. btopend = cap->bounds.top+cap->bounds.height;
  466. ctop = cptr->hdw->cropt_val;
  467. *height = ctop < btopend ? btopend-ctop : 0;
  468. return 0;
  469. }
  470. static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
  471. {
  472. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  473. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  474. if (stat != 0) {
  475. return stat;
  476. }
  477. *val = cap->bounds.left;
  478. return 0;
  479. }
  480. static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
  481. {
  482. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  483. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  484. if (stat != 0) {
  485. return stat;
  486. }
  487. *val = cap->bounds.top;
  488. return 0;
  489. }
  490. static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
  491. {
  492. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  493. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  494. if (stat != 0) {
  495. return stat;
  496. }
  497. *val = cap->bounds.width;
  498. return 0;
  499. }
  500. static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
  501. {
  502. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  503. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  504. if (stat != 0) {
  505. return stat;
  506. }
  507. *val = cap->bounds.height;
  508. return 0;
  509. }
  510. static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
  511. {
  512. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  513. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  514. if (stat != 0) {
  515. return stat;
  516. }
  517. *val = cap->defrect.left;
  518. return 0;
  519. }
  520. static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
  521. {
  522. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  523. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  524. if (stat != 0) {
  525. return stat;
  526. }
  527. *val = cap->defrect.top;
  528. return 0;
  529. }
  530. static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
  531. {
  532. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  533. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  534. if (stat != 0) {
  535. return stat;
  536. }
  537. *val = cap->defrect.width;
  538. return 0;
  539. }
  540. static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
  541. {
  542. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  543. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  544. if (stat != 0) {
  545. return stat;
  546. }
  547. *val = cap->defrect.height;
  548. return 0;
  549. }
  550. static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
  551. {
  552. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  553. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  554. if (stat != 0) {
  555. return stat;
  556. }
  557. *val = cap->pixelaspect.numerator;
  558. return 0;
  559. }
  560. static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
  561. {
  562. struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
  563. int stat = pvr2_hdw_check_cropcap(cptr->hdw);
  564. if (stat != 0) {
  565. return stat;
  566. }
  567. *val = cap->pixelaspect.denominator;
  568. return 0;
  569. }
  570. static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
  571. {
  572. /* Actual maximum depends on the video standard in effect. */
  573. if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
  574. *vp = 480;
  575. } else {
  576. *vp = 576;
  577. }
  578. return 0;
  579. }
  580. static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
  581. {
  582. /* Actual minimum depends on device digitizer type. */
  583. if (cptr->hdw->hdw_desc->flag_has_cx25840) {
  584. *vp = 75;
  585. } else {
  586. *vp = 17;
  587. }
  588. return 0;
  589. }
  590. static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
  591. {
  592. *vp = cptr->hdw->input_val;
  593. return 0;
  594. }
  595. static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
  596. {
  597. return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
  598. }
  599. static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
  600. {
  601. return pvr2_hdw_set_input(cptr->hdw,v);
  602. }
  603. static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
  604. {
  605. return cptr->hdw->input_dirty != 0;
  606. }
  607. static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
  608. {
  609. cptr->hdw->input_dirty = 0;
  610. }
  611. static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
  612. {
  613. unsigned long fv;
  614. struct pvr2_hdw *hdw = cptr->hdw;
  615. if (hdw->tuner_signal_stale) {
  616. pvr2_hdw_status_poll(hdw);
  617. }
  618. fv = hdw->tuner_signal_info.rangehigh;
  619. if (!fv) {
  620. /* Safety fallback */
  621. *vp = TV_MAX_FREQ;
  622. return 0;
  623. }
  624. if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
  625. fv = (fv * 125) / 2;
  626. } else {
  627. fv = fv * 62500;
  628. }
  629. *vp = fv;
  630. return 0;
  631. }
  632. static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
  633. {
  634. unsigned long fv;
  635. struct pvr2_hdw *hdw = cptr->hdw;
  636. if (hdw->tuner_signal_stale) {
  637. pvr2_hdw_status_poll(hdw);
  638. }
  639. fv = hdw->tuner_signal_info.rangelow;
  640. if (!fv) {
  641. /* Safety fallback */
  642. *vp = TV_MIN_FREQ;
  643. return 0;
  644. }
  645. if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
  646. fv = (fv * 125) / 2;
  647. } else {
  648. fv = fv * 62500;
  649. }
  650. *vp = fv;
  651. return 0;
  652. }
  653. static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
  654. {
  655. return cptr->hdw->enc_stale != 0;
  656. }
  657. static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
  658. {
  659. cptr->hdw->enc_stale = 0;
  660. cptr->hdw->enc_unsafe_stale = 0;
  661. }
  662. static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
  663. {
  664. int ret;
  665. struct v4l2_ext_controls cs;
  666. struct v4l2_ext_control c1;
  667. memset(&cs,0,sizeof(cs));
  668. memset(&c1,0,sizeof(c1));
  669. cs.controls = &c1;
  670. cs.count = 1;
  671. c1.id = cptr->info->v4l_id;
  672. ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
  673. VIDIOC_G_EXT_CTRLS);
  674. if (ret) return ret;
  675. *vp = c1.value;
  676. return 0;
  677. }
  678. static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
  679. {
  680. int ret;
  681. struct pvr2_hdw *hdw = cptr->hdw;
  682. struct v4l2_ext_controls cs;
  683. struct v4l2_ext_control c1;
  684. memset(&cs,0,sizeof(cs));
  685. memset(&c1,0,sizeof(c1));
  686. cs.controls = &c1;
  687. cs.count = 1;
  688. c1.id = cptr->info->v4l_id;
  689. c1.value = v;
  690. ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
  691. hdw->state_encoder_run, &cs,
  692. VIDIOC_S_EXT_CTRLS);
  693. if (ret == -EBUSY) {
  694. /* Oops. cx2341x is telling us it's not safe to change
  695. this control while we're capturing. Make a note of this
  696. fact so that the pipeline will be stopped the next time
  697. controls are committed. Then go on ahead and store this
  698. change anyway. */
  699. ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
  700. 0, &cs,
  701. VIDIOC_S_EXT_CTRLS);
  702. if (!ret) hdw->enc_unsafe_stale = !0;
  703. }
  704. if (ret) return ret;
  705. hdw->enc_stale = !0;
  706. return 0;
  707. }
  708. static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
  709. {
  710. struct v4l2_queryctrl qctrl;
  711. struct pvr2_ctl_info *info;
  712. qctrl.id = cptr->info->v4l_id;
  713. cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
  714. /* Strip out the const so we can adjust a function pointer. It's
  715. OK to do this here because we know this is a dynamically created
  716. control, so the underlying storage for the info pointer is (a)
  717. private to us, and (b) not in read-only storage. Either we do
  718. this or we significantly complicate the underlying control
  719. implementation. */
  720. info = (struct pvr2_ctl_info *)(cptr->info);
  721. if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
  722. if (info->set_value) {
  723. info->set_value = NULL;
  724. }
  725. } else {
  726. if (!(info->set_value)) {
  727. info->set_value = ctrl_cx2341x_set;
  728. }
  729. }
  730. return qctrl.flags;
  731. }
  732. static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
  733. {
  734. *vp = cptr->hdw->state_pipeline_req;
  735. return 0;
  736. }
  737. static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
  738. {
  739. *vp = cptr->hdw->master_state;
  740. return 0;
  741. }
  742. static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
  743. {
  744. int result = pvr2_hdw_is_hsm(cptr->hdw);
  745. *vp = PVR2_CVAL_HSM_FULL;
  746. if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
  747. if (result) *vp = PVR2_CVAL_HSM_HIGH;
  748. return 0;
  749. }
  750. static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
  751. {
  752. *vp = cptr->hdw->std_mask_avail;
  753. return 0;
  754. }
  755. static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
  756. {
  757. struct pvr2_hdw *hdw = cptr->hdw;
  758. v4l2_std_id ns;
  759. ns = hdw->std_mask_avail;
  760. ns = (ns & ~m) | (v & m);
  761. if (ns == hdw->std_mask_avail) return 0;
  762. hdw->std_mask_avail = ns;
  763. pvr2_hdw_internal_set_std_avail(hdw);
  764. pvr2_hdw_internal_find_stdenum(hdw);
  765. return 0;
  766. }
  767. static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
  768. char *bufPtr,unsigned int bufSize,
  769. unsigned int *len)
  770. {
  771. *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
  772. return 0;
  773. }
  774. static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
  775. const char *bufPtr,unsigned int bufSize,
  776. int *mskp,int *valp)
  777. {
  778. int ret;
  779. v4l2_std_id id;
  780. ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
  781. if (ret < 0) return ret;
  782. if (mskp) *mskp = id;
  783. if (valp) *valp = id;
  784. return 0;
  785. }
  786. static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
  787. {
  788. *vp = cptr->hdw->std_mask_cur;
  789. return 0;
  790. }
  791. static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
  792. {
  793. struct pvr2_hdw *hdw = cptr->hdw;
  794. v4l2_std_id ns;
  795. ns = hdw->std_mask_cur;
  796. ns = (ns & ~m) | (v & m);
  797. if (ns == hdw->std_mask_cur) return 0;
  798. hdw->std_mask_cur = ns;
  799. hdw->std_dirty = !0;
  800. pvr2_hdw_internal_find_stdenum(hdw);
  801. return 0;
  802. }
  803. static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
  804. {
  805. return cptr->hdw->std_dirty != 0;
  806. }
  807. static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
  808. {
  809. cptr->hdw->std_dirty = 0;
  810. }
  811. static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
  812. {
  813. struct pvr2_hdw *hdw = cptr->hdw;
  814. pvr2_hdw_status_poll(hdw);
  815. *vp = hdw->tuner_signal_info.signal;
  816. return 0;
  817. }
  818. static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
  819. {
  820. int val = 0;
  821. unsigned int subchan;
  822. struct pvr2_hdw *hdw = cptr->hdw;
  823. pvr2_hdw_status_poll(hdw);
  824. subchan = hdw->tuner_signal_info.rxsubchans;
  825. if (subchan & V4L2_TUNER_SUB_MONO) {
  826. val |= (1 << V4L2_TUNER_MODE_MONO);
  827. }
  828. if (subchan & V4L2_TUNER_SUB_STEREO) {
  829. val |= (1 << V4L2_TUNER_MODE_STEREO);
  830. }
  831. if (subchan & V4L2_TUNER_SUB_LANG1) {
  832. val |= (1 << V4L2_TUNER_MODE_LANG1);
  833. }
  834. if (subchan & V4L2_TUNER_SUB_LANG2) {
  835. val |= (1 << V4L2_TUNER_MODE_LANG2);
  836. }
  837. *vp = val;
  838. return 0;
  839. }
  840. static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
  841. {
  842. struct pvr2_hdw *hdw = cptr->hdw;
  843. if (v < 0) return -EINVAL;
  844. if (v > hdw->std_enum_cnt) return -EINVAL;
  845. hdw->std_enum_cur = v;
  846. if (!v) return 0;
  847. v--;
  848. if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
  849. hdw->std_mask_cur = hdw->std_defs[v].id;
  850. hdw->std_dirty = !0;
  851. return 0;
  852. }
  853. static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
  854. {
  855. *vp = cptr->hdw->std_enum_cur;
  856. return 0;
  857. }
  858. static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
  859. {
  860. return cptr->hdw->std_dirty != 0;
  861. }
  862. static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
  863. {
  864. cptr->hdw->std_dirty = 0;
  865. }
  866. #define DEFINT(vmin,vmax) \
  867. .type = pvr2_ctl_int, \
  868. .def.type_int.min_value = vmin, \
  869. .def.type_int.max_value = vmax
  870. #define DEFENUM(tab) \
  871. .type = pvr2_ctl_enum, \
  872. .def.type_enum.count = ARRAY_SIZE(tab), \
  873. .def.type_enum.value_names = tab
  874. #define DEFBOOL \
  875. .type = pvr2_ctl_bool
  876. #define DEFMASK(msk,tab) \
  877. .type = pvr2_ctl_bitmask, \
  878. .def.type_bitmask.valid_bits = msk, \
  879. .def.type_bitmask.bit_names = tab
  880. #define DEFREF(vname) \
  881. .set_value = ctrl_set_##vname, \
  882. .get_value = ctrl_get_##vname, \
  883. .is_dirty = ctrl_isdirty_##vname, \
  884. .clear_dirty = ctrl_cleardirty_##vname
  885. #define VCREATE_FUNCS(vname) \
  886. static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
  887. {*vp = cptr->hdw->vname##_val; return 0;} \
  888. static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
  889. {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
  890. static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
  891. {return cptr->hdw->vname##_dirty != 0;} \
  892. static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
  893. {cptr->hdw->vname##_dirty = 0;}
  894. VCREATE_FUNCS(brightness)
  895. VCREATE_FUNCS(contrast)
  896. VCREATE_FUNCS(saturation)
  897. VCREATE_FUNCS(hue)
  898. VCREATE_FUNCS(volume)
  899. VCREATE_FUNCS(balance)
  900. VCREATE_FUNCS(bass)
  901. VCREATE_FUNCS(treble)
  902. VCREATE_FUNCS(mute)
  903. VCREATE_FUNCS(cropl)
  904. VCREATE_FUNCS(cropt)
  905. VCREATE_FUNCS(cropw)
  906. VCREATE_FUNCS(croph)
  907. VCREATE_FUNCS(audiomode)
  908. VCREATE_FUNCS(res_hor)
  909. VCREATE_FUNCS(res_ver)
  910. VCREATE_FUNCS(srate)
  911. /* Table definition of all controls which can be manipulated */
  912. static const struct pvr2_ctl_info control_defs[] = {
  913. {
  914. .v4l_id = V4L2_CID_BRIGHTNESS,
  915. .desc = "Brightness",
  916. .name = "brightness",
  917. .default_value = 128,
  918. DEFREF(brightness),
  919. DEFINT(0,255),
  920. },{
  921. .v4l_id = V4L2_CID_CONTRAST,
  922. .desc = "Contrast",
  923. .name = "contrast",
  924. .default_value = 68,
  925. DEFREF(contrast),
  926. DEFINT(0,127),
  927. },{
  928. .v4l_id = V4L2_CID_SATURATION,
  929. .desc = "Saturation",
  930. .name = "saturation",
  931. .default_value = 64,
  932. DEFREF(saturation),
  933. DEFINT(0,127),
  934. },{
  935. .v4l_id = V4L2_CID_HUE,
  936. .desc = "Hue",
  937. .name = "hue",
  938. .default_value = 0,
  939. DEFREF(hue),
  940. DEFINT(-128,127),
  941. },{
  942. .v4l_id = V4L2_CID_AUDIO_VOLUME,
  943. .desc = "Volume",
  944. .name = "volume",
  945. .default_value = 62000,
  946. DEFREF(volume),
  947. DEFINT(0,65535),
  948. },{
  949. .v4l_id = V4L2_CID_AUDIO_BALANCE,
  950. .desc = "Balance",
  951. .name = "balance",
  952. .default_value = 0,
  953. DEFREF(balance),
  954. DEFINT(-32768,32767),
  955. },{
  956. .v4l_id = V4L2_CID_AUDIO_BASS,
  957. .desc = "Bass",
  958. .name = "bass",
  959. .default_value = 0,
  960. DEFREF(bass),
  961. DEFINT(-32768,32767),
  962. },{
  963. .v4l_id = V4L2_CID_AUDIO_TREBLE,
  964. .desc = "Treble",
  965. .name = "treble",
  966. .default_value = 0,
  967. DEFREF(treble),
  968. DEFINT(-32768,32767),
  969. },{
  970. .v4l_id = V4L2_CID_AUDIO_MUTE,
  971. .desc = "Mute",
  972. .name = "mute",
  973. .default_value = 0,
  974. DEFREF(mute),
  975. DEFBOOL,
  976. }, {
  977. .desc = "Capture crop left margin",
  978. .name = "crop_left",
  979. .internal_id = PVR2_CID_CROPL,
  980. .default_value = 0,
  981. DEFREF(cropl),
  982. DEFINT(-129, 340),
  983. .get_min_value = ctrl_cropl_min_get,
  984. .get_max_value = ctrl_cropl_max_get,
  985. .get_def_value = ctrl_get_cropcapdl,
  986. }, {
  987. .desc = "Capture crop top margin",
  988. .name = "crop_top",
  989. .internal_id = PVR2_CID_CROPT,
  990. .default_value = 0,
  991. DEFREF(cropt),
  992. DEFINT(-35, 544),
  993. .get_min_value = ctrl_cropt_min_get,
  994. .get_max_value = ctrl_cropt_max_get,
  995. .get_def_value = ctrl_get_cropcapdt,
  996. }, {
  997. .desc = "Capture crop width",
  998. .name = "crop_width",
  999. .internal_id = PVR2_CID_CROPW,
  1000. .default_value = 720,
  1001. DEFREF(cropw),
  1002. DEFINT(0, 864),
  1003. .get_max_value = ctrl_cropw_max_get,
  1004. .get_def_value = ctrl_get_cropcapdw,
  1005. }, {
  1006. .desc = "Capture crop height",
  1007. .name = "crop_height",
  1008. .internal_id = PVR2_CID_CROPH,
  1009. .default_value = 480,
  1010. DEFREF(croph),
  1011. DEFINT(0, 576),
  1012. .get_max_value = ctrl_croph_max_get,
  1013. .get_def_value = ctrl_get_cropcapdh,
  1014. }, {
  1015. .desc = "Capture capability pixel aspect numerator",
  1016. .name = "cropcap_pixel_numerator",
  1017. .internal_id = PVR2_CID_CROPCAPPAN,
  1018. .get_value = ctrl_get_cropcappan,
  1019. }, {
  1020. .desc = "Capture capability pixel aspect denominator",
  1021. .name = "cropcap_pixel_denominator",
  1022. .internal_id = PVR2_CID_CROPCAPPAD,
  1023. .get_value = ctrl_get_cropcappad,
  1024. }, {
  1025. .desc = "Capture capability bounds top",
  1026. .name = "cropcap_bounds_top",
  1027. .internal_id = PVR2_CID_CROPCAPBT,
  1028. .get_value = ctrl_get_cropcapbt,
  1029. }, {
  1030. .desc = "Capture capability bounds left",
  1031. .name = "cropcap_bounds_left",
  1032. .internal_id = PVR2_CID_CROPCAPBL,
  1033. .get_value = ctrl_get_cropcapbl,
  1034. }, {
  1035. .desc = "Capture capability bounds width",
  1036. .name = "cropcap_bounds_width",
  1037. .internal_id = PVR2_CID_CROPCAPBW,
  1038. .get_value = ctrl_get_cropcapbw,
  1039. }, {
  1040. .desc = "Capture capability bounds height",
  1041. .name = "cropcap_bounds_height",
  1042. .internal_id = PVR2_CID_CROPCAPBH,
  1043. .get_value = ctrl_get_cropcapbh,
  1044. },{
  1045. .desc = "Video Source",
  1046. .name = "input",
  1047. .internal_id = PVR2_CID_INPUT,
  1048. .default_value = PVR2_CVAL_INPUT_TV,
  1049. .check_value = ctrl_check_input,
  1050. DEFREF(input),
  1051. DEFENUM(control_values_input),
  1052. },{
  1053. .desc = "Audio Mode",
  1054. .name = "audio_mode",
  1055. .internal_id = PVR2_CID_AUDIOMODE,
  1056. .default_value = V4L2_TUNER_MODE_STEREO,
  1057. DEFREF(audiomode),
  1058. DEFENUM(control_values_audiomode),
  1059. },{
  1060. .desc = "Horizontal capture resolution",
  1061. .name = "resolution_hor",
  1062. .internal_id = PVR2_CID_HRES,
  1063. .default_value = 720,
  1064. DEFREF(res_hor),
  1065. DEFINT(19,720),
  1066. },{
  1067. .desc = "Vertical capture resolution",
  1068. .name = "resolution_ver",
  1069. .internal_id = PVR2_CID_VRES,
  1070. .default_value = 480,
  1071. DEFREF(res_ver),
  1072. DEFINT(17,576),
  1073. /* Hook in check for video standard and adjust maximum
  1074. depending on the standard. */
  1075. .get_max_value = ctrl_vres_max_get,
  1076. .get_min_value = ctrl_vres_min_get,
  1077. },{
  1078. .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
  1079. .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
  1080. .desc = "Audio Sampling Frequency",
  1081. .name = "srate",
  1082. DEFREF(srate),
  1083. DEFENUM(control_values_srate),
  1084. },{
  1085. .desc = "Tuner Frequency (Hz)",
  1086. .name = "frequency",
  1087. .internal_id = PVR2_CID_FREQUENCY,
  1088. .default_value = 0,
  1089. .set_value = ctrl_freq_set,
  1090. .get_value = ctrl_freq_get,
  1091. .is_dirty = ctrl_freq_is_dirty,
  1092. .clear_dirty = ctrl_freq_clear_dirty,
  1093. DEFINT(0,0),
  1094. /* Hook in check for input value (tv/radio) and adjust
  1095. max/min values accordingly */
  1096. .get_max_value = ctrl_freq_max_get,
  1097. .get_min_value = ctrl_freq_min_get,
  1098. },{
  1099. .desc = "Channel",
  1100. .name = "channel",
  1101. .set_value = ctrl_channel_set,
  1102. .get_value = ctrl_channel_get,
  1103. DEFINT(0,FREQTABLE_SIZE),
  1104. },{
  1105. .desc = "Channel Program Frequency",
  1106. .name = "freq_table_value",
  1107. .set_value = ctrl_channelfreq_set,
  1108. .get_value = ctrl_channelfreq_get,
  1109. DEFINT(0,0),
  1110. /* Hook in check for input value (tv/radio) and adjust
  1111. max/min values accordingly */
  1112. .get_max_value = ctrl_freq_max_get,
  1113. .get_min_value = ctrl_freq_min_get,
  1114. },{
  1115. .desc = "Channel Program ID",
  1116. .name = "freq_table_channel",
  1117. .set_value = ctrl_channelprog_set,
  1118. .get_value = ctrl_channelprog_get,
  1119. DEFINT(0,FREQTABLE_SIZE),
  1120. },{
  1121. .desc = "Streaming Enabled",
  1122. .name = "streaming_enabled",
  1123. .get_value = ctrl_streamingenabled_get,
  1124. DEFBOOL,
  1125. },{
  1126. .desc = "USB Speed",
  1127. .name = "usb_speed",
  1128. .get_value = ctrl_hsm_get,
  1129. DEFENUM(control_values_hsm),
  1130. },{
  1131. .desc = "Master State",
  1132. .name = "master_state",
  1133. .get_value = ctrl_masterstate_get,
  1134. DEFENUM(pvr2_state_names),
  1135. },{
  1136. .desc = "Signal Present",
  1137. .name = "signal_present",
  1138. .get_value = ctrl_signal_get,
  1139. DEFINT(0,65535),
  1140. },{
  1141. .desc = "Audio Modes Present",
  1142. .name = "audio_modes_present",
  1143. .get_value = ctrl_audio_modes_present_get,
  1144. /* For this type we "borrow" the V4L2_TUNER_MODE enum from
  1145. v4l. Nothing outside of this module cares about this,
  1146. but I reuse it in order to also reuse the
  1147. control_values_audiomode string table. */
  1148. DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
  1149. (1 << V4L2_TUNER_MODE_STEREO)|
  1150. (1 << V4L2_TUNER_MODE_LANG1)|
  1151. (1 << V4L2_TUNER_MODE_LANG2)),
  1152. control_values_audiomode),
  1153. },{
  1154. .desc = "Video Standards Available Mask",
  1155. .name = "video_standard_mask_available",
  1156. .internal_id = PVR2_CID_STDAVAIL,
  1157. .skip_init = !0,
  1158. .get_value = ctrl_stdavail_get,
  1159. .set_value = ctrl_stdavail_set,
  1160. .val_to_sym = ctrl_std_val_to_sym,
  1161. .sym_to_val = ctrl_std_sym_to_val,
  1162. .type = pvr2_ctl_bitmask,
  1163. },{
  1164. .desc = "Video Standards In Use Mask",
  1165. .name = "video_standard_mask_active",
  1166. .internal_id = PVR2_CID_STDCUR,
  1167. .skip_init = !0,
  1168. .get_value = ctrl_stdcur_get,
  1169. .set_value = ctrl_stdcur_set,
  1170. .is_dirty = ctrl_stdcur_is_dirty,
  1171. .clear_dirty = ctrl_stdcur_clear_dirty,
  1172. .val_to_sym = ctrl_std_val_to_sym,
  1173. .sym_to_val = ctrl_std_sym_to_val,
  1174. .type = pvr2_ctl_bitmask,
  1175. },{
  1176. .desc = "Video Standard Name",
  1177. .name = "video_standard",
  1178. .internal_id = PVR2_CID_STDENUM,
  1179. .skip_init = !0,
  1180. .get_value = ctrl_stdenumcur_get,
  1181. .set_value = ctrl_stdenumcur_set,
  1182. .is_dirty = ctrl_stdenumcur_is_dirty,
  1183. .clear_dirty = ctrl_stdenumcur_clear_dirty,
  1184. .type = pvr2_ctl_enum,
  1185. }
  1186. };
  1187. #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
  1188. const char *pvr2_config_get_name(enum pvr2_config cfg)
  1189. {
  1190. switch (cfg) {
  1191. case pvr2_config_empty: return "empty";
  1192. case pvr2_config_mpeg: return "mpeg";
  1193. case pvr2_config_vbi: return "vbi";
  1194. case pvr2_config_pcm: return "pcm";
  1195. case pvr2_config_rawvideo: return "raw video";
  1196. }
  1197. return "<unknown>";
  1198. }
  1199. struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
  1200. {
  1201. return hdw->usb_dev;
  1202. }
  1203. unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
  1204. {
  1205. return hdw->serial_number;
  1206. }
  1207. const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
  1208. {
  1209. return hdw->bus_info;
  1210. }
  1211. const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
  1212. {
  1213. return hdw->identifier;
  1214. }
  1215. unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
  1216. {
  1217. return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
  1218. }
  1219. /* Set the currently tuned frequency and account for all possible
  1220. driver-core side effects of this action. */
  1221. static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
  1222. {
  1223. if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
  1224. if (hdw->freqSelector) {
  1225. /* Swing over to radio frequency selection */
  1226. hdw->freqSelector = 0;
  1227. hdw->freqDirty = !0;
  1228. }
  1229. if (hdw->freqValRadio != val) {
  1230. hdw->freqValRadio = val;
  1231. hdw->freqSlotRadio = 0;
  1232. hdw->freqDirty = !0;
  1233. }
  1234. } else {
  1235. if (!(hdw->freqSelector)) {
  1236. /* Swing over to television frequency selection */
  1237. hdw->freqSelector = 1;
  1238. hdw->freqDirty = !0;
  1239. }
  1240. if (hdw->freqValTelevision != val) {
  1241. hdw->freqValTelevision = val;
  1242. hdw->freqSlotTelevision = 0;
  1243. hdw->freqDirty = !0;
  1244. }
  1245. }
  1246. }
  1247. int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
  1248. {
  1249. return hdw->unit_number;
  1250. }
  1251. /* Attempt to locate one of the given set of files. Messages are logged
  1252. appropriate to what has been found. The return value will be 0 or
  1253. greater on success (it will be the index of the file name found) and
  1254. fw_entry will be filled in. Otherwise a negative error is returned on
  1255. failure. If the return value is -ENOENT then no viable firmware file
  1256. could be located. */
  1257. static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
  1258. const struct firmware **fw_entry,
  1259. const char *fwtypename,
  1260. unsigned int fwcount,
  1261. const char *fwnames[])
  1262. {
  1263. unsigned int idx;
  1264. int ret = -EINVAL;
  1265. for (idx = 0; idx < fwcount; idx++) {
  1266. ret = request_firmware(fw_entry,
  1267. fwnames[idx],
  1268. &hdw->usb_dev->dev);
  1269. if (!ret) {
  1270. trace_firmware("Located %s firmware: %s;"
  1271. " uploading...",
  1272. fwtypename,
  1273. fwnames[idx]);
  1274. return idx;
  1275. }
  1276. if (ret == -ENOENT) continue;
  1277. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1278. "request_firmware fatal error with code=%d",ret);
  1279. return ret;
  1280. }
  1281. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1282. "***WARNING***"
  1283. " Device %s firmware"
  1284. " seems to be missing.",
  1285. fwtypename);
  1286. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1287. "Did you install the pvrusb2 firmware files"
  1288. " in their proper location?");
  1289. if (fwcount == 1) {
  1290. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1291. "request_firmware unable to locate %s file %s",
  1292. fwtypename,fwnames[0]);
  1293. } else {
  1294. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1295. "request_firmware unable to locate"
  1296. " one of the following %s files:",
  1297. fwtypename);
  1298. for (idx = 0; idx < fwcount; idx++) {
  1299. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1300. "request_firmware: Failed to find %s",
  1301. fwnames[idx]);
  1302. }
  1303. }
  1304. return ret;
  1305. }
  1306. /*
  1307. * pvr2_upload_firmware1().
  1308. *
  1309. * Send the 8051 firmware to the device. After the upload, arrange for
  1310. * device to re-enumerate.
  1311. *
  1312. * NOTE : the pointer to the firmware data given by request_firmware()
  1313. * is not suitable for an usb transaction.
  1314. *
  1315. */
  1316. static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
  1317. {
  1318. const struct firmware *fw_entry = NULL;
  1319. void *fw_ptr;
  1320. unsigned int pipe;
  1321. unsigned int fwsize;
  1322. int ret;
  1323. u16 address;
  1324. if (!hdw->hdw_desc->fx2_firmware.cnt) {
  1325. hdw->fw1_state = FW1_STATE_OK;
  1326. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1327. "Connected device type defines"
  1328. " no firmware to upload; ignoring firmware");
  1329. return -ENOTTY;
  1330. }
  1331. hdw->fw1_state = FW1_STATE_FAILED; // default result
  1332. trace_firmware("pvr2_upload_firmware1");
  1333. ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
  1334. hdw->hdw_desc->fx2_firmware.cnt,
  1335. hdw->hdw_desc->fx2_firmware.lst);
  1336. if (ret < 0) {
  1337. if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
  1338. return ret;
  1339. }
  1340. usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
  1341. pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
  1342. fwsize = fw_entry->size;
  1343. if ((fwsize != 0x2000) &&
  1344. (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
  1345. if (hdw->hdw_desc->flag_fx2_16kb) {
  1346. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1347. "Wrong fx2 firmware size"
  1348. " (expected 8192 or 16384, got %u)",
  1349. fwsize);
  1350. } else {
  1351. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1352. "Wrong fx2 firmware size"
  1353. " (expected 8192, got %u)",
  1354. fwsize);
  1355. }
  1356. release_firmware(fw_entry);
  1357. return -ENOMEM;
  1358. }
  1359. fw_ptr = kmalloc(0x800, GFP_KERNEL);
  1360. if (fw_ptr == NULL){
  1361. release_firmware(fw_entry);
  1362. return -ENOMEM;
  1363. }
  1364. /* We have to hold the CPU during firmware upload. */
  1365. pvr2_hdw_cpureset_assert(hdw,1);
  1366. /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
  1367. chunk. */
  1368. ret = 0;
  1369. for (address = 0; address < fwsize; address += 0x800) {
  1370. memcpy(fw_ptr, fw_entry->data + address, 0x800);
  1371. ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
  1372. 0, fw_ptr, 0x800, HZ);
  1373. }
  1374. trace_firmware("Upload done, releasing device's CPU");
  1375. /* Now release the CPU. It will disconnect and reconnect later. */
  1376. pvr2_hdw_cpureset_assert(hdw,0);
  1377. kfree(fw_ptr);
  1378. release_firmware(fw_entry);
  1379. trace_firmware("Upload done (%d bytes sent)",ret);
  1380. /* We should have written fwsize bytes */
  1381. if (ret == fwsize) {
  1382. hdw->fw1_state = FW1_STATE_RELOAD;
  1383. return 0;
  1384. }
  1385. return -EIO;
  1386. }
  1387. /*
  1388. * pvr2_upload_firmware2()
  1389. *
  1390. * This uploads encoder firmware on endpoint 2.
  1391. *
  1392. */
  1393. int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
  1394. {
  1395. const struct firmware *fw_entry = NULL;
  1396. void *fw_ptr;
  1397. unsigned int pipe, fw_len, fw_done, bcnt, icnt;
  1398. int actual_length;
  1399. int ret = 0;
  1400. int fwidx;
  1401. static const char *fw_files[] = {
  1402. CX2341X_FIRM_ENC_FILENAME,
  1403. };
  1404. if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
  1405. return 0;
  1406. }
  1407. trace_firmware("pvr2_upload_firmware2");
  1408. ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
  1409. ARRAY_SIZE(fw_files), fw_files);
  1410. if (ret < 0) return ret;
  1411. fwidx = ret;
  1412. ret = 0;
  1413. /* Since we're about to completely reinitialize the encoder,
  1414. invalidate our cached copy of its configuration state. Next
  1415. time we configure the encoder, then we'll fully configure it. */
  1416. hdw->enc_cur_valid = 0;
  1417. /* Encoder is about to be reset so note that as far as we're
  1418. concerned now, the encoder has never been run. */
  1419. del_timer_sync(&hdw->encoder_run_timer);
  1420. if (hdw->state_encoder_runok) {
  1421. hdw->state_encoder_runok = 0;
  1422. trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
  1423. }
  1424. /* First prepare firmware loading */
  1425. ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
  1426. ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
  1427. ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
  1428. ret |= pvr2_hdw_cmd_deep_reset(hdw);
  1429. ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
  1430. ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
  1431. ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
  1432. ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
  1433. ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
  1434. ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
  1435. ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
  1436. ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
  1437. ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
  1438. ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
  1439. ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
  1440. ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
  1441. ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
  1442. ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
  1443. if (ret) {
  1444. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1445. "firmware2 upload prep failed, ret=%d",ret);
  1446. release_firmware(fw_entry);
  1447. goto done;
  1448. }
  1449. /* Now send firmware */
  1450. fw_len = fw_entry->size;
  1451. if (fw_len % sizeof(u32)) {
  1452. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1453. "size of %s firmware"
  1454. " must be a multiple of %zu bytes",
  1455. fw_files[fwidx],sizeof(u32));
  1456. release_firmware(fw_entry);
  1457. ret = -EINVAL;
  1458. goto done;
  1459. }
  1460. fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
  1461. if (fw_ptr == NULL){
  1462. release_firmware(fw_entry);
  1463. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1464. "failed to allocate memory for firmware2 upload");
  1465. ret = -ENOMEM;
  1466. goto done;
  1467. }
  1468. pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
  1469. fw_done = 0;
  1470. for (fw_done = 0; fw_done < fw_len;) {
  1471. bcnt = fw_len - fw_done;
  1472. if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
  1473. memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
  1474. /* Usbsnoop log shows that we must swap bytes... */
  1475. /* Some background info: The data being swapped here is a
  1476. firmware image destined for the mpeg encoder chip that
  1477. lives at the other end of a USB endpoint. The encoder
  1478. chip always talks in 32 bit chunks and its storage is
  1479. organized into 32 bit words. However from the file
  1480. system to the encoder chip everything is purely a byte
  1481. stream. The firmware file's contents are always 32 bit
  1482. swapped from what the encoder expects. Thus the need
  1483. always exists to swap the bytes regardless of the endian
  1484. type of the host processor and therefore swab32() makes
  1485. the most sense. */
  1486. for (icnt = 0; icnt < bcnt/4 ; icnt++)
  1487. ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
  1488. ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
  1489. &actual_length, HZ);
  1490. ret |= (actual_length != bcnt);
  1491. if (ret) break;
  1492. fw_done += bcnt;
  1493. }
  1494. trace_firmware("upload of %s : %i / %i ",
  1495. fw_files[fwidx],fw_done,fw_len);
  1496. kfree(fw_ptr);
  1497. release_firmware(fw_entry);
  1498. if (ret) {
  1499. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1500. "firmware2 upload transfer failure");
  1501. goto done;
  1502. }
  1503. /* Finish upload */
  1504. ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
  1505. ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
  1506. ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
  1507. if (ret) {
  1508. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1509. "firmware2 upload post-proc failure");
  1510. }
  1511. done:
  1512. if (hdw->hdw_desc->signal_routing_scheme ==
  1513. PVR2_ROUTING_SCHEME_GOTVIEW) {
  1514. /* Ensure that GPIO 11 is set to output for GOTVIEW
  1515. hardware. */
  1516. pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
  1517. }
  1518. return ret;
  1519. }
  1520. static const char *pvr2_get_state_name(unsigned int st)
  1521. {
  1522. if (st < ARRAY_SIZE(pvr2_state_names)) {
  1523. return pvr2_state_names[st];
  1524. }
  1525. return "???";
  1526. }
  1527. static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
  1528. {
  1529. /* Even though we really only care about the video decoder chip at
  1530. this point, we'll broadcast stream on/off to all sub-devices
  1531. anyway, just in case somebody else wants to hear the
  1532. command... */
  1533. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
  1534. (enablefl ? "on" : "off"));
  1535. v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
  1536. v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
  1537. if (hdw->decoder_client_id) {
  1538. /* We get here if the encoder has been noticed. Otherwise
  1539. we'll issue a warning to the user (which should
  1540. normally never happen). */
  1541. return 0;
  1542. }
  1543. if (!hdw->flag_decoder_missed) {
  1544. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1545. "WARNING: No decoder present");
  1546. hdw->flag_decoder_missed = !0;
  1547. trace_stbit("flag_decoder_missed",
  1548. hdw->flag_decoder_missed);
  1549. }
  1550. return -EIO;
  1551. }
  1552. int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
  1553. {
  1554. return hdw->master_state;
  1555. }
  1556. static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
  1557. {
  1558. if (!hdw->flag_tripped) return 0;
  1559. hdw->flag_tripped = 0;
  1560. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1561. "Clearing driver error statuss");
  1562. return !0;
  1563. }
  1564. int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
  1565. {
  1566. int fl;
  1567. LOCK_TAKE(hdw->big_lock); do {
  1568. fl = pvr2_hdw_untrip_unlocked(hdw);
  1569. } while (0); LOCK_GIVE(hdw->big_lock);
  1570. if (fl) pvr2_hdw_state_sched(hdw);
  1571. return 0;
  1572. }
  1573. int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
  1574. {
  1575. return hdw->state_pipeline_req != 0;
  1576. }
  1577. int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
  1578. {
  1579. int ret,st;
  1580. LOCK_TAKE(hdw->big_lock); do {
  1581. pvr2_hdw_untrip_unlocked(hdw);
  1582. if ((!enable_flag) != !(hdw->state_pipeline_req)) {
  1583. hdw->state_pipeline_req = enable_flag != 0;
  1584. pvr2_trace(PVR2_TRACE_START_STOP,
  1585. "/*--TRACE_STREAM--*/ %s",
  1586. enable_flag ? "enable" : "disable");
  1587. }
  1588. pvr2_hdw_state_sched(hdw);
  1589. } while (0); LOCK_GIVE(hdw->big_lock);
  1590. if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
  1591. if (enable_flag) {
  1592. while ((st = hdw->master_state) != PVR2_STATE_RUN) {
  1593. if (st != PVR2_STATE_READY) return -EIO;
  1594. if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
  1595. }
  1596. }
  1597. return 0;
  1598. }
  1599. int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
  1600. {
  1601. int fl;
  1602. LOCK_TAKE(hdw->big_lock);
  1603. if ((fl = (hdw->desired_stream_type != config)) != 0) {
  1604. hdw->desired_stream_type = config;
  1605. hdw->state_pipeline_config = 0;
  1606. trace_stbit("state_pipeline_config",
  1607. hdw->state_pipeline_config);
  1608. pvr2_hdw_state_sched(hdw);
  1609. }
  1610. LOCK_GIVE(hdw->big_lock);
  1611. if (fl) return 0;
  1612. return pvr2_hdw_wait(hdw,0);
  1613. }
  1614. static int get_default_tuner_type(struct pvr2_hdw *hdw)
  1615. {
  1616. int unit_number = hdw->unit_number;
  1617. int tp = -1;
  1618. if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
  1619. tp = tuner[unit_number];
  1620. }
  1621. if (tp < 0) return -EINVAL;
  1622. hdw->tuner_type = tp;
  1623. hdw->tuner_updated = !0;
  1624. return 0;
  1625. }
  1626. static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
  1627. {
  1628. int unit_number = hdw->unit_number;
  1629. int tp = 0;
  1630. if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
  1631. tp = video_std[unit_number];
  1632. if (tp) return tp;
  1633. }
  1634. return 0;
  1635. }
  1636. static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
  1637. {
  1638. int unit_number = hdw->unit_number;
  1639. int tp = 0;
  1640. if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
  1641. tp = tolerance[unit_number];
  1642. }
  1643. return tp;
  1644. }
  1645. static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
  1646. {
  1647. /* Try a harmless request to fetch the eeprom's address over
  1648. endpoint 1. See what happens. Only the full FX2 image can
  1649. respond to this. If this probe fails then likely the FX2
  1650. firmware needs be loaded. */
  1651. int result;
  1652. LOCK_TAKE(hdw->ctl_lock); do {
  1653. hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
  1654. result = pvr2_send_request_ex(hdw,HZ*1,!0,
  1655. hdw->cmd_buffer,1,
  1656. hdw->cmd_buffer,1);
  1657. if (result < 0) break;
  1658. } while(0); LOCK_GIVE(hdw->ctl_lock);
  1659. if (result) {
  1660. pvr2_trace(PVR2_TRACE_INIT,
  1661. "Probe of device endpoint 1 result status %d",
  1662. result);
  1663. } else {
  1664. pvr2_trace(PVR2_TRACE_INIT,
  1665. "Probe of device endpoint 1 succeeded");
  1666. }
  1667. return result == 0;
  1668. }
  1669. struct pvr2_std_hack {
  1670. v4l2_std_id pat; /* Pattern to match */
  1671. v4l2_std_id msk; /* Which bits we care about */
  1672. v4l2_std_id std; /* What additional standards or default to set */
  1673. };
  1674. /* This data structure labels specific combinations of standards from
  1675. tveeprom that we'll try to recognize. If we recognize one, then assume
  1676. a specified default standard to use. This is here because tveeprom only
  1677. tells us about available standards not the intended default standard (if
  1678. any) for the device in question. We guess the default based on what has
  1679. been reported as available. Note that this is only for guessing a
  1680. default - which can always be overridden explicitly - and if the user
  1681. has otherwise named a default then that default will always be used in
  1682. place of this table. */
  1683. static const struct pvr2_std_hack std_eeprom_maps[] = {
  1684. { /* PAL(B/G) */
  1685. .pat = V4L2_STD_B|V4L2_STD_GH,
  1686. .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
  1687. },
  1688. { /* NTSC(M) */
  1689. .pat = V4L2_STD_MN,
  1690. .std = V4L2_STD_NTSC_M,
  1691. },
  1692. { /* PAL(I) */
  1693. .pat = V4L2_STD_PAL_I,
  1694. .std = V4L2_STD_PAL_I,
  1695. },
  1696. { /* SECAM(L/L') */
  1697. .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
  1698. .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
  1699. },
  1700. { /* PAL(D/D1/K) */
  1701. .pat = V4L2_STD_DK,
  1702. .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
  1703. },
  1704. };
  1705. static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
  1706. {
  1707. char buf[40];
  1708. unsigned int bcnt;
  1709. v4l2_std_id std1,std2,std3;
  1710. std1 = get_default_standard(hdw);
  1711. std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
  1712. bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
  1713. pvr2_trace(PVR2_TRACE_STD,
  1714. "Supported video standard(s) reported available"
  1715. " in hardware: %.*s",
  1716. bcnt,buf);
  1717. hdw->std_mask_avail = hdw->std_mask_eeprom;
  1718. std2 = (std1|std3) & ~hdw->std_mask_avail;
  1719. if (std2) {
  1720. bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
  1721. pvr2_trace(PVR2_TRACE_STD,
  1722. "Expanding supported video standards"
  1723. " to include: %.*s",
  1724. bcnt,buf);
  1725. hdw->std_mask_avail |= std2;
  1726. }
  1727. pvr2_hdw_internal_set_std_avail(hdw);
  1728. if (std1) {
  1729. bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
  1730. pvr2_trace(PVR2_TRACE_STD,
  1731. "Initial video standard forced to %.*s",
  1732. bcnt,buf);
  1733. hdw->std_mask_cur = std1;
  1734. hdw->std_dirty = !0;
  1735. pvr2_hdw_internal_find_stdenum(hdw);
  1736. return;
  1737. }
  1738. if (std3) {
  1739. bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
  1740. pvr2_trace(PVR2_TRACE_STD,
  1741. "Initial video standard"
  1742. " (determined by device type): %.*s",bcnt,buf);
  1743. hdw->std_mask_cur = std3;
  1744. hdw->std_dirty = !0;
  1745. pvr2_hdw_internal_find_stdenum(hdw);
  1746. return;
  1747. }
  1748. {
  1749. unsigned int idx;
  1750. for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
  1751. if (std_eeprom_maps[idx].msk ?
  1752. ((std_eeprom_maps[idx].pat ^
  1753. hdw->std_mask_eeprom) &
  1754. std_eeprom_maps[idx].msk) :
  1755. (std_eeprom_maps[idx].pat !=
  1756. hdw->std_mask_eeprom)) continue;
  1757. bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
  1758. std_eeprom_maps[idx].std);
  1759. pvr2_trace(PVR2_TRACE_STD,
  1760. "Initial video standard guessed as %.*s",
  1761. bcnt,buf);
  1762. hdw->std_mask_cur = std_eeprom_maps[idx].std;
  1763. hdw->std_dirty = !0;
  1764. pvr2_hdw_internal_find_stdenum(hdw);
  1765. return;
  1766. }
  1767. }
  1768. if (hdw->std_enum_cnt > 1) {
  1769. // Autoselect the first listed standard
  1770. hdw->std_enum_cur = 1;
  1771. hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
  1772. hdw->std_dirty = !0;
  1773. pvr2_trace(PVR2_TRACE_STD,
  1774. "Initial video standard auto-selected to %s",
  1775. hdw->std_defs[hdw->std_enum_cur-1].name);
  1776. return;
  1777. }
  1778. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1779. "Unable to select a viable initial video standard");
  1780. }
  1781. static unsigned int pvr2_copy_i2c_addr_list(
  1782. unsigned short *dst, const unsigned char *src,
  1783. unsigned int dst_max)
  1784. {
  1785. unsigned int cnt = 0;
  1786. if (!src) return 0;
  1787. while (src[cnt] && (cnt + 1) < dst_max) {
  1788. dst[cnt] = src[cnt];
  1789. cnt++;
  1790. }
  1791. dst[cnt] = I2C_CLIENT_END;
  1792. return cnt;
  1793. }
  1794. static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
  1795. {
  1796. /*
  1797. Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
  1798. for cx25840 causes that module to correctly set up its video
  1799. scaling. This is really a problem in the cx25840 module itself,
  1800. but we work around it here. The problem has not been seen in
  1801. ivtv because there VBI is supported and set up. We don't do VBI
  1802. here (at least not yet) and thus we never attempted to even set
  1803. it up.
  1804. */
  1805. struct v4l2_format fmt;
  1806. if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
  1807. /* We're not using a cx25840 so don't enable the hack */
  1808. return;
  1809. }
  1810. pvr2_trace(PVR2_TRACE_INIT,
  1811. "Module ID %u:"
  1812. " Executing cx25840 VBI hack",
  1813. hdw->decoder_client_id);
  1814. memset(&fmt, 0, sizeof(fmt));
  1815. fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
  1816. fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
  1817. fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
  1818. v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
  1819. vbi, s_sliced_fmt, &fmt.fmt.sliced);
  1820. }
  1821. static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
  1822. const struct pvr2_device_client_desc *cd)
  1823. {
  1824. const char *fname;
  1825. unsigned char mid;
  1826. struct v4l2_subdev *sd;
  1827. unsigned int i2ccnt;
  1828. const unsigned char *p;
  1829. /* Arbitrary count - max # i2c addresses we will probe */
  1830. unsigned short i2caddr[25];
  1831. mid = cd->module_id;
  1832. fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
  1833. if (!fname) {
  1834. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1835. "Module ID %u for device %s has no name?"
  1836. " The driver might have a configuration problem.",
  1837. mid,
  1838. hdw->hdw_desc->description);
  1839. return -EINVAL;
  1840. }
  1841. pvr2_trace(PVR2_TRACE_INIT,
  1842. "Module ID %u (%s) for device %s being loaded...",
  1843. mid, fname,
  1844. hdw->hdw_desc->description);
  1845. i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
  1846. ARRAY_SIZE(i2caddr));
  1847. if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
  1848. module_i2c_addresses[mid] : NULL) != NULL)) {
  1849. /* Second chance: Try default i2c address list */
  1850. i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
  1851. ARRAY_SIZE(i2caddr));
  1852. if (i2ccnt) {
  1853. pvr2_trace(PVR2_TRACE_INIT,
  1854. "Module ID %u:"
  1855. " Using default i2c address list",
  1856. mid);
  1857. }
  1858. }
  1859. if (!i2ccnt) {
  1860. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1861. "Module ID %u (%s) for device %s:"
  1862. " No i2c addresses."
  1863. " The driver might have a configuration problem.",
  1864. mid, fname, hdw->hdw_desc->description);
  1865. return -EINVAL;
  1866. }
  1867. if (i2ccnt == 1) {
  1868. pvr2_trace(PVR2_TRACE_INIT,
  1869. "Module ID %u:"
  1870. " Setting up with specified i2c address 0x%x",
  1871. mid, i2caddr[0]);
  1872. sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
  1873. fname, i2caddr[0], NULL);
  1874. } else {
  1875. pvr2_trace(PVR2_TRACE_INIT,
  1876. "Module ID %u:"
  1877. " Setting up with address probe list",
  1878. mid);
  1879. sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
  1880. fname, 0, i2caddr);
  1881. }
  1882. if (!sd) {
  1883. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1884. "Module ID %u (%s) for device %s failed to load."
  1885. " Possible missing sub-device kernel module or"
  1886. " initialization failure within module.",
  1887. mid, fname, hdw->hdw_desc->description);
  1888. return -EIO;
  1889. }
  1890. /* Tag this sub-device instance with the module ID we know about.
  1891. In other places we'll use that tag to determine if the instance
  1892. requires special handling. */
  1893. sd->grp_id = mid;
  1894. pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
  1895. /* client-specific setup... */
  1896. switch (mid) {
  1897. case PVR2_CLIENT_ID_CX25840:
  1898. case PVR2_CLIENT_ID_SAA7115:
  1899. hdw->decoder_client_id = mid;
  1900. break;
  1901. default: break;
  1902. }
  1903. return 0;
  1904. }
  1905. static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
  1906. {
  1907. unsigned int idx;
  1908. const struct pvr2_string_table *cm;
  1909. const struct pvr2_device_client_table *ct;
  1910. int okFl = !0;
  1911. cm = &hdw->hdw_desc->client_modules;
  1912. for (idx = 0; idx < cm->cnt; idx++) {
  1913. request_module(cm->lst[idx]);
  1914. }
  1915. ct = &hdw->hdw_desc->client_table;
  1916. for (idx = 0; idx < ct->cnt; idx++) {
  1917. if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
  1918. }
  1919. if (!okFl) {
  1920. hdw->flag_modulefail = !0;
  1921. pvr2_hdw_render_useless(hdw);
  1922. }
  1923. }
  1924. static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
  1925. {
  1926. int ret;
  1927. unsigned int idx;
  1928. struct pvr2_ctrl *cptr;
  1929. int reloadFl = 0;
  1930. if (hdw->hdw_desc->fx2_firmware.cnt) {
  1931. if (!reloadFl) {
  1932. reloadFl =
  1933. (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
  1934. == 0);
  1935. if (reloadFl) {
  1936. pvr2_trace(PVR2_TRACE_INIT,
  1937. "USB endpoint config looks strange"
  1938. "; possibly firmware needs to be"
  1939. " loaded");
  1940. }
  1941. }
  1942. if (!reloadFl) {
  1943. reloadFl = !pvr2_hdw_check_firmware(hdw);
  1944. if (reloadFl) {
  1945. pvr2_trace(PVR2_TRACE_INIT,
  1946. "Check for FX2 firmware failed"
  1947. "; possibly firmware needs to be"
  1948. " loaded");
  1949. }
  1950. }
  1951. if (reloadFl) {
  1952. if (pvr2_upload_firmware1(hdw) != 0) {
  1953. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  1954. "Failure uploading firmware1");
  1955. }
  1956. return;
  1957. }
  1958. }
  1959. hdw->fw1_state = FW1_STATE_OK;
  1960. if (!pvr2_hdw_dev_ok(hdw)) return;
  1961. hdw->force_dirty = !0;
  1962. if (!hdw->hdw_desc->flag_no_powerup) {
  1963. pvr2_hdw_cmd_powerup(hdw);
  1964. if (!pvr2_hdw_dev_ok(hdw)) return;
  1965. }
  1966. /* Take the IR chip out of reset, if appropriate */
  1967. if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
  1968. pvr2_issue_simple_cmd(hdw,
  1969. FX2CMD_HCW_ZILOG_RESET |
  1970. (1 << 8) |
  1971. ((0) << 16));
  1972. }
  1973. // This step MUST happen after the earlier powerup step.
  1974. pvr2_i2c_core_init(hdw);
  1975. if (!pvr2_hdw_dev_ok(hdw)) return;
  1976. pvr2_hdw_load_modules(hdw);
  1977. if (!pvr2_hdw_dev_ok(hdw)) return;
  1978. v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
  1979. for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
  1980. cptr = hdw->controls + idx;
  1981. if (cptr->info->skip_init) continue;
  1982. if (!cptr->info->set_value) continue;
  1983. cptr->info->set_value(cptr,~0,cptr->info->default_value);
  1984. }
  1985. pvr2_hdw_cx25840_vbi_hack(hdw);
  1986. /* Set up special default values for the television and radio
  1987. frequencies here. It's not really important what these defaults
  1988. are, but I set them to something usable in the Chicago area just
  1989. to make driver testing a little easier. */
  1990. hdw->freqValTelevision = default_tv_freq;
  1991. hdw->freqValRadio = default_radio_freq;
  1992. // Do not use pvr2_reset_ctl_endpoints() here. It is not
  1993. // thread-safe against the normal pvr2_send_request() mechanism.
  1994. // (We should make it thread safe).
  1995. if (hdw->hdw_desc->flag_has_hauppauge_rom) {
  1996. ret = pvr2_hdw_get_eeprom_addr(hdw);
  1997. if (!pvr2_hdw_dev_ok(hdw)) return;
  1998. if (ret < 0) {
  1999. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  2000. "Unable to determine location of eeprom,"
  2001. " skipping");
  2002. } else {
  2003. hdw->eeprom_addr = ret;
  2004. pvr2_eeprom_analyze(hdw);
  2005. if (!pvr2_hdw_dev_ok(hdw)) return;
  2006. }
  2007. } else {
  2008. hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
  2009. hdw->tuner_updated = !0;
  2010. hdw->std_mask_eeprom = V4L2_STD_ALL;
  2011. }
  2012. if (hdw->serial_number) {
  2013. idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
  2014. "sn-%lu", hdw->serial_number);
  2015. } else if (hdw->unit_number >= 0) {
  2016. idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
  2017. "unit-%c",
  2018. hdw->unit_number + 'a');
  2019. } else {
  2020. idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
  2021. "unit-??");
  2022. }
  2023. hdw->identifier[idx] = 0;
  2024. pvr2_hdw_setup_std(hdw);
  2025. if (!get_default_tuner_type(hdw)) {
  2026. pvr2_trace(PVR2_TRACE_INIT,
  2027. "pvr2_hdw_setup: Tuner type overridden to %d",
  2028. hdw->tuner_type);
  2029. }
  2030. if (!pvr2_hdw_dev_ok(hdw)) return;
  2031. if (hdw->hdw_desc->signal_routing_scheme ==
  2032. PVR2_ROUTING_SCHEME_GOTVIEW) {
  2033. /* Ensure that GPIO 11 is set to output for GOTVIEW
  2034. hardware. */
  2035. pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
  2036. }
  2037. pvr2_hdw_commit_setup(hdw);
  2038. hdw->vid_stream = pvr2_stream_create();
  2039. if (!pvr2_hdw_dev_ok(hdw)) return;
  2040. pvr2_trace(PVR2_TRACE_INIT,
  2041. "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
  2042. if (hdw->vid_stream) {
  2043. idx = get_default_error_tolerance(hdw);
  2044. if (idx) {
  2045. pvr2_trace(PVR2_TRACE_INIT,
  2046. "pvr2_hdw_setup: video stream %p"
  2047. " setting tolerance %u",
  2048. hdw->vid_stream,idx);
  2049. }
  2050. pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
  2051. PVR2_VID_ENDPOINT,idx);
  2052. }
  2053. if (!pvr2_hdw_dev_ok(hdw)) return;
  2054. hdw->flag_init_ok = !0;
  2055. pvr2_hdw_state_sched(hdw);
  2056. }
  2057. /* Set up the structure and attempt to put the device into a usable state.
  2058. This can be a time-consuming operation, which is why it is not done
  2059. internally as part of the create() step. */
  2060. static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
  2061. {
  2062. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
  2063. do {
  2064. pvr2_hdw_setup_low(hdw);
  2065. pvr2_trace(PVR2_TRACE_INIT,
  2066. "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
  2067. hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
  2068. if (pvr2_hdw_dev_ok(hdw)) {
  2069. if (hdw->flag_init_ok) {
  2070. pvr2_trace(
  2071. PVR2_TRACE_INFO,
  2072. "Device initialization"
  2073. " completed successfully.");
  2074. break;
  2075. }
  2076. if (hdw->fw1_state == FW1_STATE_RELOAD) {
  2077. pvr2_trace(
  2078. PVR2_TRACE_INFO,
  2079. "Device microcontroller firmware"
  2080. " (re)loaded; it should now reset"
  2081. " and reconnect.");
  2082. break;
  2083. }
  2084. pvr2_trace(
  2085. PVR2_TRACE_ERROR_LEGS,
  2086. "Device initialization was not successful.");
  2087. if (hdw->fw1_state == FW1_STATE_MISSING) {
  2088. pvr2_trace(
  2089. PVR2_TRACE_ERROR_LEGS,
  2090. "Giving up since device"
  2091. " microcontroller firmware"
  2092. " appears to be missing.");
  2093. break;
  2094. }
  2095. }
  2096. if (hdw->flag_modulefail) {
  2097. pvr2_trace(
  2098. PVR2_TRACE_ERROR_LEGS,
  2099. "***WARNING*** pvrusb2 driver initialization"
  2100. " failed due to the failure of one or more"
  2101. " sub-device kernel modules.");
  2102. pvr2_trace(
  2103. PVR2_TRACE_ERROR_LEGS,
  2104. "You need to resolve the failing condition"
  2105. " before this driver can function. There"
  2106. " should be some earlier messages giving more"
  2107. " information about the problem.");
  2108. break;
  2109. }
  2110. if (procreload) {
  2111. pvr2_trace(
  2112. PVR2_TRACE_ERROR_LEGS,
  2113. "Attempting pvrusb2 recovery by reloading"
  2114. " primary firmware.");
  2115. pvr2_trace(
  2116. PVR2_TRACE_ERROR_LEGS,
  2117. "If this works, device should disconnect"
  2118. " and reconnect in a sane state.");
  2119. hdw->fw1_state = FW1_STATE_UNKNOWN;
  2120. pvr2_upload_firmware1(hdw);
  2121. } else {
  2122. pvr2_trace(
  2123. PVR2_TRACE_ERROR_LEGS,
  2124. "***WARNING*** pvrusb2 device hardware"
  2125. " appears to be jammed"
  2126. " and I can't clear it.");
  2127. pvr2_trace(
  2128. PVR2_TRACE_ERROR_LEGS,
  2129. "You might need to power cycle"
  2130. " the pvrusb2 device"
  2131. " in order to recover.");
  2132. }
  2133. } while (0);
  2134. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
  2135. }
  2136. /* Perform second stage initialization. Set callback pointer first so that
  2137. we can avoid a possible initialization race (if the kernel thread runs
  2138. before the callback has been set). */
  2139. int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
  2140. void (*callback_func)(void *),
  2141. void *callback_data)
  2142. {
  2143. LOCK_TAKE(hdw->big_lock); do {
  2144. if (hdw->flag_disconnected) {
  2145. /* Handle a race here: If we're already
  2146. disconnected by this point, then give up. If we
  2147. get past this then we'll remain connected for
  2148. the duration of initialization since the entire
  2149. initialization sequence is now protected by the
  2150. big_lock. */
  2151. break;
  2152. }
  2153. hdw->state_data = callback_data;
  2154. hdw->state_func = callback_func;
  2155. pvr2_hdw_setup(hdw);
  2156. } while (0); LOCK_GIVE(hdw->big_lock);
  2157. return hdw->flag_init_ok;
  2158. }
  2159. /* Create, set up, and return a structure for interacting with the
  2160. underlying hardware. */
  2161. struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
  2162. const struct usb_device_id *devid)
  2163. {
  2164. unsigned int idx,cnt1,cnt2,m;
  2165. struct pvr2_hdw *hdw = NULL;
  2166. int valid_std_mask;
  2167. struct pvr2_ctrl *cptr;
  2168. struct usb_device *usb_dev;
  2169. const struct pvr2_device_desc *hdw_desc;
  2170. __u8 ifnum;
  2171. struct v4l2_queryctrl qctrl;
  2172. struct pvr2_ctl_info *ciptr;
  2173. usb_dev = interface_to_usbdev(intf);
  2174. hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
  2175. if (hdw_desc == NULL) {
  2176. pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
  2177. " No device description pointer,"
  2178. " unable to continue.");
  2179. pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
  2180. " please contact Mike Isely <isely@pobox.com>"
  2181. " to get it included in the driver\n");
  2182. goto fail;
  2183. }
  2184. hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
  2185. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
  2186. hdw,hdw_desc->description);
  2187. pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
  2188. hdw_desc->description);
  2189. if (hdw_desc->flag_is_experimental) {
  2190. pvr2_trace(PVR2_TRACE_INFO, "**********");
  2191. pvr2_trace(PVR2_TRACE_INFO,
  2192. "WARNING: Support for this device (%s) is"
  2193. " experimental.", hdw_desc->description);
  2194. pvr2_trace(PVR2_TRACE_INFO,
  2195. "Important functionality might not be"
  2196. " entirely working.");
  2197. pvr2_trace(PVR2_TRACE_INFO,
  2198. "Please consider contacting the driver author to"
  2199. " help with further stabilization of the driver.");
  2200. pvr2_trace(PVR2_TRACE_INFO, "**********");
  2201. }
  2202. if (!hdw) goto fail;
  2203. init_timer(&hdw->quiescent_timer);
  2204. hdw->quiescent_timer.data = (unsigned long)hdw;
  2205. hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
  2206. init_timer(&hdw->decoder_stabilization_timer);
  2207. hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
  2208. hdw->decoder_stabilization_timer.function =
  2209. pvr2_hdw_decoder_stabilization_timeout;
  2210. init_timer(&hdw->encoder_wait_timer);
  2211. hdw->encoder_wait_timer.data = (unsigned long)hdw;
  2212. hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
  2213. init_timer(&hdw->encoder_run_timer);
  2214. hdw->encoder_run_timer.data = (unsigned long)hdw;
  2215. hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
  2216. hdw->master_state = PVR2_STATE_DEAD;
  2217. init_waitqueue_head(&hdw->state_wait_data);
  2218. hdw->tuner_signal_stale = !0;
  2219. cx2341x_fill_defaults(&hdw->enc_ctl_state);
  2220. /* Calculate which inputs are OK */
  2221. m = 0;
  2222. if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
  2223. if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
  2224. m |= 1 << PVR2_CVAL_INPUT_DTV;
  2225. }
  2226. if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
  2227. if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
  2228. if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
  2229. hdw->input_avail_mask = m;
  2230. hdw->input_allowed_mask = hdw->input_avail_mask;
  2231. /* If not a hybrid device, pathway_state never changes. So
  2232. initialize it here to what it should forever be. */
  2233. if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
  2234. hdw->pathway_state = PVR2_PATHWAY_ANALOG;
  2235. } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
  2236. hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
  2237. }
  2238. hdw->control_cnt = CTRLDEF_COUNT;
  2239. hdw->control_cnt += MPEGDEF_COUNT;
  2240. hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
  2241. GFP_KERNEL);
  2242. if (!hdw->controls) goto fail;
  2243. hdw->hdw_desc = hdw_desc;
  2244. hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
  2245. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2246. cptr = hdw->controls + idx;
  2247. cptr->hdw = hdw;
  2248. }
  2249. for (idx = 0; idx < 32; idx++) {
  2250. hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
  2251. }
  2252. for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
  2253. cptr = hdw->controls + idx;
  2254. cptr->info = control_defs+idx;
  2255. }
  2256. /* Ensure that default input choice is a valid one. */
  2257. m = hdw->input_avail_mask;
  2258. if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
  2259. if (!((1 << idx) & m)) continue;
  2260. hdw->input_val = idx;
  2261. break;
  2262. }
  2263. /* Define and configure additional controls from cx2341x module. */
  2264. hdw->mpeg_ctrl_info = kzalloc(
  2265. sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
  2266. if (!hdw->mpeg_ctrl_info) goto fail;
  2267. for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
  2268. cptr = hdw->controls + idx + CTRLDEF_COUNT;
  2269. ciptr = &(hdw->mpeg_ctrl_info[idx].info);
  2270. ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
  2271. ciptr->name = mpeg_ids[idx].strid;
  2272. ciptr->v4l_id = mpeg_ids[idx].id;
  2273. ciptr->skip_init = !0;
  2274. ciptr->get_value = ctrl_cx2341x_get;
  2275. ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
  2276. ciptr->is_dirty = ctrl_cx2341x_is_dirty;
  2277. if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
  2278. qctrl.id = ciptr->v4l_id;
  2279. cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
  2280. if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
  2281. ciptr->set_value = ctrl_cx2341x_set;
  2282. }
  2283. strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
  2284. PVR2_CTLD_INFO_DESC_SIZE);
  2285. hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
  2286. ciptr->default_value = qctrl.default_value;
  2287. switch (qctrl.type) {
  2288. default:
  2289. case V4L2_CTRL_TYPE_INTEGER:
  2290. ciptr->type = pvr2_ctl_int;
  2291. ciptr->def.type_int.min_value = qctrl.minimum;
  2292. ciptr->def.type_int.max_value = qctrl.maximum;
  2293. break;
  2294. case V4L2_CTRL_TYPE_BOOLEAN:
  2295. ciptr->type = pvr2_ctl_bool;
  2296. break;
  2297. case V4L2_CTRL_TYPE_MENU:
  2298. ciptr->type = pvr2_ctl_enum;
  2299. ciptr->def.type_enum.value_names =
  2300. cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
  2301. ciptr->v4l_id);
  2302. for (cnt1 = 0;
  2303. ciptr->def.type_enum.value_names[cnt1] != NULL;
  2304. cnt1++) { }
  2305. ciptr->def.type_enum.count = cnt1;
  2306. break;
  2307. }
  2308. cptr->info = ciptr;
  2309. }
  2310. // Initialize video standard enum dynamic control
  2311. cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
  2312. if (cptr) {
  2313. memcpy(&hdw->std_info_enum,cptr->info,
  2314. sizeof(hdw->std_info_enum));
  2315. cptr->info = &hdw->std_info_enum;
  2316. }
  2317. // Initialize control data regarding video standard masks
  2318. valid_std_mask = pvr2_std_get_usable();
  2319. for (idx = 0; idx < 32; idx++) {
  2320. if (!(valid_std_mask & (1 << idx))) continue;
  2321. cnt1 = pvr2_std_id_to_str(
  2322. hdw->std_mask_names[idx],
  2323. sizeof(hdw->std_mask_names[idx])-1,
  2324. 1 << idx);
  2325. hdw->std_mask_names[idx][cnt1] = 0;
  2326. }
  2327. cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
  2328. if (cptr) {
  2329. memcpy(&hdw->std_info_avail,cptr->info,
  2330. sizeof(hdw->std_info_avail));
  2331. cptr->info = &hdw->std_info_avail;
  2332. hdw->std_info_avail.def.type_bitmask.bit_names =
  2333. hdw->std_mask_ptrs;
  2334. hdw->std_info_avail.def.type_bitmask.valid_bits =
  2335. valid_std_mask;
  2336. }
  2337. cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
  2338. if (cptr) {
  2339. memcpy(&hdw->std_info_cur,cptr->info,
  2340. sizeof(hdw->std_info_cur));
  2341. cptr->info = &hdw->std_info_cur;
  2342. hdw->std_info_cur.def.type_bitmask.bit_names =
  2343. hdw->std_mask_ptrs;
  2344. hdw->std_info_avail.def.type_bitmask.valid_bits =
  2345. valid_std_mask;
  2346. }
  2347. hdw->cropcap_stale = !0;
  2348. hdw->eeprom_addr = -1;
  2349. hdw->unit_number = -1;
  2350. hdw->v4l_minor_number_video = -1;
  2351. hdw->v4l_minor_number_vbi = -1;
  2352. hdw->v4l_minor_number_radio = -1;
  2353. hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
  2354. if (!hdw->ctl_write_buffer) goto fail;
  2355. hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
  2356. if (!hdw->ctl_read_buffer) goto fail;
  2357. hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
  2358. if (!hdw->ctl_write_urb) goto fail;
  2359. hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
  2360. if (!hdw->ctl_read_urb) goto fail;
  2361. if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
  2362. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  2363. "Error registering with v4l core, giving up");
  2364. goto fail;
  2365. }
  2366. mutex_lock(&pvr2_unit_mtx); do {
  2367. for (idx = 0; idx < PVR_NUM; idx++) {
  2368. if (unit_pointers[idx]) continue;
  2369. hdw->unit_number = idx;
  2370. unit_pointers[idx] = hdw;
  2371. break;
  2372. }
  2373. } while (0); mutex_unlock(&pvr2_unit_mtx);
  2374. cnt1 = 0;
  2375. cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
  2376. cnt1 += cnt2;
  2377. if (hdw->unit_number >= 0) {
  2378. cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
  2379. ('a' + hdw->unit_number));
  2380. cnt1 += cnt2;
  2381. }
  2382. if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
  2383. hdw->name[cnt1] = 0;
  2384. hdw->workqueue = create_singlethread_workqueue(hdw->name);
  2385. INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
  2386. pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
  2387. hdw->unit_number,hdw->name);
  2388. hdw->tuner_type = -1;
  2389. hdw->flag_ok = !0;
  2390. hdw->usb_intf = intf;
  2391. hdw->usb_dev = usb_dev;
  2392. usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
  2393. ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
  2394. usb_set_interface(hdw->usb_dev,ifnum,0);
  2395. mutex_init(&hdw->ctl_lock_mutex);
  2396. mutex_init(&hdw->big_lock_mutex);
  2397. return hdw;
  2398. fail:
  2399. if (hdw) {
  2400. del_timer_sync(&hdw->quiescent_timer);
  2401. del_timer_sync(&hdw->decoder_stabilization_timer);
  2402. del_timer_sync(&hdw->encoder_run_timer);
  2403. del_timer_sync(&hdw->encoder_wait_timer);
  2404. if (hdw->workqueue) {
  2405. flush_workqueue(hdw->workqueue);
  2406. destroy_workqueue(hdw->workqueue);
  2407. hdw->workqueue = NULL;
  2408. }
  2409. usb_free_urb(hdw->ctl_read_urb);
  2410. usb_free_urb(hdw->ctl_write_urb);
  2411. kfree(hdw->ctl_read_buffer);
  2412. kfree(hdw->ctl_write_buffer);
  2413. kfree(hdw->controls);
  2414. kfree(hdw->mpeg_ctrl_info);
  2415. kfree(hdw->std_defs);
  2416. kfree(hdw->std_enum_names);
  2417. kfree(hdw);
  2418. }
  2419. return NULL;
  2420. }
  2421. /* Remove _all_ associations between this driver and the underlying USB
  2422. layer. */
  2423. static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
  2424. {
  2425. if (hdw->flag_disconnected) return;
  2426. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
  2427. if (hdw->ctl_read_urb) {
  2428. usb_kill_urb(hdw->ctl_read_urb);
  2429. usb_free_urb(hdw->ctl_read_urb);
  2430. hdw->ctl_read_urb = NULL;
  2431. }
  2432. if (hdw->ctl_write_urb) {
  2433. usb_kill_urb(hdw->ctl_write_urb);
  2434. usb_free_urb(hdw->ctl_write_urb);
  2435. hdw->ctl_write_urb = NULL;
  2436. }
  2437. if (hdw->ctl_read_buffer) {
  2438. kfree(hdw->ctl_read_buffer);
  2439. hdw->ctl_read_buffer = NULL;
  2440. }
  2441. if (hdw->ctl_write_buffer) {
  2442. kfree(hdw->ctl_write_buffer);
  2443. hdw->ctl_write_buffer = NULL;
  2444. }
  2445. hdw->flag_disconnected = !0;
  2446. /* If we don't do this, then there will be a dangling struct device
  2447. reference to our disappearing device persisting inside the V4L
  2448. core... */
  2449. v4l2_device_disconnect(&hdw->v4l2_dev);
  2450. hdw->usb_dev = NULL;
  2451. hdw->usb_intf = NULL;
  2452. pvr2_hdw_render_useless(hdw);
  2453. }
  2454. /* Destroy hardware interaction structure */
  2455. void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
  2456. {
  2457. if (!hdw) return;
  2458. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
  2459. if (hdw->workqueue) {
  2460. flush_workqueue(hdw->workqueue);
  2461. destroy_workqueue(hdw->workqueue);
  2462. hdw->workqueue = NULL;
  2463. }
  2464. del_timer_sync(&hdw->quiescent_timer);
  2465. del_timer_sync(&hdw->decoder_stabilization_timer);
  2466. del_timer_sync(&hdw->encoder_run_timer);
  2467. del_timer_sync(&hdw->encoder_wait_timer);
  2468. if (hdw->fw_buffer) {
  2469. kfree(hdw->fw_buffer);
  2470. hdw->fw_buffer = NULL;
  2471. }
  2472. if (hdw->vid_stream) {
  2473. pvr2_stream_destroy(hdw->vid_stream);
  2474. hdw->vid_stream = NULL;
  2475. }
  2476. pvr2_i2c_core_done(hdw);
  2477. v4l2_device_unregister(&hdw->v4l2_dev);
  2478. pvr2_hdw_remove_usb_stuff(hdw);
  2479. mutex_lock(&pvr2_unit_mtx); do {
  2480. if ((hdw->unit_number >= 0) &&
  2481. (hdw->unit_number < PVR_NUM) &&
  2482. (unit_pointers[hdw->unit_number] == hdw)) {
  2483. unit_pointers[hdw->unit_number] = NULL;
  2484. }
  2485. } while (0); mutex_unlock(&pvr2_unit_mtx);
  2486. kfree(hdw->controls);
  2487. kfree(hdw->mpeg_ctrl_info);
  2488. kfree(hdw->std_defs);
  2489. kfree(hdw->std_enum_names);
  2490. kfree(hdw);
  2491. }
  2492. int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
  2493. {
  2494. return (hdw && hdw->flag_ok);
  2495. }
  2496. /* Called when hardware has been unplugged */
  2497. void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
  2498. {
  2499. pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
  2500. LOCK_TAKE(hdw->big_lock);
  2501. LOCK_TAKE(hdw->ctl_lock);
  2502. pvr2_hdw_remove_usb_stuff(hdw);
  2503. LOCK_GIVE(hdw->ctl_lock);
  2504. LOCK_GIVE(hdw->big_lock);
  2505. }
  2506. // Attempt to autoselect an appropriate value for std_enum_cur given
  2507. // whatever is currently in std_mask_cur
  2508. static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
  2509. {
  2510. unsigned int idx;
  2511. for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
  2512. if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
  2513. hdw->std_enum_cur = idx;
  2514. return;
  2515. }
  2516. }
  2517. hdw->std_enum_cur = 0;
  2518. }
  2519. // Calculate correct set of enumerated standards based on currently known
  2520. // set of available standards bits.
  2521. static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
  2522. {
  2523. struct v4l2_standard *newstd;
  2524. unsigned int std_cnt;
  2525. unsigned int idx;
  2526. newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
  2527. if (hdw->std_defs) {
  2528. kfree(hdw->std_defs);
  2529. hdw->std_defs = NULL;
  2530. }
  2531. hdw->std_enum_cnt = 0;
  2532. if (hdw->std_enum_names) {
  2533. kfree(hdw->std_enum_names);
  2534. hdw->std_enum_names = NULL;
  2535. }
  2536. if (!std_cnt) {
  2537. pvr2_trace(
  2538. PVR2_TRACE_ERROR_LEGS,
  2539. "WARNING: Failed to identify any viable standards");
  2540. }
  2541. /* Set up the dynamic control for this standard */
  2542. hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
  2543. if (hdw->std_enum_names) {
  2544. hdw->std_enum_names[0] = "none";
  2545. for (idx = 0; idx < std_cnt; idx++)
  2546. hdw->std_enum_names[idx+1] = newstd[idx].name;
  2547. hdw->std_info_enum.def.type_enum.value_names =
  2548. hdw->std_enum_names;
  2549. hdw->std_info_enum.def.type_enum.count = std_cnt+1;
  2550. } else {
  2551. pvr2_trace(
  2552. PVR2_TRACE_ERROR_LEGS,
  2553. "WARNING: Failed to alloc memory for names");
  2554. hdw->std_info_enum.def.type_enum.value_names = NULL;
  2555. hdw->std_info_enum.def.type_enum.count = 0;
  2556. }
  2557. hdw->std_defs = newstd;
  2558. hdw->std_enum_cnt = std_cnt+1;
  2559. hdw->std_enum_cur = 0;
  2560. hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
  2561. }
  2562. int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
  2563. struct v4l2_standard *std,
  2564. unsigned int idx)
  2565. {
  2566. int ret = -EINVAL;
  2567. if (!idx) return ret;
  2568. LOCK_TAKE(hdw->big_lock); do {
  2569. if (idx >= hdw->std_enum_cnt) break;
  2570. idx--;
  2571. memcpy(std,hdw->std_defs+idx,sizeof(*std));
  2572. ret = 0;
  2573. } while (0); LOCK_GIVE(hdw->big_lock);
  2574. return ret;
  2575. }
  2576. /* Get the number of defined controls */
  2577. unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
  2578. {
  2579. return hdw->control_cnt;
  2580. }
  2581. /* Retrieve a control handle given its index (0..count-1) */
  2582. struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
  2583. unsigned int idx)
  2584. {
  2585. if (idx >= hdw->control_cnt) return NULL;
  2586. return hdw->controls + idx;
  2587. }
  2588. /* Retrieve a control handle given its index (0..count-1) */
  2589. struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
  2590. unsigned int ctl_id)
  2591. {
  2592. struct pvr2_ctrl *cptr;
  2593. unsigned int idx;
  2594. int i;
  2595. /* This could be made a lot more efficient, but for now... */
  2596. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2597. cptr = hdw->controls + idx;
  2598. i = cptr->info->internal_id;
  2599. if (i && (i == ctl_id)) return cptr;
  2600. }
  2601. return NULL;
  2602. }
  2603. /* Given a V4L ID, retrieve the control structure associated with it. */
  2604. struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
  2605. {
  2606. struct pvr2_ctrl *cptr;
  2607. unsigned int idx;
  2608. int i;
  2609. /* This could be made a lot more efficient, but for now... */
  2610. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2611. cptr = hdw->controls + idx;
  2612. i = cptr->info->v4l_id;
  2613. if (i && (i == ctl_id)) return cptr;
  2614. }
  2615. return NULL;
  2616. }
  2617. /* Given a V4L ID for its immediate predecessor, retrieve the control
  2618. structure associated with it. */
  2619. struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
  2620. unsigned int ctl_id)
  2621. {
  2622. struct pvr2_ctrl *cptr,*cp2;
  2623. unsigned int idx;
  2624. int i;
  2625. /* This could be made a lot more efficient, but for now... */
  2626. cp2 = NULL;
  2627. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2628. cptr = hdw->controls + idx;
  2629. i = cptr->info->v4l_id;
  2630. if (!i) continue;
  2631. if (i <= ctl_id) continue;
  2632. if (cp2 && (cp2->info->v4l_id < i)) continue;
  2633. cp2 = cptr;
  2634. }
  2635. return cp2;
  2636. return NULL;
  2637. }
  2638. static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
  2639. {
  2640. switch (tp) {
  2641. case pvr2_ctl_int: return "integer";
  2642. case pvr2_ctl_enum: return "enum";
  2643. case pvr2_ctl_bool: return "boolean";
  2644. case pvr2_ctl_bitmask: return "bitmask";
  2645. }
  2646. return "";
  2647. }
  2648. static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
  2649. const char *name, int val)
  2650. {
  2651. struct v4l2_control ctrl;
  2652. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
  2653. memset(&ctrl, 0, sizeof(ctrl));
  2654. ctrl.id = id;
  2655. ctrl.value = val;
  2656. v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
  2657. }
  2658. #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
  2659. if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
  2660. pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
  2661. }
  2662. /* Execute whatever commands are required to update the state of all the
  2663. sub-devices so that they match our current control values. */
  2664. static void pvr2_subdev_update(struct pvr2_hdw *hdw)
  2665. {
  2666. struct v4l2_subdev *sd;
  2667. unsigned int id;
  2668. pvr2_subdev_update_func fp;
  2669. pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
  2670. if (hdw->tuner_updated || hdw->force_dirty) {
  2671. struct tuner_setup setup;
  2672. pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
  2673. hdw->tuner_type);
  2674. if (((int)(hdw->tuner_type)) >= 0) {
  2675. memset(&setup, 0, sizeof(setup));
  2676. setup.addr = ADDR_UNSET;
  2677. setup.type = hdw->tuner_type;
  2678. setup.mode_mask = T_RADIO | T_ANALOG_TV;
  2679. v4l2_device_call_all(&hdw->v4l2_dev, 0,
  2680. tuner, s_type_addr, &setup);
  2681. }
  2682. }
  2683. if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
  2684. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
  2685. if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
  2686. v4l2_device_call_all(&hdw->v4l2_dev, 0,
  2687. tuner, s_radio);
  2688. } else {
  2689. v4l2_std_id vs;
  2690. vs = hdw->std_mask_cur;
  2691. v4l2_device_call_all(&hdw->v4l2_dev, 0,
  2692. core, s_std, vs);
  2693. pvr2_hdw_cx25840_vbi_hack(hdw);
  2694. }
  2695. hdw->tuner_signal_stale = !0;
  2696. hdw->cropcap_stale = !0;
  2697. }
  2698. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
  2699. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
  2700. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
  2701. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
  2702. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
  2703. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
  2704. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
  2705. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
  2706. PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
  2707. if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
  2708. struct v4l2_tuner vt;
  2709. memset(&vt, 0, sizeof(vt));
  2710. vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
  2711. V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
  2712. vt.audmode = hdw->audiomode_val;
  2713. v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
  2714. }
  2715. if (hdw->freqDirty || hdw->force_dirty) {
  2716. unsigned long fv;
  2717. struct v4l2_frequency freq;
  2718. fv = pvr2_hdw_get_cur_freq(hdw);
  2719. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
  2720. if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
  2721. memset(&freq, 0, sizeof(freq));
  2722. if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
  2723. /* ((fv * 1000) / 62500) */
  2724. freq.frequency = (fv * 2) / 125;
  2725. } else {
  2726. freq.frequency = fv / 62500;
  2727. }
  2728. /* tuner-core currently doesn't seem to care about this, but
  2729. let's set it anyway for completeness. */
  2730. if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
  2731. freq.type = V4L2_TUNER_RADIO;
  2732. } else {
  2733. freq.type = V4L2_TUNER_ANALOG_TV;
  2734. }
  2735. freq.tuner = 0;
  2736. v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
  2737. s_frequency, &freq);
  2738. }
  2739. if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
  2740. struct v4l2_mbus_framefmt fmt;
  2741. memset(&fmt, 0, sizeof(fmt));
  2742. fmt.width = hdw->res_hor_val;
  2743. fmt.height = hdw->res_ver_val;
  2744. fmt.code = V4L2_MBUS_FMT_FIXED;
  2745. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
  2746. fmt.width, fmt.height);
  2747. v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
  2748. }
  2749. if (hdw->srate_dirty || hdw->force_dirty) {
  2750. u32 val;
  2751. pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
  2752. hdw->srate_val);
  2753. switch (hdw->srate_val) {
  2754. default:
  2755. case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
  2756. val = 48000;
  2757. break;
  2758. case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
  2759. val = 44100;
  2760. break;
  2761. case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
  2762. val = 32000;
  2763. break;
  2764. }
  2765. v4l2_device_call_all(&hdw->v4l2_dev, 0,
  2766. audio, s_clock_freq, val);
  2767. }
  2768. /* Unable to set crop parameters; there is apparently no equivalent
  2769. for VIDIOC_S_CROP */
  2770. v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
  2771. id = sd->grp_id;
  2772. if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
  2773. fp = pvr2_module_update_functions[id];
  2774. if (!fp) continue;
  2775. (*fp)(hdw, sd);
  2776. }
  2777. if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
  2778. pvr2_hdw_status_poll(hdw);
  2779. }
  2780. }
  2781. /* Figure out if we need to commit control changes. If so, mark internal
  2782. state flags to indicate this fact and return true. Otherwise do nothing
  2783. else and return false. */
  2784. static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
  2785. {
  2786. unsigned int idx;
  2787. struct pvr2_ctrl *cptr;
  2788. int value;
  2789. int commit_flag = hdw->force_dirty;
  2790. char buf[100];
  2791. unsigned int bcnt,ccnt;
  2792. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2793. cptr = hdw->controls + idx;
  2794. if (!cptr->info->is_dirty) continue;
  2795. if (!cptr->info->is_dirty(cptr)) continue;
  2796. commit_flag = !0;
  2797. if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
  2798. bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
  2799. cptr->info->name);
  2800. value = 0;
  2801. cptr->info->get_value(cptr,&value);
  2802. pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
  2803. buf+bcnt,
  2804. sizeof(buf)-bcnt,&ccnt);
  2805. bcnt += ccnt;
  2806. bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
  2807. get_ctrl_typename(cptr->info->type));
  2808. pvr2_trace(PVR2_TRACE_CTL,
  2809. "/*--TRACE_COMMIT--*/ %.*s",
  2810. bcnt,buf);
  2811. }
  2812. if (!commit_flag) {
  2813. /* Nothing has changed */
  2814. return 0;
  2815. }
  2816. hdw->state_pipeline_config = 0;
  2817. trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
  2818. pvr2_hdw_state_sched(hdw);
  2819. return !0;
  2820. }
  2821. /* Perform all operations needed to commit all control changes. This must
  2822. be performed in synchronization with the pipeline state and is thus
  2823. expected to be called as part of the driver's worker thread. Return
  2824. true if commit successful, otherwise return false to indicate that
  2825. commit isn't possible at this time. */
  2826. static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
  2827. {
  2828. unsigned int idx;
  2829. struct pvr2_ctrl *cptr;
  2830. int disruptive_change;
  2831. if (hdw->input_dirty && hdw->state_pathway_ok &&
  2832. (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
  2833. PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
  2834. hdw->pathway_state)) {
  2835. /* Change of mode being asked for... */
  2836. hdw->state_pathway_ok = 0;
  2837. trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
  2838. }
  2839. if (!hdw->state_pathway_ok) {
  2840. /* Can't commit anything until pathway is ok. */
  2841. return 0;
  2842. }
  2843. /* Handle some required side effects when the video standard is
  2844. changed.... */
  2845. if (hdw->std_dirty) {
  2846. int nvres;
  2847. int gop_size;
  2848. if (hdw->std_mask_cur & V4L2_STD_525_60) {
  2849. nvres = 480;
  2850. gop_size = 15;
  2851. } else {
  2852. nvres = 576;
  2853. gop_size = 12;
  2854. }
  2855. /* Rewrite the vertical resolution to be appropriate to the
  2856. video standard that has been selected. */
  2857. if (nvres != hdw->res_ver_val) {
  2858. hdw->res_ver_val = nvres;
  2859. hdw->res_ver_dirty = !0;
  2860. }
  2861. /* Rewrite the GOP size to be appropriate to the video
  2862. standard that has been selected. */
  2863. if (gop_size != hdw->enc_ctl_state.video_gop_size) {
  2864. struct v4l2_ext_controls cs;
  2865. struct v4l2_ext_control c1;
  2866. memset(&cs, 0, sizeof(cs));
  2867. memset(&c1, 0, sizeof(c1));
  2868. cs.controls = &c1;
  2869. cs.count = 1;
  2870. c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
  2871. c1.value = gop_size;
  2872. cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
  2873. VIDIOC_S_EXT_CTRLS);
  2874. }
  2875. }
  2876. /* The broadcast decoder can only scale down, so if
  2877. * res_*_dirty && crop window < output format ==> enlarge crop.
  2878. *
  2879. * The mpeg encoder receives fields of res_hor_val dots and
  2880. * res_ver_val halflines. Limits: hor<=720, ver<=576.
  2881. */
  2882. if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
  2883. hdw->cropw_val = hdw->res_hor_val;
  2884. hdw->cropw_dirty = !0;
  2885. } else if (hdw->cropw_dirty) {
  2886. hdw->res_hor_dirty = !0; /* must rescale */
  2887. hdw->res_hor_val = min(720, hdw->cropw_val);
  2888. }
  2889. if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
  2890. hdw->croph_val = hdw->res_ver_val;
  2891. hdw->croph_dirty = !0;
  2892. } else if (hdw->croph_dirty) {
  2893. int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
  2894. hdw->res_ver_dirty = !0;
  2895. hdw->res_ver_val = min(nvres, hdw->croph_val);
  2896. }
  2897. /* If any of the below has changed, then we can't do the update
  2898. while the pipeline is running. Pipeline must be paused first
  2899. and decoder -> encoder connection be made quiescent before we
  2900. can proceed. */
  2901. disruptive_change =
  2902. (hdw->std_dirty ||
  2903. hdw->enc_unsafe_stale ||
  2904. hdw->srate_dirty ||
  2905. hdw->res_ver_dirty ||
  2906. hdw->res_hor_dirty ||
  2907. hdw->cropw_dirty ||
  2908. hdw->croph_dirty ||
  2909. hdw->input_dirty ||
  2910. (hdw->active_stream_type != hdw->desired_stream_type));
  2911. if (disruptive_change && !hdw->state_pipeline_idle) {
  2912. /* Pipeline is not idle; we can't proceed. Arrange to
  2913. cause pipeline to stop so that we can try this again
  2914. later.... */
  2915. hdw->state_pipeline_pause = !0;
  2916. return 0;
  2917. }
  2918. if (hdw->srate_dirty) {
  2919. /* Write new sample rate into control structure since
  2920. * the master copy is stale. We must track srate
  2921. * separate from the mpeg control structure because
  2922. * other logic also uses this value. */
  2923. struct v4l2_ext_controls cs;
  2924. struct v4l2_ext_control c1;
  2925. memset(&cs,0,sizeof(cs));
  2926. memset(&c1,0,sizeof(c1));
  2927. cs.controls = &c1;
  2928. cs.count = 1;
  2929. c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
  2930. c1.value = hdw->srate_val;
  2931. cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
  2932. }
  2933. if (hdw->active_stream_type != hdw->desired_stream_type) {
  2934. /* Handle any side effects of stream config here */
  2935. hdw->active_stream_type = hdw->desired_stream_type;
  2936. }
  2937. if (hdw->hdw_desc->signal_routing_scheme ==
  2938. PVR2_ROUTING_SCHEME_GOTVIEW) {
  2939. u32 b;
  2940. /* Handle GOTVIEW audio switching */
  2941. pvr2_hdw_gpio_get_out(hdw,&b);
  2942. if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
  2943. /* Set GPIO 11 */
  2944. pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
  2945. } else {
  2946. /* Clear GPIO 11 */
  2947. pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
  2948. }
  2949. }
  2950. /* Check and update state for all sub-devices. */
  2951. pvr2_subdev_update(hdw);
  2952. hdw->tuner_updated = 0;
  2953. hdw->force_dirty = 0;
  2954. for (idx = 0; idx < hdw->control_cnt; idx++) {
  2955. cptr = hdw->controls + idx;
  2956. if (!cptr->info->clear_dirty) continue;
  2957. cptr->info->clear_dirty(cptr);
  2958. }
  2959. if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
  2960. hdw->state_encoder_run) {
  2961. /* If encoder isn't running or it can't be touched, then
  2962. this will get worked out later when we start the
  2963. encoder. */
  2964. if (pvr2_encoder_adjust(hdw) < 0) return !0;
  2965. }
  2966. hdw->state_pipeline_config = !0;
  2967. /* Hardware state may have changed in a way to cause the cropping
  2968. capabilities to have changed. So mark it stale, which will
  2969. cause a later re-fetch. */
  2970. trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
  2971. return !0;
  2972. }
  2973. int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
  2974. {
  2975. int fl;
  2976. LOCK_TAKE(hdw->big_lock);
  2977. fl = pvr2_hdw_commit_setup(hdw);
  2978. LOCK_GIVE(hdw->big_lock);
  2979. if (!fl) return 0;
  2980. return pvr2_hdw_wait(hdw,0);
  2981. }
  2982. static void pvr2_hdw_worker_poll(struct work_struct *work)
  2983. {
  2984. int fl = 0;
  2985. struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
  2986. LOCK_TAKE(hdw->big_lock); do {
  2987. fl = pvr2_hdw_state_eval(hdw);
  2988. } while (0); LOCK_GIVE(hdw->big_lock);
  2989. if (fl && hdw->state_func) {
  2990. hdw->state_func(hdw->state_data);
  2991. }
  2992. }
  2993. static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
  2994. {
  2995. return wait_event_interruptible(
  2996. hdw->state_wait_data,
  2997. (hdw->state_stale == 0) &&
  2998. (!state || (hdw->master_state != state)));
  2999. }
  3000. /* Return name for this driver instance */
  3001. const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
  3002. {
  3003. return hdw->name;
  3004. }
  3005. const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
  3006. {
  3007. return hdw->hdw_desc->description;
  3008. }
  3009. const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
  3010. {
  3011. return hdw->hdw_desc->shortname;
  3012. }
  3013. int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
  3014. {
  3015. int result;
  3016. LOCK_TAKE(hdw->ctl_lock); do {
  3017. hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
  3018. result = pvr2_send_request(hdw,
  3019. hdw->cmd_buffer,1,
  3020. hdw->cmd_buffer,1);
  3021. if (result < 0) break;
  3022. result = (hdw->cmd_buffer[0] != 0);
  3023. } while(0); LOCK_GIVE(hdw->ctl_lock);
  3024. return result;
  3025. }
  3026. /* Execute poll of tuner status */
  3027. void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
  3028. {
  3029. LOCK_TAKE(hdw->big_lock); do {
  3030. pvr2_hdw_status_poll(hdw);
  3031. } while (0); LOCK_GIVE(hdw->big_lock);
  3032. }
  3033. static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
  3034. {
  3035. if (!hdw->cropcap_stale) {
  3036. return 0;
  3037. }
  3038. pvr2_hdw_status_poll(hdw);
  3039. if (hdw->cropcap_stale) {
  3040. return -EIO;
  3041. }
  3042. return 0;
  3043. }
  3044. /* Return information about cropping capabilities */
  3045. int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
  3046. {
  3047. int stat = 0;
  3048. LOCK_TAKE(hdw->big_lock);
  3049. stat = pvr2_hdw_check_cropcap(hdw);
  3050. if (!stat) {
  3051. memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
  3052. }
  3053. LOCK_GIVE(hdw->big_lock);
  3054. return stat;
  3055. }
  3056. /* Return information about the tuner */
  3057. int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
  3058. {
  3059. LOCK_TAKE(hdw->big_lock); do {
  3060. if (hdw->tuner_signal_stale) {
  3061. pvr2_hdw_status_poll(hdw);
  3062. }
  3063. memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
  3064. } while (0); LOCK_GIVE(hdw->big_lock);
  3065. return 0;
  3066. }
  3067. /* Get handle to video output stream */
  3068. struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
  3069. {
  3070. return hp->vid_stream;
  3071. }
  3072. void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
  3073. {
  3074. int nr = pvr2_hdw_get_unit_number(hdw);
  3075. LOCK_TAKE(hdw->big_lock); do {
  3076. printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
  3077. v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
  3078. pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
  3079. cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
  3080. pvr2_hdw_state_log_state(hdw);
  3081. printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
  3082. } while (0); LOCK_GIVE(hdw->big_lock);
  3083. }
  3084. /* Grab EEPROM contents, needed for direct method. */
  3085. #define EEPROM_SIZE 8192
  3086. #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
  3087. static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
  3088. {
  3089. struct i2c_msg msg[2];
  3090. u8 *eeprom;
  3091. u8 iadd[2];
  3092. u8 addr;
  3093. u16 eepromSize;
  3094. unsigned int offs;
  3095. int ret;
  3096. int mode16 = 0;
  3097. unsigned pcnt,tcnt;
  3098. eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
  3099. if (!eeprom) {
  3100. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3101. "Failed to allocate memory"
  3102. " required to read eeprom");
  3103. return NULL;
  3104. }
  3105. trace_eeprom("Value for eeprom addr from controller was 0x%x",
  3106. hdw->eeprom_addr);
  3107. addr = hdw->eeprom_addr;
  3108. /* Seems that if the high bit is set, then the *real* eeprom
  3109. address is shifted right now bit position (noticed this in
  3110. newer PVR USB2 hardware) */
  3111. if (addr & 0x80) addr >>= 1;
  3112. /* FX2 documentation states that a 16bit-addressed eeprom is
  3113. expected if the I2C address is an odd number (yeah, this is
  3114. strange but it's what they do) */
  3115. mode16 = (addr & 1);
  3116. eepromSize = (mode16 ? EEPROM_SIZE : 256);
  3117. trace_eeprom("Examining %d byte eeprom at location 0x%x"
  3118. " using %d bit addressing",eepromSize,addr,
  3119. mode16 ? 16 : 8);
  3120. msg[0].addr = addr;
  3121. msg[0].flags = 0;
  3122. msg[0].len = mode16 ? 2 : 1;
  3123. msg[0].buf = iadd;
  3124. msg[1].addr = addr;
  3125. msg[1].flags = I2C_M_RD;
  3126. /* We have to do the actual eeprom data fetch ourselves, because
  3127. (1) we're only fetching part of the eeprom, and (2) if we were
  3128. getting the whole thing our I2C driver can't grab it in one
  3129. pass - which is what tveeprom is otherwise going to attempt */
  3130. memset(eeprom,0,EEPROM_SIZE);
  3131. for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
  3132. pcnt = 16;
  3133. if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
  3134. offs = tcnt + (eepromSize - EEPROM_SIZE);
  3135. if (mode16) {
  3136. iadd[0] = offs >> 8;
  3137. iadd[1] = offs;
  3138. } else {
  3139. iadd[0] = offs;
  3140. }
  3141. msg[1].len = pcnt;
  3142. msg[1].buf = eeprom+tcnt;
  3143. if ((ret = i2c_transfer(&hdw->i2c_adap,
  3144. msg,ARRAY_SIZE(msg))) != 2) {
  3145. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3146. "eeprom fetch set offs err=%d",ret);
  3147. kfree(eeprom);
  3148. return NULL;
  3149. }
  3150. }
  3151. return eeprom;
  3152. }
  3153. void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
  3154. int mode,
  3155. int enable_flag)
  3156. {
  3157. int ret;
  3158. u16 address;
  3159. unsigned int pipe;
  3160. LOCK_TAKE(hdw->big_lock); do {
  3161. if ((hdw->fw_buffer == NULL) == !enable_flag) break;
  3162. if (!enable_flag) {
  3163. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3164. "Cleaning up after CPU firmware fetch");
  3165. kfree(hdw->fw_buffer);
  3166. hdw->fw_buffer = NULL;
  3167. hdw->fw_size = 0;
  3168. if (hdw->fw_cpu_flag) {
  3169. /* Now release the CPU. It will disconnect
  3170. and reconnect later. */
  3171. pvr2_hdw_cpureset_assert(hdw,0);
  3172. }
  3173. break;
  3174. }
  3175. hdw->fw_cpu_flag = (mode != 2);
  3176. if (hdw->fw_cpu_flag) {
  3177. hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
  3178. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3179. "Preparing to suck out CPU firmware"
  3180. " (size=%u)", hdw->fw_size);
  3181. hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
  3182. if (!hdw->fw_buffer) {
  3183. hdw->fw_size = 0;
  3184. break;
  3185. }
  3186. /* We have to hold the CPU during firmware upload. */
  3187. pvr2_hdw_cpureset_assert(hdw,1);
  3188. /* download the firmware from address 0000-1fff in 2048
  3189. (=0x800) bytes chunk. */
  3190. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3191. "Grabbing CPU firmware");
  3192. pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
  3193. for(address = 0; address < hdw->fw_size;
  3194. address += 0x800) {
  3195. ret = usb_control_msg(hdw->usb_dev,pipe,
  3196. 0xa0,0xc0,
  3197. address,0,
  3198. hdw->fw_buffer+address,
  3199. 0x800,HZ);
  3200. if (ret < 0) break;
  3201. }
  3202. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3203. "Done grabbing CPU firmware");
  3204. } else {
  3205. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3206. "Sucking down EEPROM contents");
  3207. hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
  3208. if (!hdw->fw_buffer) {
  3209. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3210. "EEPROM content suck failed.");
  3211. break;
  3212. }
  3213. hdw->fw_size = EEPROM_SIZE;
  3214. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3215. "Done sucking down EEPROM contents");
  3216. }
  3217. } while (0); LOCK_GIVE(hdw->big_lock);
  3218. }
  3219. /* Return true if we're in a mode for retrieval CPU firmware */
  3220. int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
  3221. {
  3222. return hdw->fw_buffer != NULL;
  3223. }
  3224. int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
  3225. char *buf,unsigned int cnt)
  3226. {
  3227. int ret = -EINVAL;
  3228. LOCK_TAKE(hdw->big_lock); do {
  3229. if (!buf) break;
  3230. if (!cnt) break;
  3231. if (!hdw->fw_buffer) {
  3232. ret = -EIO;
  3233. break;
  3234. }
  3235. if (offs >= hdw->fw_size) {
  3236. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3237. "Read firmware data offs=%d EOF",
  3238. offs);
  3239. ret = 0;
  3240. break;
  3241. }
  3242. if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
  3243. memcpy(buf,hdw->fw_buffer+offs,cnt);
  3244. pvr2_trace(PVR2_TRACE_FIRMWARE,
  3245. "Read firmware data offs=%d cnt=%d",
  3246. offs,cnt);
  3247. ret = cnt;
  3248. } while (0); LOCK_GIVE(hdw->big_lock);
  3249. return ret;
  3250. }
  3251. int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
  3252. enum pvr2_v4l_type index)
  3253. {
  3254. switch (index) {
  3255. case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
  3256. case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
  3257. case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
  3258. default: return -1;
  3259. }
  3260. }
  3261. /* Store a v4l minor device number */
  3262. void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
  3263. enum pvr2_v4l_type index,int v)
  3264. {
  3265. switch (index) {
  3266. case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
  3267. case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
  3268. case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
  3269. default: break;
  3270. }
  3271. }
  3272. static void pvr2_ctl_write_complete(struct urb *urb)
  3273. {
  3274. struct pvr2_hdw *hdw = urb->context;
  3275. hdw->ctl_write_pend_flag = 0;
  3276. if (hdw->ctl_read_pend_flag) return;
  3277. complete(&hdw->ctl_done);
  3278. }
  3279. static void pvr2_ctl_read_complete(struct urb *urb)
  3280. {
  3281. struct pvr2_hdw *hdw = urb->context;
  3282. hdw->ctl_read_pend_flag = 0;
  3283. if (hdw->ctl_write_pend_flag) return;
  3284. complete(&hdw->ctl_done);
  3285. }
  3286. static void pvr2_ctl_timeout(unsigned long data)
  3287. {
  3288. struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
  3289. if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
  3290. hdw->ctl_timeout_flag = !0;
  3291. if (hdw->ctl_write_pend_flag)
  3292. usb_unlink_urb(hdw->ctl_write_urb);
  3293. if (hdw->ctl_read_pend_flag)
  3294. usb_unlink_urb(hdw->ctl_read_urb);
  3295. }
  3296. }
  3297. /* Issue a command and get a response from the device. This extended
  3298. version includes a probe flag (which if set means that device errors
  3299. should not be logged or treated as fatal) and a timeout in jiffies.
  3300. This can be used to non-lethally probe the health of endpoint 1. */
  3301. static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
  3302. unsigned int timeout,int probe_fl,
  3303. void *write_data,unsigned int write_len,
  3304. void *read_data,unsigned int read_len)
  3305. {
  3306. unsigned int idx;
  3307. int status = 0;
  3308. struct timer_list timer;
  3309. if (!hdw->ctl_lock_held) {
  3310. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3311. "Attempted to execute control transfer"
  3312. " without lock!!");
  3313. return -EDEADLK;
  3314. }
  3315. if (!hdw->flag_ok && !probe_fl) {
  3316. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3317. "Attempted to execute control transfer"
  3318. " when device not ok");
  3319. return -EIO;
  3320. }
  3321. if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
  3322. if (!probe_fl) {
  3323. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3324. "Attempted to execute control transfer"
  3325. " when USB is disconnected");
  3326. }
  3327. return -ENOTTY;
  3328. }
  3329. /* Ensure that we have sane parameters */
  3330. if (!write_data) write_len = 0;
  3331. if (!read_data) read_len = 0;
  3332. if (write_len > PVR2_CTL_BUFFSIZE) {
  3333. pvr2_trace(
  3334. PVR2_TRACE_ERROR_LEGS,
  3335. "Attempted to execute %d byte"
  3336. " control-write transfer (limit=%d)",
  3337. write_len,PVR2_CTL_BUFFSIZE);
  3338. return -EINVAL;
  3339. }
  3340. if (read_len > PVR2_CTL_BUFFSIZE) {
  3341. pvr2_trace(
  3342. PVR2_TRACE_ERROR_LEGS,
  3343. "Attempted to execute %d byte"
  3344. " control-read transfer (limit=%d)",
  3345. write_len,PVR2_CTL_BUFFSIZE);
  3346. return -EINVAL;
  3347. }
  3348. if ((!write_len) && (!read_len)) {
  3349. pvr2_trace(
  3350. PVR2_TRACE_ERROR_LEGS,
  3351. "Attempted to execute null control transfer?");
  3352. return -EINVAL;
  3353. }
  3354. hdw->cmd_debug_state = 1;
  3355. if (write_len) {
  3356. hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
  3357. } else {
  3358. hdw->cmd_debug_code = 0;
  3359. }
  3360. hdw->cmd_debug_write_len = write_len;
  3361. hdw->cmd_debug_read_len = read_len;
  3362. /* Initialize common stuff */
  3363. init_completion(&hdw->ctl_done);
  3364. hdw->ctl_timeout_flag = 0;
  3365. hdw->ctl_write_pend_flag = 0;
  3366. hdw->ctl_read_pend_flag = 0;
  3367. init_timer(&timer);
  3368. timer.expires = jiffies + timeout;
  3369. timer.data = (unsigned long)hdw;
  3370. timer.function = pvr2_ctl_timeout;
  3371. if (write_len) {
  3372. hdw->cmd_debug_state = 2;
  3373. /* Transfer write data to internal buffer */
  3374. for (idx = 0; idx < write_len; idx++) {
  3375. hdw->ctl_write_buffer[idx] =
  3376. ((unsigned char *)write_data)[idx];
  3377. }
  3378. /* Initiate a write request */
  3379. usb_fill_bulk_urb(hdw->ctl_write_urb,
  3380. hdw->usb_dev,
  3381. usb_sndbulkpipe(hdw->usb_dev,
  3382. PVR2_CTL_WRITE_ENDPOINT),
  3383. hdw->ctl_write_buffer,
  3384. write_len,
  3385. pvr2_ctl_write_complete,
  3386. hdw);
  3387. hdw->ctl_write_urb->actual_length = 0;
  3388. hdw->ctl_write_pend_flag = !0;
  3389. status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
  3390. if (status < 0) {
  3391. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3392. "Failed to submit write-control"
  3393. " URB status=%d",status);
  3394. hdw->ctl_write_pend_flag = 0;
  3395. goto done;
  3396. }
  3397. }
  3398. if (read_len) {
  3399. hdw->cmd_debug_state = 3;
  3400. memset(hdw->ctl_read_buffer,0x43,read_len);
  3401. /* Initiate a read request */
  3402. usb_fill_bulk_urb(hdw->ctl_read_urb,
  3403. hdw->usb_dev,
  3404. usb_rcvbulkpipe(hdw->usb_dev,
  3405. PVR2_CTL_READ_ENDPOINT),
  3406. hdw->ctl_read_buffer,
  3407. read_len,
  3408. pvr2_ctl_read_complete,
  3409. hdw);
  3410. hdw->ctl_read_urb->actual_length = 0;
  3411. hdw->ctl_read_pend_flag = !0;
  3412. status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
  3413. if (status < 0) {
  3414. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3415. "Failed to submit read-control"
  3416. " URB status=%d",status);
  3417. hdw->ctl_read_pend_flag = 0;
  3418. goto done;
  3419. }
  3420. }
  3421. /* Start timer */
  3422. add_timer(&timer);
  3423. /* Now wait for all I/O to complete */
  3424. hdw->cmd_debug_state = 4;
  3425. while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
  3426. wait_for_completion(&hdw->ctl_done);
  3427. }
  3428. hdw->cmd_debug_state = 5;
  3429. /* Stop timer */
  3430. del_timer_sync(&timer);
  3431. hdw->cmd_debug_state = 6;
  3432. status = 0;
  3433. if (hdw->ctl_timeout_flag) {
  3434. status = -ETIMEDOUT;
  3435. if (!probe_fl) {
  3436. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3437. "Timed out control-write");
  3438. }
  3439. goto done;
  3440. }
  3441. if (write_len) {
  3442. /* Validate results of write request */
  3443. if ((hdw->ctl_write_urb->status != 0) &&
  3444. (hdw->ctl_write_urb->status != -ENOENT) &&
  3445. (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
  3446. (hdw->ctl_write_urb->status != -ECONNRESET)) {
  3447. /* USB subsystem is reporting some kind of failure
  3448. on the write */
  3449. status = hdw->ctl_write_urb->status;
  3450. if (!probe_fl) {
  3451. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3452. "control-write URB failure,"
  3453. " status=%d",
  3454. status);
  3455. }
  3456. goto done;
  3457. }
  3458. if (hdw->ctl_write_urb->actual_length < write_len) {
  3459. /* Failed to write enough data */
  3460. status = -EIO;
  3461. if (!probe_fl) {
  3462. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3463. "control-write URB short,"
  3464. " expected=%d got=%d",
  3465. write_len,
  3466. hdw->ctl_write_urb->actual_length);
  3467. }
  3468. goto done;
  3469. }
  3470. }
  3471. if (read_len) {
  3472. /* Validate results of read request */
  3473. if ((hdw->ctl_read_urb->status != 0) &&
  3474. (hdw->ctl_read_urb->status != -ENOENT) &&
  3475. (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
  3476. (hdw->ctl_read_urb->status != -ECONNRESET)) {
  3477. /* USB subsystem is reporting some kind of failure
  3478. on the read */
  3479. status = hdw->ctl_read_urb->status;
  3480. if (!probe_fl) {
  3481. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3482. "control-read URB failure,"
  3483. " status=%d",
  3484. status);
  3485. }
  3486. goto done;
  3487. }
  3488. if (hdw->ctl_read_urb->actual_length < read_len) {
  3489. /* Failed to read enough data */
  3490. status = -EIO;
  3491. if (!probe_fl) {
  3492. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3493. "control-read URB short,"
  3494. " expected=%d got=%d",
  3495. read_len,
  3496. hdw->ctl_read_urb->actual_length);
  3497. }
  3498. goto done;
  3499. }
  3500. /* Transfer retrieved data out from internal buffer */
  3501. for (idx = 0; idx < read_len; idx++) {
  3502. ((unsigned char *)read_data)[idx] =
  3503. hdw->ctl_read_buffer[idx];
  3504. }
  3505. }
  3506. done:
  3507. hdw->cmd_debug_state = 0;
  3508. if ((status < 0) && (!probe_fl)) {
  3509. pvr2_hdw_render_useless(hdw);
  3510. }
  3511. return status;
  3512. }
  3513. int pvr2_send_request(struct pvr2_hdw *hdw,
  3514. void *write_data,unsigned int write_len,
  3515. void *read_data,unsigned int read_len)
  3516. {
  3517. return pvr2_send_request_ex(hdw,HZ*4,0,
  3518. write_data,write_len,
  3519. read_data,read_len);
  3520. }
  3521. static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
  3522. {
  3523. int ret;
  3524. unsigned int cnt = 1;
  3525. unsigned int args = 0;
  3526. LOCK_TAKE(hdw->ctl_lock);
  3527. hdw->cmd_buffer[0] = cmdcode & 0xffu;
  3528. args = (cmdcode >> 8) & 0xffu;
  3529. args = (args > 2) ? 2 : args;
  3530. if (args) {
  3531. cnt += args;
  3532. hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
  3533. if (args > 1) {
  3534. hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
  3535. }
  3536. }
  3537. if (pvrusb2_debug & PVR2_TRACE_INIT) {
  3538. unsigned int idx;
  3539. unsigned int ccnt,bcnt;
  3540. char tbuf[50];
  3541. cmdcode &= 0xffu;
  3542. bcnt = 0;
  3543. ccnt = scnprintf(tbuf+bcnt,
  3544. sizeof(tbuf)-bcnt,
  3545. "Sending FX2 command 0x%x",cmdcode);
  3546. bcnt += ccnt;
  3547. for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
  3548. if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
  3549. ccnt = scnprintf(tbuf+bcnt,
  3550. sizeof(tbuf)-bcnt,
  3551. " \"%s\"",
  3552. pvr2_fx2cmd_desc[idx].desc);
  3553. bcnt += ccnt;
  3554. break;
  3555. }
  3556. }
  3557. if (args) {
  3558. ccnt = scnprintf(tbuf+bcnt,
  3559. sizeof(tbuf)-bcnt,
  3560. " (%u",hdw->cmd_buffer[1]);
  3561. bcnt += ccnt;
  3562. if (args > 1) {
  3563. ccnt = scnprintf(tbuf+bcnt,
  3564. sizeof(tbuf)-bcnt,
  3565. ",%u",hdw->cmd_buffer[2]);
  3566. bcnt += ccnt;
  3567. }
  3568. ccnt = scnprintf(tbuf+bcnt,
  3569. sizeof(tbuf)-bcnt,
  3570. ")");
  3571. bcnt += ccnt;
  3572. }
  3573. pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
  3574. }
  3575. ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
  3576. LOCK_GIVE(hdw->ctl_lock);
  3577. return ret;
  3578. }
  3579. int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
  3580. {
  3581. int ret;
  3582. LOCK_TAKE(hdw->ctl_lock);
  3583. hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
  3584. PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
  3585. hdw->cmd_buffer[5] = 0;
  3586. hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
  3587. hdw->cmd_buffer[7] = reg & 0xff;
  3588. ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
  3589. LOCK_GIVE(hdw->ctl_lock);
  3590. return ret;
  3591. }
  3592. static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
  3593. {
  3594. int ret = 0;
  3595. LOCK_TAKE(hdw->ctl_lock);
  3596. hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
  3597. hdw->cmd_buffer[1] = 0;
  3598. hdw->cmd_buffer[2] = 0;
  3599. hdw->cmd_buffer[3] = 0;
  3600. hdw->cmd_buffer[4] = 0;
  3601. hdw->cmd_buffer[5] = 0;
  3602. hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
  3603. hdw->cmd_buffer[7] = reg & 0xff;
  3604. ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
  3605. *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
  3606. LOCK_GIVE(hdw->ctl_lock);
  3607. return ret;
  3608. }
  3609. void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
  3610. {
  3611. if (!hdw->flag_ok) return;
  3612. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3613. "Device being rendered inoperable");
  3614. if (hdw->vid_stream) {
  3615. pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
  3616. }
  3617. hdw->flag_ok = 0;
  3618. trace_stbit("flag_ok",hdw->flag_ok);
  3619. pvr2_hdw_state_sched(hdw);
  3620. }
  3621. void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
  3622. {
  3623. int ret;
  3624. pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
  3625. ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
  3626. if (ret == 0) {
  3627. ret = usb_reset_device(hdw->usb_dev);
  3628. usb_unlock_device(hdw->usb_dev);
  3629. } else {
  3630. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3631. "Failed to lock USB device ret=%d",ret);
  3632. }
  3633. if (init_pause_msec) {
  3634. pvr2_trace(PVR2_TRACE_INFO,
  3635. "Waiting %u msec for hardware to settle",
  3636. init_pause_msec);
  3637. msleep(init_pause_msec);
  3638. }
  3639. }
  3640. void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
  3641. {
  3642. char *da;
  3643. unsigned int pipe;
  3644. int ret;
  3645. if (!hdw->usb_dev) return;
  3646. da = kmalloc(16, GFP_KERNEL);
  3647. if (da == NULL) {
  3648. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3649. "Unable to allocate memory to control CPU reset");
  3650. return;
  3651. }
  3652. pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
  3653. da[0] = val ? 0x01 : 0x00;
  3654. /* Write the CPUCS register on the 8051. The lsb of the register
  3655. is the reset bit; a 1 asserts reset while a 0 clears it. */
  3656. pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
  3657. ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
  3658. if (ret < 0) {
  3659. pvr2_trace(PVR2_TRACE_ERROR_LEGS,
  3660. "cpureset_assert(%d) error=%d",val,ret);
  3661. pvr2_hdw_render_useless(hdw);
  3662. }
  3663. kfree(da);
  3664. }
  3665. int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
  3666. {
  3667. return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
  3668. }
  3669. int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
  3670. {
  3671. return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
  3672. }
  3673. int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
  3674. {
  3675. return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
  3676. }
  3677. int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
  3678. {
  3679. pvr2_trace(PVR2_TRACE_INIT,
  3680. "Requesting decoder reset");
  3681. if (hdw->decoder_client_id) {
  3682. v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
  3683. core, reset, 0);
  3684. pvr2_hdw_cx25840_vbi_hack(hdw);
  3685. return 0;
  3686. }
  3687. pvr2_trace(PVR2_TRACE_INIT,
  3688. "Unable to reset decoder: nothing attached");
  3689. return -ENOTTY;
  3690. }
  3691. static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
  3692. {
  3693. hdw->flag_ok = !0;
  3694. return pvr2_issue_simple_cmd(hdw,
  3695. FX2CMD_HCW_DEMOD_RESETIN |
  3696. (1 << 8) |
  3697. ((onoff ? 1 : 0) << 16));
  3698. }
  3699. static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
  3700. {
  3701. hdw->flag_ok = !0;
  3702. return pvr2_issue_simple_cmd(hdw,(onoff ?
  3703. FX2CMD_ONAIR_DTV_POWER_ON :
  3704. FX2CMD_ONAIR_DTV_POWER_OFF));
  3705. }
  3706. static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
  3707. int onoff)
  3708. {
  3709. return pvr2_issue_simple_cmd(hdw,(onoff ?
  3710. FX2CMD_ONAIR_DTV_STREAMING_ON :
  3711. FX2CMD_ONAIR_DTV_STREAMING_OFF));
  3712. }
  3713. static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
  3714. {
  3715. int cmode;
  3716. /* Compare digital/analog desired setting with current setting. If
  3717. they don't match, fix it... */
  3718. cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
  3719. if (cmode == hdw->pathway_state) {
  3720. /* They match; nothing to do */
  3721. return;
  3722. }
  3723. switch (hdw->hdw_desc->digital_control_scheme) {
  3724. case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
  3725. pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
  3726. if (cmode == PVR2_PATHWAY_ANALOG) {
  3727. /* If moving to analog mode, also force the decoder
  3728. to reset. If no decoder is attached, then it's
  3729. ok to ignore this because if/when the decoder
  3730. attaches, it will reset itself at that time. */
  3731. pvr2_hdw_cmd_decoder_reset(hdw);
  3732. }
  3733. break;
  3734. case PVR2_DIGITAL_SCHEME_ONAIR:
  3735. /* Supposedly we should always have the power on whether in
  3736. digital or analog mode. But for now do what appears to
  3737. work... */
  3738. pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
  3739. break;
  3740. default: break;
  3741. }
  3742. pvr2_hdw_untrip_unlocked(hdw);
  3743. hdw->pathway_state = cmode;
  3744. }
  3745. static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
  3746. {
  3747. /* change some GPIO data
  3748. *
  3749. * note: bit d7 of dir appears to control the LED,
  3750. * so we shut it off here.
  3751. *
  3752. */
  3753. if (onoff) {
  3754. pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
  3755. } else {
  3756. pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
  3757. }
  3758. pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
  3759. }
  3760. typedef void (*led_method_func)(struct pvr2_hdw *,int);
  3761. static led_method_func led_methods[] = {
  3762. [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
  3763. };
  3764. /* Toggle LED */
  3765. static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
  3766. {
  3767. unsigned int scheme_id;
  3768. led_method_func fp;
  3769. if ((!onoff) == (!hdw->led_on)) return;
  3770. hdw->led_on = onoff != 0;
  3771. scheme_id = hdw->hdw_desc->led_scheme;
  3772. if (scheme_id < ARRAY_SIZE(led_methods)) {
  3773. fp = led_methods[scheme_id];
  3774. } else {
  3775. fp = NULL;
  3776. }
  3777. if (fp) (*fp)(hdw,onoff);
  3778. }
  3779. /* Stop / start video stream transport */
  3780. static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
  3781. {
  3782. int ret;
  3783. /* If we're in analog mode, then just issue the usual analog
  3784. command. */
  3785. if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
  3786. return pvr2_issue_simple_cmd(hdw,
  3787. (runFl ?
  3788. FX2CMD_STREAMING_ON :
  3789. FX2CMD_STREAMING_OFF));
  3790. /*Note: Not reached */
  3791. }
  3792. if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
  3793. /* Whoops, we don't know what mode we're in... */
  3794. return -EINVAL;
  3795. }
  3796. /* To get here we have to be in digital mode. The mechanism here
  3797. is unfortunately different for different vendors. So we switch
  3798. on the device's digital scheme attribute in order to figure out
  3799. what to do. */
  3800. switch (hdw->hdw_desc->digital_control_scheme) {
  3801. case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
  3802. return pvr2_issue_simple_cmd(hdw,
  3803. (runFl ?
  3804. FX2CMD_HCW_DTV_STREAMING_ON :
  3805. FX2CMD_HCW_DTV_STREAMING_OFF));
  3806. case PVR2_DIGITAL_SCHEME_ONAIR:
  3807. ret = pvr2_issue_simple_cmd(hdw,
  3808. (runFl ?
  3809. FX2CMD_STREAMING_ON :
  3810. FX2CMD_STREAMING_OFF));
  3811. if (ret) return ret;
  3812. return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
  3813. default:
  3814. return -EINVAL;
  3815. }
  3816. }
  3817. /* Evaluate whether or not state_pathway_ok can change */
  3818. static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
  3819. {
  3820. if (hdw->state_pathway_ok) {
  3821. /* Nothing to do if pathway is already ok */
  3822. return 0;
  3823. }
  3824. if (!hdw->state_pipeline_idle) {
  3825. /* Not allowed to change anything if pipeline is not idle */
  3826. return 0;
  3827. }
  3828. pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
  3829. hdw->state_pathway_ok = !0;
  3830. trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
  3831. return !0;
  3832. }
  3833. /* Evaluate whether or not state_encoder_ok can change */
  3834. static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
  3835. {
  3836. if (hdw->state_encoder_ok) return 0;
  3837. if (hdw->flag_tripped) return 0;
  3838. if (hdw->state_encoder_run) return 0;
  3839. if (hdw->state_encoder_config) return 0;
  3840. if (hdw->state_decoder_run) return 0;
  3841. if (hdw->state_usbstream_run) return 0;
  3842. if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
  3843. if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
  3844. } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
  3845. return 0;
  3846. }
  3847. if (pvr2_upload_firmware2(hdw) < 0) {
  3848. hdw->flag_tripped = !0;
  3849. trace_stbit("flag_tripped",hdw->flag_tripped);
  3850. return !0;
  3851. }
  3852. hdw->state_encoder_ok = !0;
  3853. trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
  3854. return !0;
  3855. }
  3856. /* Evaluate whether or not state_encoder_config can change */
  3857. static int state_eval_encoder_config(struct pvr2_hdw *hdw)
  3858. {
  3859. if (hdw->state_encoder_config) {
  3860. if (hdw->state_encoder_ok) {
  3861. if (hdw->state_pipeline_req &&
  3862. !hdw->state_pipeline_pause) return 0;
  3863. }
  3864. hdw->state_encoder_config = 0;
  3865. hdw->state_encoder_waitok = 0;
  3866. trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
  3867. /* paranoia - solve race if timer just completed */
  3868. del_timer_sync(&hdw->encoder_wait_timer);
  3869. } else {
  3870. if (!hdw->state_pathway_ok ||
  3871. (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
  3872. !hdw->state_encoder_ok ||
  3873. !hdw->state_pipeline_idle ||
  3874. hdw->state_pipeline_pause ||
  3875. !hdw->state_pipeline_req ||
  3876. !hdw->state_pipeline_config) {
  3877. /* We must reset the enforced wait interval if
  3878. anything has happened that might have disturbed
  3879. the encoder. This should be a rare case. */
  3880. if (timer_pending(&hdw->encoder_wait_timer)) {
  3881. del_timer_sync(&hdw->encoder_wait_timer);
  3882. }
  3883. if (hdw->state_encoder_waitok) {
  3884. /* Must clear the state - therefore we did
  3885. something to a state bit and must also
  3886. return true. */
  3887. hdw->state_encoder_waitok = 0;
  3888. trace_stbit("state_encoder_waitok",
  3889. hdw->state_encoder_waitok);
  3890. return !0;
  3891. }
  3892. return 0;
  3893. }
  3894. if (!hdw->state_encoder_waitok) {
  3895. if (!timer_pending(&hdw->encoder_wait_timer)) {
  3896. /* waitok flag wasn't set and timer isn't
  3897. running. Check flag once more to avoid
  3898. a race then start the timer. This is
  3899. the point when we measure out a minimal
  3900. quiet interval before doing something to
  3901. the encoder. */
  3902. if (!hdw->state_encoder_waitok) {
  3903. hdw->encoder_wait_timer.expires =
  3904. jiffies +
  3905. (HZ * TIME_MSEC_ENCODER_WAIT
  3906. / 1000);
  3907. add_timer(&hdw->encoder_wait_timer);
  3908. }
  3909. }
  3910. /* We can't continue until we know we have been
  3911. quiet for the interval measured by this
  3912. timer. */
  3913. return 0;
  3914. }
  3915. pvr2_encoder_configure(hdw);
  3916. if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
  3917. }
  3918. trace_stbit("state_encoder_config",hdw->state_encoder_config);
  3919. return !0;
  3920. }
  3921. /* Return true if the encoder should not be running. */
  3922. static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
  3923. {
  3924. if (!hdw->state_encoder_ok) {
  3925. /* Encoder isn't healthy at the moment, so stop it. */
  3926. return !0;
  3927. }
  3928. if (!hdw->state_pathway_ok) {
  3929. /* Mode is not understood at the moment (i.e. it wants to
  3930. change), so encoder must be stopped. */
  3931. return !0;
  3932. }
  3933. switch (hdw->pathway_state) {
  3934. case PVR2_PATHWAY_ANALOG:
  3935. if (!hdw->state_decoder_run) {
  3936. /* We're in analog mode and the decoder is not
  3937. running; thus the encoder should be stopped as
  3938. well. */
  3939. return !0;
  3940. }
  3941. break;
  3942. case PVR2_PATHWAY_DIGITAL:
  3943. if (hdw->state_encoder_runok) {
  3944. /* This is a funny case. We're in digital mode so
  3945. really the encoder should be stopped. However
  3946. if it really is running, only kill it after
  3947. runok has been set. This gives a chance for the
  3948. onair quirk to function (encoder must run
  3949. briefly first, at least once, before onair
  3950. digital streaming can work). */
  3951. return !0;
  3952. }
  3953. break;
  3954. default:
  3955. /* Unknown mode; so encoder should be stopped. */
  3956. return !0;
  3957. }
  3958. /* If we get here, we haven't found a reason to stop the
  3959. encoder. */
  3960. return 0;
  3961. }
  3962. /* Return true if the encoder should be running. */
  3963. static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
  3964. {
  3965. if (!hdw->state_encoder_ok) {
  3966. /* Don't run the encoder if it isn't healthy... */
  3967. return 0;
  3968. }
  3969. if (!hdw->state_pathway_ok) {
  3970. /* Don't run the encoder if we don't (yet) know what mode
  3971. we need to be in... */
  3972. return 0;
  3973. }
  3974. switch (hdw->pathway_state) {
  3975. case PVR2_PATHWAY_ANALOG:
  3976. if (hdw->state_decoder_run && hdw->state_decoder_ready) {
  3977. /* In analog mode, if the decoder is running, then
  3978. run the encoder. */
  3979. return !0;
  3980. }
  3981. break;
  3982. case PVR2_PATHWAY_DIGITAL:
  3983. if ((hdw->hdw_desc->digital_control_scheme ==
  3984. PVR2_DIGITAL_SCHEME_ONAIR) &&
  3985. !hdw->state_encoder_runok) {
  3986. /* This is a quirk. OnAir hardware won't stream
  3987. digital until the encoder has been run at least
  3988. once, for a minimal period of time (empiricially
  3989. measured to be 1/4 second). So if we're on
  3990. OnAir hardware and the encoder has never been
  3991. run at all, then start the encoder. Normal
  3992. state machine logic in the driver will
  3993. automatically handle the remaining bits. */
  3994. return !0;
  3995. }
  3996. break;
  3997. default:
  3998. /* For completeness (unknown mode; encoder won't run ever) */
  3999. break;
  4000. }
  4001. /* If we get here, then we haven't found any reason to run the
  4002. encoder, so don't run it. */
  4003. return 0;
  4004. }
  4005. /* Evaluate whether or not state_encoder_run can change */
  4006. static int state_eval_encoder_run(struct pvr2_hdw *hdw)
  4007. {
  4008. if (hdw->state_encoder_run) {
  4009. if (!state_check_disable_encoder_run(hdw)) return 0;
  4010. if (hdw->state_encoder_ok) {
  4011. del_timer_sync(&hdw->encoder_run_timer);
  4012. if (pvr2_encoder_stop(hdw) < 0) return !0;
  4013. }
  4014. hdw->state_encoder_run = 0;
  4015. } else {
  4016. if (!state_check_enable_encoder_run(hdw)) return 0;
  4017. if (pvr2_encoder_start(hdw) < 0) return !0;
  4018. hdw->state_encoder_run = !0;
  4019. if (!hdw->state_encoder_runok) {
  4020. hdw->encoder_run_timer.expires =
  4021. jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
  4022. add_timer(&hdw->encoder_run_timer);
  4023. }
  4024. }
  4025. trace_stbit("state_encoder_run",hdw->state_encoder_run);
  4026. return !0;
  4027. }
  4028. /* Timeout function for quiescent timer. */
  4029. static void pvr2_hdw_quiescent_timeout(unsigned long data)
  4030. {
  4031. struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
  4032. hdw->state_decoder_quiescent = !0;
  4033. trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
  4034. hdw->state_stale = !0;
  4035. queue_work(hdw->workqueue,&hdw->workpoll);
  4036. }
  4037. /* Timeout function for decoder stabilization timer. */
  4038. static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
  4039. {
  4040. struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
  4041. hdw->state_decoder_ready = !0;
  4042. trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
  4043. hdw->state_stale = !0;
  4044. queue_work(hdw->workqueue, &hdw->workpoll);
  4045. }
  4046. /* Timeout function for encoder wait timer. */
  4047. static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
  4048. {
  4049. struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
  4050. hdw->state_encoder_waitok = !0;
  4051. trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
  4052. hdw->state_stale = !0;
  4053. queue_work(hdw->workqueue,&hdw->workpoll);
  4054. }
  4055. /* Timeout function for encoder run timer. */
  4056. static void pvr2_hdw_encoder_run_timeout(unsigned long data)
  4057. {
  4058. struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
  4059. if (!hdw->state_encoder_runok) {
  4060. hdw->state_encoder_runok = !0;
  4061. trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
  4062. hdw->state_stale = !0;
  4063. queue_work(hdw->workqueue,&hdw->workpoll);
  4064. }
  4065. }
  4066. /* Evaluate whether or not state_decoder_run can change */
  4067. static int state_eval_decoder_run(struct pvr2_hdw *hdw)
  4068. {
  4069. if (hdw->state_decoder_run) {
  4070. if (hdw->state_encoder_ok) {
  4071. if (hdw->state_pipeline_req &&
  4072. !hdw->state_pipeline_pause &&
  4073. hdw->state_pathway_ok) return 0;
  4074. }
  4075. if (!hdw->flag_decoder_missed) {
  4076. pvr2_decoder_enable(hdw,0);
  4077. }
  4078. hdw->state_decoder_quiescent = 0;
  4079. hdw->state_decoder_run = 0;
  4080. /* paranoia - solve race if timer(s) just completed */
  4081. del_timer_sync(&hdw->quiescent_timer);
  4082. /* Kill the stabilization timer, in case we're killing the
  4083. encoder before the previous stabilization interval has
  4084. been properly timed. */
  4085. del_timer_sync(&hdw->decoder_stabilization_timer);
  4086. hdw->state_decoder_ready = 0;
  4087. } else {
  4088. if (!hdw->state_decoder_quiescent) {
  4089. if (!timer_pending(&hdw->quiescent_timer)) {
  4090. /* We don't do something about the
  4091. quiescent timer until right here because
  4092. we also want to catch cases where the
  4093. decoder was already not running (like
  4094. after initialization) as opposed to
  4095. knowing that we had just stopped it.
  4096. The second flag check is here to cover a
  4097. race - the timer could have run and set
  4098. this flag just after the previous check
  4099. but before we did the pending check. */
  4100. if (!hdw->state_decoder_quiescent) {
  4101. hdw->quiescent_timer.expires =
  4102. jiffies +
  4103. (HZ * TIME_MSEC_DECODER_WAIT
  4104. / 1000);
  4105. add_timer(&hdw->quiescent_timer);
  4106. }
  4107. }
  4108. /* Don't allow decoder to start again until it has
  4109. been quiesced first. This little detail should
  4110. hopefully further stabilize the encoder. */
  4111. return 0;
  4112. }
  4113. if (!hdw->state_pathway_ok ||
  4114. (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
  4115. !hdw->state_pipeline_req ||
  4116. hdw->state_pipeline_pause ||
  4117. !hdw->state_pipeline_config ||
  4118. !hdw->state_encoder_config ||
  4119. !hdw->state_encoder_ok) return 0;
  4120. del_timer_sync(&hdw->quiescent_timer);
  4121. if (hdw->flag_decoder_missed) return 0;
  4122. if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
  4123. hdw->state_decoder_quiescent = 0;
  4124. hdw->state_decoder_ready = 0;
  4125. hdw->state_decoder_run = !0;
  4126. if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
  4127. hdw->decoder_stabilization_timer.expires =
  4128. jiffies +
  4129. (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
  4130. 1000);
  4131. add_timer(&hdw->decoder_stabilization_timer);
  4132. } else {
  4133. hdw->state_decoder_ready = !0;
  4134. }
  4135. }
  4136. trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
  4137. trace_stbit("state_decoder_run",hdw->state_decoder_run);
  4138. trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
  4139. return !0;
  4140. }
  4141. /* Evaluate whether or not state_usbstream_run can change */
  4142. static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
  4143. {
  4144. if (hdw->state_usbstream_run) {
  4145. int fl = !0;
  4146. if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
  4147. fl = (hdw->state_encoder_ok &&
  4148. hdw->state_encoder_run);
  4149. } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
  4150. (hdw->hdw_desc->flag_digital_requires_cx23416)) {
  4151. fl = hdw->state_encoder_ok;
  4152. }
  4153. if (fl &&
  4154. hdw->state_pipeline_req &&
  4155. !hdw->state_pipeline_pause &&
  4156. hdw->state_pathway_ok) {
  4157. return 0;
  4158. }
  4159. pvr2_hdw_cmd_usbstream(hdw,0);
  4160. hdw->state_usbstream_run = 0;
  4161. } else {
  4162. if (!hdw->state_pipeline_req ||
  4163. hdw->state_pipeline_pause ||
  4164. !hdw->state_pathway_ok) return 0;
  4165. if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
  4166. if (!hdw->state_encoder_ok ||
  4167. !hdw->state_encoder_run) return 0;
  4168. } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
  4169. (hdw->hdw_desc->flag_digital_requires_cx23416)) {
  4170. if (!hdw->state_encoder_ok) return 0;
  4171. if (hdw->state_encoder_run) return 0;
  4172. if (hdw->hdw_desc->digital_control_scheme ==
  4173. PVR2_DIGITAL_SCHEME_ONAIR) {
  4174. /* OnAir digital receivers won't stream
  4175. unless the analog encoder has run first.
  4176. Why? I have no idea. But don't even
  4177. try until we know the analog side is
  4178. known to have run. */
  4179. if (!hdw->state_encoder_runok) return 0;
  4180. }
  4181. }
  4182. if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
  4183. hdw->state_usbstream_run = !0;
  4184. }
  4185. trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
  4186. return !0;
  4187. }
  4188. /* Attempt to configure pipeline, if needed */
  4189. static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
  4190. {
  4191. if (hdw->state_pipeline_config ||
  4192. hdw->state_pipeline_pause) return 0;
  4193. pvr2_hdw_commit_execute(hdw);
  4194. return !0;
  4195. }
  4196. /* Update pipeline idle and pipeline pause tracking states based on other
  4197. inputs. This must be called whenever the other relevant inputs have
  4198. changed. */
  4199. static int state_update_pipeline_state(struct pvr2_hdw *hdw)
  4200. {
  4201. unsigned int st;
  4202. int updatedFl = 0;
  4203. /* Update pipeline state */
  4204. st = !(hdw->state_encoder_run ||
  4205. hdw->state_decoder_run ||
  4206. hdw->state_usbstream_run ||
  4207. (!hdw->state_decoder_quiescent));
  4208. if (!st != !hdw->state_pipeline_idle) {
  4209. hdw->state_pipeline_idle = st;
  4210. updatedFl = !0;
  4211. }
  4212. if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
  4213. hdw->state_pipeline_pause = 0;
  4214. updatedFl = !0;
  4215. }
  4216. return updatedFl;
  4217. }
  4218. typedef int (*state_eval_func)(struct pvr2_hdw *);
  4219. /* Set of functions to be run to evaluate various states in the driver. */
  4220. static const state_eval_func eval_funcs[] = {
  4221. state_eval_pathway_ok,
  4222. state_eval_pipeline_config,
  4223. state_eval_encoder_ok,
  4224. state_eval_encoder_config,
  4225. state_eval_decoder_run,
  4226. state_eval_encoder_run,
  4227. state_eval_usbstream_run,
  4228. };
  4229. /* Process various states and return true if we did anything interesting. */
  4230. static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
  4231. {
  4232. unsigned int i;
  4233. int state_updated = 0;
  4234. int check_flag;
  4235. if (!hdw->state_stale) return 0;
  4236. if ((hdw->fw1_state != FW1_STATE_OK) ||
  4237. !hdw->flag_ok) {
  4238. hdw->state_stale = 0;
  4239. return !0;
  4240. }
  4241. /* This loop is the heart of the entire driver. It keeps trying to
  4242. evaluate various bits of driver state until nothing changes for
  4243. one full iteration. Each "bit of state" tracks some global
  4244. aspect of the driver, e.g. whether decoder should run, if
  4245. pipeline is configured, usb streaming is on, etc. We separately
  4246. evaluate each of those questions based on other driver state to
  4247. arrive at the correct running configuration. */
  4248. do {
  4249. check_flag = 0;
  4250. state_update_pipeline_state(hdw);
  4251. /* Iterate over each bit of state */
  4252. for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
  4253. if ((*eval_funcs[i])(hdw)) {
  4254. check_flag = !0;
  4255. state_updated = !0;
  4256. state_update_pipeline_state(hdw);
  4257. }
  4258. }
  4259. } while (check_flag && hdw->flag_ok);
  4260. hdw->state_stale = 0;
  4261. trace_stbit("state_stale",hdw->state_stale);
  4262. return state_updated;
  4263. }
  4264. static unsigned int print_input_mask(unsigned int msk,
  4265. char *buf,unsigned int acnt)
  4266. {
  4267. unsigned int idx,ccnt;
  4268. unsigned int tcnt = 0;
  4269. for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
  4270. if (!((1 << idx) & msk)) continue;
  4271. ccnt = scnprintf(buf+tcnt,
  4272. acnt-tcnt,
  4273. "%s%s",
  4274. (tcnt ? ", " : ""),
  4275. control_values_input[idx]);
  4276. tcnt += ccnt;
  4277. }
  4278. return tcnt;
  4279. }
  4280. static const char *pvr2_pathway_state_name(int id)
  4281. {
  4282. switch (id) {
  4283. case PVR2_PATHWAY_ANALOG: return "analog";
  4284. case PVR2_PATHWAY_DIGITAL: return "digital";
  4285. default: return "unknown";
  4286. }
  4287. }
  4288. static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
  4289. char *buf,unsigned int acnt)
  4290. {
  4291. switch (which) {
  4292. case 0:
  4293. return scnprintf(
  4294. buf,acnt,
  4295. "driver:%s%s%s%s%s <mode=%s>",
  4296. (hdw->flag_ok ? " <ok>" : " <fail>"),
  4297. (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
  4298. (hdw->flag_disconnected ? " <disconnected>" :
  4299. " <connected>"),
  4300. (hdw->flag_tripped ? " <tripped>" : ""),
  4301. (hdw->flag_decoder_missed ? " <no decoder>" : ""),
  4302. pvr2_pathway_state_name(hdw->pathway_state));
  4303. case 1:
  4304. return scnprintf(
  4305. buf,acnt,
  4306. "pipeline:%s%s%s%s",
  4307. (hdw->state_pipeline_idle ? " <idle>" : ""),
  4308. (hdw->state_pipeline_config ?
  4309. " <configok>" : " <stale>"),
  4310. (hdw->state_pipeline_req ? " <req>" : ""),
  4311. (hdw->state_pipeline_pause ? " <pause>" : ""));
  4312. case 2:
  4313. return scnprintf(
  4314. buf,acnt,
  4315. "worker:%s%s%s%s%s%s%s",
  4316. (hdw->state_decoder_run ?
  4317. (hdw->state_decoder_ready ?
  4318. "<decode:run>" : " <decode:start>") :
  4319. (hdw->state_decoder_quiescent ?
  4320. "" : " <decode:stop>")),
  4321. (hdw->state_decoder_quiescent ?
  4322. " <decode:quiescent>" : ""),
  4323. (hdw->state_encoder_ok ?
  4324. "" : " <encode:init>"),
  4325. (hdw->state_encoder_run ?
  4326. (hdw->state_encoder_runok ?
  4327. " <encode:run>" :
  4328. " <encode:firstrun>") :
  4329. (hdw->state_encoder_runok ?
  4330. " <encode:stop>" :
  4331. " <encode:virgin>")),
  4332. (hdw->state_encoder_config ?
  4333. " <encode:configok>" :
  4334. (hdw->state_encoder_waitok ?
  4335. "" : " <encode:waitok>")),
  4336. (hdw->state_usbstream_run ?
  4337. " <usb:run>" : " <usb:stop>"),
  4338. (hdw->state_pathway_ok ?
  4339. " <pathway:ok>" : ""));
  4340. case 3:
  4341. return scnprintf(
  4342. buf,acnt,
  4343. "state: %s",
  4344. pvr2_get_state_name(hdw->master_state));
  4345. case 4: {
  4346. unsigned int tcnt = 0;
  4347. unsigned int ccnt;
  4348. ccnt = scnprintf(buf,
  4349. acnt,
  4350. "Hardware supported inputs: ");
  4351. tcnt += ccnt;
  4352. tcnt += print_input_mask(hdw->input_avail_mask,
  4353. buf+tcnt,
  4354. acnt-tcnt);
  4355. if (hdw->input_avail_mask != hdw->input_allowed_mask) {
  4356. ccnt = scnprintf(buf+tcnt,
  4357. acnt-tcnt,
  4358. "; allowed inputs: ");
  4359. tcnt += ccnt;
  4360. tcnt += print_input_mask(hdw->input_allowed_mask,
  4361. buf+tcnt,
  4362. acnt-tcnt);
  4363. }
  4364. return tcnt;
  4365. }
  4366. case 5: {
  4367. struct pvr2_stream_stats stats;
  4368. if (!hdw->vid_stream) break;
  4369. pvr2_stream_get_stats(hdw->vid_stream,
  4370. &stats,
  4371. 0);
  4372. return scnprintf(
  4373. buf,acnt,
  4374. "Bytes streamed=%u"
  4375. " URBs: queued=%u idle=%u ready=%u"
  4376. " processed=%u failed=%u",
  4377. stats.bytes_processed,
  4378. stats.buffers_in_queue,
  4379. stats.buffers_in_idle,
  4380. stats.buffers_in_ready,
  4381. stats.buffers_processed,
  4382. stats.buffers_failed);
  4383. }
  4384. case 6: {
  4385. unsigned int id = hdw->ir_scheme_active;
  4386. return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
  4387. (id >= ARRAY_SIZE(ir_scheme_names) ?
  4388. "?" : ir_scheme_names[id]));
  4389. }
  4390. default: break;
  4391. }
  4392. return 0;
  4393. }
  4394. /* Generate report containing info about attached sub-devices and attached
  4395. i2c clients, including an indication of which attached i2c clients are
  4396. actually sub-devices. */
  4397. static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
  4398. char *buf, unsigned int acnt)
  4399. {
  4400. struct v4l2_subdev *sd;
  4401. unsigned int tcnt = 0;
  4402. unsigned int ccnt;
  4403. struct i2c_client *client;
  4404. const char *p;
  4405. unsigned int id;
  4406. ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
  4407. tcnt += ccnt;
  4408. v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
  4409. id = sd->grp_id;
  4410. p = NULL;
  4411. if (id < ARRAY_SIZE(module_names)) p = module_names[id];
  4412. if (p) {
  4413. ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
  4414. tcnt += ccnt;
  4415. } else {
  4416. ccnt = scnprintf(buf + tcnt, acnt - tcnt,
  4417. " (unknown id=%u):", id);
  4418. tcnt += ccnt;
  4419. }
  4420. client = v4l2_get_subdevdata(sd);
  4421. if (client) {
  4422. ccnt = scnprintf(buf + tcnt, acnt - tcnt,
  4423. " %s @ %02x\n", client->name,
  4424. client->addr);
  4425. tcnt += ccnt;
  4426. } else {
  4427. ccnt = scnprintf(buf + tcnt, acnt - tcnt,
  4428. " no i2c client\n");
  4429. tcnt += ccnt;
  4430. }
  4431. }
  4432. return tcnt;
  4433. }
  4434. unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
  4435. char *buf,unsigned int acnt)
  4436. {
  4437. unsigned int bcnt,ccnt,idx;
  4438. bcnt = 0;
  4439. LOCK_TAKE(hdw->big_lock);
  4440. for (idx = 0; ; idx++) {
  4441. ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
  4442. if (!ccnt) break;
  4443. bcnt += ccnt; acnt -= ccnt; buf += ccnt;
  4444. if (!acnt) break;
  4445. buf[0] = '\n'; ccnt = 1;
  4446. bcnt += ccnt; acnt -= ccnt; buf += ccnt;
  4447. }
  4448. ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
  4449. bcnt += ccnt; acnt -= ccnt; buf += ccnt;
  4450. LOCK_GIVE(hdw->big_lock);
  4451. return bcnt;
  4452. }
  4453. static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
  4454. {
  4455. char buf[256];
  4456. unsigned int idx, ccnt;
  4457. unsigned int lcnt, ucnt;
  4458. for (idx = 0; ; idx++) {
  4459. ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
  4460. if (!ccnt) break;
  4461. printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
  4462. }
  4463. ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
  4464. ucnt = 0;
  4465. while (ucnt < ccnt) {
  4466. lcnt = 0;
  4467. while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
  4468. lcnt++;
  4469. }
  4470. printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
  4471. ucnt += lcnt + 1;
  4472. }
  4473. }
  4474. /* Evaluate and update the driver's current state, taking various actions
  4475. as appropriate for the update. */
  4476. static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
  4477. {
  4478. unsigned int st;
  4479. int state_updated = 0;
  4480. int callback_flag = 0;
  4481. int analog_mode;
  4482. pvr2_trace(PVR2_TRACE_STBITS,
  4483. "Drive state check START");
  4484. if (pvrusb2_debug & PVR2_TRACE_STBITS) {
  4485. pvr2_hdw_state_log_state(hdw);
  4486. }
  4487. /* Process all state and get back over disposition */
  4488. state_updated = pvr2_hdw_state_update(hdw);
  4489. analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
  4490. /* Update master state based upon all other states. */
  4491. if (!hdw->flag_ok) {
  4492. st = PVR2_STATE_DEAD;
  4493. } else if (hdw->fw1_state != FW1_STATE_OK) {
  4494. st = PVR2_STATE_COLD;
  4495. } else if ((analog_mode ||
  4496. hdw->hdw_desc->flag_digital_requires_cx23416) &&
  4497. !hdw->state_encoder_ok) {
  4498. st = PVR2_STATE_WARM;
  4499. } else if (hdw->flag_tripped ||
  4500. (analog_mode && hdw->flag_decoder_missed)) {
  4501. st = PVR2_STATE_ERROR;
  4502. } else if (hdw->state_usbstream_run &&
  4503. (!analog_mode ||
  4504. (hdw->state_encoder_run && hdw->state_decoder_run))) {
  4505. st = PVR2_STATE_RUN;
  4506. } else {
  4507. st = PVR2_STATE_READY;
  4508. }
  4509. if (hdw->master_state != st) {
  4510. pvr2_trace(PVR2_TRACE_STATE,
  4511. "Device state change from %s to %s",
  4512. pvr2_get_state_name(hdw->master_state),
  4513. pvr2_get_state_name(st));
  4514. pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
  4515. hdw->master_state = st;
  4516. state_updated = !0;
  4517. callback_flag = !0;
  4518. }
  4519. if (state_updated) {
  4520. /* Trigger anyone waiting on any state changes here. */
  4521. wake_up(&hdw->state_wait_data);
  4522. }
  4523. if (pvrusb2_debug & PVR2_TRACE_STBITS) {
  4524. pvr2_hdw_state_log_state(hdw);
  4525. }
  4526. pvr2_trace(PVR2_TRACE_STBITS,
  4527. "Drive state check DONE callback=%d",callback_flag);
  4528. return callback_flag;
  4529. }
  4530. /* Cause kernel thread to check / update driver state */
  4531. static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
  4532. {
  4533. if (hdw->state_stale) return;
  4534. hdw->state_stale = !0;
  4535. trace_stbit("state_stale",hdw->state_stale);
  4536. queue_work(hdw->workqueue,&hdw->workpoll);
  4537. }
  4538. int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
  4539. {
  4540. return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
  4541. }
  4542. int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
  4543. {
  4544. return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
  4545. }
  4546. int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
  4547. {
  4548. return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
  4549. }
  4550. int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
  4551. {
  4552. u32 cval,nval;
  4553. int ret;
  4554. if (~msk) {
  4555. ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
  4556. if (ret) return ret;
  4557. nval = (cval & ~msk) | (val & msk);
  4558. pvr2_trace(PVR2_TRACE_GPIO,
  4559. "GPIO direction changing 0x%x:0x%x"
  4560. " from 0x%x to 0x%x",
  4561. msk,val,cval,nval);
  4562. } else {
  4563. nval = val;
  4564. pvr2_trace(PVR2_TRACE_GPIO,
  4565. "GPIO direction changing to 0x%x",nval);
  4566. }
  4567. return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
  4568. }
  4569. int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
  4570. {
  4571. u32 cval,nval;
  4572. int ret;
  4573. if (~msk) {
  4574. ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
  4575. if (ret) return ret;
  4576. nval = (cval & ~msk) | (val & msk);
  4577. pvr2_trace(PVR2_TRACE_GPIO,
  4578. "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
  4579. msk,val,cval,nval);
  4580. } else {
  4581. nval = val;
  4582. pvr2_trace(PVR2_TRACE_GPIO,
  4583. "GPIO output changing to 0x%x",nval);
  4584. }
  4585. return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
  4586. }
  4587. void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
  4588. {
  4589. struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
  4590. memset(vtp, 0, sizeof(*vtp));
  4591. vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
  4592. V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
  4593. hdw->tuner_signal_stale = 0;
  4594. /* Note: There apparently is no replacement for VIDIOC_CROPCAP
  4595. using v4l2-subdev - therefore we can't support that AT ALL right
  4596. now. (Of course, no sub-drivers seem to implement it either.
  4597. But now it's a a chicken and egg problem...) */
  4598. v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
  4599. pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
  4600. " type=%u strength=%u audio=0x%x cap=0x%x"
  4601. " low=%u hi=%u",
  4602. vtp->type,
  4603. vtp->signal, vtp->rxsubchans, vtp->capability,
  4604. vtp->rangelow, vtp->rangehigh);
  4605. /* We have to do this to avoid getting into constant polling if
  4606. there's nobody to answer a poll of cropcap info. */
  4607. hdw->cropcap_stale = 0;
  4608. }
  4609. unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
  4610. {
  4611. return hdw->input_avail_mask;
  4612. }
  4613. unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
  4614. {
  4615. return hdw->input_allowed_mask;
  4616. }
  4617. static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
  4618. {
  4619. if (hdw->input_val != v) {
  4620. hdw->input_val = v;
  4621. hdw->input_dirty = !0;
  4622. }
  4623. /* Handle side effects - if we switch to a mode that needs the RF
  4624. tuner, then select the right frequency choice as well and mark
  4625. it dirty. */
  4626. if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
  4627. hdw->freqSelector = 0;
  4628. hdw->freqDirty = !0;
  4629. } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
  4630. (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
  4631. hdw->freqSelector = 1;
  4632. hdw->freqDirty = !0;
  4633. }
  4634. return 0;
  4635. }
  4636. int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
  4637. unsigned int change_mask,
  4638. unsigned int change_val)
  4639. {
  4640. int ret = 0;
  4641. unsigned int nv,m,idx;
  4642. LOCK_TAKE(hdw->big_lock);
  4643. do {
  4644. nv = hdw->input_allowed_mask & ~change_mask;
  4645. nv |= (change_val & change_mask);
  4646. nv &= hdw->input_avail_mask;
  4647. if (!nv) {
  4648. /* No legal modes left; return error instead. */
  4649. ret = -EPERM;
  4650. break;
  4651. }
  4652. hdw->input_allowed_mask = nv;
  4653. if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
  4654. /* Current mode is still in the allowed mask, so
  4655. we're done. */
  4656. break;
  4657. }
  4658. /* Select and switch to a mode that is still in the allowed
  4659. mask */
  4660. if (!hdw->input_allowed_mask) {
  4661. /* Nothing legal; give up */
  4662. break;
  4663. }
  4664. m = hdw->input_allowed_mask;
  4665. for (idx = 0; idx < (sizeof(m) << 3); idx++) {
  4666. if (!((1 << idx) & m)) continue;
  4667. pvr2_hdw_set_input(hdw,idx);
  4668. break;
  4669. }
  4670. } while (0);
  4671. LOCK_GIVE(hdw->big_lock);
  4672. return ret;
  4673. }
  4674. /* Find I2C address of eeprom */
  4675. static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
  4676. {
  4677. int result;
  4678. LOCK_TAKE(hdw->ctl_lock); do {
  4679. hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
  4680. result = pvr2_send_request(hdw,
  4681. hdw->cmd_buffer,1,
  4682. hdw->cmd_buffer,1);
  4683. if (result < 0) break;
  4684. result = hdw->cmd_buffer[0];
  4685. } while(0); LOCK_GIVE(hdw->ctl_lock);
  4686. return result;
  4687. }
  4688. int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
  4689. struct v4l2_dbg_match *match, u64 reg_id,
  4690. int setFl, u64 *val_ptr)
  4691. {
  4692. #ifdef CONFIG_VIDEO_ADV_DEBUG
  4693. struct v4l2_dbg_register req;
  4694. int stat = 0;
  4695. int okFl = 0;
  4696. if (!capable(CAP_SYS_ADMIN)) return -EPERM;
  4697. req.match = *match;
  4698. req.reg = reg_id;
  4699. if (setFl) req.val = *val_ptr;
  4700. /* It would be nice to know if a sub-device answered the request */
  4701. v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
  4702. if (!setFl) *val_ptr = req.val;
  4703. if (okFl) {
  4704. return stat;
  4705. }
  4706. return -EINVAL;
  4707. #else
  4708. return -ENOSYS;
  4709. #endif
  4710. }
  4711. /*
  4712. Stuff for Emacs to see, in order to encourage consistent editing style:
  4713. *** Local Variables: ***
  4714. *** mode: c ***
  4715. *** fill-column: 75 ***
  4716. *** tab-width: 8 ***
  4717. *** c-basic-offset: 8 ***
  4718. *** End: ***
  4719. */