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/drivers/atm/he.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 2897 lines | 2041 code | 559 blank | 297 comment | 321 complexity | 8c64c5a648ccf2c3dbb31f55554c729a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. he.c
  3. ForeRunnerHE ATM Adapter driver for ATM on Linux
  4. Copyright (C) 1999-2001 Naval Research Laboratory
  5. This library is free software; you can redistribute it and/or
  6. modify it under the terms of the GNU Lesser General Public
  7. License as published by the Free Software Foundation; either
  8. version 2.1 of the License, or (at your option) any later version.
  9. This library is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. Lesser General Public License for more details.
  13. You should have received a copy of the GNU Lesser General Public
  14. License along with this library; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. /*
  18. he.c
  19. ForeRunnerHE ATM Adapter driver for ATM on Linux
  20. Copyright (C) 1999-2001 Naval Research Laboratory
  21. Permission to use, copy, modify and distribute this software and its
  22. documentation is hereby granted, provided that both the copyright
  23. notice and this permission notice appear in all copies of the software,
  24. derivative works or modified versions, and any portions thereof, and
  25. that both notices appear in supporting documentation.
  26. NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
  27. DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
  28. RESULTING FROM THE USE OF THIS SOFTWARE.
  29. This driver was written using the "Programmer's Reference Manual for
  30. ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.
  31. AUTHORS:
  32. chas williams <chas@cmf.nrl.navy.mil>
  33. eric kinzie <ekinzie@cmf.nrl.navy.mil>
  34. NOTES:
  35. 4096 supported 'connections'
  36. group 0 is used for all traffic
  37. interrupt queue 0 is used for all interrupts
  38. aal0 support (based on work from ulrich.u.muller@nokia.com)
  39. */
  40. #include <linux/module.h>
  41. #include <linux/kernel.h>
  42. #include <linux/skbuff.h>
  43. #include <linux/pci.h>
  44. #include <linux/errno.h>
  45. #include <linux/types.h>
  46. #include <linux/string.h>
  47. #include <linux/delay.h>
  48. #include <linux/init.h>
  49. #include <linux/mm.h>
  50. #include <linux/sched.h>
  51. #include <linux/timer.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/dma-mapping.h>
  54. #include <linux/bitmap.h>
  55. #include <linux/slab.h>
  56. #include <asm/io.h>
  57. #include <asm/byteorder.h>
  58. #include <asm/uaccess.h>
  59. #include <linux/atmdev.h>
  60. #include <linux/atm.h>
  61. #include <linux/sonet.h>
  62. #undef USE_SCATTERGATHER
  63. #undef USE_CHECKSUM_HW /* still confused about this */
  64. /* #undef HE_DEBUG */
  65. #include "he.h"
  66. #include "suni.h"
  67. #include <linux/atm_he.h>
  68. #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
  69. #ifdef HE_DEBUG
  70. #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
  71. #else /* !HE_DEBUG */
  72. #define HPRINTK(fmt,args...) do { } while (0)
  73. #endif /* HE_DEBUG */
  74. /* declarations */
  75. static int he_open(struct atm_vcc *vcc);
  76. static void he_close(struct atm_vcc *vcc);
  77. static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);
  78. static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);
  79. static irqreturn_t he_irq_handler(int irq, void *dev_id);
  80. static void he_tasklet(unsigned long data);
  81. static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);
  82. static int he_start(struct atm_dev *dev);
  83. static void he_stop(struct he_dev *dev);
  84. static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);
  85. static unsigned char he_phy_get(struct atm_dev *, unsigned long);
  86. static u8 read_prom_byte(struct he_dev *he_dev, int addr);
  87. /* globals */
  88. static struct he_dev *he_devs;
  89. static int disable64;
  90. static short nvpibits = -1;
  91. static short nvcibits = -1;
  92. static short rx_skb_reserve = 16;
  93. static int irq_coalesce = 1;
  94. static int sdh = 0;
  95. /* Read from EEPROM = 0000 0011b */
  96. static unsigned int readtab[] = {
  97. CS_HIGH | CLK_HIGH,
  98. CS_LOW | CLK_LOW,
  99. CLK_HIGH, /* 0 */
  100. CLK_LOW,
  101. CLK_HIGH, /* 0 */
  102. CLK_LOW,
  103. CLK_HIGH, /* 0 */
  104. CLK_LOW,
  105. CLK_HIGH, /* 0 */
  106. CLK_LOW,
  107. CLK_HIGH, /* 0 */
  108. CLK_LOW,
  109. CLK_HIGH, /* 0 */
  110. CLK_LOW | SI_HIGH,
  111. CLK_HIGH | SI_HIGH, /* 1 */
  112. CLK_LOW | SI_HIGH,
  113. CLK_HIGH | SI_HIGH /* 1 */
  114. };
  115. /* Clock to read from/write to the EEPROM */
  116. static unsigned int clocktab[] = {
  117. CLK_LOW,
  118. CLK_HIGH,
  119. CLK_LOW,
  120. CLK_HIGH,
  121. CLK_LOW,
  122. CLK_HIGH,
  123. CLK_LOW,
  124. CLK_HIGH,
  125. CLK_LOW,
  126. CLK_HIGH,
  127. CLK_LOW,
  128. CLK_HIGH,
  129. CLK_LOW,
  130. CLK_HIGH,
  131. CLK_LOW,
  132. CLK_HIGH,
  133. CLK_LOW
  134. };
  135. static struct atmdev_ops he_ops =
  136. {
  137. .open = he_open,
  138. .close = he_close,
  139. .ioctl = he_ioctl,
  140. .send = he_send,
  141. .phy_put = he_phy_put,
  142. .phy_get = he_phy_get,
  143. .proc_read = he_proc_read,
  144. .owner = THIS_MODULE
  145. };
  146. #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
  147. #define he_readl(dev, reg) readl((dev)->membase + (reg))
  148. /* section 2.12 connection memory access */
  149. static __inline__ void
  150. he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
  151. unsigned flags)
  152. {
  153. he_writel(he_dev, val, CON_DAT);
  154. (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
  155. he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
  156. while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
  157. }
  158. #define he_writel_rcm(dev, val, reg) \
  159. he_writel_internal(dev, val, reg, CON_CTL_RCM)
  160. #define he_writel_tcm(dev, val, reg) \
  161. he_writel_internal(dev, val, reg, CON_CTL_TCM)
  162. #define he_writel_mbox(dev, val, reg) \
  163. he_writel_internal(dev, val, reg, CON_CTL_MBOX)
  164. static unsigned
  165. he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
  166. {
  167. he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
  168. while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
  169. return he_readl(he_dev, CON_DAT);
  170. }
  171. #define he_readl_rcm(dev, reg) \
  172. he_readl_internal(dev, reg, CON_CTL_RCM)
  173. #define he_readl_tcm(dev, reg) \
  174. he_readl_internal(dev, reg, CON_CTL_TCM)
  175. #define he_readl_mbox(dev, reg) \
  176. he_readl_internal(dev, reg, CON_CTL_MBOX)
  177. /* figure 2.2 connection id */
  178. #define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
  179. /* 2.5.1 per connection transmit state registers */
  180. #define he_writel_tsr0(dev, val, cid) \
  181. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
  182. #define he_readl_tsr0(dev, cid) \
  183. he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
  184. #define he_writel_tsr1(dev, val, cid) \
  185. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
  186. #define he_writel_tsr2(dev, val, cid) \
  187. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
  188. #define he_writel_tsr3(dev, val, cid) \
  189. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
  190. #define he_writel_tsr4(dev, val, cid) \
  191. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
  192. /* from page 2-20
  193. *
  194. * NOTE While the transmit connection is active, bits 23 through 0
  195. * of this register must not be written by the host. Byte
  196. * enables should be used during normal operation when writing
  197. * the most significant byte.
  198. */
  199. #define he_writel_tsr4_upper(dev, val, cid) \
  200. he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
  201. CON_CTL_TCM \
  202. | CON_BYTE_DISABLE_2 \
  203. | CON_BYTE_DISABLE_1 \
  204. | CON_BYTE_DISABLE_0)
  205. #define he_readl_tsr4(dev, cid) \
  206. he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
  207. #define he_writel_tsr5(dev, val, cid) \
  208. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
  209. #define he_writel_tsr6(dev, val, cid) \
  210. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
  211. #define he_writel_tsr7(dev, val, cid) \
  212. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
  213. #define he_writel_tsr8(dev, val, cid) \
  214. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
  215. #define he_writel_tsr9(dev, val, cid) \
  216. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
  217. #define he_writel_tsr10(dev, val, cid) \
  218. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
  219. #define he_writel_tsr11(dev, val, cid) \
  220. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
  221. #define he_writel_tsr12(dev, val, cid) \
  222. he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
  223. #define he_writel_tsr13(dev, val, cid) \
  224. he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
  225. #define he_writel_tsr14(dev, val, cid) \
  226. he_writel_tcm(dev, val, CONFIG_TSRD | cid)
  227. #define he_writel_tsr14_upper(dev, val, cid) \
  228. he_writel_internal(dev, val, CONFIG_TSRD | cid, \
  229. CON_CTL_TCM \
  230. | CON_BYTE_DISABLE_2 \
  231. | CON_BYTE_DISABLE_1 \
  232. | CON_BYTE_DISABLE_0)
  233. /* 2.7.1 per connection receive state registers */
  234. #define he_writel_rsr0(dev, val, cid) \
  235. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
  236. #define he_readl_rsr0(dev, cid) \
  237. he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
  238. #define he_writel_rsr1(dev, val, cid) \
  239. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
  240. #define he_writel_rsr2(dev, val, cid) \
  241. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
  242. #define he_writel_rsr3(dev, val, cid) \
  243. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
  244. #define he_writel_rsr4(dev, val, cid) \
  245. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
  246. #define he_writel_rsr5(dev, val, cid) \
  247. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
  248. #define he_writel_rsr6(dev, val, cid) \
  249. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
  250. #define he_writel_rsr7(dev, val, cid) \
  251. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
  252. static __inline__ struct atm_vcc*
  253. __find_vcc(struct he_dev *he_dev, unsigned cid)
  254. {
  255. struct hlist_head *head;
  256. struct atm_vcc *vcc;
  257. struct hlist_node *node;
  258. struct sock *s;
  259. short vpi;
  260. int vci;
  261. vpi = cid >> he_dev->vcibits;
  262. vci = cid & ((1 << he_dev->vcibits) - 1);
  263. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  264. sk_for_each(s, node, head) {
  265. vcc = atm_sk(s);
  266. if (vcc->dev == he_dev->atm_dev &&
  267. vcc->vci == vci && vcc->vpi == vpi &&
  268. vcc->qos.rxtp.traffic_class != ATM_NONE) {
  269. return vcc;
  270. }
  271. }
  272. return NULL;
  273. }
  274. static int __devinit
  275. he_init_one(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
  276. {
  277. struct atm_dev *atm_dev = NULL;
  278. struct he_dev *he_dev = NULL;
  279. int err = 0;
  280. printk(KERN_INFO "ATM he driver\n");
  281. if (pci_enable_device(pci_dev))
  282. return -EIO;
  283. if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)) != 0) {
  284. printk(KERN_WARNING "he: no suitable dma available\n");
  285. err = -EIO;
  286. goto init_one_failure;
  287. }
  288. atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &he_ops, -1, NULL);
  289. if (!atm_dev) {
  290. err = -ENODEV;
  291. goto init_one_failure;
  292. }
  293. pci_set_drvdata(pci_dev, atm_dev);
  294. he_dev = kzalloc(sizeof(struct he_dev),
  295. GFP_KERNEL);
  296. if (!he_dev) {
  297. err = -ENOMEM;
  298. goto init_one_failure;
  299. }
  300. he_dev->pci_dev = pci_dev;
  301. he_dev->atm_dev = atm_dev;
  302. he_dev->atm_dev->dev_data = he_dev;
  303. atm_dev->dev_data = he_dev;
  304. he_dev->number = atm_dev->number;
  305. tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
  306. spin_lock_init(&he_dev->global_lock);
  307. if (he_start(atm_dev)) {
  308. he_stop(he_dev);
  309. err = -ENODEV;
  310. goto init_one_failure;
  311. }
  312. he_dev->next = NULL;
  313. if (he_devs)
  314. he_dev->next = he_devs;
  315. he_devs = he_dev;
  316. return 0;
  317. init_one_failure:
  318. if (atm_dev)
  319. atm_dev_deregister(atm_dev);
  320. kfree(he_dev);
  321. pci_disable_device(pci_dev);
  322. return err;
  323. }
  324. static void __devexit
  325. he_remove_one (struct pci_dev *pci_dev)
  326. {
  327. struct atm_dev *atm_dev;
  328. struct he_dev *he_dev;
  329. atm_dev = pci_get_drvdata(pci_dev);
  330. he_dev = HE_DEV(atm_dev);
  331. /* need to remove from he_devs */
  332. he_stop(he_dev);
  333. atm_dev_deregister(atm_dev);
  334. kfree(he_dev);
  335. pci_set_drvdata(pci_dev, NULL);
  336. pci_disable_device(pci_dev);
  337. }
  338. static unsigned
  339. rate_to_atmf(unsigned rate) /* cps to atm forum format */
  340. {
  341. #define NONZERO (1 << 14)
  342. unsigned exp = 0;
  343. if (rate == 0)
  344. return 0;
  345. rate <<= 9;
  346. while (rate > 0x3ff) {
  347. ++exp;
  348. rate >>= 1;
  349. }
  350. return (NONZERO | (exp << 9) | (rate & 0x1ff));
  351. }
  352. static void __devinit
  353. he_init_rx_lbfp0(struct he_dev *he_dev)
  354. {
  355. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  356. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  357. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  358. unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
  359. lbufd_index = 0;
  360. lbm_offset = he_readl(he_dev, RCMLBM_BA);
  361. he_writel(he_dev, lbufd_index, RLBF0_H);
  362. for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
  363. lbufd_index += 2;
  364. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  365. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  366. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  367. if (++lbuf_count == lbufs_per_row) {
  368. lbuf_count = 0;
  369. row_offset += he_dev->bytes_per_row;
  370. }
  371. lbm_offset += 4;
  372. }
  373. he_writel(he_dev, lbufd_index - 2, RLBF0_T);
  374. he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
  375. }
  376. static void __devinit
  377. he_init_rx_lbfp1(struct he_dev *he_dev)
  378. {
  379. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  380. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  381. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  382. unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
  383. lbufd_index = 1;
  384. lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
  385. he_writel(he_dev, lbufd_index, RLBF1_H);
  386. for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
  387. lbufd_index += 2;
  388. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  389. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  390. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  391. if (++lbuf_count == lbufs_per_row) {
  392. lbuf_count = 0;
  393. row_offset += he_dev->bytes_per_row;
  394. }
  395. lbm_offset += 4;
  396. }
  397. he_writel(he_dev, lbufd_index - 2, RLBF1_T);
  398. he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
  399. }
  400. static void __devinit
  401. he_init_tx_lbfp(struct he_dev *he_dev)
  402. {
  403. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  404. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  405. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  406. unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
  407. lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
  408. lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
  409. he_writel(he_dev, lbufd_index, TLBF_H);
  410. for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
  411. lbufd_index += 1;
  412. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  413. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  414. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  415. if (++lbuf_count == lbufs_per_row) {
  416. lbuf_count = 0;
  417. row_offset += he_dev->bytes_per_row;
  418. }
  419. lbm_offset += 2;
  420. }
  421. he_writel(he_dev, lbufd_index - 1, TLBF_T);
  422. }
  423. static int __devinit
  424. he_init_tpdrq(struct he_dev *he_dev)
  425. {
  426. he_dev->tpdrq_base = pci_alloc_consistent(he_dev->pci_dev,
  427. CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq), &he_dev->tpdrq_phys);
  428. if (he_dev->tpdrq_base == NULL) {
  429. hprintk("failed to alloc tpdrq\n");
  430. return -ENOMEM;
  431. }
  432. memset(he_dev->tpdrq_base, 0,
  433. CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq));
  434. he_dev->tpdrq_tail = he_dev->tpdrq_base;
  435. he_dev->tpdrq_head = he_dev->tpdrq_base;
  436. he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
  437. he_writel(he_dev, 0, TPDRQ_T);
  438. he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
  439. return 0;
  440. }
  441. static void __devinit
  442. he_init_cs_block(struct he_dev *he_dev)
  443. {
  444. unsigned clock, rate, delta;
  445. int reg;
  446. /* 5.1.7 cs block initialization */
  447. for (reg = 0; reg < 0x20; ++reg)
  448. he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
  449. /* rate grid timer reload values */
  450. clock = he_is622(he_dev) ? 66667000 : 50000000;
  451. rate = he_dev->atm_dev->link_rate;
  452. delta = rate / 16 / 2;
  453. for (reg = 0; reg < 0x10; ++reg) {
  454. /* 2.4 internal transmit function
  455. *
  456. * we initialize the first row in the rate grid.
  457. * values are period (in clock cycles) of timer
  458. */
  459. unsigned period = clock / rate;
  460. he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
  461. rate -= delta;
  462. }
  463. if (he_is622(he_dev)) {
  464. /* table 5.2 (4 cells per lbuf) */
  465. he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
  466. he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
  467. he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
  468. he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
  469. he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
  470. /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
  471. he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
  472. he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
  473. he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
  474. he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
  475. he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
  476. he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
  477. he_writel_mbox(he_dev, 0x4680, CS_RTATR);
  478. /* table 5.8 */
  479. he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
  480. he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
  481. he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
  482. he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
  483. he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
  484. he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
  485. /* table 5.9 */
  486. he_writel_mbox(he_dev, 0x5, CS_OTPPER);
  487. he_writel_mbox(he_dev, 0x14, CS_OTWPER);
  488. } else {
  489. /* table 5.1 (4 cells per lbuf) */
  490. he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
  491. he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
  492. he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
  493. he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
  494. he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
  495. /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
  496. he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
  497. he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
  498. he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
  499. he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
  500. he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
  501. he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
  502. he_writel_mbox(he_dev, 0x4680, CS_RTATR);
  503. /* table 5.8 */
  504. he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
  505. he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
  506. he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
  507. he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
  508. he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
  509. he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
  510. /* table 5.9 */
  511. he_writel_mbox(he_dev, 0x6, CS_OTPPER);
  512. he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
  513. }
  514. he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
  515. for (reg = 0; reg < 0x8; ++reg)
  516. he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
  517. }
  518. static int __devinit
  519. he_init_cs_block_rcm(struct he_dev *he_dev)
  520. {
  521. unsigned (*rategrid)[16][16];
  522. unsigned rate, delta;
  523. int i, j, reg;
  524. unsigned rate_atmf, exp, man;
  525. unsigned long long rate_cps;
  526. int mult, buf, buf_limit = 4;
  527. rategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);
  528. if (!rategrid)
  529. return -ENOMEM;
  530. /* initialize rate grid group table */
  531. for (reg = 0x0; reg < 0xff; ++reg)
  532. he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
  533. /* initialize rate controller groups */
  534. for (reg = 0x100; reg < 0x1ff; ++reg)
  535. he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
  536. /* initialize tNrm lookup table */
  537. /* the manual makes reference to a routine in a sample driver
  538. for proper configuration; fortunately, we only need this
  539. in order to support abr connection */
  540. /* initialize rate to group table */
  541. rate = he_dev->atm_dev->link_rate;
  542. delta = rate / 32;
  543. /*
  544. * 2.4 transmit internal functions
  545. *
  546. * we construct a copy of the rate grid used by the scheduler
  547. * in order to construct the rate to group table below
  548. */
  549. for (j = 0; j < 16; j++) {
  550. (*rategrid)[0][j] = rate;
  551. rate -= delta;
  552. }
  553. for (i = 1; i < 16; i++)
  554. for (j = 0; j < 16; j++)
  555. if (i > 14)
  556. (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;
  557. else
  558. (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;
  559. /*
  560. * 2.4 transmit internal function
  561. *
  562. * this table maps the upper 5 bits of exponent and mantissa
  563. * of the atm forum representation of the rate into an index
  564. * on rate grid
  565. */
  566. rate_atmf = 0;
  567. while (rate_atmf < 0x400) {
  568. man = (rate_atmf & 0x1f) << 4;
  569. exp = rate_atmf >> 5;
  570. /*
  571. instead of '/ 512', use '>> 9' to prevent a call
  572. to divdu3 on x86 platforms
  573. */
  574. rate_cps = (unsigned long long) (1 << exp) * (man + 512) >> 9;
  575. if (rate_cps < 10)
  576. rate_cps = 10; /* 2.2.1 minimum payload rate is 10 cps */
  577. for (i = 255; i > 0; i--)
  578. if ((*rategrid)[i/16][i%16] >= rate_cps)
  579. break; /* pick nearest rate instead? */
  580. /*
  581. * each table entry is 16 bits: (rate grid index (8 bits)
  582. * and a buffer limit (8 bits)
  583. * there are two table entries in each 32-bit register
  584. */
  585. #ifdef notdef
  586. buf = rate_cps * he_dev->tx_numbuffs /
  587. (he_dev->atm_dev->link_rate * 2);
  588. #else
  589. /* this is pretty, but avoids _divdu3 and is mostly correct */
  590. mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
  591. if (rate_cps > (272 * mult))
  592. buf = 4;
  593. else if (rate_cps > (204 * mult))
  594. buf = 3;
  595. else if (rate_cps > (136 * mult))
  596. buf = 2;
  597. else if (rate_cps > (68 * mult))
  598. buf = 1;
  599. else
  600. buf = 0;
  601. #endif
  602. if (buf > buf_limit)
  603. buf = buf_limit;
  604. reg = (reg << 16) | ((i << 8) | buf);
  605. #define RTGTBL_OFFSET 0x400
  606. if (rate_atmf & 0x1)
  607. he_writel_rcm(he_dev, reg,
  608. CONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));
  609. ++rate_atmf;
  610. }
  611. kfree(rategrid);
  612. return 0;
  613. }
  614. static int __devinit
  615. he_init_group(struct he_dev *he_dev, int group)
  616. {
  617. struct he_buff *heb, *next;
  618. dma_addr_t mapping;
  619. int i;
  620. he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
  621. he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
  622. he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
  623. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  624. G0_RBPS_BS + (group * 32));
  625. /* bitmap table */
  626. he_dev->rbpl_table = kmalloc(BITS_TO_LONGS(RBPL_TABLE_SIZE)
  627. * sizeof(unsigned long), GFP_KERNEL);
  628. if (!he_dev->rbpl_table) {
  629. hprintk("unable to allocate rbpl bitmap table\n");
  630. return -ENOMEM;
  631. }
  632. bitmap_zero(he_dev->rbpl_table, RBPL_TABLE_SIZE);
  633. /* rbpl_virt 64-bit pointers */
  634. he_dev->rbpl_virt = kmalloc(RBPL_TABLE_SIZE
  635. * sizeof(struct he_buff *), GFP_KERNEL);
  636. if (!he_dev->rbpl_virt) {
  637. hprintk("unable to allocate rbpl virt table\n");
  638. goto out_free_rbpl_table;
  639. }
  640. /* large buffer pool */
  641. he_dev->rbpl_pool = pci_pool_create("rbpl", he_dev->pci_dev,
  642. CONFIG_RBPL_BUFSIZE, 64, 0);
  643. if (he_dev->rbpl_pool == NULL) {
  644. hprintk("unable to create rbpl pool\n");
  645. goto out_free_rbpl_virt;
  646. }
  647. he_dev->rbpl_base = pci_alloc_consistent(he_dev->pci_dev,
  648. CONFIG_RBPL_SIZE * sizeof(struct he_rbp), &he_dev->rbpl_phys);
  649. if (he_dev->rbpl_base == NULL) {
  650. hprintk("failed to alloc rbpl_base\n");
  651. goto out_destroy_rbpl_pool;
  652. }
  653. memset(he_dev->rbpl_base, 0, CONFIG_RBPL_SIZE * sizeof(struct he_rbp));
  654. INIT_LIST_HEAD(&he_dev->rbpl_outstanding);
  655. for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
  656. heb = pci_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL|GFP_DMA, &mapping);
  657. if (!heb)
  658. goto out_free_rbpl;
  659. heb->mapping = mapping;
  660. list_add(&heb->entry, &he_dev->rbpl_outstanding);
  661. set_bit(i, he_dev->rbpl_table);
  662. he_dev->rbpl_virt[i] = heb;
  663. he_dev->rbpl_hint = i + 1;
  664. he_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;
  665. he_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);
  666. }
  667. he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
  668. he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
  669. he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
  670. G0_RBPL_T + (group * 32));
  671. he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
  672. G0_RBPL_BS + (group * 32));
  673. he_writel(he_dev,
  674. RBP_THRESH(CONFIG_RBPL_THRESH) |
  675. RBP_QSIZE(CONFIG_RBPL_SIZE - 1) |
  676. RBP_INT_ENB,
  677. G0_RBPL_QI + (group * 32));
  678. /* rx buffer ready queue */
  679. he_dev->rbrq_base = pci_alloc_consistent(he_dev->pci_dev,
  680. CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq), &he_dev->rbrq_phys);
  681. if (he_dev->rbrq_base == NULL) {
  682. hprintk("failed to allocate rbrq\n");
  683. goto out_free_rbpl;
  684. }
  685. memset(he_dev->rbrq_base, 0, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq));
  686. he_dev->rbrq_head = he_dev->rbrq_base;
  687. he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
  688. he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
  689. he_writel(he_dev,
  690. RBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),
  691. G0_RBRQ_Q + (group * 16));
  692. if (irq_coalesce) {
  693. hprintk("coalescing interrupts\n");
  694. he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
  695. G0_RBRQ_I + (group * 16));
  696. } else
  697. he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
  698. G0_RBRQ_I + (group * 16));
  699. /* tx buffer ready queue */
  700. he_dev->tbrq_base = pci_alloc_consistent(he_dev->pci_dev,
  701. CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq), &he_dev->tbrq_phys);
  702. if (he_dev->tbrq_base == NULL) {
  703. hprintk("failed to allocate tbrq\n");
  704. goto out_free_rbpq_base;
  705. }
  706. memset(he_dev->tbrq_base, 0, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq));
  707. he_dev->tbrq_head = he_dev->tbrq_base;
  708. he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
  709. he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
  710. he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
  711. he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
  712. return 0;
  713. out_free_rbpq_base:
  714. pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE *
  715. sizeof(struct he_rbrq), he_dev->rbrq_base,
  716. he_dev->rbrq_phys);
  717. out_free_rbpl:
  718. list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
  719. pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
  720. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE *
  721. sizeof(struct he_rbp), he_dev->rbpl_base,
  722. he_dev->rbpl_phys);
  723. out_destroy_rbpl_pool:
  724. pci_pool_destroy(he_dev->rbpl_pool);
  725. out_free_rbpl_virt:
  726. kfree(he_dev->rbpl_virt);
  727. out_free_rbpl_table:
  728. kfree(he_dev->rbpl_table);
  729. return -ENOMEM;
  730. }
  731. static int __devinit
  732. he_init_irq(struct he_dev *he_dev)
  733. {
  734. int i;
  735. /* 2.9.3.5 tail offset for each interrupt queue is located after the
  736. end of the interrupt queue */
  737. he_dev->irq_base = pci_alloc_consistent(he_dev->pci_dev,
  738. (CONFIG_IRQ_SIZE+1) * sizeof(struct he_irq), &he_dev->irq_phys);
  739. if (he_dev->irq_base == NULL) {
  740. hprintk("failed to allocate irq\n");
  741. return -ENOMEM;
  742. }
  743. he_dev->irq_tailoffset = (unsigned *)
  744. &he_dev->irq_base[CONFIG_IRQ_SIZE];
  745. *he_dev->irq_tailoffset = 0;
  746. he_dev->irq_head = he_dev->irq_base;
  747. he_dev->irq_tail = he_dev->irq_base;
  748. for (i = 0; i < CONFIG_IRQ_SIZE; ++i)
  749. he_dev->irq_base[i].isw = ITYPE_INVALID;
  750. he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
  751. he_writel(he_dev,
  752. IRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),
  753. IRQ0_HEAD);
  754. he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
  755. he_writel(he_dev, 0x0, IRQ0_DATA);
  756. he_writel(he_dev, 0x0, IRQ1_BASE);
  757. he_writel(he_dev, 0x0, IRQ1_HEAD);
  758. he_writel(he_dev, 0x0, IRQ1_CNTL);
  759. he_writel(he_dev, 0x0, IRQ1_DATA);
  760. he_writel(he_dev, 0x0, IRQ2_BASE);
  761. he_writel(he_dev, 0x0, IRQ2_HEAD);
  762. he_writel(he_dev, 0x0, IRQ2_CNTL);
  763. he_writel(he_dev, 0x0, IRQ2_DATA);
  764. he_writel(he_dev, 0x0, IRQ3_BASE);
  765. he_writel(he_dev, 0x0, IRQ3_HEAD);
  766. he_writel(he_dev, 0x0, IRQ3_CNTL);
  767. he_writel(he_dev, 0x0, IRQ3_DATA);
  768. /* 2.9.3.2 interrupt queue mapping registers */
  769. he_writel(he_dev, 0x0, GRP_10_MAP);
  770. he_writel(he_dev, 0x0, GRP_32_MAP);
  771. he_writel(he_dev, 0x0, GRP_54_MAP);
  772. he_writel(he_dev, 0x0, GRP_76_MAP);
  773. if (request_irq(he_dev->pci_dev->irq,
  774. he_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {
  775. hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
  776. return -EINVAL;
  777. }
  778. he_dev->irq = he_dev->pci_dev->irq;
  779. return 0;
  780. }
  781. static int __devinit
  782. he_start(struct atm_dev *dev)
  783. {
  784. struct he_dev *he_dev;
  785. struct pci_dev *pci_dev;
  786. unsigned long membase;
  787. u16 command;
  788. u32 gen_cntl_0, host_cntl, lb_swap;
  789. u8 cache_size, timer;
  790. unsigned err;
  791. unsigned int status, reg;
  792. int i, group;
  793. he_dev = HE_DEV(dev);
  794. pci_dev = he_dev->pci_dev;
  795. membase = pci_resource_start(pci_dev, 0);
  796. HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq);
  797. /*
  798. * pci bus controller initialization
  799. */
  800. /* 4.3 pci bus controller-specific initialization */
  801. if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {
  802. hprintk("can't read GEN_CNTL_0\n");
  803. return -EINVAL;
  804. }
  805. gen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);
  806. if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {
  807. hprintk("can't write GEN_CNTL_0.\n");
  808. return -EINVAL;
  809. }
  810. if (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) {
  811. hprintk("can't read PCI_COMMAND.\n");
  812. return -EINVAL;
  813. }
  814. command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
  815. if (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) {
  816. hprintk("can't enable memory.\n");
  817. return -EINVAL;
  818. }
  819. if (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {
  820. hprintk("can't read cache line size?\n");
  821. return -EINVAL;
  822. }
  823. if (cache_size < 16) {
  824. cache_size = 16;
  825. if (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))
  826. hprintk("can't set cache line size to %d\n", cache_size);
  827. }
  828. if (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {
  829. hprintk("can't read latency timer?\n");
  830. return -EINVAL;
  831. }
  832. /* from table 3.9
  833. *
  834. * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE
  835. *
  836. * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]
  837. * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]
  838. *
  839. */
  840. #define LAT_TIMER 209
  841. if (timer < LAT_TIMER) {
  842. HPRINTK("latency timer was %d, setting to %d\n", timer, LAT_TIMER);
  843. timer = LAT_TIMER;
  844. if (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))
  845. hprintk("can't set latency timer to %d\n", timer);
  846. }
  847. if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {
  848. hprintk("can't set up page mapping\n");
  849. return -EINVAL;
  850. }
  851. /* 4.4 card reset */
  852. he_writel(he_dev, 0x0, RESET_CNTL);
  853. he_writel(he_dev, 0xff, RESET_CNTL);
  854. udelay(16*1000); /* 16 ms */
  855. status = he_readl(he_dev, RESET_CNTL);
  856. if ((status & BOARD_RST_STATUS) == 0) {
  857. hprintk("reset failed\n");
  858. return -EINVAL;
  859. }
  860. /* 4.5 set bus width */
  861. host_cntl = he_readl(he_dev, HOST_CNTL);
  862. if (host_cntl & PCI_BUS_SIZE64)
  863. gen_cntl_0 |= ENBL_64;
  864. else
  865. gen_cntl_0 &= ~ENBL_64;
  866. if (disable64 == 1) {
  867. hprintk("disabling 64-bit pci bus transfers\n");
  868. gen_cntl_0 &= ~ENBL_64;
  869. }
  870. if (gen_cntl_0 & ENBL_64)
  871. hprintk("64-bit transfers enabled\n");
  872. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  873. /* 4.7 read prom contents */
  874. for (i = 0; i < PROD_ID_LEN; ++i)
  875. he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);
  876. he_dev->media = read_prom_byte(he_dev, MEDIA);
  877. for (i = 0; i < 6; ++i)
  878. dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);
  879. hprintk("%s%s, %x:%x:%x:%x:%x:%x\n",
  880. he_dev->prod_id,
  881. he_dev->media & 0x40 ? "SM" : "MM",
  882. dev->esi[0],
  883. dev->esi[1],
  884. dev->esi[2],
  885. dev->esi[3],
  886. dev->esi[4],
  887. dev->esi[5]);
  888. he_dev->atm_dev->link_rate = he_is622(he_dev) ?
  889. ATM_OC12_PCR : ATM_OC3_PCR;
  890. /* 4.6 set host endianess */
  891. lb_swap = he_readl(he_dev, LB_SWAP);
  892. if (he_is622(he_dev))
  893. lb_swap &= ~XFER_SIZE; /* 4 cells */
  894. else
  895. lb_swap |= XFER_SIZE; /* 8 cells */
  896. #ifdef __BIG_ENDIAN
  897. lb_swap |= DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST;
  898. #else
  899. lb_swap &= ~(DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST |
  900. DATA_WR_SWAP | DATA_RD_SWAP | DESC_RD_SWAP);
  901. #endif /* __BIG_ENDIAN */
  902. he_writel(he_dev, lb_swap, LB_SWAP);
  903. /* 4.8 sdram controller initialization */
  904. he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
  905. /* 4.9 initialize rnum value */
  906. lb_swap |= SWAP_RNUM_MAX(0xf);
  907. he_writel(he_dev, lb_swap, LB_SWAP);
  908. /* 4.10 initialize the interrupt queues */
  909. if ((err = he_init_irq(he_dev)) != 0)
  910. return err;
  911. /* 4.11 enable pci bus controller state machines */
  912. host_cntl |= (OUTFF_ENB | CMDFF_ENB |
  913. QUICK_RD_RETRY | QUICK_WR_RETRY | PERR_INT_ENB);
  914. he_writel(he_dev, host_cntl, HOST_CNTL);
  915. gen_cntl_0 |= INT_PROC_ENBL|INIT_ENB;
  916. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  917. /*
  918. * atm network controller initialization
  919. */
  920. /* 5.1.1 generic configuration state */
  921. /*
  922. * local (cell) buffer memory map
  923. *
  924. * HE155 HE622
  925. *
  926. * 0 ____________1023 bytes 0 _______________________2047 bytes
  927. * | | | | |
  928. * | utility | | rx0 | |
  929. * 5|____________| 255|___________________| u |
  930. * 6| | 256| | t |
  931. * | | | | i |
  932. * | rx0 | row | tx | l |
  933. * | | | | i |
  934. * | | 767|___________________| t |
  935. * 517|____________| 768| | y |
  936. * row 518| | | rx1 | |
  937. * | | 1023|___________________|___|
  938. * | |
  939. * | tx |
  940. * | |
  941. * | |
  942. * 1535|____________|
  943. * 1536| |
  944. * | rx1 |
  945. * 2047|____________|
  946. *
  947. */
  948. /* total 4096 connections */
  949. he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
  950. he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;
  951. if (nvpibits != -1 && nvcibits != -1 && nvpibits+nvcibits != HE_MAXCIDBITS) {
  952. hprintk("nvpibits + nvcibits != %d\n", HE_MAXCIDBITS);
  953. return -ENODEV;
  954. }
  955. if (nvpibits != -1) {
  956. he_dev->vpibits = nvpibits;
  957. he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
  958. }
  959. if (nvcibits != -1) {
  960. he_dev->vcibits = nvcibits;
  961. he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
  962. }
  963. if (he_is622(he_dev)) {
  964. he_dev->cells_per_row = 40;
  965. he_dev->bytes_per_row = 2048;
  966. he_dev->r0_numrows = 256;
  967. he_dev->tx_numrows = 512;
  968. he_dev->r1_numrows = 256;
  969. he_dev->r0_startrow = 0;
  970. he_dev->tx_startrow = 256;
  971. he_dev->r1_startrow = 768;
  972. } else {
  973. he_dev->cells_per_row = 20;
  974. he_dev->bytes_per_row = 1024;
  975. he_dev->r0_numrows = 512;
  976. he_dev->tx_numrows = 1018;
  977. he_dev->r1_numrows = 512;
  978. he_dev->r0_startrow = 6;
  979. he_dev->tx_startrow = 518;
  980. he_dev->r1_startrow = 1536;
  981. }
  982. he_dev->cells_per_lbuf = 4;
  983. he_dev->buffer_limit = 4;
  984. he_dev->r0_numbuffs = he_dev->r0_numrows *
  985. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  986. if (he_dev->r0_numbuffs > 2560)
  987. he_dev->r0_numbuffs = 2560;
  988. he_dev->r1_numbuffs = he_dev->r1_numrows *
  989. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  990. if (he_dev->r1_numbuffs > 2560)
  991. he_dev->r1_numbuffs = 2560;
  992. he_dev->tx_numbuffs = he_dev->tx_numrows *
  993. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  994. if (he_dev->tx_numbuffs > 5120)
  995. he_dev->tx_numbuffs = 5120;
  996. /* 5.1.2 configure hardware dependent registers */
  997. he_writel(he_dev,
  998. SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |
  999. RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |
  1000. (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
  1001. (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
  1002. LBARB);
  1003. he_writel(he_dev, BANK_ON |
  1004. (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
  1005. SDRAMCON);
  1006. he_writel(he_dev,
  1007. (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
  1008. RM_RW_WAIT(1), RCMCONFIG);
  1009. he_writel(he_dev,
  1010. (he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
  1011. TM_RW_WAIT(1), TCMCONFIG);
  1012. he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
  1013. he_writel(he_dev,
  1014. (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
  1015. (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
  1016. RX_VALVP(he_dev->vpibits) |
  1017. RX_VALVC(he_dev->vcibits), RC_CONFIG);
  1018. he_writel(he_dev, DRF_THRESH(0x20) |
  1019. (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
  1020. TX_VCI_MASK(he_dev->vcibits) |
  1021. LBFREE_CNT(he_dev->tx_numbuffs), TX_CONFIG);
  1022. he_writel(he_dev, 0x0, TXAAL5_PROTO);
  1023. he_writel(he_dev, PHY_INT_ENB |
  1024. (he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
  1025. RH_CONFIG);
  1026. /* 5.1.3 initialize connection memory */
  1027. for (i = 0; i < TCM_MEM_SIZE; ++i)
  1028. he_writel_tcm(he_dev, 0, i);
  1029. for (i = 0; i < RCM_MEM_SIZE; ++i)
  1030. he_writel_rcm(he_dev, 0, i);
  1031. /*
  1032. * transmit connection memory map
  1033. *
  1034. * tx memory
  1035. * 0x0 ___________________
  1036. * | |
  1037. * | |
  1038. * | TSRa |
  1039. * | |
  1040. * | |
  1041. * 0x8000|___________________|
  1042. * | |
  1043. * | TSRb |
  1044. * 0xc000|___________________|
  1045. * | |
  1046. * | TSRc |
  1047. * 0xe000|___________________|
  1048. * | TSRd |
  1049. * 0xf000|___________________|
  1050. * | tmABR |
  1051. * 0x10000|___________________|
  1052. * | |
  1053. * | tmTPD |
  1054. * |___________________|
  1055. * | |
  1056. * ....
  1057. * 0x1ffff|___________________|
  1058. *
  1059. *
  1060. */
  1061. he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
  1062. he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
  1063. he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
  1064. he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
  1065. he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
  1066. /*
  1067. * receive connection memory map
  1068. *
  1069. * 0x0 ___________________
  1070. * | |
  1071. * | |
  1072. * | RSRa |
  1073. * | |
  1074. * | |
  1075. * 0x8000|___________________|
  1076. * | |
  1077. * | rx0/1 |
  1078. * | LBM | link lists of local
  1079. * | tx | buffer memory
  1080. * | |
  1081. * 0xd000|___________________|
  1082. * | |
  1083. * | rmABR |
  1084. * 0xe000|___________________|
  1085. * | |
  1086. * | RSRb |
  1087. * |___________________|
  1088. * | |
  1089. * ....
  1090. * 0xffff|___________________|
  1091. */
  1092. he_writel(he_dev, 0x08000, RCMLBM_BA);
  1093. he_writel(he_dev, 0x0e000, RCMRSRB_BA);
  1094. he_writel(he_dev, 0x0d800, RCMABR_BA);
  1095. /* 5.1.4 initialize local buffer free pools linked lists */
  1096. he_init_rx_lbfp0(he_dev);
  1097. he_init_rx_lbfp1(he_dev);
  1098. he_writel(he_dev, 0x0, RLBC_H);
  1099. he_writel(he_dev, 0x0, RLBC_T);
  1100. he_writel(he_dev, 0x0, RLBC_H2);
  1101. he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
  1102. he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
  1103. he_init_tx_lbfp(he_dev);
  1104. he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
  1105. /* 5.1.5 initialize intermediate receive queues */
  1106. if (he_is622(he_dev)) {
  1107. he_writel(he_dev, 0x000f, G0_INMQ_S);
  1108. he_writel(he_dev, 0x200f, G0_INMQ_L);
  1109. he_writel(he_dev, 0x001f, G1_INMQ_S);
  1110. he_writel(he_dev, 0x201f, G1_INMQ_L);
  1111. he_writel(he_dev, 0x002f, G2_INMQ_S);
  1112. he_writel(he_dev, 0x202f, G2_INMQ_L);
  1113. he_writel(he_dev, 0x003f, G3_INMQ_S);
  1114. he_writel(he_dev, 0x203f, G3_INMQ_L);
  1115. he_writel(he_dev, 0x004f, G4_INMQ_S);
  1116. he_writel(he_dev, 0x204f, G4_INMQ_L);
  1117. he_writel(he_dev, 0x005f, G5_INMQ_S);
  1118. he_writel(he_dev, 0x205f, G5_INMQ_L);
  1119. he_writel(he_dev, 0x006f, G6_INMQ_S);
  1120. he_writel(he_dev, 0x206f, G6_INMQ_L);
  1121. he_writel(he_dev, 0x007f, G7_INMQ_S);
  1122. he_writel(he_dev, 0x207f, G7_INMQ_L);
  1123. } else {
  1124. he_writel(he_dev, 0x0000, G0_INMQ_S);
  1125. he_writel(he_dev, 0x0008, G0_INMQ_L);
  1126. he_writel(he_dev, 0x0001, G1_INMQ_S);
  1127. he_writel(he_dev, 0x0009, G1_INMQ_L);
  1128. he_writel(he_dev, 0x0002, G2_INMQ_S);
  1129. he_writel(he_dev, 0x000a, G2_INMQ_L);
  1130. he_writel(he_dev, 0x0003, G3_INMQ_S);
  1131. he_writel(he_dev, 0x000b, G3_INMQ_L);
  1132. he_writel(he_dev, 0x0004, G4_INMQ_S);
  1133. he_writel(he_dev, 0x000c, G4_INMQ_L);
  1134. he_writel(he_dev, 0x0005, G5_INMQ_S);
  1135. he_writel(he_dev, 0x000d, G5_INMQ_L);
  1136. he_writel(he_dev, 0x0006, G6_INMQ_S);
  1137. he_writel(he_dev, 0x000e, G6_INMQ_L);
  1138. he_writel(he_dev, 0x0007, G7_INMQ_S);
  1139. he_writel(he_dev, 0x000f, G7_INMQ_L);
  1140. }
  1141. /* 5.1.6 application tunable parameters */
  1142. he_writel(he_dev, 0x0, MCC);
  1143. he_writel(he_dev, 0x0, OEC);
  1144. he_writel(he_dev, 0x0, DCC);
  1145. he_writel(he_dev, 0x0, CEC);
  1146. /* 5.1.7 cs block initialization */
  1147. he_init_cs_block(he_dev);
  1148. /* 5.1.8 cs block connection memory initialization */
  1149. if (he_init_cs_block_rcm(he_dev) < 0)
  1150. return -ENOMEM;
  1151. /* 5.1.10 initialize host structures */
  1152. he_init_tpdrq(he_dev);
  1153. he_dev->tpd_pool = pci_pool_create("tpd", he_dev->pci_dev,
  1154. sizeof(struct he_tpd), TPD_ALIGNMENT, 0);
  1155. if (he_dev->tpd_pool == NULL) {
  1156. hprintk("unable to create tpd pci_pool\n");
  1157. return -ENOMEM;
  1158. }
  1159. INIT_LIST_HEAD(&he_dev->outstanding_tpds);
  1160. if (he_init_group(he_dev, 0) != 0)
  1161. return -ENOMEM;
  1162. for (group = 1; group < HE_NUM_GROUPS; ++group) {
  1163. he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
  1164. he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
  1165. he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
  1166. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  1167. G0_RBPS_BS + (group * 32));
  1168. he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
  1169. he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
  1170. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  1171. G0_RBPL_QI + (group * 32));
  1172. he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
  1173. he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
  1174. he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
  1175. he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
  1176. G0_RBRQ_Q + (group * 16));
  1177. he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
  1178. he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
  1179. he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
  1180. he_writel(he_dev, TBRQ_THRESH(0x1),
  1181. G0_TBRQ_THRESH + (group * 16));
  1182. he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
  1183. }
  1184. /* host status page */
  1185. he_dev->hsp = pci_alloc_consistent(he_dev->pci_dev,
  1186. sizeof(struct he_hsp), &he_dev->hsp_phys);
  1187. if (he_dev->hsp == NULL) {
  1188. hprintk("failed to allocate host status page\n");
  1189. return -ENOMEM;
  1190. }
  1191. memset(he_dev->hsp, 0, sizeof(struct he_hsp));
  1192. he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
  1193. /* initialize framer */
  1194. #ifdef CONFIG_ATM_HE_USE_SUNI
  1195. if (he_isMM(he_dev))
  1196. suni_init(he_dev->atm_dev);
  1197. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
  1198. he_dev->atm_dev->phy->start(he_dev->atm_dev);
  1199. #endif /* CONFIG_ATM_HE_USE_SUNI */
  1200. if (sdh) {
  1201. /* this really should be in suni.c but for now... */
  1202. int val;
  1203. val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
  1204. val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT);
  1205. he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
  1206. he_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);
  1207. }
  1208. /* 5.1.12 enable transmit and receive */
  1209. reg = he_readl_mbox(he_dev, CS_ERCTL0);
  1210. reg |= TX_ENABLE|ER_ENABLE;
  1211. he_writel_mbox(he_dev, reg, CS_ERCTL0);
  1212. reg = he_readl(he_dev, RC_CONFIG);
  1213. reg |= RX_ENABLE;
  1214. he_writel(he_dev, reg, RC_CONFIG);
  1215. for (i = 0; i < HE_NUM_CS_STPER; ++i) {
  1216. he_dev->cs_stper[i].inuse = 0;
  1217. he_dev->cs_stper[i].pcr = -1;
  1218. }
  1219. he_dev->total_bw = 0;
  1220. /* atm linux initialization */
  1221. he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
  1222. he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;
  1223. he_dev->irq_peak = 0;
  1224. he_dev->rbrq_peak = 0;
  1225. he_dev->rbpl_peak = 0;
  1226. he_dev->tbrq_peak = 0;
  1227. HPRINTK("hell bent for leather!\n");
  1228. return 0;
  1229. }
  1230. static void
  1231. he_stop(struct he_dev *he_dev)
  1232. {
  1233. struct he_buff *heb, *next;
  1234. struct pci_dev *pci_dev;
  1235. u32 gen_cntl_0, reg;
  1236. u16 command;
  1237. pci_dev = he_dev->pci_dev;
  1238. /* disable interrupts */
  1239. if (he_dev->membase) {
  1240. pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0);
  1241. gen_cntl_0 &= ~(INT_PROC_ENBL | INIT_ENB);
  1242. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  1243. tasklet_disable(&he_dev->tasklet);
  1244. /* disable recv and transmit */
  1245. reg = he_readl_mbox(he_dev, CS_ERCTL0);
  1246. reg &= ~(TX_ENABLE|ER_ENABLE);
  1247. he_writel_mbox(he_dev, reg, CS_ERCTL0);
  1248. reg = he_readl(he_dev, RC_CONFIG);
  1249. reg &= ~(RX_ENABLE);
  1250. he_writel(he_dev, reg, RC_CONFIG);
  1251. }
  1252. #ifdef CONFIG_ATM_HE_USE_SUNI
  1253. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
  1254. he_dev->atm_dev->phy->stop(he_dev->atm_dev);
  1255. #endif /* CONFIG_ATM_HE_USE_SUNI */
  1256. if (he_dev->irq)
  1257. free_irq(he_dev->irq, he_dev);
  1258. if (he_dev->irq_base)
  1259. pci_free_consistent(he_dev->pci_dev, (CONFIG_IRQ_SIZE+1)
  1260. * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);
  1261. if (he_dev->hsp)
  1262. pci_free_consistent(he_dev->pci_dev, sizeof(struct he_hsp),
  1263. he_dev->hsp, he_dev->hsp_phys);
  1264. if (he_dev->rbpl_base) {
  1265. list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
  1266. pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
  1267. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
  1268. * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
  1269. }
  1270. kfree(he_dev->rbpl_virt);
  1271. kfree(he_dev->rbpl_table);
  1272. if (he_dev->rbpl_pool)
  1273. pci_pool_destroy(he_dev->rbpl_pool);
  1274. if (he_dev->rbrq_base)
  1275. pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
  1276. he_dev->rbrq_base, he_dev->rbrq_phys);
  1277. if (he_dev->tbrq_base)
  1278. pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
  1279. he_dev->tbrq_base, he_dev->tbrq_phys);
  1280. if (he_dev->tpdrq_base)
  1281. pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
  1282. he_dev->tpdrq_base, he_dev->tpdrq_phys);
  1283. if (he_dev->tpd_pool)
  1284. pci_pool_destroy(he_dev->tpd_pool);
  1285. if (he_dev->pci_dev) {
  1286. pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
  1287. command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  1288. pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
  1289. }
  1290. if (he_dev->membase)
  1291. iounmap(he_dev->membase);
  1292. }
  1293. static struct he_tpd *
  1294. __alloc_tpd(struct he_dev *he_dev)
  1295. {
  1296. struct he_tpd *tpd;
  1297. dma_addr_t mapping;
  1298. tpd = pci_pool_alloc(he_dev->tpd_pool, GFP_ATOMIC|GFP_DMA, &mapping);
  1299. if (tpd == NULL)
  1300. return NULL;
  1301. tpd->status = TPD_ADDR(mapping);
  1302. tpd->reserved = 0;
  1303. tpd->iovec[0].addr = 0; tpd->iovec[0].len = 0;
  1304. tpd->iovec[1].addr = 0; tpd->iovec[1].len = 0;
  1305. tpd->iovec[2].addr = 0; tpd->iovec[2].len = 0;
  1306. return tpd;
  1307. }
  1308. #define AAL5_LEN(buf,len) \
  1309. ((((unsigned char *)(buf))[(len)-6] << 8) | \
  1310. (((unsigned char *)(buf))[(len)-5]))
  1311. /* 2.10.1.2 receive
  1312. *
  1313. * aal5 packets can optionally return the tcp checksum in the lower
  1314. * 16 bits of the crc (RSR0_TCP_CKSUM)
  1315. */
  1316. #define TCP_CKSUM(buf,len) \
  1317. ((((unsigned char *)(buf))[(len)-2] << 8) | \
  1318. (((unsigned char *)(buf))[(len-1)]))
  1319. static int
  1320. he_service_rbrq(struct he_dev *he_dev, int group)
  1321. {
  1322. struct he_rbrq *rbrq_tail = (struct he_rbrq *)
  1323. ((unsigned long)he_dev->rbrq_base |
  1324. he_dev->hsp->group[group].rbrq_tail);
  1325. unsigned cid, lastcid = -1;
  1326. struct sk_buff *skb;
  1327. struct atm_vcc *vcc = NULL;
  1328. struct he_vcc *he_vcc;
  1329. struct he_buff *heb, *next;
  1330. int i;
  1331. int pdus_assembled = 0;
  1332. int updated = 0;
  1333. read_lock(&vcc_sklist_lock);
  1334. while (he_dev->rbrq_head != rbrq_tail) {
  1335. ++updated;
  1336. HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n",
  1337. he_dev->rbrq_head, group,
  1338. RBRQ_ADDR(he_dev->rbrq_head),
  1339. RBRQ_BUFLEN(he_dev->rbrq_head),
  1340. RBRQ_CID(he_dev->rbrq_head),
  1341. RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
  1342. RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
  1343. RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
  1344. RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
  1345. RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
  1346. RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");
  1347. i = RBRQ_ADDR(he_dev->rbrq_head) >> RBP_IDX_OFFSET;
  1348. heb = he_dev->rbpl_virt[i];
  1349. cid = RBRQ_CID(he_dev->rbrq_head);
  1350. if (cid != lastcid)
  1351. vcc = __find_vcc(he_dev, cid);
  1352. lastcid = cid;
  1353. if (vcc == NULL || (he_vcc = HE_VCC(vcc)) == NULL) {
  1354. hprintk("vcc/he_vcc == NULL (cid 0x%x)\n", cid);
  1355. if (!RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
  1356. clear_bit(i, he_dev->rbpl_table);
  1357. list_del(&heb->entry);
  1358. pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
  1359. }
  1360. goto next_rbrq_entry;
  1361. }
  1362. if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
  1363. hprintk("HBUF_ERR! (cid 0x%x)\n", cid);
  1364. atomic_inc(&vcc->stats->rx_drop);
  1365. goto return_host_buffers;
  1366. }
  1367. heb->len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
  1368. clear_bit(i, he_dev->rbpl_table);
  1369. list_move_tail(&heb->entry, &he_vcc->buffers);
  1370. he_vcc->pdu_len += heb->len;
  1371. if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
  1372. lastcid = -1;
  1373. HPRINTK("wake_up rx_waitq (cid 0x%x)\n", cid);
  1374. wake_up(&he_vcc->rx_waitq);
  1375. goto return_host_buffers;
  1376. }
  1377. if (!RBRQ_END_PDU(he_dev->rbrq_head))
  1378. goto next_rbrq_entry;
  1379. if (RBRQ_LEN_ERR(he_dev->rbrq_head)
  1380. || RBRQ_CRC_ERR(he_dev->rbrq_head)) {
  1381. HPRINTK("%s%s (%d.%d)\n",
  1382. RBRQ_CRC_ERR(he_dev->rbrq_head)
  1383. ? "CRC_ERR " : "",
  1384. RBRQ_LEN_ERR(he_dev->rbrq_head)
  1385. ? "LEN_ERR" : "",
  1386. vcc->vpi, vcc->vci);
  1387. atomic_inc(&vcc->stats->rx_err);
  1388. goto return_host_buffers;
  1389. }
  1390. skb = atm_alloc_charge(vcc, he_vcc->pdu_len + rx_skb_reserve,
  1391. GFP_ATOMIC);
  1392. if (!skb) {
  1393. HPRINTK("charge failed (%d.%d)\n", vcc->vpi, vcc->vci);
  1394. goto return_host_buffers;
  1395. }
  1396. if (rx_skb_reserve > 0)
  1397. skb_reserve(skb, rx_skb_reserve);
  1398. __net_timestamp(skb);
  1399. list_for_each_entry(heb, &he_vcc->buffers, entry)
  1400. memcpy(skb_put(skb, heb->len), &heb->data, heb->len);
  1401. switch (vcc->qos.aal) {
  1402. case ATM_AAL0:
  1403. /* 2.10.1.5 raw cell receive */
  1404. skb->len = ATM_AAL0_SDU;
  1405. skb_set_tail_pointer(skb, skb->len);
  1406. break;
  1407. case ATM_AAL5:
  1408. /* 2.10.1.2 aal5 receive */
  1409. skb->len = AAL5_LEN(skb->data, he_vcc->pdu_len);
  1410. skb_set_tail_pointer(skb, skb->len);
  1411. #ifdef USE_CHECKSUM_HW
  1412. if (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) {
  1413. skb->ip_summed = CHECKSUM_COMPLETE;
  1414. skb->csum = TCP_CKSUM(skb->data,
  1415. he_vcc->pdu_len);
  1416. }
  1417. #endif
  1418. break;
  1419. }
  1420. #ifdef should_never_happen
  1421. if (skb->len > vcc->qos.rxtp.max_sdu)
  1422. hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\n", skb->len, vcc->qos.rxtp.max_sdu, cid);
  1423. #endif
  1424. #ifdef notdef
  1425. ATM_SKB(skb)->vcc = vcc;
  1426. #endif
  1427. spin_unlock(&he_dev->global_lock);
  1428. vcc->push(vcc, skb);
  1429. spin_lock(&he_dev->global_lock);
  1430. atomic_inc(&vcc->stats->rx);
  1431. return_host_buffers:
  1432. ++pdus_assembled;
  1433. list_for_each_entry_safe(heb, next, &he_vcc->buffers, entry)
  1434. pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
  1435. INIT_LIST_HEAD(&he_vcc->buffers);
  1436. he_vcc->pdu_len = 0;
  1437. next_rbrq_entry:
  1438. he_dev->rbrq_head = (struct he_rbrq *)
  1439. ((unsigned long) he_dev->rbrq_base |
  1440. RBRQ_MASK(he_dev->rbrq_head + 1));
  1441. }
  1442. read_unlock(&vcc_sklist_lock);
  1443. if (updated) {
  1444. if (updated > he_dev->rbrq_peak)
  1445. he_dev->rbrq_peak = updated;
  1446. he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
  1447. G0_RBRQ_H + (group * 16));
  1448. }
  1449. return pdus_assembled;
  1450. }
  1451. static void
  1452. he_service_tbrq(struct he_dev *he_dev, int group)
  1453. {
  1454. struct he_tbrq *tbrq_tail = (struct he_tbrq *)
  1455. ((unsigned long)he_dev->tbrq_base |
  1456. he_dev->hsp->group[group].tbrq_tail);
  1457. struct he_tpd *tpd;
  1458. int slot, updated = 0;
  1459. struct he_tpd *__tpd;
  1460. /* 2.1.6 transmit buffer return queue */
  1461. while (he_dev->tbrq_head != tbrq_tail) {
  1462. ++updated;
  1463. HPRINTK("tbrq%d 0x%x%s%s\n",
  1464. group,
  1465. TBRQ_TPD(he_dev->tbrq_head),
  1466. TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
  1467. TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
  1468. tpd = NULL;
  1469. list_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {
  1470. if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
  1471. tpd = __tpd;
  1472. list_del(&__tpd->entry);
  1473. break;
  1474. }
  1475. }
  1476. if (tpd == NULL) {
  1477. hprintk("unable to locate tpd for dma buffer %x\n",
  1478. TBRQ_TPD(he_dev->tbrq_head));
  1479. goto next_tbrq_entry;
  1480. }
  1481. if (TBRQ_EOS(he_dev->tbrq_head)) {
  1482. HPRINTK("wake_up(tx_waitq) cid 0x%x\n",
  1483. he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
  1484. if (tpd->vcc)
  1485. wake_up(&HE_VCC(tpd->vcc)->tx_waitq);
  1486. goto next_tbrq_entry;
  1487. }
  1488. for (slot = 0; slot < TPD_MAXIOV; ++slot) {
  1489. if (tpd->iovec[slot].addr)
  1490. pci_unmap_single(he_dev->pci_dev,
  1491. tpd->iovec[slot].addr,
  1492. tpd->iovec[slot].len & TPD_LEN_MASK,
  1493. PCI_DMA_TODEVICE);
  1494. if (tpd->iovec[slot].len & TPD_LST)
  1495. break;
  1496. }
  1497. if (tpd->skb) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
  1498. if (tpd->vcc && tpd->vcc->pop)
  1499. tpd->vcc->pop(tpd->vcc, tpd->skb);
  1500. else
  1501. dev_kfree_skb_any(tpd->skb);
  1502. }
  1503. next_tbrq_entry:
  1504. if (tpd)
  1505. pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
  1506. he_dev->tbrq_head = (struct he_tbrq *)
  1507. ((unsigned long) he_dev->tbrq_base |
  1508. TBRQ_MASK(he_dev->tbrq_head + 1));
  1509. }
  1510. if (updated) {
  1511. if (updated > he_dev->tbrq_peak)
  1512. he_dev->tbrq_peak = updated;
  1513. he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
  1514. G0_TBRQ_H + (group * 16));
  1515. }
  1516. }
  1517. static void
  1518. he_service_rbpl(struct he_dev *he_dev, int group)
  1519. {
  1520. struct he_rbp *new_tail;
  1521. struct he_rbp *rbpl_head;
  1522. struct he_buff *heb;
  1523. dma_addr_t mapping;
  1524. int i;
  1525. int moved = 0;
  1526. rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
  1527. RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
  1528. for (;;) {
  1529. new_tail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
  1530. RBPL_MASK(he_dev->rbpl_tail+1));
  1531. /* table 3.42 -- rbpl_tail should never be set to rbpl_head */
  1532. if (new_tail == rbpl_head)
  1533. break;
  1534. i = find_next_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE, he_dev->rbpl_hint);
  1535. if (i > (RBPL_TABLE_SIZE - 1)) {
  1536. i = find_first_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE);
  1537. if (i > (RBPL_TABLE_SIZE - 1))
  1538. break;
  1539. }
  1540. he_dev->rbpl_hint = i + 1;
  1541. heb = pci_pool_alloc(he_dev->rbpl_pool, GFP_ATOMIC|GFP_DMA, &mapping);
  1542. if (!heb)
  1543. break;
  1544. heb->mapping = mapping;
  1545. list_add(&heb->entry, &he_dev->rbpl_outstanding);
  1546. he_dev->rbpl_virt[i] = heb;
  1547. set_bit(i, he_dev->rbpl_table);
  1548. new_tail->idx = i << RBP_IDX_OFFSET;
  1549. new_tail->phys = mapping + offsetof(struct he_buff, data);
  1550. he_dev->rbpl_tail = new_tail;
  1551. ++moved;
  1552. }
  1553. if (moved)
  1554. he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
  1555. }
  1556. static void
  1557. he_tasklet(unsigned long data)
  1558. {
  1559. unsigned long flags;
  1560. struct he_dev *he_dev = (struct he_dev *) data;
  1561. int group, type;
  1562. int updated = 0;
  1563. HPRINTK("tasklet (0x%lx)\n", data);
  1564. spin_lock_irqsave(&he_dev->global_lock, flags);
  1565. while (he_dev->irq_head != he_dev->irq_tail) {
  1566. ++updated;
  1567. type = ITYPE_TYPE(he_dev->irq_head->isw);
  1568. group = ITYPE_GROUP(he_dev->irq_head->isw);
  1569. switch (type) {
  1570. case ITYPE_RBRQ_THRESH:
  1571. HPRINTK("rbrq%d threshold\n", group);
  1572. /* fall through */
  1573. case ITYPE_RBRQ_TIMER:
  1574. if (he_service_rbrq(he_dev, group))
  1575. he_service_rbpl(he_dev, group);
  1576. break;
  1577. case ITYPE_TBRQ_THRESH:
  1578. HPRINTK("tbrq%d threshold\n", group);
  1579. /* fall through */
  1580. case ITYPE_TPD_COMPLETE:
  1581. he_service_tbrq(he_dev, group);
  1582. break;
  1583. case ITYPE_RBPL_THRESH:
  1584. he_service_rbpl(he_dev, group);
  1585. break;
  1586. case ITYPE_RBPS_THRESH:
  1587. /* shouldn't happen unless small buffers enabled */
  1588. break;
  1589. case ITYPE_PHY:
  1590. HPRINTK("phy interrupt\n");
  1591. #ifdef CONFIG_ATM_HE_USE_SUNI
  1592. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1593. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
  1594. he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
  1595. spin_lock_irqsave(&he_dev->global_lock, flags);
  1596. #endif
  1597. break;
  1598. case ITYPE_OTHER:
  1599. switch (type|group) {
  1600. case ITYPE_PARITY:
  1601. hprintk("parity error\n");
  1602. break;
  1603. case ITYPE_ABORT:
  1604. hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
  1605. break;
  1606. }
  1607. break;
  1608. case ITYPE_TYPE(ITYPE_INVALID):
  1609. /* see 8.1.1 -- check all queues */
  1610. HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
  1611. he_service_rbrq(he_dev, 0);
  1612. he_service_rbpl(he_dev, 0);
  1613. he_service_tbrq(he_dev, 0);
  1614. break;
  1615. default:
  1616. hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
  1617. }
  1618. he_dev->irq_head->isw = ITYPE_INVALID;
  1619. he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
  1620. }
  1621. if (updated) {
  1622. if (updated > he_dev->irq_peak)
  1623. he_dev->irq_peak = updated;
  1624. he_writel(he_dev,
  1625. IRQ_SIZE(CONFIG_IRQ_SIZE) |
  1626. IRQ_THRESH(CONFIG_IRQ_THRESH) |
  1627. IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
  1628. (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
  1629. }
  1630. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1631. }
  1632. static irqreturn_t
  1633. he_irq_handler(int irq, void *dev_id)
  1634. {
  1635. unsigned long flags;
  1636. struct he_dev *he_dev = (struct he_dev * )dev_id;
  1637. int handled = 0;
  1638. if (he_dev == NULL)
  1639. return IRQ_NONE;
  1640. spin_lock_irqsave(&he_dev->global_lock, flags);
  1641. he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
  1642. (*he_dev->irq_tailoffset << 2));
  1643. if (he_dev->irq_tail == he_dev->irq_head) {
  1644. HPRINTK("tailoffset not updated?\n");
  1645. he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
  1646. ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
  1647. (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
  1648. }
  1649. #ifdef DEBUG
  1650. if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
  1651. hprintk("spurious (or shared) interrupt?\n");
  1652. #endif
  1653. if (he_dev->irq_head != he_dev->irq_tail) {
  1654. handled = 1;
  1655. tasklet_schedule(&he_dev->tasklet);
  1656. he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
  1657. (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
  1658. }
  1659. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1660. return IRQ_RETVAL(handled);
  1661. }
  1662. static __inline__ void
  1663. __enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
  1664. {
  1665. struct he_tpdrq *new_tail;
  1666. HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n",
  1667. tpd, cid, he_dev->tpdrq_tail);
  1668. /* new_tail = he_dev->tpdrq_tail; */
  1669. new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
  1670. TPDRQ_MASK(he_dev->tpdrq_tail+1));
  1671. /*
  1672. * check to see if we are about to set the tail == head
  1673. * if true, update the head pointer from the adapter
  1674. * to see if this is really the case (reading the queue
  1675. * head for every enqueue would be unnecessarily slow)
  1676. */
  1677. if (new_tail == he_dev->tpdrq_head) {
  1678. he_dev->tpdrq_head = (struct he_tpdrq *)
  1679. (((unsigned long)he_dev->tpdrq_base) |
  1680. TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
  1681. if (new_tail == he_dev->tpdrq_head) {
  1682. int slot;
  1683. hprintk("tpdrq full (cid 0x%x)\n", cid);
  1684. /*
  1685. * FIXME
  1686. * push tpd onto a transmit backlog queue
  1687. * after service_tbrq, service the backlog
  1688. * for now, we just drop the pdu
  1689. */
  1690. for (slot = 0; slot < TPD_MAXIOV; ++slot) {
  1691. if (tpd->iovec[slot].addr)
  1692. pci_unmap_single(he_dev->pci_dev,
  1693. tpd->iovec[slot].addr,
  1694. tpd->iovec[slot].len & TPD_LEN_MASK,
  1695. PCI_DMA_TODEVICE);
  1696. }
  1697. if (tpd->skb) {
  1698. if (tpd->vcc->pop)
  1699. tpd->vcc->pop(tpd->vcc, tpd->skb);
  1700. else
  1701. dev_kfree_skb_any(tpd->skb);
  1702. atomic_inc(&tpd->vcc->stats->tx_err);
  1703. }
  1704. pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
  1705. return;
  1706. }
  1707. }
  1708. /* 2.1.5 transmit packet descriptor ready queue */
  1709. list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
  1710. he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
  1711. he_dev->tpdrq_tail->cid = cid;
  1712. wmb();
  1713. he_dev->tpdrq_tail = new_tail;
  1714. he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
  1715. (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
  1716. }
  1717. static int
  1718. he_open(struct atm_vcc *vcc)
  1719. {
  1720. unsigned long flags;
  1721. struct he_dev *he_dev = HE_DEV(vcc->dev);
  1722. struct he_vcc *he_vcc;
  1723. int err = 0;
  1724. unsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock;
  1725. short vpi = vcc->vpi;
  1726. int vci = vcc->vci;
  1727. if (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)
  1728. return 0;
  1729. HPRINTK("open vcc %p %d.%d\n", vcc, vpi, vci);
  1730. set_bit(ATM_VF_ADDR, &vcc->flags);
  1731. cid = he_mkcid(he_dev, vpi, vci);
  1732. he_vcc = kmalloc(sizeof(struct he_vcc), GFP_ATOMIC);
  1733. if (he_vcc == NULL) {
  1734. hprintk("unable to allocate he_vcc during open\n");
  1735. return -ENOMEM;
  1736. }
  1737. INIT_LIST_HEAD(&he_vcc->buffers);
  1738. he_vcc->pdu_len = 0;
  1739. he_vcc->rc_index = -1;
  1740. init_waitqueue_head(&he_vcc->rx_waitq);
  1741. init_waitqueue_head(&he_vcc->tx_waitq);
  1742. vcc->dev_data = he_vcc;
  1743. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1744. int pcr_goal;
  1745. pcr_goal = atm_pcr_goal(&vcc->qos.txtp);
  1746. if (pcr_goal == 0)
  1747. pcr_goal = he_dev->atm_dev->link_rate;
  1748. if (pcr_goal < 0) /* means round down, technically */
  1749. pcr_goal = -pcr_goal;
  1750. HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid, pcr_goal);
  1751. switch (vcc->qos.aal) {
  1752. case ATM_AAL5:
  1753. tsr0_aal = TSR0_AAL5;
  1754. tsr4 = TSR4_AAL5;
  1755. break;
  1756. case ATM_AAL0:
  1757. tsr0_aal = TSR0_AAL0_SDU;
  1758. tsr4 = TSR4_AAL0_SDU;
  1759. break;
  1760. default:
  1761. err = -EINVAL;
  1762. goto open_failed;
  1763. }
  1764. spin_lock_irqsave(&he_dev->global_lock, flags);
  1765. tsr0 = he_readl_tsr0(he_dev, cid);
  1766. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1767. if (TSR0_CONN_STATE(tsr0) != 0) {
  1768. hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid, tsr0);
  1769. err = -EBUSY;
  1770. goto open_failed;
  1771. }
  1772. switch (vcc->qos.txtp.traffic_class) {
  1773. case ATM_UBR:
  1774. /* 2.3.3.1 open connection ubr */
  1775. tsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal |
  1776. TSR0_USE_WMIN | TSR0_UPDATE_GER;
  1777. break;
  1778. case ATM_CBR:
  1779. /* 2.3.3.2 open connection cbr */
  1780. /* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */
  1781. if ((he_dev->total_bw + pcr_goal)
  1782. > (he_dev->atm_dev->link_rate * 9 / 10))
  1783. {
  1784. err = -EBUSY;
  1785. goto open_failed;
  1786. }
  1787. spin_lock_irqsave(&he_dev->global_lock, flags); /* also protects he_dev->cs_stper[] */
  1788. /* find an unused cs_stper register */
  1789. for (reg = 0; reg < HE_NUM_CS_STPER; ++reg)
  1790. if (he_dev->cs_stper[reg].inuse == 0 ||
  1791. he_dev->cs_stper[reg].pcr == pcr_goal)
  1792. break;
  1793. if (reg == HE_NUM_CS_STPER) {
  1794. err = -EBUSY;
  1795. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1796. goto open_failed;
  1797. }
  1798. he_dev->total_bw += pcr_goal;
  1799. he_vcc->rc_index = reg;
  1800. ++he_dev->cs_stper[reg].inuse;
  1801. he_dev->cs_stper[reg].pcr = pcr_goal;
  1802. clock = he_is622(he_dev) ? 66667000 : 50000000;
  1803. period = clock / pcr_goal;
  1804. HPRINTK("rc_index = %d period = %d\n",
  1805. reg, period);
  1806. he_writel_mbox(he_dev, rate_to_atmf(period/2),
  1807. CS_STPER0 + reg);
  1808. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1809. tsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal |
  1810. TSR0_RC_INDEX(reg);
  1811. break;
  1812. default:
  1813. err = -EINVAL;
  1814. goto open_failed;
  1815. }
  1816. spin_lock_irqsave(&he_dev->global_lock, flags);
  1817. he_writel_tsr0(he_dev, tsr0, cid);
  1818. he_writel_tsr4(he_dev, tsr4 | 1, cid);
  1819. he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
  1820. TSR1_PCR(rate_to_atmf(pcr_goal)), cid);
  1821. he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
  1822. he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);
  1823. he_writel_tsr3(he_dev, 0x0, cid);
  1824. he_writel_tsr5(he_dev, 0x0, cid);
  1825. he_writel_tsr6(he_dev, 0x0, cid);
  1826. he_writel_tsr7(he_dev, 0x0, cid);
  1827. he_writel_tsr8(he_dev, 0x0, cid);
  1828. he_writel_tsr10(he_dev, 0x0, cid);
  1829. he_writel_tsr11(he_dev, 0x0, cid);
  1830. he_writel_tsr12(he_dev, 0x0, cid);
  1831. he_writel_tsr13(he_dev, 0x0, cid);
  1832. he_writel_tsr14(he_dev, 0x0, cid);
  1833. (void) he_readl_tsr0(he_dev, cid); /* flush posted writes */
  1834. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1835. }
  1836. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1837. unsigned aal;
  1838. HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid,
  1839. &HE_VCC(vcc)->rx_waitq);
  1840. switch (vcc->qos.aal) {
  1841. case ATM_AAL5:
  1842. aal = RSR0_AAL5;
  1843. break;
  1844. case ATM_AAL0:
  1845. aal = RSR0_RAWCELL;
  1846. break;
  1847. default:
  1848. err = -EINVAL;
  1849. goto open_failed;
  1850. }
  1851. spin_lock_irqsave(&he_dev->global_lock, flags);
  1852. rsr0 = he_readl_rsr0(he_dev, cid);
  1853. if (rsr0 & RSR0_OPEN_CONN) {
  1854. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1855. hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid, rsr0);
  1856. err = -EBUSY;
  1857. goto open_failed;
  1858. }
  1859. rsr1 = RSR1_GROUP(0) | RSR1_RBPL_ONLY;
  1860. rsr4 = RSR4_GROUP(0) | RSR4_RBPL_ONLY;
  1861. rsr0 = vcc->qos.rxtp.traffic_class == ATM_UBR ?
  1862. (RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0;
  1863. #ifdef USE_CHECKSUM_HW
  1864. if (vpi == 0 && vci >= ATM_NOT_RSV_VCI)
  1865. rsr0 |= RSR0_TCP_CKSUM;
  1866. #endif
  1867. he_writel_rsr4(he_dev, rsr4, cid);
  1868. he_writel_rsr1(he_dev, rsr1, cid);
  1869. /* 5.1.11 last parameter initialized should be
  1870. the open/closed indication in rsr0 */
  1871. he_writel_rsr0(he_dev,
  1872. rsr0 | RSR0_START_PDU | RSR0_OPEN_CONN | aal, cid);
  1873. (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
  1874. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1875. }
  1876. open_failed:
  1877. if (err) {
  1878. kfree(he_vcc);
  1879. clear_bit(ATM_VF_ADDR, &vcc->flags);
  1880. }
  1881. else
  1882. set_bit(ATM_VF_READY, &vcc->flags);
  1883. return err;
  1884. }
  1885. static void
  1886. he_close(struct atm_vcc *vcc)
  1887. {
  1888. unsigned long flags;
  1889. DECLARE_WAITQUEUE(wait, current);
  1890. struct he_dev *he_dev = HE_DEV(vcc->dev);
  1891. struct he_tpd *tpd;
  1892. unsigned cid;
  1893. struct he_vcc *he_vcc = HE_VCC(vcc);
  1894. #define MAX_RETRY 30
  1895. int retry = 0, sleep = 1, tx_inuse;
  1896. HPRINTK("close vcc %p %d.%d\n", vcc, vcc->vpi, vcc->vci);
  1897. clear_bit(ATM_VF_READY, &vcc->flags);
  1898. cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
  1899. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  1900. int timeout;
  1901. HPRINTK("close rx cid 0x%x\n", cid);
  1902. /* 2.7.2.2 close receive operation */
  1903. /* wait for previous close (if any) to finish */
  1904. spin_lock_irqsave(&he_dev->global_lock, flags);
  1905. while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
  1906. HPRINTK("close cid 0x%x RCC_BUSY\n", cid);
  1907. udelay(250);
  1908. }
  1909. set_current_state(TASK_UNINTERRUPTIBLE);
  1910. add_wait_queue(&he_vcc->rx_waitq, &wait);
  1911. he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
  1912. (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
  1913. he_writel_mbox(he_dev, cid, RXCON_CLOSE);
  1914. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1915. timeout = schedule_timeout(30*HZ);
  1916. remove_wait_queue(&he_vcc->rx_waitq, &wait);
  1917. set_current_state(TASK_RUNNING);
  1918. if (timeout == 0)
  1919. hprintk("close rx timeout cid 0x%x\n", cid);
  1920. HPRINTK("close rx cid 0x%x complete\n", cid);
  1921. }
  1922. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1923. volatile unsigned tsr4, tsr0;
  1924. int timeout;
  1925. HPRINTK("close tx cid 0x%x\n", cid);
  1926. /* 2.1.2
  1927. *
  1928. * ... the host must first stop queueing packets to the TPDRQ
  1929. * on the connection to be closed, then wait for all outstanding
  1930. * packets to be transmitted and their buffers returned to the
  1931. * TBRQ. When the last packet on the connection arrives in the
  1932. * TBRQ, the host issues the close command to the adapter.
  1933. */
  1934. while (((tx_inuse = atomic_read(&sk_atm(vcc)->sk_wmem_alloc)) > 1) &&
  1935. (retry < MAX_RETRY)) {
  1936. msleep(sleep);
  1937. if (sleep < 250)
  1938. sleep = sleep * 2;
  1939. ++retry;
  1940. }
  1941. if (tx_inuse > 1)
  1942. hprintk("close tx cid 0x%x tx_inuse = %d\n", cid, tx_inuse);
  1943. /* 2.3.1.1 generic close operations with flush */
  1944. spin_lock_irqsave(&he_dev->global_lock, flags);
  1945. he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
  1946. /* also clears TSR4_SESSION_ENDED */
  1947. switch (vcc->qos.txtp.traffic_class) {
  1948. case ATM_UBR:
  1949. he_writel_tsr1(he_dev,
  1950. TSR1_MCR(rate_to_atmf(200000))
  1951. | TSR1_PCR(0), cid);
  1952. break;
  1953. case ATM_CBR:
  1954. he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
  1955. break;
  1956. }
  1957. (void) he_readl_tsr4(he_dev, cid); /* flush posted writes */
  1958. tpd = __alloc_tpd(he_dev);
  1959. if (tpd == NULL) {
  1960. hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid);
  1961. goto close_tx_incomplete;
  1962. }
  1963. tpd->status |= TPD_EOS | TPD_INT;
  1964. tpd->skb = NULL;
  1965. tpd->vcc = vcc;
  1966. wmb();
  1967. set_current_state(TASK_UNINTERRUPTIBLE);
  1968. add_wait_queue(&he_vcc->tx_waitq, &wait);
  1969. __enqueue_tpd(he_dev, tpd, cid);
  1970. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1971. timeout = schedule_timeout(30*HZ);
  1972. remove_wait_queue(&he_vcc->tx_waitq, &wait);
  1973. set_current_state(TASK_RUNNING);
  1974. spin_lock_irqsave(&he_dev->global_lock, flags);
  1975. if (timeout == 0) {
  1976. hprintk("close tx timeout cid 0x%x\n", cid);
  1977. goto close_tx_incomplete;
  1978. }
  1979. while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
  1980. HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid, tsr4);
  1981. udelay(250);
  1982. }
  1983. while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
  1984. HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid, tsr0);
  1985. udelay(250);
  1986. }
  1987. close_tx_incomplete:
  1988. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  1989. int reg = he_vcc->rc_index;
  1990. HPRINTK("cs_stper reg = %d\n", reg);
  1991. if (he_dev->cs_stper[reg].inuse == 0)
  1992. hprintk("cs_stper[%d].inuse = 0!\n", reg);
  1993. else
  1994. --he_dev->cs_stper[reg].inuse;
  1995. he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
  1996. }
  1997. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1998. HPRINTK("close tx cid 0x%x complete\n", cid);
  1999. }
  2000. kfree(he_vcc);
  2001. clear_bit(ATM_VF_ADDR, &vcc->flags);
  2002. }
  2003. static int
  2004. he_send(struct atm_vcc *vcc, struct sk_buff *skb)
  2005. {
  2006. unsigned long flags;
  2007. struct he_dev *he_dev = HE_DEV(vcc->dev);
  2008. unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
  2009. struct he_tpd *tpd;
  2010. #ifdef USE_SCATTERGATHER
  2011. int i, slot = 0;
  2012. #endif
  2013. #define HE_TPD_BUFSIZE 0xffff
  2014. HPRINTK("send %d.%d\n", vcc->vpi, vcc->vci);
  2015. if ((skb->len > HE_TPD_BUFSIZE) ||
  2016. ((vcc->qos.aal == ATM_AAL0) && (skb->len != ATM_AAL0_SDU))) {
  2017. hprintk("buffer too large (or small) -- %d bytes\n", skb->len );
  2018. if (vcc->pop)
  2019. vcc->pop(vcc, skb);
  2020. else
  2021. dev_kfree_skb_any(skb);
  2022. atomic_inc(&vcc->stats->tx_err);
  2023. return -EINVAL;
  2024. }
  2025. #ifndef USE_SCATTERGATHER
  2026. if (skb_shinfo(skb)->nr_frags) {
  2027. hprintk("no scatter/gather support\n");
  2028. if (vcc->pop)
  2029. vcc->pop(vcc, skb);
  2030. else
  2031. dev_kfree_skb_any(skb);
  2032. atomic_inc(&vcc->stats->tx_err);
  2033. return -EINVAL;
  2034. }
  2035. #endif
  2036. spin_lock_irqsave(&he_dev->global_lock, flags);
  2037. tpd = __alloc_tpd(he_dev);
  2038. if (tpd == NULL) {
  2039. if (vcc->pop)
  2040. vcc->pop(vcc, skb);
  2041. else
  2042. dev_kfree_skb_any(skb);
  2043. atomic_inc(&vcc->stats->tx_err);
  2044. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2045. return -ENOMEM;
  2046. }
  2047. if (vcc->qos.aal == ATM_AAL5)
  2048. tpd->status |= TPD_CELLTYPE(TPD_USERCELL);
  2049. else {
  2050. char *pti_clp = (void *) (skb->data + 3);
  2051. int clp, pti;
  2052. pti = (*pti_clp & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
  2053. clp = (*pti_clp & ATM_HDR_CLP);
  2054. tpd->status |= TPD_CELLTYPE(pti);
  2055. if (clp)
  2056. tpd->status |= TPD_CLP;
  2057. skb_pull(skb, ATM_AAL0_SDU - ATM_CELL_PAYLOAD);
  2058. }
  2059. #ifdef USE_SCATTERGATHER
  2060. tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev, skb->data,
  2061. skb_headlen(skb), PCI_DMA_TODEVICE);
  2062. tpd->iovec[slot].len = skb_headlen(skb);
  2063. ++slot;
  2064. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2065. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2066. if (slot == TPD_MAXIOV) { /* queue tpd; start new tpd */
  2067. tpd->vcc = vcc;
  2068. tpd->skb = NULL; /* not the last fragment
  2069. so dont ->push() yet */
  2070. wmb();
  2071. __enqueue_tpd(he_dev, tpd, cid);
  2072. tpd = __alloc_tpd(he_dev);
  2073. if (tpd == NULL) {
  2074. if (vcc->pop)
  2075. vcc->pop(vcc, skb);
  2076. else
  2077. dev_kfree_skb_any(skb);
  2078. atomic_inc(&vcc->stats->tx_err);
  2079. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2080. return -ENOMEM;
  2081. }
  2082. tpd->status |= TPD_USERCELL;
  2083. slot = 0;
  2084. }
  2085. tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev,
  2086. (void *) page_address(frag->page) + frag->page_offset,
  2087. frag->size, PCI_DMA_TODEVICE);
  2088. tpd->iovec[slot].len = frag->size;
  2089. ++slot;
  2090. }
  2091. tpd->iovec[slot - 1].len |= TPD_LST;
  2092. #else
  2093. tpd->address0 = pci_map_single(he_dev->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  2094. tpd->length0 = skb->len | TPD_LST;
  2095. #endif
  2096. tpd->status |= TPD_INT;
  2097. tpd->vcc = vcc;
  2098. tpd->skb = skb;
  2099. wmb();
  2100. ATM_SKB(skb)->vcc = vcc;
  2101. __enqueue_tpd(he_dev, tpd, cid);
  2102. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2103. atomic_inc(&vcc->stats->tx);
  2104. return 0;
  2105. }
  2106. static int
  2107. he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void __user *arg)
  2108. {
  2109. unsigned long flags;
  2110. struct he_dev *he_dev = HE_DEV(atm_dev);
  2111. struct he_ioctl_reg reg;
  2112. int err = 0;
  2113. switch (cmd) {
  2114. case HE_GET_REG:
  2115. if (!capable(CAP_NET_ADMIN))
  2116. return -EPERM;
  2117. if (copy_from_user(&reg, arg,
  2118. sizeof(struct he_ioctl_reg)))
  2119. return -EFAULT;
  2120. spin_lock_irqsave(&he_dev->global_lock, flags);
  2121. switch (reg.type) {
  2122. case HE_REGTYPE_PCI:
  2123. if (reg.addr >= HE_REGMAP_SIZE) {
  2124. err = -EINVAL;
  2125. break;
  2126. }
  2127. reg.val = he_readl(he_dev, reg.addr);
  2128. break;
  2129. case HE_REGTYPE_RCM:
  2130. reg.val =
  2131. he_readl_rcm(he_dev, reg.addr);
  2132. break;
  2133. case HE_REGTYPE_TCM:
  2134. reg.val =
  2135. he_readl_tcm(he_dev, reg.addr);
  2136. break;
  2137. case HE_REGTYPE_MBOX:
  2138. reg.val =
  2139. he_readl_mbox(he_dev, reg.addr);
  2140. break;
  2141. default:
  2142. err = -EINVAL;
  2143. break;
  2144. }
  2145. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2146. if (err == 0)
  2147. if (copy_to_user(arg, &reg,
  2148. sizeof(struct he_ioctl_reg)))
  2149. return -EFAULT;
  2150. break;
  2151. default:
  2152. #ifdef CONFIG_ATM_HE_USE_SUNI
  2153. if (atm_dev->phy && atm_dev->phy->ioctl)
  2154. err = atm_dev->phy->ioctl(atm_dev, cmd, arg);
  2155. #else /* CONFIG_ATM_HE_USE_SUNI */
  2156. err = -EINVAL;
  2157. #endif /* CONFIG_ATM_HE_USE_SUNI */
  2158. break;
  2159. }
  2160. return err;
  2161. }
  2162. static void
  2163. he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)
  2164. {
  2165. unsigned long flags;
  2166. struct he_dev *he_dev = HE_DEV(atm_dev);
  2167. HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr);
  2168. spin_lock_irqsave(&he_dev->global_lock, flags);
  2169. he_writel(he_dev, val, FRAMER + (addr*4));
  2170. (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
  2171. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2172. }
  2173. static unsigned char
  2174. he_phy_get(struct atm_dev *atm_dev, unsigned long addr)
  2175. {
  2176. unsigned long flags;
  2177. struct he_dev *he_dev = HE_DEV(atm_dev);
  2178. unsigned reg;
  2179. spin_lock_irqsave(&he_dev->global_lock, flags);
  2180. reg = he_readl(he_dev, FRAMER + (addr*4));
  2181. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2182. HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg);
  2183. return reg;
  2184. }
  2185. static int
  2186. he_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
  2187. {
  2188. unsigned long flags;
  2189. struct he_dev *he_dev = HE_DEV(dev);
  2190. int left, i;
  2191. #ifdef notdef
  2192. struct he_rbrq *rbrq_tail;
  2193. struct he_tpdrq *tpdrq_head;
  2194. int rbpl_head, rbpl_tail;
  2195. #endif
  2196. static long mcc = 0, oec = 0, dcc = 0, cec = 0;
  2197. left = *pos;
  2198. if (!left--)
  2199. return sprintf(page, "ATM he driver\n");
  2200. if (!left--)
  2201. return sprintf(page, "%s%s\n\n",
  2202. he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");
  2203. if (!left--)
  2204. return sprintf(page, "Mismatched Cells VPI/VCI Not Open Dropped Cells RCM Dropped Cells\n");
  2205. spin_lock_irqsave(&he_dev->global_lock, flags);
  2206. mcc += he_readl(he_dev, MCC);
  2207. oec += he_readl(he_dev, OEC);
  2208. dcc += he_readl(he_dev, DCC);
  2209. cec += he_readl(he_dev, CEC);
  2210. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2211. if (!left--)
  2212. return sprintf(page, "%16ld %16ld %13ld %17ld\n\n",
  2213. mcc, oec, dcc, cec);
  2214. if (!left--)
  2215. return sprintf(page, "irq_size = %d inuse = ? peak = %d\n",
  2216. CONFIG_IRQ_SIZE, he_dev->irq_peak);
  2217. if (!left--)
  2218. return sprintf(page, "tpdrq_size = %d inuse = ?\n",
  2219. CONFIG_TPDRQ_SIZE);
  2220. if (!left--)
  2221. return sprintf(page, "rbrq_size = %d inuse = ? peak = %d\n",
  2222. CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);
  2223. if (!left--)
  2224. return sprintf(page, "tbrq_size = %d peak = %d\n",
  2225. CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);
  2226. #ifdef notdef
  2227. rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
  2228. rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
  2229. inuse = rbpl_head - rbpl_tail;
  2230. if (inuse < 0)
  2231. inuse += CONFIG_RBPL_SIZE * sizeof(struct he_rbp);
  2232. inuse /= sizeof(struct he_rbp);
  2233. if (!left--)
  2234. return sprintf(page, "rbpl_size = %d inuse = %d\n\n",
  2235. CONFIG_RBPL_SIZE, inuse);
  2236. #endif
  2237. if (!left--)
  2238. return sprintf(page, "rate controller periods (cbr)\n pcr #vc\n");
  2239. for (i = 0; i < HE_NUM_CS_STPER; ++i)
  2240. if (!left--)
  2241. return sprintf(page, "cs_stper%-2d %8ld %3d\n", i,
  2242. he_dev->cs_stper[i].pcr,
  2243. he_dev->cs_stper[i].inuse);
  2244. if (!left--)
  2245. return sprintf(page, "total bw (cbr): %d (limit %d)\n",
  2246. he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);
  2247. return 0;
  2248. }
  2249. /* eeprom routines -- see 4.7 */
  2250. static u8 read_prom_byte(struct he_dev *he_dev, int addr)
  2251. {
  2252. u32 val = 0, tmp_read = 0;
  2253. int i, j = 0;
  2254. u8 byte_read = 0;
  2255. val = readl(he_dev->membase + HOST_CNTL);
  2256. val &= 0xFFFFE0FF;
  2257. /* Turn on write enable */
  2258. val |= 0x800;
  2259. he_writel(he_dev, val, HOST_CNTL);
  2260. /* Send READ instruction */
  2261. for (i = 0; i < ARRAY_SIZE(readtab); i++) {
  2262. he_writel(he_dev, val | readtab[i], HOST_CNTL);
  2263. udelay(EEPROM_DELAY);
  2264. }
  2265. /* Next, we need to send the byte address to read from */
  2266. for (i = 7; i >= 0; i--) {
  2267. he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
  2268. udelay(EEPROM_DELAY);
  2269. he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
  2270. udelay(EEPROM_DELAY);
  2271. }
  2272. j = 0;
  2273. val &= 0xFFFFF7FF; /* Turn off write enable */
  2274. he_writel(he_dev, val, HOST_CNTL);
  2275. /* Now, we can read data from the EEPROM by clocking it in */
  2276. for (i = 7; i >= 0; i--) {
  2277. he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
  2278. udelay(EEPROM_DELAY);
  2279. tmp_read = he_readl(he_dev, HOST_CNTL);
  2280. byte_read |= (unsigned char)
  2281. ((tmp_read & ID_DOUT) >> ID_DOFFSET << i);
  2282. he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
  2283. udelay(EEPROM_DELAY);
  2284. }
  2285. he_writel(he_dev, val | ID_CS, HOST_CNTL);
  2286. udelay(EEPROM_DELAY);
  2287. return byte_read;
  2288. }
  2289. MODULE_LICENSE("GPL");
  2290. MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
  2291. MODULE_DESCRIPTION("ForeRunnerHE ATM Adapter driver");
  2292. module_param(disable64, bool, 0);
  2293. MODULE_PARM_DESC(disable64, "disable 64-bit pci bus transfers");
  2294. module_param(nvpibits, short, 0);
  2295. MODULE_PARM_DESC(nvpibits, "numbers of bits for vpi (default 0)");
  2296. module_param(nvcibits, short, 0);
  2297. MODULE_PARM_DESC(nvcibits, "numbers of bits for vci (default 12)");
  2298. module_param(rx_skb_reserve, short, 0);
  2299. MODULE_PARM_DESC(rx_skb_reserve, "padding for receive skb (default 16)");
  2300. module_param(irq_coalesce, bool, 0);
  2301. MODULE_PARM_DESC(irq_coalesce, "use interrupt coalescing (default 1)");
  2302. module_param(sdh, bool, 0);
  2303. MODULE_PARM_DESC(sdh, "use SDH framing (default 0)");
  2304. static struct pci_device_id he_pci_tbl[] = {
  2305. { PCI_VDEVICE(FORE, PCI_DEVICE_ID_FORE_HE), 0 },
  2306. { 0, }
  2307. };
  2308. MODULE_DEVICE_TABLE(pci, he_pci_tbl);
  2309. static struct pci_driver he_driver = {
  2310. .name = "he",
  2311. .probe = he_init_one,
  2312. .remove = __devexit_p(he_remove_one),
  2313. .id_table = he_pci_tbl,
  2314. };
  2315. static int __init he_init(void)
  2316. {
  2317. return pci_register_driver(&he_driver);
  2318. }
  2319. static void __exit he_cleanup(void)
  2320. {
  2321. pci_unregister_driver(&he_driver);
  2322. }
  2323. module_init(he_init);
  2324. module_exit(he_cleanup);