PageRenderTime 78ms CodeModel.GetById 27ms RepoModel.GetById 0ms app.codeStats 1ms

/drivers/char/pcmcia/synclink_cs.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 4311 lines | 2938 code | 672 blank | 701 comment | 620 complexity | 9990b381aff71ea36e28a41ddda3c1f6 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/system.h>
  60. #include <asm/io.h>
  61. #include <asm/irq.h>
  62. #include <asm/dma.h>
  63. #include <linux/bitops.h>
  64. #include <asm/types.h>
  65. #include <linux/termios.h>
  66. #include <linux/workqueue.h>
  67. #include <linux/hdlc.h>
  68. #include <pcmcia/cistpl.h>
  69. #include <pcmcia/cisreg.h>
  70. #include <pcmcia/ds.h>
  71. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  72. #define SYNCLINK_GENERIC_HDLC 1
  73. #else
  74. #define SYNCLINK_GENERIC_HDLC 0
  75. #endif
  76. #define GET_USER(error,value,addr) error = get_user(value,addr)
  77. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  78. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  79. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  80. #include <asm/uaccess.h>
  81. static MGSL_PARAMS default_params = {
  82. MGSL_MODE_HDLC, /* unsigned long mode */
  83. 0, /* unsigned char loopback; */
  84. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  85. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  86. 0, /* unsigned long clock_speed; */
  87. 0xff, /* unsigned char addr_filter; */
  88. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  89. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  90. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  91. 9600, /* unsigned long data_rate; */
  92. 8, /* unsigned char data_bits; */
  93. 1, /* unsigned char stop_bits; */
  94. ASYNC_PARITY_NONE /* unsigned char parity; */
  95. };
  96. typedef struct
  97. {
  98. int count;
  99. unsigned char status;
  100. char data[1];
  101. } RXBUF;
  102. /* The queue of BH actions to be performed */
  103. #define BH_RECEIVE 1
  104. #define BH_TRANSMIT 2
  105. #define BH_STATUS 4
  106. #define IO_PIN_SHUTDOWN_LIMIT 100
  107. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  108. struct _input_signal_events {
  109. int ri_up;
  110. int ri_down;
  111. int dsr_up;
  112. int dsr_down;
  113. int dcd_up;
  114. int dcd_down;
  115. int cts_up;
  116. int cts_down;
  117. };
  118. /*
  119. * Device instance data structure
  120. */
  121. typedef struct _mgslpc_info {
  122. struct tty_port port;
  123. void *if_ptr; /* General purpose pointer (used by SPPP) */
  124. int magic;
  125. int line;
  126. struct mgsl_icount icount;
  127. int timeout;
  128. int x_char; /* xon/xoff character */
  129. unsigned char read_status_mask;
  130. unsigned char ignore_status_mask;
  131. unsigned char *tx_buf;
  132. int tx_put;
  133. int tx_get;
  134. int tx_count;
  135. /* circular list of fixed length rx buffers */
  136. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  137. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  138. int rx_put; /* index of next empty rx buffer */
  139. int rx_get; /* index of next full rx buffer */
  140. int rx_buf_size; /* size in bytes of single rx buffer */
  141. int rx_buf_count; /* total number of rx buffers */
  142. int rx_frame_count; /* number of full rx buffers */
  143. wait_queue_head_t status_event_wait_q;
  144. wait_queue_head_t event_wait_q;
  145. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  146. struct _mgslpc_info *next_device; /* device list link */
  147. unsigned short imra_value;
  148. unsigned short imrb_value;
  149. unsigned char pim_value;
  150. spinlock_t lock;
  151. struct work_struct task; /* task structure for scheduling bh */
  152. u32 max_frame_size;
  153. u32 pending_bh;
  154. bool bh_running;
  155. bool bh_requested;
  156. int dcd_chkcount; /* check counts to prevent */
  157. int cts_chkcount; /* too many IRQs if a signal */
  158. int dsr_chkcount; /* is floating */
  159. int ri_chkcount;
  160. bool rx_enabled;
  161. bool rx_overflow;
  162. bool tx_enabled;
  163. bool tx_active;
  164. bool tx_aborting;
  165. u32 idle_mode;
  166. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  167. char device_name[25]; /* device instance name */
  168. unsigned int io_base; /* base I/O address of adapter */
  169. unsigned int irq_level;
  170. MGSL_PARAMS params; /* communications parameters */
  171. unsigned char serial_signals; /* current serial signal states */
  172. bool irq_occurred; /* for diagnostics use */
  173. char testing_irq;
  174. unsigned int init_error; /* startup error (DIAGS) */
  175. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  176. bool drop_rts_on_tx_done;
  177. struct _input_signal_events input_signal_events;
  178. /* PCMCIA support */
  179. struct pcmcia_device *p_dev;
  180. int stop;
  181. /* SPPP/Cisco HDLC device parts */
  182. int netcount;
  183. spinlock_t netlock;
  184. #if SYNCLINK_GENERIC_HDLC
  185. struct net_device *netdev;
  186. #endif
  187. } MGSLPC_INFO;
  188. #define MGSLPC_MAGIC 0x5402
  189. /*
  190. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  191. */
  192. #define TXBUFSIZE 4096
  193. #define CHA 0x00 /* channel A offset */
  194. #define CHB 0x40 /* channel B offset */
  195. /*
  196. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  197. */
  198. #undef PVR
  199. #define RXFIFO 0
  200. #define TXFIFO 0
  201. #define STAR 0x20
  202. #define CMDR 0x20
  203. #define RSTA 0x21
  204. #define PRE 0x21
  205. #define MODE 0x22
  206. #define TIMR 0x23
  207. #define XAD1 0x24
  208. #define XAD2 0x25
  209. #define RAH1 0x26
  210. #define RAH2 0x27
  211. #define DAFO 0x27
  212. #define RAL1 0x28
  213. #define RFC 0x28
  214. #define RHCR 0x29
  215. #define RAL2 0x29
  216. #define RBCL 0x2a
  217. #define XBCL 0x2a
  218. #define RBCH 0x2b
  219. #define XBCH 0x2b
  220. #define CCR0 0x2c
  221. #define CCR1 0x2d
  222. #define CCR2 0x2e
  223. #define CCR3 0x2f
  224. #define VSTR 0x34
  225. #define BGR 0x34
  226. #define RLCR 0x35
  227. #define AML 0x36
  228. #define AMH 0x37
  229. #define GIS 0x38
  230. #define IVA 0x38
  231. #define IPC 0x39
  232. #define ISR 0x3a
  233. #define IMR 0x3a
  234. #define PVR 0x3c
  235. #define PIS 0x3d
  236. #define PIM 0x3d
  237. #define PCR 0x3e
  238. #define CCR4 0x3f
  239. // IMR/ISR
  240. #define IRQ_BREAK_ON BIT15 // rx break detected
  241. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  242. #define IRQ_ALLSENT BIT13 // all sent
  243. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  244. #define IRQ_TIMER BIT11 // timer interrupt
  245. #define IRQ_CTS BIT10 // CTS status change
  246. #define IRQ_TXREPEAT BIT9 // tx message repeat
  247. #define IRQ_TXFIFO BIT8 // transmit pool ready
  248. #define IRQ_RXEOM BIT7 // receive message end
  249. #define IRQ_EXITHUNT BIT6 // receive frame start
  250. #define IRQ_RXTIME BIT6 // rx char timeout
  251. #define IRQ_DCD BIT2 // carrier detect status change
  252. #define IRQ_OVERRUN BIT1 // receive frame overflow
  253. #define IRQ_RXFIFO BIT0 // receive pool full
  254. // STAR
  255. #define XFW BIT6 // transmit FIFO write enable
  256. #define CEC BIT2 // command executing
  257. #define CTS BIT1 // CTS state
  258. #define PVR_DTR BIT0
  259. #define PVR_DSR BIT1
  260. #define PVR_RI BIT2
  261. #define PVR_AUTOCTS BIT3
  262. #define PVR_RS232 0x20 /* 0010b */
  263. #define PVR_V35 0xe0 /* 1110b */
  264. #define PVR_RS422 0x40 /* 0100b */
  265. /* Register access functions */
  266. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  267. #define read_reg(info, reg) inb((info)->io_base + (reg))
  268. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  269. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  270. #define set_reg_bits(info, reg, mask) \
  271. write_reg(info, (reg), \
  272. (unsigned char) (read_reg(info, (reg)) | (mask)))
  273. #define clear_reg_bits(info, reg, mask) \
  274. write_reg(info, (reg), \
  275. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  276. /*
  277. * interrupt enable/disable routines
  278. */
  279. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  280. {
  281. if (channel == CHA) {
  282. info->imra_value |= mask;
  283. write_reg16(info, CHA + IMR, info->imra_value);
  284. } else {
  285. info->imrb_value |= mask;
  286. write_reg16(info, CHB + IMR, info->imrb_value);
  287. }
  288. }
  289. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  290. {
  291. if (channel == CHA) {
  292. info->imra_value &= ~mask;
  293. write_reg16(info, CHA + IMR, info->imra_value);
  294. } else {
  295. info->imrb_value &= ~mask;
  296. write_reg16(info, CHB + IMR, info->imrb_value);
  297. }
  298. }
  299. #define port_irq_disable(info, mask) \
  300. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  301. #define port_irq_enable(info, mask) \
  302. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  303. static void rx_start(MGSLPC_INFO *info);
  304. static void rx_stop(MGSLPC_INFO *info);
  305. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  306. static void tx_stop(MGSLPC_INFO *info);
  307. static void tx_set_idle(MGSLPC_INFO *info);
  308. static void get_signals(MGSLPC_INFO *info);
  309. static void set_signals(MGSLPC_INFO *info);
  310. static void reset_device(MGSLPC_INFO *info);
  311. static void hdlc_mode(MGSLPC_INFO *info);
  312. static void async_mode(MGSLPC_INFO *info);
  313. static void tx_timeout(unsigned long context);
  314. static int carrier_raised(struct tty_port *port);
  315. static void dtr_rts(struct tty_port *port, int onoff);
  316. #if SYNCLINK_GENERIC_HDLC
  317. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  318. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  319. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  320. static int hdlcdev_init(MGSLPC_INFO *info);
  321. static void hdlcdev_exit(MGSLPC_INFO *info);
  322. #endif
  323. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  324. static bool register_test(MGSLPC_INFO *info);
  325. static bool irq_test(MGSLPC_INFO *info);
  326. static int adapter_test(MGSLPC_INFO *info);
  327. static int claim_resources(MGSLPC_INFO *info);
  328. static void release_resources(MGSLPC_INFO *info);
  329. static void mgslpc_add_device(MGSLPC_INFO *info);
  330. static void mgslpc_remove_device(MGSLPC_INFO *info);
  331. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  332. static void rx_reset_buffers(MGSLPC_INFO *info);
  333. static int rx_alloc_buffers(MGSLPC_INFO *info);
  334. static void rx_free_buffers(MGSLPC_INFO *info);
  335. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  336. /*
  337. * Bottom half interrupt handlers
  338. */
  339. static void bh_handler(struct work_struct *work);
  340. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  341. static void bh_status(MGSLPC_INFO *info);
  342. /*
  343. * ioctl handlers
  344. */
  345. static int tiocmget(struct tty_struct *tty);
  346. static int tiocmset(struct tty_struct *tty,
  347. unsigned int set, unsigned int clear);
  348. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  349. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  350. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  351. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  352. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  353. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  354. static int tx_abort(MGSLPC_INFO *info);
  355. static int set_rxenable(MGSLPC_INFO *info, int enable);
  356. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  357. static MGSLPC_INFO *mgslpc_device_list = NULL;
  358. static int mgslpc_device_count = 0;
  359. /*
  360. * Set this param to non-zero to load eax with the
  361. * .text section address and breakpoint on module load.
  362. * This is useful for use with gdb and add-symbol-file command.
  363. */
  364. static int break_on_load=0;
  365. /*
  366. * Driver major number, defaults to zero to get auto
  367. * assigned major number. May be forced as module parameter.
  368. */
  369. static int ttymajor=0;
  370. static int debug_level = 0;
  371. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  372. module_param(break_on_load, bool, 0);
  373. module_param(ttymajor, int, 0);
  374. module_param(debug_level, int, 0);
  375. module_param_array(maxframe, int, NULL, 0);
  376. MODULE_LICENSE("GPL");
  377. static char *driver_name = "SyncLink PC Card driver";
  378. static char *driver_version = "$Revision: 4.34 $";
  379. static struct tty_driver *serial_driver;
  380. /* number of characters left in xmit buffer before we ask for more */
  381. #define WAKEUP_CHARS 256
  382. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  383. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  384. /* PCMCIA prototypes */
  385. static int mgslpc_config(struct pcmcia_device *link);
  386. static void mgslpc_release(u_long arg);
  387. static void mgslpc_detach(struct pcmcia_device *p_dev);
  388. /*
  389. * 1st function defined in .text section. Calling this function in
  390. * init_module() followed by a breakpoint allows a remote debugger
  391. * (gdb) to get the .text address for the add-symbol-file command.
  392. * This allows remote debugging of dynamically loadable modules.
  393. */
  394. static void* mgslpc_get_text_ptr(void)
  395. {
  396. return mgslpc_get_text_ptr;
  397. }
  398. /**
  399. * line discipline callback wrappers
  400. *
  401. * The wrappers maintain line discipline references
  402. * while calling into the line discipline.
  403. *
  404. * ldisc_receive_buf - pass receive data to line discipline
  405. */
  406. static void ldisc_receive_buf(struct tty_struct *tty,
  407. const __u8 *data, char *flags, int count)
  408. {
  409. struct tty_ldisc *ld;
  410. if (!tty)
  411. return;
  412. ld = tty_ldisc_ref(tty);
  413. if (ld) {
  414. if (ld->ops->receive_buf)
  415. ld->ops->receive_buf(tty, data, flags, count);
  416. tty_ldisc_deref(ld);
  417. }
  418. }
  419. static const struct tty_port_operations mgslpc_port_ops = {
  420. .carrier_raised = carrier_raised,
  421. .dtr_rts = dtr_rts
  422. };
  423. static int mgslpc_probe(struct pcmcia_device *link)
  424. {
  425. MGSLPC_INFO *info;
  426. int ret;
  427. if (debug_level >= DEBUG_LEVEL_INFO)
  428. printk("mgslpc_attach\n");
  429. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  430. if (!info) {
  431. printk("Error can't allocate device instance data\n");
  432. return -ENOMEM;
  433. }
  434. info->magic = MGSLPC_MAGIC;
  435. tty_port_init(&info->port);
  436. info->port.ops = &mgslpc_port_ops;
  437. INIT_WORK(&info->task, bh_handler);
  438. info->max_frame_size = 4096;
  439. info->port.close_delay = 5*HZ/10;
  440. info->port.closing_wait = 30*HZ;
  441. init_waitqueue_head(&info->status_event_wait_q);
  442. init_waitqueue_head(&info->event_wait_q);
  443. spin_lock_init(&info->lock);
  444. spin_lock_init(&info->netlock);
  445. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  446. info->idle_mode = HDLC_TXIDLE_FLAGS;
  447. info->imra_value = 0xffff;
  448. info->imrb_value = 0xffff;
  449. info->pim_value = 0xff;
  450. info->p_dev = link;
  451. link->priv = info;
  452. /* Initialize the struct pcmcia_device structure */
  453. ret = mgslpc_config(link);
  454. if (ret)
  455. return ret;
  456. mgslpc_add_device(info);
  457. return 0;
  458. }
  459. /* Card has been inserted.
  460. */
  461. static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
  462. {
  463. return pcmcia_request_io(p_dev);
  464. }
  465. static int mgslpc_config(struct pcmcia_device *link)
  466. {
  467. MGSLPC_INFO *info = link->priv;
  468. int ret;
  469. if (debug_level >= DEBUG_LEVEL_INFO)
  470. printk("mgslpc_config(0x%p)\n", link);
  471. link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
  472. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  473. if (ret != 0)
  474. goto failed;
  475. link->config_index = 8;
  476. link->config_regs = PRESENT_OPTION;
  477. ret = pcmcia_request_irq(link, mgslpc_isr);
  478. if (ret)
  479. goto failed;
  480. ret = pcmcia_enable_device(link);
  481. if (ret)
  482. goto failed;
  483. info->io_base = link->resource[0]->start;
  484. info->irq_level = link->irq;
  485. return 0;
  486. failed:
  487. mgslpc_release((u_long)link);
  488. return -ENODEV;
  489. }
  490. /* Card has been removed.
  491. * Unregister device and release PCMCIA configuration.
  492. * If device is open, postpone until it is closed.
  493. */
  494. static void mgslpc_release(u_long arg)
  495. {
  496. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  497. if (debug_level >= DEBUG_LEVEL_INFO)
  498. printk("mgslpc_release(0x%p)\n", link);
  499. pcmcia_disable_device(link);
  500. }
  501. static void mgslpc_detach(struct pcmcia_device *link)
  502. {
  503. if (debug_level >= DEBUG_LEVEL_INFO)
  504. printk("mgslpc_detach(0x%p)\n", link);
  505. ((MGSLPC_INFO *)link->priv)->stop = 1;
  506. mgslpc_release((u_long)link);
  507. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  508. }
  509. static int mgslpc_suspend(struct pcmcia_device *link)
  510. {
  511. MGSLPC_INFO *info = link->priv;
  512. info->stop = 1;
  513. return 0;
  514. }
  515. static int mgslpc_resume(struct pcmcia_device *link)
  516. {
  517. MGSLPC_INFO *info = link->priv;
  518. info->stop = 0;
  519. return 0;
  520. }
  521. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  522. char *name, const char *routine)
  523. {
  524. #ifdef MGSLPC_PARANOIA_CHECK
  525. static const char *badmagic =
  526. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  527. static const char *badinfo =
  528. "Warning: null mgslpc_info for (%s) in %s\n";
  529. if (!info) {
  530. printk(badinfo, name, routine);
  531. return true;
  532. }
  533. if (info->magic != MGSLPC_MAGIC) {
  534. printk(badmagic, name, routine);
  535. return true;
  536. }
  537. #else
  538. if (!info)
  539. return true;
  540. #endif
  541. return false;
  542. }
  543. #define CMD_RXFIFO BIT7 // release current rx FIFO
  544. #define CMD_RXRESET BIT6 // receiver reset
  545. #define CMD_RXFIFO_READ BIT5
  546. #define CMD_START_TIMER BIT4
  547. #define CMD_TXFIFO BIT3 // release current tx FIFO
  548. #define CMD_TXEOM BIT1 // transmit end message
  549. #define CMD_TXRESET BIT0 // transmit reset
  550. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  551. {
  552. int i = 0;
  553. /* wait for command completion */
  554. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  555. udelay(1);
  556. if (i++ == 1000)
  557. return false;
  558. }
  559. return true;
  560. }
  561. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  562. {
  563. wait_command_complete(info, channel);
  564. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  565. }
  566. static void tx_pause(struct tty_struct *tty)
  567. {
  568. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  569. unsigned long flags;
  570. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  571. return;
  572. if (debug_level >= DEBUG_LEVEL_INFO)
  573. printk("tx_pause(%s)\n",info->device_name);
  574. spin_lock_irqsave(&info->lock,flags);
  575. if (info->tx_enabled)
  576. tx_stop(info);
  577. spin_unlock_irqrestore(&info->lock,flags);
  578. }
  579. static void tx_release(struct tty_struct *tty)
  580. {
  581. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  582. unsigned long flags;
  583. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  584. return;
  585. if (debug_level >= DEBUG_LEVEL_INFO)
  586. printk("tx_release(%s)\n",info->device_name);
  587. spin_lock_irqsave(&info->lock,flags);
  588. if (!info->tx_enabled)
  589. tx_start(info, tty);
  590. spin_unlock_irqrestore(&info->lock,flags);
  591. }
  592. /* Return next bottom half action to perform.
  593. * or 0 if nothing to do.
  594. */
  595. static int bh_action(MGSLPC_INFO *info)
  596. {
  597. unsigned long flags;
  598. int rc = 0;
  599. spin_lock_irqsave(&info->lock,flags);
  600. if (info->pending_bh & BH_RECEIVE) {
  601. info->pending_bh &= ~BH_RECEIVE;
  602. rc = BH_RECEIVE;
  603. } else if (info->pending_bh & BH_TRANSMIT) {
  604. info->pending_bh &= ~BH_TRANSMIT;
  605. rc = BH_TRANSMIT;
  606. } else if (info->pending_bh & BH_STATUS) {
  607. info->pending_bh &= ~BH_STATUS;
  608. rc = BH_STATUS;
  609. }
  610. if (!rc) {
  611. /* Mark BH routine as complete */
  612. info->bh_running = false;
  613. info->bh_requested = false;
  614. }
  615. spin_unlock_irqrestore(&info->lock,flags);
  616. return rc;
  617. }
  618. static void bh_handler(struct work_struct *work)
  619. {
  620. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  621. struct tty_struct *tty;
  622. int action;
  623. if (!info)
  624. return;
  625. if (debug_level >= DEBUG_LEVEL_BH)
  626. printk( "%s(%d):bh_handler(%s) entry\n",
  627. __FILE__,__LINE__,info->device_name);
  628. info->bh_running = true;
  629. tty = tty_port_tty_get(&info->port);
  630. while((action = bh_action(info)) != 0) {
  631. /* Process work item */
  632. if ( debug_level >= DEBUG_LEVEL_BH )
  633. printk( "%s(%d):bh_handler() work item action=%d\n",
  634. __FILE__,__LINE__,action);
  635. switch (action) {
  636. case BH_RECEIVE:
  637. while(rx_get_frame(info, tty));
  638. break;
  639. case BH_TRANSMIT:
  640. bh_transmit(info, tty);
  641. break;
  642. case BH_STATUS:
  643. bh_status(info);
  644. break;
  645. default:
  646. /* unknown work item ID */
  647. printk("Unknown work item ID=%08X!\n", action);
  648. break;
  649. }
  650. }
  651. tty_kref_put(tty);
  652. if (debug_level >= DEBUG_LEVEL_BH)
  653. printk( "%s(%d):bh_handler(%s) exit\n",
  654. __FILE__,__LINE__,info->device_name);
  655. }
  656. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  657. {
  658. if (debug_level >= DEBUG_LEVEL_BH)
  659. printk("bh_transmit() entry on %s\n", info->device_name);
  660. if (tty)
  661. tty_wakeup(tty);
  662. }
  663. static void bh_status(MGSLPC_INFO *info)
  664. {
  665. info->ri_chkcount = 0;
  666. info->dsr_chkcount = 0;
  667. info->dcd_chkcount = 0;
  668. info->cts_chkcount = 0;
  669. }
  670. /* eom: non-zero = end of frame */
  671. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  672. {
  673. unsigned char data[2];
  674. unsigned char fifo_count, read_count, i;
  675. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  676. if (debug_level >= DEBUG_LEVEL_ISR)
  677. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  678. if (!info->rx_enabled)
  679. return;
  680. if (info->rx_frame_count >= info->rx_buf_count) {
  681. /* no more free buffers */
  682. issue_command(info, CHA, CMD_RXRESET);
  683. info->pending_bh |= BH_RECEIVE;
  684. info->rx_overflow = true;
  685. info->icount.buf_overrun++;
  686. return;
  687. }
  688. if (eom) {
  689. /* end of frame, get FIFO count from RBCL register */
  690. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  691. fifo_count = 32;
  692. } else
  693. fifo_count = 32;
  694. do {
  695. if (fifo_count == 1) {
  696. read_count = 1;
  697. data[0] = read_reg(info, CHA + RXFIFO);
  698. } else {
  699. read_count = 2;
  700. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  701. }
  702. fifo_count -= read_count;
  703. if (!fifo_count && eom)
  704. buf->status = data[--read_count];
  705. for (i = 0; i < read_count; i++) {
  706. if (buf->count >= info->max_frame_size) {
  707. /* frame too large, reset receiver and reset current buffer */
  708. issue_command(info, CHA, CMD_RXRESET);
  709. buf->count = 0;
  710. return;
  711. }
  712. *(buf->data + buf->count) = data[i];
  713. buf->count++;
  714. }
  715. } while (fifo_count);
  716. if (eom) {
  717. info->pending_bh |= BH_RECEIVE;
  718. info->rx_frame_count++;
  719. info->rx_put++;
  720. if (info->rx_put >= info->rx_buf_count)
  721. info->rx_put = 0;
  722. }
  723. issue_command(info, CHA, CMD_RXFIFO);
  724. }
  725. static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
  726. {
  727. unsigned char data, status, flag;
  728. int fifo_count;
  729. int work = 0;
  730. struct mgsl_icount *icount = &info->icount;
  731. if (tcd) {
  732. /* early termination, get FIFO count from RBCL register */
  733. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  734. /* Zero fifo count could mean 0 or 32 bytes available.
  735. * If BIT5 of STAR is set then at least 1 byte is available.
  736. */
  737. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  738. fifo_count = 32;
  739. } else
  740. fifo_count = 32;
  741. tty_buffer_request_room(tty, fifo_count);
  742. /* Flush received async data to receive data buffer. */
  743. while (fifo_count) {
  744. data = read_reg(info, CHA + RXFIFO);
  745. status = read_reg(info, CHA + RXFIFO);
  746. fifo_count -= 2;
  747. icount->rx++;
  748. flag = TTY_NORMAL;
  749. // if no frameing/crc error then save data
  750. // BIT7:parity error
  751. // BIT6:framing error
  752. if (status & (BIT7 + BIT6)) {
  753. if (status & BIT7)
  754. icount->parity++;
  755. else
  756. icount->frame++;
  757. /* discard char if tty control flags say so */
  758. if (status & info->ignore_status_mask)
  759. continue;
  760. status &= info->read_status_mask;
  761. if (status & BIT7)
  762. flag = TTY_PARITY;
  763. else if (status & BIT6)
  764. flag = TTY_FRAME;
  765. }
  766. work += tty_insert_flip_char(tty, data, flag);
  767. }
  768. issue_command(info, CHA, CMD_RXFIFO);
  769. if (debug_level >= DEBUG_LEVEL_ISR) {
  770. printk("%s(%d):rx_ready_async",
  771. __FILE__,__LINE__);
  772. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  773. __FILE__,__LINE__,icount->rx,icount->brk,
  774. icount->parity,icount->frame,icount->overrun);
  775. }
  776. if (work)
  777. tty_flip_buffer_push(tty);
  778. }
  779. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  780. {
  781. if (!info->tx_active)
  782. return;
  783. info->tx_active = false;
  784. info->tx_aborting = false;
  785. if (info->params.mode == MGSL_MODE_ASYNC)
  786. return;
  787. info->tx_count = info->tx_put = info->tx_get = 0;
  788. del_timer(&info->tx_timer);
  789. if (info->drop_rts_on_tx_done) {
  790. get_signals(info);
  791. if (info->serial_signals & SerialSignal_RTS) {
  792. info->serial_signals &= ~SerialSignal_RTS;
  793. set_signals(info);
  794. }
  795. info->drop_rts_on_tx_done = false;
  796. }
  797. #if SYNCLINK_GENERIC_HDLC
  798. if (info->netcount)
  799. hdlcdev_tx_done(info);
  800. else
  801. #endif
  802. {
  803. if (tty->stopped || tty->hw_stopped) {
  804. tx_stop(info);
  805. return;
  806. }
  807. info->pending_bh |= BH_TRANSMIT;
  808. }
  809. }
  810. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  811. {
  812. unsigned char fifo_count = 32;
  813. int c;
  814. if (debug_level >= DEBUG_LEVEL_ISR)
  815. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  816. if (info->params.mode == MGSL_MODE_HDLC) {
  817. if (!info->tx_active)
  818. return;
  819. } else {
  820. if (tty->stopped || tty->hw_stopped) {
  821. tx_stop(info);
  822. return;
  823. }
  824. if (!info->tx_count)
  825. info->tx_active = false;
  826. }
  827. if (!info->tx_count)
  828. return;
  829. while (info->tx_count && fifo_count) {
  830. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  831. if (c == 1) {
  832. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  833. } else {
  834. write_reg16(info, CHA + TXFIFO,
  835. *((unsigned short*)(info->tx_buf + info->tx_get)));
  836. }
  837. info->tx_count -= c;
  838. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  839. fifo_count -= c;
  840. }
  841. if (info->params.mode == MGSL_MODE_ASYNC) {
  842. if (info->tx_count < WAKEUP_CHARS)
  843. info->pending_bh |= BH_TRANSMIT;
  844. issue_command(info, CHA, CMD_TXFIFO);
  845. } else {
  846. if (info->tx_count)
  847. issue_command(info, CHA, CMD_TXFIFO);
  848. else
  849. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  850. }
  851. }
  852. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  853. {
  854. get_signals(info);
  855. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  856. irq_disable(info, CHB, IRQ_CTS);
  857. info->icount.cts++;
  858. if (info->serial_signals & SerialSignal_CTS)
  859. info->input_signal_events.cts_up++;
  860. else
  861. info->input_signal_events.cts_down++;
  862. wake_up_interruptible(&info->status_event_wait_q);
  863. wake_up_interruptible(&info->event_wait_q);
  864. if (info->port.flags & ASYNC_CTS_FLOW) {
  865. if (tty->hw_stopped) {
  866. if (info->serial_signals & SerialSignal_CTS) {
  867. if (debug_level >= DEBUG_LEVEL_ISR)
  868. printk("CTS tx start...");
  869. if (tty)
  870. tty->hw_stopped = 0;
  871. tx_start(info, tty);
  872. info->pending_bh |= BH_TRANSMIT;
  873. return;
  874. }
  875. } else {
  876. if (!(info->serial_signals & SerialSignal_CTS)) {
  877. if (debug_level >= DEBUG_LEVEL_ISR)
  878. printk("CTS tx stop...");
  879. if (tty)
  880. tty->hw_stopped = 1;
  881. tx_stop(info);
  882. }
  883. }
  884. }
  885. info->pending_bh |= BH_STATUS;
  886. }
  887. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  888. {
  889. get_signals(info);
  890. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  891. irq_disable(info, CHB, IRQ_DCD);
  892. info->icount.dcd++;
  893. if (info->serial_signals & SerialSignal_DCD) {
  894. info->input_signal_events.dcd_up++;
  895. }
  896. else
  897. info->input_signal_events.dcd_down++;
  898. #if SYNCLINK_GENERIC_HDLC
  899. if (info->netcount) {
  900. if (info->serial_signals & SerialSignal_DCD)
  901. netif_carrier_on(info->netdev);
  902. else
  903. netif_carrier_off(info->netdev);
  904. }
  905. #endif
  906. wake_up_interruptible(&info->status_event_wait_q);
  907. wake_up_interruptible(&info->event_wait_q);
  908. if (info->port.flags & ASYNC_CHECK_CD) {
  909. if (debug_level >= DEBUG_LEVEL_ISR)
  910. printk("%s CD now %s...", info->device_name,
  911. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  912. if (info->serial_signals & SerialSignal_DCD)
  913. wake_up_interruptible(&info->port.open_wait);
  914. else {
  915. if (debug_level >= DEBUG_LEVEL_ISR)
  916. printk("doing serial hangup...");
  917. if (tty)
  918. tty_hangup(tty);
  919. }
  920. }
  921. info->pending_bh |= BH_STATUS;
  922. }
  923. static void dsr_change(MGSLPC_INFO *info)
  924. {
  925. get_signals(info);
  926. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  927. port_irq_disable(info, PVR_DSR);
  928. info->icount.dsr++;
  929. if (info->serial_signals & SerialSignal_DSR)
  930. info->input_signal_events.dsr_up++;
  931. else
  932. info->input_signal_events.dsr_down++;
  933. wake_up_interruptible(&info->status_event_wait_q);
  934. wake_up_interruptible(&info->event_wait_q);
  935. info->pending_bh |= BH_STATUS;
  936. }
  937. static void ri_change(MGSLPC_INFO *info)
  938. {
  939. get_signals(info);
  940. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  941. port_irq_disable(info, PVR_RI);
  942. info->icount.rng++;
  943. if (info->serial_signals & SerialSignal_RI)
  944. info->input_signal_events.ri_up++;
  945. else
  946. info->input_signal_events.ri_down++;
  947. wake_up_interruptible(&info->status_event_wait_q);
  948. wake_up_interruptible(&info->event_wait_q);
  949. info->pending_bh |= BH_STATUS;
  950. }
  951. /* Interrupt service routine entry point.
  952. *
  953. * Arguments:
  954. *
  955. * irq interrupt number that caused interrupt
  956. * dev_id device ID supplied during interrupt registration
  957. */
  958. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  959. {
  960. MGSLPC_INFO *info = dev_id;
  961. struct tty_struct *tty;
  962. unsigned short isr;
  963. unsigned char gis, pis;
  964. int count=0;
  965. if (debug_level >= DEBUG_LEVEL_ISR)
  966. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  967. if (!(info->p_dev->_locked))
  968. return IRQ_HANDLED;
  969. tty = tty_port_tty_get(&info->port);
  970. spin_lock(&info->lock);
  971. while ((gis = read_reg(info, CHA + GIS))) {
  972. if (debug_level >= DEBUG_LEVEL_ISR)
  973. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  974. if ((gis & 0x70) || count > 1000) {
  975. printk("synclink_cs:hardware failed or ejected\n");
  976. break;
  977. }
  978. count++;
  979. if (gis & (BIT1 + BIT0)) {
  980. isr = read_reg16(info, CHB + ISR);
  981. if (isr & IRQ_DCD)
  982. dcd_change(info, tty);
  983. if (isr & IRQ_CTS)
  984. cts_change(info, tty);
  985. }
  986. if (gis & (BIT3 + BIT2))
  987. {
  988. isr = read_reg16(info, CHA + ISR);
  989. if (isr & IRQ_TIMER) {
  990. info->irq_occurred = true;
  991. irq_disable(info, CHA, IRQ_TIMER);
  992. }
  993. /* receive IRQs */
  994. if (isr & IRQ_EXITHUNT) {
  995. info->icount.exithunt++;
  996. wake_up_interruptible(&info->event_wait_q);
  997. }
  998. if (isr & IRQ_BREAK_ON) {
  999. info->icount.brk++;
  1000. if (info->port.flags & ASYNC_SAK)
  1001. do_SAK(tty);
  1002. }
  1003. if (isr & IRQ_RXTIME) {
  1004. issue_command(info, CHA, CMD_RXFIFO_READ);
  1005. }
  1006. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1007. if (info->params.mode == MGSL_MODE_HDLC)
  1008. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1009. else
  1010. rx_ready_async(info, isr & IRQ_RXEOM, tty);
  1011. }
  1012. /* transmit IRQs */
  1013. if (isr & IRQ_UNDERRUN) {
  1014. if (info->tx_aborting)
  1015. info->icount.txabort++;
  1016. else
  1017. info->icount.txunder++;
  1018. tx_done(info, tty);
  1019. }
  1020. else if (isr & IRQ_ALLSENT) {
  1021. info->icount.txok++;
  1022. tx_done(info, tty);
  1023. }
  1024. else if (isr & IRQ_TXFIFO)
  1025. tx_ready(info, tty);
  1026. }
  1027. if (gis & BIT7) {
  1028. pis = read_reg(info, CHA + PIS);
  1029. if (pis & BIT1)
  1030. dsr_change(info);
  1031. if (pis & BIT2)
  1032. ri_change(info);
  1033. }
  1034. }
  1035. /* Request bottom half processing if there's something
  1036. * for it to do and the bh is not already running
  1037. */
  1038. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1039. if ( debug_level >= DEBUG_LEVEL_ISR )
  1040. printk("%s(%d):%s queueing bh task.\n",
  1041. __FILE__,__LINE__,info->device_name);
  1042. schedule_work(&info->task);
  1043. info->bh_requested = true;
  1044. }
  1045. spin_unlock(&info->lock);
  1046. tty_kref_put(tty);
  1047. if (debug_level >= DEBUG_LEVEL_ISR)
  1048. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1049. __FILE__, __LINE__, info->irq_level);
  1050. return IRQ_HANDLED;
  1051. }
  1052. /* Initialize and start device.
  1053. */
  1054. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1055. {
  1056. int retval = 0;
  1057. if (debug_level >= DEBUG_LEVEL_INFO)
  1058. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1059. if (info->port.flags & ASYNC_INITIALIZED)
  1060. return 0;
  1061. if (!info->tx_buf) {
  1062. /* allocate a page of memory for a transmit buffer */
  1063. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1064. if (!info->tx_buf) {
  1065. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1066. __FILE__,__LINE__,info->device_name);
  1067. return -ENOMEM;
  1068. }
  1069. }
  1070. info->pending_bh = 0;
  1071. memset(&info->icount, 0, sizeof(info->icount));
  1072. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1073. /* Allocate and claim adapter resources */
  1074. retval = claim_resources(info);
  1075. /* perform existence check and diagnostics */
  1076. if ( !retval )
  1077. retval = adapter_test(info);
  1078. if ( retval ) {
  1079. if (capable(CAP_SYS_ADMIN) && tty)
  1080. set_bit(TTY_IO_ERROR, &tty->flags);
  1081. release_resources(info);
  1082. return retval;
  1083. }
  1084. /* program hardware for current parameters */
  1085. mgslpc_change_params(info, tty);
  1086. if (tty)
  1087. clear_bit(TTY_IO_ERROR, &tty->flags);
  1088. info->port.flags |= ASYNC_INITIALIZED;
  1089. return 0;
  1090. }
  1091. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1092. */
  1093. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1094. {
  1095. unsigned long flags;
  1096. if (!(info->port.flags & ASYNC_INITIALIZED))
  1097. return;
  1098. if (debug_level >= DEBUG_LEVEL_INFO)
  1099. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1100. __FILE__,__LINE__, info->device_name );
  1101. /* clear status wait queue because status changes */
  1102. /* can't happen after shutting down the hardware */
  1103. wake_up_interruptible(&info->status_event_wait_q);
  1104. wake_up_interruptible(&info->event_wait_q);
  1105. del_timer_sync(&info->tx_timer);
  1106. if (info->tx_buf) {
  1107. free_page((unsigned long) info->tx_buf);
  1108. info->tx_buf = NULL;
  1109. }
  1110. spin_lock_irqsave(&info->lock,flags);
  1111. rx_stop(info);
  1112. tx_stop(info);
  1113. /* TODO:disable interrupts instead of reset to preserve signal states */
  1114. reset_device(info);
  1115. if (!tty || tty->termios->c_cflag & HUPCL) {
  1116. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1117. set_signals(info);
  1118. }
  1119. spin_unlock_irqrestore(&info->lock,flags);
  1120. release_resources(info);
  1121. if (tty)
  1122. set_bit(TTY_IO_ERROR, &tty->flags);
  1123. info->port.flags &= ~ASYNC_INITIALIZED;
  1124. }
  1125. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1126. {
  1127. unsigned long flags;
  1128. spin_lock_irqsave(&info->lock,flags);
  1129. rx_stop(info);
  1130. tx_stop(info);
  1131. info->tx_count = info->tx_put = info->tx_get = 0;
  1132. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1133. hdlc_mode(info);
  1134. else
  1135. async_mode(info);
  1136. set_signals(info);
  1137. info->dcd_chkcount = 0;
  1138. info->cts_chkcount = 0;
  1139. info->ri_chkcount = 0;
  1140. info->dsr_chkcount = 0;
  1141. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1142. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1143. get_signals(info);
  1144. if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
  1145. rx_start(info);
  1146. spin_unlock_irqrestore(&info->lock,flags);
  1147. }
  1148. /* Reconfigure adapter based on new parameters
  1149. */
  1150. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1151. {
  1152. unsigned cflag;
  1153. int bits_per_char;
  1154. if (!tty || !tty->termios)
  1155. return;
  1156. if (debug_level >= DEBUG_LEVEL_INFO)
  1157. printk("%s(%d):mgslpc_change_params(%s)\n",
  1158. __FILE__,__LINE__, info->device_name );
  1159. cflag = tty->termios->c_cflag;
  1160. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1161. /* otherwise assert DTR and RTS */
  1162. if (cflag & CBAUD)
  1163. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1164. else
  1165. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1166. /* byte size and parity */
  1167. switch (cflag & CSIZE) {
  1168. case CS5: info->params.data_bits = 5; break;
  1169. case CS6: info->params.data_bits = 6; break;
  1170. case CS7: info->params.data_bits = 7; break;
  1171. case CS8: info->params.data_bits = 8; break;
  1172. default: info->params.data_bits = 7; break;
  1173. }
  1174. if (cflag & CSTOPB)
  1175. info->params.stop_bits = 2;
  1176. else
  1177. info->params.stop_bits = 1;
  1178. info->params.parity = ASYNC_PARITY_NONE;
  1179. if (cflag & PARENB) {
  1180. if (cflag & PARODD)
  1181. info->params.parity = ASYNC_PARITY_ODD;
  1182. else
  1183. info->params.parity = ASYNC_PARITY_EVEN;
  1184. #ifdef CMSPAR
  1185. if (cflag & CMSPAR)
  1186. info->params.parity = ASYNC_PARITY_SPACE;
  1187. #endif
  1188. }
  1189. /* calculate number of jiffies to transmit a full
  1190. * FIFO (32 bytes) at specified data rate
  1191. */
  1192. bits_per_char = info->params.data_bits +
  1193. info->params.stop_bits + 1;
  1194. /* if port data rate is set to 460800 or less then
  1195. * allow tty settings to override, otherwise keep the
  1196. * current data rate.
  1197. */
  1198. if (info->params.data_rate <= 460800) {
  1199. info->params.data_rate = tty_get_baud_rate(tty);
  1200. }
  1201. if ( info->params.data_rate ) {
  1202. info->timeout = (32*HZ*bits_per_char) /
  1203. info->params.data_rate;
  1204. }
  1205. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1206. if (cflag & CRTSCTS)
  1207. info->port.flags |= ASYNC_CTS_FLOW;
  1208. else
  1209. info->port.flags &= ~ASYNC_CTS_FLOW;
  1210. if (cflag & CLOCAL)
  1211. info->port.flags &= ~ASYNC_CHECK_CD;
  1212. else
  1213. info->port.flags |= ASYNC_CHECK_CD;
  1214. /* process tty input control flags */
  1215. info->read_status_mask = 0;
  1216. if (I_INPCK(tty))
  1217. info->read_status_mask |= BIT7 | BIT6;
  1218. if (I_IGNPAR(tty))
  1219. info->ignore_status_mask |= BIT7 | BIT6;
  1220. mgslpc_program_hw(info, tty);
  1221. }
  1222. /* Add a character to the transmit buffer
  1223. */
  1224. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1225. {
  1226. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1227. unsigned long flags;
  1228. if (debug_level >= DEBUG_LEVEL_INFO) {
  1229. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1230. __FILE__,__LINE__,ch,info->device_name);
  1231. }
  1232. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1233. return 0;
  1234. if (!info->tx_buf)
  1235. return 0;
  1236. spin_lock_irqsave(&info->lock,flags);
  1237. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1238. if (info->tx_count < TXBUFSIZE - 1) {
  1239. info->tx_buf[info->tx_put++] = ch;
  1240. info->tx_put &= TXBUFSIZE-1;
  1241. info->tx_count++;
  1242. }
  1243. }
  1244. spin_unlock_irqrestore(&info->lock,flags);
  1245. return 1;
  1246. }
  1247. /* Enable transmitter so remaining characters in the
  1248. * transmit buffer are sent.
  1249. */
  1250. static void mgslpc_flush_chars(struct tty_struct *tty)
  1251. {
  1252. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1253. unsigned long flags;
  1254. if (debug_level >= DEBUG_LEVEL_INFO)
  1255. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1256. __FILE__,__LINE__,info->device_name,info->tx_count);
  1257. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1258. return;
  1259. if (info->tx_count <= 0 || tty->stopped ||
  1260. tty->hw_stopped || !info->tx_buf)
  1261. return;
  1262. if (debug_level >= DEBUG_LEVEL_INFO)
  1263. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1264. __FILE__,__LINE__,info->device_name);
  1265. spin_lock_irqsave(&info->lock,flags);
  1266. if (!info->tx_active)
  1267. tx_start(info, tty);
  1268. spin_unlock_irqrestore(&info->lock,flags);
  1269. }
  1270. /* Send a block of data
  1271. *
  1272. * Arguments:
  1273. *
  1274. * tty pointer to tty information structure
  1275. * buf pointer to buffer containing send data
  1276. * count size of send data in bytes
  1277. *
  1278. * Returns: number of characters written
  1279. */
  1280. static int mgslpc_write(struct tty_struct * tty,
  1281. const unsigned char *buf, int count)
  1282. {
  1283. int c, ret = 0;
  1284. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1285. unsigned long flags;
  1286. if (debug_level >= DEBUG_LEVEL_INFO)
  1287. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1288. __FILE__,__LINE__,info->device_name,count);
  1289. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1290. !info->tx_buf)
  1291. goto cleanup;
  1292. if (info->params.mode == MGSL_MODE_HDLC) {
  1293. if (count > TXBUFSIZE) {
  1294. ret = -EIO;
  1295. goto cleanup;
  1296. }
  1297. if (info->tx_active)
  1298. goto cleanup;
  1299. else if (info->tx_count)
  1300. goto start;
  1301. }
  1302. for (;;) {
  1303. c = min(count,
  1304. min(TXBUFSIZE - info->tx_count - 1,
  1305. TXBUFSIZE - info->tx_put));
  1306. if (c <= 0)
  1307. break;
  1308. memcpy(info->tx_buf + info->tx_put, buf, c);
  1309. spin_lock_irqsave(&info->lock,flags);
  1310. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1311. info->tx_count += c;
  1312. spin_unlock_irqrestore(&info->lock,flags);
  1313. buf += c;
  1314. count -= c;
  1315. ret += c;
  1316. }
  1317. start:
  1318. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1319. spin_lock_irqsave(&info->lock,flags);
  1320. if (!info->tx_active)
  1321. tx_start(info, tty);
  1322. spin_unlock_irqrestore(&info->lock,flags);
  1323. }
  1324. cleanup:
  1325. if (debug_level >= DEBUG_LEVEL_INFO)
  1326. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1327. __FILE__,__LINE__,info->device_name,ret);
  1328. return ret;
  1329. }
  1330. /* Return the count of free bytes in transmit buffer
  1331. */
  1332. static int mgslpc_write_room(struct tty_struct *tty)
  1333. {
  1334. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1335. int ret;
  1336. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1337. return 0;
  1338. if (info->params.mode == MGSL_MODE_HDLC) {
  1339. /* HDLC (frame oriented) mode */
  1340. if (info->tx_active)
  1341. return 0;
  1342. else
  1343. return HDLC_MAX_FRAME_SIZE;
  1344. } else {
  1345. ret = TXBUFSIZE - info->tx_count - 1;
  1346. if (ret < 0)
  1347. ret = 0;
  1348. }
  1349. if (debug_level >= DEBUG_LEVEL_INFO)
  1350. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1351. __FILE__,__LINE__, info->device_name, ret);
  1352. return ret;
  1353. }
  1354. /* Return the count of bytes in transmit buffer
  1355. */
  1356. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1357. {
  1358. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1359. int rc;
  1360. if (debug_level >= DEBUG_LEVEL_INFO)
  1361. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1362. __FILE__,__LINE__, info->device_name );
  1363. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1364. return 0;
  1365. if (info->params.mode == MGSL_MODE_HDLC)
  1366. rc = info->tx_active ? info->max_frame_size : 0;
  1367. else
  1368. rc = info->tx_count;
  1369. if (debug_level >= DEBUG_LEVEL_INFO)
  1370. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1371. __FILE__,__LINE__, info->device_name, rc);
  1372. return rc;
  1373. }
  1374. /* Discard all data in the send buffer
  1375. */
  1376. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1377. {
  1378. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1379. unsigned long flags;
  1380. if (debug_level >= DEBUG_LEVEL_INFO)
  1381. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1382. __FILE__,__LINE__, info->device_name );
  1383. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1384. return;
  1385. spin_lock_irqsave(&info->lock,flags);
  1386. info->tx_count = info->tx_put = info->tx_get = 0;
  1387. del_timer(&info->tx_timer);
  1388. spin_unlock_irqrestore(&info->lock,flags);
  1389. wake_up_interruptible(&tty->write_wait);
  1390. tty_wakeup(tty);
  1391. }
  1392. /* Send a high-priority XON/XOFF character
  1393. */
  1394. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1395. {
  1396. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1397. unsigned long flags;
  1398. if (debug_level >= DEBUG_LEVEL_INFO)
  1399. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1400. __FILE__,__LINE__, info->device_name, ch );
  1401. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1402. return;
  1403. info->x_char = ch;
  1404. if (ch) {
  1405. spin_lock_irqsave(&info->lock,flags);
  1406. if (!info->tx_enabled)
  1407. tx_start(info, tty);
  1408. spin_unlock_irqrestore(&info->lock,flags);
  1409. }
  1410. }
  1411. /* Signal remote device to throttle send data (our receive data)
  1412. */
  1413. static void mgslpc_throttle(struct tty_struct * tty)
  1414. {
  1415. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1416. unsigned long flags;
  1417. if (debug_level >= DEBUG_LEVEL_INFO)
  1418. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1419. __FILE__,__LINE__, info->device_name );
  1420. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1421. return;
  1422. if (I_IXOFF(tty))
  1423. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1424. if (tty->termios->c_cflag & CRTSCTS) {
  1425. spin_lock_irqsave(&info->lock,flags);
  1426. info->serial_signals &= ~SerialSignal_RTS;
  1427. set_signals(info);
  1428. spin_unlock_irqrestore(&info->lock,flags);
  1429. }
  1430. }
  1431. /* Signal remote device to stop throttling send data (our receive data)
  1432. */
  1433. static void mgslpc_unthrottle(struct tty_struct * tty)
  1434. {
  1435. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1436. unsigned long flags;
  1437. if (debug_level >= DEBUG_LEVEL_INFO)
  1438. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1439. __FILE__,__LINE__, info->device_name );
  1440. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1441. return;
  1442. if (I_IXOFF(tty)) {
  1443. if (info->x_char)
  1444. info->x_char = 0;
  1445. else
  1446. mgslpc_send_xchar(tty, START_CHAR(tty));
  1447. }
  1448. if (tty->termios->c_cflag & CRTSCTS) {
  1449. spin_lock_irqsave(&info->lock,flags);
  1450. info->serial_signals |= SerialSignal_RTS;
  1451. set_signals(info);
  1452. spin_unlock_irqrestore(&info->lock,flags);
  1453. }
  1454. }
  1455. /* get the current serial statistics
  1456. */
  1457. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1458. {
  1459. int err;
  1460. if (debug_level >= DEBUG_LEVEL_INFO)
  1461. printk("get_params(%s)\n", info->device_name);
  1462. if (!user_icount) {
  1463. memset(&info->icount, 0, sizeof(info->icount));
  1464. } else {
  1465. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1466. if (err)
  1467. return -EFAULT;
  1468. }
  1469. return 0;
  1470. }
  1471. /* get the current serial parameters
  1472. */
  1473. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1474. {
  1475. int err;
  1476. if (debug_level >= DEBUG_LEVEL_INFO)
  1477. printk("get_params(%s)\n", info->device_name);
  1478. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1479. if (err)
  1480. return -EFAULT;
  1481. return 0;
  1482. }
  1483. /* set the serial parameters
  1484. *
  1485. * Arguments:
  1486. *
  1487. * info pointer to device instance data
  1488. * new_params user buffer containing new serial params
  1489. *
  1490. * Returns: 0 if success, otherwise error code
  1491. */
  1492. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1493. {
  1494. unsigned long flags;
  1495. MGSL_PARAMS tmp_params;
  1496. int err;
  1497. if (debug_level >= DEBUG_LEVEL_INFO)
  1498. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1499. info->device_name );
  1500. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1501. if (err) {
  1502. if ( debug_level >= DEBUG_LEVEL_INFO )
  1503. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1504. __FILE__,__LINE__,info->device_name);
  1505. return -EFAULT;
  1506. }
  1507. spin_lock_irqsave(&info->lock,flags);
  1508. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1509. spin_unlock_irqrestore(&info->lock,flags);
  1510. mgslpc_change_params(info, tty);
  1511. return 0;
  1512. }
  1513. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1514. {
  1515. int err;
  1516. if (debug_level >= DEBUG_LEVEL_INFO)
  1517. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1518. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1519. if (err)
  1520. return -EFAULT;
  1521. return 0;
  1522. }
  1523. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1524. {
  1525. unsigned long flags;
  1526. if (debug_level >= DEBUG_LEVEL_INFO)
  1527. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1528. spin_lock_irqsave(&info->lock,flags);
  1529. info->idle_mode = idle_mode;
  1530. tx_set_idle(info);
  1531. spin_unlock_irqrestore(&info->lock,flags);
  1532. return 0;
  1533. }
  1534. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1535. {
  1536. int err;
  1537. if (debug_level >= DEBUG_LEVEL_INFO)
  1538. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1539. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1540. if (err)
  1541. return -EFAULT;
  1542. return 0;
  1543. }
  1544. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1545. {
  1546. unsigned long flags;
  1547. unsigned char val;
  1548. if (debug_level >= DEBUG_LEVEL_INFO)
  1549. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1550. spin_lock_irqsave(&info->lock,flags);
  1551. info->if_mode = if_mode;
  1552. val = read_reg(info, PVR) & 0x0f;
  1553. switch (info->if_mode)
  1554. {
  1555. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1556. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1557. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1558. }
  1559. write_reg(info, PVR, val);
  1560. spin_unlock_irqrestore(&info->lock,flags);
  1561. return 0;
  1562. }
  1563. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1564. {
  1565. unsigned long flags;
  1566. if (debug_level >= DEBUG_LEVEL_INFO)
  1567. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1568. spin_lock_irqsave(&info->lock,flags);
  1569. if (enable) {
  1570. if (!info->tx_enabled)
  1571. tx_start(info, tty);
  1572. } else {
  1573. if (info->tx_enabled)
  1574. tx_stop(info);
  1575. }
  1576. spin_unlock_irqrestore(&info->lock,flags);
  1577. return 0;
  1578. }
  1579. static int tx_abort(MGSLPC_INFO * info)
  1580. {
  1581. unsigned long flags;
  1582. if (debug_level >= DEBUG_LEVEL_INFO)
  1583. printk("tx_abort(%s)\n", info->device_name);
  1584. spin_lock_irqsave(&info->lock,flags);
  1585. if (info->tx_active && info->tx_count &&
  1586. info->params.mode == MGSL_MODE_HDLC) {
  1587. /* clear data count so FIFO is not filled on next IRQ.
  1588. * This results in underrun and abort transmission.
  1589. */
  1590. info->tx_count = info->tx_put = info->tx_get = 0;
  1591. info->tx_aborting = true;
  1592. }
  1593. spin_unlock_irqrestore(&info->lock,flags);
  1594. return 0;
  1595. }
  1596. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1597. {
  1598. unsigned long flags;
  1599. if (debug_level >= DEBUG_LEVEL_INFO)
  1600. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1601. spin_lock_irqsave(&info->lock,flags);
  1602. if (enable) {
  1603. if (!info->rx_enabled)
  1604. rx_start(info);
  1605. } else {
  1606. if (info->rx_enabled)
  1607. rx_stop(info);
  1608. }
  1609. spin_unlock_irqrestore(&info->lock,flags);
  1610. return 0;
  1611. }
  1612. /* wait for specified event to occur
  1613. *
  1614. * Arguments: info pointer to device instance data
  1615. * mask pointer to bitmask of events to wait for
  1616. * Return Value: 0 if successful and bit mask updated with
  1617. * of events triggerred,
  1618. * otherwise error code
  1619. */
  1620. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1621. {
  1622. unsigned long flags;
  1623. int s;
  1624. int rc=0;
  1625. struct mgsl_icount cprev, cnow;
  1626. int events;
  1627. int mask;
  1628. struct _input_signal_events oldsigs, newsigs;
  1629. DECLARE_WAITQUEUE(wait, current);
  1630. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1631. if (rc)
  1632. return -EFAULT;
  1633. if (debug_level >= DEBUG_LEVEL_INFO)
  1634. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1635. spin_lock_irqsave(&info->lock,flags);
  1636. /* return immediately if state matches requested events */
  1637. get_signals(info);
  1638. s = info->serial_signals;
  1639. events = mask &
  1640. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1641. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1642. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1643. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1644. if (events) {
  1645. spin_unlock_irqrestore(&info->lock,flags);
  1646. goto exit;
  1647. }
  1648. /* save current irq counts */
  1649. cprev = info->icount;
  1650. oldsigs = info->input_signal_events;
  1651. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1652. (mask & MgslEvent_ExitHuntMode))
  1653. irq_enable(info, CHA, IRQ_EXITHUNT);
  1654. set_current_state(TASK_INTERRUPTIBLE);
  1655. add_wait_queue(&info->event_wait_q, &wait);
  1656. spin_unlock_irqrestore(&info->lock,flags);
  1657. for(;;) {
  1658. schedule();
  1659. if (signal_pending(current)) {
  1660. rc = -ERESTARTSYS;
  1661. break;
  1662. }
  1663. /* get current irq counts */
  1664. spin_lock_irqsave(&info->lock,flags);
  1665. cnow = info->icount;
  1666. newsigs = info->input_signal_events;
  1667. set_current_state(TASK_INTERRUPTIBLE);
  1668. spin_unlock_irqrestore(&info->lock,flags);
  1669. /* if no change, wait aborted for some reason */
  1670. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1671. newsigs.dsr_down == oldsigs.dsr_down &&
  1672. newsigs.dcd_up == oldsigs.dcd_up &&
  1673. newsigs.dcd_down == oldsigs.dcd_down &&
  1674. newsigs.cts_up == oldsigs.cts_up &&
  1675. newsigs.cts_down == oldsigs.cts_down &&
  1676. newsigs.ri_up == oldsigs.ri_up &&
  1677. newsigs.ri_down == oldsigs.ri_down &&
  1678. cnow.exithunt == cprev.exithunt &&
  1679. cnow.rxidle == cprev.rxidle) {
  1680. rc = -EIO;
  1681. break;
  1682. }
  1683. events = mask &
  1684. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1685. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1686. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1687. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1688. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1689. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1690. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1691. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1692. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1693. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1694. if (events)
  1695. break;
  1696. cprev = cnow;
  1697. oldsigs = newsigs;
  1698. }
  1699. remove_wait_queue(&info->event_wait_q, &wait);
  1700. set_current_state(TASK_RUNNING);
  1701. if (mask & MgslEvent_ExitHuntMode) {
  1702. spin_lock_irqsave(&info->lock,flags);
  1703. if (!waitqueue_active(&info->event_wait_q))
  1704. irq_disable(info, CHA, IRQ_EXITHUNT);
  1705. spin_unlock_irqrestore(&info->lock,flags);
  1706. }
  1707. exit:
  1708. if (rc == 0)
  1709. PUT_USER(rc, events, mask_ptr);
  1710. return rc;
  1711. }
  1712. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1713. {
  1714. unsigned long flags;
  1715. int rc;
  1716. struct mgsl_icount cprev, cnow;
  1717. DECLARE_WAITQUEUE(wait, current);
  1718. /* save current irq counts */
  1719. spin_lock_irqsave(&info->lock,flags);
  1720. cprev = info->icount;
  1721. add_wait_queue(&info->status_event_wait_q, &wait);
  1722. set_current_state(TASK_INTERRUPTIBLE);
  1723. spin_unlock_irqrestore(&info->lock,flags);
  1724. for(;;) {
  1725. schedule();
  1726. if (signal_pending(current)) {
  1727. rc = -ERESTARTSYS;
  1728. break;
  1729. }
  1730. /* get new irq counts */
  1731. spin_lock_irqsave(&info->lock,flags);
  1732. cnow = info->icount;
  1733. set_current_state(TASK_INTERRUPTIBLE);
  1734. spin_unlock_irqrestore(&info->lock,flags);
  1735. /* if no change, wait aborted for some reason */
  1736. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1737. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1738. rc = -EIO;
  1739. break;
  1740. }
  1741. /* check for change in caller specified modem input */
  1742. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1743. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1744. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1745. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1746. rc = 0;
  1747. break;
  1748. }
  1749. cprev = cnow;
  1750. }
  1751. remove_wait_queue(&info->status_event_wait_q, &wait);
  1752. set_current_state(TASK_RUNNING);
  1753. return rc;
  1754. }
  1755. /* return the state of the serial control and status signals
  1756. */
  1757. static int tiocmget(struct tty_struct *tty)
  1758. {
  1759. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1760. unsigned int result;
  1761. unsigned long flags;
  1762. spin_lock_irqsave(&info->lock,flags);
  1763. get_signals(info);
  1764. spin_unlock_irqrestore(&info->lock,flags);
  1765. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1766. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1767. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1768. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1769. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1770. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1771. if (debug_level >= DEBUG_LEVEL_INFO)
  1772. printk("%s(%d):%s tiocmget() value=%08X\n",
  1773. __FILE__,__LINE__, info->device_name, result );
  1774. return result;
  1775. }
  1776. /* set modem control signals (DTR/RTS)
  1777. */
  1778. static int tiocmset(struct tty_struct *tty,
  1779. unsigned int set, unsigned int clear)
  1780. {
  1781. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1782. unsigned long flags;
  1783. if (debug_level >= DEBUG_LEVEL_INFO)
  1784. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1785. __FILE__,__LINE__,info->device_name, set, clear);
  1786. if (set & TIOCM_RTS)
  1787. info->serial_signals |= SerialSignal_RTS;
  1788. if (set & TIOCM_DTR)
  1789. info->serial_signals |= SerialSignal_DTR;
  1790. if (clear & TIOCM_RTS)
  1791. info->serial_signals &= ~SerialSignal_RTS;
  1792. if (clear & TIOCM_DTR)
  1793. info->serial_signals &= ~SerialSignal_DTR;
  1794. spin_lock_irqsave(&info->lock,flags);
  1795. set_signals(info);
  1796. spin_unlock_irqrestore(&info->lock,flags);
  1797. return 0;
  1798. }
  1799. /* Set or clear transmit break condition
  1800. *
  1801. * Arguments: tty pointer to tty instance data
  1802. * break_state -1=set break condition, 0=clear
  1803. */
  1804. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1805. {
  1806. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1807. unsigned long flags;
  1808. if (debug_level >= DEBUG_LEVEL_INFO)
  1809. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1810. __FILE__,__LINE__, info->device_name, break_state);
  1811. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1812. return -EINVAL;
  1813. spin_lock_irqsave(&info->lock,flags);
  1814. if (break_state == -1)
  1815. set_reg_bits(info, CHA+DAFO, BIT6);
  1816. else
  1817. clear_reg_bits(info, CHA+DAFO, BIT6);
  1818. spin_unlock_irqrestore(&info->lock,flags);
  1819. return 0;
  1820. }
  1821. static int mgslpc_get_icount(struct tty_struct *tty,
  1822. struct serial_icounter_struct *icount)
  1823. {
  1824. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1825. struct mgsl_icount cnow; /* kernel counter temps */
  1826. unsigned long flags;
  1827. spin_lock_irqsave(&info->lock,flags);
  1828. cnow = info->icount;
  1829. spin_unlock_irqrestore(&info->lock,flags);
  1830. icount->cts = cnow.cts;
  1831. icount->dsr = cnow.dsr;
  1832. icount->rng = cnow.rng;
  1833. icount->dcd = cnow.dcd;
  1834. icount->rx = cnow.rx;
  1835. icount->tx = cnow.tx;
  1836. icount->frame = cnow.frame;
  1837. icount->overrun = cnow.overrun;
  1838. icount->parity = cnow.parity;
  1839. icount->brk = cnow.brk;
  1840. icount->buf_overrun = cnow.buf_overrun;
  1841. return 0;
  1842. }
  1843. /* Service an IOCTL request
  1844. *
  1845. * Arguments:
  1846. *
  1847. * tty pointer to tty instance data
  1848. * cmd IOCTL command code
  1849. * arg command argument/context
  1850. *
  1851. * Return Value: 0 if success, otherwise error code
  1852. */
  1853. static int mgslpc_ioctl(struct tty_struct *tty,
  1854. unsigned int cmd, unsigned long arg)
  1855. {
  1856. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1857. void __user *argp = (void __user *)arg;
  1858. if (debug_level >= DEBUG_LEVEL_INFO)
  1859. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1860. info->device_name, cmd );
  1861. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1862. return -ENODEV;
  1863. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1864. (cmd != TIOCMIWAIT)) {
  1865. if (tty->flags & (1 << TTY_IO_ERROR))
  1866. return -EIO;
  1867. }
  1868. switch (cmd) {
  1869. case MGSL_IOCGPARAMS:
  1870. return get_params(info, argp);
  1871. case MGSL_IOCSPARAMS:
  1872. return set_params(info, argp, tty);
  1873. case MGSL_IOCGTXIDLE:
  1874. return get_txidle(info, argp);
  1875. case MGSL_IOCSTXIDLE:
  1876. return set_txidle(info, (int)arg);
  1877. case MGSL_IOCGIF:
  1878. return get_interface(info, argp);
  1879. case MGSL_IOCSIF:
  1880. return set_interface(info,(int)arg);
  1881. case MGSL_IOCTXENABLE:
  1882. return set_txenable(info,(int)arg, tty);
  1883. case MGSL_IOCRXENABLE:
  1884. return set_rxenable(info,(int)arg);
  1885. case MGSL_IOCTXABORT:
  1886. return tx_abort(info);
  1887. case MGSL_IOCGSTATS:
  1888. return get_stats(info, argp);
  1889. case MGSL_IOCWAITEVENT:
  1890. return wait_events(info, argp);
  1891. case TIOCMIWAIT:
  1892. return modem_input_wait(info,(int)arg);
  1893. default:
  1894. return -ENOIOCTLCMD;
  1895. }
  1896. return 0;
  1897. }
  1898. /* Set new termios settings
  1899. *
  1900. * Arguments:
  1901. *
  1902. * tty pointer to tty structure
  1903. * termios pointer to buffer to hold returned old termios
  1904. */
  1905. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1906. {
  1907. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1908. unsigned long flags;
  1909. if (debug_level >= DEBUG_LEVEL_INFO)
  1910. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  1911. tty->driver->name );
  1912. /* just return if nothing has changed */
  1913. if ((tty->termios->c_cflag == old_termios->c_cflag)
  1914. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  1915. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1916. return;
  1917. mgslpc_change_params(info, tty);
  1918. /* Handle transition to B0 status */
  1919. if (old_termios->c_cflag & CBAUD &&
  1920. !(tty->termios->c_cflag & CBAUD)) {
  1921. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1922. spin_lock_irqsave(&info->lock,flags);
  1923. set_signals(info);
  1924. spin_unlock_irqrestore(&info->lock,flags);
  1925. }
  1926. /* Handle transition away from B0 status */
  1927. if (!(old_termios->c_cflag & CBAUD) &&
  1928. tty->termios->c_cflag & CBAUD) {
  1929. info->serial_signals |= SerialSignal_DTR;
  1930. if (!(tty->termios->c_cflag & CRTSCTS) ||
  1931. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1932. info->serial_signals |= SerialSignal_RTS;
  1933. }
  1934. spin_lock_irqsave(&info->lock,flags);
  1935. set_signals(info);
  1936. spin_unlock_irqrestore(&info->lock,flags);
  1937. }
  1938. /* Handle turning off CRTSCTS */
  1939. if (old_termios->c_cflag & CRTSCTS &&
  1940. !(tty->termios->c_cflag & CRTSCTS)) {
  1941. tty->hw_stopped = 0;
  1942. tx_release(tty);
  1943. }
  1944. }
  1945. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1946. {
  1947. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1948. struct tty_port *port = &info->port;
  1949. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1950. return;
  1951. if (debug_level >= DEBUG_LEVEL_INFO)
  1952. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1953. __FILE__,__LINE__, info->device_name, port->count);
  1954. WARN_ON(!port->count);
  1955. if (tty_port_close_start(port, tty, filp) == 0)
  1956. goto cleanup;
  1957. if (port->flags & ASYNC_INITIALIZED)
  1958. mgslpc_wait_until_sent(tty, info->timeout);
  1959. mgslpc_flush_buffer(tty);
  1960. tty_ldisc_flush(tty);
  1961. shutdown(info, tty);
  1962. tty_port_close_end(port, tty);
  1963. tty_port_tty_set(port, NULL);
  1964. cleanup:
  1965. if (debug_level >= DEBUG_LEVEL_INFO)
  1966. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  1967. tty->driver->name, port->count);
  1968. }
  1969. /* Wait until the transmitter is empty.
  1970. */
  1971. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  1972. {
  1973. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1974. unsigned long orig_jiffies, char_time;
  1975. if (!info )
  1976. return;
  1977. if (debug_level >= DEBUG_LEVEL_INFO)
  1978. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  1979. __FILE__,__LINE__, info->device_name );
  1980. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  1981. return;
  1982. if (!(info->port.flags & ASYNC_INITIALIZED))
  1983. goto exit;
  1984. orig_jiffies = jiffies;
  1985. /* Set check interval to 1/5 of estimated time to
  1986. * send a character, and make it at least 1. The check
  1987. * interval should also be less than the timeout.
  1988. * Note: use tight timings here to satisfy the NIST-PCTS.
  1989. */
  1990. if ( info->params.data_rate ) {
  1991. char_time = info->timeout/(32 * 5);
  1992. if (!char_time)
  1993. char_time++;
  1994. } else
  1995. char_time = 1;
  1996. if (timeout)
  1997. char_time = min_t(unsigned long, char_time, timeout);
  1998. if (info->params.mode == MGSL_MODE_HDLC) {
  1999. while (info->tx_active) {
  2000. msleep_interruptible(jiffies_to_msecs(char_time));
  2001. if (signal_pending(current))
  2002. break;
  2003. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2004. break;
  2005. }
  2006. } else {
  2007. while ((info->tx_count || info->tx_active) &&
  2008. info->tx_enabled) {
  2009. msleep_interruptible(jiffies_to_msecs(char_time));
  2010. if (signal_pending(current))
  2011. break;
  2012. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2013. break;
  2014. }
  2015. }
  2016. exit:
  2017. if (debug_level >= DEBUG_LEVEL_INFO)
  2018. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2019. __FILE__,__LINE__, info->device_name );
  2020. }
  2021. /* Called by tty_hangup() when a hangup is signaled.
  2022. * This is the same as closing all open files for the port.
  2023. */
  2024. static void mgslpc_hangup(struct tty_struct *tty)
  2025. {
  2026. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2027. if (debug_level >= DEBUG_LEVEL_INFO)
  2028. printk("%s(%d):mgslpc_hangup(%s)\n",
  2029. __FILE__,__LINE__, info->device_name );
  2030. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2031. return;
  2032. mgslpc_flush_buffer(tty);
  2033. shutdown(info, tty);
  2034. tty_port_hangup(&info->port);
  2035. }
  2036. static int carrier_raised(struct tty_port *port)
  2037. {
  2038. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2039. unsigned long flags;
  2040. spin_lock_irqsave(&info->lock,flags);
  2041. get_signals(info);
  2042. spin_unlock_irqrestore(&info->lock,flags);
  2043. if (info->serial_signals & SerialSignal_DCD)
  2044. return 1;
  2045. return 0;
  2046. }
  2047. static void dtr_rts(struct tty_port *port, int onoff)
  2048. {
  2049. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2050. unsigned long flags;
  2051. spin_lock_irqsave(&info->lock,flags);
  2052. if (onoff)
  2053. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2054. else
  2055. info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
  2056. set_signals(info);
  2057. spin_unlock_irqrestore(&info->lock,flags);
  2058. }
  2059. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2060. {
  2061. MGSLPC_INFO *info;
  2062. struct tty_port *port;
  2063. int retval, line;
  2064. unsigned long flags;
  2065. /* verify range of specified line number */
  2066. line = tty->index;
  2067. if ((line < 0) || (line >= mgslpc_device_count)) {
  2068. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2069. __FILE__,__LINE__,line);
  2070. return -ENODEV;
  2071. }
  2072. /* find the info structure for the specified line */
  2073. info = mgslpc_device_list;
  2074. while(info && info->line != line)
  2075. info = info->next_device;
  2076. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2077. return -ENODEV;
  2078. port = &info->port;
  2079. tty->driver_data = info;
  2080. tty_port_tty_set(port, tty);
  2081. if (debug_level >= DEBUG_LEVEL_INFO)
  2082. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2083. __FILE__,__LINE__,tty->driver->name, port->count);
  2084. /* If port is closing, signal caller to try again */
  2085. if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
  2086. if (port->flags & ASYNC_CLOSING)
  2087. interruptible_sleep_on(&port->close_wait);
  2088. retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
  2089. -EAGAIN : -ERESTARTSYS);
  2090. goto cleanup;
  2091. }
  2092. tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2093. spin_lock_irqsave(&info->netlock, flags);
  2094. if (info->netcount) {
  2095. retval = -EBUSY;
  2096. spin_unlock_irqrestore(&info->netlock, flags);
  2097. goto cleanup;
  2098. }
  2099. spin_lock(&port->lock);
  2100. port->count++;
  2101. spin_unlock(&port->lock);
  2102. spin_unlock_irqrestore(&info->netlock, flags);
  2103. if (port->count == 1) {
  2104. /* 1st open on this device, init hardware */
  2105. retval = startup(info, tty);
  2106. if (retval < 0)
  2107. goto cleanup;
  2108. }
  2109. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2110. if (retval) {
  2111. if (debug_level >= DEBUG_LEVEL_INFO)
  2112. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2113. __FILE__,__LINE__, info->device_name, retval);
  2114. goto cleanup;
  2115. }
  2116. if (debug_level >= DEBUG_LEVEL_INFO)
  2117. printk("%s(%d):mgslpc_open(%s) success\n",
  2118. __FILE__,__LINE__, info->device_name);
  2119. retval = 0;
  2120. cleanup:
  2121. return retval;
  2122. }
  2123. /*
  2124. * /proc fs routines....
  2125. */
  2126. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2127. {
  2128. char stat_buf[30];
  2129. unsigned long flags;
  2130. seq_printf(m, "%s:io:%04X irq:%d",
  2131. info->device_name, info->io_base, info->irq_level);
  2132. /* output current serial signal states */
  2133. spin_lock_irqsave(&info->lock,flags);
  2134. get_signals(info);
  2135. spin_unlock_irqrestore(&info->lock,flags);
  2136. stat_buf[0] = 0;
  2137. stat_buf[1] = 0;
  2138. if (info->serial_signals & SerialSignal_RTS)
  2139. strcat(stat_buf, "|RTS");
  2140. if (info->serial_signals & SerialSignal_CTS)
  2141. strcat(stat_buf, "|CTS");
  2142. if (info->serial_signals & SerialSignal_DTR)
  2143. strcat(stat_buf, "|DTR");
  2144. if (info->serial_signals & SerialSignal_DSR)
  2145. strcat(stat_buf, "|DSR");
  2146. if (info->serial_signals & SerialSignal_DCD)
  2147. strcat(stat_buf, "|CD");
  2148. if (info->serial_signals & SerialSignal_RI)
  2149. strcat(stat_buf, "|RI");
  2150. if (info->params.mode == MGSL_MODE_HDLC) {
  2151. seq_printf(m, " HDLC txok:%d rxok:%d",
  2152. info->icount.txok, info->icount.rxok);
  2153. if (info->icount.txunder)
  2154. seq_printf(m, " txunder:%d", info->icount.txunder);
  2155. if (info->icount.txabort)
  2156. seq_printf(m, " txabort:%d", info->icount.txabort);
  2157. if (info->icount.rxshort)
  2158. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2159. if (info->icount.rxlong)
  2160. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2161. if (info->icount.rxover)
  2162. seq_printf(m, " rxover:%d", info->icount.rxover);
  2163. if (info->icount.rxcrc)
  2164. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2165. } else {
  2166. seq_printf(m, " ASYNC tx:%d rx:%d",
  2167. info->icount.tx, info->icount.rx);
  2168. if (info->icount.frame)
  2169. seq_printf(m, " fe:%d", info->icount.frame);
  2170. if (info->icount.parity)
  2171. seq_printf(m, " pe:%d", info->icount.parity);
  2172. if (info->icount.brk)
  2173. seq_printf(m, " brk:%d", info->icount.brk);
  2174. if (info->icount.overrun)
  2175. seq_printf(m, " oe:%d", info->icount.overrun);
  2176. }
  2177. /* Append serial signal status to end */
  2178. seq_printf(m, " %s\n", stat_buf+1);
  2179. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2180. info->tx_active,info->bh_requested,info->bh_running,
  2181. info->pending_bh);
  2182. }
  2183. /* Called to print information about devices
  2184. */
  2185. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2186. {
  2187. MGSLPC_INFO *info;
  2188. seq_printf(m, "synclink driver:%s\n", driver_version);
  2189. info = mgslpc_device_list;
  2190. while( info ) {
  2191. line_info(m, info);
  2192. info = info->next_device;
  2193. }
  2194. return 0;
  2195. }
  2196. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2197. {
  2198. return single_open(file, mgslpc_proc_show, NULL);
  2199. }
  2200. static const struct file_operations mgslpc_proc_fops = {
  2201. .owner = THIS_MODULE,
  2202. .open = mgslpc_proc_open,
  2203. .read = seq_read,
  2204. .llseek = seq_lseek,
  2205. .release = single_release,
  2206. };
  2207. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2208. {
  2209. /* each buffer has header and data */
  2210. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2211. /* calculate total allocation size for 8 buffers */
  2212. info->rx_buf_total_size = info->rx_buf_size * 8;
  2213. /* limit total allocated memory */
  2214. if (info->rx_buf_total_size > 0x10000)
  2215. info->rx_buf_total_size = 0x10000;
  2216. /* calculate number of buffers */
  2217. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2218. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2219. if (info->rx_buf == NULL)
  2220. return -ENOMEM;
  2221. rx_reset_buffers(info);
  2222. return 0;
  2223. }
  2224. static void rx_free_buffers(MGSLPC_INFO *info)
  2225. {
  2226. kfree(info->rx_buf);
  2227. info->rx_buf = NULL;
  2228. }
  2229. static int claim_resources(MGSLPC_INFO *info)
  2230. {
  2231. if (rx_alloc_buffers(info) < 0 ) {
  2232. printk( "Can't allocate rx buffer %s\n", info->device_name);
  2233. release_resources(info);
  2234. return -ENODEV;
  2235. }
  2236. return 0;
  2237. }
  2238. static void release_resources(MGSLPC_INFO *info)
  2239. {
  2240. if (debug_level >= DEBUG_LEVEL_INFO)
  2241. printk("release_resources(%s)\n", info->device_name);
  2242. rx_free_buffers(info);
  2243. }
  2244. /* Add the specified device instance data structure to the
  2245. * global linked list of devices and increment the device count.
  2246. *
  2247. * Arguments: info pointer to device instance data
  2248. */
  2249. static void mgslpc_add_device(MGSLPC_INFO *info)
  2250. {
  2251. info->next_device = NULL;
  2252. info->line = mgslpc_device_count;
  2253. sprintf(info->device_name,"ttySLP%d",info->line);
  2254. if (info->line < MAX_DEVICE_COUNT) {
  2255. if (maxframe[info->line])
  2256. info->max_frame_size = maxframe[info->line];
  2257. }
  2258. mgslpc_device_count++;
  2259. if (!mgslpc_device_list)
  2260. mgslpc_device_list = info;
  2261. else {
  2262. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2263. while( current_dev->next_device )
  2264. current_dev = current_dev->next_device;
  2265. current_dev->next_device = info;
  2266. }
  2267. if (info->max_frame_size < 4096)
  2268. info->max_frame_size = 4096;
  2269. else if (info->max_frame_size > 65535)
  2270. info->max_frame_size = 65535;
  2271. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2272. info->device_name, info->io_base, info->irq_level);
  2273. #if SYNCLINK_GENERIC_HDLC
  2274. hdlcdev_init(info);
  2275. #endif
  2276. }
  2277. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2278. {
  2279. MGSLPC_INFO *info = mgslpc_device_list;
  2280. MGSLPC_INFO *last = NULL;
  2281. while(info) {
  2282. if (info == remove_info) {
  2283. if (last)
  2284. last->next_device = info->next_device;
  2285. else
  2286. mgslpc_device_list = info->next_device;
  2287. #if SYNCLINK_GENERIC_HDLC
  2288. hdlcdev_exit(info);
  2289. #endif
  2290. release_resources(info);
  2291. kfree(info);
  2292. mgslpc_device_count--;
  2293. return;
  2294. }
  2295. last = info;
  2296. info = info->next_device;
  2297. }
  2298. }
  2299. static const struct pcmcia_device_id mgslpc_ids[] = {
  2300. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2301. PCMCIA_DEVICE_NULL
  2302. };
  2303. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2304. static struct pcmcia_driver mgslpc_driver = {
  2305. .owner = THIS_MODULE,
  2306. .name = "synclink_cs",
  2307. .probe = mgslpc_probe,
  2308. .remove = mgslpc_detach,
  2309. .id_table = mgslpc_ids,
  2310. .suspend = mgslpc_suspend,
  2311. .resume = mgslpc_resume,
  2312. };
  2313. static const struct tty_operations mgslpc_ops = {
  2314. .open = mgslpc_open,
  2315. .close = mgslpc_close,
  2316. .write = mgslpc_write,
  2317. .put_char = mgslpc_put_char,
  2318. .flush_chars = mgslpc_flush_chars,
  2319. .write_room = mgslpc_write_room,
  2320. .chars_in_buffer = mgslpc_chars_in_buffer,
  2321. .flush_buffer = mgslpc_flush_buffer,
  2322. .ioctl = mgslpc_ioctl,
  2323. .throttle = mgslpc_throttle,
  2324. .unthrottle = mgslpc_unthrottle,
  2325. .send_xchar = mgslpc_send_xchar,
  2326. .break_ctl = mgslpc_break,
  2327. .wait_until_sent = mgslpc_wait_until_sent,
  2328. .set_termios = mgslpc_set_termios,
  2329. .stop = tx_pause,
  2330. .start = tx_release,
  2331. .hangup = mgslpc_hangup,
  2332. .tiocmget = tiocmget,
  2333. .tiocmset = tiocmset,
  2334. .get_icount = mgslpc_get_icount,
  2335. .proc_fops = &mgslpc_proc_fops,
  2336. };
  2337. static void synclink_cs_cleanup(void)
  2338. {
  2339. int rc;
  2340. while(mgslpc_device_list)
  2341. mgslpc_remove_device(mgslpc_device_list);
  2342. if (serial_driver) {
  2343. if ((rc = tty_unregister_driver(serial_driver)))
  2344. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2345. __FILE__,__LINE__,rc);
  2346. put_tty_driver(serial_driver);
  2347. }
  2348. pcmcia_unregister_driver(&mgslpc_driver);
  2349. }
  2350. static int __init synclink_cs_init(void)
  2351. {
  2352. int rc;
  2353. if (break_on_load) {
  2354. mgslpc_get_text_ptr();
  2355. BREAKPOINT();
  2356. }
  2357. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2358. return rc;
  2359. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2360. if (!serial_driver) {
  2361. rc = -ENOMEM;
  2362. goto error;
  2363. }
  2364. /* Initialize the tty_driver structure */
  2365. serial_driver->owner = THIS_MODULE;
  2366. serial_driver->driver_name = "synclink_cs";
  2367. serial_driver->name = "ttySLP";
  2368. serial_driver->major = ttymajor;
  2369. serial_driver->minor_start = 64;
  2370. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2371. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2372. serial_driver->init_termios = tty_std_termios;
  2373. serial_driver->init_termios.c_cflag =
  2374. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2375. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2376. tty_set_operations(serial_driver, &mgslpc_ops);
  2377. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2378. printk("%s(%d):Couldn't register serial driver\n",
  2379. __FILE__,__LINE__);
  2380. put_tty_driver(serial_driver);
  2381. serial_driver = NULL;
  2382. goto error;
  2383. }
  2384. printk("%s %s, tty major#%d\n",
  2385. driver_name, driver_version,
  2386. serial_driver->major);
  2387. return 0;
  2388. error:
  2389. synclink_cs_cleanup();
  2390. return rc;
  2391. }
  2392. static void __exit synclink_cs_exit(void)
  2393. {
  2394. synclink_cs_cleanup();
  2395. }
  2396. module_init(synclink_cs_init);
  2397. module_exit(synclink_cs_exit);
  2398. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2399. {
  2400. unsigned int M, N;
  2401. unsigned char val;
  2402. /* note:standard BRG mode is broken in V3.2 chip
  2403. * so enhanced mode is always used
  2404. */
  2405. if (rate) {
  2406. N = 3686400 / rate;
  2407. if (!N)
  2408. N = 1;
  2409. N >>= 1;
  2410. for (M = 1; N > 64 && M < 16; M++)
  2411. N >>= 1;
  2412. N--;
  2413. /* BGR[5..0] = N
  2414. * BGR[9..6] = M
  2415. * BGR[7..0] contained in BGR register
  2416. * BGR[9..8] contained in CCR2[7..6]
  2417. * divisor = (N+1)*2^M
  2418. *
  2419. * Note: M *must* not be zero (causes asymetric duty cycle)
  2420. */
  2421. write_reg(info, (unsigned char) (channel + BGR),
  2422. (unsigned char) ((M << 6) + N));
  2423. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2424. val |= ((M << 4) & 0xc0);
  2425. write_reg(info, (unsigned char) (channel + CCR2), val);
  2426. }
  2427. }
  2428. /* Enabled the AUX clock output at the specified frequency.
  2429. */
  2430. static void enable_auxclk(MGSLPC_INFO *info)
  2431. {
  2432. unsigned char val;
  2433. /* MODE
  2434. *
  2435. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2436. * 05 ADM Address Mode, 0 = no addr recognition
  2437. * 04 TMD Timer Mode, 0 = external
  2438. * 03 RAC Receiver Active, 0 = inactive
  2439. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2440. * 01 TRS Timer Resolution, 1=512
  2441. * 00 TLP Test Loop, 0 = no loop
  2442. *
  2443. * 1000 0010
  2444. */
  2445. val = 0x82;
  2446. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2447. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2448. val |= BIT2;
  2449. write_reg(info, CHB + MODE, val);
  2450. /* CCR0
  2451. *
  2452. * 07 PU Power Up, 1=active, 0=power down
  2453. * 06 MCE Master Clock Enable, 1=enabled
  2454. * 05 Reserved, 0
  2455. * 04..02 SC[2..0] Encoding
  2456. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2457. *
  2458. * 11000000
  2459. */
  2460. write_reg(info, CHB + CCR0, 0xc0);
  2461. /* CCR1
  2462. *
  2463. * 07 SFLG Shared Flag, 0 = disable shared flags
  2464. * 06 GALP Go Active On Loop, 0 = not used
  2465. * 05 GLP Go On Loop, 0 = not used
  2466. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2467. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2468. * 02..00 CM[2..0] Clock Mode
  2469. *
  2470. * 0001 0111
  2471. */
  2472. write_reg(info, CHB + CCR1, 0x17);
  2473. /* CCR2 (Channel B)
  2474. *
  2475. * 07..06 BGR[9..8] Baud rate bits 9..8
  2476. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2477. * 04 SSEL Clock source select, 1=submode b
  2478. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2479. * 02 RWX Read/Write Exchange 0=disabled
  2480. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2481. * 00 DIV, data inversion 0=disabled, 1=enabled
  2482. *
  2483. * 0011 1000
  2484. */
  2485. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2486. write_reg(info, CHB + CCR2, 0x38);
  2487. else
  2488. write_reg(info, CHB + CCR2, 0x30);
  2489. /* CCR4
  2490. *
  2491. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2492. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2493. * 05 TST1 Test Pin, 0=normal operation
  2494. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2495. * 03..02 Reserved, must be 0
  2496. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2497. *
  2498. * 0101 0000
  2499. */
  2500. write_reg(info, CHB + CCR4, 0x50);
  2501. /* if auxclk not enabled, set internal BRG so
  2502. * CTS transitions can be detected (requires TxC)
  2503. */
  2504. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2505. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2506. else
  2507. mgslpc_set_rate(info, CHB, 921600);
  2508. }
  2509. static void loopback_enable(MGSLPC_INFO *info)
  2510. {
  2511. unsigned char val;
  2512. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2513. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2514. write_reg(info, CHA + CCR1, val);
  2515. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2516. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2517. write_reg(info, CHA + CCR2, val);
  2518. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2519. if (info->params.clock_speed)
  2520. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2521. else
  2522. mgslpc_set_rate(info, CHA, 1843200);
  2523. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2524. val = read_reg(info, CHA + MODE) | BIT0;
  2525. write_reg(info, CHA + MODE, val);
  2526. }
  2527. static void hdlc_mode(MGSLPC_INFO *info)
  2528. {
  2529. unsigned char val;
  2530. unsigned char clkmode, clksubmode;
  2531. /* disable all interrupts */
  2532. irq_disable(info, CHA, 0xffff);
  2533. irq_disable(info, CHB, 0xffff);
  2534. port_irq_disable(info, 0xff);
  2535. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2536. clkmode = clksubmode = 0;
  2537. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2538. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2539. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2540. clkmode = 7;
  2541. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2542. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2543. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2544. clkmode = 7;
  2545. clksubmode = 1;
  2546. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2547. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2548. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2549. clkmode = 6;
  2550. clksubmode = 1;
  2551. } else {
  2552. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2553. clkmode = 6;
  2554. }
  2555. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2556. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2557. clksubmode = 1;
  2558. }
  2559. /* MODE
  2560. *
  2561. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2562. * 05 ADM Address Mode, 0 = no addr recognition
  2563. * 04 TMD Timer Mode, 0 = external
  2564. * 03 RAC Receiver Active, 0 = inactive
  2565. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2566. * 01 TRS Timer Resolution, 1=512
  2567. * 00 TLP Test Loop, 0 = no loop
  2568. *
  2569. * 1000 0010
  2570. */
  2571. val = 0x82;
  2572. if (info->params.loopback)
  2573. val |= BIT0;
  2574. /* preserve RTS state */
  2575. if (info->serial_signals & SerialSignal_RTS)
  2576. val |= BIT2;
  2577. write_reg(info, CHA + MODE, val);
  2578. /* CCR0
  2579. *
  2580. * 07 PU Power Up, 1=active, 0=power down
  2581. * 06 MCE Master Clock Enable, 1=enabled
  2582. * 05 Reserved, 0
  2583. * 04..02 SC[2..0] Encoding
  2584. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2585. *
  2586. * 11000000
  2587. */
  2588. val = 0xc0;
  2589. switch (info->params.encoding)
  2590. {
  2591. case HDLC_ENCODING_NRZI:
  2592. val |= BIT3;
  2593. break;
  2594. case HDLC_ENCODING_BIPHASE_SPACE:
  2595. val |= BIT4;
  2596. break; // FM0
  2597. case HDLC_ENCODING_BIPHASE_MARK:
  2598. val |= BIT4 + BIT2;
  2599. break; // FM1
  2600. case HDLC_ENCODING_BIPHASE_LEVEL:
  2601. val |= BIT4 + BIT3;
  2602. break; // Manchester
  2603. }
  2604. write_reg(info, CHA + CCR0, val);
  2605. /* CCR1
  2606. *
  2607. * 07 SFLG Shared Flag, 0 = disable shared flags
  2608. * 06 GALP Go Active On Loop, 0 = not used
  2609. * 05 GLP Go On Loop, 0 = not used
  2610. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2611. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2612. * 02..00 CM[2..0] Clock Mode
  2613. *
  2614. * 0001 0000
  2615. */
  2616. val = 0x10 + clkmode;
  2617. write_reg(info, CHA + CCR1, val);
  2618. /* CCR2
  2619. *
  2620. * 07..06 BGR[9..8] Baud rate bits 9..8
  2621. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2622. * 04 SSEL Clock source select, 1=submode b
  2623. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2624. * 02 RWX Read/Write Exchange 0=disabled
  2625. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2626. * 00 DIV, data inversion 0=disabled, 1=enabled
  2627. *
  2628. * 0000 0000
  2629. */
  2630. val = 0x00;
  2631. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2632. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2633. val |= BIT5;
  2634. if (clksubmode)
  2635. val |= BIT4;
  2636. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2637. val |= BIT1;
  2638. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2639. val |= BIT0;
  2640. write_reg(info, CHA + CCR2, val);
  2641. /* CCR3
  2642. *
  2643. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2644. * 05 EPT Enable preamble transmission, 1=enabled
  2645. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2646. * 03 CRL CRC Reset Level, 0=FFFF
  2647. * 02 RCRC Rx CRC 0=On 1=Off
  2648. * 01 TCRC Tx CRC 0=On 1=Off
  2649. * 00 PSD DPLL Phase Shift Disable
  2650. *
  2651. * 0000 0000
  2652. */
  2653. val = 0x00;
  2654. if (info->params.crc_type == HDLC_CRC_NONE)
  2655. val |= BIT2 + BIT1;
  2656. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2657. val |= BIT5;
  2658. switch (info->params.preamble_length)
  2659. {
  2660. case HDLC_PREAMBLE_LENGTH_16BITS:
  2661. val |= BIT6;
  2662. break;
  2663. case HDLC_PREAMBLE_LENGTH_32BITS:
  2664. val |= BIT6;
  2665. break;
  2666. case HDLC_PREAMBLE_LENGTH_64BITS:
  2667. val |= BIT7 + BIT6;
  2668. break;
  2669. }
  2670. write_reg(info, CHA + CCR3, val);
  2671. /* PRE - Preamble pattern */
  2672. val = 0;
  2673. switch (info->params.preamble)
  2674. {
  2675. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2676. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2677. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2678. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2679. }
  2680. write_reg(info, CHA + PRE, val);
  2681. /* CCR4
  2682. *
  2683. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2684. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2685. * 05 TST1 Test Pin, 0=normal operation
  2686. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2687. * 03..02 Reserved, must be 0
  2688. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2689. *
  2690. * 0101 0000
  2691. */
  2692. val = 0x50;
  2693. write_reg(info, CHA + CCR4, val);
  2694. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2695. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2696. else
  2697. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2698. /* RLCR Receive length check register
  2699. *
  2700. * 7 1=enable receive length check
  2701. * 6..0 Max frame length = (RL + 1) * 32
  2702. */
  2703. write_reg(info, CHA + RLCR, 0);
  2704. /* XBCH Transmit Byte Count High
  2705. *
  2706. * 07 DMA mode, 0 = interrupt driven
  2707. * 06 NRM, 0=ABM (ignored)
  2708. * 05 CAS Carrier Auto Start
  2709. * 04 XC Transmit Continuously (ignored)
  2710. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2711. *
  2712. * 0000 0000
  2713. */
  2714. val = 0x00;
  2715. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2716. val |= BIT5;
  2717. write_reg(info, CHA + XBCH, val);
  2718. enable_auxclk(info);
  2719. if (info->params.loopback || info->testing_irq)
  2720. loopback_enable(info);
  2721. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2722. {
  2723. irq_enable(info, CHB, IRQ_CTS);
  2724. /* PVR[3] 1=AUTO CTS active */
  2725. set_reg_bits(info, CHA + PVR, BIT3);
  2726. } else
  2727. clear_reg_bits(info, CHA + PVR, BIT3);
  2728. irq_enable(info, CHA,
  2729. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2730. IRQ_UNDERRUN + IRQ_TXFIFO);
  2731. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2732. wait_command_complete(info, CHA);
  2733. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2734. /* Master clock mode enabled above to allow reset commands
  2735. * to complete even if no data clocks are present.
  2736. *
  2737. * Disable master clock mode for normal communications because
  2738. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2739. * IRQ when in master clock mode.
  2740. *
  2741. * Leave master clock mode enabled for IRQ test because the
  2742. * timer IRQ used by the test can only happen in master clock mode.
  2743. */
  2744. if (!info->testing_irq)
  2745. clear_reg_bits(info, CHA + CCR0, BIT6);
  2746. tx_set_idle(info);
  2747. tx_stop(info);
  2748. rx_stop(info);
  2749. }
  2750. static void rx_stop(MGSLPC_INFO *info)
  2751. {
  2752. if (debug_level >= DEBUG_LEVEL_ISR)
  2753. printk("%s(%d):rx_stop(%s)\n",
  2754. __FILE__,__LINE__, info->device_name );
  2755. /* MODE:03 RAC Receiver Active, 0=inactive */
  2756. clear_reg_bits(info, CHA + MODE, BIT3);
  2757. info->rx_enabled = false;
  2758. info->rx_overflow = false;
  2759. }
  2760. static void rx_start(MGSLPC_INFO *info)
  2761. {
  2762. if (debug_level >= DEBUG_LEVEL_ISR)
  2763. printk("%s(%d):rx_start(%s)\n",
  2764. __FILE__,__LINE__, info->device_name );
  2765. rx_reset_buffers(info);
  2766. info->rx_enabled = false;
  2767. info->rx_overflow = false;
  2768. /* MODE:03 RAC Receiver Active, 1=active */
  2769. set_reg_bits(info, CHA + MODE, BIT3);
  2770. info->rx_enabled = true;
  2771. }
  2772. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2773. {
  2774. if (debug_level >= DEBUG_LEVEL_ISR)
  2775. printk("%s(%d):tx_start(%s)\n",
  2776. __FILE__,__LINE__, info->device_name );
  2777. if (info->tx_count) {
  2778. /* If auto RTS enabled and RTS is inactive, then assert */
  2779. /* RTS and set a flag indicating that the driver should */
  2780. /* negate RTS when the transmission completes. */
  2781. info->drop_rts_on_tx_done = false;
  2782. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2783. get_signals(info);
  2784. if (!(info->serial_signals & SerialSignal_RTS)) {
  2785. info->serial_signals |= SerialSignal_RTS;
  2786. set_signals(info);
  2787. info->drop_rts_on_tx_done = true;
  2788. }
  2789. }
  2790. if (info->params.mode == MGSL_MODE_ASYNC) {
  2791. if (!info->tx_active) {
  2792. info->tx_active = true;
  2793. tx_ready(info, tty);
  2794. }
  2795. } else {
  2796. info->tx_active = true;
  2797. tx_ready(info, tty);
  2798. mod_timer(&info->tx_timer, jiffies +
  2799. msecs_to_jiffies(5000));
  2800. }
  2801. }
  2802. if (!info->tx_enabled)
  2803. info->tx_enabled = true;
  2804. }
  2805. static void tx_stop(MGSLPC_INFO *info)
  2806. {
  2807. if (debug_level >= DEBUG_LEVEL_ISR)
  2808. printk("%s(%d):tx_stop(%s)\n",
  2809. __FILE__,__LINE__, info->device_name );
  2810. del_timer(&info->tx_timer);
  2811. info->tx_enabled = false;
  2812. info->tx_active = false;
  2813. }
  2814. /* Reset the adapter to a known state and prepare it for further use.
  2815. */
  2816. static void reset_device(MGSLPC_INFO *info)
  2817. {
  2818. /* power up both channels (set BIT7) */
  2819. write_reg(info, CHA + CCR0, 0x80);
  2820. write_reg(info, CHB + CCR0, 0x80);
  2821. write_reg(info, CHA + MODE, 0);
  2822. write_reg(info, CHB + MODE, 0);
  2823. /* disable all interrupts */
  2824. irq_disable(info, CHA, 0xffff);
  2825. irq_disable(info, CHB, 0xffff);
  2826. port_irq_disable(info, 0xff);
  2827. /* PCR Port Configuration Register
  2828. *
  2829. * 07..04 DEC[3..0] Serial I/F select outputs
  2830. * 03 output, 1=AUTO CTS control enabled
  2831. * 02 RI Ring Indicator input 0=active
  2832. * 01 DSR input 0=active
  2833. * 00 DTR output 0=active
  2834. *
  2835. * 0000 0110
  2836. */
  2837. write_reg(info, PCR, 0x06);
  2838. /* PVR Port Value Register
  2839. *
  2840. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2841. * 03 AUTO CTS output 1=enabled
  2842. * 02 RI Ring Indicator input
  2843. * 01 DSR input
  2844. * 00 DTR output (1=inactive)
  2845. *
  2846. * 0000 0001
  2847. */
  2848. // write_reg(info, PVR, PVR_DTR);
  2849. /* IPC Interrupt Port Configuration
  2850. *
  2851. * 07 VIS 1=Masked interrupts visible
  2852. * 06..05 Reserved, 0
  2853. * 04..03 SLA Slave address, 00 ignored
  2854. * 02 CASM Cascading Mode, 1=daisy chain
  2855. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2856. *
  2857. * 0000 0101
  2858. */
  2859. write_reg(info, IPC, 0x05);
  2860. }
  2861. static void async_mode(MGSLPC_INFO *info)
  2862. {
  2863. unsigned char val;
  2864. /* disable all interrupts */
  2865. irq_disable(info, CHA, 0xffff);
  2866. irq_disable(info, CHB, 0xffff);
  2867. port_irq_disable(info, 0xff);
  2868. /* MODE
  2869. *
  2870. * 07 Reserved, 0
  2871. * 06 FRTS RTS State, 0=active
  2872. * 05 FCTS Flow Control on CTS
  2873. * 04 FLON Flow Control Enable
  2874. * 03 RAC Receiver Active, 0 = inactive
  2875. * 02 RTS 0=Auto RTS, 1=manual RTS
  2876. * 01 TRS Timer Resolution, 1=512
  2877. * 00 TLP Test Loop, 0 = no loop
  2878. *
  2879. * 0000 0110
  2880. */
  2881. val = 0x06;
  2882. if (info->params.loopback)
  2883. val |= BIT0;
  2884. /* preserve RTS state */
  2885. if (!(info->serial_signals & SerialSignal_RTS))
  2886. val |= BIT6;
  2887. write_reg(info, CHA + MODE, val);
  2888. /* CCR0
  2889. *
  2890. * 07 PU Power Up, 1=active, 0=power down
  2891. * 06 MCE Master Clock Enable, 1=enabled
  2892. * 05 Reserved, 0
  2893. * 04..02 SC[2..0] Encoding, 000=NRZ
  2894. * 01..00 SM[1..0] Serial Mode, 11=Async
  2895. *
  2896. * 1000 0011
  2897. */
  2898. write_reg(info, CHA + CCR0, 0x83);
  2899. /* CCR1
  2900. *
  2901. * 07..05 Reserved, 0
  2902. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2903. * 03 BCR Bit Clock Rate, 1=16x
  2904. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2905. *
  2906. * 0001 1111
  2907. */
  2908. write_reg(info, CHA + CCR1, 0x1f);
  2909. /* CCR2 (channel A)
  2910. *
  2911. * 07..06 BGR[9..8] Baud rate bits 9..8
  2912. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2913. * 04 SSEL Clock source select, 1=submode b
  2914. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2915. * 02 RWX Read/Write Exchange 0=disabled
  2916. * 01 Reserved, 0
  2917. * 00 DIV, data inversion 0=disabled, 1=enabled
  2918. *
  2919. * 0001 0000
  2920. */
  2921. write_reg(info, CHA + CCR2, 0x10);
  2922. /* CCR3
  2923. *
  2924. * 07..01 Reserved, 0
  2925. * 00 PSD DPLL Phase Shift Disable
  2926. *
  2927. * 0000 0000
  2928. */
  2929. write_reg(info, CHA + CCR3, 0);
  2930. /* CCR4
  2931. *
  2932. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2933. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2934. * 05 TST1 Test Pin, 0=normal operation
  2935. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2936. * 03..00 Reserved, must be 0
  2937. *
  2938. * 0101 0000
  2939. */
  2940. write_reg(info, CHA + CCR4, 0x50);
  2941. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2942. /* DAFO Data Format
  2943. *
  2944. * 07 Reserved, 0
  2945. * 06 XBRK transmit break, 0=normal operation
  2946. * 05 Stop bits (0=1, 1=2)
  2947. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2948. * 02 PAREN Parity Enable
  2949. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2950. *
  2951. */
  2952. val = 0x00;
  2953. if (info->params.data_bits != 8)
  2954. val |= BIT0; /* 7 bits */
  2955. if (info->params.stop_bits != 1)
  2956. val |= BIT5;
  2957. if (info->params.parity != ASYNC_PARITY_NONE)
  2958. {
  2959. val |= BIT2; /* Parity enable */
  2960. if (info->params.parity == ASYNC_PARITY_ODD)
  2961. val |= BIT3;
  2962. else
  2963. val |= BIT4;
  2964. }
  2965. write_reg(info, CHA + DAFO, val);
  2966. /* RFC Rx FIFO Control
  2967. *
  2968. * 07 Reserved, 0
  2969. * 06 DPS, 1=parity bit not stored in data byte
  2970. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  2971. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  2972. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  2973. * 01 Reserved, 0
  2974. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  2975. *
  2976. * 0101 1100
  2977. */
  2978. write_reg(info, CHA + RFC, 0x5c);
  2979. /* RLCR Receive length check register
  2980. *
  2981. * Max frame length = (RL + 1) * 32
  2982. */
  2983. write_reg(info, CHA + RLCR, 0);
  2984. /* XBCH Transmit Byte Count High
  2985. *
  2986. * 07 DMA mode, 0 = interrupt driven
  2987. * 06 NRM, 0=ABM (ignored)
  2988. * 05 CAS Carrier Auto Start
  2989. * 04 XC Transmit Continuously (ignored)
  2990. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2991. *
  2992. * 0000 0000
  2993. */
  2994. val = 0x00;
  2995. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2996. val |= BIT5;
  2997. write_reg(info, CHA + XBCH, val);
  2998. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2999. irq_enable(info, CHA, IRQ_CTS);
  3000. /* MODE:03 RAC Receiver Active, 1=active */
  3001. set_reg_bits(info, CHA + MODE, BIT3);
  3002. enable_auxclk(info);
  3003. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3004. irq_enable(info, CHB, IRQ_CTS);
  3005. /* PVR[3] 1=AUTO CTS active */
  3006. set_reg_bits(info, CHA + PVR, BIT3);
  3007. } else
  3008. clear_reg_bits(info, CHA + PVR, BIT3);
  3009. irq_enable(info, CHA,
  3010. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3011. IRQ_ALLSENT + IRQ_TXFIFO);
  3012. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3013. wait_command_complete(info, CHA);
  3014. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3015. }
  3016. /* Set the HDLC idle mode for the transmitter.
  3017. */
  3018. static void tx_set_idle(MGSLPC_INFO *info)
  3019. {
  3020. /* Note: ESCC2 only supports flags and one idle modes */
  3021. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3022. set_reg_bits(info, CHA + CCR1, BIT3);
  3023. else
  3024. clear_reg_bits(info, CHA + CCR1, BIT3);
  3025. }
  3026. /* get state of the V24 status (input) signals.
  3027. */
  3028. static void get_signals(MGSLPC_INFO *info)
  3029. {
  3030. unsigned char status = 0;
  3031. /* preserve DTR and RTS */
  3032. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3033. if (read_reg(info, CHB + VSTR) & BIT7)
  3034. info->serial_signals |= SerialSignal_DCD;
  3035. if (read_reg(info, CHB + STAR) & BIT1)
  3036. info->serial_signals |= SerialSignal_CTS;
  3037. status = read_reg(info, CHA + PVR);
  3038. if (!(status & PVR_RI))
  3039. info->serial_signals |= SerialSignal_RI;
  3040. if (!(status & PVR_DSR))
  3041. info->serial_signals |= SerialSignal_DSR;
  3042. }
  3043. /* Set the state of DTR and RTS based on contents of
  3044. * serial_signals member of device extension.
  3045. */
  3046. static void set_signals(MGSLPC_INFO *info)
  3047. {
  3048. unsigned char val;
  3049. val = read_reg(info, CHA + MODE);
  3050. if (info->params.mode == MGSL_MODE_ASYNC) {
  3051. if (info->serial_signals & SerialSignal_RTS)
  3052. val &= ~BIT6;
  3053. else
  3054. val |= BIT6;
  3055. } else {
  3056. if (info->serial_signals & SerialSignal_RTS)
  3057. val |= BIT2;
  3058. else
  3059. val &= ~BIT2;
  3060. }
  3061. write_reg(info, CHA + MODE, val);
  3062. if (info->serial_signals & SerialSignal_DTR)
  3063. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3064. else
  3065. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3066. }
  3067. static void rx_reset_buffers(MGSLPC_INFO *info)
  3068. {
  3069. RXBUF *buf;
  3070. int i;
  3071. info->rx_put = 0;
  3072. info->rx_get = 0;
  3073. info->rx_frame_count = 0;
  3074. for (i=0 ; i < info->rx_buf_count ; i++) {
  3075. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3076. buf->status = buf->count = 0;
  3077. }
  3078. }
  3079. /* Attempt to return a received HDLC frame
  3080. * Only frames received without errors are returned.
  3081. *
  3082. * Returns true if frame returned, otherwise false
  3083. */
  3084. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3085. {
  3086. unsigned short status;
  3087. RXBUF *buf;
  3088. unsigned int framesize = 0;
  3089. unsigned long flags;
  3090. bool return_frame = false;
  3091. if (info->rx_frame_count == 0)
  3092. return false;
  3093. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3094. status = buf->status;
  3095. /* 07 VFR 1=valid frame
  3096. * 06 RDO 1=data overrun
  3097. * 05 CRC 1=OK, 0=error
  3098. * 04 RAB 1=frame aborted
  3099. */
  3100. if ((status & 0xf0) != 0xA0) {
  3101. if (!(status & BIT7) || (status & BIT4))
  3102. info->icount.rxabort++;
  3103. else if (status & BIT6)
  3104. info->icount.rxover++;
  3105. else if (!(status & BIT5)) {
  3106. info->icount.rxcrc++;
  3107. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3108. return_frame = true;
  3109. }
  3110. framesize = 0;
  3111. #if SYNCLINK_GENERIC_HDLC
  3112. {
  3113. info->netdev->stats.rx_errors++;
  3114. info->netdev->stats.rx_frame_errors++;
  3115. }
  3116. #endif
  3117. } else
  3118. return_frame = true;
  3119. if (return_frame)
  3120. framesize = buf->count;
  3121. if (debug_level >= DEBUG_LEVEL_BH)
  3122. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3123. __FILE__,__LINE__,info->device_name,status,framesize);
  3124. if (debug_level >= DEBUG_LEVEL_DATA)
  3125. trace_block(info, buf->data, framesize, 0);
  3126. if (framesize) {
  3127. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3128. framesize+1 > info->max_frame_size) ||
  3129. framesize > info->max_frame_size)
  3130. info->icount.rxlong++;
  3131. else {
  3132. if (status & BIT5)
  3133. info->icount.rxok++;
  3134. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3135. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3136. ++framesize;
  3137. }
  3138. #if SYNCLINK_GENERIC_HDLC
  3139. if (info->netcount)
  3140. hdlcdev_rx(info, buf->data, framesize);
  3141. else
  3142. #endif
  3143. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3144. }
  3145. }
  3146. spin_lock_irqsave(&info->lock,flags);
  3147. buf->status = buf->count = 0;
  3148. info->rx_frame_count--;
  3149. info->rx_get++;
  3150. if (info->rx_get >= info->rx_buf_count)
  3151. info->rx_get = 0;
  3152. spin_unlock_irqrestore(&info->lock,flags);
  3153. return true;
  3154. }
  3155. static bool register_test(MGSLPC_INFO *info)
  3156. {
  3157. static unsigned char patterns[] =
  3158. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3159. static unsigned int count = ARRAY_SIZE(patterns);
  3160. unsigned int i;
  3161. bool rc = true;
  3162. unsigned long flags;
  3163. spin_lock_irqsave(&info->lock,flags);
  3164. reset_device(info);
  3165. for (i = 0; i < count; i++) {
  3166. write_reg(info, XAD1, patterns[i]);
  3167. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3168. if ((read_reg(info, XAD1) != patterns[i]) ||
  3169. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3170. rc = false;
  3171. break;
  3172. }
  3173. }
  3174. spin_unlock_irqrestore(&info->lock,flags);
  3175. return rc;
  3176. }
  3177. static bool irq_test(MGSLPC_INFO *info)
  3178. {
  3179. unsigned long end_time;
  3180. unsigned long flags;
  3181. spin_lock_irqsave(&info->lock,flags);
  3182. reset_device(info);
  3183. info->testing_irq = true;
  3184. hdlc_mode(info);
  3185. info->irq_occurred = false;
  3186. /* init hdlc mode */
  3187. irq_enable(info, CHA, IRQ_TIMER);
  3188. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3189. issue_command(info, CHA, CMD_START_TIMER);
  3190. spin_unlock_irqrestore(&info->lock,flags);
  3191. end_time=100;
  3192. while(end_time-- && !info->irq_occurred) {
  3193. msleep_interruptible(10);
  3194. }
  3195. info->testing_irq = false;
  3196. spin_lock_irqsave(&info->lock,flags);
  3197. reset_device(info);
  3198. spin_unlock_irqrestore(&info->lock,flags);
  3199. return info->irq_occurred;
  3200. }
  3201. static int adapter_test(MGSLPC_INFO *info)
  3202. {
  3203. if (!register_test(info)) {
  3204. info->init_error = DiagStatus_AddressFailure;
  3205. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3206. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3207. return -ENODEV;
  3208. }
  3209. if (!irq_test(info)) {
  3210. info->init_error = DiagStatus_IrqFailure;
  3211. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3212. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3213. return -ENODEV;
  3214. }
  3215. if (debug_level >= DEBUG_LEVEL_INFO)
  3216. printk("%s(%d):device %s passed diagnostics\n",
  3217. __FILE__,__LINE__,info->device_name);
  3218. return 0;
  3219. }
  3220. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3221. {
  3222. int i;
  3223. int linecount;
  3224. if (xmit)
  3225. printk("%s tx data:\n",info->device_name);
  3226. else
  3227. printk("%s rx data:\n",info->device_name);
  3228. while(count) {
  3229. if (count > 16)
  3230. linecount = 16;
  3231. else
  3232. linecount = count;
  3233. for(i=0;i<linecount;i++)
  3234. printk("%02X ",(unsigned char)data[i]);
  3235. for(;i<17;i++)
  3236. printk(" ");
  3237. for(i=0;i<linecount;i++) {
  3238. if (data[i]>=040 && data[i]<=0176)
  3239. printk("%c",data[i]);
  3240. else
  3241. printk(".");
  3242. }
  3243. printk("\n");
  3244. data += linecount;
  3245. count -= linecount;
  3246. }
  3247. }
  3248. /* HDLC frame time out
  3249. * update stats and do tx completion processing
  3250. */
  3251. static void tx_timeout(unsigned long context)
  3252. {
  3253. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3254. unsigned long flags;
  3255. if ( debug_level >= DEBUG_LEVEL_INFO )
  3256. printk( "%s(%d):tx_timeout(%s)\n",
  3257. __FILE__,__LINE__,info->device_name);
  3258. if(info->tx_active &&
  3259. info->params.mode == MGSL_MODE_HDLC) {
  3260. info->icount.txtimeout++;
  3261. }
  3262. spin_lock_irqsave(&info->lock,flags);
  3263. info->tx_active = false;
  3264. info->tx_count = info->tx_put = info->tx_get = 0;
  3265. spin_unlock_irqrestore(&info->lock,flags);
  3266. #if SYNCLINK_GENERIC_HDLC
  3267. if (info->netcount)
  3268. hdlcdev_tx_done(info);
  3269. else
  3270. #endif
  3271. {
  3272. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3273. bh_transmit(info, tty);
  3274. tty_kref_put(tty);
  3275. }
  3276. }
  3277. #if SYNCLINK_GENERIC_HDLC
  3278. /**
  3279. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3280. * set encoding and frame check sequence (FCS) options
  3281. *
  3282. * dev pointer to network device structure
  3283. * encoding serial encoding setting
  3284. * parity FCS setting
  3285. *
  3286. * returns 0 if success, otherwise error code
  3287. */
  3288. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3289. unsigned short parity)
  3290. {
  3291. MGSLPC_INFO *info = dev_to_port(dev);
  3292. struct tty_struct *tty;
  3293. unsigned char new_encoding;
  3294. unsigned short new_crctype;
  3295. /* return error if TTY interface open */
  3296. if (info->port.count)
  3297. return -EBUSY;
  3298. switch (encoding)
  3299. {
  3300. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3301. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3302. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3303. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3304. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3305. default: return -EINVAL;
  3306. }
  3307. switch (parity)
  3308. {
  3309. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3310. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3311. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3312. default: return -EINVAL;
  3313. }
  3314. info->params.encoding = new_encoding;
  3315. info->params.crc_type = new_crctype;
  3316. /* if network interface up, reprogram hardware */
  3317. if (info->netcount) {
  3318. tty = tty_port_tty_get(&info->port);
  3319. mgslpc_program_hw(info, tty);
  3320. tty_kref_put(tty);
  3321. }
  3322. return 0;
  3323. }
  3324. /**
  3325. * called by generic HDLC layer to send frame
  3326. *
  3327. * skb socket buffer containing HDLC frame
  3328. * dev pointer to network device structure
  3329. */
  3330. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3331. struct net_device *dev)
  3332. {
  3333. MGSLPC_INFO *info = dev_to_port(dev);
  3334. unsigned long flags;
  3335. if (debug_level >= DEBUG_LEVEL_INFO)
  3336. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3337. /* stop sending until this frame completes */
  3338. netif_stop_queue(dev);
  3339. /* copy data to device buffers */
  3340. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3341. info->tx_get = 0;
  3342. info->tx_put = info->tx_count = skb->len;
  3343. /* update network statistics */
  3344. dev->stats.tx_packets++;
  3345. dev->stats.tx_bytes += skb->len;
  3346. /* done with socket buffer, so free it */
  3347. dev_kfree_skb(skb);
  3348. /* save start time for transmit timeout detection */
  3349. dev->trans_start = jiffies;
  3350. /* start hardware transmitter if necessary */
  3351. spin_lock_irqsave(&info->lock,flags);
  3352. if (!info->tx_active) {
  3353. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3354. tx_start(info, tty);
  3355. tty_kref_put(tty);
  3356. }
  3357. spin_unlock_irqrestore(&info->lock,flags);
  3358. return NETDEV_TX_OK;
  3359. }
  3360. /**
  3361. * called by network layer when interface enabled
  3362. * claim resources and initialize hardware
  3363. *
  3364. * dev pointer to network device structure
  3365. *
  3366. * returns 0 if success, otherwise error code
  3367. */
  3368. static int hdlcdev_open(struct net_device *dev)
  3369. {
  3370. MGSLPC_INFO *info = dev_to_port(dev);
  3371. struct tty_struct *tty;
  3372. int rc;
  3373. unsigned long flags;
  3374. if (debug_level >= DEBUG_LEVEL_INFO)
  3375. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3376. /* generic HDLC layer open processing */
  3377. if ((rc = hdlc_open(dev)))
  3378. return rc;
  3379. /* arbitrate between network and tty opens */
  3380. spin_lock_irqsave(&info->netlock, flags);
  3381. if (info->port.count != 0 || info->netcount != 0) {
  3382. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3383. spin_unlock_irqrestore(&info->netlock, flags);
  3384. return -EBUSY;
  3385. }
  3386. info->netcount=1;
  3387. spin_unlock_irqrestore(&info->netlock, flags);
  3388. tty = tty_port_tty_get(&info->port);
  3389. /* claim resources and init adapter */
  3390. if ((rc = startup(info, tty)) != 0) {
  3391. tty_kref_put(tty);
  3392. spin_lock_irqsave(&info->netlock, flags);
  3393. info->netcount=0;
  3394. spin_unlock_irqrestore(&info->netlock, flags);
  3395. return rc;
  3396. }
  3397. /* assert DTR and RTS, apply hardware settings */
  3398. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3399. mgslpc_program_hw(info, tty);
  3400. tty_kref_put(tty);
  3401. /* enable network layer transmit */
  3402. dev->trans_start = jiffies;
  3403. netif_start_queue(dev);
  3404. /* inform generic HDLC layer of current DCD status */
  3405. spin_lock_irqsave(&info->lock, flags);
  3406. get_signals(info);
  3407. spin_unlock_irqrestore(&info->lock, flags);
  3408. if (info->serial_signals & SerialSignal_DCD)
  3409. netif_carrier_on(dev);
  3410. else
  3411. netif_carrier_off(dev);
  3412. return 0;
  3413. }
  3414. /**
  3415. * called by network layer when interface is disabled
  3416. * shutdown hardware and release resources
  3417. *
  3418. * dev pointer to network device structure
  3419. *
  3420. * returns 0 if success, otherwise error code
  3421. */
  3422. static int hdlcdev_close(struct net_device *dev)
  3423. {
  3424. MGSLPC_INFO *info = dev_to_port(dev);
  3425. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3426. unsigned long flags;
  3427. if (debug_level >= DEBUG_LEVEL_INFO)
  3428. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3429. netif_stop_queue(dev);
  3430. /* shutdown adapter and release resources */
  3431. shutdown(info, tty);
  3432. tty_kref_put(tty);
  3433. hdlc_close(dev);
  3434. spin_lock_irqsave(&info->netlock, flags);
  3435. info->netcount=0;
  3436. spin_unlock_irqrestore(&info->netlock, flags);
  3437. return 0;
  3438. }
  3439. /**
  3440. * called by network layer to process IOCTL call to network device
  3441. *
  3442. * dev pointer to network device structure
  3443. * ifr pointer to network interface request structure
  3444. * cmd IOCTL command code
  3445. *
  3446. * returns 0 if success, otherwise error code
  3447. */
  3448. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3449. {
  3450. const size_t size = sizeof(sync_serial_settings);
  3451. sync_serial_settings new_line;
  3452. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3453. MGSLPC_INFO *info = dev_to_port(dev);
  3454. unsigned int flags;
  3455. if (debug_level >= DEBUG_LEVEL_INFO)
  3456. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3457. /* return error if TTY interface open */
  3458. if (info->port.count)
  3459. return -EBUSY;
  3460. if (cmd != SIOCWANDEV)
  3461. return hdlc_ioctl(dev, ifr, cmd);
  3462. memset(&new_line, 0, size);
  3463. switch(ifr->ifr_settings.type) {
  3464. case IF_GET_IFACE: /* return current sync_serial_settings */
  3465. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3466. if (ifr->ifr_settings.size < size) {
  3467. ifr->ifr_settings.size = size; /* data size wanted */
  3468. return -ENOBUFS;
  3469. }
  3470. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3471. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3472. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3473. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3474. switch (flags){
  3475. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3476. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3477. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3478. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3479. default: new_line.clock_type = CLOCK_DEFAULT;
  3480. }
  3481. new_line.clock_rate = info->params.clock_speed;
  3482. new_line.loopback = info->params.loopback ? 1:0;
  3483. if (copy_to_user(line, &new_line, size))
  3484. return -EFAULT;
  3485. return 0;
  3486. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3487. if(!capable(CAP_NET_ADMIN))
  3488. return -EPERM;
  3489. if (copy_from_user(&new_line, line, size))
  3490. return -EFAULT;
  3491. switch (new_line.clock_type)
  3492. {
  3493. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3494. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3495. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3496. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3497. case CLOCK_DEFAULT: flags = info->params.flags &
  3498. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3499. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3500. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3501. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3502. default: return -EINVAL;
  3503. }
  3504. if (new_line.loopback != 0 && new_line.loopback != 1)
  3505. return -EINVAL;
  3506. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3507. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3508. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3509. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3510. info->params.flags |= flags;
  3511. info->params.loopback = new_line.loopback;
  3512. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3513. info->params.clock_speed = new_line.clock_rate;
  3514. else
  3515. info->params.clock_speed = 0;
  3516. /* if network interface up, reprogram hardware */
  3517. if (info->netcount) {
  3518. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3519. mgslpc_program_hw(info, tty);
  3520. tty_kref_put(tty);
  3521. }
  3522. return 0;
  3523. default:
  3524. return hdlc_ioctl(dev, ifr, cmd);
  3525. }
  3526. }
  3527. /**
  3528. * called by network layer when transmit timeout is detected
  3529. *
  3530. * dev pointer to network device structure
  3531. */
  3532. static void hdlcdev_tx_timeout(struct net_device *dev)
  3533. {
  3534. MGSLPC_INFO *info = dev_to_port(dev);
  3535. unsigned long flags;
  3536. if (debug_level >= DEBUG_LEVEL_INFO)
  3537. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3538. dev->stats.tx_errors++;
  3539. dev->stats.tx_aborted_errors++;
  3540. spin_lock_irqsave(&info->lock,flags);
  3541. tx_stop(info);
  3542. spin_unlock_irqrestore(&info->lock,flags);
  3543. netif_wake_queue(dev);
  3544. }
  3545. /**
  3546. * called by device driver when transmit completes
  3547. * reenable network layer transmit if stopped
  3548. *
  3549. * info pointer to device instance information
  3550. */
  3551. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3552. {
  3553. if (netif_queue_stopped(info->netdev))
  3554. netif_wake_queue(info->netdev);
  3555. }
  3556. /**
  3557. * called by device driver when frame received
  3558. * pass frame to network layer
  3559. *
  3560. * info pointer to device instance information
  3561. * buf pointer to buffer contianing frame data
  3562. * size count of data bytes in buf
  3563. */
  3564. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3565. {
  3566. struct sk_buff *skb = dev_alloc_skb(size);
  3567. struct net_device *dev = info->netdev;
  3568. if (debug_level >= DEBUG_LEVEL_INFO)
  3569. printk("hdlcdev_rx(%s)\n",dev->name);
  3570. if (skb == NULL) {
  3571. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3572. dev->stats.rx_dropped++;
  3573. return;
  3574. }
  3575. memcpy(skb_put(skb, size), buf, size);
  3576. skb->protocol = hdlc_type_trans(skb, dev);
  3577. dev->stats.rx_packets++;
  3578. dev->stats.rx_bytes += size;
  3579. netif_rx(skb);
  3580. }
  3581. static const struct net_device_ops hdlcdev_ops = {
  3582. .ndo_open = hdlcdev_open,
  3583. .ndo_stop = hdlcdev_close,
  3584. .ndo_change_mtu = hdlc_change_mtu,
  3585. .ndo_start_xmit = hdlc_start_xmit,
  3586. .ndo_do_ioctl = hdlcdev_ioctl,
  3587. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3588. };
  3589. /**
  3590. * called by device driver when adding device instance
  3591. * do generic HDLC initialization
  3592. *
  3593. * info pointer to device instance information
  3594. *
  3595. * returns 0 if success, otherwise error code
  3596. */
  3597. static int hdlcdev_init(MGSLPC_INFO *info)
  3598. {
  3599. int rc;
  3600. struct net_device *dev;
  3601. hdlc_device *hdlc;
  3602. /* allocate and initialize network and HDLC layer objects */
  3603. if (!(dev = alloc_hdlcdev(info))) {
  3604. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3605. return -ENOMEM;
  3606. }
  3607. /* for network layer reporting purposes only */
  3608. dev->base_addr = info->io_base;
  3609. dev->irq = info->irq_level;
  3610. /* network layer callbacks and settings */
  3611. dev->netdev_ops = &hdlcdev_ops;
  3612. dev->watchdog_timeo = 10 * HZ;
  3613. dev->tx_queue_len = 50;
  3614. /* generic HDLC layer callbacks and settings */
  3615. hdlc = dev_to_hdlc(dev);
  3616. hdlc->attach = hdlcdev_attach;
  3617. hdlc->xmit = hdlcdev_xmit;
  3618. /* register objects with HDLC layer */
  3619. if ((rc = register_hdlc_device(dev))) {
  3620. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3621. free_netdev(dev);
  3622. return rc;
  3623. }
  3624. info->netdev = dev;
  3625. return 0;
  3626. }
  3627. /**
  3628. * called by device driver when removing device instance
  3629. * do generic HDLC cleanup
  3630. *
  3631. * info pointer to device instance information
  3632. */
  3633. static void hdlcdev_exit(MGSLPC_INFO *info)
  3634. {
  3635. unregister_hdlc_device(info->netdev);
  3636. free_netdev(info->netdev);
  3637. info->netdev = NULL;
  3638. }
  3639. #endif /* CONFIG_HDLC */