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/drivers/tty/serial/pmac_zilog.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 2206 lines | 1466 code | 339 blank | 401 comment | 290 complexity | 1f1725625c5ed44c9818af04bf0ba409 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Driver for PowerMac Z85c30 based ESCC cell found in the
  3. * "macio" ASICs of various PowerMac models
  4. *
  5. * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
  6. *
  7. * Derived from drivers/macintosh/macserial.c by Paul Mackerras
  8. * and drivers/serial/sunzilog.c by David S. Miller
  9. *
  10. * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
  11. * adapted special tweaks needed for us. I don't think it's worth
  12. * merging back those though. The DMA code still has to get in
  13. * and once done, I expect that driver to remain fairly stable in
  14. * the long term, unless we change the driver model again...
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  29. *
  30. * 2004-08-06 Harald Welte <laforge@gnumonks.org>
  31. * - Enable BREAK interrupt
  32. * - Add support for sysreq
  33. *
  34. * TODO: - Add DMA support
  35. * - Defer port shutdown to a few seconds after close
  36. * - maybe put something right into uap->clk_divisor
  37. */
  38. #undef DEBUG
  39. #undef DEBUG_HARD
  40. #undef USE_CTRL_O_SYSRQ
  41. #include <linux/module.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/major.h>
  45. #include <linux/string.h>
  46. #include <linux/fcntl.h>
  47. #include <linux/mm.h>
  48. #include <linux/kernel.h>
  49. #include <linux/delay.h>
  50. #include <linux/init.h>
  51. #include <linux/console.h>
  52. #include <linux/adb.h>
  53. #include <linux/pmu.h>
  54. #include <linux/bitops.h>
  55. #include <linux/sysrq.h>
  56. #include <linux/mutex.h>
  57. #include <asm/sections.h>
  58. #include <asm/io.h>
  59. #include <asm/irq.h>
  60. #ifdef CONFIG_PPC_PMAC
  61. #include <asm/prom.h>
  62. #include <asm/machdep.h>
  63. #include <asm/pmac_feature.h>
  64. #include <asm/dbdma.h>
  65. #include <asm/macio.h>
  66. #else
  67. #include <linux/platform_device.h>
  68. #define of_machine_is_compatible(x) (0)
  69. #endif
  70. #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  71. #define SUPPORT_SYSRQ
  72. #endif
  73. #include <linux/serial.h>
  74. #include <linux/serial_core.h>
  75. #include "pmac_zilog.h"
  76. /* Not yet implemented */
  77. #undef HAS_DBDMA
  78. static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
  79. MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
  80. MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
  81. MODULE_LICENSE("GPL");
  82. #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
  83. #define PMACZILOG_MAJOR TTY_MAJOR
  84. #define PMACZILOG_MINOR 64
  85. #define PMACZILOG_NAME "ttyS"
  86. #else
  87. #define PMACZILOG_MAJOR 204
  88. #define PMACZILOG_MINOR 192
  89. #define PMACZILOG_NAME "ttyPZ"
  90. #endif
  91. /*
  92. * For the sake of early serial console, we can do a pre-probe
  93. * (optional) of the ports at rather early boot time.
  94. */
  95. static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
  96. static int pmz_ports_count;
  97. static DEFINE_MUTEX(pmz_irq_mutex);
  98. static struct uart_driver pmz_uart_reg = {
  99. .owner = THIS_MODULE,
  100. .driver_name = PMACZILOG_NAME,
  101. .dev_name = PMACZILOG_NAME,
  102. .major = PMACZILOG_MAJOR,
  103. .minor = PMACZILOG_MINOR,
  104. };
  105. /*
  106. * Load all registers to reprogram the port
  107. * This function must only be called when the TX is not busy. The UART
  108. * port lock must be held and local interrupts disabled.
  109. */
  110. static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
  111. {
  112. int i;
  113. if (ZS_IS_ASLEEP(uap))
  114. return;
  115. /* Let pending transmits finish. */
  116. for (i = 0; i < 1000; i++) {
  117. unsigned char stat = read_zsreg(uap, R1);
  118. if (stat & ALL_SNT)
  119. break;
  120. udelay(100);
  121. }
  122. ZS_CLEARERR(uap);
  123. zssync(uap);
  124. ZS_CLEARFIFO(uap);
  125. zssync(uap);
  126. ZS_CLEARERR(uap);
  127. /* Disable all interrupts. */
  128. write_zsreg(uap, R1,
  129. regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
  130. /* Set parity, sync config, stop bits, and clock divisor. */
  131. write_zsreg(uap, R4, regs[R4]);
  132. /* Set misc. TX/RX control bits. */
  133. write_zsreg(uap, R10, regs[R10]);
  134. /* Set TX/RX controls sans the enable bits. */
  135. write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
  136. write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
  137. /* now set R7 "prime" on ESCC */
  138. write_zsreg(uap, R15, regs[R15] | EN85C30);
  139. write_zsreg(uap, R7, regs[R7P]);
  140. /* make sure we use R7 "non-prime" on ESCC */
  141. write_zsreg(uap, R15, regs[R15] & ~EN85C30);
  142. /* Synchronous mode config. */
  143. write_zsreg(uap, R6, regs[R6]);
  144. write_zsreg(uap, R7, regs[R7]);
  145. /* Disable baud generator. */
  146. write_zsreg(uap, R14, regs[R14] & ~BRENAB);
  147. /* Clock mode control. */
  148. write_zsreg(uap, R11, regs[R11]);
  149. /* Lower and upper byte of baud rate generator divisor. */
  150. write_zsreg(uap, R12, regs[R12]);
  151. write_zsreg(uap, R13, regs[R13]);
  152. /* Now rewrite R14, with BRENAB (if set). */
  153. write_zsreg(uap, R14, regs[R14]);
  154. /* Reset external status interrupts. */
  155. write_zsreg(uap, R0, RES_EXT_INT);
  156. write_zsreg(uap, R0, RES_EXT_INT);
  157. /* Rewrite R3/R5, this time without enables masked. */
  158. write_zsreg(uap, R3, regs[R3]);
  159. write_zsreg(uap, R5, regs[R5]);
  160. /* Rewrite R1, this time without IRQ enabled masked. */
  161. write_zsreg(uap, R1, regs[R1]);
  162. /* Enable interrupts */
  163. write_zsreg(uap, R9, regs[R9]);
  164. }
  165. /*
  166. * We do like sunzilog to avoid disrupting pending Tx
  167. * Reprogram the Zilog channel HW registers with the copies found in the
  168. * software state struct. If the transmitter is busy, we defer this update
  169. * until the next TX complete interrupt. Else, we do it right now.
  170. *
  171. * The UART port lock must be held and local interrupts disabled.
  172. */
  173. static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
  174. {
  175. if (!ZS_REGS_HELD(uap)) {
  176. if (ZS_TX_ACTIVE(uap)) {
  177. uap->flags |= PMACZILOG_FLAG_REGS_HELD;
  178. } else {
  179. pmz_debug("pmz: maybe_update_regs: updating\n");
  180. pmz_load_zsregs(uap, uap->curregs);
  181. }
  182. }
  183. }
  184. static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
  185. {
  186. struct tty_struct *tty = NULL;
  187. unsigned char ch, r1, drop, error, flag;
  188. int loops = 0;
  189. /* The interrupt can be enabled when the port isn't open, typically
  190. * that happens when using one port is open and the other closed (stale
  191. * interrupt) or when one port is used as a console.
  192. */
  193. if (!ZS_IS_OPEN(uap)) {
  194. pmz_debug("pmz: draining input\n");
  195. /* Port is closed, drain input data */
  196. for (;;) {
  197. if ((++loops) > 1000)
  198. goto flood;
  199. (void)read_zsreg(uap, R1);
  200. write_zsreg(uap, R0, ERR_RES);
  201. (void)read_zsdata(uap);
  202. ch = read_zsreg(uap, R0);
  203. if (!(ch & Rx_CH_AV))
  204. break;
  205. }
  206. return NULL;
  207. }
  208. /* Sanity check, make sure the old bug is no longer happening */
  209. if (uap->port.state == NULL || uap->port.state->port.tty == NULL) {
  210. WARN_ON(1);
  211. (void)read_zsdata(uap);
  212. return NULL;
  213. }
  214. tty = uap->port.state->port.tty;
  215. while (1) {
  216. error = 0;
  217. drop = 0;
  218. r1 = read_zsreg(uap, R1);
  219. ch = read_zsdata(uap);
  220. if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
  221. write_zsreg(uap, R0, ERR_RES);
  222. zssync(uap);
  223. }
  224. ch &= uap->parity_mask;
  225. if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
  226. uap->flags &= ~PMACZILOG_FLAG_BREAK;
  227. }
  228. #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
  229. #ifdef USE_CTRL_O_SYSRQ
  230. /* Handle the SysRq ^O Hack */
  231. if (ch == '\x0f') {
  232. uap->port.sysrq = jiffies + HZ*5;
  233. goto next_char;
  234. }
  235. #endif /* USE_CTRL_O_SYSRQ */
  236. if (uap->port.sysrq) {
  237. int swallow;
  238. spin_unlock(&uap->port.lock);
  239. swallow = uart_handle_sysrq_char(&uap->port, ch);
  240. spin_lock(&uap->port.lock);
  241. if (swallow)
  242. goto next_char;
  243. }
  244. #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
  245. /* A real serial line, record the character and status. */
  246. if (drop)
  247. goto next_char;
  248. flag = TTY_NORMAL;
  249. uap->port.icount.rx++;
  250. if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
  251. error = 1;
  252. if (r1 & BRK_ABRT) {
  253. pmz_debug("pmz: got break !\n");
  254. r1 &= ~(PAR_ERR | CRC_ERR);
  255. uap->port.icount.brk++;
  256. if (uart_handle_break(&uap->port))
  257. goto next_char;
  258. }
  259. else if (r1 & PAR_ERR)
  260. uap->port.icount.parity++;
  261. else if (r1 & CRC_ERR)
  262. uap->port.icount.frame++;
  263. if (r1 & Rx_OVR)
  264. uap->port.icount.overrun++;
  265. r1 &= uap->port.read_status_mask;
  266. if (r1 & BRK_ABRT)
  267. flag = TTY_BREAK;
  268. else if (r1 & PAR_ERR)
  269. flag = TTY_PARITY;
  270. else if (r1 & CRC_ERR)
  271. flag = TTY_FRAME;
  272. }
  273. if (uap->port.ignore_status_mask == 0xff ||
  274. (r1 & uap->port.ignore_status_mask) == 0) {
  275. tty_insert_flip_char(tty, ch, flag);
  276. }
  277. if (r1 & Rx_OVR)
  278. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  279. next_char:
  280. /* We can get stuck in an infinite loop getting char 0 when the
  281. * line is in a wrong HW state, we break that here.
  282. * When that happens, I disable the receive side of the driver.
  283. * Note that what I've been experiencing is a real irq loop where
  284. * I'm getting flooded regardless of the actual port speed.
  285. * Something strange is going on with the HW
  286. */
  287. if ((++loops) > 1000)
  288. goto flood;
  289. ch = read_zsreg(uap, R0);
  290. if (!(ch & Rx_CH_AV))
  291. break;
  292. }
  293. return tty;
  294. flood:
  295. uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  296. write_zsreg(uap, R1, uap->curregs[R1]);
  297. zssync(uap);
  298. pmz_error("pmz: rx irq flood !\n");
  299. return tty;
  300. }
  301. static void pmz_status_handle(struct uart_pmac_port *uap)
  302. {
  303. unsigned char status;
  304. status = read_zsreg(uap, R0);
  305. write_zsreg(uap, R0, RES_EXT_INT);
  306. zssync(uap);
  307. if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
  308. if (status & SYNC_HUNT)
  309. uap->port.icount.dsr++;
  310. /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
  311. * But it does not tell us which bit has changed, we have to keep
  312. * track of this ourselves.
  313. * The CTS input is inverted for some reason. -- paulus
  314. */
  315. if ((status ^ uap->prev_status) & DCD)
  316. uart_handle_dcd_change(&uap->port,
  317. (status & DCD));
  318. if ((status ^ uap->prev_status) & CTS)
  319. uart_handle_cts_change(&uap->port,
  320. !(status & CTS));
  321. wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
  322. }
  323. if (status & BRK_ABRT)
  324. uap->flags |= PMACZILOG_FLAG_BREAK;
  325. uap->prev_status = status;
  326. }
  327. static void pmz_transmit_chars(struct uart_pmac_port *uap)
  328. {
  329. struct circ_buf *xmit;
  330. if (ZS_IS_ASLEEP(uap))
  331. return;
  332. if (ZS_IS_CONS(uap)) {
  333. unsigned char status = read_zsreg(uap, R0);
  334. /* TX still busy? Just wait for the next TX done interrupt.
  335. *
  336. * It can occur because of how we do serial console writes. It would
  337. * be nice to transmit console writes just like we normally would for
  338. * a TTY line. (ie. buffered and TX interrupt driven). That is not
  339. * easy because console writes cannot sleep. One solution might be
  340. * to poll on enough port->xmit space becoming free. -DaveM
  341. */
  342. if (!(status & Tx_BUF_EMP))
  343. return;
  344. }
  345. uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
  346. if (ZS_REGS_HELD(uap)) {
  347. pmz_load_zsregs(uap, uap->curregs);
  348. uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
  349. }
  350. if (ZS_TX_STOPPED(uap)) {
  351. uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
  352. goto ack_tx_int;
  353. }
  354. /* Under some circumstances, we see interrupts reported for
  355. * a closed channel. The interrupt mask in R1 is clear, but
  356. * R3 still signals the interrupts and we see them when taking
  357. * an interrupt for the other channel (this could be a qemu
  358. * bug but since the ESCC doc doesn't specify precsiely whether
  359. * R3 interrup status bits are masked by R1 interrupt enable
  360. * bits, better safe than sorry). --BenH.
  361. */
  362. if (!ZS_IS_OPEN(uap))
  363. goto ack_tx_int;
  364. if (uap->port.x_char) {
  365. uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
  366. write_zsdata(uap, uap->port.x_char);
  367. zssync(uap);
  368. uap->port.icount.tx++;
  369. uap->port.x_char = 0;
  370. return;
  371. }
  372. if (uap->port.state == NULL)
  373. goto ack_tx_int;
  374. xmit = &uap->port.state->xmit;
  375. if (uart_circ_empty(xmit)) {
  376. uart_write_wakeup(&uap->port);
  377. goto ack_tx_int;
  378. }
  379. if (uart_tx_stopped(&uap->port))
  380. goto ack_tx_int;
  381. uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
  382. write_zsdata(uap, xmit->buf[xmit->tail]);
  383. zssync(uap);
  384. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  385. uap->port.icount.tx++;
  386. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  387. uart_write_wakeup(&uap->port);
  388. return;
  389. ack_tx_int:
  390. write_zsreg(uap, R0, RES_Tx_P);
  391. zssync(uap);
  392. }
  393. /* Hrm... we register that twice, fixme later.... */
  394. static irqreturn_t pmz_interrupt(int irq, void *dev_id)
  395. {
  396. struct uart_pmac_port *uap = dev_id;
  397. struct uart_pmac_port *uap_a;
  398. struct uart_pmac_port *uap_b;
  399. int rc = IRQ_NONE;
  400. struct tty_struct *tty;
  401. u8 r3;
  402. uap_a = pmz_get_port_A(uap);
  403. uap_b = uap_a->mate;
  404. spin_lock(&uap_a->port.lock);
  405. r3 = read_zsreg(uap_a, R3);
  406. #ifdef DEBUG_HARD
  407. pmz_debug("irq, r3: %x\n", r3);
  408. #endif
  409. /* Channel A */
  410. tty = NULL;
  411. if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
  412. write_zsreg(uap_a, R0, RES_H_IUS);
  413. zssync(uap_a);
  414. if (r3 & CHAEXT)
  415. pmz_status_handle(uap_a);
  416. if (r3 & CHARxIP)
  417. tty = pmz_receive_chars(uap_a);
  418. if (r3 & CHATxIP)
  419. pmz_transmit_chars(uap_a);
  420. rc = IRQ_HANDLED;
  421. }
  422. spin_unlock(&uap_a->port.lock);
  423. if (tty != NULL)
  424. tty_flip_buffer_push(tty);
  425. if (uap_b->node == NULL)
  426. goto out;
  427. spin_lock(&uap_b->port.lock);
  428. tty = NULL;
  429. if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
  430. write_zsreg(uap_b, R0, RES_H_IUS);
  431. zssync(uap_b);
  432. if (r3 & CHBEXT)
  433. pmz_status_handle(uap_b);
  434. if (r3 & CHBRxIP)
  435. tty = pmz_receive_chars(uap_b);
  436. if (r3 & CHBTxIP)
  437. pmz_transmit_chars(uap_b);
  438. rc = IRQ_HANDLED;
  439. }
  440. spin_unlock(&uap_b->port.lock);
  441. if (tty != NULL)
  442. tty_flip_buffer_push(tty);
  443. out:
  444. #ifdef DEBUG_HARD
  445. pmz_debug("irq done.\n");
  446. #endif
  447. return rc;
  448. }
  449. /*
  450. * Peek the status register, lock not held by caller
  451. */
  452. static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
  453. {
  454. unsigned long flags;
  455. u8 status;
  456. spin_lock_irqsave(&uap->port.lock, flags);
  457. status = read_zsreg(uap, R0);
  458. spin_unlock_irqrestore(&uap->port.lock, flags);
  459. return status;
  460. }
  461. /*
  462. * Check if transmitter is empty
  463. * The port lock is not held.
  464. */
  465. static unsigned int pmz_tx_empty(struct uart_port *port)
  466. {
  467. struct uart_pmac_port *uap = to_pmz(port);
  468. unsigned char status;
  469. if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
  470. return TIOCSER_TEMT;
  471. status = pmz_peek_status(to_pmz(port));
  472. if (status & Tx_BUF_EMP)
  473. return TIOCSER_TEMT;
  474. return 0;
  475. }
  476. /*
  477. * Set Modem Control (RTS & DTR) bits
  478. * The port lock is held and interrupts are disabled.
  479. * Note: Shall we really filter out RTS on external ports or
  480. * should that be dealt at higher level only ?
  481. */
  482. static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
  483. {
  484. struct uart_pmac_port *uap = to_pmz(port);
  485. unsigned char set_bits, clear_bits;
  486. /* Do nothing for irda for now... */
  487. if (ZS_IS_IRDA(uap))
  488. return;
  489. /* We get called during boot with a port not up yet */
  490. if (ZS_IS_ASLEEP(uap) ||
  491. !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
  492. return;
  493. set_bits = clear_bits = 0;
  494. if (ZS_IS_INTMODEM(uap)) {
  495. if (mctrl & TIOCM_RTS)
  496. set_bits |= RTS;
  497. else
  498. clear_bits |= RTS;
  499. }
  500. if (mctrl & TIOCM_DTR)
  501. set_bits |= DTR;
  502. else
  503. clear_bits |= DTR;
  504. /* NOTE: Not subject to 'transmitter active' rule. */
  505. uap->curregs[R5] |= set_bits;
  506. uap->curregs[R5] &= ~clear_bits;
  507. if (ZS_IS_ASLEEP(uap))
  508. return;
  509. write_zsreg(uap, R5, uap->curregs[R5]);
  510. pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
  511. set_bits, clear_bits, uap->curregs[R5]);
  512. zssync(uap);
  513. }
  514. /*
  515. * Get Modem Control bits (only the input ones, the core will
  516. * or that with a cached value of the control ones)
  517. * The port lock is held and interrupts are disabled.
  518. */
  519. static unsigned int pmz_get_mctrl(struct uart_port *port)
  520. {
  521. struct uart_pmac_port *uap = to_pmz(port);
  522. unsigned char status;
  523. unsigned int ret;
  524. if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
  525. return 0;
  526. status = read_zsreg(uap, R0);
  527. ret = 0;
  528. if (status & DCD)
  529. ret |= TIOCM_CAR;
  530. if (status & SYNC_HUNT)
  531. ret |= TIOCM_DSR;
  532. if (!(status & CTS))
  533. ret |= TIOCM_CTS;
  534. return ret;
  535. }
  536. /*
  537. * Stop TX side. Dealt like sunzilog at next Tx interrupt,
  538. * though for DMA, we will have to do a bit more.
  539. * The port lock is held and interrupts are disabled.
  540. */
  541. static void pmz_stop_tx(struct uart_port *port)
  542. {
  543. to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
  544. }
  545. /*
  546. * Kick the Tx side.
  547. * The port lock is held and interrupts are disabled.
  548. */
  549. static void pmz_start_tx(struct uart_port *port)
  550. {
  551. struct uart_pmac_port *uap = to_pmz(port);
  552. unsigned char status;
  553. pmz_debug("pmz: start_tx()\n");
  554. uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
  555. uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
  556. if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
  557. return;
  558. status = read_zsreg(uap, R0);
  559. /* TX busy? Just wait for the TX done interrupt. */
  560. if (!(status & Tx_BUF_EMP))
  561. return;
  562. /* Send the first character to jump-start the TX done
  563. * IRQ sending engine.
  564. */
  565. if (port->x_char) {
  566. write_zsdata(uap, port->x_char);
  567. zssync(uap);
  568. port->icount.tx++;
  569. port->x_char = 0;
  570. } else {
  571. struct circ_buf *xmit = &port->state->xmit;
  572. write_zsdata(uap, xmit->buf[xmit->tail]);
  573. zssync(uap);
  574. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  575. port->icount.tx++;
  576. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  577. uart_write_wakeup(&uap->port);
  578. }
  579. pmz_debug("pmz: start_tx() done.\n");
  580. }
  581. /*
  582. * Stop Rx side, basically disable emitting of
  583. * Rx interrupts on the port. We don't disable the rx
  584. * side of the chip proper though
  585. * The port lock is held.
  586. */
  587. static void pmz_stop_rx(struct uart_port *port)
  588. {
  589. struct uart_pmac_port *uap = to_pmz(port);
  590. if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
  591. return;
  592. pmz_debug("pmz: stop_rx()()\n");
  593. /* Disable all RX interrupts. */
  594. uap->curregs[R1] &= ~RxINT_MASK;
  595. pmz_maybe_update_regs(uap);
  596. pmz_debug("pmz: stop_rx() done.\n");
  597. }
  598. /*
  599. * Enable modem status change interrupts
  600. * The port lock is held.
  601. */
  602. static void pmz_enable_ms(struct uart_port *port)
  603. {
  604. struct uart_pmac_port *uap = to_pmz(port);
  605. unsigned char new_reg;
  606. if (ZS_IS_IRDA(uap) || uap->node == NULL)
  607. return;
  608. new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
  609. if (new_reg != uap->curregs[R15]) {
  610. uap->curregs[R15] = new_reg;
  611. if (ZS_IS_ASLEEP(uap))
  612. return;
  613. /* NOTE: Not subject to 'transmitter active' rule. */
  614. write_zsreg(uap, R15, uap->curregs[R15]);
  615. }
  616. }
  617. /*
  618. * Control break state emission
  619. * The port lock is not held.
  620. */
  621. static void pmz_break_ctl(struct uart_port *port, int break_state)
  622. {
  623. struct uart_pmac_port *uap = to_pmz(port);
  624. unsigned char set_bits, clear_bits, new_reg;
  625. unsigned long flags;
  626. if (uap->node == NULL)
  627. return;
  628. set_bits = clear_bits = 0;
  629. if (break_state)
  630. set_bits |= SND_BRK;
  631. else
  632. clear_bits |= SND_BRK;
  633. spin_lock_irqsave(&port->lock, flags);
  634. new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
  635. if (new_reg != uap->curregs[R5]) {
  636. uap->curregs[R5] = new_reg;
  637. /* NOTE: Not subject to 'transmitter active' rule. */
  638. if (ZS_IS_ASLEEP(uap)) {
  639. spin_unlock_irqrestore(&port->lock, flags);
  640. return;
  641. }
  642. write_zsreg(uap, R5, uap->curregs[R5]);
  643. }
  644. spin_unlock_irqrestore(&port->lock, flags);
  645. }
  646. #ifdef CONFIG_PPC_PMAC
  647. /*
  648. * Turn power on or off to the SCC and associated stuff
  649. * (port drivers, modem, IR port, etc.)
  650. * Returns the number of milliseconds we should wait before
  651. * trying to use the port.
  652. */
  653. static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
  654. {
  655. int delay = 0;
  656. int rc;
  657. if (state) {
  658. rc = pmac_call_feature(
  659. PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
  660. pmz_debug("port power on result: %d\n", rc);
  661. if (ZS_IS_INTMODEM(uap)) {
  662. rc = pmac_call_feature(
  663. PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
  664. delay = 2500; /* wait for 2.5s before using */
  665. pmz_debug("modem power result: %d\n", rc);
  666. }
  667. } else {
  668. /* TODO: Make that depend on a timer, don't power down
  669. * immediately
  670. */
  671. if (ZS_IS_INTMODEM(uap)) {
  672. rc = pmac_call_feature(
  673. PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
  674. pmz_debug("port power off result: %d\n", rc);
  675. }
  676. pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
  677. }
  678. return delay;
  679. }
  680. #else
  681. static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
  682. {
  683. return 0;
  684. }
  685. #endif /* !CONFIG_PPC_PMAC */
  686. /*
  687. * FixZeroBug....Works around a bug in the SCC receiving channel.
  688. * Inspired from Darwin code, 15 Sept. 2000 -DanM
  689. *
  690. * The following sequence prevents a problem that is seen with O'Hare ASICs
  691. * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
  692. * at the input to the receiver becomes 'stuck' and locks up the receiver.
  693. * This problem can occur as a result of a zero bit at the receiver input
  694. * coincident with any of the following events:
  695. *
  696. * The SCC is initialized (hardware or software).
  697. * A framing error is detected.
  698. * The clocking option changes from synchronous or X1 asynchronous
  699. * clocking to X16, X32, or X64 asynchronous clocking.
  700. * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
  701. *
  702. * This workaround attempts to recover from the lockup condition by placing
  703. * the SCC in synchronous loopback mode with a fast clock before programming
  704. * any of the asynchronous modes.
  705. */
  706. static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
  707. {
  708. write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
  709. zssync(uap);
  710. udelay(10);
  711. write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
  712. zssync(uap);
  713. write_zsreg(uap, 4, X1CLK | MONSYNC);
  714. write_zsreg(uap, 3, Rx8);
  715. write_zsreg(uap, 5, Tx8 | RTS);
  716. write_zsreg(uap, 9, NV); /* Didn't we already do this? */
  717. write_zsreg(uap, 11, RCBR | TCBR);
  718. write_zsreg(uap, 12, 0);
  719. write_zsreg(uap, 13, 0);
  720. write_zsreg(uap, 14, (LOOPBAK | BRSRC));
  721. write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
  722. write_zsreg(uap, 3, Rx8 | RxENABLE);
  723. write_zsreg(uap, 0, RES_EXT_INT);
  724. write_zsreg(uap, 0, RES_EXT_INT);
  725. write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
  726. /* The channel should be OK now, but it is probably receiving
  727. * loopback garbage.
  728. * Switch to asynchronous mode, disable the receiver,
  729. * and discard everything in the receive buffer.
  730. */
  731. write_zsreg(uap, 9, NV);
  732. write_zsreg(uap, 4, X16CLK | SB_MASK);
  733. write_zsreg(uap, 3, Rx8);
  734. while (read_zsreg(uap, 0) & Rx_CH_AV) {
  735. (void)read_zsreg(uap, 8);
  736. write_zsreg(uap, 0, RES_EXT_INT);
  737. write_zsreg(uap, 0, ERR_RES);
  738. }
  739. }
  740. /*
  741. * Real startup routine, powers up the hardware and sets up
  742. * the SCC. Returns a delay in ms where you need to wait before
  743. * actually using the port, this is typically the internal modem
  744. * powerup delay. This routine expect the lock to be taken.
  745. */
  746. static int __pmz_startup(struct uart_pmac_port *uap)
  747. {
  748. int pwr_delay = 0;
  749. memset(&uap->curregs, 0, sizeof(uap->curregs));
  750. /* Power up the SCC & underlying hardware (modem/irda) */
  751. pwr_delay = pmz_set_scc_power(uap, 1);
  752. /* Nice buggy HW ... */
  753. pmz_fix_zero_bug_scc(uap);
  754. /* Reset the channel */
  755. uap->curregs[R9] = 0;
  756. write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
  757. zssync(uap);
  758. udelay(10);
  759. write_zsreg(uap, 9, 0);
  760. zssync(uap);
  761. /* Clear the interrupt registers */
  762. write_zsreg(uap, R1, 0);
  763. write_zsreg(uap, R0, ERR_RES);
  764. write_zsreg(uap, R0, ERR_RES);
  765. write_zsreg(uap, R0, RES_H_IUS);
  766. write_zsreg(uap, R0, RES_H_IUS);
  767. /* Setup some valid baud rate */
  768. uap->curregs[R4] = X16CLK | SB1;
  769. uap->curregs[R3] = Rx8;
  770. uap->curregs[R5] = Tx8 | RTS;
  771. if (!ZS_IS_IRDA(uap))
  772. uap->curregs[R5] |= DTR;
  773. uap->curregs[R12] = 0;
  774. uap->curregs[R13] = 0;
  775. uap->curregs[R14] = BRENAB;
  776. /* Clear handshaking, enable BREAK interrupts */
  777. uap->curregs[R15] = BRKIE;
  778. /* Master interrupt enable */
  779. uap->curregs[R9] |= NV | MIE;
  780. pmz_load_zsregs(uap, uap->curregs);
  781. /* Enable receiver and transmitter. */
  782. write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
  783. write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
  784. /* Remember status for DCD/CTS changes */
  785. uap->prev_status = read_zsreg(uap, R0);
  786. return pwr_delay;
  787. }
  788. static void pmz_irda_reset(struct uart_pmac_port *uap)
  789. {
  790. uap->curregs[R5] |= DTR;
  791. write_zsreg(uap, R5, uap->curregs[R5]);
  792. zssync(uap);
  793. mdelay(110);
  794. uap->curregs[R5] &= ~DTR;
  795. write_zsreg(uap, R5, uap->curregs[R5]);
  796. zssync(uap);
  797. mdelay(10);
  798. }
  799. /*
  800. * This is the "normal" startup routine, using the above one
  801. * wrapped with the lock and doing a schedule delay
  802. */
  803. static int pmz_startup(struct uart_port *port)
  804. {
  805. struct uart_pmac_port *uap = to_pmz(port);
  806. unsigned long flags;
  807. int pwr_delay = 0;
  808. pmz_debug("pmz: startup()\n");
  809. if (ZS_IS_ASLEEP(uap))
  810. return -EAGAIN;
  811. if (uap->node == NULL)
  812. return -ENODEV;
  813. mutex_lock(&pmz_irq_mutex);
  814. uap->flags |= PMACZILOG_FLAG_IS_OPEN;
  815. /* A console is never powered down. Else, power up and
  816. * initialize the chip
  817. */
  818. if (!ZS_IS_CONS(uap)) {
  819. spin_lock_irqsave(&port->lock, flags);
  820. pwr_delay = __pmz_startup(uap);
  821. spin_unlock_irqrestore(&port->lock, flags);
  822. }
  823. pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
  824. if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
  825. "SCC", uap)) {
  826. pmz_error("Unable to register zs interrupt handler.\n");
  827. pmz_set_scc_power(uap, 0);
  828. mutex_unlock(&pmz_irq_mutex);
  829. return -ENXIO;
  830. }
  831. mutex_unlock(&pmz_irq_mutex);
  832. /* Right now, we deal with delay by blocking here, I'll be
  833. * smarter later on
  834. */
  835. if (pwr_delay != 0) {
  836. pmz_debug("pmz: delaying %d ms\n", pwr_delay);
  837. msleep(pwr_delay);
  838. }
  839. /* IrDA reset is done now */
  840. if (ZS_IS_IRDA(uap))
  841. pmz_irda_reset(uap);
  842. /* Enable interrupts emission from the chip */
  843. spin_lock_irqsave(&port->lock, flags);
  844. uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
  845. if (!ZS_IS_EXTCLK(uap))
  846. uap->curregs[R1] |= EXT_INT_ENAB;
  847. write_zsreg(uap, R1, uap->curregs[R1]);
  848. spin_unlock_irqrestore(&port->lock, flags);
  849. pmz_debug("pmz: startup() done.\n");
  850. return 0;
  851. }
  852. static void pmz_shutdown(struct uart_port *port)
  853. {
  854. struct uart_pmac_port *uap = to_pmz(port);
  855. unsigned long flags;
  856. pmz_debug("pmz: shutdown()\n");
  857. if (uap->node == NULL)
  858. return;
  859. mutex_lock(&pmz_irq_mutex);
  860. /* Release interrupt handler */
  861. free_irq(uap->port.irq, uap);
  862. spin_lock_irqsave(&port->lock, flags);
  863. uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
  864. if (!ZS_IS_OPEN(uap->mate))
  865. pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
  866. /* Disable interrupts */
  867. if (!ZS_IS_ASLEEP(uap)) {
  868. uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  869. write_zsreg(uap, R1, uap->curregs[R1]);
  870. zssync(uap);
  871. }
  872. if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
  873. spin_unlock_irqrestore(&port->lock, flags);
  874. mutex_unlock(&pmz_irq_mutex);
  875. return;
  876. }
  877. /* Disable receiver and transmitter. */
  878. uap->curregs[R3] &= ~RxENABLE;
  879. uap->curregs[R5] &= ~TxENABLE;
  880. /* Disable all interrupts and BRK assertion. */
  881. uap->curregs[R5] &= ~SND_BRK;
  882. pmz_maybe_update_regs(uap);
  883. /* Shut the chip down */
  884. pmz_set_scc_power(uap, 0);
  885. spin_unlock_irqrestore(&port->lock, flags);
  886. mutex_unlock(&pmz_irq_mutex);
  887. pmz_debug("pmz: shutdown() done.\n");
  888. }
  889. /* Shared by TTY driver and serial console setup. The port lock is held
  890. * and local interrupts are disabled.
  891. */
  892. static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
  893. unsigned int iflag, unsigned long baud)
  894. {
  895. int brg;
  896. /* Switch to external clocking for IrDA high clock rates. That
  897. * code could be re-used for Midi interfaces with different
  898. * multipliers
  899. */
  900. if (baud >= 115200 && ZS_IS_IRDA(uap)) {
  901. uap->curregs[R4] = X1CLK;
  902. uap->curregs[R11] = RCTRxCP | TCTRxCP;
  903. uap->curregs[R14] = 0; /* BRG off */
  904. uap->curregs[R12] = 0;
  905. uap->curregs[R13] = 0;
  906. uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
  907. } else {
  908. switch (baud) {
  909. case ZS_CLOCK/16: /* 230400 */
  910. uap->curregs[R4] = X16CLK;
  911. uap->curregs[R11] = 0;
  912. uap->curregs[R14] = 0;
  913. break;
  914. case ZS_CLOCK/32: /* 115200 */
  915. uap->curregs[R4] = X32CLK;
  916. uap->curregs[R11] = 0;
  917. uap->curregs[R14] = 0;
  918. break;
  919. default:
  920. uap->curregs[R4] = X16CLK;
  921. uap->curregs[R11] = TCBR | RCBR;
  922. brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
  923. uap->curregs[R12] = (brg & 255);
  924. uap->curregs[R13] = ((brg >> 8) & 255);
  925. uap->curregs[R14] = BRENAB;
  926. }
  927. uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
  928. }
  929. /* Character size, stop bits, and parity. */
  930. uap->curregs[3] &= ~RxN_MASK;
  931. uap->curregs[5] &= ~TxN_MASK;
  932. switch (cflag & CSIZE) {
  933. case CS5:
  934. uap->curregs[3] |= Rx5;
  935. uap->curregs[5] |= Tx5;
  936. uap->parity_mask = 0x1f;
  937. break;
  938. case CS6:
  939. uap->curregs[3] |= Rx6;
  940. uap->curregs[5] |= Tx6;
  941. uap->parity_mask = 0x3f;
  942. break;
  943. case CS7:
  944. uap->curregs[3] |= Rx7;
  945. uap->curregs[5] |= Tx7;
  946. uap->parity_mask = 0x7f;
  947. break;
  948. case CS8:
  949. default:
  950. uap->curregs[3] |= Rx8;
  951. uap->curregs[5] |= Tx8;
  952. uap->parity_mask = 0xff;
  953. break;
  954. };
  955. uap->curregs[4] &= ~(SB_MASK);
  956. if (cflag & CSTOPB)
  957. uap->curregs[4] |= SB2;
  958. else
  959. uap->curregs[4] |= SB1;
  960. if (cflag & PARENB)
  961. uap->curregs[4] |= PAR_ENAB;
  962. else
  963. uap->curregs[4] &= ~PAR_ENAB;
  964. if (!(cflag & PARODD))
  965. uap->curregs[4] |= PAR_EVEN;
  966. else
  967. uap->curregs[4] &= ~PAR_EVEN;
  968. uap->port.read_status_mask = Rx_OVR;
  969. if (iflag & INPCK)
  970. uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
  971. if (iflag & (BRKINT | PARMRK))
  972. uap->port.read_status_mask |= BRK_ABRT;
  973. uap->port.ignore_status_mask = 0;
  974. if (iflag & IGNPAR)
  975. uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
  976. if (iflag & IGNBRK) {
  977. uap->port.ignore_status_mask |= BRK_ABRT;
  978. if (iflag & IGNPAR)
  979. uap->port.ignore_status_mask |= Rx_OVR;
  980. }
  981. if ((cflag & CREAD) == 0)
  982. uap->port.ignore_status_mask = 0xff;
  983. }
  984. /*
  985. * Set the irda codec on the imac to the specified baud rate.
  986. */
  987. static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
  988. {
  989. u8 cmdbyte;
  990. int t, version;
  991. switch (*baud) {
  992. /* SIR modes */
  993. case 2400:
  994. cmdbyte = 0x53;
  995. break;
  996. case 4800:
  997. cmdbyte = 0x52;
  998. break;
  999. case 9600:
  1000. cmdbyte = 0x51;
  1001. break;
  1002. case 19200:
  1003. cmdbyte = 0x50;
  1004. break;
  1005. case 38400:
  1006. cmdbyte = 0x4f;
  1007. break;
  1008. case 57600:
  1009. cmdbyte = 0x4e;
  1010. break;
  1011. case 115200:
  1012. cmdbyte = 0x4d;
  1013. break;
  1014. /* The FIR modes aren't really supported at this point, how
  1015. * do we select the speed ? via the FCR on KeyLargo ?
  1016. */
  1017. case 1152000:
  1018. cmdbyte = 0;
  1019. break;
  1020. case 4000000:
  1021. cmdbyte = 0;
  1022. break;
  1023. default: /* 9600 */
  1024. cmdbyte = 0x51;
  1025. *baud = 9600;
  1026. break;
  1027. }
  1028. /* Wait for transmitter to drain */
  1029. t = 10000;
  1030. while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
  1031. || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
  1032. if (--t <= 0) {
  1033. pmz_error("transmitter didn't drain\n");
  1034. return;
  1035. }
  1036. udelay(10);
  1037. }
  1038. /* Drain the receiver too */
  1039. t = 100;
  1040. (void)read_zsdata(uap);
  1041. (void)read_zsdata(uap);
  1042. (void)read_zsdata(uap);
  1043. mdelay(10);
  1044. while (read_zsreg(uap, R0) & Rx_CH_AV) {
  1045. read_zsdata(uap);
  1046. mdelay(10);
  1047. if (--t <= 0) {
  1048. pmz_error("receiver didn't drain\n");
  1049. return;
  1050. }
  1051. }
  1052. /* Switch to command mode */
  1053. uap->curregs[R5] |= DTR;
  1054. write_zsreg(uap, R5, uap->curregs[R5]);
  1055. zssync(uap);
  1056. mdelay(1);
  1057. /* Switch SCC to 19200 */
  1058. pmz_convert_to_zs(uap, CS8, 0, 19200);
  1059. pmz_load_zsregs(uap, uap->curregs);
  1060. mdelay(1);
  1061. /* Write get_version command byte */
  1062. write_zsdata(uap, 1);
  1063. t = 5000;
  1064. while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
  1065. if (--t <= 0) {
  1066. pmz_error("irda_setup timed out on get_version byte\n");
  1067. goto out;
  1068. }
  1069. udelay(10);
  1070. }
  1071. version = read_zsdata(uap);
  1072. if (version < 4) {
  1073. pmz_info("IrDA: dongle version %d not supported\n", version);
  1074. goto out;
  1075. }
  1076. /* Send speed mode */
  1077. write_zsdata(uap, cmdbyte);
  1078. t = 5000;
  1079. while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
  1080. if (--t <= 0) {
  1081. pmz_error("irda_setup timed out on speed mode byte\n");
  1082. goto out;
  1083. }
  1084. udelay(10);
  1085. }
  1086. t = read_zsdata(uap);
  1087. if (t != cmdbyte)
  1088. pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
  1089. pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
  1090. *baud, version);
  1091. (void)read_zsdata(uap);
  1092. (void)read_zsdata(uap);
  1093. (void)read_zsdata(uap);
  1094. out:
  1095. /* Switch back to data mode */
  1096. uap->curregs[R5] &= ~DTR;
  1097. write_zsreg(uap, R5, uap->curregs[R5]);
  1098. zssync(uap);
  1099. (void)read_zsdata(uap);
  1100. (void)read_zsdata(uap);
  1101. (void)read_zsdata(uap);
  1102. }
  1103. static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
  1104. struct ktermios *old)
  1105. {
  1106. struct uart_pmac_port *uap = to_pmz(port);
  1107. unsigned long baud;
  1108. pmz_debug("pmz: set_termios()\n");
  1109. if (ZS_IS_ASLEEP(uap))
  1110. return;
  1111. memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
  1112. /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
  1113. * on the IR dongle. Note that the IRTTY driver currently doesn't know
  1114. * about the FIR mode and high speed modes. So these are unused. For
  1115. * implementing proper support for these, we should probably add some
  1116. * DMA as well, at least on the Rx side, which isn't a simple thing
  1117. * at this point.
  1118. */
  1119. if (ZS_IS_IRDA(uap)) {
  1120. /* Calc baud rate */
  1121. baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
  1122. pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
  1123. /* Cet the irda codec to the right rate */
  1124. pmz_irda_setup(uap, &baud);
  1125. /* Set final baud rate */
  1126. pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
  1127. pmz_load_zsregs(uap, uap->curregs);
  1128. zssync(uap);
  1129. } else {
  1130. baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
  1131. pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
  1132. /* Make sure modem status interrupts are correctly configured */
  1133. if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
  1134. uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
  1135. uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
  1136. } else {
  1137. uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
  1138. uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
  1139. }
  1140. /* Load registers to the chip */
  1141. pmz_maybe_update_regs(uap);
  1142. }
  1143. uart_update_timeout(port, termios->c_cflag, baud);
  1144. pmz_debug("pmz: set_termios() done.\n");
  1145. }
  1146. /* The port lock is not held. */
  1147. static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
  1148. struct ktermios *old)
  1149. {
  1150. struct uart_pmac_port *uap = to_pmz(port);
  1151. unsigned long flags;
  1152. spin_lock_irqsave(&port->lock, flags);
  1153. /* Disable IRQs on the port */
  1154. uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  1155. write_zsreg(uap, R1, uap->curregs[R1]);
  1156. /* Setup new port configuration */
  1157. __pmz_set_termios(port, termios, old);
  1158. /* Re-enable IRQs on the port */
  1159. if (ZS_IS_OPEN(uap)) {
  1160. uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
  1161. if (!ZS_IS_EXTCLK(uap))
  1162. uap->curregs[R1] |= EXT_INT_ENAB;
  1163. write_zsreg(uap, R1, uap->curregs[R1]);
  1164. }
  1165. spin_unlock_irqrestore(&port->lock, flags);
  1166. }
  1167. static const char *pmz_type(struct uart_port *port)
  1168. {
  1169. struct uart_pmac_port *uap = to_pmz(port);
  1170. if (ZS_IS_IRDA(uap))
  1171. return "Z85c30 ESCC - Infrared port";
  1172. else if (ZS_IS_INTMODEM(uap))
  1173. return "Z85c30 ESCC - Internal modem";
  1174. return "Z85c30 ESCC - Serial port";
  1175. }
  1176. /* We do not request/release mappings of the registers here, this
  1177. * happens at early serial probe time.
  1178. */
  1179. static void pmz_release_port(struct uart_port *port)
  1180. {
  1181. }
  1182. static int pmz_request_port(struct uart_port *port)
  1183. {
  1184. return 0;
  1185. }
  1186. /* These do not need to do anything interesting either. */
  1187. static void pmz_config_port(struct uart_port *port, int flags)
  1188. {
  1189. }
  1190. /* We do not support letting the user mess with the divisor, IRQ, etc. */
  1191. static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
  1192. {
  1193. return -EINVAL;
  1194. }
  1195. #ifdef CONFIG_CONSOLE_POLL
  1196. static int pmz_poll_get_char(struct uart_port *port)
  1197. {
  1198. struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
  1199. while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0)
  1200. udelay(5);
  1201. return read_zsdata(uap);
  1202. }
  1203. static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
  1204. {
  1205. struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
  1206. /* Wait for the transmit buffer to empty. */
  1207. while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
  1208. udelay(5);
  1209. write_zsdata(uap, c);
  1210. }
  1211. #endif /* CONFIG_CONSOLE_POLL */
  1212. static struct uart_ops pmz_pops = {
  1213. .tx_empty = pmz_tx_empty,
  1214. .set_mctrl = pmz_set_mctrl,
  1215. .get_mctrl = pmz_get_mctrl,
  1216. .stop_tx = pmz_stop_tx,
  1217. .start_tx = pmz_start_tx,
  1218. .stop_rx = pmz_stop_rx,
  1219. .enable_ms = pmz_enable_ms,
  1220. .break_ctl = pmz_break_ctl,
  1221. .startup = pmz_startup,
  1222. .shutdown = pmz_shutdown,
  1223. .set_termios = pmz_set_termios,
  1224. .type = pmz_type,
  1225. .release_port = pmz_release_port,
  1226. .request_port = pmz_request_port,
  1227. .config_port = pmz_config_port,
  1228. .verify_port = pmz_verify_port,
  1229. #ifdef CONFIG_CONSOLE_POLL
  1230. .poll_get_char = pmz_poll_get_char,
  1231. .poll_put_char = pmz_poll_put_char,
  1232. #endif
  1233. };
  1234. #ifdef CONFIG_PPC_PMAC
  1235. /*
  1236. * Setup one port structure after probing, HW is down at this point,
  1237. * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
  1238. * register our console before uart_add_one_port() is called
  1239. */
  1240. static int __init pmz_init_port(struct uart_pmac_port *uap)
  1241. {
  1242. struct device_node *np = uap->node;
  1243. const char *conn;
  1244. const struct slot_names_prop {
  1245. int count;
  1246. char name[1];
  1247. } *slots;
  1248. int len;
  1249. struct resource r_ports, r_rxdma, r_txdma;
  1250. /*
  1251. * Request & map chip registers
  1252. */
  1253. if (of_address_to_resource(np, 0, &r_ports))
  1254. return -ENODEV;
  1255. uap->port.mapbase = r_ports.start;
  1256. uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
  1257. uap->control_reg = uap->port.membase;
  1258. uap->data_reg = uap->control_reg + 0x10;
  1259. /*
  1260. * Request & map DBDMA registers
  1261. */
  1262. #ifdef HAS_DBDMA
  1263. if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
  1264. of_address_to_resource(np, 2, &r_rxdma) == 0)
  1265. uap->flags |= PMACZILOG_FLAG_HAS_DMA;
  1266. #else
  1267. memset(&r_txdma, 0, sizeof(struct resource));
  1268. memset(&r_rxdma, 0, sizeof(struct resource));
  1269. #endif
  1270. if (ZS_HAS_DMA(uap)) {
  1271. uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
  1272. if (uap->tx_dma_regs == NULL) {
  1273. uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
  1274. goto no_dma;
  1275. }
  1276. uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
  1277. if (uap->rx_dma_regs == NULL) {
  1278. iounmap(uap->tx_dma_regs);
  1279. uap->tx_dma_regs = NULL;
  1280. uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
  1281. goto no_dma;
  1282. }
  1283. uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
  1284. uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
  1285. }
  1286. no_dma:
  1287. /*
  1288. * Detect port type
  1289. */
  1290. if (of_device_is_compatible(np, "cobalt"))
  1291. uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
  1292. conn = of_get_property(np, "AAPL,connector", &len);
  1293. if (conn && (strcmp(conn, "infrared") == 0))
  1294. uap->flags |= PMACZILOG_FLAG_IS_IRDA;
  1295. uap->port_type = PMAC_SCC_ASYNC;
  1296. /* 1999 Powerbook G3 has slot-names property instead */
  1297. slots = of_get_property(np, "slot-names", &len);
  1298. if (slots && slots->count > 0) {
  1299. if (strcmp(slots->name, "IrDA") == 0)
  1300. uap->flags |= PMACZILOG_FLAG_IS_IRDA;
  1301. else if (strcmp(slots->name, "Modem") == 0)
  1302. uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
  1303. }
  1304. if (ZS_IS_IRDA(uap))
  1305. uap->port_type = PMAC_SCC_IRDA;
  1306. if (ZS_IS_INTMODEM(uap)) {
  1307. struct device_node* i2c_modem =
  1308. of_find_node_by_name(NULL, "i2c-modem");
  1309. if (i2c_modem) {
  1310. const char* mid =
  1311. of_get_property(i2c_modem, "modem-id", NULL);
  1312. if (mid) switch(*mid) {
  1313. case 0x04 :
  1314. case 0x05 :
  1315. case 0x07 :
  1316. case 0x08 :
  1317. case 0x0b :
  1318. case 0x0c :
  1319. uap->port_type = PMAC_SCC_I2S1;
  1320. }
  1321. printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
  1322. mid ? (*mid) : 0);
  1323. of_node_put(i2c_modem);
  1324. } else {
  1325. printk(KERN_INFO "pmac_zilog: serial modem detected\n");
  1326. }
  1327. }
  1328. /*
  1329. * Init remaining bits of "port" structure
  1330. */
  1331. uap->port.iotype = UPIO_MEM;
  1332. uap->port.irq = irq_of_parse_and_map(np, 0);
  1333. uap->port.uartclk = ZS_CLOCK;
  1334. uap->port.fifosize = 1;
  1335. uap->port.ops = &pmz_pops;
  1336. uap->port.type = PORT_PMAC_ZILOG;
  1337. uap->port.flags = 0;
  1338. /*
  1339. * Fixup for the port on Gatwick for which the device-tree has
  1340. * missing interrupts. Normally, the macio_dev would contain
  1341. * fixed up interrupt info, but we use the device-tree directly
  1342. * here due to early probing so we need the fixup too.
  1343. */
  1344. if (uap->port.irq == NO_IRQ &&
  1345. np->parent && np->parent->parent &&
  1346. of_device_is_compatible(np->parent->parent, "gatwick")) {
  1347. /* IRQs on gatwick are offset by 64 */
  1348. uap->port.irq = irq_create_mapping(NULL, 64 + 15);
  1349. uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
  1350. uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
  1351. }
  1352. /* Setup some valid baud rate information in the register
  1353. * shadows so we don't write crap there before baud rate is
  1354. * first initialized.
  1355. */
  1356. pmz_convert_to_zs(uap, CS8, 0, 9600);
  1357. return 0;
  1358. }
  1359. /*
  1360. * Get rid of a port on module removal
  1361. */
  1362. static void pmz_dispose_port(struct uart_pmac_port *uap)
  1363. {
  1364. struct device_node *np;
  1365. np = uap->node;
  1366. iounmap(uap->rx_dma_regs);
  1367. iounmap(uap->tx_dma_regs);
  1368. iounmap(uap->control_reg);
  1369. uap->node = NULL;
  1370. of_node_put(np);
  1371. memset(uap, 0, sizeof(struct uart_pmac_port));
  1372. }
  1373. /*
  1374. * Called upon match with an escc node in the device-tree.
  1375. */
  1376. static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
  1377. {
  1378. int i;
  1379. /* Iterate the pmz_ports array to find a matching entry
  1380. */
  1381. for (i = 0; i < MAX_ZS_PORTS; i++)
  1382. if (pmz_ports[i].node == mdev->ofdev.dev.of_node) {
  1383. struct uart_pmac_port *uap = &pmz_ports[i];
  1384. uap->dev = mdev;
  1385. dev_set_drvdata(&mdev->ofdev.dev, uap);
  1386. if (macio_request_resources(uap->dev, "pmac_zilog"))
  1387. printk(KERN_WARNING "%s: Failed to request resource"
  1388. ", port still active\n",
  1389. uap->node->name);
  1390. else
  1391. uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
  1392. return 0;
  1393. }
  1394. return -ENODEV;
  1395. }
  1396. /*
  1397. * That one should not be called, macio isn't really a hotswap device,
  1398. * we don't expect one of those serial ports to go away...
  1399. */
  1400. static int pmz_detach(struct macio_dev *mdev)
  1401. {
  1402. struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
  1403. if (!uap)
  1404. return -ENODEV;
  1405. if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
  1406. macio_release_resources(uap->dev);
  1407. uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
  1408. }
  1409. dev_set_drvdata(&mdev->ofdev.dev, NULL);
  1410. uap->dev = NULL;
  1411. return 0;
  1412. }
  1413. static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
  1414. {
  1415. struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
  1416. struct uart_state *state;
  1417. unsigned long flags;
  1418. if (uap == NULL) {
  1419. printk("HRM... pmz_suspend with NULL uap\n");
  1420. return 0;
  1421. }
  1422. if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
  1423. return 0;
  1424. pmz_debug("suspend, switching to state %d\n", pm_state.event);
  1425. state = pmz_uart_reg.state + uap->port.line;
  1426. mutex_lock(&pmz_irq_mutex);
  1427. mutex_lock(&state->port.mutex);
  1428. spin_lock_irqsave(&uap->port.lock, flags);
  1429. if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
  1430. /* Disable receiver and transmitter. */
  1431. uap->curregs[R3] &= ~RxENABLE;
  1432. uap->curregs[R5] &= ~TxENABLE;
  1433. /* Disable all interrupts and BRK assertion. */
  1434. uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
  1435. uap->curregs[R5] &= ~SND_BRK;
  1436. pmz_load_zsregs(uap, uap->curregs);
  1437. uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
  1438. mb();
  1439. }
  1440. spin_unlock_irqrestore(&uap->port.lock, flags);
  1441. if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
  1442. if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
  1443. pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
  1444. disable_irq(uap->port.irq);
  1445. }
  1446. if (ZS_IS_CONS(uap))
  1447. uap->port.cons->flags &= ~CON_ENABLED;
  1448. /* Shut the chip down */
  1449. pmz_set_scc_power(uap, 0);
  1450. mutex_unlock(&state->port.mutex);
  1451. mutex_unlock(&pmz_irq_mutex);
  1452. pmz_debug("suspend, switching complete\n");
  1453. mdev->ofdev.dev.power.power_state = pm_state;
  1454. return 0;
  1455. }
  1456. static int pmz_resume(struct macio_dev *mdev)
  1457. {
  1458. struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
  1459. struct uart_state *state;
  1460. unsigned long flags;
  1461. int pwr_delay = 0;
  1462. if (uap == NULL)
  1463. return 0;
  1464. if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
  1465. return 0;
  1466. pmz_debug("resume, switching to state 0\n");
  1467. state = pmz_uart_reg.state + uap->port.line;
  1468. mutex_lock(&pmz_irq_mutex);
  1469. mutex_lock(&state->port.mutex);
  1470. spin_lock_irqsave(&uap->port.lock, flags);
  1471. if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
  1472. spin_unlock_irqrestore(&uap->port.lock, flags);
  1473. goto bail;
  1474. }
  1475. pwr_delay = __pmz_startup(uap);
  1476. /* Take care of config that may have changed while asleep */
  1477. __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
  1478. if (ZS_IS_OPEN(uap)) {
  1479. /* Enable interrupts */
  1480. uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
  1481. if (!ZS_IS_EXTCLK(uap))
  1482. uap->curregs[R1] |= EXT_INT_ENAB;
  1483. write_zsreg(uap, R1, uap->curregs[R1]);
  1484. }
  1485. spin_unlock_irqrestore(&uap->port.lock, flags);
  1486. if (ZS_IS_CONS(uap))
  1487. uap->port.cons->flags |= CON_ENABLED;
  1488. /* Re-enable IRQ on the controller */
  1489. if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
  1490. pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
  1491. enable_irq(uap->port.irq);
  1492. }
  1493. bail:
  1494. mutex_unlock(&state->port.mutex);
  1495. mutex_unlock(&pmz_irq_mutex);
  1496. /* Right now, we deal with delay by blocking here, I'll be
  1497. * smarter later on
  1498. */
  1499. if (pwr_delay != 0) {
  1500. pmz_debug("pmz: delaying %d ms\n", pwr_delay);
  1501. msleep(pwr_delay);
  1502. }
  1503. pmz_debug("resume, switching complete\n");
  1504. mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
  1505. return 0;
  1506. }
  1507. /*
  1508. * Probe all ports in the system and build the ports array, we register
  1509. * with the serial layer at this point, the macio-type probing is only
  1510. * used later to "attach" to the sysfs tree so we get power management
  1511. * events
  1512. */
  1513. static int __init pmz_probe(void)
  1514. {
  1515. struct device_node *node_p, *node_a, *node_b, *np;
  1516. int count = 0;
  1517. int rc;
  1518. /*
  1519. * Find all escc chips in the system
  1520. */
  1521. node_p = of_find_node_by_name(NULL, "escc");
  1522. while (node_p) {
  1523. /*
  1524. * First get channel A/B node pointers
  1525. *
  1526. * TODO: Add routines with proper locking to do that...
  1527. */
  1528. node_a = node_b = NULL;
  1529. for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
  1530. if (strncmp(np->name, "ch-a", 4) == 0)
  1531. node_a = of_node_get(np);
  1532. else if (strncmp(np->name, "ch-b", 4) == 0)
  1533. node_b = of_node_get(np);
  1534. }
  1535. if (!node_a && !node_b) {
  1536. of_node_put(node_a);
  1537. of_node_put(node_b);
  1538. printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
  1539. (!node_a) ? 'a' : 'b', node_p->full_name);
  1540. goto next;
  1541. }
  1542. /*
  1543. * Fill basic fields in the port structures
  1544. */
  1545. pmz_ports[count].mate = &pmz_ports[count+1];
  1546. pmz_ports[count+1].mate = &pmz_ports[count];
  1547. pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
  1548. pmz_ports[count].node = node_a;
  1549. pmz_ports[count+1].node = node_b;
  1550. pmz_ports[count].port.line = count;
  1551. pmz_ports[count+1].port.line = count+1;
  1552. /*
  1553. * Setup the ports for real
  1554. */
  1555. rc = pmz_init_port(&pmz_ports[count]);
  1556. if (rc == 0 && node_b != NULL)
  1557. rc = pmz_init_port(&pmz_ports[count+1]);
  1558. if (rc != 0) {
  1559. of_node_put(node_a);
  1560. of_node_put(node_b);
  1561. memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
  1562. memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
  1563. goto next;
  1564. }
  1565. count += 2;
  1566. next:
  1567. node_p = of_find_node_by_name(node_p, "escc");
  1568. }
  1569. pmz_ports_count = count;
  1570. return 0;
  1571. }
  1572. #else
  1573. extern struct platform_device scc_a_pdev, scc_b_pdev;
  1574. static int __init pmz_init_port(struct uart_pmac_port *uap)
  1575. {
  1576. struct resource *r_ports;
  1577. int irq;
  1578. r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0);
  1579. irq = platform_get_irq(uap->node, 0);
  1580. if (!r_ports || !irq)
  1581. return -ENODEV;
  1582. uap->port.mapbase = r_ports->start;
  1583. uap->port.membase = (unsigned char __iomem *) r_ports->start;
  1584. uap->port.iotype = UPIO_MEM;
  1585. uap->port.irq = irq;
  1586. uap->port.uartclk = ZS_CLOCK;
  1587. uap->port.fifosize = 1;
  1588. uap->port.ops = &pmz_pops;
  1589. uap->port.type = PORT_PMAC_ZILOG;
  1590. uap->port.flags = 0;
  1591. uap->control_reg = uap->port.membase;
  1592. uap->data_reg = uap->control_reg + 4;
  1593. uap->port_type = 0;
  1594. pmz_convert_to_zs(uap, CS8, 0, 9600);
  1595. return 0;
  1596. }
  1597. static int __init pmz_probe(void)
  1598. {
  1599. int err;
  1600. pmz_ports_count = 0;
  1601. pmz_ports[0].mate = &pmz_ports[1];
  1602. pmz_ports[0].port.line = 0;
  1603. pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
  1604. pmz_ports[0].node = &scc_a_pdev;
  1605. err = pmz_init_port(&pmz_ports[0]);
  1606. if (err)
  1607. return err;
  1608. pmz_ports_count++;
  1609. pmz_ports[1].mate = &pmz_ports[0];
  1610. pmz_ports[1].port.line = 1;
  1611. pmz_ports[1].flags = 0;
  1612. pmz_ports[1].node = &scc_b_pdev;
  1613. err = pmz_init_port(&pmz_ports[1]);
  1614. if (err)
  1615. return err;
  1616. pmz_ports_count++;
  1617. return 0;
  1618. }
  1619. static void pmz_dispose_port(struct uart_pmac_port *uap)
  1620. {
  1621. memset(uap, 0, sizeof(struct uart_pmac_port));
  1622. }
  1623. static int __init pmz_attach(struct platform_device *pdev)
  1624. {
  1625. int i;
  1626. for (i = 0; i < pmz_ports_count; i++)
  1627. if (pmz_ports[i].node == pdev)
  1628. return 0;
  1629. return -ENODEV;
  1630. }
  1631. static int __exit pmz_detach(struct platform_device *pdev)
  1632. {
  1633. return 0;
  1634. }
  1635. #endif /* !CONFIG_PPC_PMAC */
  1636. #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
  1637. static void pmz_console_write(struct console *con, const char *s, unsigned int count);
  1638. static int __init pmz_console_setup(struct console *co, char *options);
  1639. static struct console pmz_console = {
  1640. .name = PMACZILOG_NAME,
  1641. .write = pmz_console_write,
  1642. .device = uart_console_device,
  1643. .setup = pmz_console_setup,
  1644. .flags = CON_PRINTBUFFER,
  1645. .index = -1,
  1646. .data = &pmz_uart_reg,
  1647. };
  1648. #define PMACZILOG_CONSOLE &pmz_console
  1649. #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
  1650. #define PMACZILOG_CONSOLE (NULL)
  1651. #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
  1652. /*
  1653. * Register the driver, console driver and ports with the serial
  1654. * core
  1655. */
  1656. static int __init pmz_register(void)
  1657. {
  1658. int i, rc;
  1659. pmz_uart_reg.nr = pmz_ports_count;
  1660. pmz_uart_reg.cons = PMACZILOG_CONSOLE;
  1661. /*
  1662. * Register this driver with the serial core
  1663. */
  1664. rc = uart_register_driver(&pmz_uart_reg);
  1665. if (rc)
  1666. return rc;
  1667. /*
  1668. * Register each port with the serial core
  1669. */
  1670. for (i = 0; i < pmz_ports_count; i++) {
  1671. struct uart_pmac_port *uport = &pmz_ports[i];
  1672. /* NULL node may happen on wallstreet */
  1673. if (uport->node != NULL)
  1674. rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
  1675. if (rc)
  1676. goto err_out;
  1677. }
  1678. return 0;
  1679. err_out:
  1680. while (i-- > 0) {
  1681. struct uart_pmac_port *uport = &pmz_ports[i];
  1682. uart_remove_one_port(&pmz_uart_reg, &uport->port);
  1683. }
  1684. uart_unregister_driver(&pmz_uart_reg);
  1685. return rc;
  1686. }
  1687. #ifdef CONFIG_PPC_PMAC
  1688. static struct of_device_id pmz_match[] =
  1689. {
  1690. {
  1691. .name = "ch-a",
  1692. },
  1693. {
  1694. .name = "ch-b",
  1695. },
  1696. {},
  1697. };
  1698. MODULE_DEVICE_TABLE (of, pmz_match);
  1699. static struct macio_driver pmz_driver = {
  1700. .driver = {
  1701. .name = "pmac_zilog",
  1702. .owner = THIS_MODULE,
  1703. .of_match_table = pmz_match,
  1704. },
  1705. .probe = pmz_attach,
  1706. .remove = pmz_detach,
  1707. .suspend = pmz_suspend,
  1708. .resume = pmz_resume,
  1709. };
  1710. #else
  1711. static struct platform_driver pmz_driver = {
  1712. .remove = __exit_p(pmz_detach),
  1713. .driver = {
  1714. .name = "scc",
  1715. .owner = THIS_MODULE,
  1716. },
  1717. };
  1718. #endif /* !CONFIG_PPC_PMAC */
  1719. static int __init init_pmz(void)
  1720. {
  1721. int rc, i;
  1722. printk(KERN_INFO "%s\n", version);
  1723. /*
  1724. * First, we need to do a direct OF-based probe pass. We
  1725. * do that because we want serial console up before the
  1726. * macio stuffs calls us back, and since that makes it
  1727. * easier to pass the proper number of channels to
  1728. * uart_register_driver()
  1729. */
  1730. if (pmz_ports_count == 0)
  1731. pmz_probe();
  1732. /*
  1733. * Bail early if no port found
  1734. */
  1735. if (pmz_ports_count == 0)
  1736. return -ENODEV;
  1737. /*
  1738. * Now we register with the serial layer
  1739. */
  1740. rc = pmz_register();
  1741. if (rc) {
  1742. printk(KERN_ERR
  1743. "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
  1744. "pmac_zilog: Did another serial driver already claim the minors?\n");
  1745. /* effectively "pmz_unprobe()" */
  1746. for (i=0; i < pmz_ports_count; i++)
  1747. pmz_dispose_port(&pmz_ports[i]);
  1748. return rc;
  1749. }
  1750. /*
  1751. * Then we register the macio driver itself
  1752. */
  1753. #ifdef CONFIG_PPC_PMAC
  1754. return macio_register_driver(&pmz_driver);
  1755. #else
  1756. return platform_driver_probe(&pmz_driver, pmz_attach);
  1757. #endif
  1758. }
  1759. static void __exit exit_pmz(void)
  1760. {
  1761. int i;
  1762. #ifdef CONFIG_PPC_PMAC
  1763. /* Get rid of macio-driver (detach from macio) */
  1764. macio_unregister_driver(&pmz_driver);
  1765. #else
  1766. platform_driver_unregister(&pmz_driver);
  1767. #endif
  1768. for (i = 0; i < pmz_ports_count; i++) {
  1769. struct uart_pmac_port *uport = &pmz_ports[i];
  1770. if (uport->node != NULL) {
  1771. uart_remove_one_port(&pmz_uart_reg, &uport->port);
  1772. pmz_dispose_port(uport);
  1773. }
  1774. }
  1775. /* Unregister UART driver */
  1776. uart_unregister_driver(&pmz_uart_reg);
  1777. }
  1778. #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
  1779. static void pmz_console_putchar(struct uart_port *port, int ch)
  1780. {
  1781. struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
  1782. /* Wait for the transmit buffer to empty. */
  1783. while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
  1784. udelay(5);
  1785. write_zsdata(uap, ch);
  1786. }
  1787. /*
  1788. * Print a string to the serial port trying not to disturb
  1789. * any possible real use of the port...
  1790. */
  1791. static void pmz_console_write(struct console *con, const char *s, unsigned int count)
  1792. {
  1793. struct uart_pmac_port *uap = &pmz_ports[con->index];
  1794. unsigned long flags;
  1795. if (ZS_IS_ASLEEP(uap))
  1796. return;
  1797. spin_lock_irqsave(&uap->port.lock, flags);
  1798. /* Turn of interrupts and enable the transmitter. */
  1799. write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
  1800. write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
  1801. uart_console_write(&uap->port, s, count, pmz_console_putchar);
  1802. /* Restore the values in the registers. */
  1803. write_zsreg(uap, R1, uap->curregs[1]);
  1804. /* Don't disable the transmitter. */
  1805. spin_unlock_irqrestore(&uap->port.lock, flags);
  1806. }
  1807. /*
  1808. * Setup the serial console
  1809. */
  1810. static int __init pmz_console_setup(struct console *co, char *options)
  1811. {
  1812. struct uart_pmac_port *uap;
  1813. struct uart_port *port;
  1814. int baud = 38400;
  1815. int bits = 8;
  1816. int parity = 'n';
  1817. int flow = 'n';
  1818. unsigned long pwr_delay;
  1819. /*
  1820. * XServe's default to 57600 bps
  1821. */
  1822. if (of_machine_is_compatible("RackMac1,1")
  1823. || of_machine_is_compatible("RackMac1,2")
  1824. || of_machine_is_compatible("MacRISC4"))
  1825. baud = 57600;
  1826. /*
  1827. * Check whether an invalid uart number has been specified, and
  1828. * if so, search for the first available port that does have
  1829. * console support.
  1830. */
  1831. if (co->index >= pmz_ports_count)
  1832. co->index = 0;
  1833. uap = &pmz_ports[co->index];
  1834. if (uap->node == NULL)
  1835. return -ENODEV;
  1836. port = &uap->port;
  1837. /*
  1838. * Mark port as beeing a console
  1839. */
  1840. uap->flags |= PMACZILOG_FLAG_IS_CONS;
  1841. /*
  1842. * Temporary fix for uart layer who didn't setup the spinlock yet
  1843. */
  1844. spin_lock_init(&port->lock);
  1845. /*
  1846. * Enable the hardware
  1847. */
  1848. pwr_delay = __pmz_startup(uap);
  1849. if (pwr_delay)
  1850. mdelay(pwr_delay);
  1851. if (options)
  1852. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1853. return uart_set_options(port, co, baud, parity, bits, flow);
  1854. }
  1855. static int __init pmz_console_init(void)
  1856. {
  1857. /* Probe ports */
  1858. pmz_probe();
  1859. /* TODO: Autoprobe console based on OF */
  1860. /* pmz_console.index = i; */
  1861. register_console(&pmz_console);
  1862. return 0;
  1863. }
  1864. console_initcall(pmz_console_init);
  1865. #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
  1866. module_init(init_pmz);
  1867. module_exit(exit_pmz);