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/drivers/net/wireless/rt2x00/rt2800.h

https://bitbucket.org/wisechild/galaxy-nexus
C++ Header | 2406 lines | 1052 code | 250 blank | 1104 comment | 0 complexity | 8a6b5b1e0640dea25189f1abf28fca75 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
  3. Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
  4. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  5. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  6. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  7. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  8. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  9. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  10. Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  11. <http://rt2x00.serialmonkey.com>
  12. This program is free software; you can redistribute it and/or modify
  13. it under the terms of the GNU General Public License as published by
  14. the Free Software Foundation; either version 2 of the License, or
  15. (at your option) any later version.
  16. This program is distributed in the hope that it will be useful,
  17. but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. GNU General Public License for more details.
  20. You should have received a copy of the GNU General Public License
  21. along with this program; if not, write to the
  22. Free Software Foundation, Inc.,
  23. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  24. */
  25. /*
  26. Module: rt2800
  27. Abstract: Data structures and registers for the rt2800 modules.
  28. Supported chipsets: RT2800E, RT2800ED & RT2800U.
  29. */
  30. #ifndef RT2800_H
  31. #define RT2800_H
  32. /*
  33. * RF chip defines.
  34. *
  35. * RF2820 2.4G 2T3R
  36. * RF2850 2.4G/5G 2T3R
  37. * RF2720 2.4G 1T2R
  38. * RF2750 2.4G/5G 1T2R
  39. * RF3020 2.4G 1T1R
  40. * RF2020 2.4G B/G
  41. * RF3021 2.4G 1T2R
  42. * RF3022 2.4G 2T2R
  43. * RF3052 2.4G/5G 2T2R
  44. * RF2853 2.4G/5G 3T3R
  45. * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
  46. * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
  47. * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
  48. * RF5370 2.4G 1T1R
  49. * RF5390 2.4G 1T1R
  50. */
  51. #define RF2820 0x0001
  52. #define RF2850 0x0002
  53. #define RF2720 0x0003
  54. #define RF2750 0x0004
  55. #define RF3020 0x0005
  56. #define RF2020 0x0006
  57. #define RF3021 0x0007
  58. #define RF3022 0x0008
  59. #define RF3052 0x0009
  60. #define RF2853 0x000a
  61. #define RF3320 0x000b
  62. #define RF3322 0x000c
  63. #define RF3853 0x000d
  64. #define RF5370 0x5370
  65. #define RF5390 0x5390
  66. /*
  67. * Chipset revisions.
  68. */
  69. #define REV_RT2860C 0x0100
  70. #define REV_RT2860D 0x0101
  71. #define REV_RT2872E 0x0200
  72. #define REV_RT3070E 0x0200
  73. #define REV_RT3070F 0x0201
  74. #define REV_RT3071E 0x0211
  75. #define REV_RT3090E 0x0211
  76. #define REV_RT3390E 0x0211
  77. #define REV_RT5390F 0x0502
  78. /*
  79. * Signal information.
  80. * Default offset is required for RSSI <-> dBm conversion.
  81. */
  82. #define DEFAULT_RSSI_OFFSET 120
  83. /*
  84. * Register layout information.
  85. */
  86. #define CSR_REG_BASE 0x1000
  87. #define CSR_REG_SIZE 0x0800
  88. #define EEPROM_BASE 0x0000
  89. #define EEPROM_SIZE 0x0110
  90. #define BBP_BASE 0x0000
  91. #define BBP_SIZE 0x0080
  92. #define RF_BASE 0x0004
  93. #define RF_SIZE 0x0010
  94. /*
  95. * Number of TX queues.
  96. */
  97. #define NUM_TX_QUEUES 4
  98. /*
  99. * Registers.
  100. */
  101. /*
  102. * E2PROM_CSR: PCI EEPROM control register.
  103. * RELOAD: Write 1 to reload eeprom content.
  104. * TYPE: 0: 93c46, 1:93c66.
  105. * LOAD_STATUS: 1:loading, 0:done.
  106. */
  107. #define E2PROM_CSR 0x0004
  108. #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
  109. #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
  110. #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
  111. #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
  112. #define E2PROM_CSR_TYPE FIELD32(0x00000030)
  113. #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
  114. #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
  115. /*
  116. * AUX_CTRL: Aux/PCI-E related configuration
  117. */
  118. #define AUX_CTRL 0x10c
  119. #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
  120. #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
  121. /*
  122. * OPT_14: Unknown register used by rt3xxx devices.
  123. */
  124. #define OPT_14_CSR 0x0114
  125. #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
  126. /*
  127. * INT_SOURCE_CSR: Interrupt source register.
  128. * Write one to clear corresponding bit.
  129. * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
  130. */
  131. #define INT_SOURCE_CSR 0x0200
  132. #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
  133. #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
  134. #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
  135. #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
  136. #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
  137. #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
  138. #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
  139. #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
  140. #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
  141. #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
  142. #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
  143. #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
  144. #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
  145. #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
  146. #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
  147. #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
  148. #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
  149. #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
  150. /*
  151. * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
  152. */
  153. #define INT_MASK_CSR 0x0204
  154. #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
  155. #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
  156. #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
  157. #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
  158. #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
  159. #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
  160. #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
  161. #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
  162. #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
  163. #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
  164. #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
  165. #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
  166. #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
  167. #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
  168. #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
  169. #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
  170. #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
  171. #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
  172. /*
  173. * WPDMA_GLO_CFG
  174. */
  175. #define WPDMA_GLO_CFG 0x0208
  176. #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
  177. #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
  178. #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
  179. #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
  180. #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
  181. #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
  182. #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
  183. #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
  184. #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
  185. /*
  186. * WPDMA_RST_IDX
  187. */
  188. #define WPDMA_RST_IDX 0x020c
  189. #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
  190. #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
  191. #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
  192. #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
  193. #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
  194. #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
  195. #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
  196. /*
  197. * DELAY_INT_CFG
  198. */
  199. #define DELAY_INT_CFG 0x0210
  200. #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
  201. #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
  202. #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
  203. #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
  204. #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
  205. #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
  206. /*
  207. * WMM_AIFSN_CFG: Aifsn for each EDCA AC
  208. * AIFSN0: AC_VO
  209. * AIFSN1: AC_VI
  210. * AIFSN2: AC_BE
  211. * AIFSN3: AC_BK
  212. */
  213. #define WMM_AIFSN_CFG 0x0214
  214. #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
  215. #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
  216. #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
  217. #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
  218. /*
  219. * WMM_CWMIN_CSR: CWmin for each EDCA AC
  220. * CWMIN0: AC_VO
  221. * CWMIN1: AC_VI
  222. * CWMIN2: AC_BE
  223. * CWMIN3: AC_BK
  224. */
  225. #define WMM_CWMIN_CFG 0x0218
  226. #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
  227. #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
  228. #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
  229. #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
  230. /*
  231. * WMM_CWMAX_CSR: CWmax for each EDCA AC
  232. * CWMAX0: AC_VO
  233. * CWMAX1: AC_VI
  234. * CWMAX2: AC_BE
  235. * CWMAX3: AC_BK
  236. */
  237. #define WMM_CWMAX_CFG 0x021c
  238. #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
  239. #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
  240. #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
  241. #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
  242. /*
  243. * AC_TXOP0: AC_VO/AC_VI TXOP register
  244. * AC0TXOP: AC_VO in unit of 32us
  245. * AC1TXOP: AC_VI in unit of 32us
  246. */
  247. #define WMM_TXOP0_CFG 0x0220
  248. #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
  249. #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
  250. /*
  251. * AC_TXOP1: AC_BE/AC_BK TXOP register
  252. * AC2TXOP: AC_BE in unit of 32us
  253. * AC3TXOP: AC_BK in unit of 32us
  254. */
  255. #define WMM_TXOP1_CFG 0x0224
  256. #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
  257. #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
  258. /*
  259. * GPIO_CTRL_CFG:
  260. * GPIOD: GPIO direction, 0: Output, 1: Input
  261. */
  262. #define GPIO_CTRL_CFG 0x0228
  263. #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
  264. #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
  265. #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
  266. #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
  267. #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
  268. #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
  269. #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
  270. #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
  271. #define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
  272. #define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
  273. #define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
  274. #define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
  275. #define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
  276. #define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
  277. #define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
  278. #define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
  279. /*
  280. * MCU_CMD_CFG
  281. */
  282. #define MCU_CMD_CFG 0x022c
  283. /*
  284. * AC_VO register offsets
  285. */
  286. #define TX_BASE_PTR0 0x0230
  287. #define TX_MAX_CNT0 0x0234
  288. #define TX_CTX_IDX0 0x0238
  289. #define TX_DTX_IDX0 0x023c
  290. /*
  291. * AC_VI register offsets
  292. */
  293. #define TX_BASE_PTR1 0x0240
  294. #define TX_MAX_CNT1 0x0244
  295. #define TX_CTX_IDX1 0x0248
  296. #define TX_DTX_IDX1 0x024c
  297. /*
  298. * AC_BE register offsets
  299. */
  300. #define TX_BASE_PTR2 0x0250
  301. #define TX_MAX_CNT2 0x0254
  302. #define TX_CTX_IDX2 0x0258
  303. #define TX_DTX_IDX2 0x025c
  304. /*
  305. * AC_BK register offsets
  306. */
  307. #define TX_BASE_PTR3 0x0260
  308. #define TX_MAX_CNT3 0x0264
  309. #define TX_CTX_IDX3 0x0268
  310. #define TX_DTX_IDX3 0x026c
  311. /*
  312. * HCCA register offsets
  313. */
  314. #define TX_BASE_PTR4 0x0270
  315. #define TX_MAX_CNT4 0x0274
  316. #define TX_CTX_IDX4 0x0278
  317. #define TX_DTX_IDX4 0x027c
  318. /*
  319. * MGMT register offsets
  320. */
  321. #define TX_BASE_PTR5 0x0280
  322. #define TX_MAX_CNT5 0x0284
  323. #define TX_CTX_IDX5 0x0288
  324. #define TX_DTX_IDX5 0x028c
  325. /*
  326. * RX register offsets
  327. */
  328. #define RX_BASE_PTR 0x0290
  329. #define RX_MAX_CNT 0x0294
  330. #define RX_CRX_IDX 0x0298
  331. #define RX_DRX_IDX 0x029c
  332. /*
  333. * USB_DMA_CFG
  334. * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
  335. * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
  336. * PHY_CLEAR: phy watch dog enable.
  337. * TX_CLEAR: Clear USB DMA TX path.
  338. * TXOP_HALT: Halt TXOP count down when TX buffer is full.
  339. * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
  340. * RX_BULK_EN: Enable USB DMA Rx.
  341. * TX_BULK_EN: Enable USB DMA Tx.
  342. * EP_OUT_VALID: OUT endpoint data valid.
  343. * RX_BUSY: USB DMA RX FSM busy.
  344. * TX_BUSY: USB DMA TX FSM busy.
  345. */
  346. #define USB_DMA_CFG 0x02a0
  347. #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
  348. #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
  349. #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
  350. #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
  351. #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
  352. #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
  353. #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
  354. #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
  355. #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
  356. #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
  357. #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
  358. /*
  359. * US_CYC_CNT
  360. * BT_MODE_EN: Bluetooth mode enable
  361. * CLOCK CYCLE: Clock cycle count in 1us.
  362. * PCI:0x21, PCIE:0x7d, USB:0x1e
  363. */
  364. #define US_CYC_CNT 0x02a4
  365. #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
  366. #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
  367. /*
  368. * PBF_SYS_CTRL
  369. * HOST_RAM_WRITE: enable Host program ram write selection
  370. */
  371. #define PBF_SYS_CTRL 0x0400
  372. #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
  373. #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
  374. /*
  375. * HOST-MCU shared memory
  376. */
  377. #define HOST_CMD_CSR 0x0404
  378. #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
  379. /*
  380. * PBF registers
  381. * Most are for debug. Driver doesn't touch PBF register.
  382. */
  383. #define PBF_CFG 0x0408
  384. #define PBF_MAX_PCNT 0x040c
  385. #define PBF_CTRL 0x0410
  386. #define PBF_INT_STA 0x0414
  387. #define PBF_INT_ENA 0x0418
  388. /*
  389. * BCN_OFFSET0:
  390. */
  391. #define BCN_OFFSET0 0x042c
  392. #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
  393. #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
  394. #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
  395. #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
  396. /*
  397. * BCN_OFFSET1:
  398. */
  399. #define BCN_OFFSET1 0x0430
  400. #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
  401. #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
  402. #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
  403. #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
  404. /*
  405. * TXRXQ_PCNT: PBF register
  406. * PCNT_TX0Q: Page count for TX hardware queue 0
  407. * PCNT_TX1Q: Page count for TX hardware queue 1
  408. * PCNT_TX2Q: Page count for TX hardware queue 2
  409. * PCNT_RX0Q: Page count for RX hardware queue
  410. */
  411. #define TXRXQ_PCNT 0x0438
  412. #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
  413. #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
  414. #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
  415. #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
  416. /*
  417. * PBF register
  418. * Debug. Driver doesn't touch PBF register.
  419. */
  420. #define PBF_DBG 0x043c
  421. /*
  422. * RF registers
  423. */
  424. #define RF_CSR_CFG 0x0500
  425. #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
  426. #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
  427. #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
  428. #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
  429. /*
  430. * EFUSE_CSR: RT30x0 EEPROM
  431. */
  432. #define EFUSE_CTRL 0x0580
  433. #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
  434. #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
  435. #define EFUSE_CTRL_KICK FIELD32(0x40000000)
  436. #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
  437. /*
  438. * EFUSE_DATA0
  439. */
  440. #define EFUSE_DATA0 0x0590
  441. /*
  442. * EFUSE_DATA1
  443. */
  444. #define EFUSE_DATA1 0x0594
  445. /*
  446. * EFUSE_DATA2
  447. */
  448. #define EFUSE_DATA2 0x0598
  449. /*
  450. * EFUSE_DATA3
  451. */
  452. #define EFUSE_DATA3 0x059c
  453. /*
  454. * LDO_CFG0
  455. */
  456. #define LDO_CFG0 0x05d4
  457. #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
  458. #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
  459. #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
  460. #define LDO_CFG0_BGSEL FIELD32(0x03000000)
  461. #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
  462. #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
  463. #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
  464. /*
  465. * GPIO_SWITCH
  466. */
  467. #define GPIO_SWITCH 0x05dc
  468. #define GPIO_SWITCH_0 FIELD32(0x00000001)
  469. #define GPIO_SWITCH_1 FIELD32(0x00000002)
  470. #define GPIO_SWITCH_2 FIELD32(0x00000004)
  471. #define GPIO_SWITCH_3 FIELD32(0x00000008)
  472. #define GPIO_SWITCH_4 FIELD32(0x00000010)
  473. #define GPIO_SWITCH_5 FIELD32(0x00000020)
  474. #define GPIO_SWITCH_6 FIELD32(0x00000040)
  475. #define GPIO_SWITCH_7 FIELD32(0x00000080)
  476. /*
  477. * MAC Control/Status Registers(CSR).
  478. * Some values are set in TU, whereas 1 TU == 1024 us.
  479. */
  480. /*
  481. * MAC_CSR0: ASIC revision number.
  482. * ASIC_REV: 0
  483. * ASIC_VER: 2860 or 2870
  484. */
  485. #define MAC_CSR0 0x1000
  486. #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
  487. #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
  488. /*
  489. * MAC_SYS_CTRL:
  490. */
  491. #define MAC_SYS_CTRL 0x1004
  492. #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
  493. #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
  494. #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
  495. #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
  496. #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
  497. #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
  498. #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
  499. #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
  500. /*
  501. * MAC_ADDR_DW0: STA MAC register 0
  502. */
  503. #define MAC_ADDR_DW0 0x1008
  504. #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
  505. #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
  506. #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
  507. #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
  508. /*
  509. * MAC_ADDR_DW1: STA MAC register 1
  510. * UNICAST_TO_ME_MASK:
  511. * Used to mask off bits from byte 5 of the MAC address
  512. * to determine the UNICAST_TO_ME bit for RX frames.
  513. * The full mask is complemented by BSS_ID_MASK:
  514. * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
  515. */
  516. #define MAC_ADDR_DW1 0x100c
  517. #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
  518. #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
  519. #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
  520. /*
  521. * MAC_BSSID_DW0: BSSID register 0
  522. */
  523. #define MAC_BSSID_DW0 0x1010
  524. #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
  525. #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
  526. #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
  527. #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
  528. /*
  529. * MAC_BSSID_DW1: BSSID register 1
  530. * BSS_ID_MASK:
  531. * 0: 1-BSSID mode (BSS index = 0)
  532. * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
  533. * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
  534. * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
  535. * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
  536. * BSSID. This will make sure that those bits will be ignored
  537. * when determining the MY_BSS of RX frames.
  538. */
  539. #define MAC_BSSID_DW1 0x1014
  540. #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
  541. #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
  542. #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
  543. #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
  544. /*
  545. * MAX_LEN_CFG: Maximum frame length register.
  546. * MAX_MPDU: rt2860b max 16k bytes
  547. * MAX_PSDU: Maximum PSDU length
  548. * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
  549. */
  550. #define MAX_LEN_CFG 0x1018
  551. #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
  552. #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
  553. #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
  554. #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
  555. /*
  556. * BBP_CSR_CFG: BBP serial control register
  557. * VALUE: Register value to program into BBP
  558. * REG_NUM: Selected BBP register
  559. * READ_CONTROL: 0 write BBP, 1 read BBP
  560. * BUSY: ASIC is busy executing BBP commands
  561. * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
  562. * BBP_RW_MODE: 0 serial, 1 parallel
  563. */
  564. #define BBP_CSR_CFG 0x101c
  565. #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
  566. #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
  567. #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
  568. #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
  569. #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
  570. #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
  571. /*
  572. * RF_CSR_CFG0: RF control register
  573. * REGID_AND_VALUE: Register value to program into RF
  574. * BITWIDTH: Selected RF register
  575. * STANDBYMODE: 0 high when standby, 1 low when standby
  576. * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
  577. * BUSY: ASIC is busy executing RF commands
  578. */
  579. #define RF_CSR_CFG0 0x1020
  580. #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
  581. #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
  582. #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
  583. #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
  584. #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
  585. #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
  586. /*
  587. * RF_CSR_CFG1: RF control register
  588. * REGID_AND_VALUE: Register value to program into RF
  589. * RFGAP: Gap between BB_CONTROL_RF and RF_LE
  590. * 0: 3 system clock cycle (37.5usec)
  591. * 1: 5 system clock cycle (62.5usec)
  592. */
  593. #define RF_CSR_CFG1 0x1024
  594. #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
  595. #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
  596. /*
  597. * RF_CSR_CFG2: RF control register
  598. * VALUE: Register value to program into RF
  599. */
  600. #define RF_CSR_CFG2 0x1028
  601. #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
  602. /*
  603. * LED_CFG: LED control
  604. * color LED's:
  605. * 0: off
  606. * 1: blinking upon TX2
  607. * 2: periodic slow blinking
  608. * 3: always on
  609. * LED polarity:
  610. * 0: active low
  611. * 1: active high
  612. */
  613. #define LED_CFG 0x102c
  614. #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
  615. #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
  616. #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
  617. #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
  618. #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
  619. #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
  620. #define LED_CFG_LED_POLAR FIELD32(0x40000000)
  621. /*
  622. * AMPDU_BA_WINSIZE: Force BlockAck window size
  623. * FORCE_WINSIZE_ENABLE:
  624. * 0: Disable forcing of BlockAck window size
  625. * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
  626. * window size values in the TXWI
  627. * FORCE_WINSIZE: BlockAck window size
  628. */
  629. #define AMPDU_BA_WINSIZE 0x1040
  630. #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
  631. #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
  632. /*
  633. * XIFS_TIME_CFG: MAC timing
  634. * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
  635. * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
  636. * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
  637. * when MAC doesn't reference BBP signal BBRXEND
  638. * EIFS: unit 1us
  639. * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
  640. *
  641. */
  642. #define XIFS_TIME_CFG 0x1100
  643. #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
  644. #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
  645. #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
  646. #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
  647. #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
  648. /*
  649. * BKOFF_SLOT_CFG:
  650. */
  651. #define BKOFF_SLOT_CFG 0x1104
  652. #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
  653. #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
  654. /*
  655. * NAV_TIME_CFG:
  656. */
  657. #define NAV_TIME_CFG 0x1108
  658. #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
  659. #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
  660. #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
  661. #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
  662. /*
  663. * CH_TIME_CFG: count as channel busy
  664. * EIFS_BUSY: Count EIFS as channel busy
  665. * NAV_BUSY: Count NAS as channel busy
  666. * RX_BUSY: Count RX as channel busy
  667. * TX_BUSY: Count TX as channel busy
  668. * TMR_EN: Enable channel statistics timer
  669. */
  670. #define CH_TIME_CFG 0x110c
  671. #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
  672. #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
  673. #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
  674. #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
  675. #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
  676. /*
  677. * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
  678. */
  679. #define PBF_LIFE_TIMER 0x1110
  680. /*
  681. * BCN_TIME_CFG:
  682. * BEACON_INTERVAL: in unit of 1/16 TU
  683. * TSF_TICKING: Enable TSF auto counting
  684. * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
  685. * BEACON_GEN: Enable beacon generator
  686. */
  687. #define BCN_TIME_CFG 0x1114
  688. #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
  689. #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
  690. #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
  691. #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
  692. #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
  693. #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
  694. /*
  695. * TBTT_SYNC_CFG:
  696. * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
  697. * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
  698. */
  699. #define TBTT_SYNC_CFG 0x1118
  700. #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
  701. #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
  702. #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
  703. #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
  704. /*
  705. * TSF_TIMER_DW0: Local lsb TSF timer, read-only
  706. */
  707. #define TSF_TIMER_DW0 0x111c
  708. #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
  709. /*
  710. * TSF_TIMER_DW1: Local msb TSF timer, read-only
  711. */
  712. #define TSF_TIMER_DW1 0x1120
  713. #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
  714. /*
  715. * TBTT_TIMER: TImer remains till next TBTT, read-only
  716. */
  717. #define TBTT_TIMER 0x1124
  718. /*
  719. * INT_TIMER_CFG: timer configuration
  720. * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
  721. * GP_TIMER: period of general purpose timer in units of 1/16 TU
  722. */
  723. #define INT_TIMER_CFG 0x1128
  724. #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
  725. #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
  726. /*
  727. * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
  728. */
  729. #define INT_TIMER_EN 0x112c
  730. #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
  731. #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
  732. /*
  733. * CH_IDLE_STA: channel idle time (in us)
  734. */
  735. #define CH_IDLE_STA 0x1130
  736. /*
  737. * CH_BUSY_STA: channel busy time on primary channel (in us)
  738. */
  739. #define CH_BUSY_STA 0x1134
  740. /*
  741. * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
  742. */
  743. #define CH_BUSY_STA_SEC 0x1138
  744. /*
  745. * MAC_STATUS_CFG:
  746. * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
  747. * if 1 or higher one of the 2 registers is busy.
  748. */
  749. #define MAC_STATUS_CFG 0x1200
  750. #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
  751. /*
  752. * PWR_PIN_CFG:
  753. */
  754. #define PWR_PIN_CFG 0x1204
  755. /*
  756. * AUTOWAKEUP_CFG: Manual power control / status register
  757. * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
  758. * AUTOWAKE: 0:sleep, 1:awake
  759. */
  760. #define AUTOWAKEUP_CFG 0x1208
  761. #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
  762. #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
  763. #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
  764. /*
  765. * EDCA_AC0_CFG:
  766. */
  767. #define EDCA_AC0_CFG 0x1300
  768. #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
  769. #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
  770. #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
  771. #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
  772. /*
  773. * EDCA_AC1_CFG:
  774. */
  775. #define EDCA_AC1_CFG 0x1304
  776. #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
  777. #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
  778. #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
  779. #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
  780. /*
  781. * EDCA_AC2_CFG:
  782. */
  783. #define EDCA_AC2_CFG 0x1308
  784. #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
  785. #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
  786. #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
  787. #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
  788. /*
  789. * EDCA_AC3_CFG:
  790. */
  791. #define EDCA_AC3_CFG 0x130c
  792. #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
  793. #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
  794. #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
  795. #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
  796. /*
  797. * EDCA_TID_AC_MAP:
  798. */
  799. #define EDCA_TID_AC_MAP 0x1310
  800. /*
  801. * TX_PWR_CFG:
  802. */
  803. #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
  804. #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
  805. #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
  806. #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
  807. #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
  808. #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
  809. #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
  810. #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
  811. /*
  812. * TX_PWR_CFG_0:
  813. */
  814. #define TX_PWR_CFG_0 0x1314
  815. #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
  816. #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
  817. #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
  818. #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
  819. #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
  820. #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
  821. #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
  822. #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
  823. /*
  824. * TX_PWR_CFG_1:
  825. */
  826. #define TX_PWR_CFG_1 0x1318
  827. #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
  828. #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
  829. #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
  830. #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
  831. #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
  832. #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
  833. #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
  834. #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
  835. /*
  836. * TX_PWR_CFG_2:
  837. */
  838. #define TX_PWR_CFG_2 0x131c
  839. #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
  840. #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
  841. #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
  842. #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
  843. #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
  844. #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
  845. #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
  846. #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
  847. /*
  848. * TX_PWR_CFG_3:
  849. */
  850. #define TX_PWR_CFG_3 0x1320
  851. #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
  852. #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
  853. #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
  854. #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
  855. #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
  856. #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
  857. #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
  858. #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
  859. /*
  860. * TX_PWR_CFG_4:
  861. */
  862. #define TX_PWR_CFG_4 0x1324
  863. #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
  864. #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
  865. #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
  866. #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
  867. /*
  868. * TX_PIN_CFG:
  869. */
  870. #define TX_PIN_CFG 0x1328
  871. #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
  872. #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
  873. #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
  874. #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
  875. #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
  876. #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
  877. #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
  878. #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
  879. #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
  880. #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
  881. #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
  882. #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
  883. #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
  884. #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
  885. #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
  886. #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
  887. #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
  888. #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
  889. #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
  890. #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
  891. /*
  892. * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
  893. */
  894. #define TX_BAND_CFG 0x132c
  895. #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
  896. #define TX_BAND_CFG_A FIELD32(0x00000002)
  897. #define TX_BAND_CFG_BG FIELD32(0x00000004)
  898. /*
  899. * TX_SW_CFG0:
  900. */
  901. #define TX_SW_CFG0 0x1330
  902. /*
  903. * TX_SW_CFG1:
  904. */
  905. #define TX_SW_CFG1 0x1334
  906. /*
  907. * TX_SW_CFG2:
  908. */
  909. #define TX_SW_CFG2 0x1338
  910. /*
  911. * TXOP_THRES_CFG:
  912. */
  913. #define TXOP_THRES_CFG 0x133c
  914. /*
  915. * TXOP_CTRL_CFG:
  916. * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
  917. * AC_TRUN_EN: Enable/Disable truncation for AC change
  918. * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
  919. * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
  920. * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
  921. * RESERVED_TRUN_EN: Reserved
  922. * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
  923. * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
  924. * transmissions if extension CCA is clear).
  925. * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
  926. * EXT_CWMIN: CwMin for extension channel backoff
  927. * 0: Disabled
  928. *
  929. */
  930. #define TXOP_CTRL_CFG 0x1340
  931. #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
  932. #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
  933. #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
  934. #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
  935. #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
  936. #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
  937. #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
  938. #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
  939. #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
  940. #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
  941. /*
  942. * TX_RTS_CFG:
  943. * RTS_THRES: unit:byte
  944. * RTS_FBK_EN: enable rts rate fallback
  945. */
  946. #define TX_RTS_CFG 0x1344
  947. #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
  948. #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
  949. #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
  950. /*
  951. * TX_TIMEOUT_CFG:
  952. * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
  953. * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
  954. * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
  955. * it is recommended that:
  956. * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
  957. */
  958. #define TX_TIMEOUT_CFG 0x1348
  959. #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
  960. #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
  961. #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
  962. /*
  963. * TX_RTY_CFG:
  964. * SHORT_RTY_LIMIT: short retry limit
  965. * LONG_RTY_LIMIT: long retry limit
  966. * LONG_RTY_THRE: Long retry threshoold
  967. * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
  968. * 0:expired by retry limit, 1: expired by mpdu life timer
  969. * AGG_RTY_MODE: Aggregate MPDU retry mode
  970. * 0:expired by retry limit, 1: expired by mpdu life timer
  971. * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
  972. */
  973. #define TX_RTY_CFG 0x134c
  974. #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
  975. #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
  976. #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
  977. #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
  978. #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
  979. #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
  980. /*
  981. * TX_LINK_CFG:
  982. * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
  983. * MFB_ENABLE: TX apply remote MFB 1:enable
  984. * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
  985. * 0: not apply remote remote unsolicit (MFS=7)
  986. * TX_MRQ_EN: MCS request TX enable
  987. * TX_RDG_EN: RDG TX enable
  988. * TX_CF_ACK_EN: Piggyback CF-ACK enable
  989. * REMOTE_MFB: remote MCS feedback
  990. * REMOTE_MFS: remote MCS feedback sequence number
  991. */
  992. #define TX_LINK_CFG 0x1350
  993. #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
  994. #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
  995. #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
  996. #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
  997. #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
  998. #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
  999. #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
  1000. #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
  1001. /*
  1002. * HT_FBK_CFG0:
  1003. */
  1004. #define HT_FBK_CFG0 0x1354
  1005. #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
  1006. #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
  1007. #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
  1008. #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
  1009. #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
  1010. #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
  1011. #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
  1012. #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
  1013. /*
  1014. * HT_FBK_CFG1:
  1015. */
  1016. #define HT_FBK_CFG1 0x1358
  1017. #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
  1018. #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
  1019. #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
  1020. #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
  1021. #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
  1022. #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
  1023. #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
  1024. #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
  1025. /*
  1026. * LG_FBK_CFG0:
  1027. */
  1028. #define LG_FBK_CFG0 0x135c
  1029. #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
  1030. #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
  1031. #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
  1032. #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
  1033. #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
  1034. #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
  1035. #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
  1036. #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
  1037. /*
  1038. * LG_FBK_CFG1:
  1039. */
  1040. #define LG_FBK_CFG1 0x1360
  1041. #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
  1042. #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
  1043. #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
  1044. #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
  1045. /*
  1046. * CCK_PROT_CFG: CCK Protection
  1047. * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
  1048. * PROTECT_CTRL: Protection control frame type for CCK TX
  1049. * 0:none, 1:RTS/CTS, 2:CTS-to-self
  1050. * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
  1051. * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
  1052. * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
  1053. * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
  1054. * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
  1055. * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
  1056. * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
  1057. * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
  1058. * RTS_TH_EN: RTS threshold enable on CCK TX
  1059. */
  1060. #define CCK_PROT_CFG 0x1364
  1061. #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1062. #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1063. #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1064. #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1065. #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1066. #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1067. #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1068. #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1069. #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1070. #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1071. #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1072. /*
  1073. * OFDM_PROT_CFG: OFDM Protection
  1074. */
  1075. #define OFDM_PROT_CFG 0x1368
  1076. #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1077. #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1078. #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1079. #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1080. #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1081. #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1082. #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1083. #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1084. #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1085. #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1086. #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1087. /*
  1088. * MM20_PROT_CFG: MM20 Protection
  1089. */
  1090. #define MM20_PROT_CFG 0x136c
  1091. #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1092. #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1093. #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1094. #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1095. #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1096. #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1097. #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1098. #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1099. #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1100. #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1101. #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1102. /*
  1103. * MM40_PROT_CFG: MM40 Protection
  1104. */
  1105. #define MM40_PROT_CFG 0x1370
  1106. #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1107. #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1108. #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1109. #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1110. #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1111. #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1112. #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1113. #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1114. #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1115. #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1116. #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1117. /*
  1118. * GF20_PROT_CFG: GF20 Protection
  1119. */
  1120. #define GF20_PROT_CFG 0x1374
  1121. #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1122. #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1123. #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1124. #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1125. #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1126. #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1127. #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1128. #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1129. #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1130. #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1131. #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1132. /*
  1133. * GF40_PROT_CFG: GF40 Protection
  1134. */
  1135. #define GF40_PROT_CFG 0x1378
  1136. #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1137. #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1138. #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
  1139. #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
  1140. #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1141. #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1142. #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1143. #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1144. #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1145. #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1146. #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1147. /*
  1148. * EXP_CTS_TIME:
  1149. */
  1150. #define EXP_CTS_TIME 0x137c
  1151. /*
  1152. * EXP_ACK_TIME:
  1153. */
  1154. #define EXP_ACK_TIME 0x1380
  1155. /*
  1156. * RX_FILTER_CFG: RX configuration register.
  1157. */
  1158. #define RX_FILTER_CFG 0x1400
  1159. #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
  1160. #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
  1161. #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
  1162. #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
  1163. #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
  1164. #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
  1165. #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
  1166. #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
  1167. #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
  1168. #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
  1169. #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
  1170. #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
  1171. #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
  1172. #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
  1173. #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
  1174. #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
  1175. #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
  1176. /*
  1177. * AUTO_RSP_CFG:
  1178. * AUTORESPONDER: 0: disable, 1: enable
  1179. * BAC_ACK_POLICY: 0:long, 1:short preamble
  1180. * CTS_40_MMODE: Response CTS 40MHz duplicate mode
  1181. * CTS_40_MREF: Response CTS 40MHz duplicate mode
  1182. * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
  1183. * DUAL_CTS_EN: Power bit value in control frame
  1184. * ACK_CTS_PSM_BIT:Power bit value in control frame
  1185. */
  1186. #define AUTO_RSP_CFG 0x1404
  1187. #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
  1188. #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
  1189. #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
  1190. #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
  1191. #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
  1192. #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
  1193. #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
  1194. /*
  1195. * LEGACY_BASIC_RATE:
  1196. */
  1197. #define LEGACY_BASIC_RATE 0x1408
  1198. /*
  1199. * HT_BASIC_RATE:
  1200. */
  1201. #define HT_BASIC_RATE 0x140c
  1202. /*
  1203. * HT_CTRL_CFG:
  1204. */
  1205. #define HT_CTRL_CFG 0x1410
  1206. /*
  1207. * SIFS_COST_CFG:
  1208. */
  1209. #define SIFS_COST_CFG 0x1414
  1210. /*
  1211. * RX_PARSER_CFG:
  1212. * Set NAV for all received frames
  1213. */
  1214. #define RX_PARSER_CFG 0x1418
  1215. /*
  1216. * TX_SEC_CNT0:
  1217. */
  1218. #define TX_SEC_CNT0 0x1500
  1219. /*
  1220. * RX_SEC_CNT0:
  1221. */
  1222. #define RX_SEC_CNT0 0x1504
  1223. /*
  1224. * CCMP_FC_MUTE:
  1225. */
  1226. #define CCMP_FC_MUTE 0x1508
  1227. /*
  1228. * TXOP_HLDR_ADDR0:
  1229. */
  1230. #define TXOP_HLDR_ADDR0 0x1600
  1231. /*
  1232. * TXOP_HLDR_ADDR1:
  1233. */
  1234. #define TXOP_HLDR_ADDR1 0x1604
  1235. /*
  1236. * TXOP_HLDR_ET:
  1237. */
  1238. #define TXOP_HLDR_ET 0x1608
  1239. /*
  1240. * QOS_CFPOLL_RA_DW0:
  1241. */
  1242. #define QOS_CFPOLL_RA_DW0 0x160c
  1243. /*
  1244. * QOS_CFPOLL_RA_DW1:
  1245. */
  1246. #define QOS_CFPOLL_RA_DW1 0x1610
  1247. /*
  1248. * QOS_CFPOLL_QC:
  1249. */
  1250. #define QOS_CFPOLL_QC 0x1614
  1251. /*
  1252. * RX_STA_CNT0: RX PLCP error count & RX CRC error count
  1253. */
  1254. #define RX_STA_CNT0 0x1700
  1255. #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
  1256. #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
  1257. /*
  1258. * RX_STA_CNT1: RX False CCA count & RX LONG frame count
  1259. */
  1260. #define RX_STA_CNT1 0x1704
  1261. #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
  1262. #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
  1263. /*
  1264. * RX_STA_CNT2:
  1265. */
  1266. #define RX_STA_CNT2 0x1708
  1267. #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
  1268. #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
  1269. /*
  1270. * TX_STA_CNT0: TX Beacon count
  1271. */
  1272. #define TX_STA_CNT0 0x170c
  1273. #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
  1274. #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
  1275. /*
  1276. * TX_STA_CNT1: TX tx count
  1277. */
  1278. #define TX_STA_CNT1 0x1710
  1279. #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
  1280. #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
  1281. /*
  1282. * TX_STA_CNT2: TX tx count
  1283. */
  1284. #define TX_STA_CNT2 0x1714
  1285. #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
  1286. #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
  1287. /*
  1288. * TX_STA_FIFO: TX Result for specific PID status fifo register.
  1289. *
  1290. * This register is implemented as FIFO with 16 entries in the HW. Each
  1291. * register read fetches the next tx result. If the FIFO is full because
  1292. * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
  1293. * triggered, the hw seems to simply drop further tx results.
  1294. *
  1295. * VALID: 1: this tx result is valid
  1296. * 0: no valid tx result -> driver should stop reading
  1297. * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
  1298. * to match a frame with its tx result (even though the PID is
  1299. * only 4 bits wide).
  1300. * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
  1301. * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
  1302. * This identification number is calculated by ((idx % 3) + 1).
  1303. * TX_SUCCESS: Indicates tx success (1) or failure (0)
  1304. * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
  1305. * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
  1306. * WCID: The wireless client ID.
  1307. * MCS: The tx rate used during the last transmission of this frame, be it
  1308. * successful or not.
  1309. * PHYMODE: The phymode used for the transmission.
  1310. */
  1311. #define TX_STA_FIFO 0x1718
  1312. #define TX_STA_FIFO_VALID FIELD32(0x00000001)
  1313. #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
  1314. #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
  1315. #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
  1316. #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
  1317. #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
  1318. #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
  1319. #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
  1320. #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
  1321. #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
  1322. #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
  1323. /*
  1324. * TX_AGG_CNT: Debug counter
  1325. */
  1326. #define TX_AGG_CNT 0x171c
  1327. #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
  1328. #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
  1329. /*
  1330. * TX_AGG_CNT0:
  1331. */
  1332. #define TX_AGG_CNT0 0x1720
  1333. #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
  1334. #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
  1335. /*
  1336. * TX_AGG_CNT1:
  1337. */
  1338. #define TX_AGG_CNT1 0x1724
  1339. #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
  1340. #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
  1341. /*
  1342. * TX_AGG_CNT2:
  1343. */
  1344. #define TX_AGG_CNT2 0x1728
  1345. #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
  1346. #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
  1347. /*
  1348. * TX_AGG_CNT3:
  1349. */
  1350. #define TX_AGG_CNT3 0x172c
  1351. #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
  1352. #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
  1353. /*
  1354. * TX_AGG_CNT4:
  1355. */
  1356. #define TX_AGG_CNT4 0x1730
  1357. #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
  1358. #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
  1359. /*
  1360. * TX_AGG_CNT5:
  1361. */
  1362. #define TX_AGG_CNT5 0x1734
  1363. #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
  1364. #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
  1365. /*
  1366. * TX_AGG_CNT6:
  1367. */
  1368. #define TX_AGG_CNT6 0x1738
  1369. #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
  1370. #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
  1371. /*
  1372. * TX_AGG_CNT7:
  1373. */
  1374. #define TX_AGG_CNT7 0x173c
  1375. #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
  1376. #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
  1377. /*
  1378. * MPDU_DENSITY_CNT:
  1379. * TX_ZERO_DEL: TX zero length delimiter count
  1380. * RX_ZERO_DEL: RX zero length delimiter count
  1381. */
  1382. #define MPDU_DENSITY_CNT 0x1740
  1383. #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
  1384. #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
  1385. /*
  1386. * Security key table memory.
  1387. *
  1388. * The pairwise key table shares some memory with the beacon frame
  1389. * buffers 6 and 7. That basically means that when beacon 6 & 7
  1390. * are used we should only use the reduced pairwise key table which
  1391. * has a maximum of 222 entries.
  1392. *
  1393. * ---------------------------------------------
  1394. * |0x4000 | Pairwise Key | Reduced Pairwise |
  1395. * | | Table | Key Table |
  1396. * | | Size: 256 * 32 | Size: 222 * 32 |
  1397. * |0x5BC0 | |-------------------
  1398. * | | | Beacon 6 |
  1399. * |0x5DC0 | |-------------------
  1400. * | | | Beacon 7 |
  1401. * |0x5FC0 | |-------------------
  1402. * |0x5FFF | |
  1403. * --------------------------
  1404. *
  1405. * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
  1406. * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
  1407. * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
  1408. * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
  1409. * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
  1410. * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
  1411. */
  1412. #define MAC_WCID_BASE 0x1800
  1413. #define PAIRWISE_KEY_TABLE_BASE 0x4000
  1414. #define MAC_IVEIV_TABLE_BASE 0x6000
  1415. #define MAC_WCID_ATTRIBUTE_BASE 0x6800
  1416. #define SHARED_KEY_TABLE_BASE 0x6c00
  1417. #define SHARED_KEY_MODE_BASE 0x7000
  1418. #define MAC_WCID_ENTRY(__idx) \
  1419. (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
  1420. #define PAIRWISE_KEY_ENTRY(__idx) \
  1421. (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
  1422. #define MAC_IVEIV_ENTRY(__idx) \
  1423. (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
  1424. #define MAC_WCID_ATTR_ENTRY(__idx) \
  1425. (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
  1426. #define SHARED_KEY_ENTRY(__idx) \
  1427. (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
  1428. #define SHARED_KEY_MODE_ENTRY(__idx) \
  1429. (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
  1430. struct mac_wcid_entry {
  1431. u8 mac[6];
  1432. u8 reserved[2];
  1433. } __packed;
  1434. struct hw_key_entry {
  1435. u8 key[16];
  1436. u8 tx_mic[8];
  1437. u8 rx_mic[8];
  1438. } __packed;
  1439. struct mac_iveiv_entry {
  1440. u8 iv[8];
  1441. } __packed;
  1442. /*
  1443. * MAC_WCID_ATTRIBUTE:
  1444. */
  1445. #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
  1446. #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
  1447. #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
  1448. #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
  1449. #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
  1450. #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
  1451. #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
  1452. #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
  1453. /*
  1454. * SHARED_KEY_MODE:
  1455. */
  1456. #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
  1457. #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
  1458. #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
  1459. #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
  1460. #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
  1461. #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
  1462. #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
  1463. #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
  1464. /*
  1465. * HOST-MCU communication
  1466. */
  1467. /*
  1468. * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
  1469. */
  1470. #define H2M_MAILBOX_CSR 0x7010
  1471. #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
  1472. #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
  1473. #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
  1474. #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
  1475. /*
  1476. * H2M_MAILBOX_CID:
  1477. */
  1478. #define H2M_MAILBOX_CID 0x7014
  1479. #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
  1480. #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
  1481. #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
  1482. #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
  1483. /*
  1484. * H2M_MAILBOX_STATUS:
  1485. */
  1486. #define H2M_MAILBOX_STATUS 0x701c
  1487. /*
  1488. * H2M_INT_SRC:
  1489. */
  1490. #define H2M_INT_SRC 0x7024
  1491. /*
  1492. * H2M_BBP_AGENT:
  1493. */
  1494. #define H2M_BBP_AGENT 0x7028
  1495. /*
  1496. * MCU_LEDCS: LED control for MCU Mailbox.
  1497. */
  1498. #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
  1499. #define MCU_LEDCS_POLARITY FIELD8(0x01)
  1500. /*
  1501. * HW_CS_CTS_BASE:
  1502. * Carrier-sense CTS frame base address.
  1503. * It's where mac stores carrier-sense frame for carrier-sense function.
  1504. */
  1505. #define HW_CS_CTS_BASE 0x7700
  1506. /*
  1507. * HW_DFS_CTS_BASE:
  1508. * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
  1509. */
  1510. #define HW_DFS_CTS_BASE 0x7780
  1511. /*
  1512. * TXRX control registers - base address 0x3000
  1513. */
  1514. /*
  1515. * TXRX_CSR1:
  1516. * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
  1517. */
  1518. #define TXRX_CSR1 0x77d0
  1519. /*
  1520. * HW_DEBUG_SETTING_BASE:
  1521. * since NULL frame won't be that long (256 byte)
  1522. * We steal 16 tail bytes to save debugging settings
  1523. */
  1524. #define HW_DEBUG_SETTING_BASE 0x77f0
  1525. #define HW_DEBUG_SETTING_BASE2 0x7770
  1526. /*
  1527. * HW_BEACON_BASE
  1528. * In order to support maximum 8 MBSS and its maximum length
  1529. * is 512 bytes for each beacon
  1530. * Three section discontinue memory segments will be used.
  1531. * 1. The original region for BCN 0~3
  1532. * 2. Extract memory from FCE table for BCN 4~5
  1533. * 3. Extract memory from Pair-wise key table for BCN 6~7
  1534. * It occupied those memory of wcid 238~253 for BCN 6
  1535. * and wcid 222~237 for BCN 7 (see Security key table memory
  1536. * for more info).
  1537. *
  1538. * IMPORTANT NOTE: Not sure why legacy driver does this,
  1539. * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
  1540. */
  1541. #define HW_BEACON_BASE0 0x7800
  1542. #define HW_BEACON_BASE1 0x7a00
  1543. #define HW_BEACON_BASE2 0x7c00
  1544. #define HW_BEACON_BASE3 0x7e00
  1545. #define HW_BEACON_BASE4 0x7200
  1546. #define HW_BEACON_BASE5 0x7400
  1547. #define HW_BEACON_BASE6 0x5dc0
  1548. #define HW_BEACON_BASE7 0x5bc0
  1549. #define HW_BEACON_OFFSET(__index) \
  1550. (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
  1551. (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
  1552. (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
  1553. /*
  1554. * BBP registers.
  1555. * The wordsize of the BBP is 8 bits.
  1556. */
  1557. /*
  1558. * BBP 1: TX Antenna & Power Control
  1559. * POWER_CTRL:
  1560. * 0 - normal,
  1561. * 1 - drop tx power by 6dBm,
  1562. * 2 - drop tx power by 12dBm,
  1563. * 3 - increase tx power by 6dBm
  1564. */
  1565. #define BBP1_TX_POWER_CTRL FIELD8(0x07)
  1566. #define BBP1_TX_ANTENNA FIELD8(0x18)
  1567. /*
  1568. * BBP 3: RX Antenna
  1569. */
  1570. #define BBP3_RX_ANTENNA FIELD8(0x18)
  1571. #define BBP3_HT40_MINUS FIELD8(0x20)
  1572. /*
  1573. * BBP 4: Bandwidth
  1574. */
  1575. #define BBP4_TX_BF FIELD8(0x01)
  1576. #define BBP4_BANDWIDTH FIELD8(0x18)
  1577. #define BBP4_MAC_IF_CTRL FIELD8(0x40)
  1578. /*
  1579. * BBP 109
  1580. */
  1581. #define BBP109_TX0_POWER FIELD8(0x0f)
  1582. #define BBP109_TX1_POWER FIELD8(0xf0)
  1583. /*
  1584. * BBP 138: Unknown
  1585. */
  1586. #define BBP138_RX_ADC1 FIELD8(0x02)
  1587. #define BBP138_RX_ADC2 FIELD8(0x04)
  1588. #define BBP138_TX_DAC1 FIELD8(0x20)
  1589. #define BBP138_TX_DAC2 FIELD8(0x40)
  1590. /*
  1591. * BBP 152: Rx Ant
  1592. */
  1593. #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
  1594. /*
  1595. * RFCSR registers
  1596. * The wordsize of the RFCSR is 8 bits.
  1597. */
  1598. /*
  1599. * RFCSR 1:
  1600. */
  1601. #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
  1602. #define RFCSR1_PLL_PD FIELD8(0x02)
  1603. #define RFCSR1_RX0_PD FIELD8(0x04)
  1604. #define RFCSR1_TX0_PD FIELD8(0x08)
  1605. #define RFCSR1_RX1_PD FIELD8(0x10)
  1606. #define RFCSR1_TX1_PD FIELD8(0x20)
  1607. /*
  1608. * RFCSR 2:
  1609. */
  1610. #define RFCSR2_RESCAL_EN FIELD8(0x80)
  1611. /*
  1612. * RFCSR 6:
  1613. */
  1614. #define RFCSR6_R1 FIELD8(0x03)
  1615. #define RFCSR6_R2 FIELD8(0x40)
  1616. /*
  1617. * RFCSR 7:
  1618. */
  1619. #define RFCSR7_RF_TUNING FIELD8(0x01)
  1620. /*
  1621. * RFCSR 11:
  1622. */
  1623. #define RFCSR11_R FIELD8(0x03)
  1624. /*
  1625. * RFCSR 12:
  1626. */
  1627. #define RFCSR12_TX_POWER FIELD8(0x1f)
  1628. /*
  1629. * RFCSR 13:
  1630. */
  1631. #define RFCSR13_TX_POWER FIELD8(0x1f)
  1632. /*
  1633. * RFCSR 15:
  1634. */
  1635. #define RFCSR15_TX_LO2_EN FIELD8(0x08)
  1636. /*
  1637. * RFCSR 17:
  1638. */
  1639. #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
  1640. #define RFCSR17_TX_LO1_EN FIELD8(0x08)
  1641. #define RFCSR17_R FIELD8(0x20)
  1642. #define RFCSR17_CODE FIELD8(0x7f)
  1643. /*
  1644. * RFCSR 20:
  1645. */
  1646. #define RFCSR20_RX_LO1_EN FIELD8(0x08)
  1647. /*
  1648. * RFCSR 21:
  1649. */
  1650. #define RFCSR21_RX_LO2_EN FIELD8(0x08)
  1651. /*
  1652. * RFCSR 22:
  1653. */
  1654. #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
  1655. /*
  1656. * RFCSR 23:
  1657. */
  1658. #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
  1659. /*
  1660. * RFCSR 27:
  1661. */
  1662. #define RFCSR27_R1 FIELD8(0x03)
  1663. #define RFCSR27_R2 FIELD8(0x04)
  1664. #define RFCSR27_R3 FIELD8(0x30)
  1665. #define RFCSR27_R4 FIELD8(0x40)
  1666. /*
  1667. * RFCSR 30:
  1668. */
  1669. #define RFCSR30_TX_H20M FIELD8(0x02)
  1670. #define RFCSR30_RX_H20M FIELD8(0x04)
  1671. #define RFCSR30_RX_VCM FIELD8(0x18)
  1672. #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
  1673. /*
  1674. * RFCSR 31:
  1675. */
  1676. #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
  1677. #define RFCSR31_RX_H20M FIELD8(0x20)
  1678. /*
  1679. * RFCSR 38:
  1680. */
  1681. #define RFCSR38_RX_LO1_EN FIELD8(0x20)
  1682. /*
  1683. * RFCSR 39:
  1684. */
  1685. #define RFCSR39_RX_LO2_EN FIELD8(0x80)
  1686. /*
  1687. * RFCSR 49:
  1688. */
  1689. #define RFCSR49_TX FIELD8(0x3f)
  1690. /*
  1691. * RF registers
  1692. */
  1693. /*
  1694. * RF 2
  1695. */
  1696. #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
  1697. #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
  1698. #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
  1699. /*
  1700. * RF 3
  1701. */
  1702. #define RF3_TXPOWER_G FIELD32(0x00003e00)
  1703. #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
  1704. #define RF3_TXPOWER_A FIELD32(0x00003c00)
  1705. /*
  1706. * RF 4
  1707. */
  1708. #define RF4_TXPOWER_G FIELD32(0x000007c0)
  1709. #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
  1710. #define RF4_TXPOWER_A FIELD32(0x00000780)
  1711. #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
  1712. #define RF4_HT40 FIELD32(0x00200000)
  1713. /*
  1714. * EEPROM content.
  1715. * The wordsize of the EEPROM is 16 bits.
  1716. */
  1717. /*
  1718. * Chip ID
  1719. */
  1720. #define EEPROM_CHIP_ID 0x0000
  1721. /*
  1722. * EEPROM Version
  1723. */
  1724. #define EEPROM_VERSION 0x0001
  1725. #define EEPROM_VERSION_FAE FIELD16(0x00ff)
  1726. #define EEPROM_VERSION_VERSION FIELD16(0xff00)
  1727. /*
  1728. * HW MAC address.
  1729. */
  1730. #define EEPROM_MAC_ADDR_0 0x0002
  1731. #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
  1732. #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
  1733. #define EEPROM_MAC_ADDR_1 0x0003
  1734. #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
  1735. #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
  1736. #define EEPROM_MAC_ADDR_2 0x0004
  1737. #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
  1738. #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
  1739. /*
  1740. * EEPROM NIC Configuration 0
  1741. * RXPATH: 1: 1R, 2: 2R, 3: 3R
  1742. * TXPATH: 1: 1T, 2: 2T, 3: 3T
  1743. * RF_TYPE: RFIC type
  1744. */
  1745. #define EEPROM_NIC_CONF0 0x001a
  1746. #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
  1747. #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
  1748. #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
  1749. /*
  1750. * EEPROM NIC Configuration 1
  1751. * HW_RADIO: 0: disable, 1: enable
  1752. * EXTERNAL_TX_ALC: 0: disable, 1: enable
  1753. * EXTERNAL_LNA_2G: 0: disable, 1: enable
  1754. * EXTERNAL_LNA_5G: 0: disable, 1: enable
  1755. * CARDBUS_ACCEL: 0: enable, 1: disable
  1756. * BW40M_SB_2G: 0: disable, 1: enable
  1757. * BW40M_SB_5G: 0: disable, 1: enable
  1758. * WPS_PBC: 0: disable, 1: enable
  1759. * BW40M_2G: 0: enable, 1: disable
  1760. * BW40M_5G: 0: enable, 1: disable
  1761. * BROADBAND_EXT_LNA: 0: disable, 1: enable
  1762. * ANT_DIVERSITY: 00: Disable, 01: Diversity,
  1763. * 10: Main antenna, 11: Aux antenna
  1764. * INTERNAL_TX_ALC: 0: disable, 1: enable
  1765. * BT_COEXIST: 0: disable, 1: enable
  1766. * DAC_TEST: 0: disable, 1: enable
  1767. */
  1768. #define EEPROM_NIC_CONF1 0x001b
  1769. #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
  1770. #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
  1771. #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
  1772. #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
  1773. #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
  1774. #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
  1775. #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
  1776. #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
  1777. #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
  1778. #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
  1779. #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
  1780. #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
  1781. #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
  1782. #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
  1783. #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
  1784. /*
  1785. * EEPROM frequency
  1786. */
  1787. #define EEPROM_FREQ 0x001d
  1788. #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
  1789. #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
  1790. #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
  1791. /*
  1792. * EEPROM LED
  1793. * POLARITY_RDY_G: Polarity RDY_G setting.
  1794. * POLARITY_RDY_A: Polarity RDY_A setting.
  1795. * POLARITY_ACT: Polarity ACT setting.
  1796. * POLARITY_GPIO_0: Polarity GPIO0 setting.
  1797. * POLARITY_GPIO_1: Polarity GPIO1 setting.
  1798. * POLARITY_GPIO_2: Polarity GPIO2 setting.
  1799. * POLARITY_GPIO_3: Polarity GPIO3 setting.
  1800. * POLARITY_GPIO_4: Polarity GPIO4 setting.
  1801. * LED_MODE: Led mode.
  1802. */
  1803. #define EEPROM_LED_AG_CONF 0x001e
  1804. #define EEPROM_LED_ACT_CONF 0x001f
  1805. #define EEPROM_LED_POLARITY 0x0020
  1806. #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
  1807. #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
  1808. #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
  1809. #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
  1810. #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
  1811. #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
  1812. #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
  1813. #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
  1814. #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
  1815. /*
  1816. * EEPROM NIC Configuration 2
  1817. * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
  1818. * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
  1819. * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
  1820. */
  1821. #define EEPROM_NIC_CONF2 0x0021
  1822. #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
  1823. #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
  1824. #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
  1825. /*
  1826. * EEPROM LNA
  1827. */
  1828. #define EEPROM_LNA 0x0022
  1829. #define EEPROM_LNA_BG FIELD16(0x00ff)
  1830. #define EEPROM_LNA_A0 FIELD16(0xff00)
  1831. /*
  1832. * EEPROM RSSI BG offset
  1833. */
  1834. #define EEPROM_RSSI_BG 0x0023
  1835. #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
  1836. #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
  1837. /*
  1838. * EEPROM RSSI BG2 offset
  1839. */
  1840. #define EEPROM_RSSI_BG2 0x0024
  1841. #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
  1842. #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
  1843. /*
  1844. * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
  1845. */
  1846. #define EEPROM_TXMIXER_GAIN_BG 0x0024
  1847. #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
  1848. /*
  1849. * EEPROM RSSI A offset
  1850. */
  1851. #define EEPROM_RSSI_A 0x0025
  1852. #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
  1853. #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
  1854. /*
  1855. * EEPROM RSSI A2 offset
  1856. */
  1857. #define EEPROM_RSSI_A2 0x0026
  1858. #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
  1859. #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
  1860. /*
  1861. * EEPROM EIRP Maximum TX power values(unit: dbm)
  1862. */
  1863. #define EEPROM_EIRP_MAX_TX_POWER 0x0027
  1864. #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
  1865. #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
  1866. /*
  1867. * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
  1868. * This is delta in 40MHZ.
  1869. * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
  1870. * TYPE: 1: Plus the delta value, 0: minus the delta value
  1871. * ENABLE: enable tx power compensation for 40BW
  1872. */
  1873. #define EEPROM_TXPOWER_DELTA 0x0028
  1874. #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
  1875. #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
  1876. #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
  1877. #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
  1878. #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
  1879. #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
  1880. /*
  1881. * EEPROM TXPOWER 802.11BG
  1882. */
  1883. #define EEPROM_TXPOWER_BG1 0x0029
  1884. #define EEPROM_TXPOWER_BG2 0x0030
  1885. #define EEPROM_TXPOWER_BG_SIZE 7
  1886. #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
  1887. #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
  1888. /*
  1889. * EEPROM temperature compensation boundaries 802.11BG
  1890. * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
  1891. * reduced by (agc_step * -4)
  1892. * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
  1893. * reduced by (agc_step * -3)
  1894. */
  1895. #define EEPROM_TSSI_BOUND_BG1 0x0037
  1896. #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
  1897. #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
  1898. /*
  1899. * EEPROM temperature compensation boundaries 802.11BG
  1900. * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
  1901. * reduced by (agc_step * -2)
  1902. * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
  1903. * reduced by (agc_step * -1)
  1904. */
  1905. #define EEPROM_TSSI_BOUND_BG2 0x0038
  1906. #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
  1907. #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
  1908. /*
  1909. * EEPROM temperature compensation boundaries 802.11BG
  1910. * REF: Reference TSSI value, no tx power changes needed
  1911. * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
  1912. * increased by (agc_step * 1)
  1913. */
  1914. #define EEPROM_TSSI_BOUND_BG3 0x0039
  1915. #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
  1916. #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
  1917. /*
  1918. * EEPROM temperature compensation boundaries 802.11BG
  1919. * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
  1920. * increased by (agc_step * 2)
  1921. * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
  1922. * increased by (agc_step * 3)
  1923. */
  1924. #define EEPROM_TSSI_BOUND_BG4 0x003a
  1925. #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
  1926. #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
  1927. /*
  1928. * EEPROM temperature compensation boundaries 802.11BG
  1929. * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
  1930. * increased by (agc_step * 4)
  1931. * AGC_STEP: Temperature compensation step.
  1932. */
  1933. #define EEPROM_TSSI_BOUND_BG5 0x003b
  1934. #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
  1935. #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
  1936. /*
  1937. * EEPROM TXPOWER 802.11A
  1938. */
  1939. #define EEPROM_TXPOWER_A1 0x003c
  1940. #define EEPROM_TXPOWER_A2 0x0053
  1941. #define EEPROM_TXPOWER_A_SIZE 6
  1942. #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
  1943. #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
  1944. /*
  1945. * EEPROM temperature compensation boundaries 802.11A
  1946. * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
  1947. * reduced by (agc_step * -4)
  1948. * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
  1949. * reduced by (agc_step * -3)
  1950. */
  1951. #define EEPROM_TSSI_BOUND_A1 0x006a
  1952. #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
  1953. #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
  1954. /*
  1955. * EEPROM temperature compensation boundaries 802.11A
  1956. * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
  1957. * reduced by (agc_step * -2)
  1958. * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
  1959. * reduced by (agc_step * -1)
  1960. */
  1961. #define EEPROM_TSSI_BOUND_A2 0x006b
  1962. #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
  1963. #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
  1964. /*
  1965. * EEPROM temperature compensation boundaries 802.11A
  1966. * REF: Reference TSSI value, no tx power changes needed
  1967. * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
  1968. * increased by (agc_step * 1)
  1969. */
  1970. #define EEPROM_TSSI_BOUND_A3 0x006c
  1971. #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
  1972. #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
  1973. /*
  1974. * EEPROM temperature compensation boundaries 802.11A
  1975. * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
  1976. * increased by (agc_step * 2)
  1977. * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
  1978. * increased by (agc_step * 3)
  1979. */
  1980. #define EEPROM_TSSI_BOUND_A4 0x006d
  1981. #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
  1982. #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
  1983. /*
  1984. * EEPROM temperature compensation boundaries 802.11A
  1985. * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
  1986. * increased by (agc_step * 4)
  1987. * AGC_STEP: Temperature compensation step.
  1988. */
  1989. #define EEPROM_TSSI_BOUND_A5 0x006e
  1990. #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
  1991. #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
  1992. /*
  1993. * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
  1994. */
  1995. #define EEPROM_TXPOWER_BYRATE 0x006f
  1996. #define EEPROM_TXPOWER_BYRATE_SIZE 9
  1997. #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
  1998. #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
  1999. #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
  2000. #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
  2001. /*
  2002. * EEPROM BBP.
  2003. */
  2004. #define EEPROM_BBP_START 0x0078
  2005. #define EEPROM_BBP_SIZE 16
  2006. #define EEPROM_BBP_VALUE FIELD16(0x00ff)
  2007. #define EEPROM_BBP_REG_ID FIELD16(0xff00)
  2008. /*
  2009. * MCU mailbox commands.
  2010. */
  2011. #define MCU_SLEEP 0x30
  2012. #define MCU_WAKEUP 0x31
  2013. #define MCU_RADIO_OFF 0x35
  2014. #define MCU_CURRENT 0x36
  2015. #define MCU_LED 0x50
  2016. #define MCU_LED_STRENGTH 0x51
  2017. #define MCU_LED_AG_CONF 0x52
  2018. #define MCU_LED_ACT_CONF 0x53
  2019. #define MCU_LED_LED_POLARITY 0x54
  2020. #define MCU_RADAR 0x60
  2021. #define MCU_BOOT_SIGNAL 0x72
  2022. #define MCU_ANT_SELECT 0X73
  2023. #define MCU_BBP_SIGNAL 0x80
  2024. #define MCU_POWER_SAVE 0x83
  2025. /*
  2026. * MCU mailbox tokens
  2027. */
  2028. #define TOKEN_WAKUP 3
  2029. /*
  2030. * DMA descriptor defines.
  2031. */
  2032. #define TXWI_DESC_SIZE (4 * sizeof(__le32))
  2033. #define RXWI_DESC_SIZE (4 * sizeof(__le32))
  2034. /*
  2035. * TX WI structure
  2036. */
  2037. /*
  2038. * Word0
  2039. * FRAG: 1 To inform TKIP engine this is a fragment.
  2040. * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
  2041. * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
  2042. * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
  2043. * duplicate the frame to both channels).
  2044. * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
  2045. * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
  2046. * aggregate consecutive frames with the same RA and QoS TID. If
  2047. * a frame A with the same RA and QoS TID but AMPDU=0 is queued
  2048. * directly after a frame B with AMPDU=1, frame A might still
  2049. * get aggregated into the AMPDU started by frame B. So, setting
  2050. * AMPDU to 0 does _not_ necessarily mean the frame is sent as
  2051. * MPDU, it can still end up in an AMPDU if the previous frame
  2052. * was tagged as AMPDU.
  2053. */
  2054. #define TXWI_W0_FRAG FIELD32(0x00000001)
  2055. #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
  2056. #define TXWI_W0_CF_ACK FIELD32(0x00000004)
  2057. #define TXWI_W0_TS FIELD32(0x00000008)
  2058. #define TXWI_W0_AMPDU FIELD32(0x00000010)
  2059. #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
  2060. #define TXWI_W0_TX_OP FIELD32(0x00000300)
  2061. #define TXWI_W0_MCS FIELD32(0x007f0000)
  2062. #define TXWI_W0_BW FIELD32(0x00800000)
  2063. #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
  2064. #define TXWI_W0_STBC FIELD32(0x06000000)
  2065. #define TXWI_W0_IFS FIELD32(0x08000000)
  2066. #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
  2067. /*
  2068. * Word1
  2069. * ACK: 0: No Ack needed, 1: Ack needed
  2070. * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
  2071. * BW_WIN_SIZE: BA windows size of the recipient
  2072. * WIRELESS_CLI_ID: Client ID for WCID table access
  2073. * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
  2074. * PACKETID: Will be latched into the TX_STA_FIFO register once the according
  2075. * frame was processed. If multiple frames are aggregated together
  2076. * (AMPDU==1) the reported tx status will always contain the packet
  2077. * id of the first frame. 0: Don't report tx status for this frame.
  2078. * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
  2079. * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
  2080. * This identification number is calculated by ((idx % 3) + 1).
  2081. * The (+1) is required to prevent PACKETID to become 0.
  2082. */
  2083. #define TXWI_W1_ACK FIELD32(0x00000001)
  2084. #define TXWI_W1_NSEQ FIELD32(0x00000002)
  2085. #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
  2086. #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
  2087. #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
  2088. #define TXWI_W1_PACKETID FIELD32(0xf0000000)
  2089. #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
  2090. #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
  2091. /*
  2092. * Word2
  2093. */
  2094. #define TXWI_W2_IV FIELD32(0xffffffff)
  2095. /*
  2096. * Word3
  2097. */
  2098. #define TXWI_W3_EIV FIELD32(0xffffffff)
  2099. /*
  2100. * RX WI structure
  2101. */
  2102. /*
  2103. * Word0
  2104. */
  2105. #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
  2106. #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
  2107. #define RXWI_W0_BSSID FIELD32(0x00001c00)
  2108. #define RXWI_W0_UDF FIELD32(0x0000e000)
  2109. #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
  2110. #define RXWI_W0_TID FIELD32(0xf0000000)
  2111. /*
  2112. * Word1
  2113. */
  2114. #define RXWI_W1_FRAG FIELD32(0x0000000f)
  2115. #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
  2116. #define RXWI_W1_MCS FIELD32(0x007f0000)
  2117. #define RXWI_W1_BW FIELD32(0x00800000)
  2118. #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
  2119. #define RXWI_W1_STBC FIELD32(0x06000000)
  2120. #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
  2121. /*
  2122. * Word2
  2123. */
  2124. #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
  2125. #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
  2126. #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
  2127. /*
  2128. * Word3
  2129. */
  2130. #define RXWI_W3_SNR0 FIELD32(0x000000ff)
  2131. #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
  2132. /*
  2133. * Macros for converting txpower from EEPROM to mac80211 value
  2134. * and from mac80211 value to register value.
  2135. */
  2136. #define MIN_G_TXPOWER 0
  2137. #define MIN_A_TXPOWER -7
  2138. #define MAX_G_TXPOWER 31
  2139. #define MAX_A_TXPOWER 15
  2140. #define DEFAULT_TXPOWER 5
  2141. #define TXPOWER_G_FROM_DEV(__txpower) \
  2142. ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
  2143. #define TXPOWER_G_TO_DEV(__txpower) \
  2144. clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
  2145. #define TXPOWER_A_FROM_DEV(__txpower) \
  2146. ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
  2147. #define TXPOWER_A_TO_DEV(__txpower) \
  2148. clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
  2149. /*
  2150. * Board's maximun TX power limitation
  2151. */
  2152. #define EIRP_MAX_TX_POWER_LIMIT 0x50
  2153. #endif /* RT2800_H */