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/drivers/ata/sata_mv.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 4423 lines | 2993 code | 573 blank | 857 comment | 390 complexity | 6277dbf56209256fcc7e8f48a3cf64b2 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * sata_mv.c - Marvell SATA support
  3. *
  4. * Copyright 2008-2009: Marvell Corporation, all rights reserved.
  5. * Copyright 2005: EMC Corporation, all rights reserved.
  6. * Copyright 2005 Red Hat, Inc. All rights reserved.
  7. *
  8. * Originally written by Brett Russ.
  9. * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
  10. *
  11. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; version 2 of the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. /*
  28. * sata_mv TODO list:
  29. *
  30. * --> Develop a low-power-consumption strategy, and implement it.
  31. *
  32. * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
  33. *
  34. * --> [Experiment, Marvell value added] Is it possible to use target
  35. * mode to cross-connect two Linux boxes with Marvell cards? If so,
  36. * creating LibATA target mode support would be very interesting.
  37. *
  38. * Target mode, for those without docs, is the ability to directly
  39. * connect two SATA ports.
  40. */
  41. /*
  42. * 80x1-B2 errata PCI#11:
  43. *
  44. * Users of the 6041/6081 Rev.B2 chips (current is C0)
  45. * should be careful to insert those cards only onto PCI-X bus #0,
  46. * and only in device slots 0..7, not higher. The chips may not
  47. * work correctly otherwise (note: this is a pretty rare condition).
  48. */
  49. #include <linux/kernel.h>
  50. #include <linux/module.h>
  51. #include <linux/pci.h>
  52. #include <linux/init.h>
  53. #include <linux/blkdev.h>
  54. #include <linux/delay.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/dmapool.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/device.h>
  59. #include <linux/clk.h>
  60. #include <linux/platform_device.h>
  61. #include <linux/ata_platform.h>
  62. #include <linux/mbus.h>
  63. #include <linux/bitops.h>
  64. #include <linux/gfp.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi_cmnd.h>
  67. #include <scsi/scsi_device.h>
  68. #include <linux/libata.h>
  69. #define DRV_NAME "sata_mv"
  70. #define DRV_VERSION "1.28"
  71. /*
  72. * module options
  73. */
  74. static int msi;
  75. #ifdef CONFIG_PCI
  76. module_param(msi, int, S_IRUGO);
  77. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  78. #endif
  79. static int irq_coalescing_io_count;
  80. module_param(irq_coalescing_io_count, int, S_IRUGO);
  81. MODULE_PARM_DESC(irq_coalescing_io_count,
  82. "IRQ coalescing I/O count threshold (0..255)");
  83. static int irq_coalescing_usecs;
  84. module_param(irq_coalescing_usecs, int, S_IRUGO);
  85. MODULE_PARM_DESC(irq_coalescing_usecs,
  86. "IRQ coalescing time threshold in usecs");
  87. enum {
  88. /* BAR's are enumerated in terms of pci_resource_start() terms */
  89. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  90. MV_IO_BAR = 2, /* offset 0x18: IO space */
  91. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  92. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  93. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  94. /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
  95. COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
  96. MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
  97. MAX_COAL_IO_COUNT = 255, /* completed I/O count */
  98. MV_PCI_REG_BASE = 0,
  99. /*
  100. * Per-chip ("all ports") interrupt coalescing feature.
  101. * This is only for GEN_II / GEN_IIE hardware.
  102. *
  103. * Coalescing defers the interrupt until either the IO_THRESHOLD
  104. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  105. */
  106. COAL_REG_BASE = 0x18000,
  107. IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
  108. ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
  109. IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
  110. IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
  111. /*
  112. * Registers for the (unused here) transaction coalescing feature:
  113. */
  114. TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
  115. TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
  116. SATAHC0_REG_BASE = 0x20000,
  117. FLASH_CTL = 0x1046c,
  118. GPIO_PORT_CTL = 0x104f0,
  119. RESET_CFG = 0x180d8,
  120. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  121. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  122. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  123. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  124. MV_MAX_Q_DEPTH = 32,
  125. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  126. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  127. * CRPB needs alignment on a 256B boundary. Size == 256B
  128. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  129. */
  130. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  131. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  132. MV_MAX_SG_CT = 256,
  133. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  134. /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
  135. MV_PORT_HC_SHIFT = 2,
  136. MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
  137. /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
  138. MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
  139. /* Host Flags */
  140. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  141. MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
  142. MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
  143. MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
  144. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
  145. MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
  146. CRQB_FLAG_READ = (1 << 0),
  147. CRQB_TAG_SHIFT = 1,
  148. CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
  149. CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
  150. CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
  151. CRQB_CMD_ADDR_SHIFT = 8,
  152. CRQB_CMD_CS = (0x2 << 11),
  153. CRQB_CMD_LAST = (1 << 15),
  154. CRPB_FLAG_STATUS_SHIFT = 8,
  155. CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
  156. CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
  157. EPRD_FLAG_END_OF_TBL = (1 << 31),
  158. /* PCI interface registers */
  159. MV_PCI_COMMAND = 0xc00,
  160. MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
  161. MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
  162. PCI_MAIN_CMD_STS = 0xd30,
  163. STOP_PCI_MASTER = (1 << 2),
  164. PCI_MASTER_EMPTY = (1 << 3),
  165. GLOB_SFT_RST = (1 << 4),
  166. MV_PCI_MODE = 0xd00,
  167. MV_PCI_MODE_MASK = 0x30,
  168. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  169. MV_PCI_DISC_TIMER = 0xd04,
  170. MV_PCI_MSI_TRIGGER = 0xc38,
  171. MV_PCI_SERR_MASK = 0xc28,
  172. MV_PCI_XBAR_TMOUT = 0x1d04,
  173. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  174. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  175. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  176. MV_PCI_ERR_COMMAND = 0x1d50,
  177. PCI_IRQ_CAUSE = 0x1d58,
  178. PCI_IRQ_MASK = 0x1d5c,
  179. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  180. PCIE_IRQ_CAUSE = 0x1900,
  181. PCIE_IRQ_MASK = 0x1910,
  182. PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
  183. /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
  184. PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
  185. PCI_HC_MAIN_IRQ_MASK = 0x1d64,
  186. SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
  187. SOC_HC_MAIN_IRQ_MASK = 0x20024,
  188. ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
  189. DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
  190. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  191. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  192. DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
  193. DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
  194. PCI_ERR = (1 << 18),
  195. TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
  196. TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
  197. PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
  198. PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
  199. ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
  200. GPIO_INT = (1 << 22),
  201. SELF_INT = (1 << 23),
  202. TWSI_INT = (1 << 24),
  203. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  204. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  205. HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
  206. /* SATAHC registers */
  207. HC_CFG = 0x00,
  208. HC_IRQ_CAUSE = 0x14,
  209. DMA_IRQ = (1 << 0), /* shift by port # */
  210. HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
  211. DEV_IRQ = (1 << 8), /* shift by port # */
  212. /*
  213. * Per-HC (Host-Controller) interrupt coalescing feature.
  214. * This is present on all chip generations.
  215. *
  216. * Coalescing defers the interrupt until either the IO_THRESHOLD
  217. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  218. */
  219. HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
  220. HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
  221. SOC_LED_CTRL = 0x2c,
  222. SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
  223. SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
  224. /* with dev activity LED */
  225. /* Shadow block registers */
  226. SHD_BLK = 0x100,
  227. SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
  228. /* SATA registers */
  229. SATA_STATUS = 0x300, /* ctrl, err regs follow status */
  230. SATA_ACTIVE = 0x350,
  231. FIS_IRQ_CAUSE = 0x364,
  232. FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
  233. LTMODE = 0x30c, /* requires read-after-write */
  234. LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
  235. PHY_MODE2 = 0x330,
  236. PHY_MODE3 = 0x310,
  237. PHY_MODE4 = 0x314, /* requires read-after-write */
  238. PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
  239. PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
  240. PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
  241. PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
  242. SATA_IFCTL = 0x344,
  243. SATA_TESTCTL = 0x348,
  244. SATA_IFSTAT = 0x34c,
  245. VENDOR_UNIQUE_FIS = 0x35c,
  246. FISCFG = 0x360,
  247. FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
  248. FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
  249. PHY_MODE9_GEN2 = 0x398,
  250. PHY_MODE9_GEN1 = 0x39c,
  251. PHYCFG_OFS = 0x3a0, /* only in 65n devices */
  252. MV5_PHY_MODE = 0x74,
  253. MV5_LTMODE = 0x30,
  254. MV5_PHY_CTL = 0x0C,
  255. SATA_IFCFG = 0x050,
  256. MV_M2_PREAMP_MASK = 0x7e0,
  257. /* Port registers */
  258. EDMA_CFG = 0,
  259. EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
  260. EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
  261. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  262. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  263. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  264. EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
  265. EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
  266. EDMA_ERR_IRQ_CAUSE = 0x8,
  267. EDMA_ERR_IRQ_MASK = 0xc,
  268. EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
  269. EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
  270. EDMA_ERR_DEV = (1 << 2), /* device error */
  271. EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
  272. EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
  273. EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
  274. EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
  275. EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
  276. EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
  277. EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
  278. EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
  279. EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
  280. EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
  281. EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
  282. EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
  283. EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
  284. EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
  285. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
  286. EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
  287. EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
  288. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
  289. EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
  290. EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
  291. EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
  292. EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
  293. EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
  294. EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
  295. EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
  296. EDMA_ERR_OVERRUN_5 = (1 << 5),
  297. EDMA_ERR_UNDERRUN_5 = (1 << 6),
  298. EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
  299. EDMA_ERR_LNK_CTRL_RX_1 |
  300. EDMA_ERR_LNK_CTRL_RX_3 |
  301. EDMA_ERR_LNK_CTRL_TX,
  302. EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
  303. EDMA_ERR_PRD_PAR |
  304. EDMA_ERR_DEV_DCON |
  305. EDMA_ERR_DEV_CON |
  306. EDMA_ERR_SERR |
  307. EDMA_ERR_SELF_DIS |
  308. EDMA_ERR_CRQB_PAR |
  309. EDMA_ERR_CRPB_PAR |
  310. EDMA_ERR_INTRL_PAR |
  311. EDMA_ERR_IORDY |
  312. EDMA_ERR_LNK_CTRL_RX_2 |
  313. EDMA_ERR_LNK_DATA_RX |
  314. EDMA_ERR_LNK_DATA_TX |
  315. EDMA_ERR_TRANS_PROTO,
  316. EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
  317. EDMA_ERR_PRD_PAR |
  318. EDMA_ERR_DEV_DCON |
  319. EDMA_ERR_DEV_CON |
  320. EDMA_ERR_OVERRUN_5 |
  321. EDMA_ERR_UNDERRUN_5 |
  322. EDMA_ERR_SELF_DIS_5 |
  323. EDMA_ERR_CRQB_PAR |
  324. EDMA_ERR_CRPB_PAR |
  325. EDMA_ERR_INTRL_PAR |
  326. EDMA_ERR_IORDY,
  327. EDMA_REQ_Q_BASE_HI = 0x10,
  328. EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
  329. EDMA_REQ_Q_OUT_PTR = 0x18,
  330. EDMA_REQ_Q_PTR_SHIFT = 5,
  331. EDMA_RSP_Q_BASE_HI = 0x1c,
  332. EDMA_RSP_Q_IN_PTR = 0x20,
  333. EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
  334. EDMA_RSP_Q_PTR_SHIFT = 3,
  335. EDMA_CMD = 0x28, /* EDMA command register */
  336. EDMA_EN = (1 << 0), /* enable EDMA */
  337. EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
  338. EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
  339. EDMA_STATUS = 0x30, /* EDMA engine status */
  340. EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
  341. EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
  342. EDMA_IORDY_TMOUT = 0x34,
  343. EDMA_ARB_CFG = 0x38,
  344. EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
  345. EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
  346. BMDMA_CMD = 0x224, /* bmdma command register */
  347. BMDMA_STATUS = 0x228, /* bmdma status register */
  348. BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
  349. BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
  350. /* Host private flags (hp_flags) */
  351. MV_HP_FLAG_MSI = (1 << 0),
  352. MV_HP_ERRATA_50XXB0 = (1 << 1),
  353. MV_HP_ERRATA_50XXB2 = (1 << 2),
  354. MV_HP_ERRATA_60X1B2 = (1 << 3),
  355. MV_HP_ERRATA_60X1C0 = (1 << 4),
  356. MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
  357. MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
  358. MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
  359. MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
  360. MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
  361. MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
  362. MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
  363. /* Port private flags (pp_flags) */
  364. MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
  365. MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
  366. MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
  367. MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
  368. MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
  369. };
  370. #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
  371. #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
  372. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  373. #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
  374. #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
  375. #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
  376. #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
  377. enum {
  378. /* DMA boundary 0xffff is required by the s/g splitting
  379. * we need on /length/ in mv_fill-sg().
  380. */
  381. MV_DMA_BOUNDARY = 0xffffU,
  382. /* mask of register bits containing lower 32 bits
  383. * of EDMA request queue DMA address
  384. */
  385. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  386. /* ditto, for response queue */
  387. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  388. };
  389. enum chip_type {
  390. chip_504x,
  391. chip_508x,
  392. chip_5080,
  393. chip_604x,
  394. chip_608x,
  395. chip_6042,
  396. chip_7042,
  397. chip_soc,
  398. };
  399. /* Command ReQuest Block: 32B */
  400. struct mv_crqb {
  401. __le32 sg_addr;
  402. __le32 sg_addr_hi;
  403. __le16 ctrl_flags;
  404. __le16 ata_cmd[11];
  405. };
  406. struct mv_crqb_iie {
  407. __le32 addr;
  408. __le32 addr_hi;
  409. __le32 flags;
  410. __le32 len;
  411. __le32 ata_cmd[4];
  412. };
  413. /* Command ResPonse Block: 8B */
  414. struct mv_crpb {
  415. __le16 id;
  416. __le16 flags;
  417. __le32 tmstmp;
  418. };
  419. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  420. struct mv_sg {
  421. __le32 addr;
  422. __le32 flags_size;
  423. __le32 addr_hi;
  424. __le32 reserved;
  425. };
  426. /*
  427. * We keep a local cache of a few frequently accessed port
  428. * registers here, to avoid having to read them (very slow)
  429. * when switching between EDMA and non-EDMA modes.
  430. */
  431. struct mv_cached_regs {
  432. u32 fiscfg;
  433. u32 ltmode;
  434. u32 haltcond;
  435. u32 unknown_rsvd;
  436. };
  437. struct mv_port_priv {
  438. struct mv_crqb *crqb;
  439. dma_addr_t crqb_dma;
  440. struct mv_crpb *crpb;
  441. dma_addr_t crpb_dma;
  442. struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
  443. dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
  444. unsigned int req_idx;
  445. unsigned int resp_idx;
  446. u32 pp_flags;
  447. struct mv_cached_regs cached;
  448. unsigned int delayed_eh_pmp_map;
  449. };
  450. struct mv_port_signal {
  451. u32 amps;
  452. u32 pre;
  453. };
  454. struct mv_host_priv {
  455. u32 hp_flags;
  456. unsigned int board_idx;
  457. u32 main_irq_mask;
  458. struct mv_port_signal signal[8];
  459. const struct mv_hw_ops *ops;
  460. int n_ports;
  461. void __iomem *base;
  462. void __iomem *main_irq_cause_addr;
  463. void __iomem *main_irq_mask_addr;
  464. u32 irq_cause_offset;
  465. u32 irq_mask_offset;
  466. u32 unmask_all_irqs;
  467. #if defined(CONFIG_HAVE_CLK)
  468. struct clk *clk;
  469. #endif
  470. /*
  471. * These consistent DMA memory pools give us guaranteed
  472. * alignment for hardware-accessed data structures,
  473. * and less memory waste in accomplishing the alignment.
  474. */
  475. struct dma_pool *crqb_pool;
  476. struct dma_pool *crpb_pool;
  477. struct dma_pool *sg_tbl_pool;
  478. };
  479. struct mv_hw_ops {
  480. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  481. unsigned int port);
  482. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  483. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  484. void __iomem *mmio);
  485. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  486. unsigned int n_hc);
  487. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  488. void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
  489. };
  490. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  491. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  492. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  493. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  494. static int mv_port_start(struct ata_port *ap);
  495. static void mv_port_stop(struct ata_port *ap);
  496. static int mv_qc_defer(struct ata_queued_cmd *qc);
  497. static void mv_qc_prep(struct ata_queued_cmd *qc);
  498. static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
  499. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  500. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  501. unsigned long deadline);
  502. static void mv_eh_freeze(struct ata_port *ap);
  503. static void mv_eh_thaw(struct ata_port *ap);
  504. static void mv6_dev_config(struct ata_device *dev);
  505. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  506. unsigned int port);
  507. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  508. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  509. void __iomem *mmio);
  510. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  511. unsigned int n_hc);
  512. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  513. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
  514. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  515. unsigned int port);
  516. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  517. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  518. void __iomem *mmio);
  519. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  520. unsigned int n_hc);
  521. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  522. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  523. void __iomem *mmio);
  524. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  525. void __iomem *mmio);
  526. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  527. void __iomem *mmio, unsigned int n_hc);
  528. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  529. void __iomem *mmio);
  530. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
  531. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  532. void __iomem *mmio, unsigned int port);
  533. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
  534. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  535. unsigned int port_no);
  536. static int mv_stop_edma(struct ata_port *ap);
  537. static int mv_stop_edma_engine(void __iomem *port_mmio);
  538. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
  539. static void mv_pmp_select(struct ata_port *ap, int pmp);
  540. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  541. unsigned long deadline);
  542. static int mv_softreset(struct ata_link *link, unsigned int *class,
  543. unsigned long deadline);
  544. static void mv_pmp_error_handler(struct ata_port *ap);
  545. static void mv_process_crpb_entries(struct ata_port *ap,
  546. struct mv_port_priv *pp);
  547. static void mv_sff_irq_clear(struct ata_port *ap);
  548. static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
  549. static void mv_bmdma_setup(struct ata_queued_cmd *qc);
  550. static void mv_bmdma_start(struct ata_queued_cmd *qc);
  551. static void mv_bmdma_stop(struct ata_queued_cmd *qc);
  552. static u8 mv_bmdma_status(struct ata_port *ap);
  553. static u8 mv_sff_check_status(struct ata_port *ap);
  554. /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
  555. * because we have to allow room for worst case splitting of
  556. * PRDs for 64K boundaries in mv_fill_sg().
  557. */
  558. static struct scsi_host_template mv5_sht = {
  559. ATA_BASE_SHT(DRV_NAME),
  560. .sg_tablesize = MV_MAX_SG_CT / 2,
  561. .dma_boundary = MV_DMA_BOUNDARY,
  562. };
  563. static struct scsi_host_template mv6_sht = {
  564. ATA_NCQ_SHT(DRV_NAME),
  565. .can_queue = MV_MAX_Q_DEPTH - 1,
  566. .sg_tablesize = MV_MAX_SG_CT / 2,
  567. .dma_boundary = MV_DMA_BOUNDARY,
  568. };
  569. static struct ata_port_operations mv5_ops = {
  570. .inherits = &ata_sff_port_ops,
  571. .lost_interrupt = ATA_OP_NULL,
  572. .qc_defer = mv_qc_defer,
  573. .qc_prep = mv_qc_prep,
  574. .qc_issue = mv_qc_issue,
  575. .freeze = mv_eh_freeze,
  576. .thaw = mv_eh_thaw,
  577. .hardreset = mv_hardreset,
  578. .scr_read = mv5_scr_read,
  579. .scr_write = mv5_scr_write,
  580. .port_start = mv_port_start,
  581. .port_stop = mv_port_stop,
  582. };
  583. static struct ata_port_operations mv6_ops = {
  584. .inherits = &ata_bmdma_port_ops,
  585. .lost_interrupt = ATA_OP_NULL,
  586. .qc_defer = mv_qc_defer,
  587. .qc_prep = mv_qc_prep,
  588. .qc_issue = mv_qc_issue,
  589. .dev_config = mv6_dev_config,
  590. .freeze = mv_eh_freeze,
  591. .thaw = mv_eh_thaw,
  592. .hardreset = mv_hardreset,
  593. .softreset = mv_softreset,
  594. .pmp_hardreset = mv_pmp_hardreset,
  595. .pmp_softreset = mv_softreset,
  596. .error_handler = mv_pmp_error_handler,
  597. .scr_read = mv_scr_read,
  598. .scr_write = mv_scr_write,
  599. .sff_check_status = mv_sff_check_status,
  600. .sff_irq_clear = mv_sff_irq_clear,
  601. .check_atapi_dma = mv_check_atapi_dma,
  602. .bmdma_setup = mv_bmdma_setup,
  603. .bmdma_start = mv_bmdma_start,
  604. .bmdma_stop = mv_bmdma_stop,
  605. .bmdma_status = mv_bmdma_status,
  606. .port_start = mv_port_start,
  607. .port_stop = mv_port_stop,
  608. };
  609. static struct ata_port_operations mv_iie_ops = {
  610. .inherits = &mv6_ops,
  611. .dev_config = ATA_OP_NULL,
  612. .qc_prep = mv_qc_prep_iie,
  613. };
  614. static const struct ata_port_info mv_port_info[] = {
  615. { /* chip_504x */
  616. .flags = MV_GEN_I_FLAGS,
  617. .pio_mask = ATA_PIO4,
  618. .udma_mask = ATA_UDMA6,
  619. .port_ops = &mv5_ops,
  620. },
  621. { /* chip_508x */
  622. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  623. .pio_mask = ATA_PIO4,
  624. .udma_mask = ATA_UDMA6,
  625. .port_ops = &mv5_ops,
  626. },
  627. { /* chip_5080 */
  628. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  629. .pio_mask = ATA_PIO4,
  630. .udma_mask = ATA_UDMA6,
  631. .port_ops = &mv5_ops,
  632. },
  633. { /* chip_604x */
  634. .flags = MV_GEN_II_FLAGS,
  635. .pio_mask = ATA_PIO4,
  636. .udma_mask = ATA_UDMA6,
  637. .port_ops = &mv6_ops,
  638. },
  639. { /* chip_608x */
  640. .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
  641. .pio_mask = ATA_PIO4,
  642. .udma_mask = ATA_UDMA6,
  643. .port_ops = &mv6_ops,
  644. },
  645. { /* chip_6042 */
  646. .flags = MV_GEN_IIE_FLAGS,
  647. .pio_mask = ATA_PIO4,
  648. .udma_mask = ATA_UDMA6,
  649. .port_ops = &mv_iie_ops,
  650. },
  651. { /* chip_7042 */
  652. .flags = MV_GEN_IIE_FLAGS,
  653. .pio_mask = ATA_PIO4,
  654. .udma_mask = ATA_UDMA6,
  655. .port_ops = &mv_iie_ops,
  656. },
  657. { /* chip_soc */
  658. .flags = MV_GEN_IIE_FLAGS,
  659. .pio_mask = ATA_PIO4,
  660. .udma_mask = ATA_UDMA6,
  661. .port_ops = &mv_iie_ops,
  662. },
  663. };
  664. static const struct pci_device_id mv_pci_tbl[] = {
  665. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  666. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  667. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  668. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  669. /* RocketRAID 1720/174x have different identifiers */
  670. { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
  671. { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
  672. { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
  673. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  674. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  675. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  676. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  677. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  678. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  679. /* Adaptec 1430SA */
  680. { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
  681. /* Marvell 7042 support */
  682. { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
  683. /* Highpoint RocketRAID PCIe series */
  684. { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
  685. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  686. { } /* terminate list */
  687. };
  688. static const struct mv_hw_ops mv5xxx_ops = {
  689. .phy_errata = mv5_phy_errata,
  690. .enable_leds = mv5_enable_leds,
  691. .read_preamp = mv5_read_preamp,
  692. .reset_hc = mv5_reset_hc,
  693. .reset_flash = mv5_reset_flash,
  694. .reset_bus = mv5_reset_bus,
  695. };
  696. static const struct mv_hw_ops mv6xxx_ops = {
  697. .phy_errata = mv6_phy_errata,
  698. .enable_leds = mv6_enable_leds,
  699. .read_preamp = mv6_read_preamp,
  700. .reset_hc = mv6_reset_hc,
  701. .reset_flash = mv6_reset_flash,
  702. .reset_bus = mv_reset_pci_bus,
  703. };
  704. static const struct mv_hw_ops mv_soc_ops = {
  705. .phy_errata = mv6_phy_errata,
  706. .enable_leds = mv_soc_enable_leds,
  707. .read_preamp = mv_soc_read_preamp,
  708. .reset_hc = mv_soc_reset_hc,
  709. .reset_flash = mv_soc_reset_flash,
  710. .reset_bus = mv_soc_reset_bus,
  711. };
  712. static const struct mv_hw_ops mv_soc_65n_ops = {
  713. .phy_errata = mv_soc_65n_phy_errata,
  714. .enable_leds = mv_soc_enable_leds,
  715. .reset_hc = mv_soc_reset_hc,
  716. .reset_flash = mv_soc_reset_flash,
  717. .reset_bus = mv_soc_reset_bus,
  718. };
  719. /*
  720. * Functions
  721. */
  722. static inline void writelfl(unsigned long data, void __iomem *addr)
  723. {
  724. writel(data, addr);
  725. (void) readl(addr); /* flush to avoid PCI posted write */
  726. }
  727. static inline unsigned int mv_hc_from_port(unsigned int port)
  728. {
  729. return port >> MV_PORT_HC_SHIFT;
  730. }
  731. static inline unsigned int mv_hardport_from_port(unsigned int port)
  732. {
  733. return port & MV_PORT_MASK;
  734. }
  735. /*
  736. * Consolidate some rather tricky bit shift calculations.
  737. * This is hot-path stuff, so not a function.
  738. * Simple code, with two return values, so macro rather than inline.
  739. *
  740. * port is the sole input, in range 0..7.
  741. * shift is one output, for use with main_irq_cause / main_irq_mask registers.
  742. * hardport is the other output, in range 0..3.
  743. *
  744. * Note that port and hardport may be the same variable in some cases.
  745. */
  746. #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
  747. { \
  748. shift = mv_hc_from_port(port) * HC_SHIFT; \
  749. hardport = mv_hardport_from_port(port); \
  750. shift += hardport * 2; \
  751. }
  752. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  753. {
  754. return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  755. }
  756. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  757. unsigned int port)
  758. {
  759. return mv_hc_base(base, mv_hc_from_port(port));
  760. }
  761. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  762. {
  763. return mv_hc_base_from_port(base, port) +
  764. MV_SATAHC_ARBTR_REG_SZ +
  765. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  766. }
  767. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  768. {
  769. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  770. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  771. return hc_mmio + ofs;
  772. }
  773. static inline void __iomem *mv_host_base(struct ata_host *host)
  774. {
  775. struct mv_host_priv *hpriv = host->private_data;
  776. return hpriv->base;
  777. }
  778. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  779. {
  780. return mv_port_base(mv_host_base(ap->host), ap->port_no);
  781. }
  782. static inline int mv_get_hc_count(unsigned long port_flags)
  783. {
  784. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  785. }
  786. /**
  787. * mv_save_cached_regs - (re-)initialize cached port registers
  788. * @ap: the port whose registers we are caching
  789. *
  790. * Initialize the local cache of port registers,
  791. * so that reading them over and over again can
  792. * be avoided on the hotter paths of this driver.
  793. * This saves a few microseconds each time we switch
  794. * to/from EDMA mode to perform (eg.) a drive cache flush.
  795. */
  796. static void mv_save_cached_regs(struct ata_port *ap)
  797. {
  798. void __iomem *port_mmio = mv_ap_base(ap);
  799. struct mv_port_priv *pp = ap->private_data;
  800. pp->cached.fiscfg = readl(port_mmio + FISCFG);
  801. pp->cached.ltmode = readl(port_mmio + LTMODE);
  802. pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
  803. pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
  804. }
  805. /**
  806. * mv_write_cached_reg - write to a cached port register
  807. * @addr: hardware address of the register
  808. * @old: pointer to cached value of the register
  809. * @new: new value for the register
  810. *
  811. * Write a new value to a cached register,
  812. * but only if the value is different from before.
  813. */
  814. static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
  815. {
  816. if (new != *old) {
  817. unsigned long laddr;
  818. *old = new;
  819. /*
  820. * Workaround for 88SX60x1-B2 FEr SATA#13:
  821. * Read-after-write is needed to prevent generating 64-bit
  822. * write cycles on the PCI bus for SATA interface registers
  823. * at offsets ending in 0x4 or 0xc.
  824. *
  825. * Looks like a lot of fuss, but it avoids an unnecessary
  826. * +1 usec read-after-write delay for unaffected registers.
  827. */
  828. laddr = (long)addr & 0xffff;
  829. if (laddr >= 0x300 && laddr <= 0x33c) {
  830. laddr &= 0x000f;
  831. if (laddr == 0x4 || laddr == 0xc) {
  832. writelfl(new, addr); /* read after write */
  833. return;
  834. }
  835. }
  836. writel(new, addr); /* unaffected by the errata */
  837. }
  838. }
  839. static void mv_set_edma_ptrs(void __iomem *port_mmio,
  840. struct mv_host_priv *hpriv,
  841. struct mv_port_priv *pp)
  842. {
  843. u32 index;
  844. /*
  845. * initialize request queue
  846. */
  847. pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  848. index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  849. WARN_ON(pp->crqb_dma & 0x3ff);
  850. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
  851. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
  852. port_mmio + EDMA_REQ_Q_IN_PTR);
  853. writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
  854. /*
  855. * initialize response queue
  856. */
  857. pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  858. index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
  859. WARN_ON(pp->crpb_dma & 0xff);
  860. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
  861. writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
  862. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
  863. port_mmio + EDMA_RSP_Q_OUT_PTR);
  864. }
  865. static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
  866. {
  867. /*
  868. * When writing to the main_irq_mask in hardware,
  869. * we must ensure exclusivity between the interrupt coalescing bits
  870. * and the corresponding individual port DONE_IRQ bits.
  871. *
  872. * Note that this register is really an "IRQ enable" register,
  873. * not an "IRQ mask" register as Marvell's naming might suggest.
  874. */
  875. if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
  876. mask &= ~DONE_IRQ_0_3;
  877. if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
  878. mask &= ~DONE_IRQ_4_7;
  879. writelfl(mask, hpriv->main_irq_mask_addr);
  880. }
  881. static void mv_set_main_irq_mask(struct ata_host *host,
  882. u32 disable_bits, u32 enable_bits)
  883. {
  884. struct mv_host_priv *hpriv = host->private_data;
  885. u32 old_mask, new_mask;
  886. old_mask = hpriv->main_irq_mask;
  887. new_mask = (old_mask & ~disable_bits) | enable_bits;
  888. if (new_mask != old_mask) {
  889. hpriv->main_irq_mask = new_mask;
  890. mv_write_main_irq_mask(new_mask, hpriv);
  891. }
  892. }
  893. static void mv_enable_port_irqs(struct ata_port *ap,
  894. unsigned int port_bits)
  895. {
  896. unsigned int shift, hardport, port = ap->port_no;
  897. u32 disable_bits, enable_bits;
  898. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  899. disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
  900. enable_bits = port_bits << shift;
  901. mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
  902. }
  903. static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
  904. void __iomem *port_mmio,
  905. unsigned int port_irqs)
  906. {
  907. struct mv_host_priv *hpriv = ap->host->private_data;
  908. int hardport = mv_hardport_from_port(ap->port_no);
  909. void __iomem *hc_mmio = mv_hc_base_from_port(
  910. mv_host_base(ap->host), ap->port_no);
  911. u32 hc_irq_cause;
  912. /* clear EDMA event indicators, if any */
  913. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  914. /* clear pending irq events */
  915. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  916. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  917. /* clear FIS IRQ Cause */
  918. if (IS_GEN_IIE(hpriv))
  919. writelfl(0, port_mmio + FIS_IRQ_CAUSE);
  920. mv_enable_port_irqs(ap, port_irqs);
  921. }
  922. static void mv_set_irq_coalescing(struct ata_host *host,
  923. unsigned int count, unsigned int usecs)
  924. {
  925. struct mv_host_priv *hpriv = host->private_data;
  926. void __iomem *mmio = hpriv->base, *hc_mmio;
  927. u32 coal_enable = 0;
  928. unsigned long flags;
  929. unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
  930. const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  931. ALL_PORTS_COAL_DONE;
  932. /* Disable IRQ coalescing if either threshold is zero */
  933. if (!usecs || !count) {
  934. clks = count = 0;
  935. } else {
  936. /* Respect maximum limits of the hardware */
  937. clks = usecs * COAL_CLOCKS_PER_USEC;
  938. if (clks > MAX_COAL_TIME_THRESHOLD)
  939. clks = MAX_COAL_TIME_THRESHOLD;
  940. if (count > MAX_COAL_IO_COUNT)
  941. count = MAX_COAL_IO_COUNT;
  942. }
  943. spin_lock_irqsave(&host->lock, flags);
  944. mv_set_main_irq_mask(host, coal_disable, 0);
  945. if (is_dual_hc && !IS_GEN_I(hpriv)) {
  946. /*
  947. * GEN_II/GEN_IIE with dual host controllers:
  948. * one set of global thresholds for the entire chip.
  949. */
  950. writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
  951. writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
  952. /* clear leftover coal IRQ bit */
  953. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  954. if (count)
  955. coal_enable = ALL_PORTS_COAL_DONE;
  956. clks = count = 0; /* force clearing of regular regs below */
  957. }
  958. /*
  959. * All chips: independent thresholds for each HC on the chip.
  960. */
  961. hc_mmio = mv_hc_base_from_port(mmio, 0);
  962. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  963. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  964. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  965. if (count)
  966. coal_enable |= PORTS_0_3_COAL_DONE;
  967. if (is_dual_hc) {
  968. hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
  969. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  970. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  971. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  972. if (count)
  973. coal_enable |= PORTS_4_7_COAL_DONE;
  974. }
  975. mv_set_main_irq_mask(host, 0, coal_enable);
  976. spin_unlock_irqrestore(&host->lock, flags);
  977. }
  978. /**
  979. * mv_start_edma - Enable eDMA engine
  980. * @base: port base address
  981. * @pp: port private data
  982. *
  983. * Verify the local cache of the eDMA state is accurate with a
  984. * WARN_ON.
  985. *
  986. * LOCKING:
  987. * Inherited from caller.
  988. */
  989. static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
  990. struct mv_port_priv *pp, u8 protocol)
  991. {
  992. int want_ncq = (protocol == ATA_PROT_NCQ);
  993. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  994. int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
  995. if (want_ncq != using_ncq)
  996. mv_stop_edma(ap);
  997. }
  998. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
  999. struct mv_host_priv *hpriv = ap->host->private_data;
  1000. mv_edma_cfg(ap, want_ncq, 1);
  1001. mv_set_edma_ptrs(port_mmio, hpriv, pp);
  1002. mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
  1003. writelfl(EDMA_EN, port_mmio + EDMA_CMD);
  1004. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  1005. }
  1006. }
  1007. static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
  1008. {
  1009. void __iomem *port_mmio = mv_ap_base(ap);
  1010. const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
  1011. const int per_loop = 5, timeout = (15 * 1000 / per_loop);
  1012. int i;
  1013. /*
  1014. * Wait for the EDMA engine to finish transactions in progress.
  1015. * No idea what a good "timeout" value might be, but measurements
  1016. * indicate that it often requires hundreds of microseconds
  1017. * with two drives in-use. So we use the 15msec value above
  1018. * as a rough guess at what even more drives might require.
  1019. */
  1020. for (i = 0; i < timeout; ++i) {
  1021. u32 edma_stat = readl(port_mmio + EDMA_STATUS);
  1022. if ((edma_stat & empty_idle) == empty_idle)
  1023. break;
  1024. udelay(per_loop);
  1025. }
  1026. /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
  1027. }
  1028. /**
  1029. * mv_stop_edma_engine - Disable eDMA engine
  1030. * @port_mmio: io base address
  1031. *
  1032. * LOCKING:
  1033. * Inherited from caller.
  1034. */
  1035. static int mv_stop_edma_engine(void __iomem *port_mmio)
  1036. {
  1037. int i;
  1038. /* Disable eDMA. The disable bit auto clears. */
  1039. writelfl(EDMA_DS, port_mmio + EDMA_CMD);
  1040. /* Wait for the chip to confirm eDMA is off. */
  1041. for (i = 10000; i > 0; i--) {
  1042. u32 reg = readl(port_mmio + EDMA_CMD);
  1043. if (!(reg & EDMA_EN))
  1044. return 0;
  1045. udelay(10);
  1046. }
  1047. return -EIO;
  1048. }
  1049. static int mv_stop_edma(struct ata_port *ap)
  1050. {
  1051. void __iomem *port_mmio = mv_ap_base(ap);
  1052. struct mv_port_priv *pp = ap->private_data;
  1053. int err = 0;
  1054. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  1055. return 0;
  1056. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1057. mv_wait_for_edma_empty_idle(ap);
  1058. if (mv_stop_edma_engine(port_mmio)) {
  1059. ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
  1060. err = -EIO;
  1061. }
  1062. mv_edma_cfg(ap, 0, 0);
  1063. return err;
  1064. }
  1065. #ifdef ATA_DEBUG
  1066. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  1067. {
  1068. int b, w;
  1069. for (b = 0; b < bytes; ) {
  1070. DPRINTK("%p: ", start + b);
  1071. for (w = 0; b < bytes && w < 4; w++) {
  1072. printk("%08x ", readl(start + b));
  1073. b += sizeof(u32);
  1074. }
  1075. printk("\n");
  1076. }
  1077. }
  1078. #endif
  1079. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  1080. {
  1081. #ifdef ATA_DEBUG
  1082. int b, w;
  1083. u32 dw;
  1084. for (b = 0; b < bytes; ) {
  1085. DPRINTK("%02x: ", b);
  1086. for (w = 0; b < bytes && w < 4; w++) {
  1087. (void) pci_read_config_dword(pdev, b, &dw);
  1088. printk("%08x ", dw);
  1089. b += sizeof(u32);
  1090. }
  1091. printk("\n");
  1092. }
  1093. #endif
  1094. }
  1095. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  1096. struct pci_dev *pdev)
  1097. {
  1098. #ifdef ATA_DEBUG
  1099. void __iomem *hc_base = mv_hc_base(mmio_base,
  1100. port >> MV_PORT_HC_SHIFT);
  1101. void __iomem *port_base;
  1102. int start_port, num_ports, p, start_hc, num_hcs, hc;
  1103. if (0 > port) {
  1104. start_hc = start_port = 0;
  1105. num_ports = 8; /* shld be benign for 4 port devs */
  1106. num_hcs = 2;
  1107. } else {
  1108. start_hc = port >> MV_PORT_HC_SHIFT;
  1109. start_port = port;
  1110. num_ports = num_hcs = 1;
  1111. }
  1112. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  1113. num_ports > 1 ? num_ports - 1 : start_port);
  1114. if (NULL != pdev) {
  1115. DPRINTK("PCI config space regs:\n");
  1116. mv_dump_pci_cfg(pdev, 0x68);
  1117. }
  1118. DPRINTK("PCI regs:\n");
  1119. mv_dump_mem(mmio_base+0xc00, 0x3c);
  1120. mv_dump_mem(mmio_base+0xd00, 0x34);
  1121. mv_dump_mem(mmio_base+0xf00, 0x4);
  1122. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  1123. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  1124. hc_base = mv_hc_base(mmio_base, hc);
  1125. DPRINTK("HC regs (HC %i):\n", hc);
  1126. mv_dump_mem(hc_base, 0x1c);
  1127. }
  1128. for (p = start_port; p < start_port + num_ports; p++) {
  1129. port_base = mv_port_base(mmio_base, p);
  1130. DPRINTK("EDMA regs (port %i):\n", p);
  1131. mv_dump_mem(port_base, 0x54);
  1132. DPRINTK("SATA regs (port %i):\n", p);
  1133. mv_dump_mem(port_base+0x300, 0x60);
  1134. }
  1135. #endif
  1136. }
  1137. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  1138. {
  1139. unsigned int ofs;
  1140. switch (sc_reg_in) {
  1141. case SCR_STATUS:
  1142. case SCR_CONTROL:
  1143. case SCR_ERROR:
  1144. ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
  1145. break;
  1146. case SCR_ACTIVE:
  1147. ofs = SATA_ACTIVE; /* active is not with the others */
  1148. break;
  1149. default:
  1150. ofs = 0xffffffffU;
  1151. break;
  1152. }
  1153. return ofs;
  1154. }
  1155. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  1156. {
  1157. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1158. if (ofs != 0xffffffffU) {
  1159. *val = readl(mv_ap_base(link->ap) + ofs);
  1160. return 0;
  1161. } else
  1162. return -EINVAL;
  1163. }
  1164. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  1165. {
  1166. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1167. if (ofs != 0xffffffffU) {
  1168. void __iomem *addr = mv_ap_base(link->ap) + ofs;
  1169. if (sc_reg_in == SCR_CONTROL) {
  1170. /*
  1171. * Workaround for 88SX60x1 FEr SATA#26:
  1172. *
  1173. * COMRESETs have to take care not to accidentally
  1174. * put the drive to sleep when writing SCR_CONTROL.
  1175. * Setting bits 12..15 prevents this problem.
  1176. *
  1177. * So if we see an outbound COMMRESET, set those bits.
  1178. * Ditto for the followup write that clears the reset.
  1179. *
  1180. * The proprietary driver does this for
  1181. * all chip versions, and so do we.
  1182. */
  1183. if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
  1184. val |= 0xf000;
  1185. }
  1186. writelfl(val, addr);
  1187. return 0;
  1188. } else
  1189. return -EINVAL;
  1190. }
  1191. static void mv6_dev_config(struct ata_device *adev)
  1192. {
  1193. /*
  1194. * Deal with Gen-II ("mv6") hardware quirks/restrictions:
  1195. *
  1196. * Gen-II does not support NCQ over a port multiplier
  1197. * (no FIS-based switching).
  1198. */
  1199. if (adev->flags & ATA_DFLAG_NCQ) {
  1200. if (sata_pmp_attached(adev->link->ap)) {
  1201. adev->flags &= ~ATA_DFLAG_NCQ;
  1202. ata_dev_printk(adev, KERN_INFO,
  1203. "NCQ disabled for command-based switching\n");
  1204. }
  1205. }
  1206. }
  1207. static int mv_qc_defer(struct ata_queued_cmd *qc)
  1208. {
  1209. struct ata_link *link = qc->dev->link;
  1210. struct ata_port *ap = link->ap;
  1211. struct mv_port_priv *pp = ap->private_data;
  1212. /*
  1213. * Don't allow new commands if we're in a delayed EH state
  1214. * for NCQ and/or FIS-based switching.
  1215. */
  1216. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  1217. return ATA_DEFER_PORT;
  1218. /* PIO commands need exclusive link: no other commands [DMA or PIO]
  1219. * can run concurrently.
  1220. * set excl_link when we want to send a PIO command in DMA mode
  1221. * or a non-NCQ command in NCQ mode.
  1222. * When we receive a command from that link, and there are no
  1223. * outstanding commands, mark a flag to clear excl_link and let
  1224. * the command go through.
  1225. */
  1226. if (unlikely(ap->excl_link)) {
  1227. if (link == ap->excl_link) {
  1228. if (ap->nr_active_links)
  1229. return ATA_DEFER_PORT;
  1230. qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
  1231. return 0;
  1232. } else
  1233. return ATA_DEFER_PORT;
  1234. }
  1235. /*
  1236. * If the port is completely idle, then allow the new qc.
  1237. */
  1238. if (ap->nr_active_links == 0)
  1239. return 0;
  1240. /*
  1241. * The port is operating in host queuing mode (EDMA) with NCQ
  1242. * enabled, allow multiple NCQ commands. EDMA also allows
  1243. * queueing multiple DMA commands but libata core currently
  1244. * doesn't allow it.
  1245. */
  1246. if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
  1247. (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
  1248. if (ata_is_ncq(qc->tf.protocol))
  1249. return 0;
  1250. else {
  1251. ap->excl_link = link;
  1252. return ATA_DEFER_PORT;
  1253. }
  1254. }
  1255. return ATA_DEFER_PORT;
  1256. }
  1257. static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
  1258. {
  1259. struct mv_port_priv *pp = ap->private_data;
  1260. void __iomem *port_mmio;
  1261. u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
  1262. u32 ltmode, *old_ltmode = &pp->cached.ltmode;
  1263. u32 haltcond, *old_haltcond = &pp->cached.haltcond;
  1264. ltmode = *old_ltmode & ~LTMODE_BIT8;
  1265. haltcond = *old_haltcond | EDMA_ERR_DEV;
  1266. if (want_fbs) {
  1267. fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
  1268. ltmode = *old_ltmode | LTMODE_BIT8;
  1269. if (want_ncq)
  1270. haltcond &= ~EDMA_ERR_DEV;
  1271. else
  1272. fiscfg |= FISCFG_WAIT_DEV_ERR;
  1273. } else {
  1274. fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
  1275. }
  1276. port_mmio = mv_ap_base(ap);
  1277. mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
  1278. mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
  1279. mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
  1280. }
  1281. static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
  1282. {
  1283. struct mv_host_priv *hpriv = ap->host->private_data;
  1284. u32 old, new;
  1285. /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
  1286. old = readl(hpriv->base + GPIO_PORT_CTL);
  1287. if (want_ncq)
  1288. new = old | (1 << 22);
  1289. else
  1290. new = old & ~(1 << 22);
  1291. if (new != old)
  1292. writel(new, hpriv->base + GPIO_PORT_CTL);
  1293. }
  1294. /**
  1295. * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
  1296. * @ap: Port being initialized
  1297. *
  1298. * There are two DMA modes on these chips: basic DMA, and EDMA.
  1299. *
  1300. * Bit-0 of the "EDMA RESERVED" register enables/disables use
  1301. * of basic DMA on the GEN_IIE versions of the chips.
  1302. *
  1303. * This bit survives EDMA resets, and must be set for basic DMA
  1304. * to function, and should be cleared when EDMA is active.
  1305. */
  1306. static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
  1307. {
  1308. struct mv_port_priv *pp = ap->private_data;
  1309. u32 new, *old = &pp->cached.unknown_rsvd;
  1310. if (enable_bmdma)
  1311. new = *old | 1;
  1312. else
  1313. new = *old & ~1;
  1314. mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
  1315. }
  1316. /*
  1317. * SOC chips have an issue whereby the HDD LEDs don't always blink
  1318. * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
  1319. * of the SOC takes care of it, generating a steady blink rate when
  1320. * any drive on the chip is active.
  1321. *
  1322. * Unfortunately, the blink mode is a global hardware setting for the SOC,
  1323. * so we must use it whenever at least one port on the SOC has NCQ enabled.
  1324. *
  1325. * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
  1326. * LED operation works then, and provides better (more accurate) feedback.
  1327. *
  1328. * Note that this code assumes that an SOC never has more than one HC onboard.
  1329. */
  1330. static void mv_soc_led_blink_enable(struct ata_port *ap)
  1331. {
  1332. struct ata_host *host = ap->host;
  1333. struct mv_host_priv *hpriv = host->private_data;
  1334. void __iomem *hc_mmio;
  1335. u32 led_ctrl;
  1336. if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
  1337. return;
  1338. hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
  1339. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1340. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1341. writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1342. }
  1343. static void mv_soc_led_blink_disable(struct ata_port *ap)
  1344. {
  1345. struct ata_host *host = ap->host;
  1346. struct mv_host_priv *hpriv = host->private_data;
  1347. void __iomem *hc_mmio;
  1348. u32 led_ctrl;
  1349. unsigned int port;
  1350. if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
  1351. return;
  1352. /* disable led-blink only if no ports are using NCQ */
  1353. for (port = 0; port < hpriv->n_ports; port++) {
  1354. struct ata_port *this_ap = host->ports[port];
  1355. struct mv_port_priv *pp = this_ap->private_data;
  1356. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  1357. return;
  1358. }
  1359. hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
  1360. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1361. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1362. writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1363. }
  1364. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
  1365. {
  1366. u32 cfg;
  1367. struct mv_port_priv *pp = ap->private_data;
  1368. struct mv_host_priv *hpriv = ap->host->private_data;
  1369. void __iomem *port_mmio = mv_ap_base(ap);
  1370. /* set up non-NCQ EDMA configuration */
  1371. cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
  1372. pp->pp_flags &=
  1373. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  1374. if (IS_GEN_I(hpriv))
  1375. cfg |= (1 << 8); /* enab config burst size mask */
  1376. else if (IS_GEN_II(hpriv)) {
  1377. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  1378. mv_60x1_errata_sata25(ap, want_ncq);
  1379. } else if (IS_GEN_IIE(hpriv)) {
  1380. int want_fbs = sata_pmp_attached(ap);
  1381. /*
  1382. * Possible future enhancement:
  1383. *
  1384. * The chip can use FBS with non-NCQ, if we allow it,
  1385. * But first we need to have the error handling in place
  1386. * for this mode (datasheet section 7.3.15.4.2.3).
  1387. * So disallow non-NCQ FBS for now.
  1388. */
  1389. want_fbs &= want_ncq;
  1390. mv_config_fbs(ap, want_ncq, want_fbs);
  1391. if (want_fbs) {
  1392. pp->pp_flags |= MV_PP_FLAG_FBS_EN;
  1393. cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
  1394. }
  1395. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  1396. if (want_edma) {
  1397. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  1398. if (!IS_SOC(hpriv))
  1399. cfg |= (1 << 18); /* enab early completion */
  1400. }
  1401. if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
  1402. cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
  1403. mv_bmdma_enable_iie(ap, !want_edma);
  1404. if (IS_SOC(hpriv)) {
  1405. if (want_ncq)
  1406. mv_soc_led_blink_enable(ap);
  1407. else
  1408. mv_soc_led_blink_disable(ap);
  1409. }
  1410. }
  1411. if (want_ncq) {
  1412. cfg |= EDMA_CFG_NCQ;
  1413. pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
  1414. }
  1415. writelfl(cfg, port_mmio + EDMA_CFG);
  1416. }
  1417. static void mv_port_free_dma_mem(struct ata_port *ap)
  1418. {
  1419. struct mv_host_priv *hpriv = ap->host->private_data;
  1420. struct mv_port_priv *pp = ap->private_data;
  1421. int tag;
  1422. if (pp->crqb) {
  1423. dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
  1424. pp->crqb = NULL;
  1425. }
  1426. if (pp->crpb) {
  1427. dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
  1428. pp->crpb = NULL;
  1429. }
  1430. /*
  1431. * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
  1432. * For later hardware, we have one unique sg_tbl per NCQ tag.
  1433. */
  1434. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1435. if (pp->sg_tbl[tag]) {
  1436. if (tag == 0 || !IS_GEN_I(hpriv))
  1437. dma_pool_free(hpriv->sg_tbl_pool,
  1438. pp->sg_tbl[tag],
  1439. pp->sg_tbl_dma[tag]);
  1440. pp->sg_tbl[tag] = NULL;
  1441. }
  1442. }
  1443. }
  1444. /**
  1445. * mv_port_start - Port specific init/start routine.
  1446. * @ap: ATA channel to manipulate
  1447. *
  1448. * Allocate and point to DMA memory, init port private memory,
  1449. * zero indices.
  1450. *
  1451. * LOCKING:
  1452. * Inherited from caller.
  1453. */
  1454. static int mv_port_start(struct ata_port *ap)
  1455. {
  1456. struct device *dev = ap->host->dev;
  1457. struct mv_host_priv *hpriv = ap->host->private_data;
  1458. struct mv_port_priv *pp;
  1459. unsigned long flags;
  1460. int tag;
  1461. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1462. if (!pp)
  1463. return -ENOMEM;
  1464. ap->private_data = pp;
  1465. pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
  1466. if (!pp->crqb)
  1467. return -ENOMEM;
  1468. memset(pp->crqb, 0, MV_CRQB_Q_SZ);
  1469. pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
  1470. if (!pp->crpb)
  1471. goto out_port_free_dma_mem;
  1472. memset(pp->crpb, 0, MV_CRPB_Q_SZ);
  1473. /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
  1474. if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
  1475. ap->flags |= ATA_FLAG_AN;
  1476. /*
  1477. * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
  1478. * For later hardware, we need one unique sg_tbl per NCQ tag.
  1479. */
  1480. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1481. if (tag == 0 || !IS_GEN_I(hpriv)) {
  1482. pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
  1483. GFP_KERNEL, &pp->sg_tbl_dma[tag]);
  1484. if (!pp->sg_tbl[tag])
  1485. goto out_port_free_dma_mem;
  1486. } else {
  1487. pp->sg_tbl[tag] = pp->sg_tbl[0];
  1488. pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
  1489. }
  1490. }
  1491. spin_lock_irqsave(ap->lock, flags);
  1492. mv_save_cached_regs(ap);
  1493. mv_edma_cfg(ap, 0, 0);
  1494. spin_unlock_irqrestore(ap->lock, flags);
  1495. return 0;
  1496. out_port_free_dma_mem:
  1497. mv_port_free_dma_mem(ap);
  1498. return -ENOMEM;
  1499. }
  1500. /**
  1501. * mv_port_stop - Port specific cleanup/stop routine.
  1502. * @ap: ATA channel to manipulate
  1503. *
  1504. * Stop DMA, cleanup port memory.
  1505. *
  1506. * LOCKING:
  1507. * This routine uses the host lock to protect the DMA stop.
  1508. */
  1509. static void mv_port_stop(struct ata_port *ap)
  1510. {
  1511. unsigned long flags;
  1512. spin_lock_irqsave(ap->lock, flags);
  1513. mv_stop_edma(ap);
  1514. mv_enable_port_irqs(ap, 0);
  1515. spin_unlock_irqrestore(ap->lock, flags);
  1516. mv_port_free_dma_mem(ap);
  1517. }
  1518. /**
  1519. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  1520. * @qc: queued command whose SG list to source from
  1521. *
  1522. * Populate the SG list and mark the last entry.
  1523. *
  1524. * LOCKING:
  1525. * Inherited from caller.
  1526. */
  1527. static void mv_fill_sg(struct ata_queued_cmd *qc)
  1528. {
  1529. struct mv_port_priv *pp = qc->ap->private_data;
  1530. struct scatterlist *sg;
  1531. struct mv_sg *mv_sg, *last_sg = NULL;
  1532. unsigned int si;
  1533. mv_sg = pp->sg_tbl[qc->tag];
  1534. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1535. dma_addr_t addr = sg_dma_address(sg);
  1536. u32 sg_len = sg_dma_len(sg);
  1537. while (sg_len) {
  1538. u32 offset = addr & 0xffff;
  1539. u32 len = sg_len;
  1540. if (offset + len > 0x10000)
  1541. len = 0x10000 - offset;
  1542. mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
  1543. mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1544. mv_sg->flags_size = cpu_to_le32(len & 0xffff);
  1545. mv_sg->reserved = 0;
  1546. sg_len -= len;
  1547. addr += len;
  1548. last_sg = mv_sg;
  1549. mv_sg++;
  1550. }
  1551. }
  1552. if (likely(last_sg))
  1553. last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  1554. mb(); /* ensure data structure is visible to the chipset */
  1555. }
  1556. static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  1557. {
  1558. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  1559. (last ? CRQB_CMD_LAST : 0);
  1560. *cmdw = cpu_to_le16(tmp);
  1561. }
  1562. /**
  1563. * mv_sff_irq_clear - Clear hardware interrupt after DMA.
  1564. * @ap: Port associated with this ATA transaction.
  1565. *
  1566. * We need this only for ATAPI bmdma transactions,
  1567. * as otherwise we experience spurious interrupts
  1568. * after libata-sff handles the bmdma interrupts.
  1569. */
  1570. static void mv_sff_irq_clear(struct ata_port *ap)
  1571. {
  1572. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
  1573. }
  1574. /**
  1575. * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
  1576. * @qc: queued command to check for chipset/DMA compatibility.
  1577. *
  1578. * The bmdma engines cannot handle speculative data sizes
  1579. * (bytecount under/over flow). So only allow DMA for
  1580. * data transfer commands with known data sizes.
  1581. *
  1582. * LOCKING:
  1583. * Inherited from caller.
  1584. */
  1585. static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
  1586. {
  1587. struct scsi_cmnd *scmd = qc->scsicmd;
  1588. if (scmd) {
  1589. switch (scmd->cmnd[0]) {
  1590. case READ_6:
  1591. case READ_10:
  1592. case READ_12:
  1593. case WRITE_6:
  1594. case WRITE_10:
  1595. case WRITE_12:
  1596. case GPCMD_READ_CD:
  1597. case GPCMD_SEND_DVD_STRUCTURE:
  1598. case GPCMD_SEND_CUE_SHEET:
  1599. return 0; /* DMA is safe */
  1600. }
  1601. }
  1602. return -EOPNOTSUPP; /* use PIO instead */
  1603. }
  1604. /**
  1605. * mv_bmdma_setup - Set up BMDMA transaction
  1606. * @qc: queued command to prepare DMA for.
  1607. *
  1608. * LOCKING:
  1609. * Inherited from caller.
  1610. */
  1611. static void mv_bmdma_setup(struct ata_queued_cmd *qc)
  1612. {
  1613. struct ata_port *ap = qc->ap;
  1614. void __iomem *port_mmio = mv_ap_base(ap);
  1615. struct mv_port_priv *pp = ap->private_data;
  1616. mv_fill_sg(qc);
  1617. /* clear all DMA cmd bits */
  1618. writel(0, port_mmio + BMDMA_CMD);
  1619. /* load PRD table addr. */
  1620. writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
  1621. port_mmio + BMDMA_PRD_HIGH);
  1622. writelfl(pp->sg_tbl_dma[qc->tag],
  1623. port_mmio + BMDMA_PRD_LOW);
  1624. /* issue r/w command */
  1625. ap->ops->sff_exec_command(ap, &qc->tf);
  1626. }
  1627. /**
  1628. * mv_bmdma_start - Start a BMDMA transaction
  1629. * @qc: queued command to start DMA on.
  1630. *
  1631. * LOCKING:
  1632. * Inherited from caller.
  1633. */
  1634. static void mv_bmdma_start(struct ata_queued_cmd *qc)
  1635. {
  1636. struct ata_port *ap = qc->ap;
  1637. void __iomem *port_mmio = mv_ap_base(ap);
  1638. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  1639. u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
  1640. /* start host DMA transaction */
  1641. writelfl(cmd, port_mmio + BMDMA_CMD);
  1642. }
  1643. /**
  1644. * mv_bmdma_stop - Stop BMDMA transfer
  1645. * @qc: queued command to stop DMA on.
  1646. *
  1647. * Clears the ATA_DMA_START flag in the bmdma control register
  1648. *
  1649. * LOCKING:
  1650. * Inherited from caller.
  1651. */
  1652. static void mv_bmdma_stop_ap(struct ata_port *ap)
  1653. {
  1654. void __iomem *port_mmio = mv_ap_base(ap);
  1655. u32 cmd;
  1656. /* clear start/stop bit */
  1657. cmd = readl(port_mmio + BMDMA_CMD);
  1658. if (cmd & ATA_DMA_START) {
  1659. cmd &= ~ATA_DMA_START;
  1660. writelfl(cmd, port_mmio + BMDMA_CMD);
  1661. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  1662. ata_sff_dma_pause(ap);
  1663. }
  1664. }
  1665. static void mv_bmdma_stop(struct ata_queued_cmd *qc)
  1666. {
  1667. mv_bmdma_stop_ap(qc->ap);
  1668. }
  1669. /**
  1670. * mv_bmdma_status - Read BMDMA status
  1671. * @ap: port for which to retrieve DMA status.
  1672. *
  1673. * Read and return equivalent of the sff BMDMA status register.
  1674. *
  1675. * LOCKING:
  1676. * Inherited from caller.
  1677. */
  1678. static u8 mv_bmdma_status(struct ata_port *ap)
  1679. {
  1680. void __iomem *port_mmio = mv_ap_base(ap);
  1681. u32 reg, status;
  1682. /*
  1683. * Other bits are valid only if ATA_DMA_ACTIVE==0,
  1684. * and the ATA_DMA_INTR bit doesn't exist.
  1685. */
  1686. reg = readl(port_mmio + BMDMA_STATUS);
  1687. if (reg & ATA_DMA_ACTIVE)
  1688. status = ATA_DMA_ACTIVE;
  1689. else if (reg & ATA_DMA_ERR)
  1690. status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
  1691. else {
  1692. /*
  1693. * Just because DMA_ACTIVE is 0 (DMA completed),
  1694. * this does _not_ mean the device is "done".
  1695. * So we should not yet be signalling ATA_DMA_INTR
  1696. * in some cases. Eg. DSM/TRIM, and perhaps others.
  1697. */
  1698. mv_bmdma_stop_ap(ap);
  1699. if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
  1700. status = 0;
  1701. else
  1702. status = ATA_DMA_INTR;
  1703. }
  1704. return status;
  1705. }
  1706. static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
  1707. {
  1708. struct ata_taskfile *tf = &qc->tf;
  1709. /*
  1710. * Workaround for 88SX60x1 FEr SATA#24.
  1711. *
  1712. * Chip may corrupt WRITEs if multi_count >= 4kB.
  1713. * Note that READs are unaffected.
  1714. *
  1715. * It's not clear if this errata really means "4K bytes",
  1716. * or if it always happens for multi_count > 7
  1717. * regardless of device sector_size.
  1718. *
  1719. * So, for safety, any write with multi_count > 7
  1720. * gets converted here into a regular PIO write instead:
  1721. */
  1722. if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
  1723. if (qc->dev->multi_count > 7) {
  1724. switch (tf->command) {
  1725. case ATA_CMD_WRITE_MULTI:
  1726. tf->command = ATA_CMD_PIO_WRITE;
  1727. break;
  1728. case ATA_CMD_WRITE_MULTI_FUA_EXT:
  1729. tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
  1730. /* fall through */
  1731. case ATA_CMD_WRITE_MULTI_EXT:
  1732. tf->command = ATA_CMD_PIO_WRITE_EXT;
  1733. break;
  1734. }
  1735. }
  1736. }
  1737. }
  1738. /**
  1739. * mv_qc_prep - Host specific command preparation.
  1740. * @qc: queued command to prepare
  1741. *
  1742. * This routine simply redirects to the general purpose routine
  1743. * if command is not DMA. Else, it handles prep of the CRQB
  1744. * (command request block), does some sanity checking, and calls
  1745. * the SG load routine.
  1746. *
  1747. * LOCKING:
  1748. * Inherited from caller.
  1749. */
  1750. static void mv_qc_prep(struct ata_queued_cmd *qc)
  1751. {
  1752. struct ata_port *ap = qc->ap;
  1753. struct mv_port_priv *pp = ap->private_data;
  1754. __le16 *cw;
  1755. struct ata_taskfile *tf = &qc->tf;
  1756. u16 flags = 0;
  1757. unsigned in_index;
  1758. switch (tf->protocol) {
  1759. case ATA_PROT_DMA:
  1760. if (tf->command == ATA_CMD_DSM)
  1761. return;
  1762. /* fall-thru */
  1763. case ATA_PROT_NCQ:
  1764. break; /* continue below */
  1765. case ATA_PROT_PIO:
  1766. mv_rw_multi_errata_sata24(qc);
  1767. return;
  1768. default:
  1769. return;
  1770. }
  1771. /* Fill in command request block
  1772. */
  1773. if (!(tf->flags & ATA_TFLAG_WRITE))
  1774. flags |= CRQB_FLAG_READ;
  1775. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1776. flags |= qc->tag << CRQB_TAG_SHIFT;
  1777. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1778. /* get current queue index from software */
  1779. in_index = pp->req_idx;
  1780. pp->crqb[in_index].sg_addr =
  1781. cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1782. pp->crqb[in_index].sg_addr_hi =
  1783. cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1784. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  1785. cw = &pp->crqb[in_index].ata_cmd[0];
  1786. /* Sadly, the CRQB cannot accommodate all registers--there are
  1787. * only 11 bytes...so we must pick and choose required
  1788. * registers based on the command. So, we drop feature and
  1789. * hob_feature for [RW] DMA commands, but they are needed for
  1790. * NCQ. NCQ will drop hob_nsect, which is not needed there
  1791. * (nsect is used only for the tag; feat/hob_feat hold true nsect).
  1792. */
  1793. switch (tf->command) {
  1794. case ATA_CMD_READ:
  1795. case ATA_CMD_READ_EXT:
  1796. case ATA_CMD_WRITE:
  1797. case ATA_CMD_WRITE_EXT:
  1798. case ATA_CMD_WRITE_FUA_EXT:
  1799. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  1800. break;
  1801. case ATA_CMD_FPDMA_READ:
  1802. case ATA_CMD_FPDMA_WRITE:
  1803. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  1804. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  1805. break;
  1806. default:
  1807. /* The only other commands EDMA supports in non-queued and
  1808. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  1809. * of which are defined/used by Linux. If we get here, this
  1810. * driver needs work.
  1811. *
  1812. * FIXME: modify libata to give qc_prep a return value and
  1813. * return error here.
  1814. */
  1815. BUG_ON(tf->command);
  1816. break;
  1817. }
  1818. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  1819. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  1820. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  1821. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  1822. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  1823. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  1824. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  1825. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  1826. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  1827. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1828. return;
  1829. mv_fill_sg(qc);
  1830. }
  1831. /**
  1832. * mv_qc_prep_iie - Host specific command preparation.
  1833. * @qc: queued command to prepare
  1834. *
  1835. * This routine simply redirects to the general purpose routine
  1836. * if command is not DMA. Else, it handles prep of the CRQB
  1837. * (command request block), does some sanity checking, and calls
  1838. * the SG load routine.
  1839. *
  1840. * LOCKING:
  1841. * Inherited from caller.
  1842. */
  1843. static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
  1844. {
  1845. struct ata_port *ap = qc->ap;
  1846. struct mv_port_priv *pp = ap->private_data;
  1847. struct mv_crqb_iie *crqb;
  1848. struct ata_taskfile *tf = &qc->tf;
  1849. unsigned in_index;
  1850. u32 flags = 0;
  1851. if ((tf->protocol != ATA_PROT_DMA) &&
  1852. (tf->protocol != ATA_PROT_NCQ))
  1853. return;
  1854. if (tf->command == ATA_CMD_DSM)
  1855. return; /* use bmdma for this */
  1856. /* Fill in Gen IIE command request block */
  1857. if (!(tf->flags & ATA_TFLAG_WRITE))
  1858. flags |= CRQB_FLAG_READ;
  1859. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1860. flags |= qc->tag << CRQB_TAG_SHIFT;
  1861. flags |= qc->tag << CRQB_HOSTQ_SHIFT;
  1862. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1863. /* get current queue index from software */
  1864. in_index = pp->req_idx;
  1865. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  1866. crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1867. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1868. crqb->flags = cpu_to_le32(flags);
  1869. crqb->ata_cmd[0] = cpu_to_le32(
  1870. (tf->command << 16) |
  1871. (tf->feature << 24)
  1872. );
  1873. crqb->ata_cmd[1] = cpu_to_le32(
  1874. (tf->lbal << 0) |
  1875. (tf->lbam << 8) |
  1876. (tf->lbah << 16) |
  1877. (tf->device << 24)
  1878. );
  1879. crqb->ata_cmd[2] = cpu_to_le32(
  1880. (tf->hob_lbal << 0) |
  1881. (tf->hob_lbam << 8) |
  1882. (tf->hob_lbah << 16) |
  1883. (tf->hob_feature << 24)
  1884. );
  1885. crqb->ata_cmd[3] = cpu_to_le32(
  1886. (tf->nsect << 0) |
  1887. (tf->hob_nsect << 8)
  1888. );
  1889. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1890. return;
  1891. mv_fill_sg(qc);
  1892. }
  1893. /**
  1894. * mv_sff_check_status - fetch device status, if valid
  1895. * @ap: ATA port to fetch status from
  1896. *
  1897. * When using command issue via mv_qc_issue_fis(),
  1898. * the initial ATA_BUSY state does not show up in the
  1899. * ATA status (shadow) register. This can confuse libata!
  1900. *
  1901. * So we have a hook here to fake ATA_BUSY for that situation,
  1902. * until the first time a BUSY, DRQ, or ERR bit is seen.
  1903. *
  1904. * The rest of the time, it simply returns the ATA status register.
  1905. */
  1906. static u8 mv_sff_check_status(struct ata_port *ap)
  1907. {
  1908. u8 stat = ioread8(ap->ioaddr.status_addr);
  1909. struct mv_port_priv *pp = ap->private_data;
  1910. if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
  1911. if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
  1912. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
  1913. else
  1914. stat = ATA_BUSY;
  1915. }
  1916. return stat;
  1917. }
  1918. /**
  1919. * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
  1920. * @fis: fis to be sent
  1921. * @nwords: number of 32-bit words in the fis
  1922. */
  1923. static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
  1924. {
  1925. void __iomem *port_mmio = mv_ap_base(ap);
  1926. u32 ifctl, old_ifctl, ifstat;
  1927. int i, timeout = 200, final_word = nwords - 1;
  1928. /* Initiate FIS transmission mode */
  1929. old_ifctl = readl(port_mmio + SATA_IFCTL);
  1930. ifctl = 0x100 | (old_ifctl & 0xf);
  1931. writelfl(ifctl, port_mmio + SATA_IFCTL);
  1932. /* Send all words of the FIS except for the final word */
  1933. for (i = 0; i < final_word; ++i)
  1934. writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
  1935. /* Flag end-of-transmission, and then send the final word */
  1936. writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
  1937. writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
  1938. /*
  1939. * Wait for FIS transmission to complete.
  1940. * This typically takes just a single iteration.
  1941. */
  1942. do {
  1943. ifstat = readl(port_mmio + SATA_IFSTAT);
  1944. } while (!(ifstat & 0x1000) && --timeout);
  1945. /* Restore original port configuration */
  1946. writelfl(old_ifctl, port_mmio + SATA_IFCTL);
  1947. /* See if it worked */
  1948. if ((ifstat & 0x3000) != 0x1000) {
  1949. ata_port_printk(ap, KERN_WARNING,
  1950. "%s transmission error, ifstat=%08x\n",
  1951. __func__, ifstat);
  1952. return AC_ERR_OTHER;
  1953. }
  1954. return 0;
  1955. }
  1956. /**
  1957. * mv_qc_issue_fis - Issue a command directly as a FIS
  1958. * @qc: queued command to start
  1959. *
  1960. * Note that the ATA shadow registers are not updated
  1961. * after command issue, so the device will appear "READY"
  1962. * if polled, even while it is BUSY processing the command.
  1963. *
  1964. * So we use a status hook to fake ATA_BUSY until the drive changes state.
  1965. *
  1966. * Note: we don't get updated shadow regs on *completion*
  1967. * of non-data commands. So avoid sending them via this function,
  1968. * as they will appear to have completed immediately.
  1969. *
  1970. * GEN_IIE has special registers that we could get the result tf from,
  1971. * but earlier chipsets do not. For now, we ignore those registers.
  1972. */
  1973. static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
  1974. {
  1975. struct ata_port *ap = qc->ap;
  1976. struct mv_port_priv *pp = ap->private_data;
  1977. struct ata_link *link = qc->dev->link;
  1978. u32 fis[5];
  1979. int err = 0;
  1980. ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
  1981. err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
  1982. if (err)
  1983. return err;
  1984. switch (qc->tf.protocol) {
  1985. case ATAPI_PROT_PIO:
  1986. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1987. /* fall through */
  1988. case ATAPI_PROT_NODATA:
  1989. ap->hsm_task_state = HSM_ST_FIRST;
  1990. break;
  1991. case ATA_PROT_PIO:
  1992. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1993. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1994. ap->hsm_task_state = HSM_ST_FIRST;
  1995. else
  1996. ap->hsm_task_state = HSM_ST;
  1997. break;
  1998. default:
  1999. ap->hsm_task_state = HSM_ST_LAST;
  2000. break;
  2001. }
  2002. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2003. ata_sff_queue_pio_task(link, 0);
  2004. return 0;
  2005. }
  2006. /**
  2007. * mv_qc_issue - Initiate a command to the host
  2008. * @qc: queued command to start
  2009. *
  2010. * This routine simply redirects to the general purpose routine
  2011. * if command is not DMA. Else, it sanity checks our local
  2012. * caches of the request producer/consumer indices then enables
  2013. * DMA and bumps the request producer index.
  2014. *
  2015. * LOCKING:
  2016. * Inherited from caller.
  2017. */
  2018. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  2019. {
  2020. static int limit_warnings = 10;
  2021. struct ata_port *ap = qc->ap;
  2022. void __iomem *port_mmio = mv_ap_base(ap);
  2023. struct mv_port_priv *pp = ap->private_data;
  2024. u32 in_index;
  2025. unsigned int port_irqs;
  2026. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
  2027. switch (qc->tf.protocol) {
  2028. case ATA_PROT_DMA:
  2029. if (qc->tf.command == ATA_CMD_DSM) {
  2030. if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
  2031. return AC_ERR_OTHER;
  2032. break; /* use bmdma for this */
  2033. }
  2034. /* fall thru */
  2035. case ATA_PROT_NCQ:
  2036. mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
  2037. pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2038. in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  2039. /* Write the request in pointer to kick the EDMA to life */
  2040. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
  2041. port_mmio + EDMA_REQ_Q_IN_PTR);
  2042. return 0;
  2043. case ATA_PROT_PIO:
  2044. /*
  2045. * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
  2046. *
  2047. * Someday, we might implement special polling workarounds
  2048. * for these, but it all seems rather unnecessary since we
  2049. * normally use only DMA for commands which transfer more
  2050. * than a single block of data.
  2051. *
  2052. * Much of the time, this could just work regardless.
  2053. * So for now, just log the incident, and allow the attempt.
  2054. */
  2055. if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
  2056. --limit_warnings;
  2057. ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
  2058. ": attempting PIO w/multiple DRQ: "
  2059. "this may fail due to h/w errata\n");
  2060. }
  2061. /* drop through */
  2062. case ATA_PROT_NODATA:
  2063. case ATAPI_PROT_PIO:
  2064. case ATAPI_PROT_NODATA:
  2065. if (ap->flags & ATA_FLAG_PIO_POLLING)
  2066. qc->tf.flags |= ATA_TFLAG_POLLING;
  2067. break;
  2068. }
  2069. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2070. port_irqs = ERR_IRQ; /* mask device interrupt when polling */
  2071. else
  2072. port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
  2073. /*
  2074. * We're about to send a non-EDMA capable command to the
  2075. * port. Turn off EDMA so there won't be problems accessing
  2076. * shadow block, etc registers.
  2077. */
  2078. mv_stop_edma(ap);
  2079. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
  2080. mv_pmp_select(ap, qc->dev->link->pmp);
  2081. if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
  2082. struct mv_host_priv *hpriv = ap->host->private_data;
  2083. /*
  2084. * Workaround for 88SX60x1 FEr SATA#25 (part 2).
  2085. *
  2086. * After any NCQ error, the READ_LOG_EXT command
  2087. * from libata-eh *must* use mv_qc_issue_fis().
  2088. * Otherwise it might fail, due to chip errata.
  2089. *
  2090. * Rather than special-case it, we'll just *always*
  2091. * use this method here for READ_LOG_EXT, making for
  2092. * easier testing.
  2093. */
  2094. if (IS_GEN_II(hpriv))
  2095. return mv_qc_issue_fis(qc);
  2096. }
  2097. return ata_bmdma_qc_issue(qc);
  2098. }
  2099. static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
  2100. {
  2101. struct mv_port_priv *pp = ap->private_data;
  2102. struct ata_queued_cmd *qc;
  2103. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  2104. return NULL;
  2105. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2106. if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
  2107. return qc;
  2108. return NULL;
  2109. }
  2110. static void mv_pmp_error_handler(struct ata_port *ap)
  2111. {
  2112. unsigned int pmp, pmp_map;
  2113. struct mv_port_priv *pp = ap->private_data;
  2114. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
  2115. /*
  2116. * Perform NCQ error analysis on failed PMPs
  2117. * before we freeze the port entirely.
  2118. *
  2119. * The failed PMPs are marked earlier by mv_pmp_eh_prep().
  2120. */
  2121. pmp_map = pp->delayed_eh_pmp_map;
  2122. pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
  2123. for (pmp = 0; pmp_map != 0; pmp++) {
  2124. unsigned int this_pmp = (1 << pmp);
  2125. if (pmp_map & this_pmp) {
  2126. struct ata_link *link = &ap->pmp_link[pmp];
  2127. pmp_map &= ~this_pmp;
  2128. ata_eh_analyze_ncq_error(link);
  2129. }
  2130. }
  2131. ata_port_freeze(ap);
  2132. }
  2133. sata_pmp_error_handler(ap);
  2134. }
  2135. static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
  2136. {
  2137. void __iomem *port_mmio = mv_ap_base(ap);
  2138. return readl(port_mmio + SATA_TESTCTL) >> 16;
  2139. }
  2140. static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
  2141. {
  2142. struct ata_eh_info *ehi;
  2143. unsigned int pmp;
  2144. /*
  2145. * Initialize EH info for PMPs which saw device errors
  2146. */
  2147. ehi = &ap->link.eh_info;
  2148. for (pmp = 0; pmp_map != 0; pmp++) {
  2149. unsigned int this_pmp = (1 << pmp);
  2150. if (pmp_map & this_pmp) {
  2151. struct ata_link *link = &ap->pmp_link[pmp];
  2152. pmp_map &= ~this_pmp;
  2153. ehi = &link->eh_info;
  2154. ata_ehi_clear_desc(ehi);
  2155. ata_ehi_push_desc(ehi, "dev err");
  2156. ehi->err_mask |= AC_ERR_DEV;
  2157. ehi->action |= ATA_EH_RESET;
  2158. ata_link_abort(link);
  2159. }
  2160. }
  2161. }
  2162. static int mv_req_q_empty(struct ata_port *ap)
  2163. {
  2164. void __iomem *port_mmio = mv_ap_base(ap);
  2165. u32 in_ptr, out_ptr;
  2166. in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
  2167. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2168. out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
  2169. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2170. return (in_ptr == out_ptr); /* 1 == queue_is_empty */
  2171. }
  2172. static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
  2173. {
  2174. struct mv_port_priv *pp = ap->private_data;
  2175. int failed_links;
  2176. unsigned int old_map, new_map;
  2177. /*
  2178. * Device error during FBS+NCQ operation:
  2179. *
  2180. * Set a port flag to prevent further I/O being enqueued.
  2181. * Leave the EDMA running to drain outstanding commands from this port.
  2182. * Perform the post-mortem/EH only when all responses are complete.
  2183. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
  2184. */
  2185. if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
  2186. pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
  2187. pp->delayed_eh_pmp_map = 0;
  2188. }
  2189. old_map = pp->delayed_eh_pmp_map;
  2190. new_map = old_map | mv_get_err_pmp_map(ap);
  2191. if (old_map != new_map) {
  2192. pp->delayed_eh_pmp_map = new_map;
  2193. mv_pmp_eh_prep(ap, new_map & ~old_map);
  2194. }
  2195. failed_links = hweight16(new_map);
  2196. ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
  2197. "failed_links=%d nr_active_links=%d\n",
  2198. __func__, pp->delayed_eh_pmp_map,
  2199. ap->qc_active, failed_links,
  2200. ap->nr_active_links);
  2201. if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
  2202. mv_process_crpb_entries(ap, pp);
  2203. mv_stop_edma(ap);
  2204. mv_eh_freeze(ap);
  2205. ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
  2206. return 1; /* handled */
  2207. }
  2208. ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
  2209. return 1; /* handled */
  2210. }
  2211. static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
  2212. {
  2213. /*
  2214. * Possible future enhancement:
  2215. *
  2216. * FBS+non-NCQ operation is not yet implemented.
  2217. * See related notes in mv_edma_cfg().
  2218. *
  2219. * Device error during FBS+non-NCQ operation:
  2220. *
  2221. * We need to snapshot the shadow registers for each failed command.
  2222. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
  2223. */
  2224. return 0; /* not handled */
  2225. }
  2226. static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
  2227. {
  2228. struct mv_port_priv *pp = ap->private_data;
  2229. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  2230. return 0; /* EDMA was not active: not handled */
  2231. if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
  2232. return 0; /* FBS was not active: not handled */
  2233. if (!(edma_err_cause & EDMA_ERR_DEV))
  2234. return 0; /* non DEV error: not handled */
  2235. edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
  2236. if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
  2237. return 0; /* other problems: not handled */
  2238. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
  2239. /*
  2240. * EDMA should NOT have self-disabled for this case.
  2241. * If it did, then something is wrong elsewhere,
  2242. * and we cannot handle it here.
  2243. */
  2244. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2245. ata_port_printk(ap, KERN_WARNING,
  2246. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2247. __func__, edma_err_cause, pp->pp_flags);
  2248. return 0; /* not handled */
  2249. }
  2250. return mv_handle_fbs_ncq_dev_err(ap);
  2251. } else {
  2252. /*
  2253. * EDMA should have self-disabled for this case.
  2254. * If it did not, then something is wrong elsewhere,
  2255. * and we cannot handle it here.
  2256. */
  2257. if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
  2258. ata_port_printk(ap, KERN_WARNING,
  2259. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2260. __func__, edma_err_cause, pp->pp_flags);
  2261. return 0; /* not handled */
  2262. }
  2263. return mv_handle_fbs_non_ncq_dev_err(ap);
  2264. }
  2265. return 0; /* not handled */
  2266. }
  2267. static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
  2268. {
  2269. struct ata_eh_info *ehi = &ap->link.eh_info;
  2270. char *when = "idle";
  2271. ata_ehi_clear_desc(ehi);
  2272. if (edma_was_enabled) {
  2273. when = "EDMA enabled";
  2274. } else {
  2275. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2276. if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
  2277. when = "polling";
  2278. }
  2279. ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
  2280. ehi->err_mask |= AC_ERR_OTHER;
  2281. ehi->action |= ATA_EH_RESET;
  2282. ata_port_freeze(ap);
  2283. }
  2284. /**
  2285. * mv_err_intr - Handle error interrupts on the port
  2286. * @ap: ATA channel to manipulate
  2287. *
  2288. * Most cases require a full reset of the chip's state machine,
  2289. * which also performs a COMRESET.
  2290. * Also, if the port disabled DMA, update our cached copy to match.
  2291. *
  2292. * LOCKING:
  2293. * Inherited from caller.
  2294. */
  2295. static void mv_err_intr(struct ata_port *ap)
  2296. {
  2297. void __iomem *port_mmio = mv_ap_base(ap);
  2298. u32 edma_err_cause, eh_freeze_mask, serr = 0;
  2299. u32 fis_cause = 0;
  2300. struct mv_port_priv *pp = ap->private_data;
  2301. struct mv_host_priv *hpriv = ap->host->private_data;
  2302. unsigned int action = 0, err_mask = 0;
  2303. struct ata_eh_info *ehi = &ap->link.eh_info;
  2304. struct ata_queued_cmd *qc;
  2305. int abort = 0;
  2306. /*
  2307. * Read and clear the SError and err_cause bits.
  2308. * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
  2309. * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
  2310. */
  2311. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  2312. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  2313. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
  2314. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2315. fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
  2316. writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
  2317. }
  2318. writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
  2319. if (edma_err_cause & EDMA_ERR_DEV) {
  2320. /*
  2321. * Device errors during FIS-based switching operation
  2322. * require special handling.
  2323. */
  2324. if (mv_handle_dev_err(ap, edma_err_cause))
  2325. return;
  2326. }
  2327. qc = mv_get_active_qc(ap);
  2328. ata_ehi_clear_desc(ehi);
  2329. ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
  2330. edma_err_cause, pp->pp_flags);
  2331. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2332. ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
  2333. if (fis_cause & FIS_IRQ_CAUSE_AN) {
  2334. u32 ec = edma_err_cause &
  2335. ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
  2336. sata_async_notification(ap);
  2337. if (!ec)
  2338. return; /* Just an AN; no need for the nukes */
  2339. ata_ehi_push_desc(ehi, "SDB notify");
  2340. }
  2341. }
  2342. /*
  2343. * All generations share these EDMA error cause bits:
  2344. */
  2345. if (edma_err_cause & EDMA_ERR_DEV) {
  2346. err_mask |= AC_ERR_DEV;
  2347. action |= ATA_EH_RESET;
  2348. ata_ehi_push_desc(ehi, "dev error");
  2349. }
  2350. if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  2351. EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
  2352. EDMA_ERR_INTRL_PAR)) {
  2353. err_mask |= AC_ERR_ATA_BUS;
  2354. action |= ATA_EH_RESET;
  2355. ata_ehi_push_desc(ehi, "parity error");
  2356. }
  2357. if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
  2358. ata_ehi_hotplugged(ehi);
  2359. ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
  2360. "dev disconnect" : "dev connect");
  2361. action |= ATA_EH_RESET;
  2362. }
  2363. /*
  2364. * Gen-I has a different SELF_DIS bit,
  2365. * different FREEZE bits, and no SERR bit:
  2366. */
  2367. if (IS_GEN_I(hpriv)) {
  2368. eh_freeze_mask = EDMA_EH_FREEZE_5;
  2369. if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
  2370. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2371. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2372. }
  2373. } else {
  2374. eh_freeze_mask = EDMA_EH_FREEZE;
  2375. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2376. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2377. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2378. }
  2379. if (edma_err_cause & EDMA_ERR_SERR) {
  2380. ata_ehi_push_desc(ehi, "SError=%08x", serr);
  2381. err_mask |= AC_ERR_ATA_BUS;
  2382. action |= ATA_EH_RESET;
  2383. }
  2384. }
  2385. if (!err_mask) {
  2386. err_mask = AC_ERR_OTHER;
  2387. action |= ATA_EH_RESET;
  2388. }
  2389. ehi->serror |= serr;
  2390. ehi->action |= action;
  2391. if (qc)
  2392. qc->err_mask |= err_mask;
  2393. else
  2394. ehi->err_mask |= err_mask;
  2395. if (err_mask == AC_ERR_DEV) {
  2396. /*
  2397. * Cannot do ata_port_freeze() here,
  2398. * because it would kill PIO access,
  2399. * which is needed for further diagnosis.
  2400. */
  2401. mv_eh_freeze(ap);
  2402. abort = 1;
  2403. } else if (edma_err_cause & eh_freeze_mask) {
  2404. /*
  2405. * Note to self: ata_port_freeze() calls ata_port_abort()
  2406. */
  2407. ata_port_freeze(ap);
  2408. } else {
  2409. abort = 1;
  2410. }
  2411. if (abort) {
  2412. if (qc)
  2413. ata_link_abort(qc->dev->link);
  2414. else
  2415. ata_port_abort(ap);
  2416. }
  2417. }
  2418. static bool mv_process_crpb_response(struct ata_port *ap,
  2419. struct mv_crpb *response, unsigned int tag, int ncq_enabled)
  2420. {
  2421. u8 ata_status;
  2422. u16 edma_status = le16_to_cpu(response->flags);
  2423. /*
  2424. * edma_status from a response queue entry:
  2425. * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
  2426. * MSB is saved ATA status from command completion.
  2427. */
  2428. if (!ncq_enabled) {
  2429. u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
  2430. if (err_cause) {
  2431. /*
  2432. * Error will be seen/handled by
  2433. * mv_err_intr(). So do nothing at all here.
  2434. */
  2435. return false;
  2436. }
  2437. }
  2438. ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
  2439. if (!ac_err_mask(ata_status))
  2440. return true;
  2441. /* else: leave it for mv_err_intr() */
  2442. return false;
  2443. }
  2444. static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
  2445. {
  2446. void __iomem *port_mmio = mv_ap_base(ap);
  2447. struct mv_host_priv *hpriv = ap->host->private_data;
  2448. u32 in_index;
  2449. bool work_done = false;
  2450. u32 done_mask = 0;
  2451. int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
  2452. /* Get the hardware queue position index */
  2453. in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
  2454. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2455. /* Process new responses from since the last time we looked */
  2456. while (in_index != pp->resp_idx) {
  2457. unsigned int tag;
  2458. struct mv_crpb *response = &pp->crpb[pp->resp_idx];
  2459. pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2460. if (IS_GEN_I(hpriv)) {
  2461. /* 50xx: no NCQ, only one command active at a time */
  2462. tag = ap->link.active_tag;
  2463. } else {
  2464. /* Gen II/IIE: get command tag from CRPB entry */
  2465. tag = le16_to_cpu(response->id) & 0x1f;
  2466. }
  2467. if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
  2468. done_mask |= 1 << tag;
  2469. work_done = true;
  2470. }
  2471. if (work_done) {
  2472. ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
  2473. /* Update the software queue position index in hardware */
  2474. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
  2475. (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
  2476. port_mmio + EDMA_RSP_Q_OUT_PTR);
  2477. }
  2478. }
  2479. static void mv_port_intr(struct ata_port *ap, u32 port_cause)
  2480. {
  2481. struct mv_port_priv *pp;
  2482. int edma_was_enabled;
  2483. /*
  2484. * Grab a snapshot of the EDMA_EN flag setting,
  2485. * so that we have a consistent view for this port,
  2486. * even if something we call of our routines changes it.
  2487. */
  2488. pp = ap->private_data;
  2489. edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
  2490. /*
  2491. * Process completed CRPB response(s) before other events.
  2492. */
  2493. if (edma_was_enabled && (port_cause & DONE_IRQ)) {
  2494. mv_process_crpb_entries(ap, pp);
  2495. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  2496. mv_handle_fbs_ncq_dev_err(ap);
  2497. }
  2498. /*
  2499. * Handle chip-reported errors, or continue on to handle PIO.
  2500. */
  2501. if (unlikely(port_cause & ERR_IRQ)) {
  2502. mv_err_intr(ap);
  2503. } else if (!edma_was_enabled) {
  2504. struct ata_queued_cmd *qc = mv_get_active_qc(ap);
  2505. if (qc)
  2506. ata_bmdma_port_intr(ap, qc);
  2507. else
  2508. mv_unexpected_intr(ap, edma_was_enabled);
  2509. }
  2510. }
  2511. /**
  2512. * mv_host_intr - Handle all interrupts on the given host controller
  2513. * @host: host specific structure
  2514. * @main_irq_cause: Main interrupt cause register for the chip.
  2515. *
  2516. * LOCKING:
  2517. * Inherited from caller.
  2518. */
  2519. static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
  2520. {
  2521. struct mv_host_priv *hpriv = host->private_data;
  2522. void __iomem *mmio = hpriv->base, *hc_mmio;
  2523. unsigned int handled = 0, port;
  2524. /* If asserted, clear the "all ports" IRQ coalescing bit */
  2525. if (main_irq_cause & ALL_PORTS_COAL_DONE)
  2526. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  2527. for (port = 0; port < hpriv->n_ports; port++) {
  2528. struct ata_port *ap = host->ports[port];
  2529. unsigned int p, shift, hardport, port_cause;
  2530. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  2531. /*
  2532. * Each hc within the host has its own hc_irq_cause register,
  2533. * where the interrupting ports bits get ack'd.
  2534. */
  2535. if (hardport == 0) { /* first port on this hc ? */
  2536. u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
  2537. u32 port_mask, ack_irqs;
  2538. /*
  2539. * Skip this entire hc if nothing pending for any ports
  2540. */
  2541. if (!hc_cause) {
  2542. port += MV_PORTS_PER_HC - 1;
  2543. continue;
  2544. }
  2545. /*
  2546. * We don't need/want to read the hc_irq_cause register,
  2547. * because doing so hurts performance, and
  2548. * main_irq_cause already gives us everything we need.
  2549. *
  2550. * But we do have to *write* to the hc_irq_cause to ack
  2551. * the ports that we are handling this time through.
  2552. *
  2553. * This requires that we create a bitmap for those
  2554. * ports which interrupted us, and use that bitmap
  2555. * to ack (only) those ports via hc_irq_cause.
  2556. */
  2557. ack_irqs = 0;
  2558. if (hc_cause & PORTS_0_3_COAL_DONE)
  2559. ack_irqs = HC_COAL_IRQ;
  2560. for (p = 0; p < MV_PORTS_PER_HC; ++p) {
  2561. if ((port + p) >= hpriv->n_ports)
  2562. break;
  2563. port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
  2564. if (hc_cause & port_mask)
  2565. ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
  2566. }
  2567. hc_mmio = mv_hc_base_from_port(mmio, port);
  2568. writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
  2569. handled = 1;
  2570. }
  2571. /*
  2572. * Handle interrupts signalled for this port:
  2573. */
  2574. port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
  2575. if (port_cause)
  2576. mv_port_intr(ap, port_cause);
  2577. }
  2578. return handled;
  2579. }
  2580. static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
  2581. {
  2582. struct mv_host_priv *hpriv = host->private_data;
  2583. struct ata_port *ap;
  2584. struct ata_queued_cmd *qc;
  2585. struct ata_eh_info *ehi;
  2586. unsigned int i, err_mask, printed = 0;
  2587. u32 err_cause;
  2588. err_cause = readl(mmio + hpriv->irq_cause_offset);
  2589. dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
  2590. err_cause);
  2591. DPRINTK("All regs @ PCI error\n");
  2592. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  2593. writelfl(0, mmio + hpriv->irq_cause_offset);
  2594. for (i = 0; i < host->n_ports; i++) {
  2595. ap = host->ports[i];
  2596. if (!ata_link_offline(&ap->link)) {
  2597. ehi = &ap->link.eh_info;
  2598. ata_ehi_clear_desc(ehi);
  2599. if (!printed++)
  2600. ata_ehi_push_desc(ehi,
  2601. "PCI err cause 0x%08x", err_cause);
  2602. err_mask = AC_ERR_HOST_BUS;
  2603. ehi->action = ATA_EH_RESET;
  2604. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2605. if (qc)
  2606. qc->err_mask |= err_mask;
  2607. else
  2608. ehi->err_mask |= err_mask;
  2609. ata_port_freeze(ap);
  2610. }
  2611. }
  2612. return 1; /* handled */
  2613. }
  2614. /**
  2615. * mv_interrupt - Main interrupt event handler
  2616. * @irq: unused
  2617. * @dev_instance: private data; in this case the host structure
  2618. *
  2619. * Read the read only register to determine if any host
  2620. * controllers have pending interrupts. If so, call lower level
  2621. * routine to handle. Also check for PCI errors which are only
  2622. * reported here.
  2623. *
  2624. * LOCKING:
  2625. * This routine holds the host lock while processing pending
  2626. * interrupts.
  2627. */
  2628. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  2629. {
  2630. struct ata_host *host = dev_instance;
  2631. struct mv_host_priv *hpriv = host->private_data;
  2632. unsigned int handled = 0;
  2633. int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
  2634. u32 main_irq_cause, pending_irqs;
  2635. spin_lock(&host->lock);
  2636. /* for MSI: block new interrupts while in here */
  2637. if (using_msi)
  2638. mv_write_main_irq_mask(0, hpriv);
  2639. main_irq_cause = readl(hpriv->main_irq_cause_addr);
  2640. pending_irqs = main_irq_cause & hpriv->main_irq_mask;
  2641. /*
  2642. * Deal with cases where we either have nothing pending, or have read
  2643. * a bogus register value which can indicate HW removal or PCI fault.
  2644. */
  2645. if (pending_irqs && main_irq_cause != 0xffffffffU) {
  2646. if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
  2647. handled = mv_pci_error(host, hpriv->base);
  2648. else
  2649. handled = mv_host_intr(host, pending_irqs);
  2650. }
  2651. /* for MSI: unmask; interrupt cause bits will retrigger now */
  2652. if (using_msi)
  2653. mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
  2654. spin_unlock(&host->lock);
  2655. return IRQ_RETVAL(handled);
  2656. }
  2657. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  2658. {
  2659. unsigned int ofs;
  2660. switch (sc_reg_in) {
  2661. case SCR_STATUS:
  2662. case SCR_ERROR:
  2663. case SCR_CONTROL:
  2664. ofs = sc_reg_in * sizeof(u32);
  2665. break;
  2666. default:
  2667. ofs = 0xffffffffU;
  2668. break;
  2669. }
  2670. return ofs;
  2671. }
  2672. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  2673. {
  2674. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2675. void __iomem *mmio = hpriv->base;
  2676. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2677. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2678. if (ofs != 0xffffffffU) {
  2679. *val = readl(addr + ofs);
  2680. return 0;
  2681. } else
  2682. return -EINVAL;
  2683. }
  2684. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  2685. {
  2686. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2687. void __iomem *mmio = hpriv->base;
  2688. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2689. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2690. if (ofs != 0xffffffffU) {
  2691. writelfl(val, addr + ofs);
  2692. return 0;
  2693. } else
  2694. return -EINVAL;
  2695. }
  2696. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
  2697. {
  2698. struct pci_dev *pdev = to_pci_dev(host->dev);
  2699. int early_5080;
  2700. early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
  2701. if (!early_5080) {
  2702. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2703. tmp |= (1 << 0);
  2704. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2705. }
  2706. mv_reset_pci_bus(host, mmio);
  2707. }
  2708. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2709. {
  2710. writel(0x0fcfffff, mmio + FLASH_CTL);
  2711. }
  2712. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  2713. void __iomem *mmio)
  2714. {
  2715. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  2716. u32 tmp;
  2717. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2718. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  2719. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  2720. }
  2721. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2722. {
  2723. u32 tmp;
  2724. writel(0, mmio + GPIO_PORT_CTL);
  2725. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  2726. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2727. tmp |= ~(1 << 0);
  2728. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2729. }
  2730. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2731. unsigned int port)
  2732. {
  2733. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  2734. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  2735. u32 tmp;
  2736. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  2737. if (fix_apm_sq) {
  2738. tmp = readl(phy_mmio + MV5_LTMODE);
  2739. tmp |= (1 << 19);
  2740. writel(tmp, phy_mmio + MV5_LTMODE);
  2741. tmp = readl(phy_mmio + MV5_PHY_CTL);
  2742. tmp &= ~0x3;
  2743. tmp |= 0x1;
  2744. writel(tmp, phy_mmio + MV5_PHY_CTL);
  2745. }
  2746. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2747. tmp &= ~mask;
  2748. tmp |= hpriv->signal[port].pre;
  2749. tmp |= hpriv->signal[port].amps;
  2750. writel(tmp, phy_mmio + MV5_PHY_MODE);
  2751. }
  2752. #undef ZERO
  2753. #define ZERO(reg) writel(0, port_mmio + (reg))
  2754. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  2755. unsigned int port)
  2756. {
  2757. void __iomem *port_mmio = mv_port_base(mmio, port);
  2758. mv_reset_channel(hpriv, mmio, port);
  2759. ZERO(0x028); /* command */
  2760. writel(0x11f, port_mmio + EDMA_CFG);
  2761. ZERO(0x004); /* timer */
  2762. ZERO(0x008); /* irq err cause */
  2763. ZERO(0x00c); /* irq err mask */
  2764. ZERO(0x010); /* rq bah */
  2765. ZERO(0x014); /* rq inp */
  2766. ZERO(0x018); /* rq outp */
  2767. ZERO(0x01c); /* respq bah */
  2768. ZERO(0x024); /* respq outp */
  2769. ZERO(0x020); /* respq inp */
  2770. ZERO(0x02c); /* test control */
  2771. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2772. }
  2773. #undef ZERO
  2774. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2775. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2776. unsigned int hc)
  2777. {
  2778. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2779. u32 tmp;
  2780. ZERO(0x00c);
  2781. ZERO(0x010);
  2782. ZERO(0x014);
  2783. ZERO(0x018);
  2784. tmp = readl(hc_mmio + 0x20);
  2785. tmp &= 0x1c1c1c1c;
  2786. tmp |= 0x03030303;
  2787. writel(tmp, hc_mmio + 0x20);
  2788. }
  2789. #undef ZERO
  2790. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2791. unsigned int n_hc)
  2792. {
  2793. unsigned int hc, port;
  2794. for (hc = 0; hc < n_hc; hc++) {
  2795. for (port = 0; port < MV_PORTS_PER_HC; port++)
  2796. mv5_reset_hc_port(hpriv, mmio,
  2797. (hc * MV_PORTS_PER_HC) + port);
  2798. mv5_reset_one_hc(hpriv, mmio, hc);
  2799. }
  2800. return 0;
  2801. }
  2802. #undef ZERO
  2803. #define ZERO(reg) writel(0, mmio + (reg))
  2804. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
  2805. {
  2806. struct mv_host_priv *hpriv = host->private_data;
  2807. u32 tmp;
  2808. tmp = readl(mmio + MV_PCI_MODE);
  2809. tmp &= 0xff00ffff;
  2810. writel(tmp, mmio + MV_PCI_MODE);
  2811. ZERO(MV_PCI_DISC_TIMER);
  2812. ZERO(MV_PCI_MSI_TRIGGER);
  2813. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  2814. ZERO(MV_PCI_SERR_MASK);
  2815. ZERO(hpriv->irq_cause_offset);
  2816. ZERO(hpriv->irq_mask_offset);
  2817. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  2818. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  2819. ZERO(MV_PCI_ERR_ATTRIBUTE);
  2820. ZERO(MV_PCI_ERR_COMMAND);
  2821. }
  2822. #undef ZERO
  2823. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2824. {
  2825. u32 tmp;
  2826. mv5_reset_flash(hpriv, mmio);
  2827. tmp = readl(mmio + GPIO_PORT_CTL);
  2828. tmp &= 0x3;
  2829. tmp |= (1 << 5) | (1 << 6);
  2830. writel(tmp, mmio + GPIO_PORT_CTL);
  2831. }
  2832. /**
  2833. * mv6_reset_hc - Perform the 6xxx global soft reset
  2834. * @mmio: base address of the HBA
  2835. *
  2836. * This routine only applies to 6xxx parts.
  2837. *
  2838. * LOCKING:
  2839. * Inherited from caller.
  2840. */
  2841. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2842. unsigned int n_hc)
  2843. {
  2844. void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
  2845. int i, rc = 0;
  2846. u32 t;
  2847. /* Following procedure defined in PCI "main command and status
  2848. * register" table.
  2849. */
  2850. t = readl(reg);
  2851. writel(t | STOP_PCI_MASTER, reg);
  2852. for (i = 0; i < 1000; i++) {
  2853. udelay(1);
  2854. t = readl(reg);
  2855. if (PCI_MASTER_EMPTY & t)
  2856. break;
  2857. }
  2858. if (!(PCI_MASTER_EMPTY & t)) {
  2859. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  2860. rc = 1;
  2861. goto done;
  2862. }
  2863. /* set reset */
  2864. i = 5;
  2865. do {
  2866. writel(t | GLOB_SFT_RST, reg);
  2867. t = readl(reg);
  2868. udelay(1);
  2869. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  2870. if (!(GLOB_SFT_RST & t)) {
  2871. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  2872. rc = 1;
  2873. goto done;
  2874. }
  2875. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  2876. i = 5;
  2877. do {
  2878. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  2879. t = readl(reg);
  2880. udelay(1);
  2881. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  2882. if (GLOB_SFT_RST & t) {
  2883. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  2884. rc = 1;
  2885. }
  2886. done:
  2887. return rc;
  2888. }
  2889. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  2890. void __iomem *mmio)
  2891. {
  2892. void __iomem *port_mmio;
  2893. u32 tmp;
  2894. tmp = readl(mmio + RESET_CFG);
  2895. if ((tmp & (1 << 0)) == 0) {
  2896. hpriv->signal[idx].amps = 0x7 << 8;
  2897. hpriv->signal[idx].pre = 0x1 << 5;
  2898. return;
  2899. }
  2900. port_mmio = mv_port_base(mmio, idx);
  2901. tmp = readl(port_mmio + PHY_MODE2);
  2902. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2903. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2904. }
  2905. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2906. {
  2907. writel(0x00000060, mmio + GPIO_PORT_CTL);
  2908. }
  2909. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2910. unsigned int port)
  2911. {
  2912. void __iomem *port_mmio = mv_port_base(mmio, port);
  2913. u32 hp_flags = hpriv->hp_flags;
  2914. int fix_phy_mode2 =
  2915. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2916. int fix_phy_mode4 =
  2917. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2918. u32 m2, m3;
  2919. if (fix_phy_mode2) {
  2920. m2 = readl(port_mmio + PHY_MODE2);
  2921. m2 &= ~(1 << 16);
  2922. m2 |= (1 << 31);
  2923. writel(m2, port_mmio + PHY_MODE2);
  2924. udelay(200);
  2925. m2 = readl(port_mmio + PHY_MODE2);
  2926. m2 &= ~((1 << 16) | (1 << 31));
  2927. writel(m2, port_mmio + PHY_MODE2);
  2928. udelay(200);
  2929. }
  2930. /*
  2931. * Gen-II/IIe PHY_MODE3 errata RM#2:
  2932. * Achieves better receiver noise performance than the h/w default:
  2933. */
  2934. m3 = readl(port_mmio + PHY_MODE3);
  2935. m3 = (m3 & 0x1f) | (0x5555601 << 5);
  2936. /* Guideline 88F5182 (GL# SATA-S11) */
  2937. if (IS_SOC(hpriv))
  2938. m3 &= ~0x1c;
  2939. if (fix_phy_mode4) {
  2940. u32 m4 = readl(port_mmio + PHY_MODE4);
  2941. /*
  2942. * Enforce reserved-bit restrictions on GenIIe devices only.
  2943. * For earlier chipsets, force only the internal config field
  2944. * (workaround for errata FEr SATA#10 part 1).
  2945. */
  2946. if (IS_GEN_IIE(hpriv))
  2947. m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
  2948. else
  2949. m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
  2950. writel(m4, port_mmio + PHY_MODE4);
  2951. }
  2952. /*
  2953. * Workaround for 60x1-B2 errata SATA#13:
  2954. * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
  2955. * so we must always rewrite PHY_MODE3 after PHY_MODE4.
  2956. * Or ensure we use writelfl() when writing PHY_MODE4.
  2957. */
  2958. writel(m3, port_mmio + PHY_MODE3);
  2959. /* Revert values of pre-emphasis and signal amps to the saved ones */
  2960. m2 = readl(port_mmio + PHY_MODE2);
  2961. m2 &= ~MV_M2_PREAMP_MASK;
  2962. m2 |= hpriv->signal[port].amps;
  2963. m2 |= hpriv->signal[port].pre;
  2964. m2 &= ~(1 << 16);
  2965. /* according to mvSata 3.6.1, some IIE values are fixed */
  2966. if (IS_GEN_IIE(hpriv)) {
  2967. m2 &= ~0xC30FF01F;
  2968. m2 |= 0x0000900F;
  2969. }
  2970. writel(m2, port_mmio + PHY_MODE2);
  2971. }
  2972. /* TODO: use the generic LED interface to configure the SATA Presence */
  2973. /* & Acitivy LEDs on the board */
  2974. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  2975. void __iomem *mmio)
  2976. {
  2977. return;
  2978. }
  2979. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  2980. void __iomem *mmio)
  2981. {
  2982. void __iomem *port_mmio;
  2983. u32 tmp;
  2984. port_mmio = mv_port_base(mmio, idx);
  2985. tmp = readl(port_mmio + PHY_MODE2);
  2986. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2987. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2988. }
  2989. #undef ZERO
  2990. #define ZERO(reg) writel(0, port_mmio + (reg))
  2991. static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
  2992. void __iomem *mmio, unsigned int port)
  2993. {
  2994. void __iomem *port_mmio = mv_port_base(mmio, port);
  2995. mv_reset_channel(hpriv, mmio, port);
  2996. ZERO(0x028); /* command */
  2997. writel(0x101f, port_mmio + EDMA_CFG);
  2998. ZERO(0x004); /* timer */
  2999. ZERO(0x008); /* irq err cause */
  3000. ZERO(0x00c); /* irq err mask */
  3001. ZERO(0x010); /* rq bah */
  3002. ZERO(0x014); /* rq inp */
  3003. ZERO(0x018); /* rq outp */
  3004. ZERO(0x01c); /* respq bah */
  3005. ZERO(0x024); /* respq outp */
  3006. ZERO(0x020); /* respq inp */
  3007. ZERO(0x02c); /* test control */
  3008. writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
  3009. }
  3010. #undef ZERO
  3011. #define ZERO(reg) writel(0, hc_mmio + (reg))
  3012. static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
  3013. void __iomem *mmio)
  3014. {
  3015. void __iomem *hc_mmio = mv_hc_base(mmio, 0);
  3016. ZERO(0x00c);
  3017. ZERO(0x010);
  3018. ZERO(0x014);
  3019. }
  3020. #undef ZERO
  3021. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  3022. void __iomem *mmio, unsigned int n_hc)
  3023. {
  3024. unsigned int port;
  3025. for (port = 0; port < hpriv->n_ports; port++)
  3026. mv_soc_reset_hc_port(hpriv, mmio, port);
  3027. mv_soc_reset_one_hc(hpriv, mmio);
  3028. return 0;
  3029. }
  3030. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  3031. void __iomem *mmio)
  3032. {
  3033. return;
  3034. }
  3035. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
  3036. {
  3037. return;
  3038. }
  3039. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  3040. void __iomem *mmio, unsigned int port)
  3041. {
  3042. void __iomem *port_mmio = mv_port_base(mmio, port);
  3043. u32 reg;
  3044. reg = readl(port_mmio + PHY_MODE3);
  3045. reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
  3046. reg |= (0x1 << 27);
  3047. reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
  3048. reg |= (0x1 << 29);
  3049. writel(reg, port_mmio + PHY_MODE3);
  3050. reg = readl(port_mmio + PHY_MODE4);
  3051. reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
  3052. reg |= (0x1 << 16);
  3053. writel(reg, port_mmio + PHY_MODE4);
  3054. reg = readl(port_mmio + PHY_MODE9_GEN2);
  3055. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3056. reg |= 0x8;
  3057. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3058. writel(reg, port_mmio + PHY_MODE9_GEN2);
  3059. reg = readl(port_mmio + PHY_MODE9_GEN1);
  3060. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3061. reg |= 0x8;
  3062. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3063. writel(reg, port_mmio + PHY_MODE9_GEN1);
  3064. }
  3065. /**
  3066. * soc_is_65 - check if the soc is 65 nano device
  3067. *
  3068. * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
  3069. * register, this register should contain non-zero value and it exists only
  3070. * in the 65 nano devices, when reading it from older devices we get 0.
  3071. */
  3072. static bool soc_is_65n(struct mv_host_priv *hpriv)
  3073. {
  3074. void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
  3075. if (readl(port0_mmio + PHYCFG_OFS))
  3076. return true;
  3077. return false;
  3078. }
  3079. static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
  3080. {
  3081. u32 ifcfg = readl(port_mmio + SATA_IFCFG);
  3082. ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
  3083. if (want_gen2i)
  3084. ifcfg |= (1 << 7); /* enable gen2i speed */
  3085. writelfl(ifcfg, port_mmio + SATA_IFCFG);
  3086. }
  3087. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  3088. unsigned int port_no)
  3089. {
  3090. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  3091. /*
  3092. * The datasheet warns against setting EDMA_RESET when EDMA is active
  3093. * (but doesn't say what the problem might be). So we first try
  3094. * to disable the EDMA engine before doing the EDMA_RESET operation.
  3095. */
  3096. mv_stop_edma_engine(port_mmio);
  3097. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3098. if (!IS_GEN_I(hpriv)) {
  3099. /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
  3100. mv_setup_ifcfg(port_mmio, 1);
  3101. }
  3102. /*
  3103. * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
  3104. * link, and physical layers. It resets all SATA interface registers
  3105. * (except for SATA_IFCFG), and issues a COMRESET to the dev.
  3106. */
  3107. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3108. udelay(25); /* allow reset propagation */
  3109. writelfl(0, port_mmio + EDMA_CMD);
  3110. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  3111. if (IS_GEN_I(hpriv))
  3112. mdelay(1);
  3113. }
  3114. static void mv_pmp_select(struct ata_port *ap, int pmp)
  3115. {
  3116. if (sata_pmp_supported(ap)) {
  3117. void __iomem *port_mmio = mv_ap_base(ap);
  3118. u32 reg = readl(port_mmio + SATA_IFCTL);
  3119. int old = reg & 0xf;
  3120. if (old != pmp) {
  3121. reg = (reg & ~0xf) | pmp;
  3122. writelfl(reg, port_mmio + SATA_IFCTL);
  3123. }
  3124. }
  3125. }
  3126. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  3127. unsigned long deadline)
  3128. {
  3129. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3130. return sata_std_hardreset(link, class, deadline);
  3131. }
  3132. static int mv_softreset(struct ata_link *link, unsigned int *class,
  3133. unsigned long deadline)
  3134. {
  3135. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3136. return ata_sff_softreset(link, class, deadline);
  3137. }
  3138. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  3139. unsigned long deadline)
  3140. {
  3141. struct ata_port *ap = link->ap;
  3142. struct mv_host_priv *hpriv = ap->host->private_data;
  3143. struct mv_port_priv *pp = ap->private_data;
  3144. void __iomem *mmio = hpriv->base;
  3145. int rc, attempts = 0, extra = 0;
  3146. u32 sstatus;
  3147. bool online;
  3148. mv_reset_channel(hpriv, mmio, ap->port_no);
  3149. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  3150. pp->pp_flags &=
  3151. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  3152. /* Workaround for errata FEr SATA#10 (part 2) */
  3153. do {
  3154. const unsigned long *timing =
  3155. sata_ehc_deb_timing(&link->eh_context);
  3156. rc = sata_link_hardreset(link, timing, deadline + extra,
  3157. &online, NULL);
  3158. rc = online ? -EAGAIN : rc;
  3159. if (rc)
  3160. return rc;
  3161. sata_scr_read(link, SCR_STATUS, &sstatus);
  3162. if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
  3163. /* Force 1.5gb/s link speed and try again */
  3164. mv_setup_ifcfg(mv_ap_base(ap), 0);
  3165. if (time_after(jiffies + HZ, deadline))
  3166. extra = HZ; /* only extend it once, max */
  3167. }
  3168. } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
  3169. mv_save_cached_regs(ap);
  3170. mv_edma_cfg(ap, 0, 0);
  3171. return rc;
  3172. }
  3173. static void mv_eh_freeze(struct ata_port *ap)
  3174. {
  3175. mv_stop_edma(ap);
  3176. mv_enable_port_irqs(ap, 0);
  3177. }
  3178. static void mv_eh_thaw(struct ata_port *ap)
  3179. {
  3180. struct mv_host_priv *hpriv = ap->host->private_data;
  3181. unsigned int port = ap->port_no;
  3182. unsigned int hardport = mv_hardport_from_port(port);
  3183. void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
  3184. void __iomem *port_mmio = mv_ap_base(ap);
  3185. u32 hc_irq_cause;
  3186. /* clear EDMA errors on this port */
  3187. writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3188. /* clear pending irq events */
  3189. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  3190. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  3191. mv_enable_port_irqs(ap, ERR_IRQ);
  3192. }
  3193. /**
  3194. * mv_port_init - Perform some early initialization on a single port.
  3195. * @port: libata data structure storing shadow register addresses
  3196. * @port_mmio: base address of the port
  3197. *
  3198. * Initialize shadow register mmio addresses, clear outstanding
  3199. * interrupts on the port, and unmask interrupts for the future
  3200. * start of the port.
  3201. *
  3202. * LOCKING:
  3203. * Inherited from caller.
  3204. */
  3205. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  3206. {
  3207. void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
  3208. /* PIO related setup
  3209. */
  3210. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  3211. port->error_addr =
  3212. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  3213. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  3214. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  3215. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  3216. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  3217. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  3218. port->status_addr =
  3219. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  3220. /* special case: control/altstatus doesn't have ATA_REG_ address */
  3221. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
  3222. /* Clear any currently outstanding port interrupt conditions */
  3223. serr = port_mmio + mv_scr_offset(SCR_ERROR);
  3224. writelfl(readl(serr), serr);
  3225. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3226. /* unmask all non-transient EDMA error interrupts */
  3227. writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
  3228. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  3229. readl(port_mmio + EDMA_CFG),
  3230. readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
  3231. readl(port_mmio + EDMA_ERR_IRQ_MASK));
  3232. }
  3233. static unsigned int mv_in_pcix_mode(struct ata_host *host)
  3234. {
  3235. struct mv_host_priv *hpriv = host->private_data;
  3236. void __iomem *mmio = hpriv->base;
  3237. u32 reg;
  3238. if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
  3239. return 0; /* not PCI-X capable */
  3240. reg = readl(mmio + MV_PCI_MODE);
  3241. if ((reg & MV_PCI_MODE_MASK) == 0)
  3242. return 0; /* conventional PCI mode */
  3243. return 1; /* chip is in PCI-X mode */
  3244. }
  3245. static int mv_pci_cut_through_okay(struct ata_host *host)
  3246. {
  3247. struct mv_host_priv *hpriv = host->private_data;
  3248. void __iomem *mmio = hpriv->base;
  3249. u32 reg;
  3250. if (!mv_in_pcix_mode(host)) {
  3251. reg = readl(mmio + MV_PCI_COMMAND);
  3252. if (reg & MV_PCI_COMMAND_MRDTRIG)
  3253. return 0; /* not okay */
  3254. }
  3255. return 1; /* okay */
  3256. }
  3257. static void mv_60x1b2_errata_pci7(struct ata_host *host)
  3258. {
  3259. struct mv_host_priv *hpriv = host->private_data;
  3260. void __iomem *mmio = hpriv->base;
  3261. /* workaround for 60x1-B2 errata PCI#7 */
  3262. if (mv_in_pcix_mode(host)) {
  3263. u32 reg = readl(mmio + MV_PCI_COMMAND);
  3264. writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
  3265. }
  3266. }
  3267. static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
  3268. {
  3269. struct pci_dev *pdev = to_pci_dev(host->dev);
  3270. struct mv_host_priv *hpriv = host->private_data;
  3271. u32 hp_flags = hpriv->hp_flags;
  3272. switch (board_idx) {
  3273. case chip_5080:
  3274. hpriv->ops = &mv5xxx_ops;
  3275. hp_flags |= MV_HP_GEN_I;
  3276. switch (pdev->revision) {
  3277. case 0x1:
  3278. hp_flags |= MV_HP_ERRATA_50XXB0;
  3279. break;
  3280. case 0x3:
  3281. hp_flags |= MV_HP_ERRATA_50XXB2;
  3282. break;
  3283. default:
  3284. dev_printk(KERN_WARNING, &pdev->dev,
  3285. "Applying 50XXB2 workarounds to unknown rev\n");
  3286. hp_flags |= MV_HP_ERRATA_50XXB2;
  3287. break;
  3288. }
  3289. break;
  3290. case chip_504x:
  3291. case chip_508x:
  3292. hpriv->ops = &mv5xxx_ops;
  3293. hp_flags |= MV_HP_GEN_I;
  3294. switch (pdev->revision) {
  3295. case 0x0:
  3296. hp_flags |= MV_HP_ERRATA_50XXB0;
  3297. break;
  3298. case 0x3:
  3299. hp_flags |= MV_HP_ERRATA_50XXB2;
  3300. break;
  3301. default:
  3302. dev_printk(KERN_WARNING, &pdev->dev,
  3303. "Applying B2 workarounds to unknown rev\n");
  3304. hp_flags |= MV_HP_ERRATA_50XXB2;
  3305. break;
  3306. }
  3307. break;
  3308. case chip_604x:
  3309. case chip_608x:
  3310. hpriv->ops = &mv6xxx_ops;
  3311. hp_flags |= MV_HP_GEN_II;
  3312. switch (pdev->revision) {
  3313. case 0x7:
  3314. mv_60x1b2_errata_pci7(host);
  3315. hp_flags |= MV_HP_ERRATA_60X1B2;
  3316. break;
  3317. case 0x9:
  3318. hp_flags |= MV_HP_ERRATA_60X1C0;
  3319. break;
  3320. default:
  3321. dev_printk(KERN_WARNING, &pdev->dev,
  3322. "Applying B2 workarounds to unknown rev\n");
  3323. hp_flags |= MV_HP_ERRATA_60X1B2;
  3324. break;
  3325. }
  3326. break;
  3327. case chip_7042:
  3328. hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
  3329. if (pdev->vendor == PCI_VENDOR_ID_TTI &&
  3330. (pdev->device == 0x2300 || pdev->device == 0x2310))
  3331. {
  3332. /*
  3333. * Highpoint RocketRAID PCIe 23xx series cards:
  3334. *
  3335. * Unconfigured drives are treated as "Legacy"
  3336. * by the BIOS, and it overwrites sector 8 with
  3337. * a "Lgcy" metadata block prior to Linux boot.
  3338. *
  3339. * Configured drives (RAID or JBOD) leave sector 8
  3340. * alone, but instead overwrite a high numbered
  3341. * sector for the RAID metadata. This sector can
  3342. * be determined exactly, by truncating the physical
  3343. * drive capacity to a nice even GB value.
  3344. *
  3345. * RAID metadata is at: (dev->n_sectors & ~0xfffff)
  3346. *
  3347. * Warn the user, lest they think we're just buggy.
  3348. */
  3349. printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
  3350. " BIOS CORRUPTS DATA on all attached drives,"
  3351. " regardless of if/how they are configured."
  3352. " BEWARE!\n");
  3353. printk(KERN_WARNING DRV_NAME ": For data safety, do not"
  3354. " use sectors 8-9 on \"Legacy\" drives,"
  3355. " and avoid the final two gigabytes on"
  3356. " all RocketRAID BIOS initialized drives.\n");
  3357. }
  3358. /* drop through */
  3359. case chip_6042:
  3360. hpriv->ops = &mv6xxx_ops;
  3361. hp_flags |= MV_HP_GEN_IIE;
  3362. if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
  3363. hp_flags |= MV_HP_CUT_THROUGH;
  3364. switch (pdev->revision) {
  3365. case 0x2: /* Rev.B0: the first/only public release */
  3366. hp_flags |= MV_HP_ERRATA_60X1C0;
  3367. break;
  3368. default:
  3369. dev_printk(KERN_WARNING, &pdev->dev,
  3370. "Applying 60X1C0 workarounds to unknown rev\n");
  3371. hp_flags |= MV_HP_ERRATA_60X1C0;
  3372. break;
  3373. }
  3374. break;
  3375. case chip_soc:
  3376. if (soc_is_65n(hpriv))
  3377. hpriv->ops = &mv_soc_65n_ops;
  3378. else
  3379. hpriv->ops = &mv_soc_ops;
  3380. hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
  3381. MV_HP_ERRATA_60X1C0;
  3382. break;
  3383. default:
  3384. dev_printk(KERN_ERR, host->dev,
  3385. "BUG: invalid board index %u\n", board_idx);
  3386. return 1;
  3387. }
  3388. hpriv->hp_flags = hp_flags;
  3389. if (hp_flags & MV_HP_PCIE) {
  3390. hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
  3391. hpriv->irq_mask_offset = PCIE_IRQ_MASK;
  3392. hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
  3393. } else {
  3394. hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
  3395. hpriv->irq_mask_offset = PCI_IRQ_MASK;
  3396. hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
  3397. }
  3398. return 0;
  3399. }
  3400. /**
  3401. * mv_init_host - Perform some early initialization of the host.
  3402. * @host: ATA host to initialize
  3403. *
  3404. * If possible, do an early global reset of the host. Then do
  3405. * our port init and clear/unmask all/relevant host interrupts.
  3406. *
  3407. * LOCKING:
  3408. * Inherited from caller.
  3409. */
  3410. static int mv_init_host(struct ata_host *host)
  3411. {
  3412. int rc = 0, n_hc, port, hc;
  3413. struct mv_host_priv *hpriv = host->private_data;
  3414. void __iomem *mmio = hpriv->base;
  3415. rc = mv_chip_id(host, hpriv->board_idx);
  3416. if (rc)
  3417. goto done;
  3418. if (IS_SOC(hpriv)) {
  3419. hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
  3420. hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
  3421. } else {
  3422. hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
  3423. hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
  3424. }
  3425. /* initialize shadow irq mask with register's value */
  3426. hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
  3427. /* global interrupt mask: 0 == mask everything */
  3428. mv_set_main_irq_mask(host, ~0, 0);
  3429. n_hc = mv_get_hc_count(host->ports[0]->flags);
  3430. for (port = 0; port < host->n_ports; port++)
  3431. if (hpriv->ops->read_preamp)
  3432. hpriv->ops->read_preamp(hpriv, port, mmio);
  3433. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  3434. if (rc)
  3435. goto done;
  3436. hpriv->ops->reset_flash(hpriv, mmio);
  3437. hpriv->ops->reset_bus(host, mmio);
  3438. hpriv->ops->enable_leds(hpriv, mmio);
  3439. for (port = 0; port < host->n_ports; port++) {
  3440. struct ata_port *ap = host->ports[port];
  3441. void __iomem *port_mmio = mv_port_base(mmio, port);
  3442. mv_port_init(&ap->ioaddr, port_mmio);
  3443. }
  3444. for (hc = 0; hc < n_hc; hc++) {
  3445. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  3446. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  3447. "(before clear)=0x%08x\n", hc,
  3448. readl(hc_mmio + HC_CFG),
  3449. readl(hc_mmio + HC_IRQ_CAUSE));
  3450. /* Clear any currently outstanding hc interrupt conditions */
  3451. writelfl(0, hc_mmio + HC_IRQ_CAUSE);
  3452. }
  3453. if (!IS_SOC(hpriv)) {
  3454. /* Clear any currently outstanding host interrupt conditions */
  3455. writelfl(0, mmio + hpriv->irq_cause_offset);
  3456. /* and unmask interrupt generation for host regs */
  3457. writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
  3458. }
  3459. /*
  3460. * enable only global host interrupts for now.
  3461. * The per-port interrupts get done later as ports are set up.
  3462. */
  3463. mv_set_main_irq_mask(host, 0, PCI_ERR);
  3464. mv_set_irq_coalescing(host, irq_coalescing_io_count,
  3465. irq_coalescing_usecs);
  3466. done:
  3467. return rc;
  3468. }
  3469. static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
  3470. {
  3471. hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
  3472. MV_CRQB_Q_SZ, 0);
  3473. if (!hpriv->crqb_pool)
  3474. return -ENOMEM;
  3475. hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
  3476. MV_CRPB_Q_SZ, 0);
  3477. if (!hpriv->crpb_pool)
  3478. return -ENOMEM;
  3479. hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
  3480. MV_SG_TBL_SZ, 0);
  3481. if (!hpriv->sg_tbl_pool)
  3482. return -ENOMEM;
  3483. return 0;
  3484. }
  3485. static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
  3486. struct mbus_dram_target_info *dram)
  3487. {
  3488. int i;
  3489. for (i = 0; i < 4; i++) {
  3490. writel(0, hpriv->base + WINDOW_CTRL(i));
  3491. writel(0, hpriv->base + WINDOW_BASE(i));
  3492. }
  3493. for (i = 0; i < dram->num_cs; i++) {
  3494. struct mbus_dram_window *cs = dram->cs + i;
  3495. writel(((cs->size - 1) & 0xffff0000) |
  3496. (cs->mbus_attr << 8) |
  3497. (dram->mbus_dram_target_id << 4) | 1,
  3498. hpriv->base + WINDOW_CTRL(i));
  3499. writel(cs->base, hpriv->base + WINDOW_BASE(i));
  3500. }
  3501. }
  3502. /**
  3503. * mv_platform_probe - handle a positive probe of an soc Marvell
  3504. * host
  3505. * @pdev: platform device found
  3506. *
  3507. * LOCKING:
  3508. * Inherited from caller.
  3509. */
  3510. static int mv_platform_probe(struct platform_device *pdev)
  3511. {
  3512. static int printed_version;
  3513. const struct mv_sata_platform_data *mv_platform_data;
  3514. const struct ata_port_info *ppi[] =
  3515. { &mv_port_info[chip_soc], NULL };
  3516. struct ata_host *host;
  3517. struct mv_host_priv *hpriv;
  3518. struct resource *res;
  3519. int n_ports, rc;
  3520. if (!printed_version++)
  3521. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3522. /*
  3523. * Simple resource validation ..
  3524. */
  3525. if (unlikely(pdev->num_resources != 2)) {
  3526. dev_err(&pdev->dev, "invalid number of resources\n");
  3527. return -EINVAL;
  3528. }
  3529. /*
  3530. * Get the register base first
  3531. */
  3532. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3533. if (res == NULL)
  3534. return -EINVAL;
  3535. /* allocate host */
  3536. mv_platform_data = pdev->dev.platform_data;
  3537. n_ports = mv_platform_data->n_ports;
  3538. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3539. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3540. if (!host || !hpriv)
  3541. return -ENOMEM;
  3542. host->private_data = hpriv;
  3543. hpriv->n_ports = n_ports;
  3544. hpriv->board_idx = chip_soc;
  3545. host->iomap = NULL;
  3546. hpriv->base = devm_ioremap(&pdev->dev, res->start,
  3547. resource_size(res));
  3548. hpriv->base -= SATAHC0_REG_BASE;
  3549. #if defined(CONFIG_HAVE_CLK)
  3550. hpriv->clk = clk_get(&pdev->dev, NULL);
  3551. if (IS_ERR(hpriv->clk))
  3552. dev_notice(&pdev->dev, "cannot get clkdev\n");
  3553. else
  3554. clk_enable(hpriv->clk);
  3555. #endif
  3556. /*
  3557. * (Re-)program MBUS remapping windows if we are asked to.
  3558. */
  3559. if (mv_platform_data->dram != NULL)
  3560. mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
  3561. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3562. if (rc)
  3563. goto err;
  3564. /* initialize adapter */
  3565. rc = mv_init_host(host);
  3566. if (rc)
  3567. goto err;
  3568. dev_printk(KERN_INFO, &pdev->dev,
  3569. "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
  3570. host->n_ports);
  3571. return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
  3572. IRQF_SHARED, &mv6_sht);
  3573. err:
  3574. #if defined(CONFIG_HAVE_CLK)
  3575. if (!IS_ERR(hpriv->clk)) {
  3576. clk_disable(hpriv->clk);
  3577. clk_put(hpriv->clk);
  3578. }
  3579. #endif
  3580. return rc;
  3581. }
  3582. /*
  3583. *
  3584. * mv_platform_remove - unplug a platform interface
  3585. * @pdev: platform device
  3586. *
  3587. * A platform bus SATA device has been unplugged. Perform the needed
  3588. * cleanup. Also called on module unload for any active devices.
  3589. */
  3590. static int __devexit mv_platform_remove(struct platform_device *pdev)
  3591. {
  3592. struct device *dev = &pdev->dev;
  3593. struct ata_host *host = dev_get_drvdata(dev);
  3594. #if defined(CONFIG_HAVE_CLK)
  3595. struct mv_host_priv *hpriv = host->private_data;
  3596. #endif
  3597. ata_host_detach(host);
  3598. #if defined(CONFIG_HAVE_CLK)
  3599. if (!IS_ERR(hpriv->clk)) {
  3600. clk_disable(hpriv->clk);
  3601. clk_put(hpriv->clk);
  3602. }
  3603. #endif
  3604. return 0;
  3605. }
  3606. #ifdef CONFIG_PM
  3607. static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
  3608. {
  3609. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  3610. if (host)
  3611. return ata_host_suspend(host, state);
  3612. else
  3613. return 0;
  3614. }
  3615. static int mv_platform_resume(struct platform_device *pdev)
  3616. {
  3617. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  3618. int ret;
  3619. if (host) {
  3620. struct mv_host_priv *hpriv = host->private_data;
  3621. const struct mv_sata_platform_data *mv_platform_data = \
  3622. pdev->dev.platform_data;
  3623. /*
  3624. * (Re-)program MBUS remapping windows if we are asked to.
  3625. */
  3626. if (mv_platform_data->dram != NULL)
  3627. mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
  3628. /* initialize adapter */
  3629. ret = mv_init_host(host);
  3630. if (ret) {
  3631. printk(KERN_ERR DRV_NAME ": Error during HW init\n");
  3632. return ret;
  3633. }
  3634. ata_host_resume(host);
  3635. }
  3636. return 0;
  3637. }
  3638. #else
  3639. #define mv_platform_suspend NULL
  3640. #define mv_platform_resume NULL
  3641. #endif
  3642. static struct platform_driver mv_platform_driver = {
  3643. .probe = mv_platform_probe,
  3644. .remove = __devexit_p(mv_platform_remove),
  3645. .suspend = mv_platform_suspend,
  3646. .resume = mv_platform_resume,
  3647. .driver = {
  3648. .name = DRV_NAME,
  3649. .owner = THIS_MODULE,
  3650. },
  3651. };
  3652. #ifdef CONFIG_PCI
  3653. static int mv_pci_init_one(struct pci_dev *pdev,
  3654. const struct pci_device_id *ent);
  3655. #ifdef CONFIG_PM
  3656. static int mv_pci_device_resume(struct pci_dev *pdev);
  3657. #endif
  3658. static struct pci_driver mv_pci_driver = {
  3659. .name = DRV_NAME,
  3660. .id_table = mv_pci_tbl,
  3661. .probe = mv_pci_init_one,
  3662. .remove = ata_pci_remove_one,
  3663. #ifdef CONFIG_PM
  3664. .suspend = ata_pci_device_suspend,
  3665. .resume = mv_pci_device_resume,
  3666. #endif
  3667. };
  3668. /* move to PCI layer or libata core? */
  3669. static int pci_go_64(struct pci_dev *pdev)
  3670. {
  3671. int rc;
  3672. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  3673. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  3674. if (rc) {
  3675. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3676. if (rc) {
  3677. dev_printk(KERN_ERR, &pdev->dev,
  3678. "64-bit DMA enable failed\n");
  3679. return rc;
  3680. }
  3681. }
  3682. } else {
  3683. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3684. if (rc) {
  3685. dev_printk(KERN_ERR, &pdev->dev,
  3686. "32-bit DMA enable failed\n");
  3687. return rc;
  3688. }
  3689. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3690. if (rc) {
  3691. dev_printk(KERN_ERR, &pdev->dev,
  3692. "32-bit consistent DMA enable failed\n");
  3693. return rc;
  3694. }
  3695. }
  3696. return rc;
  3697. }
  3698. /**
  3699. * mv_print_info - Dump key info to kernel log for perusal.
  3700. * @host: ATA host to print info about
  3701. *
  3702. * FIXME: complete this.
  3703. *
  3704. * LOCKING:
  3705. * Inherited from caller.
  3706. */
  3707. static void mv_print_info(struct ata_host *host)
  3708. {
  3709. struct pci_dev *pdev = to_pci_dev(host->dev);
  3710. struct mv_host_priv *hpriv = host->private_data;
  3711. u8 scc;
  3712. const char *scc_s, *gen;
  3713. /* Use this to determine the HW stepping of the chip so we know
  3714. * what errata to workaround
  3715. */
  3716. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  3717. if (scc == 0)
  3718. scc_s = "SCSI";
  3719. else if (scc == 0x01)
  3720. scc_s = "RAID";
  3721. else
  3722. scc_s = "?";
  3723. if (IS_GEN_I(hpriv))
  3724. gen = "I";
  3725. else if (IS_GEN_II(hpriv))
  3726. gen = "II";
  3727. else if (IS_GEN_IIE(hpriv))
  3728. gen = "IIE";
  3729. else
  3730. gen = "?";
  3731. dev_printk(KERN_INFO, &pdev->dev,
  3732. "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
  3733. gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
  3734. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  3735. }
  3736. /**
  3737. * mv_pci_init_one - handle a positive probe of a PCI Marvell host
  3738. * @pdev: PCI device found
  3739. * @ent: PCI device ID entry for the matched host
  3740. *
  3741. * LOCKING:
  3742. * Inherited from caller.
  3743. */
  3744. static int mv_pci_init_one(struct pci_dev *pdev,
  3745. const struct pci_device_id *ent)
  3746. {
  3747. static int printed_version;
  3748. unsigned int board_idx = (unsigned int)ent->driver_data;
  3749. const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
  3750. struct ata_host *host;
  3751. struct mv_host_priv *hpriv;
  3752. int n_ports, port, rc;
  3753. if (!printed_version++)
  3754. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3755. /* allocate host */
  3756. n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
  3757. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3758. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3759. if (!host || !hpriv)
  3760. return -ENOMEM;
  3761. host->private_data = hpriv;
  3762. hpriv->n_ports = n_ports;
  3763. hpriv->board_idx = board_idx;
  3764. /* acquire resources */
  3765. rc = pcim_enable_device(pdev);
  3766. if (rc)
  3767. return rc;
  3768. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  3769. if (rc == -EBUSY)
  3770. pcim_pin_device(pdev);
  3771. if (rc)
  3772. return rc;
  3773. host->iomap = pcim_iomap_table(pdev);
  3774. hpriv->base = host->iomap[MV_PRIMARY_BAR];
  3775. rc = pci_go_64(pdev);
  3776. if (rc)
  3777. return rc;
  3778. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3779. if (rc)
  3780. return rc;
  3781. for (port = 0; port < host->n_ports; port++) {
  3782. struct ata_port *ap = host->ports[port];
  3783. void __iomem *port_mmio = mv_port_base(hpriv->base, port);
  3784. unsigned int offset = port_mmio - hpriv->base;
  3785. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
  3786. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
  3787. }
  3788. /* initialize adapter */
  3789. rc = mv_init_host(host);
  3790. if (rc)
  3791. return rc;
  3792. /* Enable message-switched interrupts, if requested */
  3793. if (msi && pci_enable_msi(pdev) == 0)
  3794. hpriv->hp_flags |= MV_HP_FLAG_MSI;
  3795. mv_dump_pci_cfg(pdev, 0x68);
  3796. mv_print_info(host);
  3797. pci_set_master(pdev);
  3798. pci_try_set_mwi(pdev);
  3799. return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
  3800. IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
  3801. }
  3802. #ifdef CONFIG_PM
  3803. static int mv_pci_device_resume(struct pci_dev *pdev)
  3804. {
  3805. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  3806. int rc;
  3807. rc = ata_pci_device_do_resume(pdev);
  3808. if (rc)
  3809. return rc;
  3810. /* initialize adapter */
  3811. rc = mv_init_host(host);
  3812. if (rc)
  3813. return rc;
  3814. ata_host_resume(host);
  3815. return 0;
  3816. }
  3817. #endif
  3818. #endif
  3819. static int mv_platform_probe(struct platform_device *pdev);
  3820. static int __devexit mv_platform_remove(struct platform_device *pdev);
  3821. static int __init mv_init(void)
  3822. {
  3823. int rc = -ENODEV;
  3824. #ifdef CONFIG_PCI
  3825. rc = pci_register_driver(&mv_pci_driver);
  3826. if (rc < 0)
  3827. return rc;
  3828. #endif
  3829. rc = platform_driver_register(&mv_platform_driver);
  3830. #ifdef CONFIG_PCI
  3831. if (rc < 0)
  3832. pci_unregister_driver(&mv_pci_driver);
  3833. #endif
  3834. return rc;
  3835. }
  3836. static void __exit mv_exit(void)
  3837. {
  3838. #ifdef CONFIG_PCI
  3839. pci_unregister_driver(&mv_pci_driver);
  3840. #endif
  3841. platform_driver_unregister(&mv_platform_driver);
  3842. }
  3843. MODULE_AUTHOR("Brett Russ");
  3844. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  3845. MODULE_LICENSE("GPL");
  3846. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  3847. MODULE_VERSION(DRV_VERSION);
  3848. MODULE_ALIAS("platform:" DRV_NAME);
  3849. module_init(mv_init);
  3850. module_exit(mv_exit);