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/arch/arm/mach-msm/board-qrdc.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 4213 lines | 3554 code | 458 blank | 201 comment | 246 complexity | 89f1b7783fc1bdce4c6c17cc22a92312 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/gpio.h>
  21. #include <linux/irq.h>
  22. #include <linux/io.h>
  23. #include <linux/mfd/pmic8058.h>
  24. #include <linux/mfd/bahama.h>
  25. #include <linux/input/pmic8058-keypad.h>
  26. #include <linux/pmic8058-pwrkey.h>
  27. #include <linux/pmic8058-vibrator.h>
  28. #include <linux/leds.h>
  29. #include <linux/pmic8058-othc.h>
  30. #include <linux/mfd/pmic8901.h>
  31. #include <linux/regulator/pmic8901-regulator.h>
  32. #include <linux/bootmem.h>
  33. #include <linux/pwm.h>
  34. #include <linux/pmic8058-pwm.h>
  35. #include <linux/leds-pmic8058.h>
  36. #include <linux/mfd/marimba.h>
  37. #include <linux/i2c.h>
  38. #include <linux/i2c/sx150x.h>
  39. #include <linux/smsc911x.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/input/tdisc_shinetsu.h>
  42. #include <linux/input/cy8c_ts.h>
  43. #include <linux/input/qci_kbd.h>
  44. #include <linux/mfd/wm8994/core.h>
  45. #include <linux/mfd/wm8994/pdata.h>
  46. #ifdef CONFIG_ANDROID_PMEM
  47. #include <linux/android_pmem.h>
  48. #endif
  49. #include <asm/mach-types.h>
  50. #include <asm/mach/arch.h>
  51. #include <asm/setup.h>
  52. #include <mach/mpp.h>
  53. #include <mach/board.h>
  54. #include <mach/irqs.h>
  55. #include <mach/msm_spi.h>
  56. #include <mach/msm_serial_hs.h>
  57. #include <mach/msm_iomap.h>
  58. #include <asm/mach/mmc.h>
  59. #include <mach/msm_battery.h>
  60. #include <mach/msm_hsusb.h>
  61. #include <mach/msm_xo.h>
  62. #include <mach/msm_bus_board.h>
  63. #include <mach/tpm_st_i2c.h>
  64. #include <mach/socinfo.h>
  65. #ifdef CONFIG_USB_ANDROID
  66. #include <linux/usb/android_composite.h>
  67. #endif
  68. #include <linux/regulator/consumer.h>
  69. #include <linux/regulator/machine.h>
  70. #include "devices.h"
  71. #include "devices-msm8x60.h"
  72. #include "cpuidle.h"
  73. #include "pm.h"
  74. #include "rpm.h"
  75. #include "mpm.h"
  76. #include "spm.h"
  77. #include "rpm_log.h"
  78. #include "timer.h"
  79. #include "saw-regulator.h"
  80. #include "rpm-regulator.h"
  81. #include "gpiomux.h"
  82. #include "gpiomux-8x60.h"
  83. #define MSM_SHARED_RAM_PHYS 0x40000000
  84. /* Macros assume PMIC GPIOs start at 0 */
  85. #define PM8058_GPIO_BASE NR_MSM_GPIOS
  86. #define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
  87. #define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
  88. #define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
  89. #define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
  90. PM8058_GPIOS + PM8058_MPPS)
  91. #define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
  92. #define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
  93. #define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
  94. NR_PMIC8058_IRQS)
  95. #define GPIO_EXPANDER_GPIO_BASE \
  96. (PM8901_GPIO_BASE + PM8901_MPPS)
  97. #define GPIO_EXPANDER_IRQ_BASE (PM8901_IRQ_BASE + NR_PMIC8901_IRQS)
  98. /*
  99. * The UI_INTx_N lines are pmic gpio lines which connect i2c
  100. * gpio expanders to the pm8058.
  101. */
  102. #define UI_INT1_N 25
  103. #define UI_INT2_N 34
  104. #define UI_INT3_N 14
  105. static struct msm_spm_platform_data msm_spm_data[] __initdata = {
  106. [0] = {
  107. .reg_base_addr = MSM_SAW0_BASE,
  108. .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
  109. .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
  110. .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
  111. .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
  112. .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
  113. .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
  114. .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
  115. .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
  116. .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
  117. .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
  118. .awake_vlevel = 0x9C,
  119. .retention_vlevel = 0x81,
  120. .collapse_vlevel = 0x20,
  121. .retention_mid_vlevel = 0x94,
  122. .collapse_mid_vlevel = 0x8C,
  123. .vctl_timeout_us = 50,
  124. },
  125. [1] = {
  126. .reg_base_addr = MSM_SAW1_BASE,
  127. .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
  128. .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
  129. .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
  130. .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
  131. .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
  132. .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
  133. .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
  134. .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
  135. .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
  136. .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
  137. .awake_vlevel = 0x9C,
  138. .retention_vlevel = 0x81,
  139. .collapse_vlevel = 0x20,
  140. .retention_mid_vlevel = 0x94,
  141. .collapse_mid_vlevel = 0x8C,
  142. .vctl_timeout_us = 50,
  143. },
  144. };
  145. static struct msm_acpu_clock_platform_data msm8x60_acpu_clock_data = {
  146. };
  147. static struct regulator_consumer_supply saw_s0_supply =
  148. REGULATOR_SUPPLY("8901_s0", NULL);
  149. static struct regulator_consumer_supply saw_s1_supply =
  150. REGULATOR_SUPPLY("8901_s1", NULL);
  151. static struct regulator_init_data saw_s0_init_data = {
  152. .constraints = {
  153. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  154. .min_uV = 840000,
  155. .max_uV = 1200000,
  156. },
  157. .num_consumer_supplies = 1,
  158. .consumer_supplies = &saw_s0_supply,
  159. };
  160. static struct regulator_init_data saw_s1_init_data = {
  161. .constraints = {
  162. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  163. .min_uV = 840000,
  164. .max_uV = 1200000,
  165. },
  166. .num_consumer_supplies = 1,
  167. .consumer_supplies = &saw_s1_supply,
  168. };
  169. static struct platform_device msm_device_saw_s0 = {
  170. .name = "saw-regulator",
  171. .id = SAW_VREG_ID_S0,
  172. .dev = {
  173. .platform_data = &saw_s0_init_data,
  174. },
  175. };
  176. static struct platform_device msm_device_saw_s1 = {
  177. .name = "saw-regulator",
  178. .id = SAW_VREG_ID_S1,
  179. .dev = {
  180. .platform_data = &saw_s1_init_data,
  181. },
  182. };
  183. static struct resource smsc911x_resources[] = {
  184. [0] = {
  185. .flags = IORESOURCE_MEM,
  186. .start = 0x1b800000,
  187. .end = 0x1b8000ff
  188. },
  189. [1] = {
  190. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  191. },
  192. };
  193. static struct smsc911x_platform_config smsc911x_config = {
  194. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
  195. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  196. .flags = SMSC911X_USE_16BIT
  197. };
  198. static struct platform_device smsc911x_device = {
  199. .name = "smsc911x",
  200. .id = 0,
  201. .num_resources = ARRAY_SIZE(smsc911x_resources),
  202. .resource = smsc911x_resources,
  203. .dev = {
  204. .platform_data = &smsc911x_config
  205. }
  206. };
  207. static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
  208. [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
  209. .supported = 1,
  210. .suspend_enabled = 0,
  211. .idle_enabled = 0,
  212. .latency = 4000,
  213. .residency = 13000,
  214. },
  215. [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
  216. .supported = 1,
  217. .suspend_enabled = 0,
  218. .idle_enabled = 0,
  219. .latency = 500,
  220. .residency = 6000,
  221. },
  222. [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
  223. .supported = 1,
  224. .suspend_enabled = 1,
  225. .idle_enabled = 1,
  226. .latency = 2,
  227. .residency = 0,
  228. },
  229. [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
  230. .supported = 1,
  231. .suspend_enabled = 0,
  232. .idle_enabled = 0,
  233. .latency = 600,
  234. .residency = 7200,
  235. },
  236. [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
  237. .supported = 1,
  238. .suspend_enabled = 0,
  239. .idle_enabled = 0,
  240. .latency = 500,
  241. .residency = 6000,
  242. },
  243. [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
  244. .supported = 1,
  245. .suspend_enabled = 1,
  246. .idle_enabled = 1,
  247. .latency = 2,
  248. .residency = 0,
  249. },
  250. };
  251. static struct msm_cpuidle_state msm_cstates[] __initdata = {
  252. {0, 0, "C0", "WFI",
  253. MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
  254. {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
  255. MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
  256. {0, 2, "C2", "POWER_COLLAPSE",
  257. MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
  258. {1, 0, "C0", "WFI",
  259. MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
  260. {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
  261. MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
  262. };
  263. #if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
  264. static struct regulator *ldo6_3p3;
  265. static struct regulator *ldo7_1p8;
  266. static struct regulator *vdd_cx;
  267. static int msm_hsusb_ldo_init(int init)
  268. {
  269. if (init) {
  270. ldo6_3p3 = regulator_get(NULL, "8058_l6");
  271. if (IS_ERR(ldo6_3p3))
  272. return PTR_ERR(ldo6_3p3);
  273. ldo7_1p8 = regulator_get(NULL, "8058_l7");
  274. if (IS_ERR(ldo7_1p8)) {
  275. regulator_put(ldo6_3p3);
  276. return PTR_ERR(ldo7_1p8);
  277. }
  278. /*digital core voltage for usb phy*/
  279. vdd_cx = regulator_get(NULL, "8058_s1");
  280. if (IS_ERR(vdd_cx)) {
  281. regulator_put(ldo6_3p3);
  282. regulator_put(ldo7_1p8);
  283. return PTR_ERR(vdd_cx);
  284. }
  285. regulator_set_voltage(vdd_cx, 1000000, 1200000);
  286. regulator_set_voltage(ldo7_1p8, 1800000, 1800000);
  287. regulator_set_voltage(ldo6_3p3, 3050000, 3050000);
  288. } else {
  289. regulator_put(ldo6_3p3);
  290. regulator_put(ldo7_1p8);
  291. regulator_put(vdd_cx);
  292. }
  293. return 0;
  294. }
  295. static int msm_hsusb_ldo_enable(int on)
  296. {
  297. static int ldo_status;
  298. int ret = 0;
  299. if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
  300. pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
  301. return -ENODEV;
  302. }
  303. if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
  304. pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
  305. return -ENODEV;
  306. }
  307. if (!vdd_cx || IS_ERR(vdd_cx)) {
  308. pr_err("%s: vdd_cx is not initialized\n", __func__);
  309. return -ENODEV;
  310. }
  311. if (ldo_status == on)
  312. return 0;
  313. ldo_status = on;
  314. if (on) {
  315. ret = regulator_enable(ldo7_1p8);
  316. if (ret) {
  317. pr_err("%s: Unable to enable the regulator:"
  318. "ldo7_1p8\n", __func__);
  319. ldo_status = !on;
  320. return ret;
  321. }
  322. ret = regulator_enable(ldo6_3p3);
  323. if (ret) {
  324. pr_err("%s: Unable to enable the regulator:"
  325. "ldo6_3p3\n", __func__);
  326. regulator_disable(ldo7_1p8);
  327. ldo_status = !on;
  328. return ret;
  329. }
  330. ret = regulator_enable(vdd_cx);
  331. if (ret) {
  332. pr_err("%s: Unable to enable VDDCX digital core:"
  333. " vdd_dig\n", __func__);
  334. regulator_disable(ldo6_3p3);
  335. regulator_disable(ldo7_1p8);
  336. ldo_status = !on;
  337. return ret;
  338. }
  339. } else {
  340. /* calling regulator_disable when its already disabled might
  341. * * print WARN_ON. Trying to avoid it by regulator_is_enable
  342. * * */
  343. if (regulator_is_enabled(ldo6_3p3)) {
  344. ret = regulator_disable(ldo6_3p3);
  345. if (ret) {
  346. pr_err("%s: Unable to disable the regulator:"
  347. "ldo6_3p3\n", __func__);
  348. ldo_status = !on;
  349. return ret;
  350. }
  351. }
  352. if (regulator_is_enabled(ldo7_1p8)) {
  353. ret = regulator_disable(ldo7_1p8);
  354. if (ret) {
  355. pr_err("%s: Unable to enable the regulator:"
  356. " ldo7_1p8\n", __func__);
  357. ldo_status = !on;
  358. return ret;
  359. }
  360. }
  361. if (regulator_is_enabled(vdd_cx)) {
  362. ret = regulator_disable(vdd_cx);
  363. if (ret) {
  364. pr_err("%s: Unable to enable the regulator:"
  365. "vdd_cx\n", __func__);
  366. ldo_status = !on;
  367. return ret;
  368. }
  369. }
  370. }
  371. pr_debug("reg (%s)\n", on ? "ENABLED" : "DISABLED");
  372. return 0;
  373. }
  374. #endif
  375. #ifdef CONFIG_USB_EHCI_MSM
  376. static void msm_hsusb_vbus_power(unsigned phy_info, int on)
  377. {
  378. static struct regulator *votg_5v_switch;
  379. static struct regulator *ext_5v_reg;
  380. static int vbus_is_on;
  381. /* If VBUS is already on (or off), do nothing. */
  382. if (on == vbus_is_on)
  383. return;
  384. if (!votg_5v_switch) {
  385. votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
  386. if (IS_ERR(votg_5v_switch)) {
  387. pr_err("%s: unable to get votg_5v_switch\n", __func__);
  388. return;
  389. }
  390. }
  391. if (!ext_5v_reg) {
  392. ext_5v_reg = regulator_get(NULL, "8901_mpp0");
  393. if (IS_ERR(ext_5v_reg)) {
  394. pr_err("%s: unable to get ext_5v_reg\n", __func__);
  395. return;
  396. }
  397. }
  398. if (on) {
  399. if (regulator_enable(ext_5v_reg)) {
  400. pr_err("%s: Unable to enable the regulator:"
  401. " ext_5v_reg\n", __func__);
  402. return;
  403. }
  404. if (regulator_enable(votg_5v_switch)) {
  405. pr_err("%s: Unable to enable the regulator:"
  406. " votg_5v_switch\n", __func__);
  407. return;
  408. }
  409. } else {
  410. if (regulator_disable(votg_5v_switch))
  411. pr_err("%s: Unable to enable the regulator:"
  412. " votg_5v_switch\n", __func__);
  413. if (regulator_disable(ext_5v_reg))
  414. pr_err("%s: Unable to enable the regulator:"
  415. " ext_5v_reg\n", __func__);
  416. }
  417. vbus_is_on = on;
  418. }
  419. static struct msm_usb_host_platform_data msm_usb_host_pdata = {
  420. .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
  421. .power_budget = 390,
  422. };
  423. #endif
  424. #if defined(CONFIG_BATTERY_MSM8X60) && !defined(CONFIG_USB_EHCI_MSM)
  425. static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
  426. int init)
  427. {
  428. if (init) {
  429. /* TBD: right API will get filled here as a part of
  430. * PMIC chanrger patch and removes thsi comments.*/
  431. } else {
  432. /* TBD: right API will get filled here as a part of
  433. * PMIC chanrger patch and removes thsi comments.*/
  434. }
  435. return 0;
  436. }
  437. #endif
  438. #define USB_SWITCH_EN_GPIO 132 /* !CS of analog switch */
  439. #define USB_SWITCH_CNTL_GPIO 131 /* 0: Host, 1: Peripheral */
  440. #define USB_HUB_RESET_GPIO 34 /* 0: HUB is RESET */
  441. static int msm_otg_init_analog_switch_gpio(int on)
  442. {
  443. int rc = 0;
  444. if (on) {
  445. /* USB SWITCH ENABLE*/
  446. rc = gpio_request(USB_SWITCH_EN_GPIO, "USB_SWITCH_ENABLE");
  447. if (rc) {
  448. pr_err("%s: SW_EN gpio %d request failed\n", __func__,
  449. USB_SWITCH_EN_GPIO);
  450. return rc;
  451. }
  452. /* USB SWITCH CONTROL */
  453. rc = gpio_request(USB_SWITCH_CNTL_GPIO, "USB_SWITCH_CONTROL");
  454. if (rc) {
  455. pr_err("%s: SW_CNTL gpio %d request failed\n", __func__,
  456. USB_SWITCH_CNTL_GPIO);
  457. goto fail_gpio_usb_switch_en;
  458. }
  459. /* USB HUB RESET */
  460. rc = gpio_request(USB_HUB_RESET_GPIO, "USB_HUB_RESET");
  461. if (rc) {
  462. pr_err("%s: HUB_RESET gpio %d request failed\n",
  463. __func__, USB_HUB_RESET_GPIO);
  464. goto fail_gpio_usb_switch_cntl;
  465. }
  466. /* Set direction of USB SWITCH ENABLE gpio */
  467. rc = gpio_direction_output(USB_SWITCH_EN_GPIO, 0);
  468. if (rc) {
  469. pr_err("%s: gpio_direction_output failed for %d\n",
  470. __func__, USB_SWITCH_EN_GPIO);
  471. goto fail_gpio_usb_hub_reset;
  472. }
  473. /* Set direction of USB SWITCH CONTROL gpio */
  474. rc = gpio_direction_output(USB_SWITCH_CNTL_GPIO, 0);
  475. if (rc) {
  476. pr_err("%s: gpio_direction_output failed for %d\n",
  477. __func__, USB_SWITCH_CNTL_GPIO);
  478. goto fail_gpio_usb_hub_reset;
  479. }
  480. /* Set direction of USB HUB RESET gpio */
  481. rc = gpio_direction_output(USB_HUB_RESET_GPIO, 0);
  482. if (rc) {
  483. pr_err("%s: gpio_direction_output failed for %d\n",
  484. __func__, USB_HUB_RESET_GPIO);
  485. goto fail_gpio_usb_hub_reset;
  486. }
  487. return rc;
  488. }
  489. fail_gpio_usb_hub_reset:
  490. gpio_free(USB_HUB_RESET_GPIO);
  491. fail_gpio_usb_switch_cntl:
  492. gpio_free(USB_SWITCH_CNTL_GPIO);
  493. fail_gpio_usb_switch_en:
  494. gpio_free(USB_SWITCH_EN_GPIO);
  495. return rc;
  496. }
  497. static void msm_otg_setup_analog_switch_gpio(enum usb_switch_control mode)
  498. {
  499. switch (mode) {
  500. case USB_SWITCH_HOST:
  501. /* Configure analog switch as USB host. */
  502. gpio_set_value(USB_SWITCH_EN_GPIO, 0);
  503. gpio_set_value(USB_SWITCH_CNTL_GPIO, 0);
  504. /* Bring HUB out of RESET */
  505. gpio_set_value(USB_HUB_RESET_GPIO, 1);
  506. break;
  507. case USB_SWITCH_PERIPHERAL:
  508. /* Configure analog switch as USB peripheral. */
  509. gpio_set_value(USB_SWITCH_EN_GPIO, 0);
  510. gpio_set_value(USB_SWITCH_CNTL_GPIO, 1);
  511. gpio_set_value(USB_HUB_RESET_GPIO, 0);
  512. break;
  513. case USB_SWITCH_DISABLE:
  514. default:
  515. /* Disable Switch */
  516. gpio_set_value(USB_SWITCH_EN_GPIO, 1);
  517. gpio_set_value(USB_HUB_RESET_GPIO, 0);
  518. }
  519. }
  520. #if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
  521. static struct msm_otg_platform_data msm_otg_pdata = {
  522. /* if usb link is in sps there is no need for
  523. * usb pclk as dayatona fabric clock will be
  524. * used instead
  525. */
  526. .usb_in_sps = 1,
  527. .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
  528. .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
  529. .se1_gating = SE1_GATING_DISABLE,
  530. .init_gpio = msm_otg_init_analog_switch_gpio,
  531. .setup_gpio = msm_otg_setup_analog_switch_gpio,
  532. #ifdef CONFIG_USB_EHCI_MSM
  533. .vbus_power = msm_hsusb_vbus_power,
  534. #endif
  535. #if defined(CONFIG_BATTERY_MSM8X60) && !defined(CONFIG_USB_EHCI_MSM)
  536. .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
  537. #endif
  538. .otg_mode = OTG_USER_CONTROL,
  539. .usb_mode = USB_HOST_MODE,
  540. .ldo_init = msm_hsusb_ldo_init,
  541. .ldo_enable = msm_hsusb_ldo_enable,
  542. };
  543. #endif
  544. #ifdef CONFIG_USB_ANDROID
  545. static char *usb_functions_default[] = {
  546. "diag",
  547. "modem",
  548. "nmea",
  549. "rmnet",
  550. "usb_mass_storage",
  551. };
  552. static char *usb_functions_default_adb[] = {
  553. "diag",
  554. "adb",
  555. "modem",
  556. "nmea",
  557. "rmnet",
  558. "usb_mass_storage",
  559. };
  560. static char *usb_functions_rndis[] = {
  561. "rndis",
  562. };
  563. static char *usb_functions_rndis_adb[] = {
  564. "rndis",
  565. "adb",
  566. };
  567. static char *usb_functions_all[] = {
  568. #ifdef CONFIG_USB_ANDROID_RNDIS
  569. "rndis",
  570. #endif
  571. #ifdef CONFIG_USB_ANDROID_DIAG
  572. "diag",
  573. #endif
  574. "adb",
  575. #ifdef CONFIG_USB_F_SERIAL
  576. "modem",
  577. "nmea",
  578. #endif
  579. #ifdef CONFIG_USB_ANDROID_RMNET
  580. "rmnet",
  581. #endif
  582. "usb_mass_storage",
  583. #ifdef CONFIG_USB_ANDROID_ACM
  584. "acm",
  585. #endif
  586. };
  587. static struct android_usb_product usb_products[] = {
  588. {
  589. .product_id = 0x9026,
  590. .num_functions = ARRAY_SIZE(usb_functions_default),
  591. .functions = usb_functions_default,
  592. },
  593. {
  594. .product_id = 0x9025,
  595. .num_functions = ARRAY_SIZE(usb_functions_default_adb),
  596. .functions = usb_functions_default_adb,
  597. },
  598. {
  599. .product_id = 0xf00e,
  600. .num_functions = ARRAY_SIZE(usb_functions_rndis),
  601. .functions = usb_functions_rndis,
  602. },
  603. {
  604. .product_id = 0x9024,
  605. .num_functions = ARRAY_SIZE(usb_functions_rndis_adb),
  606. .functions = usb_functions_rndis_adb,
  607. },
  608. };
  609. static struct usb_mass_storage_platform_data mass_storage_pdata = {
  610. .nluns = 1,
  611. .vendor = "Qualcomm Incorporated",
  612. .product = "Mass storage",
  613. };
  614. static struct platform_device usb_mass_storage_device = {
  615. .name = "usb_mass_storage",
  616. .id = -1,
  617. .dev = {
  618. .platform_data = &mass_storage_pdata,
  619. },
  620. };
  621. static struct usb_ether_platform_data rndis_pdata = {
  622. /* ethaddr is filled by board_serialno_setup */
  623. .vendorID = 0x05C6,
  624. .vendorDescr = "Qualcomm Incorporated",
  625. };
  626. static struct platform_device rndis_device = {
  627. .name = "rndis",
  628. .id = -1,
  629. .dev = {
  630. .platform_data = &rndis_pdata,
  631. },
  632. };
  633. static struct android_usb_platform_data android_usb_pdata = {
  634. .vendor_id = 0x05C6,
  635. .product_id = 0x9026,
  636. .version = 0x0100,
  637. .product_name = "Qualcomm HSUSB Device",
  638. .manufacturer_name = "Qualcomm Incorporated",
  639. .num_products = ARRAY_SIZE(usb_products),
  640. .products = usb_products,
  641. .num_functions = ARRAY_SIZE(usb_functions_all),
  642. .functions = usb_functions_all,
  643. .serial_number = "1234567890ABCDEF",
  644. };
  645. static struct platform_device android_usb_device = {
  646. .name = "android_usb",
  647. .id = -1,
  648. .dev = {
  649. .platform_data = &android_usb_pdata,
  650. },
  651. };
  652. static int __init board_serialno_setup(char *serialno)
  653. {
  654. int i;
  655. char *src = serialno;
  656. /* create a fake MAC address from our serial number.
  657. * first byte is 0x02 to signify locally administered.
  658. */
  659. rndis_pdata.ethaddr[0] = 0x02;
  660. for (i = 0; *src; i++) {
  661. /* XOR the USB serial across the remaining bytes */
  662. rndis_pdata.ethaddr[i % (ETH_ALEN - 1) + 1] ^= *src++;
  663. }
  664. android_usb_pdata.serial_number = serialno;
  665. return 1;
  666. }
  667. __setup("androidboot.serialno=", board_serialno_setup);
  668. #endif
  669. #ifdef CONFIG_MSM_VPE
  670. static struct resource msm_vpe_resources[] = {
  671. {
  672. .start = 0x05300000,
  673. .end = 0x05300000 + SZ_1M - 1,
  674. .flags = IORESOURCE_MEM,
  675. },
  676. {
  677. .start = INT_VPE,
  678. .end = INT_VPE,
  679. .flags = IORESOURCE_IRQ,
  680. },
  681. };
  682. static struct platform_device msm_vpe_device = {
  683. .name = "msm_vpe",
  684. .id = 0,
  685. .num_resources = ARRAY_SIZE(msm_vpe_resources),
  686. .resource = msm_vpe_resources,
  687. };
  688. #endif
  689. #ifdef CONFIG_MSM_GEMINI
  690. static struct resource msm_gemini_resources[] = {
  691. {
  692. .start = 0x04600000,
  693. .end = 0x04600000 + SZ_1M - 1,
  694. .flags = IORESOURCE_MEM,
  695. },
  696. {
  697. .start = INT_JPEG,
  698. .end = INT_JPEG,
  699. .flags = IORESOURCE_IRQ,
  700. },
  701. };
  702. static struct platform_device msm_gemini_device = {
  703. .name = "msm_gemini",
  704. .resource = msm_gemini_resources,
  705. .num_resources = ARRAY_SIZE(msm_gemini_resources),
  706. };
  707. #endif
  708. #ifdef CONFIG_I2C_QUP
  709. static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
  710. {
  711. }
  712. static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
  713. .clk_freq = 100000,
  714. .src_clk_rate = 24000000,
  715. .clk = "gsbi_qup_clk",
  716. .pclk = "gsbi_pclk",
  717. .use_gsbi_shared_mode = 1,
  718. .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
  719. };
  720. static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
  721. .clk_freq = 100000,
  722. .src_clk_rate = 24000000,
  723. .clk = "gsbi_qup_clk",
  724. .pclk = "gsbi_pclk",
  725. .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
  726. };
  727. static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
  728. .clk_freq = 100000,
  729. .src_clk_rate = 24000000,
  730. .clk = "gsbi_qup_clk",
  731. .pclk = "gsbi_pclk",
  732. .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
  733. };
  734. static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
  735. .clk_freq = 100000,
  736. .src_clk_rate = 24000000,
  737. .clk = "gsbi_qup_clk",
  738. .pclk = "gsbi_pclk",
  739. .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
  740. };
  741. static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
  742. .clk_freq = 100000,
  743. .src_clk_rate = 24000000,
  744. .clk = "gsbi_qup_clk",
  745. .pclk = "gsbi_pclk",
  746. .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
  747. };
  748. #endif
  749. #if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
  750. static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
  751. .max_clock_speed = 24000000,
  752. .clk_name = "gsbi_qup_clk",
  753. .pclk_name = "gsbi_pclk",
  754. };
  755. #endif
  756. #ifdef CONFIG_I2C_SSBI
  757. /* PMIC SSBI */
  758. static struct msm_ssbi_platform_data msm_ssbi1_pdata = {
  759. .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
  760. };
  761. /* PMIC SSBI */
  762. static struct msm_ssbi_platform_data msm_ssbi2_pdata = {
  763. .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
  764. };
  765. /* CODEC/TSSC SSBI */
  766. static struct msm_ssbi_platform_data msm_ssbi3_pdata = {
  767. .controller_type = MSM_SBI_CTRL_SSBI,
  768. };
  769. #endif
  770. #ifdef CONFIG_BATTERY_MSM
  771. /* Use basic value for fake MSM battery */
  772. static struct msm_psy_batt_pdata msm_psy_batt_data = {
  773. .avail_chg_sources = AC_CHG,
  774. };
  775. static struct platform_device msm_batt_device = {
  776. .name = "msm-battery",
  777. .id = -1,
  778. .dev.platform_data = &msm_psy_batt_data,
  779. };
  780. #endif
  781. #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
  782. /* prim = 1366 (rounds up to 1376) x 768 x 4(bpp) x 2(pages)
  783. * hdmi = 1920 x 1080 x 2(bpp) x 1(page)
  784. * Note: must be multiple of 4096 */
  785. #define MSM_FB_SIZE 0xC08000
  786. #else /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
  787. #define MSM_FB_SIZE 0x811000
  788. #endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
  789. #define MSM_PMEM_SF_SIZE 0x1700000
  790. #define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
  791. #define MSM_PMEM_ADSP_SIZE 0x2000000
  792. #define MSM_SMI_BASE 0x38000000
  793. /* Kernel SMI PMEM Region for video core, used for Firmware */
  794. /* and encoder,decoder scratch buffers */
  795. /* Kernel SMI PMEM Region Should always precede the user space */
  796. /* SMI PMEM Region, as the video core will use offset address */
  797. /* from the Firmware base */
  798. #define PMEM_KERNEL_SMI_BASE (MSM_SMI_BASE)
  799. #define PMEM_KERNEL_SMI_SIZE 0x1000000
  800. /* User space SMI PMEM Region for video core*/
  801. /* used for encoder, decoder input & output buffers */
  802. #define MSM_PMEM_SMIPOOL_BASE (PMEM_KERNEL_SMI_BASE + PMEM_KERNEL_SMI_SIZE)
  803. #define MSM_PMEM_SMIPOOL_SIZE 0x2800000
  804. static unsigned fb_size = MSM_FB_SIZE;
  805. static int __init fb_size_setup(char *p)
  806. {
  807. fb_size = memparse(p, NULL);
  808. return 0;
  809. }
  810. early_param("fb_size", fb_size_setup);
  811. #ifdef CONFIG_KERNEL_PMEM_EBI_REGION
  812. static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
  813. static int __init pmem_kernel_ebi1_size_setup(char *p)
  814. {
  815. pmem_kernel_ebi1_size = memparse(p, NULL);
  816. return 0;
  817. }
  818. early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
  819. #endif
  820. #ifdef CONFIG_ANDROID_PMEM
  821. static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
  822. static int __init pmem_sf_size_setup(char *p)
  823. {
  824. pmem_sf_size = memparse(p, NULL);
  825. return 0;
  826. }
  827. early_param("pmem_sf_size", pmem_sf_size_setup);
  828. static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
  829. static int __init pmem_adsp_size_setup(char *p)
  830. {
  831. pmem_adsp_size = memparse(p, NULL);
  832. return 0;
  833. }
  834. early_param("pmem_adsp_size", pmem_adsp_size_setup);
  835. #endif
  836. static struct resource msm_fb_resources[] = {
  837. {
  838. .flags = IORESOURCE_DMA,
  839. }
  840. };
  841. static int msm_fb_detect_panel(const char *name)
  842. {
  843. #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
  844. if (!strcmp(name, "hdmi_msm"))
  845. return 0;
  846. #endif
  847. if (!strcmp(name, "lcdc_qrdc"))
  848. return 0;
  849. pr_warning("%s: not supported '%s'", __func__, name);
  850. return -ENODEV;
  851. }
  852. static void lcd_panel_power(int on);
  853. static int msm_fb_lcdc_gpio_config(int on);
  854. static int vga_enabled;
  855. static int vga_enable(int select_vga)
  856. {
  857. int rc = 0;
  858. vga_enabled = select_vga;
  859. rc = msm_fb_lcdc_gpio_config(1);
  860. if (rc)
  861. return rc;
  862. lcd_panel_power(1);
  863. return 0;
  864. }
  865. static struct msm_panel_common_pdata lcdc_qrdc_panel_data = {
  866. .vga_switch = vga_enable,
  867. };
  868. static struct platform_device lcdc_qrdc_panel_device = {
  869. .name = "lcdc_qrdc",
  870. .id = 0,
  871. .dev = {
  872. .platform_data = &lcdc_qrdc_panel_data,
  873. }
  874. };
  875. static struct msm_fb_platform_data msm_fb_pdata = {
  876. .detect_client = msm_fb_detect_panel,
  877. };
  878. static struct platform_device msm_fb_device = {
  879. .name = "msm_fb",
  880. .id = 0,
  881. .num_resources = ARRAY_SIZE(msm_fb_resources),
  882. .resource = msm_fb_resources,
  883. .dev = {
  884. .platform_data = &msm_fb_pdata,
  885. }
  886. };
  887. #ifdef CONFIG_KERNEL_PMEM_EBI_REGION
  888. static struct android_pmem_platform_data android_pmem_kernel_ebi1_pdata = {
  889. .name = PMEM_KERNEL_EBI1_DATA_NAME,
  890. .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
  891. .cached = 0,
  892. };
  893. static struct platform_device android_pmem_kernel_ebi1_device = {
  894. .name = "android_pmem",
  895. .id = 1,
  896. .dev = { .platform_data = &android_pmem_kernel_ebi1_pdata },
  897. };
  898. #endif
  899. #ifdef CONFIG_KERNEL_PMEM_SMI_REGION
  900. static struct android_pmem_platform_data android_pmem_kernel_smi_pdata = {
  901. .name = PMEM_KERNEL_SMI_DATA_NAME,
  902. /* defaults to bitmap don't edit */
  903. .cached = 0,
  904. };
  905. static struct platform_device android_pmem_kernel_smi_device = {
  906. .name = "android_pmem",
  907. .id = 6,
  908. .dev = { .platform_data = &android_pmem_kernel_smi_pdata },
  909. };
  910. #endif
  911. #ifdef CONFIG_ANDROID_PMEM
  912. static struct android_pmem_platform_data android_pmem_pdata = {
  913. .name = "pmem",
  914. .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
  915. .cached = 0,
  916. };
  917. static struct platform_device android_pmem_device = {
  918. .name = "android_pmem",
  919. .id = 0,
  920. .dev = {.platform_data = &android_pmem_pdata},
  921. };
  922. static struct android_pmem_platform_data android_pmem_adsp_pdata = {
  923. .name = "pmem_adsp",
  924. .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
  925. .cached = 0,
  926. };
  927. static struct platform_device android_pmem_adsp_device = {
  928. .name = "android_pmem",
  929. .id = 2,
  930. .dev = { .platform_data = &android_pmem_adsp_pdata },
  931. };
  932. static struct android_pmem_platform_data android_pmem_smipool_pdata = {
  933. .name = "pmem_smipool",
  934. .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
  935. .cached = 0,
  936. };
  937. static struct platform_device android_pmem_smipool_device = {
  938. .name = "android_pmem",
  939. .id = 7,
  940. .dev = { .platform_data = &android_pmem_smipool_pdata },
  941. };
  942. #endif
  943. #define GPIO_BACKLIGHT_PWM0 0
  944. #define GPIO_BACKLIGHT_PWM1 1
  945. static int pmic_backlight_gpio[2]
  946. = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
  947. static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
  948. .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
  949. };
  950. static struct platform_device lcdc_samsung_panel_device = {
  951. .name = "lcdc_samsung_wsvga",
  952. .id = 0,
  953. .dev = {
  954. .platform_data = &lcdc_samsung_panel_data,
  955. }
  956. };
  957. #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
  958. static struct resource hdmi_msm_resources[] = {
  959. {
  960. .name = "hdmi_msm_qfprom_addr",
  961. .start = 0x00700000,
  962. .end = 0x007060FF,
  963. .flags = IORESOURCE_MEM,
  964. },
  965. {
  966. .name = "hdmi_msm_hdmi_addr",
  967. .start = 0x04A00000,
  968. .end = 0x04A00FFF,
  969. .flags = IORESOURCE_MEM,
  970. },
  971. {
  972. .name = "hdmi_msm_irq",
  973. .start = HDMI_IRQ,
  974. .end = HDMI_IRQ,
  975. .flags = IORESOURCE_IRQ,
  976. },
  977. };
  978. static int hdmi_enable_5v(int on);
  979. static int hdmi_core_power(int on, int show);
  980. static int hdmi_cec_power(int on);
  981. static struct msm_hdmi_platform_data hdmi_msm_data = {
  982. .irq = HDMI_IRQ,
  983. .enable_5v = hdmi_enable_5v,
  984. .core_power = hdmi_core_power,
  985. .cec_power = hdmi_cec_power,
  986. };
  987. static struct platform_device hdmi_msm_device = {
  988. .name = "hdmi_msm",
  989. .id = 0,
  990. .num_resources = ARRAY_SIZE(hdmi_msm_resources),
  991. .resource = hdmi_msm_resources,
  992. .dev.platform_data = &hdmi_msm_data,
  993. };
  994. #endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
  995. static struct platform_device mipi_dsi_video_toshiba_wvga_panel_device = {
  996. .name = "dsi_video_toshiba_wvga",
  997. .id = 0,
  998. };
  999. static void __init msm8x60_allocate_memory_regions(void)
  1000. {
  1001. void *addr;
  1002. unsigned long size;
  1003. size = MSM_FB_SIZE;
  1004. addr = alloc_bootmem(size);
  1005. msm_fb_resources[0].start = __pa(addr);
  1006. msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
  1007. pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
  1008. size, addr, __pa(addr));
  1009. #ifdef CONFIG_KERNEL_PMEM_EBI_REGION
  1010. size = pmem_kernel_ebi1_size;
  1011. if (size) {
  1012. addr = alloc_bootmem_aligned(size, 0x100000);
  1013. android_pmem_kernel_ebi1_pdata.start = __pa(addr);
  1014. android_pmem_kernel_ebi1_pdata.size = size;
  1015. pr_info("allocating %lu bytes at %p (%lx physical) for kernel"
  1016. " ebi1 pmem arena\n", size, addr, __pa(addr));
  1017. }
  1018. #endif
  1019. #ifdef CONFIG_KERNEL_PMEM_SMI_REGION
  1020. size = PMEM_KERNEL_SMI_SIZE;
  1021. if (size) {
  1022. android_pmem_kernel_smi_pdata.start = PMEM_KERNEL_SMI_BASE;
  1023. android_pmem_kernel_smi_pdata.size = size;
  1024. pr_info("allocating %lu bytes at %lx physical for kernel"
  1025. " smi pmem arena\n", size,
  1026. (unsigned long) PMEM_KERNEL_SMI_BASE);
  1027. }
  1028. #endif
  1029. #ifdef CONFIG_ANDROID_PMEM
  1030. size = pmem_adsp_size;
  1031. if (size) {
  1032. addr = alloc_bootmem(size);
  1033. android_pmem_adsp_pdata.start = __pa(addr);
  1034. android_pmem_adsp_pdata.size = size;
  1035. pr_info("allocating %lu bytes at %p (%lx physical) for adsp "
  1036. "pmem arena\n", size, addr, __pa(addr));
  1037. }
  1038. size = MSM_PMEM_SMIPOOL_SIZE;
  1039. if (size) {
  1040. android_pmem_smipool_pdata.start = MSM_PMEM_SMIPOOL_BASE;
  1041. android_pmem_smipool_pdata.size = size;
  1042. pr_info("allocating %lu bytes at %lx physical for user"
  1043. " smi pmem arena\n", size,
  1044. (unsigned long) MSM_PMEM_SMIPOOL_BASE);
  1045. }
  1046. size = pmem_sf_size;
  1047. if (size) {
  1048. addr = alloc_bootmem(size);
  1049. android_pmem_pdata.start = __pa(addr);
  1050. android_pmem_pdata.size = size;
  1051. pr_info("allocating %lu bytes at %p (%lx physical) for sf "
  1052. "pmem arena\n", size, addr, __pa(addr));
  1053. }
  1054. #endif
  1055. }
  1056. #ifdef CONFIG_SERIAL_MSM_HS
  1057. static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
  1058. .inject_rx_on_wakeup = 1,
  1059. .rx_to_inject = 0xFD,
  1060. };
  1061. #endif
  1062. #if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
  1063. static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
  1064. .phys_addr_base = 0x00106000,
  1065. .reg_offsets = {
  1066. [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
  1067. [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
  1068. },
  1069. .phys_size = SZ_8K,
  1070. .log_len = 4096, /* log's buffer length in bytes */
  1071. .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
  1072. };
  1073. static struct platform_device msm_rpm_log_device = {
  1074. .name = "msm_rpm_log",
  1075. .id = -1,
  1076. .dev = {
  1077. .platform_data = &msm_rpm_log_pdata,
  1078. },
  1079. };
  1080. #endif
  1081. static struct regulator_consumer_supply rpm_vreg_supply[RPM_VREG_ID_MAX] = {
  1082. [RPM_VREG_ID_PM8058_L0] = REGULATOR_SUPPLY("8058_l0", NULL),
  1083. [RPM_VREG_ID_PM8058_L1] = REGULATOR_SUPPLY("8058_l1", NULL),
  1084. [RPM_VREG_ID_PM8058_L2] = REGULATOR_SUPPLY("8058_l2", NULL),
  1085. [RPM_VREG_ID_PM8058_L3] = REGULATOR_SUPPLY("8058_l3", NULL),
  1086. [RPM_VREG_ID_PM8058_L4] = REGULATOR_SUPPLY("8058_l4", NULL),
  1087. [RPM_VREG_ID_PM8058_L5] = REGULATOR_SUPPLY("8058_l5", NULL),
  1088. [RPM_VREG_ID_PM8058_L6] = REGULATOR_SUPPLY("8058_l6", NULL),
  1089. [RPM_VREG_ID_PM8058_L7] = REGULATOR_SUPPLY("8058_l7", NULL),
  1090. [RPM_VREG_ID_PM8058_L8] = REGULATOR_SUPPLY("8058_l8", NULL),
  1091. [RPM_VREG_ID_PM8058_L9] = REGULATOR_SUPPLY("8058_l9", NULL),
  1092. [RPM_VREG_ID_PM8058_L10] = REGULATOR_SUPPLY("8058_l10", NULL),
  1093. [RPM_VREG_ID_PM8058_L11] = REGULATOR_SUPPLY("8058_l11", NULL),
  1094. [RPM_VREG_ID_PM8058_L12] = REGULATOR_SUPPLY("8058_l12", NULL),
  1095. [RPM_VREG_ID_PM8058_L13] = REGULATOR_SUPPLY("8058_l13", NULL),
  1096. [RPM_VREG_ID_PM8058_L14] = REGULATOR_SUPPLY("8058_l14", NULL),
  1097. [RPM_VREG_ID_PM8058_L15] = REGULATOR_SUPPLY("8058_l15", NULL),
  1098. [RPM_VREG_ID_PM8058_L16] = REGULATOR_SUPPLY("8058_l16", NULL),
  1099. [RPM_VREG_ID_PM8058_L17] = REGULATOR_SUPPLY("8058_l17", NULL),
  1100. [RPM_VREG_ID_PM8058_L18] = REGULATOR_SUPPLY("8058_l18", NULL),
  1101. [RPM_VREG_ID_PM8058_L19] = REGULATOR_SUPPLY("8058_l19", NULL),
  1102. [RPM_VREG_ID_PM8058_L20] = REGULATOR_SUPPLY("8058_l20", NULL),
  1103. [RPM_VREG_ID_PM8058_L21] = REGULATOR_SUPPLY("8058_l21", NULL),
  1104. [RPM_VREG_ID_PM8058_L22] = REGULATOR_SUPPLY("8058_l22", NULL),
  1105. [RPM_VREG_ID_PM8058_L23] = REGULATOR_SUPPLY("8058_l23", NULL),
  1106. [RPM_VREG_ID_PM8058_L24] = REGULATOR_SUPPLY("8058_l24", NULL),
  1107. [RPM_VREG_ID_PM8058_L25] = REGULATOR_SUPPLY("8058_l25", NULL),
  1108. [RPM_VREG_ID_PM8058_S0] = REGULATOR_SUPPLY("8058_s0", NULL),
  1109. [RPM_VREG_ID_PM8058_S1] = REGULATOR_SUPPLY("8058_s1", NULL),
  1110. [RPM_VREG_ID_PM8058_S2] = REGULATOR_SUPPLY("8058_s2", NULL),
  1111. [RPM_VREG_ID_PM8058_S3] = REGULATOR_SUPPLY("8058_s3", NULL),
  1112. [RPM_VREG_ID_PM8058_S4] = REGULATOR_SUPPLY("8058_s4", NULL),
  1113. [RPM_VREG_ID_PM8058_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL),
  1114. [RPM_VREG_ID_PM8058_LVS1] = REGULATOR_SUPPLY("8058_lvs1", NULL),
  1115. [RPM_VREG_ID_PM8058_NCP] = REGULATOR_SUPPLY("8058_ncp", NULL),
  1116. [RPM_VREG_ID_PM8901_L0] = REGULATOR_SUPPLY("8901_l0", NULL),
  1117. [RPM_VREG_ID_PM8901_L1] = REGULATOR_SUPPLY("8901_l1", NULL),
  1118. [RPM_VREG_ID_PM8901_L2] = REGULATOR_SUPPLY("8901_l2", NULL),
  1119. [RPM_VREG_ID_PM8901_L3] = REGULATOR_SUPPLY("8901_l3", NULL),
  1120. [RPM_VREG_ID_PM8901_L4] = REGULATOR_SUPPLY("8901_l4", NULL),
  1121. [RPM_VREG_ID_PM8901_L5] = REGULATOR_SUPPLY("8901_l5", NULL),
  1122. [RPM_VREG_ID_PM8901_L6] = REGULATOR_SUPPLY("8901_l6", NULL),
  1123. [RPM_VREG_ID_PM8901_S2] = REGULATOR_SUPPLY("8901_s2", NULL),
  1124. [RPM_VREG_ID_PM8901_S3] = REGULATOR_SUPPLY("8901_s3", NULL),
  1125. [RPM_VREG_ID_PM8901_S4] = REGULATOR_SUPPLY("8901_s4", NULL),
  1126. [RPM_VREG_ID_PM8901_LVS0] = REGULATOR_SUPPLY("8901_lvs0", NULL),
  1127. [RPM_VREG_ID_PM8901_LVS1] = REGULATOR_SUPPLY("8901_lvs1", NULL),
  1128. [RPM_VREG_ID_PM8901_LVS2] = REGULATOR_SUPPLY("8901_lvs2", NULL),
  1129. [RPM_VREG_ID_PM8901_LVS3] = REGULATOR_SUPPLY("8901_lvs3", NULL),
  1130. [RPM_VREG_ID_PM8901_MVS0] = REGULATOR_SUPPLY("8901_mvs0", NULL),
  1131. };
  1132. #define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
  1133. _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
  1134. _freq, _pin_fn, _rpm_mode, _state, _sleep_selectable, \
  1135. _always_on) \
  1136. [RPM_VREG_ID_##_id] = { \
  1137. .init_data = { \
  1138. .constraints = { \
  1139. .valid_modes_mask = _modes, \
  1140. .valid_ops_mask = _ops, \
  1141. .min_uV = _min_uV, \
  1142. .max_uV = _max_uV, \
  1143. .input_uV = _min_uV, \
  1144. .apply_uV = _apply_uV, \
  1145. .always_on = _always_on, \
  1146. }, \
  1147. .num_consumer_supplies = 1, \
  1148. .consumer_supplies = \
  1149. &rpm_vreg_supply[RPM_VREG_ID_##_id], \
  1150. }, \
  1151. .default_uV = _default_uV, \
  1152. .peak_uA = _peak_uA, \
  1153. .avg_uA = _avg_uA, \
  1154. .pull_down_enable = _pull_down, \
  1155. .pin_ctrl = _pin_ctrl, \
  1156. .freq = _freq, \
  1157. .pin_fn = _pin_fn, \
  1158. .mode = _rpm_mode, \
  1159. .state = _state, \
  1160. .sleep_selectable = _sleep_selectable, \
  1161. }
  1162. /*
  1163. * The default LPM/HPM state of an RPM controlled regulator can be controlled
  1164. * via the peak_uA value specified in the table below. If the value is less
  1165. * than the low power threshold for the regulator, then the regulator will be
  1166. * set to LPM. Otherwise, it will be set to HPM.
  1167. *
  1168. * This value can be further overridden by specifying an initial mode via
  1169. * .init_data.constraints.initial_mode.
  1170. */
  1171. #define RPM_VREG_INIT_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
  1172. _max_uV, _init_peak_uA, _pin_ctrl) \
  1173. RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
  1174. REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
  1175. REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
  1176. REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
  1177. REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
  1178. _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
  1179. RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
  1180. RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
  1181. #define RPM_VREG_INIT_LDO_PF(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
  1182. _max_uV, _init_peak_uA, _pin_ctrl, _pin_fn) \
  1183. RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
  1184. REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
  1185. REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
  1186. REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
  1187. REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
  1188. _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
  1189. _pin_fn, RPM_VREG_MODE_NONE, RPM_VREG_STATE_OFF, \
  1190. _sleep_selectable, _always_on)
  1191. #define RPM_VREG_INIT_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
  1192. _max_uV, _init_peak_uA, _pin_ctrl, _freq) \
  1193. RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
  1194. REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
  1195. REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
  1196. REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
  1197. REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
  1198. _init_peak_uA, _pd, _pin_ctrl, _freq, \
  1199. RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
  1200. RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
  1201. #define RPM_VREG_INIT_VS(_id, _always_on, _pd, _sleep_selectable, _pin_ctrl) \
  1202. RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
  1203. REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
  1204. 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
  1205. RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
  1206. RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
  1207. #define RPM_VREG_INIT_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
  1208. _max_uV, _pin_ctrl) \
  1209. RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
  1210. REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
  1211. _min_uV, 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
  1212. RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
  1213. RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
  1214. #define LDO50HMIN RPM_VREG_LDO_50_HPM_MIN_LOAD
  1215. #define LDO150HMIN RPM_VREG_LDO_150_HPM_MIN_LOAD
  1216. #define LDO300HMIN RPM_VREG_LDO_300_HPM_MIN_LOAD
  1217. #define SMPS_HMIN RPM_VREG_SMPS_HPM_MIN_LOAD
  1218. #define FTS_HMIN RPM_VREG_FTSMPS_HPM_MIN_LOAD
  1219. static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
  1220. RPM_VREG_INIT_LDO_PF(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN,
  1221. RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
  1222. RPM_VREG_INIT_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
  1223. RPM_VREG_INIT_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN, 0),
  1224. RPM_VREG_INIT_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
  1225. RPM_VREG_INIT_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN, 0),
  1226. RPM_VREG_INIT_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
  1227. RPM_VREG_INIT_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN, 0),
  1228. RPM_VREG_INIT_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN, 0),
  1229. RPM_VREG_INIT_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN, 0),
  1230. RPM_VREG_INIT_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
  1231. RPM_VREG_INIT_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
  1232. RPM_VREG_INIT_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN, 0),
  1233. RPM_VREG_INIT_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN, 0),
  1234. RPM_VREG_INIT_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN, 0),
  1235. RPM_VREG_INIT_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN, 0),
  1236. RPM_VREG_INIT_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
  1237. RPM_VREG_INIT_LDO(PM8058_L16, 1, 1, 1, 1800000, 1800000, LDO300HMIN, 0),
  1238. RPM_VREG_INIT_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN, 0),
  1239. RPM_VREG_INIT_LDO(PM8058_L18, 0, 1, 1, 2200000, 2200000, LDO150HMIN, 0),
  1240. RPM_VREG_INIT_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN, 0),
  1241. RPM_VREG_INIT_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
  1242. RPM_VREG_INIT_LDO_PF(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN,
  1243. RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
  1244. RPM_VREG_INIT_LDO(PM8058_L22, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
  1245. RPM_VREG_INIT_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
  1246. RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
  1247. RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
  1248. RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
  1249. RPM_VREG_FREQ_1p75),
  1250. RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
  1251. RPM_VREG_FREQ_1p75),
  1252. RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 0, 1200000, 1400000, SMPS_HMIN,
  1253. RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
  1254. RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
  1255. RPM_VREG_FREQ_1p75),
  1256. RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
  1257. RPM_VREG_FREQ_1p75),
  1258. RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
  1259. RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
  1260. RPM_VREG_INIT_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000, 0),
  1261. RPM_VREG_INIT_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN,
  1262. RPM_VREG_PIN_CTRL_A0),
  1263. RPM_VREG_INIT_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
  1264. RPM_VREG_INIT_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN, 0),
  1265. RPM_VREG_INIT_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
  1266. RPM_VREG_INIT_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
  1267. RPM_VREG_INIT_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
  1268. RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
  1269. RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
  1270. RPM_VREG_FREQ_1p75),
  1271. RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
  1272. RPM_VREG_FREQ_1p75),
  1273. RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
  1274. RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
  1275. RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
  1276. RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
  1277. RPM_VREG_INIT_VS(PM8901_LVS2, 0, 1, 0, 0),
  1278. RPM_VREG_INIT_VS(PM8901_LVS3, 0, 1, 0, 0),
  1279. RPM_VREG_INIT_VS(PM8901_MVS0, 0, 1, 0, 0),
  1280. };
  1281. #define RPM_VREG(_id) \
  1282. [_id] = { \
  1283. .name = "rpm-regulator", \
  1284. .id = _id, \
  1285. .dev = { \
  1286. .platform_data = &rpm_vreg_init_pdata[_id], \
  1287. }, \
  1288. }
  1289. static struct platform_device rpm_vreg_device[RPM_VREG_ID_MAX] = {
  1290. RPM_VREG(RPM_VREG_ID_PM8058_L0),
  1291. RPM_VREG(RPM_VREG_ID_PM8058_L1),
  1292. RPM_VREG(RPM_VREG_ID_PM8058_L2),
  1293. RPM_VREG(RPM_VREG_ID_PM8058_L3),
  1294. RPM_VREG(RPM_VREG_ID_PM8058_L4),
  1295. RPM_VREG(RPM_VREG_ID_PM8058_L5),
  1296. RPM_VREG(RPM_VREG_ID_PM8058_L6),
  1297. RPM_VREG(RPM_VREG_ID_PM8058_L7),
  1298. RPM_VREG(RPM_VREG_ID_PM8058_L8),
  1299. RPM_VREG(RPM_VREG_ID_PM8058_L9),
  1300. RPM_VREG(RPM_VREG_ID_PM8058_L10),
  1301. RPM_VREG(RPM_VREG_ID_PM8058_L11),
  1302. RPM_VREG(RPM_VREG_ID_PM8058_L12),
  1303. RPM_VREG(RPM_VREG_ID_PM8058_L13),
  1304. RPM_VREG(RPM_VREG_ID_PM8058_L14),
  1305. RPM_VREG(RPM_VREG_ID_PM8058_L15),
  1306. RPM_VREG(RPM_VREG_ID_PM8058_L16),
  1307. RPM_VREG(RPM_VREG_ID_PM8058_L17),
  1308. RPM_VREG(RPM_VREG_ID_PM8058_L18),
  1309. RPM_VREG(RPM_VREG_ID_PM8058_L19),
  1310. RPM_VREG(RPM_VREG_ID_PM8058_L20),
  1311. RPM_VREG(RPM_VREG_ID_PM8058_L21),
  1312. RPM_VREG(RPM_VREG_ID_PM8058_L22),
  1313. RPM_VREG(RPM_VREG_ID_PM8058_L23),
  1314. RPM_VREG(RPM_VREG_ID_PM8058_L24),
  1315. RPM_VREG(RPM_VREG_ID_PM8058_L25),
  1316. RPM_VREG(RPM_VREG_ID_PM8058_S0),
  1317. RPM_VREG(RPM_VREG_ID_PM8058_S1),
  1318. RPM_VREG(RPM_VREG_ID_PM8058_S2),
  1319. RPM_VREG(RPM_VREG_ID_PM8058_S3),
  1320. RPM_VREG(RPM_VREG_ID_PM8058_S4),
  1321. RPM_VREG(RPM_VREG_ID_PM8058_LVS0),
  1322. RPM_VREG(RPM_VREG_ID_PM8058_LVS1),
  1323. RPM_VREG(RPM_VREG_ID_PM8058_NCP),
  1324. RPM_VREG(RPM_VREG_ID_PM8901_L0),
  1325. RPM_VREG(RPM_VREG_ID_PM8901_L1),
  1326. RPM_VREG(RPM_VREG_ID_PM8901_L2),
  1327. RPM_VREG(RPM_VREG_ID_PM8901_L3),
  1328. RPM_VREG(RPM_VREG_ID_PM8901_L4),
  1329. RPM_VREG(RPM_VREG_ID_PM8901_L5),
  1330. RPM_VREG(RPM_VREG_ID_PM8901_L6),
  1331. RPM_VREG(RPM_VREG_ID_PM8901_S2),
  1332. RPM_VREG(RPM_VREG_ID_PM8901_S3),
  1333. RPM_VREG(RPM_VREG_ID_PM8901_S4),
  1334. RPM_VREG(RPM_VREG_ID_PM8901_LVS0),
  1335. RPM_VREG(RPM_VREG_ID_PM8901_LVS1),
  1336. RPM_VREG(RPM_VREG_ID_PM8901_LVS2),
  1337. RPM_VREG(RPM_VREG_ID_PM8901_LVS3),
  1338. RPM_VREG(RPM_VREG_ID_PM8901_MVS0),
  1339. };
  1340. static struct platform_device *early_regulators[] __initdata = {
  1341. &msm_device_saw_s0,
  1342. &msm_device_saw_s1,
  1343. #ifdef CONFIG_PMIC8058
  1344. &rpm_vreg_device[RPM_VREG_ID_PM8058_S0],
  1345. &rpm_vreg_device[RPM_VREG_ID_PM8058_S1],
  1346. #endif
  1347. };
  1348. static struct platform_device *early_devices[] __initdata = {
  1349. #ifdef CONFIG_MSM_BUS_SCALING
  1350. &msm_bus_apps_fabric,
  1351. &msm_bus_sys_fabric,
  1352. &msm_bus_mm_fabric,
  1353. &msm_bus_sys_fpb,
  1354. &msm_bus_cpss_fpb,
  1355. #endif
  1356. };
  1357. static struct resource msm_aux_pcm_resources[] = {
  1358. {
  1359. .name = "aux_pcm_dout",
  1360. .start = 111,
  1361. .end = 111,
  1362. .flags = IORESOURCE_IO,
  1363. },
  1364. {
  1365. .name = "aux_pcm_din",
  1366. .start = 112,
  1367. .end = 112,
  1368. .flags = IORESOURCE_IO,
  1369. },
  1370. {
  1371. .name = "aux_pcm_syncout",
  1372. .start = 113,
  1373. .end = 113,
  1374. .flags = IORESOURCE_IO,
  1375. },
  1376. {
  1377. .name = "aux_pcm_clkin_a",
  1378. .start = 114,
  1379. .end = 114,
  1380. .flags = IORESOURCE_IO,
  1381. },
  1382. };
  1383. static struct platform_device msm_aux_pcm_device = {
  1384. .name = "msm_aux_pcm",
  1385. .id = 0,
  1386. .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
  1387. .resource = msm_aux_pcm_resources,
  1388. };
  1389. static struct platform_device *qrdc_devices[] __initdata = {
  1390. &msm_device_smd,
  1391. &smsc911x_device,
  1392. &msm_device_uart_dm3,
  1393. #ifdef CONFIG_I2C_QUP
  1394. &msm_gsbi3_qup_i2c_device,
  1395. &msm_gsbi4_qup_i2c_device,
  1396. &msm_gsbi7_qup_i2c_device,
  1397. &msm_gsbi8_qup_i2c_device,
  1398. &msm_gsbi9_qup_i2c_device,
  1399. #endif
  1400. #if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
  1401. &msm_gsbi1_qup_spi_device,
  1402. #endif
  1403. #ifdef CONFIG_SERIAL_MSM_HS
  1404. &msm_device_uart_dm1,
  1405. #endif
  1406. #ifdef CONFIG_I2C_SSBI
  1407. &msm_device_ssbi1,
  1408. &msm_device_ssbi2,
  1409. &msm_device_ssbi3,
  1410. #endif
  1411. #if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
  1412. &msm_device_otg,
  1413. #endif
  1414. #ifdef CONFIG_USB_GADGET_MSM_72K
  1415. &msm_device_gadget_peripheral,
  1416. #endif
  1417. #ifdef CONFIG_USB_ANDROID
  1418. &usb_mass_storage_device,
  1419. &rndis_device,
  1420. &android_usb_device,
  1421. #endif
  1422. #ifdef CONFIG_BATTERY_MSM
  1423. &msm_batt_device,
  1424. #endif
  1425. #ifdef CONFIG_KERNEL_PMEM_EBI_REGION
  1426. &android_pmem_kernel_ebi1_device,
  1427. #endif
  1428. #ifdef CONFIG_KERNEL_PMEM_SMI_REGION
  1429. &android_pmem_kernel_smi_device,
  1430. #endif
  1431. #ifdef CONFIG_ANDROID_PMEM
  1432. &android_pmem_device,
  1433. &android_pmem_adsp_device,
  1434. &android_pmem_smipool_device,
  1435. #endif
  1436. #ifdef CONFIG_MSM_ROTATOR
  1437. &msm_rotator_device,
  1438. #endif
  1439. &msm_fb_device,
  1440. &lcdc_qrdc_panel_device,
  1441. &msm_device_kgsl,
  1442. &lcdc_samsung_panel_device,
  1443. #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
  1444. &hdmi_msm_device,
  1445. #endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
  1446. &mipi_dsi_video_toshiba_wvga_panel_device,
  1447. #ifdef CONFIG_MSM_GEMINI
  1448. &msm_gemini_device,
  1449. #endif
  1450. #ifdef CONFIG_MSM_VPE
  1451. &msm_vpe_device,
  1452. #endif
  1453. #if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
  1454. &msm_rpm_log_device,
  1455. #endif
  1456. &msm_device_vidc,
  1457. &msm_aux_pcm_device,
  1458. #ifdef CONFIG_PMIC8058
  1459. &rpm_vreg_device[RPM_VREG_ID_PM8058_L0],
  1460. &rpm_vreg_device[RPM_VREG_ID_PM8058_L1],
  1461. &rpm_vreg_device[RPM_VREG_ID_PM8058_L2],
  1462. &rpm_vreg_device[RPM_VREG_ID_PM8058_L3],
  1463. &rpm_vreg_device[RPM_VREG_ID_PM8058_L4],
  1464. &rpm_vreg_device[RPM_VREG_ID_PM8058_L5],
  1465. &rpm_vreg_device[RPM_VREG_ID_PM8058_L6],
  1466. &rpm_vreg_device[RPM_VREG_ID_PM8058_L7],
  1467. &rpm_vreg_device[RPM_VREG_ID_PM8058_L8],
  1468. &rpm_vreg_device[RPM_VREG_ID_PM8058_L9],
  1469. &rpm_vreg_device[RPM_VREG_ID_PM8058_L10],
  1470. &rpm_vreg_device[RPM_VREG_ID_PM8058_L11],
  1471. &rpm_vreg_device[RPM_VREG_ID_PM8058_L12],
  1472. &rpm_vreg_device[RPM_VREG_ID_PM8058_L13],
  1473. &rpm_vreg_device[RPM_VREG_ID_PM8058_L14],
  1474. &rpm_vreg_device[RPM_VREG_ID_PM8058_L15],
  1475. &rpm_vreg_device[RPM_VREG_ID_PM8058_L16],
  1476. &rpm_vreg_device[RPM_VREG_ID_PM8058_L17],
  1477. &rpm_vreg_device[RPM_VREG_ID_PM8058_L18],
  1478. &rpm_vreg_device[RPM_VREG_ID_PM8058_L19],
  1479. &rpm_vreg_device[RPM_VREG_ID_PM8058_L20],
  1480. &rpm_vreg_device[RPM_VREG_ID_PM8058_L21],
  1481. &rpm_vreg_device[RPM_VREG_ID_PM8058_L22],
  1482. &rpm_vreg_device[RPM_VREG_ID_PM8058_L23],
  1483. &rpm_vreg_device[RPM_VREG_ID_PM8058_L24],
  1484. &rpm_vreg_device[RPM_VREG_ID_PM8058_L25],
  1485. &rpm_vreg_device[RPM_VREG_ID_PM8058_S2],
  1486. &rpm_vreg_device[RPM_VREG_ID_PM8058_S3],
  1487. &rpm_vreg_device[RPM_VREG_ID_PM8058_S4],
  1488. &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS0],
  1489. &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS1],
  1490. &rpm_vreg_device[RPM_VREG_ID_PM8058_NCP],
  1491. #endif
  1492. #ifdef CONFIG_PMIC8901
  1493. &rpm_vreg_device[RPM_VREG_ID_PM8901_L0],
  1494. &rpm_vreg_device[RPM_VREG_ID_PM8901_L1],
  1495. &rpm_vreg_device[RPM_VREG_ID_PM8901_L2],
  1496. &rpm_vreg_device[RPM_VREG_ID_PM8901_L3],
  1497. &rpm_vreg_device[RPM_VREG_ID_PM8901_L4],
  1498. &rpm_vreg_device[RPM_VREG_ID_PM8901_L5],
  1499. &rpm_vreg_device[RPM_VREG_ID_PM8901_L6],
  1500. &rpm_vreg_device[RPM_VREG_ID_PM8901_S2],
  1501. &rpm_vreg_device[RPM_VREG_ID_PM8901_S3],
  1502. &rpm_vreg_device[RPM_VREG_ID_PM8901_S4],
  1503. &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS0],
  1504. &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS1],
  1505. &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS2],
  1506. &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS3],
  1507. &rpm_vreg_device[RPM_VREG_ID_PM8901_MVS0],
  1508. #endif
  1509. };
  1510. #ifdef CONFIG_PMIC8058
  1511. #define PMIC_GPIO_SDC3_DET 22
  1512. #define PMIC_GPIO_EXT_POWER 1
  1513. static int pm8058_gpios_init(void)
  1514. {
  1515. int i;
  1516. int rc;
  1517. struct pm8058_gpio_cfg {
  1518. int gpio;
  1519. struct pm8058_gpio cfg;
  1520. };
  1521. struct pm8058_gpio_cfg gpio_cfgs[] = {
  1522. { /* External power enable */
  1523. PMIC_GPIO_EXT_POWER - 1,
  1524. {
  1525. .direction = PM_GPIO_DIR_OUT,
  1526. .output_value = 1,
  1527. .pull = PM_GPIO_PULL_UP_30,
  1528. .vin_sel = 2,
  1529. .function = PM_GPIO_FUNC_NORMAL,
  1530. .inv_int_pol = 0,
  1531. },
  1532. },
  1533. { /* FFA ethernet */
  1534. 6,
  1535. {
  1536. .direction = PM_GPIO_DIR_IN,
  1537. .pull = PM_GPIO_PULL_DN,
  1538. .vin_sel = 2,
  1539. .function = PM_GPIO_FUNC_NORMAL,
  1540. .inv_int_pol = 0,
  1541. },
  1542. },
  1543. #ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
  1544. {
  1545. PMIC_GPIO_SDC3_DET - 1,
  1546. {
  1547. .direction = PM_GPIO_DIR_IN,
  1548. .pull = PM_GPIO_PULL_UP_30,
  1549. .vin_sel = 2,
  1550. .function = PM_GPIO_FUNC_NORMAL,
  1551. .inv_int_pol = 0,
  1552. },
  1553. },
  1554. #endif
  1555. { /* core&surf gpio expander */
  1556. UI_INT1_N,
  1557. {
  1558. .direction = PM_GPIO_DIR_IN,
  1559. .pull = PM_GPIO_PULL_NO,
  1560. .vin_sel = PM_GPIO_VIN_S3,
  1561. .function = PM_GPIO_FUNC_NORMAL,
  1562. .inv_int_pol = 0,
  1563. },
  1564. },
  1565. { /* docking gpio expander */
  1566. UI_INT2_N,
  1567. {
  1568. .direction = PM_GPIO_DIR_IN,
  1569. .pull = PM_GPIO_PULL_NO,
  1570. .vin_sel = PM_GPIO_VIN_S3,
  1571. .function = PM_GPIO_FUNC_NORMAL,
  1572. .inv_int_pol = 0,
  1573. },
  1574. },
  1575. { /* FHA/keypad gpio expanders */
  1576. UI_INT3_N,
  1577. {
  1578. .direction = PM_GPIO_DIR_IN,
  1579. .pull = PM_GPIO_PULL_NO,
  1580. .vin_sel = PM_GPIO_VIN_S3,
  1581. .function = PM_GPIO_FUNC_NORMAL,
  1582. .inv_int_pol = 0,
  1583. },
  1584. },
  1585. { /* TouchDisc Interrupt */
  1586. 5,
  1587. {
  1588. .direction = PM_GPIO_DIR_IN,
  1589. .pull = PM_GPIO_PULL_UP_1P5,
  1590. .vin_sel = 2,
  1591. .function = PM_GPIO_FUNC_NORMAL,
  1592. .inv_int_pol = 0,
  1593. }
  1594. },
  1595. { /* Timpani Reset */
  1596. 20,
  1597. {
  1598. .direction = PM_GPIO_DIR_OUT,
  1599. .output_value = 1,
  1600. .output_buffer = PM_GPIO_OUT_BUF_CMOS,
  1601. .pull = PM_GPIO_PULL_DN,
  1602. .out_strength = PM_GPIO_STRENGTH_HIGH,
  1603. .function = PM_GPIO_FUNC_NORMAL,
  1604. .vin_sel = 2,
  1605. .inv_int_pol = 0,
  1606. }
  1607. }
  1608. };
  1609. for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
  1610. rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
  1611. &gpio_cfgs[i].cfg);
  1612. if (rc < 0) {
  1613. pr_err("%s pmic gpio config failed\n",
  1614. __func__);
  1615. return rc;
  1616. }
  1617. }
  1618. return 0;
  1619. }
  1620. static struct resource resources_pwrkey[] = {
  1621. {
  1622. .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
  1623. .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
  1624. .flags = IORESOURCE_IRQ,
  1625. },
  1626. {
  1627. .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
  1628. .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
  1629. .flags = IORESOURCE_IRQ,
  1630. },
  1631. };
  1632. static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
  1633. .pull_up = 1,
  1634. .kpd_trigger_delay_us = 970,
  1635. .wakeup = 1,
  1636. .pwrkey_time_ms = 500,
  1637. };
  1638. static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
  1639. .initial_vibrate_ms = 500,
  1640. .level_mV = 3000,
  1641. .max_timeout_ms = 15000,
  1642. };
  1643. #define PM8058_OTHC_CNTR_BASE0 0xA0
  1644. #define PM8058_OTHC_CNTR_BASE1 0x134
  1645. #define PM8058_OTHC_CNTR_BASE2 0x137
  1646. /* MIC_BIAS0 is configured as normal MIC BIAS */
  1647. static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
  1648. .micbias_select = OTHC_MICBIAS_0,
  1649. .micbias_capability = OTHC_MICBIAS,
  1650. .micbias_enable = OTHC_SIGNAL_OFF,
  1651. };
  1652. /* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
  1653. static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
  1654. .micbias_select = OTHC_MICBIAS_1,
  1655. .micbias_capability = OTHC_MICBIAS,
  1656. .micbias_enable = OTHC_SIGNAL_OFF,
  1657. };
  1658. /* MIC_BIAS2 is configured as normal MIC BIAS */
  1659. static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
  1660. .micbias_select = OTHC_MICBIAS_2,
  1661. .micbias_capability = OTHC_MICBIAS,
  1662. .micbias_enable = OTHC_SIGNAL_OFF,
  1663. };
  1664. static struct resource resources_othc_0[] = {
  1665. {
  1666. .name = "othc_base",
  1667. .start = PM8058_OTHC_CNTR_BASE0,
  1668. .end = PM8058_OTHC_CNTR_BASE0,
  1669. .flags = IORESOURCE_IO,
  1670. },
  1671. };
  1672. static struct resource resources_othc_1[] = {
  1673. {
  1674. .name = "othc_base",
  1675. .start = PM8058_OTHC_CNTR_BASE1,
  1676. .end = PM8058_OTHC_CNTR_BASE1,
  1677. .flags = IORESOURCE_IO,
  1678. },
  1679. };
  1680. static struct resource resources_othc_2[] = {
  1681. {
  1682. .name = "othc_base",
  1683. .start = PM8058_OTHC_CNTR_BASE2,
  1684. .end = PM8058_OTHC_CNTR_BASE2,
  1685. .flags = IORESOURCE_IO,
  1686. },
  1687. };
  1688. static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
  1689. {
  1690. struct pm8058_gpio pwm_gpio_config = {
  1691. .direction = PM_GPIO_DIR_OUT,
  1692. .output_buffer = PM_GPIO_OUT_BUF_CMOS,
  1693. .output_value = 0,
  1694. .pull = PM_GPIO_PULL_NO,
  1695. .vin_sel = PM_GPIO_VIN_VPH,
  1696. .out_strength = PM_GPIO_STRENGTH_HIGH,
  1697. .function = PM_GPIO_FUNC_2,
  1698. };
  1699. int rc = -EINVAL;
  1700. int id, mode, max_mA;
  1701. id = mode = max_mA = 0;
  1702. switch (ch) {
  1703. case 0:
  1704. case 1:
  1705. case 2:
  1706. if (on) {
  1707. id = 24 + ch;
  1708. rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
  1709. if (rc)
  1710. pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
  1711. __func__, id, rc);
  1712. }
  1713. break;
  1714. case 6:
  1715. id = PM_PWM_LED_FLASH;
  1716. mode = PM_PWM_CONF_PWM1;
  1717. max_mA = 300;
  1718. break;
  1719. case 7:
  1720. id = PM_PWM_LED_FLASH1;
  1721. mode = PM_PWM_CONF_PWM1;
  1722. max_mA = 300;
  1723. break;
  1724. default:
  1725. break;
  1726. }
  1727. if (ch >= 6 && ch <= 7) {
  1728. if (!on) {
  1729. mode = PM_PWM_CONF_NONE;
  1730. max_mA = 0;
  1731. }
  1732. rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
  1733. if (rc)
  1734. pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
  1735. __func__, ch, rc);
  1736. }
  1737. return rc;
  1738. }
  1739. static struct pm8058_pwm_pdata pm8058_pwm_data = {
  1740. .config = pm8058_pwm_config,
  1741. };
  1742. #define PM8058_GPIO_INT 88
  1743. static struct pm8058_gpio_platform_data pm8058_gpio_data = {
  1744. .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
  1745. .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
  1746. .init = pm8058_gpios_init,
  1747. };
  1748. static struct pm8058_gpio_platform_data pm8058_mpp_data = {
  1749. .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
  1750. .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
  1751. };
  1752. static struct resource resources_rtc[] = {
  1753. {
  1754. .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
  1755. .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
  1756. .flags = IORESOURCE_IRQ,
  1757. },
  1758. {
  1759. .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
  1760. .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
  1761. .flags = IORESOURCE_IRQ,
  1762. },
  1763. };
  1764. static struct mfd_cell pm8058_subdevs[] = {
  1765. { .name = "pm8058-gpio",
  1766. .id = -1,
  1767. .platform_data = &pm8058_gpio_data,
  1768. .data_size = sizeof(pm8058_gpio_data),
  1769. },
  1770. { .name = "pm8058-mpp",
  1771. .id = -1,
  1772. .platform_data = &pm8058_mpp_data,
  1773. .data_size = sizeof(pm8058_mpp_data),
  1774. },
  1775. { .name = "pm8058-pwrkey",
  1776. .id = -1,
  1777. .resources = resources_pwrkey,
  1778. .num_resources = ARRAY_SIZE(resources_pwrkey),
  1779. .platform_data = &pwrkey_pdata,
  1780. .data_size = sizeof(pwrkey_pdata),
  1781. },
  1782. {
  1783. .name = "pm8058-vib",
  1784. .id = -1,
  1785. .platform_data = &pmic_vib_pdata,
  1786. .data_size = sizeof(pmic_vib_pdata),
  1787. },
  1788. {
  1789. .name = "pm8058-pwm",
  1790. .id = -1,
  1791. .platform_data = &pm8058_pwm_data,
  1792. .data_size = sizeof(pm8058_pwm_data),
  1793. },
  1794. {
  1795. .name = "pm8058-othc",
  1796. .id = 0,
  1797. .platform_data = &othc_config_pdata_0,
  1798. .data_size = sizeof(othc_config_pdata_0),
  1799. .num_resources = ARRAY_SIZE(resources_othc_0),
  1800. .resources = resources_othc_0,
  1801. },
  1802. {
  1803. .name = "pm8058-othc",
  1804. .id = 1,
  1805. .num_resources = ARRAY_SIZE(resources_othc_1),
  1806. .resources = resources_othc_1,
  1807. .platform_data = &othc_config_pdata_1,
  1808. .data_size = sizeof(othc_config_pdata_1),
  1809. },
  1810. {
  1811. .name = "pm8058-othc",
  1812. .id = 2,
  1813. .platform_data = &othc_config_pdata_2,
  1814. .data_size = sizeof(othc_config_pdata_2),
  1815. .num_resources = ARRAY_SIZE(resources_othc_2),
  1816. .resources = resources_othc_2,
  1817. },
  1818. {
  1819. .name = "pm8058-rtc",
  1820. .id = -1,
  1821. .num_resources = ARRAY_SIZE(resources_rtc),
  1822. .resources = resources_rtc,
  1823. },
  1824. { .name = "pm8058-upl",
  1825. .id = -1,
  1826. },
  1827. };
  1828. static struct pm8058_platform_data pm8058_platform_data = {
  1829. .irq_base = PM8058_IRQ_BASE,
  1830. .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
  1831. .sub_devices = pm8058_subdevs,
  1832. .irq_trigger_flags = IRQF_TRIGGER_LOW,
  1833. };
  1834. static struct i2c_board_info pm8058_boardinfo[] __initdata = {
  1835. {
  1836. I2C_BOARD_INFO("pm8058-core", 0x55),
  1837. .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
  1838. .platform_data = &pm8058_platform_data,
  1839. },
  1840. };
  1841. #endif /* CONFIG_PMIC8058 */
  1842. #if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
  1843. defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
  1844. #define TDISC_I2C_SLAVE_ADDR 0x67
  1845. #define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
  1846. #define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
  1847. #define TDISC_OE (GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 4)
  1848. static const char *vregs_tdisc_name[] = {
  1849. "8058_l5",
  1850. "8058_s3",
  1851. };
  1852. static const int vregs_tdisc_val[] = {
  1853. 2850000,/* uV */
  1854. 1800000,
  1855. };
  1856. static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
  1857. static int tdisc_shinetsu_setup(void)
  1858. {
  1859. int rc, i;
  1860. rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
  1861. if (rc) {
  1862. pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
  1863. __func__);
  1864. return rc;
  1865. }
  1866. rc = gpio_request(TDISC_OE, "tdisc_oe");
  1867. if (rc) {
  1868. pr_err("%s: gpio_request failed for TDISC_OE\n",
  1869. __func__);
  1870. goto fail_gpio_oe;
  1871. }
  1872. rc = gpio_direction_output(TDISC_OE, 1);
  1873. if (rc) {
  1874. pr_err("%s: gpio_direction_output failed for TDISC_OE\n",
  1875. __func__);
  1876. gpio_free(TDISC_OE);
  1877. goto fail_gpio_oe;
  1878. }
  1879. for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
  1880. vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
  1881. if (IS_ERR(vregs_tdisc[i])) {
  1882. printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
  1883. __func__, vregs_tdisc_name[i],
  1884. PTR_ERR(vregs_tdisc[i]));
  1885. rc = PTR_ERR(vregs_tdisc[i]);
  1886. goto vreg_get_fail;
  1887. }
  1888. rc = regulator_set_voltage(vregs_tdisc[i],
  1889. vregs_tdisc_val[i], vregs_tdisc_val[i]);
  1890. if (rc) {
  1891. printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
  1892. __func__, rc);
  1893. goto vreg_set_voltage_fail;
  1894. }
  1895. }
  1896. return rc;
  1897. vreg_set_voltage_fail:
  1898. i++;
  1899. vreg_get_fail:
  1900. while (i)
  1901. regulator_put(vregs_tdisc[--i]);
  1902. fail_gpio_oe:
  1903. gpio_free(PMIC_GPIO_TDISC);
  1904. return rc;
  1905. }
  1906. static void tdisc_shinetsu_release(void)
  1907. {
  1908. int i;
  1909. for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
  1910. regulator_put(vregs_tdisc[i]);
  1911. gpio_free(PMIC_GPIO_TDISC);
  1912. gpio_free(TDISC_OE);
  1913. }
  1914. static int tdisc_shinetsu_enable(void)
  1915. {
  1916. int i, rc = -EINVAL;
  1917. for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
  1918. rc = regulator_enable(vregs_tdisc[i]);
  1919. if (rc < 0) {
  1920. printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
  1921. __func__, vregs_tdisc_name[i], rc);
  1922. goto vreg_fail;
  1923. }
  1924. }
  1925. /* Enable the OE (output enable) gpio */
  1926. gpio_set_value(TDISC_OE, 1);
  1927. return 0;
  1928. vreg_fail:
  1929. while (i)
  1930. regulator_disable(vregs_tdisc[--i]);
  1931. return rc;
  1932. }
  1933. static int tdisc_shinetsu_disable(void)
  1934. {
  1935. int i, rc;
  1936. for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
  1937. rc = regulator_disable(vregs_tdisc[i]);
  1938. if (rc < 0)
  1939. printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
  1940. __func__, vregs_tdisc_name[i], rc);
  1941. }
  1942. /* Disable the OE (output enable) gpio */
  1943. gpio_set_value(TDISC_OE, 0);
  1944. return 0;
  1945. }
  1946. static struct tdisc_abs_values tdisc_abs = {
  1947. .x_max = 32,
  1948. .y_max = 32,
  1949. .x_min = -32,
  1950. .y_min = -32,
  1951. .pressure_max = 32,
  1952. .pressure_min = 0,
  1953. };
  1954. static struct tdisc_platform_data tdisc_data = {
  1955. .tdisc_setup = tdisc_shinetsu_setup,
  1956. .tdisc_release = tdisc_shinetsu_release,
  1957. .tdisc_enable = tdisc_shinetsu_enable,
  1958. .tdisc_disable = tdisc_shinetsu_disable,
  1959. .tdisc_wakeup = 1,
  1960. .tdisc_gpio = PMIC_GPIO_TDISC,
  1961. .tdisc_abs = &tdisc_abs,
  1962. };
  1963. static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
  1964. {
  1965. I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
  1966. .irq = TDISC_INT,
  1967. .platform_data = &tdisc_data,
  1968. },
  1969. };
  1970. #endif
  1971. #define TPM_PWR_EN_GPIO 94
  1972. #define TPM_RESET_GPIO 66
  1973. #define TPM_DATA_AVAIL_GPIO 67
  1974. #define TPM_ACCEPT_CMD_GPIO 68
  1975. struct tpm_gpio {
  1976. int gpio;
  1977. const char *name;
  1978. };
  1979. static struct tpm_gpio tpm_gpios[] = {
  1980. {
  1981. .gpio = TPM_PWR_EN_GPIO,
  1982. .name = "tpm_pwr_en",
  1983. },
  1984. {
  1985. .gpio = TPM_RESET_GPIO,
  1986. .name = "tpm_reset",
  1987. },
  1988. {
  1989. .gpio = TPM_ACCEPT_CMD_GPIO,
  1990. .name = "tpm_accept_cmd",
  1991. },
  1992. {
  1993. .gpio = TPM_DATA_AVAIL_GPIO,
  1994. .name = "tpm_data_avail",
  1995. },
  1996. };
  1997. static void tpm_st_i2c_gpio_release(void)
  1998. {
  1999. int i;
  2000. gpio_set_value_cansleep(TPM_RESET_GPIO, 0);
  2001. gpio_set_value_cansleep(TPM_PWR_EN_GPIO, 0);
  2002. for (i = 0; i < ARRAY_SIZE(tpm_gpios); i++)
  2003. gpio_free(tpm_gpios[i].gpio);
  2004. }
  2005. static int tpm_st_i2c_gpio_setup(void)
  2006. {
  2007. int rc = 0;
  2008. int i;
  2009. for (i = 0; i < ARRAY_SIZE(tpm_gpios); i++) {
  2010. rc = gpio_request(tpm_gpios[i].gpio, tpm_gpios[i].name);
  2011. if (rc) {
  2012. pr_err("%s: gpio request failed for gpio #%d, %s",
  2013. __func__, GPIO_PIN(tpm_gpios[i].gpio),
  2014. tpm_gpios[i].name);
  2015. goto free_gpios;
  2016. }
  2017. }
  2018. rc = gpio_direction_output(TPM_RESET_GPIO, 0);
  2019. if (rc) {
  2020. pr_err("%s: failed to setup tpm_reset\n", __func__);
  2021. goto free_gpios;
  2022. }
  2023. rc = gpio_direction_output(TPM_PWR_EN_GPIO, 1);
  2024. if (rc) {
  2025. pr_err("%s: failed to set tpm_pwr_en\n", __func__);
  2026. goto free_gpios;
  2027. }
  2028. msleep(1);
  2029. gpio_set_value_cansleep(TPM_RESET_GPIO, 1);
  2030. msleep(1);
  2031. return rc;
  2032. free_gpios:
  2033. for (i--; i >= 0; i--)
  2034. gpio_free(tpm_gpios[i].gpio);
  2035. return rc;
  2036. }
  2037. static struct tpm_st_i2c_platform_data tpm_st_i2c_data = {
  2038. .accept_cmd_gpio = TPM_ACCEPT_CMD_GPIO,
  2039. .data_avail_gpio = TPM_DATA_AVAIL_GPIO,
  2040. .accept_cmd_irq = MSM_GPIO_TO_INT(TPM_ACCEPT_CMD_GPIO),
  2041. .data_avail_irq = MSM_GPIO_TO_INT(TPM_DATA_AVAIL_GPIO),
  2042. .gpio_setup = tpm_st_i2c_gpio_setup,
  2043. .gpio_release = tpm_st_i2c_gpio_release,
  2044. };
  2045. static struct i2c_board_info msm_i2c_gsbi3_tpm_info[] = {
  2046. {
  2047. I2C_BOARD_INFO("tpm_st_i2c", 0x13),
  2048. .platform_data = &tpm_st_i2c_data,
  2049. },
  2050. };
  2051. static struct regulator *vreg_timpani_1;
  2052. static struct regulator *vreg_timpani_2;
  2053. static unsigned int msm_timpani_setup_power(void)
  2054. {
  2055. int rc;
  2056. vreg_timpani_1 = regulator_get(NULL, "8058_l0");
  2057. if (IS_ERR(vreg_timpani_1)) {
  2058. pr_err("%s: Unable to get 8058_l0\n", __func__);
  2059. return -ENODEV;
  2060. }
  2061. vreg_timpani_2 = regulator_get(NULL, "8058_s3");
  2062. if (IS_ERR(vreg_timpani_2)) {
  2063. pr_err("%s: Unable to get 8058_s3\n", __func__);
  2064. regulator_put(vreg_timpani_1);
  2065. return -ENODEV;
  2066. }
  2067. rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
  2068. if (rc) {
  2069. pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
  2070. goto fail;
  2071. }
  2072. rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
  2073. if (rc) {
  2074. pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
  2075. goto fail;
  2076. }
  2077. rc = regulator_enable(vreg_timpani_1);
  2078. if (rc) {
  2079. pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
  2080. goto fail;
  2081. }
  2082. rc = regulator_enable(vreg_timpani_2);
  2083. if (rc) {
  2084. pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
  2085. regulator_disable(vreg_timpani_1);
  2086. goto fail;
  2087. }
  2088. return rc;
  2089. fail:
  2090. regulator_put(vreg_timpani_1);
  2091. regulator_put(vreg_timpani_2);
  2092. return rc;
  2093. }
  2094. static void msm_timpani_shutdown_power(void)
  2095. {
  2096. int rc;
  2097. rc = regulator_disable(vreg_timpani_1);
  2098. if (rc)
  2099. pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
  2100. regulator_put(vreg_timpani_1);
  2101. rc = regulator_disable(vreg_timpani_2);
  2102. if (rc)
  2103. pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
  2104. regulator_put(vreg_timpani_2);
  2105. }
  2106. /* Power analog function of codec */
  2107. static struct regulator *vreg_timpani_cdc_apwr;
  2108. static int msm_timpani_codec_power(int vreg_on)
  2109. {
  2110. int rc = 0;
  2111. if (!vreg_timpani_cdc_apwr) {
  2112. vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
  2113. if (IS_ERR(vreg_timpani_cdc_apwr)) {
  2114. pr_err("%s: vreg_get failed (%ld)\n",
  2115. __func__, PTR_ERR(vreg_timpani_cdc_apwr));
  2116. rc = PTR_ERR(vreg_timpani_cdc_apwr);
  2117. return rc;
  2118. }
  2119. }
  2120. if (vreg_on) {
  2121. rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
  2122. 2200000, 2200000);
  2123. if (rc) {
  2124. pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
  2125. __func__);
  2126. goto vreg_fail;
  2127. }
  2128. rc = regulator_enable(vreg_timpani_cdc_apwr);
  2129. if (rc) {
  2130. pr_err("%s: vreg_enable failed %d\n", __func__, rc);
  2131. goto vreg_fail;
  2132. }
  2133. } else {
  2134. rc = regulator_disable(vreg_timpani_cdc_apwr);
  2135. if (rc) {
  2136. pr_err("%s: vreg_disable failed %d\n",
  2137. __func__, rc);
  2138. goto vreg_fail;
  2139. }
  2140. }
  2141. return 0;
  2142. vreg_fail:
  2143. regulator_put(vreg_timpani_cdc_apwr);
  2144. vreg_timpani_cdc_apwr = NULL;
  2145. return rc;
  2146. }
  2147. static struct marimba_codec_platform_data timpani_codec_pdata = {
  2148. .marimba_codec_power = msm_timpani_codec_power,
  2149. };
  2150. #define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
  2151. #define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
  2152. static struct marimba_platform_data timpani_pdata = {
  2153. .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
  2154. .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
  2155. .marimba_setup = msm_timpani_setup_power,
  2156. .marimba_shutdown = msm_timpani_shutdown_power,
  2157. .codec = &timpani_codec_pdata,
  2158. };
  2159. #define TIMPANI_I2C_SLAVE_ADDR 0xD
  2160. static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
  2161. {
  2162. I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
  2163. .platform_data = &timpani_pdata,
  2164. },
  2165. };
  2166. #ifdef CONFIG_PMIC8901
  2167. #define PM8901_GPIO_INT 91
  2168. static struct pm8901_gpio_platform_data pm8901_mpp_data = {
  2169. .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
  2170. .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
  2171. };
  2172. static struct resource pm8901_temp_alarm[] = {
  2173. {
  2174. .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
  2175. .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
  2176. .flags = IORESOURCE_IRQ,
  2177. },
  2178. {
  2179. .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
  2180. .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
  2181. .flags = IORESOURCE_IRQ,
  2182. },
  2183. };
  2184. static struct regulator_consumer_supply pm8901_vreg_supply[PM8901_VREG_MAX] = {
  2185. [PM8901_VREG_ID_MPP0] = REGULATOR_SUPPLY("8901_mpp0", NULL),
  2186. [PM8901_VREG_ID_USB_OTG] = REGULATOR_SUPPLY("8901_usb_otg", NULL),
  2187. [PM8901_VREG_ID_HDMI_MVS] = REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
  2188. };
  2189. #define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
  2190. _always_on, _active_high) \
  2191. [_id] = { \
  2192. .init_data = { \
  2193. .constraints = { \
  2194. .valid_modes_mask = _modes, \
  2195. .valid_ops_mask = _ops, \
  2196. .min_uV = _min_uV, \
  2197. .max_uV = _max_uV, \
  2198. .input_uV = _min_uV, \
  2199. .apply_uV = _apply_uV, \
  2200. .always_on = _always_on, \
  2201. }, \
  2202. .num_consumer_supplies = 1, \
  2203. .consumer_supplies = &pm8901_vreg_supply[_id], \
  2204. }, \
  2205. .active_high = _active_high, \
  2206. }
  2207. #define PM8901_VREG_INIT_MPP(_id, _active_high) \
  2208. PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
  2209. REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
  2210. #define PM8901_VREG_INIT_VS(_id) \
  2211. PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
  2212. REGULATOR_CHANGE_STATUS, 0, 0, 0)
  2213. static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
  2214. PM8901_VREG_INIT_MPP(PM8901_VREG_ID_MPP0, 1),
  2215. PM8901_VREG_INIT_VS(PM8901_VREG_ID_USB_OTG),
  2216. PM8901_VREG_INIT_VS(PM8901_VREG_ID_HDMI_MVS),
  2217. };
  2218. #define PM8901_VREG(_id) { \
  2219. .name = "pm8901-regulator", \
  2220. .id = _id, \
  2221. .platform_data = &pm8901_vreg_init_pdata[_id], \
  2222. .data_size = sizeof(pm8901_vreg_init_pdata[_id]), \
  2223. }
  2224. static struct mfd_cell pm8901_subdevs[] = {
  2225. { .name = "pm8901-mpp",
  2226. .id = -1,
  2227. .platform_data = &pm8901_mpp_data,
  2228. .data_size = sizeof(pm8901_mpp_data),
  2229. },
  2230. { .name = "pm8901-tm",
  2231. .id = -1,
  2232. .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
  2233. .resources = pm8901_temp_alarm,
  2234. },
  2235. PM8901_VREG(PM8901_VREG_ID_MPP0),
  2236. PM8901_VREG(PM8901_VREG_ID_USB_OTG),
  2237. PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
  2238. };
  2239. static struct pm8901_platform_data pm8901_platform_data = {
  2240. .irq_base = PM8901_IRQ_BASE,
  2241. .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
  2242. .sub_devices = pm8901_subdevs,
  2243. .irq_trigger_flags = IRQF_TRIGGER_HIGH,
  2244. };
  2245. static struct i2c_board_info pm8901_boardinfo[] __initdata = {
  2246. {
  2247. I2C_BOARD_INFO("pm8901-core", 0x55),
  2248. .irq = TLMM_SCSS_DIR_CONN_IRQ_2,
  2249. .platform_data = &pm8901_platform_data,
  2250. },
  2251. };
  2252. #endif /* CONFIG_PMIC8901 */
  2253. static struct qci_kbd_platform_data qci_i2ckbd_pdata = {
  2254. #ifdef CONFIG_KEYBOARD_QCIKBD_REPEAT
  2255. .repeat = true,
  2256. #endif
  2257. .standard_scancodes = true,
  2258. };
  2259. static struct i2c_board_info msm_i2c_gsbi3_qci_input_info[] = {
  2260. {
  2261. I2C_BOARD_INFO("qci-i2ckbd", 0x18),
  2262. .irq = 58,
  2263. .platform_data = &qci_i2ckbd_pdata,
  2264. },
  2265. {
  2266. I2C_BOARD_INFO("qci-i2cpad", 0x19),
  2267. .irq = 52,
  2268. },
  2269. {
  2270. I2C_BOARD_INFO("qci-i2cec", 0x1A),
  2271. .irq = 117,
  2272. },
  2273. };
  2274. #ifdef CONFIG_MFD_WM8994
  2275. #define WM8994_I2C_SLAVE_ADDR 0x1A
  2276. struct wm8994_pdata wm8994_platform_data = {
  2277. .gpio_defaults[0] = 0xA101,
  2278. };
  2279. static struct i2c_board_info msm_i2c_gsbi7_wm8994_info[] = {
  2280. {
  2281. I2C_BOARD_INFO("wm8994", WM8994_I2C_SLAVE_ADDR),
  2282. .platform_data = &wm8994_platform_data,
  2283. },
  2284. };
  2285. #endif /*CONFIG_MFD_WM8994 */
  2286. #ifdef CONFIG_I2C
  2287. struct i2c_registry {
  2288. int bus;
  2289. struct i2c_board_info *info;
  2290. int len;
  2291. };
  2292. static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
  2293. #ifdef CONFIG_PMIC8058
  2294. {
  2295. MSM_SSBI1_I2C_BUS_ID,
  2296. pm8058_boardinfo,
  2297. ARRAY_SIZE(pm8058_boardinfo),
  2298. },
  2299. #endif
  2300. #ifdef CONFIG_PMIC8901
  2301. {
  2302. MSM_SSBI2_I2C_BUS_ID,
  2303. pm8901_boardinfo,
  2304. ARRAY_SIZE(pm8901_boardinfo),
  2305. },
  2306. #endif
  2307. #if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
  2308. defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
  2309. {
  2310. MSM_GSBI3_QUP_I2C_BUS_ID,
  2311. msm_i2c_gsbi3_tdisc_info,
  2312. ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
  2313. },
  2314. #endif
  2315. {
  2316. MSM_GSBI7_QUP_I2C_BUS_ID,
  2317. msm_i2c_gsbi7_timpani_info,
  2318. ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
  2319. },
  2320. {
  2321. MSM_GSBI3_QUP_I2C_BUS_ID,
  2322. msm_i2c_gsbi3_qci_input_info,
  2323. ARRAY_SIZE(msm_i2c_gsbi3_qci_input_info),
  2324. },
  2325. {
  2326. MSM_GSBI3_QUP_I2C_BUS_ID,
  2327. msm_i2c_gsbi3_tpm_info,
  2328. ARRAY_SIZE(msm_i2c_gsbi3_tpm_info),
  2329. },
  2330. #ifdef CONFIG_MFD_WM8994
  2331. {
  2332. MSM_GSBI7_QUP_I2C_BUS_ID,
  2333. msm_i2c_gsbi7_wm8994_info,
  2334. ARRAY_SIZE(msm_i2c_gsbi7_wm8994_info),
  2335. },
  2336. #endif
  2337. };
  2338. #endif /* CONFIG_I2C */
  2339. static void fixup_i2c_configs(void)
  2340. {
  2341. #ifdef CONFIG_I2C
  2342. /*
  2343. * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
  2344. * implies that the regulator connected to MPP0 is enabled when
  2345. * MPP0 is low.
  2346. */
  2347. if (machine_is_msm8x60_surf() || machine_is_msm8x60_charm_surf())
  2348. pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
  2349. else
  2350. pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
  2351. #endif
  2352. }
  2353. static void register_i2c_devices(void)
  2354. {
  2355. #ifdef CONFIG_I2C
  2356. int i;
  2357. /* Run the array and install devices as appropriate */
  2358. for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
  2359. i2c_register_board_info(msm8x60_i2c_devices[i].bus,
  2360. msm8x60_i2c_devices[i].info,
  2361. msm8x60_i2c_devices[i].len);
  2362. }
  2363. #endif
  2364. }
  2365. static void __init msm8x60_init_uart12dm(void)
  2366. {
  2367. void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
  2368. /* Advanced mode */
  2369. writew(0xFFFF, fpga_mem + 0x15C);
  2370. /* FPGA_UART_SEL */
  2371. writew(0, fpga_mem + 0x172);
  2372. /* FPGA_GPIO_CONFIG_117 */
  2373. writew(1, fpga_mem + 0xEA);
  2374. /* FPGA_GPIO_CONFIG_118 */
  2375. writew(1, fpga_mem + 0xEC);
  2376. dmb();
  2377. iounmap(fpga_mem);
  2378. }
  2379. static void __init msm8x60_init_buses(void)
  2380. {
  2381. #ifdef CONFIG_I2C_QUP
  2382. void *gsbi_mem = ioremap_nocache(0x16200000, 4);
  2383. /* Setting protocol code to 0x60 for dual UART/I2C in GSBI3 */
  2384. writel(0x6 << 4, gsbi_mem);
  2385. iounmap(gsbi_mem);
  2386. msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
  2387. msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
  2388. msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
  2389. msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
  2390. msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
  2391. #endif
  2392. #if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
  2393. msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
  2394. #endif
  2395. #ifdef CONFIG_I2C_SSBI
  2396. msm_device_ssbi1.dev.platform_data = &msm_ssbi1_pdata;
  2397. msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
  2398. msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
  2399. #endif
  2400. #if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
  2401. msm_device_otg.dev.platform_data = &msm_otg_pdata;
  2402. #endif
  2403. #ifdef CONFIG_SERIAL_MSM_HS
  2404. msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
  2405. msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
  2406. #endif
  2407. #ifdef CONFIG_MSM_BUS_SCALING
  2408. /* RPM calls are only enabled on V2 */
  2409. if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
  2410. msm_bus_apps_fabric_pdata.rpm_enabled = 1;
  2411. msm_bus_sys_fabric_pdata.rpm_enabled = 1;
  2412. msm_bus_mm_fabric_pdata.rpm_enabled = 1;
  2413. msm_bus_sys_fpb_pdata.rpm_enabled = 1;
  2414. msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
  2415. }
  2416. msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
  2417. msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
  2418. msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
  2419. msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
  2420. msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
  2421. #endif
  2422. }
  2423. static void __init msm8x60_map_io(void)
  2424. {
  2425. msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
  2426. msm_map_msm8x60_io();
  2427. msm8x60_allocate_memory_regions();
  2428. }
  2429. /*
  2430. * Most segments of the EBI2 bus are disabled by default.
  2431. */
  2432. static void __init msm8x60_init_ebi2(void)
  2433. {
  2434. uint32_t ebi2_cfg;
  2435. void *ebi2_cfg_ptr;
  2436. ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
  2437. if (ebi2_cfg_ptr != 0) {
  2438. ebi2_cfg = readl(ebi2_cfg_ptr);
  2439. ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
  2440. writel(ebi2_cfg, ebi2_cfg_ptr);
  2441. iounmap(ebi2_cfg_ptr);
  2442. }
  2443. ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
  2444. if (ebi2_cfg_ptr != 0) {
  2445. /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
  2446. writel(0UL, ebi2_cfg_ptr);
  2447. /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
  2448. * LAN9221 Ethernet controller reads and writes.
  2449. * The lowest 4 bits are the read delay, the next
  2450. * 4 are the write delay. */
  2451. writel(0x031F1C99, ebi2_cfg_ptr + 0x10);
  2452. /* EBI2 CS3 muxed address/data,
  2453. * two cyc addr enable */
  2454. writel(0xA3030020, ebi2_cfg_ptr + 0x34);
  2455. iounmap(ebi2_cfg_ptr);
  2456. }
  2457. }
  2458. struct msm8x60_tlmm_cfg_struct {
  2459. unsigned gpio;
  2460. u32 flags;
  2461. };
  2462. static uint32_t msm8x60_tlmm_cfgs[] = {
  2463. #ifdef CONFIG_PMIC8058
  2464. /* PMIC8058 */
  2465. GPIO_CFG(PM8058_GPIO_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  2466. #endif
  2467. #ifdef CONFIG_SERIAL_MSM_HS
  2468. /* UARTDM_TX */
  2469. GPIO_CFG(53, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2470. /* UARTDM_RX */
  2471. GPIO_CFG(54, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2472. /* UARTDM_CTS */
  2473. GPIO_CFG(55, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2474. /* UARTDM_RFR */
  2475. GPIO_CFG(56, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2476. /* UARTDM_TX */
  2477. GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2478. /* UARTDM_RX */
  2479. GPIO_CFG(42, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA),
  2480. #endif
  2481. #ifdef CONFIG_PMIC8901
  2482. /* PMIC8901 */
  2483. GPIO_CFG(PM8901_GPIO_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  2484. #endif
  2485. };
  2486. static void __init msm8x60_init_tlmm(void)
  2487. {
  2488. unsigned n;
  2489. for (n = 0; n < ARRAY_SIZE(msm8x60_tlmm_cfgs); ++n)
  2490. gpio_tlmm_config(msm8x60_tlmm_cfgs[n], 0);
  2491. msm_gpio_install_direct_irq(PM8058_GPIO_INT, 1, 0);
  2492. msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_1,
  2493. MSM_GPIO_TO_INT(PM8058_GPIO_INT), 1);
  2494. msm_gpio_install_direct_irq(PM8901_GPIO_INT, 2, 0);
  2495. msm_set_direct_connect(TLMM_SCSS_DIR_CONN_IRQ_2,
  2496. MSM_GPIO_TO_INT(PM8901_GPIO_INT), 1);
  2497. }
  2498. #define GPIO_SDC3_WP_SWITCH (GPIO_EXPANDER_GPIO_BASE + (16 * 1) + 6)
  2499. #if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
  2500. || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
  2501. || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
  2502. || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
  2503. || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
  2504. struct msm_sdcc_gpio {
  2505. /* maximum 10 GPIOs per SDCC controller */
  2506. s16 no;
  2507. /* name of this GPIO */
  2508. const char *name;
  2509. };
  2510. #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
  2511. static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
  2512. {159, "sdc1_dat_0"},
  2513. {160, "sdc1_dat_1"},
  2514. {161, "sdc1_dat_2"},
  2515. {162, "sdc1_dat_3"},
  2516. #ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
  2517. {163, "sdc1_dat_4"},
  2518. {164, "sdc1_dat_5"},
  2519. {165, "sdc1_dat_6"},
  2520. {166, "sdc1_dat_7"},
  2521. #endif
  2522. {167, "sdc1_clk"},
  2523. {168, "sdc1_cmd"}
  2524. };
  2525. #endif
  2526. #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
  2527. static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
  2528. {143, "sdc2_dat_0"},
  2529. {144, "sdc2_dat_1"},
  2530. {145, "sdc2_dat_2"},
  2531. {146, "sdc2_dat_3"},
  2532. #ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
  2533. {147, "sdc2_dat_4"},
  2534. {148, "sdc2_dat_5"},
  2535. {149, "sdc2_dat_6"},
  2536. {150, "sdc2_dat_7"},
  2537. #endif
  2538. {151, "sdc2_cmd"},
  2539. {152, "sdc2_clk"}
  2540. };
  2541. #endif
  2542. #ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
  2543. static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
  2544. {95, "sdc5_cmd"},
  2545. {96, "sdc5_dat_3"},
  2546. {97, "sdc5_clk"},
  2547. {98, "sdc5_dat_2"},
  2548. {99, "sdc5_dat_1"},
  2549. {100, "sdc5_dat_0"}
  2550. };
  2551. #endif
  2552. struct msm_sdcc_pad_pull_cfg {
  2553. enum msm_tlmm_pull_tgt pull;
  2554. u32 pull_val;
  2555. };
  2556. struct msm_sdcc_pad_drv_cfg {
  2557. enum msm_tlmm_hdrive_tgt drv;
  2558. u32 drv_val;
  2559. };
  2560. #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
  2561. static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
  2562. {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
  2563. {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
  2564. {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
  2565. };
  2566. static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
  2567. {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
  2568. {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
  2569. };
  2570. static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
  2571. {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
  2572. {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
  2573. {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
  2574. };
  2575. static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
  2576. {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
  2577. {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
  2578. };
  2579. #endif
  2580. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  2581. static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
  2582. {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
  2583. {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
  2584. {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
  2585. };
  2586. static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
  2587. {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
  2588. {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
  2589. };
  2590. static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
  2591. {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
  2592. {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
  2593. {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
  2594. };
  2595. static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
  2596. {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
  2597. {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
  2598. };
  2599. #endif
  2600. struct msm_sdcc_pin_cfg {
  2601. /*
  2602. * = 1 if controller pins are using gpios
  2603. * = 0 if controller has dedicated MSM pins
  2604. */
  2605. u8 is_gpio;
  2606. u8 cfg_sts;
  2607. u8 gpio_data_size;
  2608. struct msm_sdcc_gpio *gpio_data;
  2609. struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
  2610. struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
  2611. struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
  2612. struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
  2613. u8 pad_drv_data_size;
  2614. u8 pad_pull_data_size;
  2615. };
  2616. static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[5] = {
  2617. #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
  2618. [0] = {
  2619. .is_gpio = 1,
  2620. .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
  2621. .gpio_data = sdc1_gpio_cfg
  2622. },
  2623. #endif
  2624. #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
  2625. [1] = {
  2626. .is_gpio = 1,
  2627. .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
  2628. .gpio_data = sdc2_gpio_cfg
  2629. },
  2630. #endif
  2631. #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
  2632. [2] = {
  2633. .is_gpio = 0,
  2634. .pad_drv_on_data = sdc3_pad_on_drv_cfg,
  2635. .pad_drv_off_data = sdc3_pad_off_drv_cfg,
  2636. .pad_pull_on_data = sdc3_pad_on_pull_cfg,
  2637. .pad_pull_off_data = sdc3_pad_off_pull_cfg,
  2638. .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
  2639. .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
  2640. },
  2641. #endif
  2642. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  2643. [3] = {
  2644. .is_gpio = 0,
  2645. .pad_drv_on_data = sdc4_pad_on_drv_cfg,
  2646. .pad_drv_off_data = sdc4_pad_off_drv_cfg,
  2647. .pad_pull_on_data = sdc4_pad_on_pull_cfg,
  2648. .pad_pull_off_data = sdc4_pad_off_pull_cfg,
  2649. .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
  2650. .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
  2651. },
  2652. #endif
  2653. #ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
  2654. [4] = {
  2655. .is_gpio = 1,
  2656. .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
  2657. .gpio_data = sdc5_gpio_cfg
  2658. }
  2659. #endif
  2660. };
  2661. static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
  2662. {
  2663. int rc = 0;
  2664. struct msm_sdcc_pin_cfg *curr;
  2665. int n;
  2666. curr = &sdcc_pin_cfg_data[dev_id - 1];
  2667. if (!curr->gpio_data)
  2668. goto out;
  2669. for (n = 0; n < curr->gpio_data_size; n++) {
  2670. if (enable) {
  2671. rc = gpio_request(curr->gpio_data[n].no,
  2672. curr->gpio_data[n].name);
  2673. if (rc) {
  2674. pr_err("%s: gpio_request(%d, %s)"
  2675. "failed", __func__,
  2676. curr->gpio_data[n].no,
  2677. curr->gpio_data[n].name);
  2678. goto free_gpios;
  2679. }
  2680. /* set direction as output for all GPIOs */
  2681. rc = gpio_direction_output(
  2682. curr->gpio_data[n].no, 1);
  2683. if (rc) {
  2684. pr_err("%s: gpio_direction_output"
  2685. "(%d, 1) failed\n", __func__,
  2686. curr->gpio_data[n].no);
  2687. goto free_gpios;
  2688. }
  2689. } else {
  2690. /*
  2691. * now free this GPIO which will put GPIO
  2692. * in low power mode and will also put GPIO
  2693. * in input mode
  2694. */
  2695. gpio_free(curr->gpio_data[n].no);
  2696. }
  2697. }
  2698. curr->cfg_sts = enable;
  2699. goto out;
  2700. free_gpios:
  2701. for (; n >= 0; n--)
  2702. gpio_free(curr->gpio_data[n].no);
  2703. out:
  2704. return rc;
  2705. }
  2706. static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
  2707. {
  2708. int rc = 0;
  2709. struct msm_sdcc_pin_cfg *curr;
  2710. int n;
  2711. curr = &sdcc_pin_cfg_data[dev_id - 1];
  2712. if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
  2713. goto out;
  2714. if (enable) {
  2715. /*
  2716. * set up the normal driver strength and
  2717. * pull config for pads
  2718. */
  2719. for (n = 0; n < curr->pad_drv_data_size; n++)
  2720. msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
  2721. curr->pad_drv_on_data[n].drv_val);
  2722. for (n = 0; n < curr->pad_pull_data_size; n++)
  2723. msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
  2724. curr->pad_pull_on_data[n].pull_val);
  2725. } else {
  2726. /* set the low power config for pads */
  2727. for (n = 0; n < curr->pad_drv_data_size; n++)
  2728. msm_tlmm_set_hdrive(
  2729. curr->pad_drv_off_data[n].drv,
  2730. curr->pad_drv_off_data[n].drv_val);
  2731. for (n = 0; n < curr->pad_pull_data_size; n++)
  2732. msm_tlmm_set_pull(
  2733. curr->pad_pull_off_data[n].pull,
  2734. curr->pad_pull_off_data[n].pull_val);
  2735. }
  2736. curr->cfg_sts = enable;
  2737. out:
  2738. return rc;
  2739. }
  2740. struct sdcc_reg {
  2741. /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
  2742. const char *reg_name;
  2743. /*
  2744. * is set voltage supported for this regulator?
  2745. * 0 = not supported, 1 = supported
  2746. */
  2747. unsigned char set_voltage_sup;
  2748. /* voltage level to be set */
  2749. unsigned int level;
  2750. /* VDD/VCC/VCCQ voltage regulator handle */
  2751. struct regulator *reg;
  2752. };
  2753. /* all 5 SDCC controllers requires VDD/VCC voltage */
  2754. static struct sdcc_reg sdcc_vdd_reg_data[5];
  2755. /* only SDCC1 requires VCCQ voltage */
  2756. static struct sdcc_reg sdcc_vccq_reg_data[1];
  2757. struct sdcc_reg_data {
  2758. struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
  2759. struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
  2760. unsigned char sts; /* regulator enable/disable status */
  2761. };
  2762. /* msm8x60 have 5 SDCC controllers */
  2763. static struct sdcc_reg_data sdcc_vreg_data[5];
  2764. /* this init function should be called only once for each SDCC */
  2765. static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
  2766. {
  2767. int rc = 0;
  2768. struct sdcc_reg *curr_vdd_reg;
  2769. struct sdcc_reg *curr_vccq_reg;
  2770. struct sdcc_reg_data *curr;
  2771. curr = &sdcc_vreg_data[dev_id - 1];
  2772. curr_vdd_reg = curr->vdd_data;
  2773. curr_vccq_reg = curr->vccq_data;
  2774. if (init) {
  2775. /*
  2776. * get the regulator handle from voltage regulator framework
  2777. * and then try to set the voltage level for the regulator
  2778. */
  2779. if (curr_vdd_reg) {
  2780. curr_vdd_reg->reg =
  2781. regulator_get(NULL, curr_vdd_reg->reg_name);
  2782. if (IS_ERR(curr_vdd_reg->reg)) {
  2783. rc = PTR_ERR(curr_vdd_reg->reg);
  2784. pr_err("%s: regulator_get(%s) failed = %d\n",
  2785. __func__, curr_vdd_reg->reg_name, rc);
  2786. goto out;
  2787. }
  2788. if (curr_vdd_reg->set_voltage_sup) {
  2789. rc = regulator_set_voltage(curr_vdd_reg->reg,
  2790. curr_vdd_reg->level,
  2791. curr_vdd_reg->level);
  2792. if (rc) {
  2793. pr_err("%s: regulator_set_voltage(%s)"
  2794. " = %d\n", __func__,
  2795. curr_vdd_reg->reg_name, rc);
  2796. goto vdd_reg_put;
  2797. }
  2798. }
  2799. }
  2800. if (curr_vccq_reg) {
  2801. curr_vccq_reg->reg =
  2802. regulator_get(NULL, curr_vccq_reg->reg_name);
  2803. if (IS_ERR(curr_vccq_reg->reg)) {
  2804. rc = PTR_ERR(curr_vccq_reg->reg);
  2805. pr_err("%s: regulator get of %s failed (%d)\n",
  2806. __func__, curr_vccq_reg->reg_name, rc);
  2807. goto vdd_reg_put;
  2808. }
  2809. if (curr_vccq_reg->set_voltage_sup) {
  2810. rc = regulator_set_voltage(curr_vccq_reg->reg,
  2811. curr_vccq_reg->level,
  2812. curr_vccq_reg->level);
  2813. if (rc) {
  2814. pr_err("%s: regulator_set_voltage()"
  2815. "= %d\n", __func__, rc);
  2816. goto vccq_reg_put;
  2817. }
  2818. }
  2819. }
  2820. } else {
  2821. /* deregister with voltage regulator framework */
  2822. rc = 0;
  2823. goto vccq_reg_put;
  2824. }
  2825. goto out;
  2826. vccq_reg_put:
  2827. if (curr_vccq_reg)
  2828. regulator_put(curr_vccq_reg->reg);
  2829. vdd_reg_put:
  2830. if (curr_vdd_reg)
  2831. regulator_put(curr_vdd_reg->reg);
  2832. out:
  2833. return rc;
  2834. }
  2835. static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
  2836. {
  2837. int rc = 0;
  2838. struct sdcc_reg *curr_vdd_reg;
  2839. struct sdcc_reg *curr_vccq_reg;
  2840. struct sdcc_reg_data *curr;
  2841. curr = &sdcc_vreg_data[dev_id - 1];
  2842. curr_vdd_reg = curr->vdd_data;
  2843. curr_vccq_reg = curr->vccq_data;
  2844. /* check if regulators are initialized or not? */
  2845. if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
  2846. (curr_vccq_reg && !curr_vccq_reg->reg)) {
  2847. /* initialize voltage regulators required for this SDCC */
  2848. rc = msm_sdcc_vreg_init(dev_id, 1);
  2849. if (rc) {
  2850. pr_err("%s: regulator init failed = %d\n",
  2851. __func__, rc);
  2852. goto out;
  2853. }
  2854. }
  2855. if (curr->sts == enable)
  2856. goto out;
  2857. if (enable) {
  2858. if (curr_vdd_reg) {
  2859. rc = regulator_enable(curr_vdd_reg->reg);
  2860. if (rc) {
  2861. pr_err("%s: regulator_enable(%s) failed"
  2862. " = %d\n", __func__,
  2863. curr_vdd_reg->reg_name, rc);
  2864. goto out;
  2865. }
  2866. }
  2867. if (curr_vccq_reg) {
  2868. rc = regulator_enable(curr_vccq_reg->reg);
  2869. if (rc) {
  2870. pr_err("%s: regulator_enable(%s) failed"
  2871. " = %d\n", __func__,
  2872. curr_vccq_reg->reg_name, rc);
  2873. goto vdd_reg_disable;
  2874. }
  2875. }
  2876. /*
  2877. * now we can safely say that all required regulators
  2878. * are enabled for this SDCC
  2879. */
  2880. curr->sts = enable;
  2881. } else {
  2882. if (curr_vdd_reg) {
  2883. rc = regulator_disable(curr_vdd_reg->reg);
  2884. if (rc) {
  2885. pr_err("%s: regulator_disable(%s) = %d\n",
  2886. __func__, curr_vdd_reg->reg_name, rc);
  2887. goto out;
  2888. }
  2889. }
  2890. if (curr_vccq_reg) {
  2891. rc = regulator_disable(curr_vccq_reg->reg);
  2892. if (rc) {
  2893. pr_err("%s: regulator_disable(%s) = %d\n",
  2894. __func__, curr_vccq_reg->reg_name, rc);
  2895. goto out;
  2896. }
  2897. }
  2898. /*
  2899. * now we can safely say that all required
  2900. * regulators are disabled for this SDCC
  2901. */
  2902. curr->sts = enable;
  2903. }
  2904. goto out;
  2905. vdd_reg_disable:
  2906. if (curr_vdd_reg)
  2907. regulator_disable(curr_vdd_reg->reg);
  2908. out:
  2909. return rc;
  2910. }
  2911. static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
  2912. {
  2913. u32 rc_pin_cfg = 0;
  2914. u32 rc_vreg_cfg = 0;
  2915. u32 rc = 0;
  2916. struct platform_device *pdev;
  2917. struct msm_sdcc_pin_cfg *curr_pin_cfg;
  2918. pdev = container_of(dv, struct platform_device, dev);
  2919. /* setup gpio/pad */
  2920. curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
  2921. if (curr_pin_cfg->cfg_sts == !!vdd)
  2922. goto setup_vreg;
  2923. if (curr_pin_cfg->is_gpio)
  2924. rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
  2925. else
  2926. rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
  2927. setup_vreg:
  2928. /* setup voltage regulators */
  2929. rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
  2930. if (rc_pin_cfg || rc_vreg_cfg)
  2931. rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
  2932. return rc;
  2933. }
  2934. static int msm_sdc3_get_wpswitch(struct device *dev)
  2935. {
  2936. struct platform_device *pdev;
  2937. int status;
  2938. pdev = container_of(dev, struct platform_device, dev);
  2939. status = gpio_request(GPIO_SDC3_WP_SWITCH, "SD_WP_Switch");
  2940. if (status) {
  2941. pr_err("%s:Failed to request GPIO %d\n",
  2942. __func__, GPIO_SDC3_WP_SWITCH);
  2943. } else {
  2944. status = gpio_get_value_cansleep(GPIO_SDC3_WP_SWITCH);
  2945. pr_info("%s: WP Status for Slot %d = %d\n", __func__,
  2946. pdev->id, status);
  2947. gpio_free(GPIO_SDC3_WP_SWITCH);
  2948. }
  2949. return (unsigned int) status;
  2950. }
  2951. #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
  2952. #ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
  2953. static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
  2954. {
  2955. int status;
  2956. status = !(gpio_get_value_cansleep(
  2957. PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
  2958. return (unsigned int) status;
  2959. }
  2960. #endif
  2961. #endif
  2962. #endif
  2963. #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
  2964. static struct mmc_platform_data msm8x60_sdc1_data = {
  2965. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
  2966. .translate_vdd = msm_sdcc_setup_power,
  2967. #ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
  2968. .mmc_bus_width = MMC_CAP_8_BIT_DATA,
  2969. #else
  2970. .mmc_bus_width = MMC_CAP_4_BIT_DATA,
  2971. #endif
  2972. .msmsdcc_fmin = 400000,
  2973. .msmsdcc_fmid = 24000000,
  2974. .msmsdcc_fmax = 48000000,
  2975. .nonremovable = 1,
  2976. };
  2977. #endif
  2978. #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
  2979. static struct mmc_platform_data msm8x60_sdc2_data = {
  2980. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
  2981. .translate_vdd = msm_sdcc_setup_power,
  2982. .mmc_bus_width = MMC_CAP_4_BIT_DATA,
  2983. .msmsdcc_fmin = 400000,
  2984. .msmsdcc_fmid = 24000000,
  2985. .msmsdcc_fmax = 48000000,
  2986. .nonremovable = 0,
  2987. };
  2988. #endif
  2989. #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
  2990. static struct mmc_platform_data msm8x60_sdc3_data = {
  2991. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
  2992. .translate_vdd = msm_sdcc_setup_power,
  2993. .mmc_bus_width = MMC_CAP_4_BIT_DATA,
  2994. .wpswitch = msm_sdc3_get_wpswitch,
  2995. #ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
  2996. .status = msm8x60_sdcc_slot_status,
  2997. .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
  2998. PMIC_GPIO_SDC3_DET - 1),
  2999. .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  3000. #endif
  3001. .msmsdcc_fmin = 400000,
  3002. .msmsdcc_fmid = 24000000,
  3003. .msmsdcc_fmax = 48000000,
  3004. .nonremovable = 0,
  3005. };
  3006. #endif
  3007. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  3008. static struct mmc_platform_data msm8x60_sdc4_data = {
  3009. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
  3010. .translate_vdd = msm_sdcc_setup_power,
  3011. .mmc_bus_width = MMC_CAP_4_BIT_DATA,
  3012. .msmsdcc_fmin = 400000,
  3013. .msmsdcc_fmid = 24000000,
  3014. .msmsdcc_fmax = 48000000,
  3015. .nonremovable = 1,
  3016. #ifdef CONFIG_MMC_MSM_SDC4_DUMMY52_REQUIRED
  3017. .dummy52_required = 1,
  3018. #endif
  3019. };
  3020. #endif
  3021. #ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
  3022. static struct mmc_platform_data msm8x60_sdc5_data = {
  3023. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
  3024. .translate_vdd = msm_sdcc_setup_power,
  3025. .mmc_bus_width = MMC_CAP_4_BIT_DATA,
  3026. .msmsdcc_fmin = 400000,
  3027. .msmsdcc_fmid = 24000000,
  3028. .msmsdcc_fmax = 48000000,
  3029. .nonremovable = 0,
  3030. };
  3031. #endif
  3032. static void __init msm8x60_init_mmc(void)
  3033. {
  3034. #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
  3035. /* SDCC1 : eMMC card connected */
  3036. sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
  3037. sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
  3038. sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
  3039. sdcc_vreg_data[0].vdd_data->level = 2850000;
  3040. sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
  3041. sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
  3042. sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
  3043. msm_add_sdcc(1, &msm8x60_sdc1_data);
  3044. #endif
  3045. #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
  3046. /* SDCC2 : NC (no card connected)*/
  3047. sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
  3048. sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
  3049. sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
  3050. sdcc_vreg_data[1].vdd_data->level = 1800000;
  3051. sdcc_vreg_data[1].vccq_data = NULL;
  3052. msm_add_sdcc(2, &msm8x60_sdc2_data);
  3053. #endif
  3054. #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
  3055. /* SDCC3 : External card slot connected */
  3056. sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
  3057. sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
  3058. sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
  3059. sdcc_vreg_data[2].vdd_data->level = 2850000;
  3060. sdcc_vreg_data[2].vccq_data = NULL;
  3061. msm_add_sdcc(3, &msm8x60_sdc3_data);
  3062. #endif
  3063. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  3064. /* SDCC4 : NC (no card connected)*/
  3065. sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
  3066. sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
  3067. sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
  3068. sdcc_vreg_data[3].vdd_data->level = 1800000;
  3069. sdcc_vreg_data[3].vccq_data = NULL;
  3070. msm_add_sdcc(4, &msm8x60_sdc4_data);
  3071. #endif
  3072. #ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
  3073. /* SDCC4 : NC (no card connected)*/
  3074. sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
  3075. sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
  3076. sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
  3077. sdcc_vreg_data[4].vdd_data->level = 1800000;
  3078. sdcc_vreg_data[4].vccq_data = NULL;
  3079. msm_add_sdcc(5, &msm8x60_sdc5_data);
  3080. #endif
  3081. }
  3082. static int wifi_power(int on)
  3083. {
  3084. int rc = 0;
  3085. static struct regulator *reg_8901_l2;
  3086. if (reg_8901_l2 == NULL) {
  3087. reg_8901_l2 = regulator_get(NULL, "8901_l2");
  3088. if (IS_ERR(reg_8901_l2)) {
  3089. pr_err("%s: Unable to get 8901_l2\n", __func__);
  3090. return PTR_ERR(reg_8901_l2);
  3091. }
  3092. }
  3093. if (on) {
  3094. rc = regulator_set_voltage(reg_8901_l2, 3300000, 3300000);
  3095. if (rc) {
  3096. pr_err("%s: error set 8901_l2 to 3.3V\n", __func__);
  3097. goto wifi_power_fail;
  3098. }
  3099. rc = regulator_enable(reg_8901_l2);
  3100. if (rc) {
  3101. pr_err("%s: 8901_l2 enable failed, rc=%d\n",
  3102. __func__, rc);
  3103. goto wifi_power_fail;
  3104. }
  3105. } else {
  3106. if (regulator_is_enabled(reg_8901_l2)) {
  3107. rc = regulator_disable(reg_8901_l2);
  3108. if (rc)
  3109. pr_warning("%s: 8901_l2 disable failed, "
  3110. "rc=%d\n", __func__, rc);
  3111. }
  3112. }
  3113. return rc;
  3114. wifi_power_fail:
  3115. regulator_put(reg_8901_l2);
  3116. return rc;
  3117. }
  3118. static uint32_t lcd_panel_gpios[] = {
  3119. GPIO_CFG(0, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_pclk */
  3120. GPIO_CFG(1, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_hsync*/
  3121. GPIO_CFG(2, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_vsync*/
  3122. GPIO_CFG(3, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_den */
  3123. GPIO_CFG(4, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red7 */
  3124. GPIO_CFG(5, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red6 */
  3125. GPIO_CFG(6, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red5 */
  3126. GPIO_CFG(7, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red4 */
  3127. GPIO_CFG(8, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red3 */
  3128. GPIO_CFG(9, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red2 */
  3129. GPIO_CFG(10, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red1 */
  3130. GPIO_CFG(11, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_red0 */
  3131. GPIO_CFG(12, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn7 */
  3132. GPIO_CFG(13, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn6 */
  3133. GPIO_CFG(14, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn5 */
  3134. GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn4 */
  3135. GPIO_CFG(16, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn3 */
  3136. GPIO_CFG(17, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn2 */
  3137. GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn1 */
  3138. GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_grn0 */
  3139. GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu7 */
  3140. GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu6 */
  3141. GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu5 */
  3142. GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu4 */
  3143. GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu3 */
  3144. GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu2 */
  3145. GPIO_CFG(26, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu1 */
  3146. GPIO_CFG(27, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), /* lcdc_blu0 */
  3147. };
  3148. static struct regulator *reg_8901_l1;
  3149. static struct regulator *vga_5v_reg;
  3150. static int lcdc_vga_panel_power(int on)
  3151. {
  3152. int rc = 0;
  3153. if (on) {
  3154. rc = regulator_enable(vga_5v_reg);
  3155. if (rc) {
  3156. pr_err("%s: VGA 5v reg enable failed, rc=%d\n",
  3157. __func__, rc);
  3158. return rc;
  3159. }
  3160. } else
  3161. if (regulator_is_enabled(vga_5v_reg)) {
  3162. rc = regulator_disable(vga_5v_reg);
  3163. if (rc)
  3164. pr_warning("%s: VGA 5v reg disable failed, "
  3165. "rc=%d\n", __func__, rc);
  3166. }
  3167. return rc;
  3168. }
  3169. static void lcd_panel_power(int on)
  3170. {
  3171. int n;
  3172. int rc = 0;
  3173. if (!reg_8901_l1) {
  3174. reg_8901_l1 = regulator_get(NULL, "8901_l1");
  3175. if (IS_ERR(reg_8901_l1)) {
  3176. pr_err("%s: Unable to get 8901_l1\n", __func__);
  3177. return;
  3178. }
  3179. }
  3180. if (!vga_5v_reg) {
  3181. vga_5v_reg = regulator_get(NULL, "8901_usb_otg");
  3182. if (IS_ERR(vga_5v_reg)) {
  3183. pr_err("%s: Unable to get 8901_usb_otg\n", __func__);
  3184. goto fail_get_vga_5v;
  3185. }
  3186. }
  3187. if (on) {
  3188. rc = regulator_set_voltage(reg_8901_l1, 3300000, 3300000);
  3189. if (rc) {
  3190. pr_err("%s: error set 8901_l1 to 3.3V\n", __func__);
  3191. goto fail_l1_enable;
  3192. }
  3193. rc = regulator_enable(reg_8901_l1);
  3194. if (rc) {
  3195. pr_err("%s: 8901_l1 enable failed, rc=%d\n",
  3196. __func__, rc);
  3197. goto fail_l1_enable;
  3198. }
  3199. if (vga_enabled) {
  3200. if (lcdc_vga_panel_power(1))
  3201. goto fail_vga_enable;
  3202. } else if (lcdc_vga_panel_power(0))
  3203. pr_warning("%s: failed to turn off VGA "
  3204. "display, rc=%d\n", __func__, rc);
  3205. } else {
  3206. if (regulator_is_enabled(reg_8901_l1)) {
  3207. rc = regulator_disable(reg_8901_l1);
  3208. if (rc)
  3209. pr_warning("%s: 8901_l1 disable failed, "
  3210. "rc=%d\n", __func__, rc);
  3211. }
  3212. lcdc_vga_panel_power(0);
  3213. }
  3214. /*TODO if on = 0 free the gpio's */
  3215. for (n = 0; n < ARRAY_SIZE(lcd_panel_gpios); ++n)
  3216. gpio_tlmm_config(lcd_panel_gpios[n], 0);
  3217. return;
  3218. fail_get_vga_5v:
  3219. regulator_put(reg_8901_l1);
  3220. reg_8901_l1 = NULL;
  3221. return;
  3222. fail_vga_enable:
  3223. regulator_disable(reg_8901_l1);
  3224. fail_l1_enable:
  3225. regulator_put(reg_8901_l1);
  3226. regulator_put(vga_5v_reg);
  3227. reg_8901_l1 = NULL;
  3228. vga_5v_reg = NULL;
  3229. }
  3230. #ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
  3231. #define _GET_REGULATOR(var, name) do { \
  3232. var = regulator_get(NULL, name); \
  3233. if (IS_ERR(var)) { \
  3234. pr_err("'%s' regulator not found, rc=%ld\n", \
  3235. name, IS_ERR(var)); \
  3236. var = NULL; \
  3237. return -ENODEV; \
  3238. } \
  3239. } while (0)
  3240. static int hdmi_enable_5v(int on)
  3241. {
  3242. static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
  3243. static struct regulator *reg_8901_mpp0; /* External 5V */
  3244. static int prev_on;
  3245. int rc;
  3246. if (on == prev_on)
  3247. return 0;
  3248. if (!reg_8901_hdmi_mvs)
  3249. _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
  3250. if (!reg_8901_mpp0)
  3251. _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
  3252. if (on) {
  3253. rc = regulator_enable(reg_8901_mpp0);
  3254. if (rc) {
  3255. pr_err("'%s' regulator enable failed, rc=%d\n",
  3256. "reg_8901_mpp0", rc);
  3257. return rc;
  3258. }
  3259. rc = regulator_enable(reg_8901_hdmi_mvs);
  3260. if (rc) {
  3261. pr_err("'%s' regulator enable failed, rc=%d\n",
  3262. "8901_hdmi_mvs", rc);
  3263. return rc;
  3264. }
  3265. pr_info("%s(on): success\n", __func__);
  3266. } else {
  3267. rc = regulator_disable(reg_8901_hdmi_mvs);
  3268. if (rc)
  3269. pr_warning("'%s' regulator disable failed, rc=%d\n",
  3270. "8901_hdmi_mvs", rc);
  3271. rc = regulator_disable(reg_8901_mpp0);
  3272. if (rc)
  3273. pr_warning("'%s' regulator disable failed, rc=%d\n",
  3274. "reg_8901_mpp0", rc);
  3275. pr_info("%s(off): success\n", __func__);
  3276. }
  3277. prev_on = on;
  3278. return 0;
  3279. }
  3280. static int hdmi_core_power(int on, int show)
  3281. {
  3282. static struct regulator *reg_8058_l16; /* VDD_HDMI */
  3283. static int prev_on;
  3284. int rc;
  3285. if (on == prev_on)
  3286. return 0;
  3287. if (!reg_8058_l16)
  3288. _GET_REGULATOR(reg_8058_l16, "8058_l16");
  3289. if (on) {
  3290. rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
  3291. if (!rc)
  3292. rc = regulator_enable(reg_8058_l16);
  3293. if (rc) {
  3294. pr_err("'%s' regulator enable failed, rc=%d\n",
  3295. "8058_l16", rc);
  3296. return rc;
  3297. }
  3298. rc = gpio_request(170, "HDMI_DDC_CLK");
  3299. if (rc) {
  3300. pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
  3301. "HDMI_DDC_CLK", 170, rc);
  3302. goto error1;
  3303. }
  3304. rc = gpio_request(171, "HDMI_DDC_DATA");
  3305. if (rc) {
  3306. pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
  3307. "HDMI_DDC_DATA", 171, rc);
  3308. goto error2;
  3309. }
  3310. rc = gpio_request(172, "HDMI_HPD");
  3311. if (rc) {
  3312. pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
  3313. "HDMI_HPD", 172, rc);
  3314. goto error3;
  3315. }
  3316. pr_info("%s(on): success\n", __func__);
  3317. } else {
  3318. gpio_free(170);
  3319. gpio_free(171);
  3320. gpio_free(172);
  3321. rc = regulator_disable(reg_8058_l16);
  3322. if (rc)
  3323. pr_warning("'%s' regulator disable failed, rc=%d\n",
  3324. "8058_l16", rc);
  3325. pr_info("%s(off): success\n", __func__);
  3326. }
  3327. prev_on = on;
  3328. return 0;
  3329. error3:
  3330. gpio_free(171);
  3331. error2:
  3332. gpio_free(170);
  3333. error1:
  3334. regulator_disable(reg_8058_l16);
  3335. return rc;
  3336. }
  3337. static int hdmi_cec_power(int on)
  3338. {
  3339. static struct regulator *reg_8901_l3; /* HDMI_CEC */
  3340. static int prev_on;
  3341. int rc;
  3342. if (on == prev_on)
  3343. return 0;
  3344. if (!reg_8901_l3)
  3345. _GET_REGULATOR(reg_8901_l3, "8901_l3");
  3346. if (on) {
  3347. rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
  3348. if (!rc)
  3349. rc = regulator_enable(reg_8901_l3);
  3350. if (rc) {
  3351. pr_err("'%s' regulator enable failed, rc=%d\n",
  3352. "8901_l3", rc);
  3353. return rc;
  3354. }
  3355. rc = gpio_request(169, "HDMI_CEC_VAR");
  3356. if (rc) {
  3357. pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
  3358. "HDMI_CEC_VAR", 169, rc);
  3359. goto error;
  3360. }
  3361. pr_info("%s(on): success\n", __func__);
  3362. } else {
  3363. gpio_free(169);
  3364. rc = regulator_disable(reg_8901_l3);
  3365. if (rc)
  3366. pr_warning("'%s' regulator disable failed, rc=%d\n",
  3367. "8901_l3", rc);
  3368. pr_info("%s(off): success\n", __func__);
  3369. }
  3370. prev_on = on;
  3371. return 0;
  3372. error:
  3373. regulator_disable(reg_8901_l3);
  3374. return rc;
  3375. }
  3376. #undef _GET_REGULATOR
  3377. #endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
  3378. #define GPIO_DAC_PWR_SAV 104
  3379. static int msm_fb_lcdc_gpio_config(int on)
  3380. {
  3381. if (vga_enabled) {
  3382. /* VGA DAC power save */
  3383. gpio_set_value_cansleep(GPIO_DAC_PWR_SAV, !on);
  3384. /* backlight */
  3385. gpio_set_value_cansleep(30, 0);
  3386. } else {
  3387. /* VGA DAC power save */
  3388. gpio_set_value_cansleep(GPIO_DAC_PWR_SAV, 1);
  3389. /* backlight */
  3390. gpio_set_value_cansleep(30, !!on);
  3391. }
  3392. return 0;
  3393. }
  3394. static int lcdc_panel_power(int on)
  3395. {
  3396. int flag_on = !!on;
  3397. static int lcdc_power_save_on;
  3398. if (lcdc_power_save_on == flag_on)
  3399. return 0;
  3400. lcdc_power_save_on = flag_on;
  3401. lcd_panel_power(on);
  3402. return 0;
  3403. }
  3404. #ifdef CONFIG_MSM_BUS_SCALING
  3405. static struct msm_bus_vectors mdp_init_vectors[] = {
  3406. /* For now, 0th array entry is reserved.
  3407. * Please leave 0 as is and don't use it
  3408. */
  3409. {
  3410. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3411. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3412. .ab = 0,
  3413. .ib = 0,
  3414. },
  3415. /* Master and slaves can be from different fabrics */
  3416. {
  3417. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3418. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3419. .ab = 0,
  3420. .ib = 0,
  3421. },
  3422. };
  3423. static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
  3424. /* Default case static display/UI/2d/3d if FB SMI */
  3425. {
  3426. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3427. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3428. .ab = 147460000,
  3429. .ib = 184325000,
  3430. },
  3431. /* Master and slaves can be from different fabrics */
  3432. {
  3433. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3434. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3435. .ab = 0,
  3436. .ib = 0,
  3437. },
  3438. };
  3439. static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
  3440. /* Default case static display/UI/2d/3d if FB SMI */
  3441. {
  3442. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3443. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3444. .ab = 0,
  3445. .ib = 0,
  3446. },
  3447. /* Master and slaves can be from different fabrics */
  3448. {
  3449. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3450. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3451. .ab = 334080000,
  3452. .ib = 417600000,
  3453. },
  3454. };
  3455. static struct msm_bus_vectors mdp_vga_vectors[] = {
  3456. /* VGA and less video */
  3457. {
  3458. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3459. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3460. .ab = 175110000,
  3461. .ib = 218887500,
  3462. },
  3463. {
  3464. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3465. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3466. .ab = 175110000,
  3467. .ib = 218887500,
  3468. },
  3469. };
  3470. static struct msm_bus_vectors mdp_720p_vectors[] = {
  3471. /* 720p and less video */
  3472. {
  3473. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3474. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3475. .ab = 230400000,
  3476. .ib = 288000000,
  3477. },
  3478. /* Master and slaves can be from different fabrics */
  3479. {
  3480. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3481. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3482. .ab = 230400000,
  3483. .ib = 288000000,
  3484. },
  3485. };
  3486. static struct msm_bus_vectors mdp_1080p_vectors[] = {
  3487. /* 1080p and less video */
  3488. {
  3489. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3490. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3491. .ab = 334080000,
  3492. .ib = 417600000,
  3493. },
  3494. /* Master and slaves can be from different fabrics */
  3495. {
  3496. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3497. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3498. .ab = 334080000,
  3499. .ib = 417600000,
  3500. },
  3501. };
  3502. static struct msm_bus_paths mdp_bus_scale_usecases[] = {
  3503. {
  3504. ARRAY_SIZE(mdp_init_vectors),
  3505. mdp_init_vectors,
  3506. },
  3507. {
  3508. ARRAY_SIZE(mdp_sd_smi_vectors),
  3509. mdp_sd_smi_vectors,
  3510. },
  3511. {
  3512. ARRAY_SIZE(mdp_sd_ebi_vectors),
  3513. mdp_sd_ebi_vectors,
  3514. },
  3515. {
  3516. ARRAY_SIZE(mdp_vga_vectors),
  3517. mdp_vga_vectors,
  3518. },
  3519. {
  3520. ARRAY_SIZE(mdp_720p_vectors),
  3521. mdp_720p_vectors,
  3522. },
  3523. {
  3524. ARRAY_SIZE(mdp_1080p_vectors),
  3525. mdp_1080p_vectors,
  3526. },
  3527. };
  3528. static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
  3529. mdp_bus_scale_usecases,
  3530. ARRAY_SIZE(mdp_bus_scale_usecases),
  3531. };
  3532. #endif
  3533. #ifdef CONFIG_MSM_BUS_SCALING
  3534. static struct msm_bus_vectors dtv_bus_init_vectors[] = {
  3535. /* For now, 0th array entry is reserved.
  3536. * Please leave 0 as is and don't use it
  3537. */
  3538. {
  3539. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3540. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3541. .ab = 0,
  3542. .ib = 0,
  3543. },
  3544. /* Master and slaves can be from different fabrics */
  3545. {
  3546. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3547. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3548. .ab = 0,
  3549. .ib = 0,
  3550. },
  3551. };
  3552. static struct msm_bus_vectors dtv_bus_def_vectors[] = {
  3553. /* For now, 0th array entry is reserved.
  3554. * Please leave 0 as is and don't use it
  3555. */
  3556. {
  3557. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3558. .dst = MSM_BUS_MMSS_SLAVE_SMI,
  3559. .ab = 435456000,
  3560. .ib = 544320000,
  3561. },
  3562. /* Master and slaves can be from different fabrics */
  3563. {
  3564. .src = MSM_BUS_MMSS_MASTER_MDP_PORT0,
  3565. .dst = MSM_BUS_APPSS_SLAVE_EBI_CH0,
  3566. .ab = 435456000,
  3567. .ib = 544320000,
  3568. },
  3569. };
  3570. static struct msm_bus_paths dtv_bus_scale_usecases[] = {
  3571. {
  3572. ARRAY_SIZE(dtv_bus_init_vectors),
  3573. dtv_bus_init_vectors,
  3574. },
  3575. {
  3576. ARRAY_SIZE(dtv_bus_def_vectors),
  3577. dtv_bus_def_vectors,
  3578. },
  3579. };
  3580. static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
  3581. dtv_bus_scale_usecases,
  3582. ARRAY_SIZE(dtv_bus_scale_usecases),
  3583. };
  3584. static struct lcdc_platform_data dtv_pdata = {
  3585. .bus_scale_table = &dtv_bus_scale_pdata,
  3586. };
  3587. #endif
  3588. static struct lcdc_platform_data lcdc_pdata = {
  3589. .lcdc_power_save = lcdc_panel_power,
  3590. .lcdc_gpio_config = msm_fb_lcdc_gpio_config,
  3591. };
  3592. static int mdp_core_clk_rate_table[] = {
  3593. 59080000,
  3594. 128000000,
  3595. 160000000,
  3596. 200000000,
  3597. 200000000,
  3598. };
  3599. static struct msm_panel_common_pdata mdp_pdata = {
  3600. .mdp_core_clk_rate = 200000000,
  3601. .mdp_core_clk_table = mdp_core_clk_rate_table,
  3602. .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
  3603. #ifdef CONFIG_MSM_BUS_SCALING
  3604. .mdp_bus_scale_table = &mdp_bus_scale_pdata,
  3605. #endif
  3606. };
  3607. static void __init msm_fb_add_devices(void)
  3608. {
  3609. gpio_request(GPIO_DAC_PWR_SAV, "DAC_PWR_SAV");
  3610. gpio_direction_output(GPIO_DAC_PWR_SAV, 1);
  3611. gpio_request(30, "BACKLIGHT_EN");
  3612. gpio_direction_output(30, 0);
  3613. msm_fb_register_device("mdp", &mdp_pdata);
  3614. msm_fb_register_device("lcdc", &lcdc_pdata);
  3615. msm_fb_register_device("mipi_dsi", 0);
  3616. #ifdef CONFIG_MSM_BUS_SCALING
  3617. msm_fb_register_device("dtv", &dtv_pdata);
  3618. #endif
  3619. }
  3620. static void __init msm8x60_cfg_smsc911x(void)
  3621. {
  3622. smsc911x_resources[1].start =
  3623. PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
  3624. smsc911x_resources[1].end =
  3625. PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
  3626. }
  3627. #ifdef CONFIG_MSM_RPM
  3628. static struct msm_rpm_platform_data msm_rpm_data = {
  3629. .reg_base_addrs = {
  3630. [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
  3631. [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
  3632. [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
  3633. [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
  3634. },
  3635. .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
  3636. .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
  3637. .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
  3638. };
  3639. #endif
  3640. static uint32_t auxpcm_gpio_table[] = {
  3641. GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  3642. GPIO_CFG(112, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  3643. GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  3644. GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
  3645. };
  3646. static void msm_auxpcm_init(void)
  3647. {
  3648. gpio_tlmm_config(auxpcm_gpio_table[0], GPIO_CFG_ENABLE);
  3649. gpio_tlmm_config(auxpcm_gpio_table[1], GPIO_CFG_ENABLE);
  3650. gpio_tlmm_config(auxpcm_gpio_table[2], GPIO_CFG_ENABLE);
  3651. gpio_tlmm_config(auxpcm_gpio_table[3], GPIO_CFG_ENABLE);
  3652. }
  3653. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  3654. #define WLAN_PWDN_N_GPIO 118
  3655. static void enable_wlan_bt(void)
  3656. {
  3657. int rc = 0;
  3658. rc = gpio_request(WLAN_PWDN_N_GPIO, "WLAN_PWDN_N");
  3659. if (rc) {
  3660. pr_err("%s: WLAN_PWDN_N gpio %d request failed: %d\n",
  3661. __func__, WLAN_PWDN_N_GPIO, rc);
  3662. return;
  3663. }
  3664. rc = gpio_direction_output(WLAN_PWDN_N_GPIO, 0);
  3665. if (rc) {
  3666. pr_err("%s: gpio_direction_output %d failed: %d\n",
  3667. __func__, WLAN_PWDN_N_GPIO, rc);
  3668. gpio_free(WLAN_PWDN_N_GPIO);
  3669. return;
  3670. }
  3671. gpio_set_value(WLAN_PWDN_N_GPIO, 1);
  3672. usleep(5);
  3673. gpio_set_value(WLAN_PWDN_N_GPIO, 0);
  3674. usleep(5);
  3675. gpio_set_value(WLAN_PWDN_N_GPIO, 1);
  3676. }
  3677. #endif
  3678. struct msm_board_data {
  3679. struct msm_gpiomux_configs *gpiomux_cfgs;
  3680. };
  3681. static struct msm_board_data msm8x60_qrdc_board_data __initdata = {
  3682. .gpiomux_cfgs = msm8x60_qrdc_gpiomux_cfgs,
  3683. };
  3684. static void __init msm8x60_init(struct msm_board_data *board_data)
  3685. {
  3686. /*
  3687. * Initialize RPM first as other drivers and devices may need
  3688. * it for their initialization.
  3689. */
  3690. #ifdef CONFIG_MSM_RPM
  3691. BUG_ON(msm_rpm_init(&msm_rpm_data));
  3692. #endif
  3693. if (msm_xo_init())
  3694. pr_err("Failed to initialize XO votes\n");
  3695. if (socinfo_init() < 0)
  3696. printk(KERN_ERR "%s: socinfo_init() failed!\n",
  3697. __func__);
  3698. /* initialize SPM before acpuclock as the latter calls into SPM
  3699. * driver to set ACPU voltages.
  3700. */
  3701. msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
  3702. /*
  3703. * Disable regulator info printing so that regulator registration
  3704. * messages do not enter the kmsg log.
  3705. */
  3706. regulator_suppress_info_printing();
  3707. /* Initialize regulators needed for clock_init. */
  3708. platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
  3709. msm_clock_init(msm_clocks_8x60, msm_num_clocks_8x60);
  3710. /* Buses need to be initialized before early-device registration
  3711. * to get the platform data for fabrics.
  3712. */
  3713. msm8x60_init_buses();
  3714. platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
  3715. msm_acpu_clock_init(&msm8x60_acpu_clock_data);
  3716. msm8x60_init_ebi2();
  3717. msm8x60_init_tlmm();
  3718. msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
  3719. msm8x60_init_uart12dm();
  3720. msm8x60_init_mmc();
  3721. msm8x60_cfg_smsc911x();
  3722. if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
  3723. platform_add_devices(msm_footswitch_devices,
  3724. msm_num_footswitch_devices);
  3725. platform_add_devices(qrdc_devices,
  3726. ARRAY_SIZE(qrdc_devices));
  3727. wifi_power(1);
  3728. #ifdef CONFIG_USB_EHCI_MSM
  3729. msm_add_host(0, &msm_usb_host_pdata);
  3730. #endif
  3731. msm_fb_add_devices();
  3732. fixup_i2c_configs();
  3733. register_i2c_devices();
  3734. msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
  3735. msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
  3736. msm_pm_data);
  3737. msm_auxpcm_init();
  3738. #ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
  3739. enable_wlan_bt();
  3740. #endif
  3741. }
  3742. static void __init msm8x60_qrdc_init(void)
  3743. {
  3744. msm8x60_init(&msm8x60_qrdc_board_data);
  3745. }
  3746. MACHINE_START(MSM8X60_QRDC, "QCT MSM8X60 QRDC")
  3747. #ifdef CONFIG_MSM_DEBUG_UART
  3748. .phys_io = MSM_DEBUG_UART_PHYS,
  3749. .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
  3750. #endif
  3751. .map_io = msm8x60_map_io,
  3752. .init_irq = msm8x60_init_irq,
  3753. .init_machine = msm8x60_qrdc_init,
  3754. .timer = &msm_timer,
  3755. MACHINE_END