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/drivers/scsi/aic7xxx/aic79xx.reg

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
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Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1. /*
  2. * Aic79xx register and scratch ram definitions.
  3. *
  4. * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
  5. * Copyright (c) 2000-2002 Adaptec Inc.
  6. * All rights reserved.
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. * 1. Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions, and the following disclaimer,
  13. * without modification.
  14. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15. * substantially similar to the "NO WARRANTY" disclaimer below
  16. * ("Disclaimer") and any redistribution must be conditioned upon
  17. * including a substantially similar Disclaimer requirement for further
  18. * binary redistribution.
  19. * 3. Neither the names of the above-listed copyright holders nor the names
  20. * of any contributors may be used to endorse or promote products derived
  21. * from this software without specific prior written permission.
  22. *
  23. * Alternatively, this software may be distributed under the terms of the
  24. * GNU General Public License ("GPL") version 2 as published by the Free
  25. * Software Foundation.
  26. *
  27. * NO WARRANTY
  28. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGES.
  39. *
  40. * $FreeBSD$
  41. */
  42. VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $"
  43. /*
  44. * This file is processed by the aic7xxx_asm utility for use in assembling
  45. * firmware for the aic79xx family of SCSI host adapters as well as to generate
  46. * a C header file for use in the kernel portion of the Aic79xx driver.
  47. */
  48. /* Register window Modes */
  49. #define M_DFF0 0
  50. #define M_DFF1 1
  51. #define M_CCHAN 2
  52. #define M_SCSI 3
  53. #define M_CFG 4
  54. #define M_DST_SHIFT 4
  55. #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
  56. #define SET_MODE(src, dst) \
  57. SET_SRC_MODE src; \
  58. SET_DST_MODE dst; \
  59. if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
  60. mvi MK_MODE(src, dst) call set_mode_work_around; \
  61. } else { \
  62. mvi MODE_PTR, MK_MODE(src, dst); \
  63. }
  64. #define RESTORE_MODE(mode) \
  65. if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
  66. mov mode call set_mode_work_around; \
  67. } else { \
  68. mov MODE_PTR, mode; \
  69. }
  70. #define SET_SEQINTCODE(code) \
  71. if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
  72. mvi code call set_seqint_work_around; \
  73. } else { \
  74. mvi SEQINTCODE, code; \
  75. }
  76. /*
  77. * Registers marked "dont_generate_debug_code" are not (yet) referenced
  78. * from the driver code, and this keyword inhibit generation
  79. * of debug code for them.
  80. *
  81. * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
  82. * is added to the register which is referenced in the driver.
  83. * Unreferenced register with no dont_generate_debug_code will result
  84. * in dead code. No warning is issued.
  85. */
  86. /*
  87. * Mode Pointer
  88. * Controls which of the 5, 512byte, address spaces should be used
  89. * as the source and destination of any register accesses in our
  90. * register window.
  91. */
  92. register MODE_PTR {
  93. address 0x000
  94. access_mode RW
  95. field DST_MODE 0x70
  96. field SRC_MODE 0x07
  97. mode_pointer
  98. dont_generate_debug_code
  99. }
  100. const SRC_MODE_SHIFT 0
  101. const DST_MODE_SHIFT 4
  102. /*
  103. * Host Interrupt Status
  104. */
  105. register INTSTAT {
  106. address 0x001
  107. access_mode RW
  108. field HWERRINT 0x80
  109. field BRKADRINT 0x40
  110. field SWTMINT 0x20
  111. field PCIINT 0x10
  112. field SCSIINT 0x08
  113. field SEQINT 0x04
  114. field CMDCMPLT 0x02
  115. field SPLTINT 0x01
  116. mask INT_PEND 0xFF
  117. }
  118. /*
  119. * Sequencer Interrupt Code
  120. */
  121. register SEQINTCODE {
  122. address 0x002
  123. access_mode RW
  124. field {
  125. NO_SEQINT, /* No seqint pending. */
  126. BAD_PHASE, /* unknown scsi bus phase */
  127. SEND_REJECT, /* sending a message reject */
  128. PROTO_VIOLATION, /* Protocol Violation */
  129. NO_MATCH, /* no cmd match for reconnect */
  130. IGN_WIDE_RES, /* Complex IGN Wide Res Msg */
  131. PDATA_REINIT, /*
  132. * Returned to data phase
  133. * that requires data
  134. * transfer pointers to be
  135. * recalculated from the
  136. * transfer residual.
  137. */
  138. HOST_MSG_LOOP, /*
  139. * The bus is ready for the
  140. * host to perform another
  141. * message transaction. This
  142. * mechanism is used for things
  143. * like sync/wide negotiation
  144. * that require a kernel based
  145. * message state engine.
  146. */
  147. BAD_STATUS, /* Bad status from target */
  148. DATA_OVERRUN, /*
  149. * Target attempted to write
  150. * beyond the bounds of its
  151. * command.
  152. */
  153. MKMSG_FAILED, /*
  154. * Target completed command
  155. * without honoring our ATN
  156. * request to issue a message.
  157. */
  158. MISSED_BUSFREE, /*
  159. * The sequencer never saw
  160. * the bus go free after
  161. * either a command complete
  162. * or disconnect message.
  163. */
  164. DUMP_CARD_STATE,
  165. ILLEGAL_PHASE,
  166. INVALID_SEQINT,
  167. CFG4ISTAT_INTR,
  168. STATUS_OVERRUN,
  169. CFG4OVERRUN,
  170. ENTERING_NONPACK,
  171. TASKMGMT_FUNC_COMPLETE, /*
  172. * Task management function
  173. * request completed with
  174. * an expected busfree.
  175. */
  176. TASKMGMT_CMD_CMPLT_OKAY, /*
  177. * A command with a non-zero
  178. * task management function
  179. * has completed via the normal
  180. * command completion method
  181. * for commands with a zero
  182. * task management function.
  183. * This happens when an attempt
  184. * to abort a command loses
  185. * the race for the command to
  186. * complete normally.
  187. */
  188. TRACEPOINT0,
  189. TRACEPOINT1,
  190. TRACEPOINT2,
  191. TRACEPOINT3,
  192. SAW_HWERR,
  193. BAD_SCB_STATUS
  194. }
  195. dont_generate_debug_code
  196. }
  197. /*
  198. * Clear Host Interrupt
  199. */
  200. register CLRINT {
  201. address 0x003
  202. access_mode WO
  203. count 19
  204. field CLRHWERRINT 0x80 /* Rev B or greater */
  205. field CLRBRKADRINT 0x40
  206. field CLRSWTMINT 0x20
  207. field CLRPCIINT 0x10
  208. field CLRSCSIINT 0x08
  209. field CLRSEQINT 0x04
  210. field CLRCMDINT 0x02
  211. field CLRSPLTINT 0x01
  212. dont_generate_debug_code
  213. }
  214. /*
  215. * Error Register
  216. */
  217. register ERROR {
  218. address 0x004
  219. access_mode RO
  220. field CIOPARERR 0x80
  221. field CIOACCESFAIL 0x40 /* Rev B or greater */
  222. field MPARERR 0x20
  223. field DPARERR 0x10
  224. field SQPARERR 0x08
  225. field ILLOPCODE 0x04
  226. field DSCTMOUT 0x02
  227. dont_generate_debug_code
  228. }
  229. /*
  230. * Clear Error
  231. */
  232. register CLRERR {
  233. address 0x004
  234. access_mode WO
  235. field CLRCIOPARERR 0x80
  236. field CLRCIOACCESFAIL 0x40 /* Rev B or greater */
  237. field CLRMPARERR 0x20
  238. field CLRDPARERR 0x10
  239. field CLRSQPARERR 0x08
  240. field CLRILLOPCODE 0x04
  241. field CLRDSCTMOUT 0x02
  242. }
  243. /*
  244. * Host Control Register
  245. * Overall host control of the device.
  246. */
  247. register HCNTRL {
  248. address 0x005
  249. access_mode RW
  250. count 12
  251. field SEQ_RESET 0x80 /* Rev B or greater */
  252. field POWRDN 0x40
  253. field SWINT 0x10
  254. field SWTIMER_START_B 0x08 /* Rev B or greater */
  255. field PAUSE 0x04
  256. field INTEN 0x02
  257. field CHIPRST 0x01
  258. field CHIPRSTACK 0x01
  259. dont_generate_debug_code
  260. }
  261. /*
  262. * Host New SCB Queue Offset
  263. */
  264. register HNSCB_QOFF {
  265. address 0x006
  266. access_mode RW
  267. size 2
  268. count 2
  269. dont_generate_debug_code
  270. }
  271. /*
  272. * Host Empty SCB Queue Offset
  273. */
  274. register HESCB_QOFF {
  275. address 0x008
  276. access_mode RW
  277. count 2
  278. dont_generate_debug_code
  279. }
  280. /*
  281. * Host Mailbox
  282. */
  283. register HS_MAILBOX {
  284. address 0x00B
  285. access_mode RW
  286. mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
  287. mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */
  288. }
  289. /*
  290. * Sequencer Interrupt Status
  291. */
  292. register SEQINTSTAT {
  293. address 0x00C
  294. count 1
  295. access_mode RO
  296. field SEQ_SWTMRTO 0x10
  297. field SEQ_SEQINT 0x08
  298. field SEQ_SCSIINT 0x04
  299. field SEQ_PCIINT 0x02
  300. field SEQ_SPLTINT 0x01
  301. }
  302. /*
  303. * Clear SEQ Interrupt
  304. */
  305. register CLRSEQINTSTAT {
  306. address 0x00C
  307. access_mode WO
  308. field CLRSEQ_SWTMRTO 0x10
  309. field CLRSEQ_SEQINT 0x08
  310. field CLRSEQ_SCSIINT 0x04
  311. field CLRSEQ_PCIINT 0x02
  312. field CLRSEQ_SPLTINT 0x01
  313. dont_generate_debug_code
  314. }
  315. /*
  316. * Software Timer
  317. */
  318. register SWTIMER {
  319. address 0x00E
  320. access_mode RW
  321. size 2
  322. dont_generate_debug_code
  323. }
  324. /*
  325. * SEQ New SCB Queue Offset
  326. */
  327. register SNSCB_QOFF {
  328. address 0x010
  329. access_mode RW
  330. size 2
  331. modes M_CCHAN
  332. dont_generate_debug_code
  333. }
  334. /*
  335. * SEQ Empty SCB Queue Offset
  336. */
  337. register SESCB_QOFF {
  338. address 0x012
  339. count 2
  340. access_mode RW
  341. modes M_CCHAN
  342. dont_generate_debug_code
  343. }
  344. /*
  345. * SEQ Done SCB Queue Offset
  346. */
  347. register SDSCB_QOFF {
  348. address 0x014
  349. access_mode RW
  350. modes M_CCHAN
  351. size 2
  352. dont_generate_debug_code
  353. }
  354. /*
  355. * Queue Offset Control & Status
  356. */
  357. register QOFF_CTLSTA {
  358. address 0x016
  359. access_mode RW
  360. modes M_CCHAN
  361. field EMPTY_SCB_AVAIL 0x80
  362. field NEW_SCB_AVAIL 0x40
  363. field SDSCB_ROLLOVR 0x20
  364. field HS_MAILBOX_ACT 0x10
  365. field SCB_QSIZE 0x0F {
  366. SCB_QSIZE_4,
  367. SCB_QSIZE_8,
  368. SCB_QSIZE_16,
  369. SCB_QSIZE_32,
  370. SCB_QSIZE_64,
  371. SCB_QSIZE_128,
  372. SCB_QSIZE_256,
  373. SCB_QSIZE_512,
  374. SCB_QSIZE_1024,
  375. SCB_QSIZE_2048,
  376. SCB_QSIZE_4096,
  377. SCB_QSIZE_8192,
  378. SCB_QSIZE_16384
  379. }
  380. dont_generate_debug_code
  381. }
  382. /*
  383. * Interrupt Control
  384. */
  385. register INTCTL {
  386. address 0x018
  387. access_mode RW
  388. field SWTMINTMASK 0x80
  389. field SWTMINTEN 0x40
  390. field SWTIMER_START 0x20
  391. field AUTOCLRCMDINT 0x10
  392. field PCIINTEN 0x08
  393. field SCSIINTEN 0x04
  394. field SEQINTEN 0x02
  395. field SPLTINTEN 0x01
  396. }
  397. /*
  398. * Data FIFO Control
  399. */
  400. register DFCNTRL {
  401. address 0x019
  402. access_mode RW
  403. modes M_DFF0, M_DFF1
  404. count 11
  405. field PRELOADEN 0x80
  406. field SCSIENWRDIS 0x40 /* Rev B only. */
  407. field SCSIEN 0x20
  408. field SCSIENACK 0x20
  409. field HDMAEN 0x08
  410. field HDMAENACK 0x08
  411. field DIRECTION 0x04
  412. field DIRECTIONACK 0x04
  413. field FIFOFLUSH 0x02
  414. field FIFOFLUSHACK 0x02
  415. field DIRECTIONEN 0x01
  416. }
  417. /*
  418. * Device Space Command 0
  419. */
  420. register DSCOMMAND0 {
  421. address 0x019
  422. count 1
  423. access_mode RW
  424. modes M_CFG
  425. field CACHETHEN 0x80 /* Cache Threshold enable */
  426. field DPARCKEN 0x40 /* Data Parity Check Enable */
  427. field MPARCKEN 0x20 /* Memory Parity Check Enable */
  428. field EXTREQLCK 0x10 /* External Request Lock */
  429. field DISABLE_TWATE 0x02 /* Rev B or greater */
  430. field CIOPARCKEN 0x01 /* Internal bus parity error enable */
  431. dont_generate_debug_code
  432. }
  433. /*
  434. * Data FIFO Status
  435. */
  436. register DFSTATUS {
  437. address 0x01A
  438. access_mode RO
  439. modes M_DFF0, M_DFF1
  440. field PRELOAD_AVAIL 0x80
  441. field PKT_PRELOAD_AVAIL 0x40
  442. field MREQPEND 0x10
  443. field HDONE 0x08
  444. field DFTHRESH 0x04
  445. field FIFOFULL 0x02
  446. field FIFOEMP 0x01
  447. }
  448. /*
  449. * S/G Cache Pointer
  450. */
  451. register SG_CACHE_PRE {
  452. address 0x01B
  453. access_mode WO
  454. modes M_DFF0, M_DFF1
  455. field SG_ADDR_MASK 0xf8
  456. field ODD_SEG 0x04
  457. field LAST_SEG 0x02
  458. dont_generate_debug_code
  459. }
  460. register SG_CACHE_SHADOW {
  461. address 0x01B
  462. access_mode RO
  463. modes M_DFF0, M_DFF1
  464. field SG_ADDR_MASK 0xf8
  465. field ODD_SEG 0x04
  466. field LAST_SEG 0x02
  467. field LAST_SEG_DONE 0x01
  468. }
  469. /*
  470. * Arbiter Control
  471. */
  472. register ARBCTL {
  473. address 0x01B
  474. access_mode RW
  475. modes M_CFG
  476. field RESET_HARB 0x80
  477. field RETRY_SWEN 0x08
  478. field USE_TIME 0x07
  479. }
  480. /*
  481. * Data Channel Host Address
  482. */
  483. register HADDR {
  484. address 0x070
  485. access_mode RW
  486. size 8
  487. modes M_DFF0, M_DFF1
  488. dont_generate_debug_code
  489. }
  490. /*
  491. * Host Overlay DMA Address
  492. */
  493. register HODMAADR {
  494. address 0x070
  495. access_mode RW
  496. size 8
  497. modes M_SCSI
  498. }
  499. /*
  500. * PCI PLL Delay.
  501. */
  502. register PLLDELAY {
  503. address 0x070
  504. access_mode RW
  505. size 1
  506. modes M_CFG
  507. field SPLIT_DROP_REQ 0x80
  508. }
  509. /*
  510. * Data Channel Host Count
  511. */
  512. register HCNT {
  513. address 0x078
  514. access_mode RW
  515. size 3
  516. modes M_DFF0, M_DFF1
  517. dont_generate_debug_code
  518. }
  519. /*
  520. * Host Overlay DMA Count
  521. */
  522. register HODMACNT {
  523. address 0x078
  524. access_mode RW
  525. size 2
  526. modes M_SCSI
  527. }
  528. /*
  529. * Host Overlay DMA Enable
  530. */
  531. register HODMAEN {
  532. address 0x07A
  533. access_mode RW
  534. modes M_SCSI
  535. }
  536. /*
  537. * Scatter/Gather Host Address
  538. */
  539. register SGHADDR {
  540. address 0x07C
  541. access_mode RW
  542. size 8
  543. modes M_DFF0, M_DFF1
  544. dont_generate_debug_code
  545. }
  546. /*
  547. * SCB Host Address
  548. */
  549. register SCBHADDR {
  550. address 0x07C
  551. access_mode RW
  552. size 8
  553. modes M_CCHAN
  554. dont_generate_debug_code
  555. }
  556. /*
  557. * Scatter/Gather Host Count
  558. */
  559. register SGHCNT {
  560. address 0x084
  561. access_mode RW
  562. modes M_DFF0, M_DFF1
  563. dont_generate_debug_code
  564. }
  565. /*
  566. * SCB Host Count
  567. */
  568. register SCBHCNT {
  569. address 0x084
  570. access_mode RW
  571. modes M_CCHAN
  572. dont_generate_debug_code
  573. }
  574. /*
  575. * Data FIFO Threshold
  576. */
  577. register DFF_THRSH {
  578. address 0x088
  579. access_mode RW
  580. modes M_CFG
  581. count 1
  582. field WR_DFTHRSH 0x70 {
  583. WR_DFTHRSH_MIN,
  584. WR_DFTHRSH_25,
  585. WR_DFTHRSH_50,
  586. WR_DFTHRSH_63,
  587. WR_DFTHRSH_75,
  588. WR_DFTHRSH_85,
  589. WR_DFTHRSH_90,
  590. WR_DFTHRSH_MAX
  591. }
  592. field RD_DFTHRSH 0x07 {
  593. RD_DFTHRSH_MIN,
  594. RD_DFTHRSH_25,
  595. RD_DFTHRSH_50,
  596. RD_DFTHRSH_63,
  597. RD_DFTHRSH_75,
  598. RD_DFTHRSH_85,
  599. RD_DFTHRSH_90,
  600. RD_DFTHRSH_MAX
  601. }
  602. dont_generate_debug_code
  603. }
  604. /*
  605. * ROM Address
  606. */
  607. register ROMADDR {
  608. address 0x08A
  609. access_mode RW
  610. size 3
  611. }
  612. /*
  613. * ROM Control
  614. */
  615. register ROMCNTRL {
  616. address 0x08D
  617. access_mode RW
  618. field ROMOP 0xE0
  619. field ROMSPD 0x18
  620. field REPEAT 0x02
  621. field RDY 0x01
  622. }
  623. /*
  624. * ROM Data
  625. */
  626. register ROMDATA {
  627. address 0x08E
  628. access_mode RW
  629. }
  630. /*
  631. * Data Channel Receive Message 0
  632. */
  633. register DCHRXMSG0 {
  634. address 0x090
  635. access_mode RO
  636. modes M_DFF0, M_DFF1
  637. field CDNUM 0xF8
  638. field CFNUM 0x07
  639. }
  640. /*
  641. * CMC Receive Message 0
  642. */
  643. register CMCRXMSG0 {
  644. address 0x090
  645. access_mode RO
  646. modes M_CCHAN
  647. field CDNUM 0xF8
  648. field CFNUM 0x07
  649. }
  650. /*
  651. * Overlay Receive Message 0
  652. */
  653. register OVLYRXMSG0 {
  654. address 0x090
  655. access_mode RO
  656. modes M_SCSI
  657. field CDNUM 0xF8
  658. field CFNUM 0x07
  659. }
  660. /*
  661. * Relaxed Order Enable
  662. */
  663. register ROENABLE {
  664. address 0x090
  665. access_mode RW
  666. modes M_CFG
  667. field MSIROEN 0x20
  668. field OVLYROEN 0x10
  669. field CMCROEN 0x08
  670. field SGROEN 0x04
  671. field DCH1ROEN 0x02
  672. field DCH0ROEN 0x01
  673. }
  674. /*
  675. * Data Channel Receive Message 1
  676. */
  677. register DCHRXMSG1 {
  678. address 0x091
  679. access_mode RO
  680. modes M_DFF0, M_DFF1
  681. field CBNUM 0xFF
  682. }
  683. /*
  684. * CMC Receive Message 1
  685. */
  686. register CMCRXMSG1 {
  687. address 0x091
  688. access_mode RO
  689. modes M_CCHAN
  690. field CBNUM 0xFF
  691. }
  692. /*
  693. * Overlay Receive Message 1
  694. */
  695. register OVLYRXMSG1 {
  696. address 0x091
  697. access_mode RO
  698. modes M_SCSI
  699. field CBNUM 0xFF
  700. }
  701. /*
  702. * No Snoop Enable
  703. */
  704. register NSENABLE {
  705. address 0x091
  706. access_mode RW
  707. modes M_CFG
  708. field MSINSEN 0x20
  709. field OVLYNSEN 0x10
  710. field CMCNSEN 0x08
  711. field SGNSEN 0x04
  712. field DCH1NSEN 0x02
  713. field DCH0NSEN 0x01
  714. }
  715. /*
  716. * Data Channel Receive Message 2
  717. */
  718. register DCHRXMSG2 {
  719. address 0x092
  720. access_mode RO
  721. modes M_DFF0, M_DFF1
  722. field MINDEX 0xFF
  723. }
  724. /*
  725. * CMC Receive Message 2
  726. */
  727. register CMCRXMSG2 {
  728. address 0x092
  729. access_mode RO
  730. modes M_CCHAN
  731. field MINDEX 0xFF
  732. }
  733. /*
  734. * Overlay Receive Message 2
  735. */
  736. register OVLYRXMSG2 {
  737. address 0x092
  738. access_mode RO
  739. modes M_SCSI
  740. field MINDEX 0xFF
  741. }
  742. /*
  743. * Outstanding Split Transactions
  744. */
  745. register OST {
  746. address 0x092
  747. access_mode RW
  748. modes M_CFG
  749. }
  750. /*
  751. * Data Channel Receive Message 3
  752. */
  753. register DCHRXMSG3 {
  754. address 0x093
  755. access_mode RO
  756. modes M_DFF0, M_DFF1
  757. field MCLASS 0x0F
  758. }
  759. /*
  760. * CMC Receive Message 3
  761. */
  762. register CMCRXMSG3 {
  763. address 0x093
  764. access_mode RO
  765. modes M_CCHAN
  766. field MCLASS 0x0F
  767. }
  768. /*
  769. * Overlay Receive Message 3
  770. */
  771. register OVLYRXMSG3 {
  772. address 0x093
  773. access_mode RO
  774. modes M_SCSI
  775. field MCLASS 0x0F
  776. }
  777. /*
  778. * PCI-X Control
  779. */
  780. register PCIXCTL {
  781. address 0x093
  782. access_mode RW
  783. modes M_CFG
  784. count 1
  785. field SERRPULSE 0x80
  786. field UNEXPSCIEN 0x20
  787. field SPLTSMADIS 0x10
  788. field SPLTSTADIS 0x08
  789. field SRSPDPEEN 0x04
  790. field TSCSERREN 0x02
  791. field CMPABCDIS 0x01
  792. dont_generate_debug_code
  793. }
  794. /*
  795. * CMC Sequencer Byte Count
  796. */
  797. register CMCSEQBCNT {
  798. address 0x094
  799. access_mode RO
  800. modes M_CCHAN
  801. }
  802. /*
  803. * Overlay Sequencer Byte Count
  804. */
  805. register OVLYSEQBCNT {
  806. address 0x094
  807. access_mode RO
  808. modes M_SCSI
  809. }
  810. /*
  811. * Data Channel Sequencer Byte Count
  812. */
  813. register DCHSEQBCNT {
  814. address 0x094
  815. access_mode RO
  816. size 2
  817. modes M_DFF0, M_DFF1
  818. }
  819. /*
  820. * Data Channel Split Status 0
  821. */
  822. register DCHSPLTSTAT0 {
  823. address 0x096
  824. access_mode RW
  825. modes M_DFF0, M_DFF1
  826. count 2
  827. field STAETERM 0x80
  828. field SCBCERR 0x40
  829. field SCADERR 0x20
  830. field SCDATBUCKET 0x10
  831. field CNTNOTCMPLT 0x08
  832. field RXOVRUN 0x04
  833. field RXSCEMSG 0x02
  834. field RXSPLTRSP 0x01
  835. dont_generate_debug_code
  836. }
  837. /*
  838. * CMC Split Status 0
  839. */
  840. register CMCSPLTSTAT0 {
  841. address 0x096
  842. access_mode RW
  843. modes M_CCHAN
  844. field STAETERM 0x80
  845. field SCBCERR 0x40
  846. field SCADERR 0x20
  847. field SCDATBUCKET 0x10
  848. field CNTNOTCMPLT 0x08
  849. field RXOVRUN 0x04
  850. field RXSCEMSG 0x02
  851. field RXSPLTRSP 0x01
  852. }
  853. /*
  854. * Overlay Split Status 0
  855. */
  856. register OVLYSPLTSTAT0 {
  857. address 0x096
  858. access_mode RW
  859. modes M_SCSI
  860. field STAETERM 0x80
  861. field SCBCERR 0x40
  862. field SCADERR 0x20
  863. field SCDATBUCKET 0x10
  864. field CNTNOTCMPLT 0x08
  865. field RXOVRUN 0x04
  866. field RXSCEMSG 0x02
  867. field RXSPLTRSP 0x01
  868. }
  869. /*
  870. * Data Channel Split Status 1
  871. */
  872. register DCHSPLTSTAT1 {
  873. address 0x097
  874. access_mode RW
  875. modes M_DFF0, M_DFF1
  876. count 2
  877. field RXDATABUCKET 0x01
  878. dont_generate_debug_code
  879. }
  880. /*
  881. * CMC Split Status 1
  882. */
  883. register CMCSPLTSTAT1 {
  884. address 0x097
  885. access_mode RW
  886. modes M_CCHAN
  887. field RXDATABUCKET 0x01
  888. }
  889. /*
  890. * Overlay Split Status 1
  891. */
  892. register OVLYSPLTSTAT1 {
  893. address 0x097
  894. access_mode RW
  895. modes M_SCSI
  896. field RXDATABUCKET 0x01
  897. }
  898. /*
  899. * S/G Receive Message 0
  900. */
  901. register SGRXMSG0 {
  902. address 0x098
  903. access_mode RO
  904. modes M_DFF0, M_DFF1
  905. field CDNUM 0xF8
  906. field CFNUM 0x07
  907. }
  908. /*
  909. * S/G Receive Message 1
  910. */
  911. register SGRXMSG1 {
  912. address 0x099
  913. access_mode RO
  914. modes M_DFF0, M_DFF1
  915. field CBNUM 0xFF
  916. }
  917. /*
  918. * S/G Receive Message 2
  919. */
  920. register SGRXMSG2 {
  921. address 0x09A
  922. access_mode RO
  923. modes M_DFF0, M_DFF1
  924. field MINDEX 0xFF
  925. }
  926. /*
  927. * S/G Receive Message 3
  928. */
  929. register SGRXMSG3 {
  930. address 0x09B
  931. access_mode RO
  932. modes M_DFF0, M_DFF1
  933. field MCLASS 0x0F
  934. }
  935. /*
  936. * Slave Split Out Address 0
  937. */
  938. register SLVSPLTOUTADR0 {
  939. address 0x098
  940. access_mode RO
  941. modes M_SCSI
  942. field LOWER_ADDR 0x7F
  943. }
  944. /*
  945. * Slave Split Out Address 1
  946. */
  947. register SLVSPLTOUTADR1 {
  948. address 0x099
  949. access_mode RO
  950. modes M_SCSI
  951. field REQ_DNUM 0xF8
  952. field REQ_FNUM 0x07
  953. }
  954. /*
  955. * Slave Split Out Address 2
  956. */
  957. register SLVSPLTOUTADR2 {
  958. address 0x09A
  959. access_mode RO
  960. modes M_SCSI
  961. field REQ_BNUM 0xFF
  962. }
  963. /*
  964. * Slave Split Out Address 3
  965. */
  966. register SLVSPLTOUTADR3 {
  967. address 0x09B
  968. access_mode RO
  969. modes M_SCSI
  970. field RLXORD 020
  971. field TAG_NUM 0x1F
  972. }
  973. /*
  974. * SG Sequencer Byte Count
  975. */
  976. register SGSEQBCNT {
  977. address 0x09C
  978. access_mode RO
  979. modes M_DFF0, M_DFF1
  980. }
  981. /*
  982. * Slave Split Out Attribute 0
  983. */
  984. register SLVSPLTOUTATTR0 {
  985. address 0x09C
  986. access_mode RO
  987. modes M_SCSI
  988. field LOWER_BCNT 0xFF
  989. }
  990. /*
  991. * Slave Split Out Attribute 1
  992. */
  993. register SLVSPLTOUTATTR1 {
  994. address 0x09D
  995. access_mode RO
  996. modes M_SCSI
  997. field CMPLT_DNUM 0xF8
  998. field CMPLT_FNUM 0x07
  999. }
  1000. /*
  1001. * Slave Split Out Attribute 2
  1002. */
  1003. register SLVSPLTOUTATTR2 {
  1004. address 0x09E
  1005. access_mode RO
  1006. size 2
  1007. modes M_SCSI
  1008. field CMPLT_BNUM 0xFF
  1009. }
  1010. /*
  1011. * S/G Split Status 0
  1012. */
  1013. register SGSPLTSTAT0 {
  1014. address 0x09E
  1015. access_mode RW
  1016. modes M_DFF0, M_DFF1
  1017. count 2
  1018. field STAETERM 0x80
  1019. field SCBCERR 0x40
  1020. field SCADERR 0x20
  1021. field SCDATBUCKET 0x10
  1022. field CNTNOTCMPLT 0x08
  1023. field RXOVRUN 0x04
  1024. field RXSCEMSG 0x02
  1025. field RXSPLTRSP 0x01
  1026. dont_generate_debug_code
  1027. }
  1028. /*
  1029. * S/G Split Status 1
  1030. */
  1031. register SGSPLTSTAT1 {
  1032. address 0x09F
  1033. access_mode RW
  1034. modes M_DFF0, M_DFF1
  1035. count 2
  1036. field RXDATABUCKET 0x01
  1037. dont_generate_debug_code
  1038. }
  1039. /*
  1040. * Special Function
  1041. */
  1042. register SFUNCT {
  1043. address 0x09f
  1044. access_mode RW
  1045. modes M_CFG
  1046. field TEST_GROUP 0xF0
  1047. field TEST_NUM 0x0F
  1048. dont_generate_debug_code
  1049. }
  1050. /*
  1051. * Data FIFO 0 PCI Status
  1052. */
  1053. register DF0PCISTAT {
  1054. address 0x0A0
  1055. access_mode RW
  1056. modes M_CFG
  1057. count 1
  1058. field DPE 0x80
  1059. field SSE 0x40
  1060. field RMA 0x20
  1061. field RTA 0x10
  1062. field SCAAPERR 0x08
  1063. field RDPERR 0x04
  1064. field TWATERR 0x02
  1065. field DPR 0x01
  1066. dont_generate_debug_code
  1067. }
  1068. /*
  1069. * Data FIFO 1 PCI Status
  1070. */
  1071. register DF1PCISTAT {
  1072. address 0x0A1
  1073. access_mode RW
  1074. modes M_CFG
  1075. field DPE 0x80
  1076. field SSE 0x40
  1077. field RMA 0x20
  1078. field RTA 0x10
  1079. field SCAAPERR 0x08
  1080. field RDPERR 0x04
  1081. field TWATERR 0x02
  1082. field DPR 0x01
  1083. }
  1084. /*
  1085. * S/G PCI Status
  1086. */
  1087. register SGPCISTAT {
  1088. address 0x0A2
  1089. access_mode RW
  1090. modes M_CFG
  1091. field DPE 0x80
  1092. field SSE 0x40
  1093. field RMA 0x20
  1094. field RTA 0x10
  1095. field SCAAPERR 0x08
  1096. field RDPERR 0x04
  1097. field DPR 0x01
  1098. }
  1099. /*
  1100. * CMC PCI Status
  1101. */
  1102. register CMCPCISTAT {
  1103. address 0x0A3
  1104. access_mode RW
  1105. modes M_CFG
  1106. field DPE 0x80
  1107. field SSE 0x40
  1108. field RMA 0x20
  1109. field RTA 0x10
  1110. field SCAAPERR 0x08
  1111. field RDPERR 0x04
  1112. field TWATERR 0x02
  1113. field DPR 0x01
  1114. }
  1115. /*
  1116. * Overlay PCI Status
  1117. */
  1118. register OVLYPCISTAT {
  1119. address 0x0A4
  1120. access_mode RW
  1121. modes M_CFG
  1122. field DPE 0x80
  1123. field SSE 0x40
  1124. field RMA 0x20
  1125. field RTA 0x10
  1126. field SCAAPERR 0x08
  1127. field RDPERR 0x04
  1128. field DPR 0x01
  1129. }
  1130. /*
  1131. * PCI Status for MSI Master DMA Transfer
  1132. */
  1133. register MSIPCISTAT {
  1134. address 0x0A6
  1135. access_mode RW
  1136. modes M_CFG
  1137. field SSE 0x40
  1138. field RMA 0x20
  1139. field RTA 0x10
  1140. field CLRPENDMSI 0x08
  1141. field TWATERR 0x02
  1142. field DPR 0x01
  1143. }
  1144. /*
  1145. * PCI Status for Target
  1146. */
  1147. register TARGPCISTAT {
  1148. address 0x0A7
  1149. access_mode RW
  1150. modes M_CFG
  1151. count 5
  1152. field DPE 0x80
  1153. field SSE 0x40
  1154. field STA 0x08
  1155. field TWATERR 0x02
  1156. dont_generate_debug_code
  1157. }
  1158. /*
  1159. * LQ Packet In
  1160. * The last LQ Packet received
  1161. */
  1162. register LQIN {
  1163. address 0x020
  1164. access_mode RW
  1165. size 20
  1166. count 2
  1167. modes M_DFF0, M_DFF1, M_SCSI
  1168. dont_generate_debug_code
  1169. }
  1170. /*
  1171. * SCB Type Pointer
  1172. * SCB offset for Target Mode SCB type information
  1173. */
  1174. register TYPEPTR {
  1175. address 0x020
  1176. access_mode RW
  1177. modes M_CFG
  1178. }
  1179. /*
  1180. * Queue Tag Pointer
  1181. * SCB offset to the Two Byte tag identifier used for target mode.
  1182. */
  1183. register TAGPTR {
  1184. address 0x021
  1185. access_mode RW
  1186. modes M_CFG
  1187. }
  1188. /*
  1189. * Logical Unit Number Pointer
  1190. * SCB offset to the LSB (little endian) of the lun field.
  1191. */
  1192. register LUNPTR {
  1193. address 0x022
  1194. access_mode RW
  1195. modes M_CFG
  1196. count 2
  1197. dont_generate_debug_code
  1198. }
  1199. /*
  1200. * Data Length Pointer
  1201. * SCB offset for the 4 byte data length field in target mode.
  1202. */
  1203. register DATALENPTR {
  1204. address 0x023
  1205. access_mode RW
  1206. modes M_CFG
  1207. }
  1208. /*
  1209. * Status Length Pointer
  1210. * SCB offset to the two byte status field in target SCBs.
  1211. */
  1212. register STATLENPTR {
  1213. address 0x024
  1214. access_mode RW
  1215. modes M_CFG
  1216. }
  1217. /*
  1218. * Command Length Pointer
  1219. * Scb offset for the CDB length field in initiator SCBs.
  1220. */
  1221. register CMDLENPTR {
  1222. address 0x025
  1223. access_mode RW
  1224. modes M_CFG
  1225. count 1
  1226. dont_generate_debug_code
  1227. }
  1228. /*
  1229. * Task Attribute Pointer
  1230. * Scb offset for the byte field specifying the attribute byte
  1231. * to be used in command packets.
  1232. */
  1233. register ATTRPTR {
  1234. address 0x026
  1235. access_mode RW
  1236. modes M_CFG
  1237. count 1
  1238. dont_generate_debug_code
  1239. }
  1240. /*
  1241. * Task Management Flags Pointer
  1242. * Scb offset for the byte field specifying the attribute flags
  1243. * byte to be used in command packets.
  1244. */
  1245. register FLAGPTR {
  1246. address 0x027
  1247. access_mode RW
  1248. modes M_CFG
  1249. count 1
  1250. dont_generate_debug_code
  1251. }
  1252. /*
  1253. * Command Pointer
  1254. * Scb offset for the first byte in the CDB for initiator SCBs.
  1255. */
  1256. register CMDPTR {
  1257. address 0x028
  1258. access_mode RW
  1259. modes M_CFG
  1260. count 1
  1261. dont_generate_debug_code
  1262. }
  1263. /*
  1264. * Queue Next Pointer
  1265. * Scb offset for the 2 byte "next scb link".
  1266. */
  1267. register QNEXTPTR {
  1268. address 0x029
  1269. access_mode RW
  1270. modes M_CFG
  1271. count 1
  1272. dont_generate_debug_code
  1273. }
  1274. /*
  1275. * SCSI ID Pointer
  1276. * Scb offset to the value to place in the SCSIID register
  1277. * during target mode connections.
  1278. */
  1279. register IDPTR {
  1280. address 0x02A
  1281. access_mode RW
  1282. modes M_CFG
  1283. }
  1284. /*
  1285. * Command Aborted Byte Pointer
  1286. * Offset to the SCB flags field that includes the
  1287. * "SCB aborted" status bit.
  1288. */
  1289. register ABRTBYTEPTR {
  1290. address 0x02B
  1291. access_mode RW
  1292. modes M_CFG
  1293. count 1
  1294. dont_generate_debug_code
  1295. }
  1296. /*
  1297. * Command Aborted Bit Pointer
  1298. * Bit offset in the SCB flags field for "SCB aborted" status.
  1299. */
  1300. register ABRTBITPTR {
  1301. address 0x02C
  1302. access_mode RW
  1303. modes M_CFG
  1304. count 1
  1305. dont_generate_debug_code
  1306. }
  1307. /*
  1308. * Rev B or greater.
  1309. */
  1310. register MAXCMDBYTES {
  1311. address 0x02D
  1312. access_mode RW
  1313. modes M_CFG
  1314. }
  1315. /*
  1316. * Rev B or greater.
  1317. */
  1318. register MAXCMD2RCV {
  1319. address 0x02E
  1320. access_mode RW
  1321. modes M_CFG
  1322. }
  1323. /*
  1324. * Rev B or greater.
  1325. */
  1326. register SHORTTHRESH {
  1327. address 0x02F
  1328. access_mode RW
  1329. modes M_CFG
  1330. }
  1331. /*
  1332. * Logical Unit Number Length
  1333. * The length, in bytes, of the SCB lun field.
  1334. */
  1335. register LUNLEN {
  1336. address 0x030
  1337. access_mode RW
  1338. modes M_CFG
  1339. count 2
  1340. mask ILUNLEN 0x0F
  1341. mask TLUNLEN 0xF0
  1342. dont_generate_debug_code
  1343. }
  1344. const LUNLEN_SINGLE_LEVEL_LUN 0xF
  1345. /*
  1346. * CDB Limit
  1347. * The size, in bytes, of the embedded CDB field in initator SCBs.
  1348. */
  1349. register CDBLIMIT {
  1350. address 0x031
  1351. access_mode RW
  1352. modes M_CFG
  1353. count 1
  1354. dont_generate_debug_code
  1355. }
  1356. /*
  1357. * Maximum Commands
  1358. * The maximum number of commands to issue during a
  1359. * single packetized connection.
  1360. */
  1361. register MAXCMD {
  1362. address 0x032
  1363. access_mode RW
  1364. modes M_CFG
  1365. count 9
  1366. dont_generate_debug_code
  1367. }
  1368. /*
  1369. * Maximum Command Counter
  1370. * The number of commands already sent during this connection
  1371. */
  1372. register MAXCMDCNT {
  1373. address 0x033
  1374. access_mode RW
  1375. modes M_CFG
  1376. dont_generate_debug_code
  1377. }
  1378. /*
  1379. * LQ Packet Reserved Bytes
  1380. * The bytes to be sent in the currently reserved fileds
  1381. * of all LQ packets.
  1382. */
  1383. register LQRSVD01 {
  1384. address 0x034
  1385. access_mode RW
  1386. modes M_SCSI
  1387. }
  1388. register LQRSVD16 {
  1389. address 0x035
  1390. access_mode RW
  1391. modes M_SCSI
  1392. }
  1393. register LQRSVD17 {
  1394. address 0x036
  1395. access_mode RW
  1396. modes M_SCSI
  1397. }
  1398. /*
  1399. * Command Reserved 0
  1400. * The byte to be sent for the reserved byte 0 of
  1401. * outgoing command packets.
  1402. */
  1403. register CMDRSVD0 {
  1404. address 0x037
  1405. access_mode RW
  1406. modes M_CFG
  1407. }
  1408. /*
  1409. * LQ Manager Control 0
  1410. */
  1411. register LQCTL0 {
  1412. address 0x038
  1413. access_mode RW
  1414. modes M_CFG
  1415. field LQITARGCLT 0xC0
  1416. field LQIINITGCLT 0x30
  1417. field LQ0TARGCLT 0x0C
  1418. field LQ0INITGCLT 0x03
  1419. }
  1420. /*
  1421. * LQ Manager Control 1
  1422. */
  1423. register LQCTL1 {
  1424. address 0x038
  1425. access_mode RW
  1426. modes M_DFF0, M_DFF1, M_SCSI
  1427. count 2
  1428. field PCI2PCI 0x04
  1429. field SINGLECMD 0x02
  1430. field ABORTPENDING 0x01
  1431. dont_generate_debug_code
  1432. }
  1433. /*
  1434. * LQ Manager Control 2
  1435. */
  1436. register LQCTL2 {
  1437. address 0x039
  1438. access_mode RW
  1439. modes M_DFF0, M_DFF1, M_SCSI
  1440. count 5
  1441. field LQIRETRY 0x80
  1442. field LQICONTINUE 0x40
  1443. field LQITOIDLE 0x20
  1444. field LQIPAUSE 0x10
  1445. field LQORETRY 0x08
  1446. field LQOCONTINUE 0x04
  1447. field LQOTOIDLE 0x02
  1448. field LQOPAUSE 0x01
  1449. dont_generate_debug_code
  1450. }
  1451. /*
  1452. * SCSI RAM BIST0
  1453. */
  1454. register SCSBIST0 {
  1455. address 0x039
  1456. access_mode RW
  1457. modes M_CFG
  1458. field GSBISTERR 0x40
  1459. field GSBISTDONE 0x20
  1460. field GSBISTRUN 0x10
  1461. field OSBISTERR 0x04
  1462. field OSBISTDONE 0x02
  1463. field OSBISTRUN 0x01
  1464. }
  1465. /*
  1466. * SCSI Sequence Control0
  1467. */
  1468. register SCSISEQ0 {
  1469. address 0x03A
  1470. access_mode RW
  1471. modes M_DFF0, M_DFF1, M_SCSI
  1472. field TEMODEO 0x80
  1473. field ENSELO 0x40
  1474. field ENARBO 0x20
  1475. field FORCEBUSFREE 0x10
  1476. field SCSIRSTO 0x01
  1477. }
  1478. /*
  1479. * SCSI RAM BIST 1
  1480. */
  1481. register SCSBIST1 {
  1482. address 0x03A
  1483. access_mode RW
  1484. modes M_CFG
  1485. field NTBISTERR 0x04
  1486. field NTBISTDONE 0x02
  1487. field NTBISTRUN 0x01
  1488. }
  1489. /*
  1490. * SCSI Sequence Control 1
  1491. */
  1492. register SCSISEQ1 {
  1493. address 0x03B
  1494. access_mode RW
  1495. modes M_DFF0, M_DFF1, M_SCSI
  1496. count 8
  1497. field MANUALCTL 0x40
  1498. field ENSELI 0x20
  1499. field ENRSELI 0x10
  1500. field MANUALP 0x0C
  1501. field ENAUTOATNP 0x02
  1502. field ALTSTIM 0x01
  1503. }
  1504. /*
  1505. * SCSI Transfer Control 0
  1506. */
  1507. register SXFRCTL0 {
  1508. address 0x03C
  1509. access_mode RW
  1510. modes M_SCSI
  1511. field DFON 0x80
  1512. field DFPEXP 0x40
  1513. field BIOSCANCELEN 0x10
  1514. field SPIOEN 0x08
  1515. dont_generate_debug_code
  1516. }
  1517. /*
  1518. * SCSI Transfer Control 1
  1519. */
  1520. register SXFRCTL1 {
  1521. address 0x03D
  1522. access_mode RW
  1523. modes M_SCSI
  1524. field BITBUCKET 0x80
  1525. field ENSACHK 0x40
  1526. field ENSPCHK 0x20
  1527. field STIMESEL 0x18
  1528. field ENSTIMER 0x04
  1529. field ACTNEGEN 0x02
  1530. field STPWEN 0x01
  1531. dont_generate_debug_code
  1532. }
  1533. /*
  1534. * SCSI Transfer Control 2
  1535. */
  1536. register SXFRCTL2 {
  1537. address 0x03E
  1538. access_mode RW
  1539. modes M_SCSI
  1540. field AUTORSTDIS 0x10
  1541. field CMDDMAEN 0x08
  1542. field ASU 0x07
  1543. }
  1544. /*
  1545. * SCSI Bus Initiator IDs
  1546. * Bitmask of observed initiators on the bus.
  1547. */
  1548. register BUSINITID {
  1549. address 0x03C
  1550. access_mode RW
  1551. modes M_CFG
  1552. size 2
  1553. }
  1554. /*
  1555. * Data Length Counters
  1556. * Packet byte counter.
  1557. */
  1558. register DLCOUNT {
  1559. address 0x03C
  1560. access_mode RW
  1561. modes M_DFF0, M_DFF1
  1562. size 3
  1563. }
  1564. /*
  1565. * Data FIFO Status
  1566. */
  1567. register DFFSTAT {
  1568. address 0x03F
  1569. access_mode RW
  1570. modes M_SCSI
  1571. field FIFO1FREE 0x20
  1572. field FIFO0FREE 0x10
  1573. /*
  1574. * On the B, this enum only works
  1575. * in the read direction. For writes,
  1576. * you must use the B version of the
  1577. * CURRFIFO_0 definition which is defined
  1578. * as a constant outside of this register
  1579. * definition to avoid confusing the
  1580. * register pretty printing code.
  1581. */
  1582. enum CURRFIFO 0x03 {
  1583. CURRFIFO_0,
  1584. CURRFIFO_1,
  1585. CURRFIFO_NONE 0x3
  1586. }
  1587. }
  1588. const B_CURRFIFO_0 0x2
  1589. /*
  1590. * SCSI Bus Target IDs
  1591. * Bitmask of observed targets on the bus.
  1592. */
  1593. register BUSTARGID {
  1594. address 0x03E
  1595. access_mode RW
  1596. modes M_CFG
  1597. size 2
  1598. }
  1599. /*
  1600. * SCSI Control Signal Out
  1601. */
  1602. register SCSISIGO {
  1603. address 0x040
  1604. access_mode RW
  1605. modes M_DFF0, M_DFF1, M_SCSI
  1606. field CDO 0x80
  1607. field IOO 0x40
  1608. field MSGO 0x20
  1609. field ATNO 0x10
  1610. field SELO 0x08
  1611. field BSYO 0x04
  1612. field REQO 0x02
  1613. field ACKO 0x01
  1614. /*
  1615. * Possible phases to write into SCSISIG0
  1616. */
  1617. enum PHASE_MASK CDO|IOO|MSGO {
  1618. P_DATAOUT 0x0,
  1619. P_DATAIN IOO,
  1620. P_DATAOUT_DT P_DATAOUT|MSGO,
  1621. P_DATAIN_DT P_DATAIN|MSGO,
  1622. P_COMMAND CDO,
  1623. P_MESGOUT CDO|MSGO,
  1624. P_STATUS CDO|IOO,
  1625. P_MESGIN CDO|IOO|MSGO
  1626. }
  1627. dont_generate_debug_code
  1628. }
  1629. /*
  1630. * SCSI Control Signal In
  1631. */
  1632. register SCSISIGI {
  1633. address 0x041
  1634. access_mode RO
  1635. modes M_DFF0, M_DFF1, M_SCSI
  1636. field CDI 0x80
  1637. field IOI 0x40
  1638. field MSGI 0x20
  1639. field ATNI 0x10
  1640. field SELI 0x08
  1641. field BSYI 0x04
  1642. field REQI 0x02
  1643. field ACKI 0x01
  1644. /*
  1645. * Possible phases in SCSISIGI
  1646. */
  1647. enum PHASE_MASK CDO|IOO|MSGO {
  1648. P_DATAOUT 0x0,
  1649. P_DATAIN IOO,
  1650. P_DATAOUT_DT P_DATAOUT|MSGO,
  1651. P_DATAIN_DT P_DATAIN|MSGO,
  1652. P_COMMAND CDO,
  1653. P_MESGOUT CDO|MSGO,
  1654. P_STATUS CDO|IOO,
  1655. P_MESGIN CDO|IOO|MSGO
  1656. }
  1657. }
  1658. /*
  1659. * Multiple Target IDs
  1660. * Bitmask of ids to respond as a target.
  1661. */
  1662. register MULTARGID {
  1663. address 0x040
  1664. access_mode RW
  1665. modes M_CFG
  1666. size 2
  1667. count 2
  1668. dont_generate_debug_code
  1669. }
  1670. /*
  1671. * SCSI Phase
  1672. */
  1673. register SCSIPHASE {
  1674. address 0x042
  1675. access_mode RO
  1676. modes M_DFF0, M_DFF1, M_SCSI
  1677. field STATUS_PHASE 0x20
  1678. field COMMAND_PHASE 0x10
  1679. field MSG_IN_PHASE 0x08
  1680. field MSG_OUT_PHASE 0x04
  1681. field DATA_PHASE_MASK 0x03 {
  1682. DATA_OUT_PHASE 0x01,
  1683. DATA_IN_PHASE 0x02
  1684. }
  1685. }
  1686. /*
  1687. * SCSI Data 0 Image
  1688. */
  1689. register SCSIDAT0_IMG {
  1690. address 0x043
  1691. access_mode RW
  1692. modes M_DFF0, M_DFF1, M_SCSI
  1693. }
  1694. /*
  1695. * SCSI Latched Data
  1696. */
  1697. register SCSIDAT {
  1698. address 0x044
  1699. access_mode RW
  1700. modes M_DFF0, M_DFF1, M_SCSI
  1701. size 2
  1702. dont_generate_debug_code
  1703. }
  1704. /*
  1705. * SCSI Data Bus
  1706. */
  1707. register SCSIBUS {
  1708. address 0x046
  1709. access_mode RW
  1710. modes M_DFF0, M_DFF1, M_SCSI
  1711. size 2
  1712. }
  1713. /*
  1714. * Target ID In
  1715. */
  1716. register TARGIDIN {
  1717. address 0x048
  1718. access_mode RO
  1719. modes M_DFF0, M_DFF1, M_SCSI
  1720. count 2
  1721. field CLKOUT 0x80
  1722. field TARGID 0x0F
  1723. dont_generate_debug_code
  1724. }
  1725. /*
  1726. * Selection/Reselection ID
  1727. * Upper four bits are the device id. The ONEBIT is set when the re/selecting
  1728. * device did not set its own ID.
  1729. */
  1730. register SELID {
  1731. address 0x049
  1732. access_mode RW
  1733. modes M_DFF0, M_DFF1, M_SCSI
  1734. field SELID_MASK 0xf0
  1735. field ONEBIT 0x08
  1736. }
  1737. /*
  1738. * SCSI Block Control
  1739. * Controls Bus type and channel selection. SELWIDE allows for the
  1740. * coexistence of 8bit and 16bit devices on a wide bus.
  1741. */
  1742. register SBLKCTL {
  1743. address 0x04A
  1744. access_mode RW
  1745. modes M_DFF0, M_DFF1, M_SCSI
  1746. field DIAGLEDEN 0x80
  1747. field DIAGLEDON 0x40
  1748. field ENAB40 0x08 /* LVD transceiver active */
  1749. field ENAB20 0x04 /* SE/HVD transceiver active */
  1750. field SELWIDE 0x02
  1751. dont_generate_debug_code
  1752. }
  1753. /*
  1754. * Option Mode
  1755. */
  1756. register OPTIONMODE {
  1757. address 0x04A
  1758. access_mode RW
  1759. modes M_CFG
  1760. count 4
  1761. field BIOSCANCTL 0x80
  1762. field AUTOACKEN 0x40
  1763. field BIASCANCTL 0x20
  1764. field BUSFREEREV 0x10
  1765. field ENDGFORMCHK 0x04
  1766. field AUTO_MSGOUT_DE 0x02
  1767. mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
  1768. dont_generate_debug_code
  1769. }
  1770. /*
  1771. * SCSI Status 0
  1772. */
  1773. register SSTAT0 {
  1774. address 0x04B
  1775. access_mode RO
  1776. modes M_DFF0, M_DFF1, M_SCSI
  1777. field TARGET 0x80 /* Board acting as target */
  1778. field SELDO 0x40 /* Selection Done */
  1779. field SELDI 0x20 /* Board has been selected */
  1780. field SELINGO 0x10 /* Selection In Progress */
  1781. field IOERR 0x08 /* LVD Tranceiver mode changed */
  1782. field OVERRUN 0x04 /* SCSI Offset overrun detected */
  1783. field SPIORDY 0x02 /* SCSI PIO Ready */
  1784. field ARBDO 0x01 /* Arbitration Done Out */
  1785. }
  1786. /*
  1787. * Clear SCSI Interrupt 0
  1788. * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
  1789. */
  1790. register CLRSINT0 {
  1791. address 0x04B
  1792. access_mode WO
  1793. modes M_DFF0, M_DFF1, M_SCSI
  1794. field CLRSELDO 0x40
  1795. field CLRSELDI 0x20
  1796. field CLRSELINGO 0x10
  1797. field CLRIOERR 0x08
  1798. field CLROVERRUN 0x04
  1799. field CLRSPIORDY 0x02
  1800. field CLRARBDO 0x01
  1801. dont_generate_debug_code
  1802. }
  1803. /*
  1804. * SCSI Interrupt Mode 0
  1805. * Setting any bit will enable the corresponding function
  1806. * in SIMODE0 to interrupt via the IRQ pin.
  1807. */
  1808. register SIMODE0 {
  1809. address 0x04B
  1810. access_mode RW
  1811. modes M_CFG
  1812. count 8
  1813. field ENSELDO 0x40
  1814. field ENSELDI 0x20
  1815. field ENSELINGO 0x10
  1816. field ENIOERR 0x08
  1817. field ENOVERRUN 0x04
  1818. field ENSPIORDY 0x02
  1819. field ENARBDO 0x01
  1820. }
  1821. /*
  1822. * SCSI Status 1
  1823. */
  1824. register SSTAT1 {
  1825. address 0x04C
  1826. access_mode RO
  1827. modes M_DFF0, M_DFF1, M_SCSI
  1828. field SELTO 0x80
  1829. field ATNTARG 0x40
  1830. field SCSIRSTI 0x20
  1831. field PHASEMIS 0x10
  1832. field BUSFREE 0x08
  1833. field SCSIPERR 0x04
  1834. field STRB2FAST 0x02
  1835. field REQINIT 0x01
  1836. }
  1837. /*
  1838. * Clear SCSI Interrupt 1
  1839. * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
  1840. */
  1841. register CLRSINT1 {
  1842. address 0x04C
  1843. access_mode WO
  1844. modes M_DFF0, M_DFF1, M_SCSI
  1845. field CLRSELTIMEO 0x80
  1846. field CLRATNO 0x40
  1847. field CLRSCSIRSTI 0x20
  1848. field CLRBUSFREE 0x08
  1849. field CLRSCSIPERR 0x04
  1850. field CLRSTRB2FAST 0x02
  1851. field CLRREQINIT 0x01
  1852. dont_generate_debug_code
  1853. }
  1854. /*
  1855. * SCSI Status 2
  1856. */
  1857. register SSTAT2 {
  1858. address 0x04d
  1859. access_mode RO
  1860. modes M_DFF0, M_DFF1, M_SCSI
  1861. field BUSFREETIME 0xc0 {
  1862. BUSFREE_LQO 0x40,
  1863. BUSFREE_DFF0 0x80,
  1864. BUSFREE_DFF1 0xC0
  1865. }
  1866. field NONPACKREQ 0x20
  1867. field EXP_ACTIVE 0x10 /* SCSI Expander Active */
  1868. field BSYX 0x08 /* Busy Expander */
  1869. field WIDE_RES 0x04 /* Modes 0 and 1 only */
  1870. field SDONE 0x02 /* Modes 0 and 1 only */
  1871. field DMADONE 0x01 /* Modes 0 and 1 only */
  1872. }
  1873. /*
  1874. * Clear SCSI Interrupt 2
  1875. */
  1876. register CLRSINT2 {
  1877. address 0x04D
  1878. access_mode WO
  1879. modes M_DFF0, M_DFF1, M_SCSI
  1880. field CLRNONPACKREQ 0x20
  1881. field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
  1882. field CLRSDONE 0x02 /* Modes 0 and 1 only */
  1883. field CLRDMADONE 0x01 /* Modes 0 and 1 only */
  1884. dont_generate_debug_code
  1885. }
  1886. /*
  1887. * SCSI Interrupt Mode 2
  1888. */
  1889. register SIMODE2 {
  1890. address 0x04D
  1891. access_mode RW
  1892. modes M_CFG
  1893. field ENWIDE_RES 0x04
  1894. field ENSDONE 0x02
  1895. field ENDMADONE 0x01
  1896. }
  1897. /*
  1898. * Physical Error Diagnosis
  1899. */
  1900. register PERRDIAG {
  1901. address 0x04E
  1902. access_mode RO
  1903. modes M_DFF0, M_DFF1, M_SCSI
  1904. count 3
  1905. field HIZERO 0x80
  1906. field HIPERR 0x40
  1907. field PREVPHASE 0x20
  1908. field PARITYERR 0x10
  1909. field AIPERR 0x08
  1910. field CRCERR 0x04
  1911. field DGFORMERR 0x02
  1912. field DTERR 0x01
  1913. }
  1914. /*
  1915. * LQI Manager Current State
  1916. */
  1917. register LQISTATE {
  1918. address 0x04E
  1919. access_mode RO
  1920. modes M_CFG
  1921. count 6
  1922. dont_generate_debug_code
  1923. }
  1924. /*
  1925. * SCSI Offset Count
  1926. */
  1927. register SOFFCNT {
  1928. address 0x04F
  1929. access_mode RO
  1930. modes M_DFF0, M_DFF1, M_SCSI
  1931. count 1
  1932. }
  1933. /*
  1934. * LQO Manager Current State
  1935. */
  1936. register LQOSTATE {
  1937. address 0x04F
  1938. access_mode RO
  1939. modes M_CFG
  1940. count 2
  1941. dont_generate_debug_code
  1942. }
  1943. /*
  1944. * LQI Manager Status
  1945. */
  1946. register LQISTAT0 {
  1947. address 0x050
  1948. access_mode RO
  1949. modes M_DFF0, M_DFF1, M_SCSI
  1950. count 2
  1951. field LQIATNQAS 0x20
  1952. field LQICRCT1 0x10
  1953. field LQICRCT2 0x08
  1954. field LQIBADLQT 0x04
  1955. field LQIATNLQ 0x02
  1956. field LQIATNCMD 0x01
  1957. }
  1958. /*
  1959. * Clear LQI Interrupts 0
  1960. */
  1961. register CLRLQIINT0 {
  1962. address 0x050
  1963. access_mode WO
  1964. modes M_DFF0, M_DFF1, M_SCSI
  1965. count 1
  1966. field CLRLQIATNQAS 0x20
  1967. field CLRLQICRCT1 0x10
  1968. field CLRLQICRCT2 0x08
  1969. field CLRLQIBADLQT 0x04
  1970. field CLRLQIATNLQ 0x02
  1971. field CLRLQIATNCMD 0x01
  1972. dont_generate_debug_code
  1973. }
  1974. /*
  1975. * LQI Manager Interrupt Mode 0
  1976. */
  1977. register LQIMODE0 {
  1978. address 0x050
  1979. access_mode RW
  1980. modes M_CFG
  1981. count 3
  1982. field ENLQIATNQASK 0x20
  1983. field ENLQICRCT1 0x10
  1984. field ENLQICRCT2 0x08
  1985. field ENLQIBADLQT 0x04
  1986. field ENLQIATNLQ 0x02
  1987. field ENLQIATNCMD 0x01
  1988. dont_generate_debug_code
  1989. }
  1990. /*
  1991. * LQI Manager Status 1
  1992. */
  1993. register LQISTAT1 {
  1994. address 0x051
  1995. access_mode RO
  1996. modes M_DFF0, M_DFF1, M_SCSI
  1997. count 3
  1998. field LQIPHASE_LQ 0x80
  1999. field LQIPHASE_NLQ 0x40
  2000. field LQIABORT 0x20
  2001. field LQICRCI_LQ 0x10
  2002. field LQICRCI_NLQ 0x08
  2003. field LQIBADLQI 0x04
  2004. field LQIOVERI_LQ 0x02
  2005. field LQIOVERI_NLQ 0x01
  2006. }
  2007. /*
  2008. * Clear LQI Manager Interrupts1
  2009. */
  2010. register CLRLQIINT1 {
  2011. address 0x051
  2012. access_mode WO
  2013. modes M_DFF0, M_DFF1, M_SCSI
  2014. count 4
  2015. field CLRLQIPHASE_LQ 0x80
  2016. field CLRLQIPHASE_NLQ 0x40
  2017. field CLRLIQABORT 0x20
  2018. field CLRLQICRCI_LQ 0x10
  2019. field CLRLQICRCI_NLQ 0x08
  2020. field CLRLQIBADLQI 0x04
  2021. field CLRLQIOVERI_LQ 0x02
  2022. field CLRLQIOVERI_NLQ 0x01
  2023. dont_generate_debug_code
  2024. }
  2025. /*
  2026. * LQI Manager Interrupt Mode 1
  2027. */
  2028. register LQIMODE1 {
  2029. address 0x051
  2030. access_mode RW
  2031. modes M_CFG
  2032. count 4
  2033. field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
  2034. field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
  2035. field ENLIQABORT 0x20
  2036. field ENLQICRCI_LQ 0x10 /* LQICRCI1 */
  2037. field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */
  2038. field ENLQIBADLQI 0x04
  2039. field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */
  2040. field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */
  2041. dont_generate_debug_code
  2042. }
  2043. /*
  2044. * LQI Manager Status 2
  2045. */
  2046. register LQISTAT2 {
  2047. address 0x052
  2048. access_mode RO
  2049. modes M_DFF0, M_DFF1, M_SCSI
  2050. field PACKETIZED 0x80
  2051. field LQIPHASE_OUTPKT 0x40
  2052. field LQIWORKONLQ 0x20
  2053. field LQIWAITFIFO 0x10
  2054. field LQISTOPPKT 0x08
  2055. field LQISTOPLQ 0x04
  2056. field LQISTOPCMD 0x02
  2057. field LQIGSAVAIL 0x01
  2058. }
  2059. /*
  2060. * SCSI Status 3
  2061. */
  2062. register SSTAT3 {
  2063. address 0x053
  2064. access_mode RO
  2065. modes M_DFF0, M_DFF1, M_SCSI
  2066. count 3
  2067. field NTRAMPERR 0x02
  2068. field OSRAMPERR 0x01
  2069. }
  2070. /*
  2071. * Clear SCSI Status 3
  2072. */
  2073. register CLRSINT3 {
  2074. address 0x053
  2075. access_mode WO
  2076. modes M_DFF0, M_DFF1, M_SCSI
  2077. count 3
  2078. field CLRNTRAMPERR 0x02
  2079. field CLROSRAMPERR 0x01
  2080. dont_generate_debug_code
  2081. }
  2082. /*
  2083. * SCSI Interrupt Mode 3
  2084. */
  2085. register SIMODE3 {
  2086. address 0x053
  2087. access_mode RW
  2088. modes M_CFG
  2089. count 4
  2090. field ENNTRAMPERR 0x02
  2091. field ENOSRAMPERR 0x01
  2092. dont_generate_debug_code
  2093. }
  2094. /*
  2095. * LQO Manager Status 0
  2096. */
  2097. register LQOSTAT0 {
  2098. address 0x054
  2099. access_mode RO
  2100. modes M_DFF0, M_DFF1, M_SCSI
  2101. count 2
  2102. field LQOTARGSCBPERR 0x10
  2103. field LQOSTOPT2 0x08
  2104. field LQOATNLQ 0x04
  2105. field LQOATNPKT 0x02
  2106. field LQOTCRC 0x01
  2107. }
  2108. /*
  2109. * Clear LQO Manager interrupt 0
  2110. */
  2111. register CLRLQOINT0 {
  2112. address 0x054
  2113. access_mode WO
  2114. modes M_DFF0, M_DFF1, M_SCSI
  2115. count 3
  2116. field CLRLQOTARGSCBPERR 0x10
  2117. field CLRLQOSTOPT2 0x08
  2118. field CLRLQOATNLQ 0x04
  2119. field CLRLQOATNPKT 0x02
  2120. field CLRLQOTCRC 0x01
  2121. dont_generate_debug_code
  2122. }
  2123. /*
  2124. * LQO Manager Interrupt Mode 0
  2125. */
  2126. register LQOMODE0 {
  2127. address 0x054
  2128. access_mode RW
  2129. modes M_CFG
  2130. count 4
  2131. field ENLQOTARGSCBPERR 0x10
  2132. field ENLQOSTOPT2 0x08
  2133. field ENLQOATNLQ 0x04
  2134. field ENLQOATNPKT 0x02
  2135. field ENLQOTCRC 0x01
  2136. dont_generate_debug_code
  2137. }
  2138. /*
  2139. * LQO Manager Status 1
  2140. */
  2141. register LQOSTAT1 {
  2142. address 0x055
  2143. access_mode RO
  2144. modes M_DFF0, M_DFF1, M_SCSI
  2145. field LQOINITSCBPERR 0x10
  2146. field LQOSTOPI2 0x08
  2147. field LQOBADQAS 0x04
  2148. field LQOBUSFREE 0x02
  2149. field LQOPHACHGINPKT 0x01
  2150. }
  2151. /*
  2152. * Clear LOQ Interrupt 1
  2153. */
  2154. register CLRLQOINT1 {
  2155. address 0x055
  2156. access_mode WO
  2157. modes M_DFF0, M_DFF1, M_SCSI
  2158. count 7
  2159. field CLRLQOINITSCBPERR 0x10
  2160. field CLRLQOSTOPI2 0x08
  2161. field CLRLQOBADQAS 0x04
  2162. field CLRLQOBUSFREE 0x02
  2163. field CLRLQOPHACHGINPKT 0x01
  2164. dont_generate_debug_code
  2165. }
  2166. /*
  2167. * LQO Manager Interrupt Mode 1
  2168. */
  2169. register LQOMODE1 {
  2170. address 0x055
  2171. access_mode RW
  2172. modes M_CFG
  2173. count 4
  2174. field ENLQOINITSCBPERR 0x10
  2175. field ENLQOSTOPI2 0x08
  2176. field ENLQOBADQAS 0x04
  2177. field ENLQOBUSFREE 0x02
  2178. field ENLQOPHACHGINPKT 0x01
  2179. dont_generate_debug_code
  2180. }
  2181. /*
  2182. * LQO Manager Status 2
  2183. */
  2184. register LQOSTAT2 {
  2185. address 0x056
  2186. access_mode RO
  2187. modes M_DFF0, M_DFF1, M_SCSI
  2188. field LQOPKT 0xE0
  2189. field LQOWAITFIFO 0x10
  2190. field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
  2191. field LQOSTOP0 0x01 /* Stopped after sending all packets */
  2192. }
  2193. /*
  2194. * Output Synchronizer Space Count
  2195. */
  2196. register OS_SPACE_CNT {
  2197. address 0x056
  2198. access_mode RO
  2199. modes M_CFG
  2200. count 2
  2201. dont_generate_debug_code
  2202. }
  2203. /*
  2204. * SCSI Interrupt Mode 1
  2205. * Setting any bit will enable the corresponding function
  2206. * in SIMODE1 to interrupt via the IRQ pin.
  2207. */
  2208. register SIMODE1 {
  2209. address 0x057
  2210. access_mode RW
  2211. modes M_DFF0, M_DFF1, M_SCSI
  2212. field ENSELTIMO 0x80
  2213. field ENATNTARG 0x40
  2214. field ENSCSIRST 0x20
  2215. field ENPHASEMIS 0x10
  2216. field ENBUSFREE 0x08
  2217. field ENSCSIPERR 0x04
  2218. field ENSTRB2FAST 0x02
  2219. field ENREQINIT 0x01
  2220. }
  2221. /*
  2222. * Good Status FIFO
  2223. */
  2224. register GSFIFO {
  2225. address 0x058
  2226. access_mode RO
  2227. size 2
  2228. modes M_DFF0, M_DFF1, M_SCSI
  2229. dont_generate_debug_code
  2230. }
  2231. /*
  2232. * Data FIFO SCSI Transfer Control
  2233. */
  2234. register DFFSXFRCTL {
  2235. address 0x05A
  2236. access_mode RW
  2237. modes M_DFF0, M_DFF1
  2238. field DFFBITBUCKET 0x08
  2239. field CLRSHCNT 0x04
  2240. field CLRCHN 0x02
  2241. field RSTCHN 0x01
  2242. }
  2243. /*
  2244. * Next SCSI Control Block
  2245. */
  2246. register NEXTSCB {
  2247. address 0x05A
  2248. access_mode RW
  2249. size 2
  2250. modes M_SCSI
  2251. dont_generate_debug_code
  2252. }
  2253. /*
  2254. * LQO SCSI Control
  2255. * (Rev B only.)
  2256. */
  2257. register LQOSCSCTL {
  2258. address 0x05A
  2259. access_mode RW
  2260. size 1
  2261. modes M_CFG
  2262. count 1
  2263. field LQOH2A_VERSION 0x80
  2264. field LQOBUSETDLY 0x40
  2265. field LQONOHOLDLACK 0x02
  2266. field LQONOCHKOVER 0x01
  2267. dont_generate_debug_code
  2268. }
  2269. /*
  2270. * SEQ Interrupts
  2271. */
  2272. register SEQINTSRC {
  2273. address 0x05B
  2274. access_mode RO
  2275. modes M_DFF0, M_DFF1
  2276. field CTXTDONE 0x40
  2277. field SAVEPTRS 0x20
  2278. field CFG4DATA 0x10
  2279. field CFG4ISTAT 0x08
  2280. field CFG4TSTAT 0x04
  2281. field CFG4ICMD 0x02
  2282. field CFG4TCMD 0x01
  2283. }
  2284. /*
  2285. * Clear Arp Interrupts
  2286. */
  2287. register CLRSEQINTSRC {
  2288. address 0x05B
  2289. access_mode WO
  2290. modes M_DFF0, M_DFF1
  2291. field CLRCTXTDONE 0x40
  2292. field CLRSAVEPTRS 0x20
  2293. field CLRCFG4DATA 0x10
  2294. field CLRCFG4ISTAT 0x08
  2295. field CLRCFG4TSTAT 0x04
  2296. field CLRCFG4ICMD 0x02
  2297. field CLRCFG4TCMD 0x01
  2298. dont_generate_debug_code
  2299. }
  2300. /*
  2301. * SEQ Interrupt Enabled (Shared)
  2302. */
  2303. register SEQIMODE {
  2304. address 0x05C
  2305. access_mode RW
  2306. modes M_DFF0, M_DFF1
  2307. field ENCTXTDONE 0x40
  2308. field ENSAVEPTRS 0x20
  2309. field ENCFG4DATA 0x10
  2310. field ENCFG4ISTAT 0x08
  2311. field ENCFG4TSTAT 0x04
  2312. field ENCFG4ICMD 0x02
  2313. field ENCFG4TCMD 0x01
  2314. }
  2315. /*
  2316. * Current SCSI Control Block
  2317. */
  2318. register CURRSCB {
  2319. address 0x05C
  2320. access_mode RW
  2321. size 2
  2322. modes M_SCSI
  2323. dont_generate_debug_code
  2324. }
  2325. /*
  2326. * Data FIFO Status
  2327. */
  2328. register MDFFSTAT {
  2329. address 0x05D
  2330. access_mode RO
  2331. modes M_DFF0, M_DFF1
  2332. field SHCNTNEGATIVE 0x40 /* Rev B or higher */
  2333. field SHCNTMINUS1 0x20 /* Rev B or higher */
  2334. field LASTSDONE 0x10
  2335. field SHVALID 0x08
  2336. field DLZERO 0x04 /* FIFO data ends on packet boundary. */
  2337. field DATAINFIFO 0x02
  2338. field FIFOFREE 0x01
  2339. }
  2340. /*
  2341. * CRC Control
  2342. */
  2343. register CRCCONTROL {
  2344. address 0x05d
  2345. access_mode RW
  2346. modes M_CFG
  2347. field CRCVALCHKEN 0x40
  2348. }
  2349. /*
  2350. * SCSI Test Control
  2351. */
  2352. register SCSITEST {
  2353. address 0x05E
  2354. access_mode RW
  2355. modes M_CFG
  2356. field CNTRTEST 0x08
  2357. field SEL_TXPLL_DEBUG 0x04
  2358. }
  2359. /*
  2360. * Data FIFO Queue Tag
  2361. */
  2362. register DFFTAG {
  2363. address 0x05E
  2364. access_mode RW
  2365. size 2
  2366. modes M_DFF0, M_DFF1
  2367. }
  2368. /*
  2369. * Last SCSI Control Block
  2370. */
  2371. register LASTSCB {
  2372. address 0x05E
  2373. access_mode RW
  2374. size 2
  2375. modes M_SCSI
  2376. dont_generate_debug_code
  2377. }
  2378. /*
  2379. * SCSI I/O Cell Power-down Control
  2380. */
  2381. register IOPDNCTL {
  2382. address 0x05F
  2383. access_mode RW
  2384. modes M_CFG
  2385. field DISABLE_OE 0x80
  2386. field PDN_IDIST 0x04
  2387. field PDN_DIFFSENSE 0x01
  2388. }
  2389. /*
  2390. * Shadow Host Address.
  2391. */
  2392. register SHADDR {
  2393. address 0x060
  2394. access_mode RO
  2395. size 8
  2396. modes M_DFF0, M_DFF1
  2397. dont_generate_debug_code
  2398. }
  2399. /*
  2400. * Data Group CRC Interval.
  2401. */
  2402. register DGRPCRCI {
  2403. address 0x060
  2404. access_mode RW
  2405. size 2
  2406. modes M_CFG
  2407. }
  2408. /*
  2409. * Data Transfer Negotiation Address
  2410. */
  2411. register NEGOADDR {
  2412. address 0x060
  2413. access_mode RW
  2414. modes M_SCSI
  2415. dont_generate_debug_code
  2416. }
  2417. /*
  2418. * Data Transfer Negotiation Data - Period Byte
  2419. */
  2420. register NEGPERIOD {
  2421. address 0x061
  2422. access_mode RW
  2423. modes M_SCSI
  2424. count 1
  2425. dont_generate_debug_code
  2426. }
  2427. /*
  2428. * Packetized CRC Interval
  2429. */
  2430. register PACKCRCI {
  2431. address 0x062
  2432. access_mode RW
  2433. size 2
  2434. modes M_CFG
  2435. }
  2436. /*
  2437. * Data Transfer Negotiation Data - Offset Byte
  2438. */
  2439. register NEGOFFSET {
  2440. address 0x062
  2441. access_mode RW
  2442. modes M_SCSI
  2443. count 1
  2444. dont_generate_debug_code
  2445. }
  2446. /*
  2447. * Data Transfer Negotiation Data - PPR Options
  2448. */
  2449. register NEGPPROPTS {
  2450. address 0x063
  2451. access_mode RW
  2452. modes M_SCSI
  2453. count 1
  2454. field PPROPT_PACE 0x08
  2455. field PPROPT_QAS 0x04
  2456. field PPROPT_DT 0x02
  2457. field PPROPT_IUT 0x01
  2458. dont_generate_debug_code
  2459. }
  2460. /*
  2461. * Data Transfer Negotiation Data - Connection Options
  2462. */
  2463. register NEGCONOPTS {
  2464. address 0x064
  2465. access_mode RW
  2466. modes M_SCSI
  2467. field ENSNAPSHOT 0x40
  2468. field RTI_WRTDIS 0x20
  2469. field RTI_OVRDTRN 0x10
  2470. field ENSLOWCRC 0x08
  2471. field ENAUTOATNI 0x04
  2472. field ENAUTOATNO 0x02
  2473. field WIDEXFER 0x01
  2474. dont_generate_debug_code
  2475. }
  2476. /*
  2477. * Negotiation Table Annex Column Index.
  2478. */
  2479. register ANNEXCOL {
  2480. address 0x065
  2481. access_mode RW
  2482. modes M_SCSI
  2483. count 7
  2484. dont_generate_debug_code
  2485. }
  2486. /*
  2487. * SCSI Check
  2488. * (Rev. B only)
  2489. */
  2490. register SCSCHKN {
  2491. address 0x066
  2492. access_mode RW
  2493. modes M_CFG
  2494. count 1
  2495. field BIDICHKDIS 0x80
  2496. field STSELSKIDDIS 0x40
  2497. field CURRFIFODEF 0x20
  2498. field WIDERESEN 0x10
  2499. field SDONEMSKDIS 0x08
  2500. field DFFACTCLR 0x04
  2501. field SHVALIDSTDIS 0x02
  2502. field LSTSGCLRDIS 0x01
  2503. dont_generate_debug_code
  2504. }
  2505. const AHD_ANNEXCOL_PER_DEV0 4
  2506. const AHD_NUM_PER_DEV_ANNEXCOLS 4
  2507. const AHD_ANNEXCOL_PRECOMP_SLEW 4
  2508. const AHD_PRECOMP_MASK 0x07
  2509. const AHD_PRECOMP_SHIFT 0
  2510. const AHD_PRECOMP_CUTBACK_17 0x04
  2511. const AHD_PRECOMP_CUTBACK_29 0x06
  2512. const AHD_PRECOMP_CUTBACK_37 0x07
  2513. const AHD_SLEWRATE_MASK 0x78
  2514. const AHD_SLEWRATE_SHIFT 3
  2515. /*
  2516. * Rev A has only a single bit (high bit of field) of slew adjustment.
  2517. * Rev B has 4 bits. The current default happens to be the same for both.
  2518. */
  2519. const AHD_SLEWRATE_DEF_REVA 0x08
  2520. const AHD_SLEWRATE_DEF_REVB 0x08
  2521. /* Rev A does not have any amplitude setting. */
  2522. const AHD_ANNEXCOL_AMPLITUDE 6
  2523. const AHD_AMPLITUDE_MASK 0x7
  2524. const AHD_AMPLITUDE_SHIFT 0
  2525. const AHD_AMPLITUDE_DEF 0x7
  2526. /*
  2527. * Negotiation Table Annex Data Port.
  2528. */
  2529. register ANNEXDAT {
  2530. address 0x066
  2531. access_mode RW
  2532. modes M_SCSI
  2533. count 3
  2534. dont_generate_debug_code
  2535. }
  2536. /*
  2537. * Initiator's Own Id.
  2538. * The SCSI ID to use for Selection Out and seen during a reselection..
  2539. */
  2540. register IOWNID {
  2541. address 0x067
  2542. access_mode RW
  2543. modes M_SCSI
  2544. dont_generate_debug_code
  2545. }
  2546. /*
  2547. * 960MHz Phase-Locked Loop Control 0
  2548. */
  2549. register PLL960CTL0 {
  2550. address 0x068
  2551. access_mode RW
  2552. modes M_CFG
  2553. field PLL_VCOSEL 0x80
  2554. field PLL_PWDN 0x40
  2555. field PLL_NS 0x30
  2556. field PLL_ENLUD 0x08
  2557. field PLL_ENLPF 0x04
  2558. field PLL_DLPF 0x02
  2559. field PLL_ENFBM 0x01
  2560. }
  2561. /*
  2562. * Target Own Id
  2563. */
  2564. register TOWNID {
  2565. address 0x069
  2566. access_mode RW
  2567. modes M_SCSI
  2568. count 2
  2569. dont_generate_debug_code
  2570. }
  2571. /*
  2572. * 960MHz Phase-Locked Loop Control 1
  2573. */
  2574. register PLL960CTL1 {
  2575. address 0x069
  2576. access_mode RW
  2577. modes M_CFG
  2578. field PLL_CNTEN 0x80
  2579. field PLL_CNTCLR 0x40
  2580. field PLL_RST 0x01
  2581. }
  2582. /*
  2583. * Expander Signature
  2584. */
  2585. register XSIG {
  2586. address 0x06A
  2587. access_mode RW
  2588. modes M_SCSI
  2589. }
  2590. /*
  2591. * Shadow Byte Count
  2592. */
  2593. register SHCNT {
  2594. address 0x068
  2595. access_mode RW
  2596. size 3
  2597. modes M_DFF0, M_DFF1
  2598. dont_generate_debug_code
  2599. }
  2600. /*
  2601. * Selection Out ID
  2602. */
  2603. register SELOID {
  2604. address 0x06B
  2605. access_mode RW
  2606. modes M_SCSI
  2607. }
  2608. /*
  2609. * 960-MHz Phase-Locked Loop Test Count
  2610. */
  2611. register PLL960CNT0 {
  2612. address 0x06A
  2613. access_mode RO
  2614. size 2
  2615. modes M_CFG
  2616. }
  2617. /*
  2618. * 400-MHz Phase-Locked Loop Control 0
  2619. */
  2620. register PLL400CTL0 {
  2621. address 0x06C
  2622. access_mode RW
  2623. modes M_CFG
  2624. field PLL_VCOSEL 0x80
  2625. field PLL_PWDN 0x40
  2626. field PLL_NS 0x30
  2627. field PLL_ENLUD 0x08
  2628. field PLL_ENLPF 0x04
  2629. field PLL_DLPF 0x02
  2630. field PLL_ENFBM 0x01
  2631. }
  2632. /*
  2633. * Arbitration Fairness
  2634. */
  2635. register FAIRNESS {
  2636. address 0x06C
  2637. access_mode RW
  2638. size 2
  2639. modes M_SCSI
  2640. }
  2641. /*
  2642. * 400-MHz Phase-Locked Loop Control 1
  2643. */
  2644. register PLL400CTL1 {
  2645. address 0x06D
  2646. access_mode RW
  2647. modes M_CFG
  2648. field PLL_CNTEN 0x80
  2649. field PLL_CNTCLR 0x40
  2650. field PLL_RST 0x01
  2651. }
  2652. /*
  2653. * Arbitration Unfairness
  2654. */
  2655. register UNFAIRNESS {
  2656. address 0x06E
  2657. access_mode RW
  2658. size 2
  2659. modes M_SCSI
  2660. }
  2661. /*
  2662. * 400-MHz Phase-Locked Loop Test Count
  2663. */
  2664. register PLL400CNT0 {
  2665. address 0x06E
  2666. access_mode RO
  2667. size 2
  2668. modes M_CFG
  2669. }
  2670. /*
  2671. * SCB Page Pointer
  2672. */
  2673. register SCBPTR {
  2674. address 0x0A8
  2675. access_mode RW
  2676. size 2
  2677. modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI
  2678. dont_generate_debug_code
  2679. }
  2680. /*
  2681. * CMC SCB Array Count
  2682. * Number of bytes to transfer between CMC SCB memory and SCBRAM.
  2683. * Transfers must be 8byte aligned and sized.
  2684. */
  2685. register CCSCBACNT {
  2686. address 0x0AB
  2687. access_mode RW
  2688. modes M_CCHAN
  2689. }
  2690. /*
  2691. * SCB Autopointer
  2692. * SCB-Next Address Snooping logic. When an SCB is transferred to
  2693. * the card, the next SCB address to be used by the CMC array can
  2694. * be autoloaded from that transfer.
  2695. */
  2696. register SCBAUTOPTR {
  2697. address 0x0AB
  2698. access_mode RW
  2699. modes M_CFG
  2700. count 1
  2701. field AUSCBPTR_EN 0x80
  2702. field SCBPTR_ADDR 0x38
  2703. field SCBPTR_OFF 0x07
  2704. dont_generate_debug_code
  2705. }
  2706. /*
  2707. * CMC SG Ram Address Pointer
  2708. */
  2709. register CCSGADDR {
  2710. address 0x0AC
  2711. access_mode RW
  2712. modes M_DFF0, M_DFF1
  2713. dont_generate_debug_code
  2714. }
  2715. /*
  2716. * CMC SCB RAM Address Pointer
  2717. */
  2718. register CCSCBADDR {
  2719. address 0x0AC
  2720. access_mode RW
  2721. modes M_CCHAN
  2722. dont_generate_debug_code
  2723. }
  2724. /*
  2725. * CMC SCB Ram Back-up Address Pointer
  2726. * Indicates the true stop location of transfers halted prior
  2727. * to SCBHCNT going to 0.
  2728. */
  2729. register CCSCBADR_BK {
  2730. address 0x0AC
  2731. access_mode RO
  2732. modes M_CFG
  2733. }
  2734. /*
  2735. * CMC SG Control
  2736. */
  2737. register CCSGCTL {
  2738. address 0x0AD
  2739. access_mode RW
  2740. modes M_DFF0, M_DFF1
  2741. field CCSGDONE 0x80
  2742. field SG_CACHE_AVAIL 0x10
  2743. field CCSGENACK 0x08
  2744. mask CCSGEN 0x0C
  2745. field SG_FETCH_REQ 0x02
  2746. field CCSGRESET 0x01
  2747. }
  2748. /*
  2749. * CMD SCB Control
  2750. */
  2751. register CCSCBCTL {
  2752. address 0x0AD
  2753. access_mode RW
  2754. modes M_CCHAN
  2755. field CCSCBDONE 0x80
  2756. field ARRDONE 0x40
  2757. field CCARREN 0x10
  2758. field CCSCBEN 0x08
  2759. field CCSCBDIR 0x04
  2760. field CCSCBRESET 0x01
  2761. }
  2762. /*
  2763. * CMC Ram BIST
  2764. */
  2765. register CMC_RAMBIST {
  2766. address 0x0AD
  2767. access_mode RW
  2768. modes M_CFG
  2769. field SG_ELEMENT_SIZE 0x80
  2770. field SCBRAMBIST_FAIL 0x40
  2771. field SG_BIST_FAIL 0x20
  2772. field SG_BIST_EN 0x10
  2773. field CMC_BUFFER_BIST_FAIL 0x02
  2774. field CMC_BUFFER_BIST_EN 0x01
  2775. }
  2776. /*
  2777. * CMC SG RAM Data Port
  2778. */
  2779. register CCSGRAM {
  2780. address 0x0B0
  2781. access_mode RW
  2782. modes M_DFF0, M_DFF1
  2783. dont_generate_debug_code
  2784. }
  2785. /*
  2786. * CMC SCB RAM Data Port
  2787. */
  2788. register CCSCBRAM {
  2789. address 0x0B0
  2790. access_mode RW
  2791. modes M_CCHAN
  2792. dont_generate_debug_code
  2793. }
  2794. /*
  2795. * Flex DMA Address.
  2796. */
  2797. register FLEXADR {
  2798. address 0x0B0
  2799. access_mode RW
  2800. size 3
  2801. modes M_SCSI
  2802. }
  2803. /*
  2804. * Flex DMA Byte Count
  2805. */
  2806. register FLEXCNT {
  2807. address 0x0B3
  2808. access_mode RW
  2809. size 2
  2810. modes M_SCSI
  2811. }
  2812. /*
  2813. * Flex DMA Status
  2814. */
  2815. register FLEXDMASTAT {
  2816. address 0x0B5
  2817. access_mode RW
  2818. modes M_SCSI
  2819. field FLEXDMAERR 0x02
  2820. field FLEXDMADONE 0x01
  2821. }
  2822. /*
  2823. * Flex DMA Data Port
  2824. */
  2825. register FLEXDATA {
  2826. address 0x0B6
  2827. access_mode RW
  2828. modes M_SCSI
  2829. }
  2830. /*
  2831. * Board Data
  2832. */
  2833. register BRDDAT {
  2834. address 0x0B8
  2835. access_mode RW
  2836. modes M_SCSI
  2837. count 2
  2838. dont_generate_debug_code
  2839. }
  2840. /*
  2841. * Board Control
  2842. */
  2843. register BRDCTL {
  2844. address 0x0B9
  2845. access_mode RW
  2846. modes M_SCSI
  2847. count 7
  2848. field FLXARBACK 0x80
  2849. field FLXARBREQ 0x40
  2850. field BRDADDR 0x38
  2851. field BRDEN 0x04
  2852. field BRDRW 0x02
  2853. field BRDSTB 0x01
  2854. dont_generate_debug_code
  2855. }
  2856. /*
  2857. * Serial EEPROM Address
  2858. */
  2859. register SEEADR {
  2860. address 0x0BA
  2861. access_mode RW
  2862. modes M_SCSI
  2863. count 4
  2864. dont_generate_debug_code
  2865. }
  2866. /*
  2867. * Serial EEPROM Data
  2868. */
  2869. register SEEDAT {
  2870. address 0x0BC
  2871. access_mode RW
  2872. size 2
  2873. modes M_SCSI
  2874. count 4
  2875. dont_generate_debug_code
  2876. }
  2877. /*
  2878. * Serial EEPROM Status
  2879. */
  2880. register SEESTAT {
  2881. address 0x0BE
  2882. access_mode RO
  2883. modes M_SCSI
  2884. count 1
  2885. field INIT_DONE 0x80
  2886. field SEEOPCODE 0x70
  2887. field LDALTID_L 0x08
  2888. field SEEARBACK 0x04
  2889. field SEEBUSY 0x02
  2890. field SEESTART 0x01
  2891. dont_generate_debug_code
  2892. }
  2893. /*
  2894. * Serial EEPROM Control
  2895. */
  2896. register SEECTL {
  2897. address 0x0BE
  2898. access_mode RW
  2899. modes M_SCSI
  2900. count 4
  2901. field SEEOPCODE 0x70 {
  2902. SEEOP_ERASE 0x70,
  2903. SEEOP_READ 0x60,
  2904. SEEOP_WRITE 0x50,
  2905. /*
  2906. * The following four commands use special
  2907. * addresses for differentiation.
  2908. */
  2909. SEEOP_ERAL 0x40
  2910. }
  2911. mask SEEOP_EWEN 0x40
  2912. mask SEEOP_WALL 0x40
  2913. mask SEEOP_EWDS 0x40
  2914. field SEERST 0x02
  2915. field SEESTART 0x01
  2916. dont_generate_debug_code
  2917. }
  2918. const SEEOP_ERAL_ADDR 0x80
  2919. const SEEOP_EWEN_ADDR 0xC0
  2920. const SEEOP_WRAL_ADDR 0x40
  2921. const SEEOP_EWDS_ADDR 0x00
  2922. /*
  2923. * SCB Counter
  2924. */
  2925. register SCBCNT {
  2926. address 0x0BF
  2927. access_mode RW
  2928. modes M_SCSI
  2929. dont_generate_debug_code
  2930. }
  2931. /*
  2932. * Data FIFO Write Address
  2933. * Pointer to the next QWD location to be written to the data FIFO.
  2934. */
  2935. register DFWADDR {
  2936. address 0x0C0
  2937. access_mode RW
  2938. size 2
  2939. modes M_DFF0, M_DFF1
  2940. dont_generate_debug_code
  2941. }
  2942. /*
  2943. * DSP Filter Control
  2944. */
  2945. register DSPFLTRCTL {
  2946. address 0x0C0
  2947. access_mode RW
  2948. modes M_CFG
  2949. field FLTRDISABLE 0x20
  2950. field EDGESENSE 0x10
  2951. field DSPFCNTSEL 0x0F
  2952. }
  2953. /*
  2954. * DSP Data Channel Control
  2955. */
  2956. register DSPDATACTL {
  2957. address 0x0C1
  2958. access_mode RW
  2959. modes M_CFG
  2960. count 3
  2961. field BYPASSENAB 0x80
  2962. field DESQDIS 0x10
  2963. field RCVROFFSTDIS 0x04
  2964. field XMITOFFSTDIS 0x02
  2965. dont_generate_debug_code
  2966. }
  2967. /*
  2968. * Data FIFO Read Address
  2969. * Pointer to the next QWD location to be read from the data FIFO.
  2970. */
  2971. register DFRADDR {
  2972. address 0x0C2
  2973. access_mode RW
  2974. size 2
  2975. modes M_DFF0, M_DFF1
  2976. }
  2977. /*
  2978. * DSP REQ Control
  2979. */
  2980. register DSPREQCTL {
  2981. address 0x0C2
  2982. access_mode RW
  2983. modes M_CFG
  2984. field MANREQCTL 0xC0
  2985. field MANREQDLY 0x3F
  2986. }
  2987. /*
  2988. * DSP ACK Control
  2989. */
  2990. register DSPACKCTL {
  2991. address 0x0C3
  2992. access_mode RW
  2993. modes M_CFG
  2994. field MANACKCTL 0xC0
  2995. field MANACKDLY 0x3F
  2996. }
  2997. /*
  2998. * Data FIFO Data
  2999. * Read/Write byte port into the data FIFO. The read and write
  3000. * FIFO pointers increment with each read and write respectively
  3001. * to this port.
  3002. */
  3003. register DFDAT {
  3004. address 0x0C4
  3005. access_mode RW
  3006. modes M_DFF0, M_DFF1
  3007. dont_generate_debug_code
  3008. }
  3009. /*
  3010. * DSP Channel Select
  3011. */
  3012. register DSPSELECT {
  3013. address 0x0C4
  3014. access_mode RW
  3015. modes M_CFG
  3016. count 1
  3017. field AUTOINCEN 0x80
  3018. field DSPSEL 0x1F
  3019. dont_generate_debug_code
  3020. }
  3021. const NUMDSPS 0x14
  3022. /*
  3023. * Write Bias Control
  3024. */
  3025. register WRTBIASCTL {
  3026. address 0x0C5
  3027. access_mode WO
  3028. modes M_CFG
  3029. count 3
  3030. field AUTOXBCDIS 0x80
  3031. field XMITMANVAL 0x3F
  3032. dont_generate_debug_code
  3033. }
  3034. /*
  3035. * Currently the WRTBIASCTL is the same as the default.
  3036. */
  3037. const WRTBIASCTL_HP_DEFAULT 0x0
  3038. /*
  3039. * Receiver Bias Control
  3040. */
  3041. register RCVRBIOSCTL {
  3042. address 0x0C6
  3043. access_mode WO
  3044. modes M_CFG
  3045. field AUTORBCDIS 0x80
  3046. field RCVRMANVAL 0x3F
  3047. }
  3048. /*
  3049. * Write Bias Calculator
  3050. */
  3051. register WRTBIASCALC {
  3052. address 0x0C7
  3053. access_mode RO
  3054. modes M_CFG
  3055. }
  3056. /*
  3057. * Data FIFO Pointers
  3058. * Contains the byte offset from DFWADDR and DWRADDR to the current
  3059. * FIFO write/read locations.
  3060. */
  3061. register DFPTRS {
  3062. address 0x0C8
  3063. access_mode RW
  3064. modes M_DFF0, M_DFF1
  3065. }
  3066. /*
  3067. * Receiver Bias Calculator
  3068. */
  3069. register RCVRBIASCALC {
  3070. address 0x0C8
  3071. access_mode RO
  3072. modes M_CFG
  3073. }
  3074. /*
  3075. * Data FIFO Backup Read Pointer
  3076. * Contains the data FIFO address to be restored if the last
  3077. * data accessed from the data FIFO was not transferred successfully.
  3078. */
  3079. register DFBKPTR {
  3080. address 0x0C9
  3081. access_mode RW
  3082. size 2
  3083. modes M_DFF0, M_DFF1
  3084. }
  3085. /*
  3086. * Skew Calculator
  3087. */
  3088. register SKEWCALC {
  3089. address 0x0C9
  3090. access_mode RO
  3091. modes M_CFG
  3092. }
  3093. /*
  3094. * Data FIFO Debug Control
  3095. */
  3096. register DFDBCTL {
  3097. address 0x0CB
  3098. access_mode RW
  3099. modes M_DFF0, M_DFF1
  3100. field DFF_CIO_WR_RDY 0x20
  3101. field DFF_CIO_RD_RDY 0x10
  3102. field DFF_DIR_ERR 0x08
  3103. field DFF_RAMBIST_FAIL 0x04
  3104. field DFF_RAMBIST_DONE 0x02
  3105. field DFF_RAMBIST_EN 0x01
  3106. }
  3107. /*
  3108. * Data FIFO Space Count
  3109. * Number of FIFO locations that are free.
  3110. */
  3111. register DFSCNT {
  3112. address 0x0CC
  3113. access_mode RO
  3114. size 2
  3115. modes M_DFF0, M_DFF1
  3116. }
  3117. /*
  3118. * Data FIFO Byte Count
  3119. * Number of filled FIFO locations.
  3120. */
  3121. register DFBCNT {
  3122. address 0x0CE
  3123. access_mode RO
  3124. size 2
  3125. modes M_DFF0, M_DFF1
  3126. }
  3127. /*
  3128. * Sequencer Program Overlay Address.
  3129. * Low address must be written prior to high address.
  3130. */
  3131. register OVLYADDR {
  3132. address 0x0D4
  3133. modes M_SCSI
  3134. size 2
  3135. access_mode RW
  3136. }
  3137. /*
  3138. * Sequencer Control 0
  3139. * Error detection mode, speed configuration,
  3140. * single step, breakpoints and program load.
  3141. */
  3142. register SEQCTL0 {
  3143. address 0x0D6
  3144. access_mode RW
  3145. count 11
  3146. field PERRORDIS 0x80
  3147. field PAUSEDIS 0x40
  3148. field FAILDIS 0x20
  3149. field FASTMODE 0x10
  3150. field BRKADRINTEN 0x08
  3151. field STEP 0x04
  3152. field SEQRESET 0x02
  3153. field LOADRAM 0x01
  3154. }
  3155. /*
  3156. * Sequencer Control 1
  3157. * Instruction RAM Diagnostics
  3158. */
  3159. register SEQCTL1 {
  3160. address 0x0D7
  3161. access_mode RW
  3162. field OVRLAY_DATA_CHK 0x08
  3163. field RAMBIST_DONE 0x04
  3164. field RAMBIST_FAIL 0x02
  3165. field RAMBIST_EN 0x01
  3166. }
  3167. /*
  3168. * Sequencer Flags
  3169. * Zero and Carry state of the ALU.
  3170. */
  3171. register FLAGS {
  3172. address 0x0D8
  3173. access_mode RO
  3174. count 23
  3175. field ZERO 0x02
  3176. field CARRY 0x01
  3177. dont_generate_debug_code
  3178. }
  3179. /*
  3180. * Sequencer Interrupt Control
  3181. */
  3182. register SEQINTCTL {
  3183. address 0x0D9
  3184. access_mode RW
  3185. field INTVEC1DSL 0x80
  3186. field INT1_CONTEXT 0x20
  3187. field SCS_SEQ_INT1M1 0x10
  3188. field SCS_SEQ_INT1M0 0x08
  3189. field INTMASK2 0x04
  3190. field INTMASK1 0x02
  3191. field IRET 0x01
  3192. }
  3193. /*
  3194. * Sequencer RAM Data Port
  3195. * Single byte window into the Sequencer Instruction Ram area starting
  3196. * at the address specified by OVLYADDR. To write a full instruction word,
  3197. * simply write four bytes in succession. OVLYADDR will increment after the
  3198. * most significant instrution byte (the byte with the parity bit) is written.
  3199. */
  3200. register SEQRAM {
  3201. address 0x0DA
  3202. access_mode RW
  3203. count 2
  3204. dont_generate_debug_code
  3205. }
  3206. /*
  3207. * Sequencer Program Counter
  3208. * Low byte must be written prior to high byte.
  3209. */
  3210. register PRGMCNT {
  3211. address 0x0DE
  3212. access_mode RW
  3213. size 2
  3214. count 5
  3215. dont_generate_debug_code
  3216. }
  3217. /*
  3218. * Accumulator
  3219. */
  3220. register ACCUM {
  3221. address 0x0E0
  3222. access_mode RW
  3223. accumulator
  3224. dont_generate_debug_code
  3225. }
  3226. /*
  3227. * Source Index Register
  3228. * Incrementing index for reads of SINDIR and the destination (low byte only)
  3229. * for any immediate operands passed in jmp, jc, jnc, call instructions.
  3230. * Example:
  3231. * mvi 0xFF call some_routine;
  3232. *
  3233. * Will set SINDEX[0] to 0xFF and call the routine "some_routine.
  3234. */
  3235. register SINDEX {
  3236. address 0x0E2
  3237. access_mode RW
  3238. size 2
  3239. sindex
  3240. dont_generate_debug_code
  3241. }
  3242. /*
  3243. * Destination Index Register
  3244. * Incrementing index for writes to DINDIR. Can be used as a scratch register.
  3245. */
  3246. register DINDEX {
  3247. address 0x0E4
  3248. access_mode RW
  3249. size 2
  3250. dont_generate_debug_code
  3251. }
  3252. /*
  3253. * Break Address
  3254. * Sequencer instruction breakpoint address address.
  3255. */
  3256. register BRKADDR0 {
  3257. address 0x0E6
  3258. access_mode RW
  3259. }
  3260. register BRKADDR1 {
  3261. address 0x0E6
  3262. access_mode RW
  3263. field BRKDIS 0x80 /* Disable Breakpoint */
  3264. }
  3265. /*
  3266. * All Ones
  3267. * All reads to this register return the value 0xFF.
  3268. */
  3269. register ALLONES {
  3270. address 0x0E8
  3271. access_mode RO
  3272. allones
  3273. dont_generate_debug_code
  3274. }
  3275. /*
  3276. * All Zeros
  3277. * All reads to this register return the value 0.
  3278. */
  3279. register ALLZEROS {
  3280. address 0x0EA
  3281. access_mode RO
  3282. allzeros
  3283. dont_generate_debug_code
  3284. }
  3285. /*
  3286. * No Destination
  3287. * Writes to this register have no effect.
  3288. */
  3289. register NONE {
  3290. address 0x0EA
  3291. access_mode WO
  3292. none
  3293. dont_generate_debug_code
  3294. }
  3295. /*
  3296. * Source Index Indirect
  3297. * Reading this register is equivalent to reading (register_base + SINDEX) and
  3298. * incrementing SINDEX by 1.
  3299. */
  3300. register SINDIR {
  3301. address 0x0EC
  3302. access_mode RO
  3303. dont_generate_debug_code
  3304. }
  3305. /*
  3306. * Destination Index Indirect
  3307. * Writing this register is equivalent to writing to (register_base + DINDEX)
  3308. * and incrementing DINDEX by 1.
  3309. */
  3310. register DINDIR {
  3311. address 0x0ED
  3312. access_mode WO
  3313. dont_generate_debug_code
  3314. }
  3315. /*
  3316. * Function One
  3317. * 2's complement to bit value conversion. Write the 2's complement value
  3318. * (0-7 only) to the top nibble and retrieve the bit indexed by that value
  3319. * on the next read of this register.
  3320. * Example:
  3321. * Write 0x60
  3322. * Read 0x40
  3323. */
  3324. register FUNCTION1 {
  3325. address 0x0F0
  3326. access_mode RW
  3327. }
  3328. /*
  3329. * Stack
  3330. * Window into the stack. Each stack location is 10 bits wide reported
  3331. * low byte followed by high byte. There are 8 stack locations.
  3332. */
  3333. register STACK {
  3334. address 0x0F2
  3335. access_mode RW
  3336. dont_generate_debug_code
  3337. }
  3338. /*
  3339. * Interrupt Vector 1 Address
  3340. * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
  3341. */
  3342. register INTVEC1_ADDR {
  3343. address 0x0F4
  3344. access_mode RW
  3345. size 2
  3346. modes M_CFG
  3347. count 1
  3348. dont_generate_debug_code
  3349. }
  3350. /*
  3351. * Current Address
  3352. * Address of the SEQRAM instruction currently executing instruction.
  3353. */
  3354. register CURADDR {
  3355. address 0x0F4
  3356. access_mode RW
  3357. size 2
  3358. modes M_SCSI
  3359. count 2
  3360. dont_generate_debug_code
  3361. }
  3362. /*
  3363. * Interrupt Vector 2 Address
  3364. * Interrupt branch address for HST_SEQ_INT2 interrupts.
  3365. */
  3366. register INTVEC2_ADDR {
  3367. address 0x0F6
  3368. access_mode RW
  3369. size 2
  3370. modes M_CFG
  3371. count 1
  3372. dont_generate_debug_code
  3373. }
  3374. /*
  3375. * Last Address
  3376. * Address of the SEQRAM instruction executed prior to the current instruction.
  3377. */
  3378. register LASTADDR {
  3379. address 0x0F6
  3380. access_mode RW
  3381. size 2
  3382. modes M_SCSI
  3383. }
  3384. register AHD_PCI_CONFIG_BASE {
  3385. address 0x100
  3386. access_mode RW
  3387. size 256
  3388. modes M_CFG
  3389. }
  3390. /* ---------------------- Scratch RAM Offsets ------------------------- */
  3391. scratch_ram {
  3392. /* Mode Specific */
  3393. address 0x0A0
  3394. size 8
  3395. modes 0, 1, 2, 3
  3396. REG0 {
  3397. size 2
  3398. dont_generate_debug_code
  3399. }
  3400. REG1 {
  3401. size 2
  3402. }
  3403. REG_ISR {
  3404. size 2
  3405. dont_generate_debug_code
  3406. }
  3407. SG_STATE {
  3408. size 1
  3409. field SEGS_AVAIL 0x01
  3410. field LOADING_NEEDED 0x02
  3411. field FETCH_INPROG 0x04
  3412. }
  3413. /*
  3414. * Track whether the transfer byte count for
  3415. * the current data phase is odd.
  3416. */
  3417. DATA_COUNT_ODD {
  3418. size 1
  3419. }
  3420. }
  3421. scratch_ram {
  3422. /* Mode Specific */
  3423. address 0x0F8
  3424. size 8
  3425. modes 0, 1, 2, 3
  3426. LONGJMP_ADDR {
  3427. size 2
  3428. dont_generate_debug_code
  3429. }
  3430. ACCUM_SAVE {
  3431. size 1
  3432. dont_generate_debug_code
  3433. }
  3434. }
  3435. scratch_ram {
  3436. address 0x100
  3437. size 128
  3438. modes 0, 1, 2, 3
  3439. /*
  3440. * Per "other-id" execution queues. We use an array of
  3441. * tail pointers into lists of SCBs sorted by "other-id".
  3442. * The execution head pointer threads the head SCBs for
  3443. * each list.
  3444. */
  3445. WAITING_SCB_TAILS {
  3446. size 32
  3447. dont_generate_debug_code
  3448. }
  3449. WAITING_TID_HEAD {
  3450. size 2
  3451. dont_generate_debug_code
  3452. }
  3453. WAITING_TID_TAIL {
  3454. size 2
  3455. dont_generate_debug_code
  3456. }
  3457. /*
  3458. * SCBID of the next SCB in the new SCB queue.
  3459. */
  3460. NEXT_QUEUED_SCB_ADDR {
  3461. size 4
  3462. dont_generate_debug_code
  3463. }
  3464. /*
  3465. * head of list of SCBs that have
  3466. * completed but have not been
  3467. * put into the qoutfifo.
  3468. */
  3469. COMPLETE_SCB_HEAD {
  3470. size 2
  3471. dont_generate_debug_code
  3472. }
  3473. /*
  3474. * The list of completed SCBs in
  3475. * the active DMA.
  3476. */
  3477. COMPLETE_SCB_DMAINPROG_HEAD {
  3478. size 2
  3479. dont_generate_debug_code
  3480. }
  3481. /*
  3482. * head of list of SCBs that have
  3483. * completed but need to be uploaded
  3484. * to the host prior to being completed.
  3485. */
  3486. COMPLETE_DMA_SCB_HEAD {
  3487. size 2
  3488. dont_generate_debug_code
  3489. }
  3490. /*
  3491. * tail of list of SCBs that have
  3492. * completed but need to be uploaded
  3493. * to the host prior to being completed.
  3494. */
  3495. COMPLETE_DMA_SCB_TAIL {
  3496. size 2
  3497. dont_generate_debug_code
  3498. }
  3499. /*
  3500. * head of list of SCBs that have
  3501. * been uploaded to the host, but cannot
  3502. * be completed until the QFREEZE is in
  3503. * full effect (i.e. no selections pending).
  3504. */
  3505. COMPLETE_ON_QFREEZE_HEAD {
  3506. size 2
  3507. dont_generate_debug_code
  3508. }
  3509. /*
  3510. * Counting semaphore to prevent new select-outs
  3511. * The queue is frozen so long as the sequencer
  3512. * and kernel freeze counts differ.
  3513. */
  3514. QFREEZE_COUNT {
  3515. size 2
  3516. }
  3517. KERNEL_QFREEZE_COUNT {
  3518. size 2
  3519. }
  3520. /*
  3521. * Mode to restore on legacy idle loop exit.
  3522. */
  3523. SAVED_MODE {
  3524. size 1
  3525. }
  3526. /*
  3527. * Single byte buffer used to designate the type or message
  3528. * to send to a target.
  3529. */
  3530. MSG_OUT {
  3531. size 1
  3532. dont_generate_debug_code
  3533. }
  3534. /* Parameters for DMA Logic */
  3535. DMAPARAMS {
  3536. size 1
  3537. count 8
  3538. field PRELOADEN 0x80
  3539. field WIDEODD 0x40
  3540. field SCSIEN 0x20
  3541. field SDMAEN 0x10
  3542. field SDMAENACK 0x10
  3543. field HDMAEN 0x08
  3544. field HDMAENACK 0x08
  3545. field DIRECTION 0x04 /* Set indicates PCI->SCSI */
  3546. field FIFOFLUSH 0x02
  3547. field FIFORESET 0x01
  3548. dont_generate_debug_code
  3549. }
  3550. SEQ_FLAGS {
  3551. size 1
  3552. field NOT_IDENTIFIED 0x80
  3553. field NO_CDB_SENT 0x40
  3554. field TARGET_CMD_IS_TAGGED 0x40
  3555. field DPHASE 0x20
  3556. /* Target flags */
  3557. field TARG_CMD_PENDING 0x10
  3558. field CMDPHASE_PENDING 0x08
  3559. field DPHASE_PENDING 0x04
  3560. field SPHASE_PENDING 0x02
  3561. field NO_DISCONNECT 0x01
  3562. }
  3563. /*
  3564. * Temporary storage for the
  3565. * target/channel/lun of a
  3566. * reconnecting target
  3567. */
  3568. SAVED_SCSIID {
  3569. size 1
  3570. dont_generate_debug_code
  3571. }
  3572. SAVED_LUN {
  3573. size 1
  3574. dont_generate_debug_code
  3575. }
  3576. /*
  3577. * The last bus phase as seen by the sequencer.
  3578. */
  3579. LASTPHASE {
  3580. size 1
  3581. field CDI 0x80
  3582. field IOI 0x40
  3583. field MSGI 0x20
  3584. field P_BUSFREE 0x01
  3585. enum PHASE_MASK CDO|IOO|MSGO {
  3586. P_DATAOUT 0x0,
  3587. P_DATAIN IOO,
  3588. P_DATAOUT_DT P_DATAOUT|MSGO,
  3589. P_DATAIN_DT P_DATAIN|MSGO,
  3590. P_COMMAND CDO,
  3591. P_MESGOUT CDO|MSGO,
  3592. P_STATUS CDO|IOO,
  3593. P_MESGIN CDO|IOO|MSGO
  3594. }
  3595. }
  3596. /*
  3597. * Value to "or" into the SCBPTR[1] value to
  3598. * indicate that an entry in the QINFIFO is valid.
  3599. */
  3600. QOUTFIFO_ENTRY_VALID_TAG {
  3601. size 1
  3602. dont_generate_debug_code
  3603. }
  3604. /*
  3605. * Kernel and sequencer offsets into the queue of
  3606. * incoming target mode command descriptors. The
  3607. * queue is full when the KERNEL_TQINPOS == TQINPOS.
  3608. */
  3609. KERNEL_TQINPOS {
  3610. size 1
  3611. count 1
  3612. dont_generate_debug_code
  3613. }
  3614. TQINPOS {
  3615. size 1
  3616. count 8
  3617. dont_generate_debug_code
  3618. }
  3619. /*
  3620. * Base address of our shared data with the kernel driver in host
  3621. * memory. This includes the qoutfifo and target mode
  3622. * incoming command queue.
  3623. */
  3624. SHARED_DATA_ADDR {
  3625. size 4
  3626. dont_generate_debug_code
  3627. }
  3628. /*
  3629. * Pointer to location in host memory for next
  3630. * position in the qoutfifo.
  3631. */
  3632. QOUTFIFO_NEXT_ADDR {
  3633. size 4
  3634. dont_generate_debug_code
  3635. }
  3636. ARG_1 {
  3637. size 1
  3638. mask SEND_MSG 0x80
  3639. mask SEND_SENSE 0x40
  3640. mask SEND_REJ 0x20
  3641. mask MSGOUT_PHASEMIS 0x10
  3642. mask EXIT_MSG_LOOP 0x08
  3643. mask CONT_MSG_LOOP_WRITE 0x04
  3644. mask CONT_MSG_LOOP_READ 0x03
  3645. mask CONT_MSG_LOOP_TARG 0x02
  3646. alias RETURN_1
  3647. dont_generate_debug_code
  3648. }
  3649. ARG_2 {
  3650. size 1
  3651. count 1
  3652. alias RETURN_2
  3653. dont_generate_debug_code
  3654. }
  3655. /*
  3656. * Snapshot of MSG_OUT taken after each message is sent.
  3657. */
  3658. LAST_MSG {
  3659. size 1
  3660. dont_generate_debug_code
  3661. }
  3662. /*
  3663. * Sequences the kernel driver has okayed for us. This allows
  3664. * the driver to do things like prevent initiator or target
  3665. * operations.
  3666. */
  3667. SCSISEQ_TEMPLATE {
  3668. size 1
  3669. count 7
  3670. field MANUALCTL 0x40
  3671. field ENSELI 0x20
  3672. field ENRSELI 0x10
  3673. field MANUALP 0x0C
  3674. field ENAUTOATNP 0x02
  3675. field ALTSTIM 0x01
  3676. dont_generate_debug_code
  3677. }
  3678. /*
  3679. * The initiator specified tag for this target mode transaction.
  3680. */
  3681. INITIATOR_TAG {
  3682. size 1
  3683. count 1
  3684. dont_generate_debug_code
  3685. }
  3686. SEQ_FLAGS2 {
  3687. size 1
  3688. field PENDING_MK_MESSAGE 0x01
  3689. field TARGET_MSG_PENDING 0x02
  3690. field SELECTOUT_QFROZEN 0x04
  3691. }
  3692. ALLOCFIFO_SCBPTR {
  3693. size 2
  3694. dont_generate_debug_code
  3695. }
  3696. /*
  3697. * The maximum amount of time to wait, when interrupt coalescing
  3698. * is enabled, before issuing a CMDCMPLT interrupt for a completed
  3699. * command.
  3700. */
  3701. INT_COALESCING_TIMER {
  3702. size 2
  3703. dont_generate_debug_code
  3704. }
  3705. /*
  3706. * The maximum number of commands to coalesce into a single interrupt.
  3707. * Actually the 2's complement of that value to simplify sequencer
  3708. * code.
  3709. */
  3710. INT_COALESCING_MAXCMDS {
  3711. size 1
  3712. dont_generate_debug_code
  3713. }
  3714. /*
  3715. * The minimum number of commands still outstanding required
  3716. * to continue coalescing (2's complement of value).
  3717. */
  3718. INT_COALESCING_MINCMDS {
  3719. size 1
  3720. dont_generate_debug_code
  3721. }
  3722. /*
  3723. * Number of commands "in-flight".
  3724. */
  3725. CMDS_PENDING {
  3726. size 2
  3727. dont_generate_debug_code
  3728. }
  3729. /*
  3730. * The count of commands that have been coalesced.
  3731. */
  3732. INT_COALESCING_CMDCOUNT {
  3733. size 1
  3734. dont_generate_debug_code
  3735. }
  3736. /*
  3737. * Since the HS_MAIBOX is self clearing, copy its contents to
  3738. * this position in scratch ram every time it changes.
  3739. */
  3740. LOCAL_HS_MAILBOX {
  3741. size 1
  3742. dont_generate_debug_code
  3743. }
  3744. /*
  3745. * Target-mode CDB type to CDB length table used
  3746. * in non-packetized operation.
  3747. */
  3748. CMDSIZE_TABLE {
  3749. size 8
  3750. count 8
  3751. dont_generate_debug_code
  3752. }
  3753. /*
  3754. * When an SCB with the MK_MESSAGE flag is
  3755. * queued to the controller, it cannot enter
  3756. * the waiting for selection list until the
  3757. * selections for any previously queued
  3758. * commands to that target complete. During
  3759. * the wait, the MK_MESSAGE SCB is queued
  3760. * here.
  3761. */
  3762. MK_MESSAGE_SCB {
  3763. size 2
  3764. }
  3765. /*
  3766. * Saved SCSIID of MK_MESSAGE_SCB to avoid
  3767. * an extra SCBPTR operation when deciding
  3768. * if the MK_MESSAGE_SCB can be run.
  3769. */
  3770. MK_MESSAGE_SCSIID {
  3771. size 1
  3772. }
  3773. }
  3774. /************************* Hardware SCB Definition ****************************/
  3775. scb {
  3776. address 0x180
  3777. size 64
  3778. modes 0, 1, 2, 3
  3779. SCB_RESIDUAL_DATACNT {
  3780. size 4
  3781. alias SCB_CDB_STORE
  3782. alias SCB_HOST_CDB_PTR
  3783. dont_generate_debug_code
  3784. }
  3785. SCB_RESIDUAL_SGPTR {
  3786. size 4
  3787. field SG_ADDR_MASK 0xf8 /* In the last byte */
  3788. field SG_OVERRUN_RESID 0x02 /* In the first byte */
  3789. field SG_LIST_NULL 0x01 /* In the first byte */
  3790. dont_generate_debug_code
  3791. }
  3792. SCB_SCSI_STATUS {
  3793. size 1
  3794. alias SCB_HOST_CDB_LEN
  3795. dont_generate_debug_code
  3796. }
  3797. SCB_TARGET_PHASES {
  3798. size 1
  3799. dont_generate_debug_code
  3800. }
  3801. SCB_TARGET_DATA_DIR {
  3802. size 1
  3803. dont_generate_debug_code
  3804. }
  3805. SCB_TARGET_ITAG {
  3806. size 1
  3807. dont_generate_debug_code
  3808. }
  3809. SCB_SENSE_BUSADDR {
  3810. /*
  3811. * Only valid if CDB length is less than 13 bytes or
  3812. * we are using a CDB pointer. Otherwise contains
  3813. * the last 4 bytes of embedded cdb information.
  3814. */
  3815. size 4
  3816. alias SCB_NEXT_COMPLETE
  3817. dont_generate_debug_code
  3818. }
  3819. SCB_TAG {
  3820. alias SCB_FIFO_USE_COUNT
  3821. size 2
  3822. dont_generate_debug_code
  3823. }
  3824. SCB_CONTROL {
  3825. size 1
  3826. field TARGET_SCB 0x80
  3827. field DISCENB 0x40
  3828. field TAG_ENB 0x20
  3829. field MK_MESSAGE 0x10
  3830. field STATUS_RCVD 0x08
  3831. field DISCONNECTED 0x04
  3832. field SCB_TAG_TYPE 0x03
  3833. }
  3834. SCB_SCSIID {
  3835. size 1
  3836. field TID 0xF0
  3837. field OID 0x0F
  3838. }
  3839. SCB_LUN {
  3840. size 1
  3841. field LID 0xff
  3842. dont_generate_debug_code
  3843. }
  3844. SCB_TASK_ATTRIBUTE {
  3845. size 1
  3846. /*
  3847. * Overloaded field for non-packetized
  3848. * ignore wide residue message handling.
  3849. */
  3850. field SCB_XFERLEN_ODD 0x01
  3851. dont_generate_debug_code
  3852. }
  3853. SCB_CDB_LEN {
  3854. size 1
  3855. field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
  3856. dont_generate_debug_code
  3857. }
  3858. SCB_TASK_MANAGEMENT {
  3859. size 1
  3860. dont_generate_debug_code
  3861. }
  3862. SCB_DATAPTR {
  3863. size 8
  3864. dont_generate_debug_code
  3865. }
  3866. SCB_DATACNT {
  3867. /*
  3868. * The last byte is really the high address bits for
  3869. * the data address.
  3870. */
  3871. size 4
  3872. field SG_LAST_SEG 0x80 /* In the fourth byte */
  3873. field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
  3874. dont_generate_debug_code
  3875. }
  3876. SCB_SGPTR {
  3877. size 4
  3878. field SG_STATUS_VALID 0x04 /* In the first byte */
  3879. field SG_FULL_RESID 0x02 /* In the first byte */
  3880. field SG_LIST_NULL 0x01 /* In the first byte */
  3881. dont_generate_debug_code
  3882. }
  3883. SCB_BUSADDR {
  3884. size 4
  3885. dont_generate_debug_code
  3886. }
  3887. SCB_NEXT {
  3888. alias SCB_NEXT_SCB_BUSADDR
  3889. size 2
  3890. dont_generate_debug_code
  3891. }
  3892. SCB_NEXT2 {
  3893. size 2
  3894. dont_generate_debug_code
  3895. }
  3896. SCB_SPARE {
  3897. size 8
  3898. alias SCB_PKT_LUN
  3899. }
  3900. SCB_DISCONNECTED_LISTS {
  3901. size 8
  3902. dont_generate_debug_code
  3903. }
  3904. }
  3905. /*********************************** Constants ********************************/
  3906. const MK_MESSAGE_BIT_OFFSET 4
  3907. const TID_SHIFT 4
  3908. const TARGET_CMD_CMPLT 0xfe
  3909. const INVALID_ADDR 0x80
  3910. #define SCB_LIST_NULL 0xff
  3911. #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80
  3912. const CCSGADDR_MAX 0x80
  3913. const CCSCBADDR_MAX 0x80
  3914. const CCSGRAM_MAXSEGS 16
  3915. /* Selection Timeout Timer Constants */
  3916. const STIMESEL_SHIFT 3
  3917. const STIMESEL_MIN 0x18
  3918. const STIMESEL_BUG_ADJ 0x8
  3919. /* WDTR Message values */
  3920. const BUS_8_BIT 0x00
  3921. const BUS_16_BIT 0x01
  3922. const BUS_32_BIT 0x02
  3923. /* Offset maximums */
  3924. const MAX_OFFSET 0xfe
  3925. const MAX_OFFSET_PACED 0xfe
  3926. const MAX_OFFSET_PACED_BUG 0x7f
  3927. /*
  3928. * Some 160 devices incorrectly accept 0xfe as a
  3929. * sync offset, but will overrun this value. Limit
  3930. * to 0x7f for speed lower than U320 which will
  3931. * avoid the persistent sync offset overruns.
  3932. */
  3933. const MAX_OFFSET_NON_PACED 0x7f
  3934. const HOST_MSG 0xff
  3935. /*
  3936. * The size of our sense buffers.
  3937. * Sense buffer mapping can be handled in either of two ways.
  3938. * The first is to allocate a dmamap for each transaction.
  3939. * Depending on the architecture, dmamaps can be costly. The
  3940. * alternative is to statically map the buffers in much the same
  3941. * way we handle our scatter gather lists. The driver implements
  3942. * the later.
  3943. */
  3944. const AHD_SENSE_BUFSIZE 256
  3945. /* Target mode command processing constants */
  3946. const CMD_GROUP_CODE_SHIFT 0x05
  3947. const STATUS_BUSY 0x08
  3948. const STATUS_QUEUE_FULL 0x28
  3949. const STATUS_PKT_SENSE 0xFF
  3950. const TARGET_DATA_IN 1
  3951. const SCB_TRANSFER_SIZE_FULL_LUN 56
  3952. const SCB_TRANSFER_SIZE_1BYTE_LUN 48
  3953. /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
  3954. const PKT_OVERRUN_BUFSIZE 512
  3955. /*
  3956. * Timer parameters.
  3957. */
  3958. const AHD_TIMER_US_PER_TICK 25
  3959. const AHD_TIMER_MAX_TICKS 0xFFFF
  3960. const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
  3961. /*
  3962. * Downloaded (kernel inserted) constants
  3963. */
  3964. const SG_PREFETCH_CNT download
  3965. const SG_PREFETCH_CNT_LIMIT download
  3966. const SG_PREFETCH_ALIGN_MASK download
  3967. const SG_PREFETCH_ADDR_MASK download
  3968. const SG_SIZEOF download
  3969. const PKT_OVERRUN_BUFOFFSET download
  3970. const SCB_TRANSFER_SIZE download
  3971. const CACHELINE_MASK download
  3972. /*
  3973. * BIOS SCB offsets
  3974. */
  3975. const NVRAM_SCB_OFFSET 0x2C