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/drivers/net/wireless/tiwlan1251/common/src/TNETW_Driver/TNETWIF/BusTxn/whalHwAccess.c

https://bitbucket.org/cyanogenmod/cm-kernel
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Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /****************************************************************************
  2. **+-----------------------------------------------------------------------+**
  3. **| |**
  4. **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |**
  5. **| All rights reserved. |**
  6. **| |**
  7. **| Redistribution and use in source and binary forms, with or without |**
  8. **| modification, are permitted provided that the following conditions |**
  9. **| are met: |**
  10. **| |**
  11. **| * Redistributions of source code must retain the above copyright |**
  12. **| notice, this list of conditions and the following disclaimer. |**
  13. **| * Redistributions in binary form must reproduce the above copyright |**
  14. **| notice, this list of conditions and the following disclaimer in |**
  15. **| the documentation and/or other materials provided with the |**
  16. **| distribution. |**
  17. **| * Neither the name Texas Instruments nor the names of its |**
  18. **| contributors may be used to endorse or promote products derived |**
  19. **| from this software without specific prior written permission. |**
  20. **| |**
  21. **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |**
  22. **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |**
  23. **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |**
  24. **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |**
  25. **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |**
  26. **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |**
  27. **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |**
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  30. **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |**
  31. **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |**
  32. **| |**
  33. **+-----------------------------------------------------------------------+**
  34. ****************************************************************************/
  35. /****************************************************************************
  36. *
  37. * MODULE: hwAccess.c
  38. * PURPOSE: Support access to the wlan hardware registers and memory
  39. *
  40. * Direct Slave mode:
  41. * -----------------
  42. *
  43. * 1. 08 bit function
  44. * - access 16 bit (WA100 has no access to 8 bits)
  45. * - set/get the relevant byte according to the address (odd or even)
  46. * + ((char *)&DataShort)[Addr&0x1]
  47. * - no endian handle
  48. * 2. 16 bit function
  49. * - access 16 bit
  50. * - short endian handle
  51. * 3. 32 bit function
  52. * - access 32 bit
  53. * - long endian handle
  54. * 4. buffers copy to (stream of bytes)
  55. * - addresses must be even
  56. * - copy buffer as stream of 16 bits (in case of src/dst address ends with 0x2)
  57. * - handle case of more bytes to copy
  58. * * TempWord = (*shortDest & 0x00ff) | (*shortSrc & 0xff00);
  59. * - no endian handle
  60. * 5. registers
  61. * - access 32 bit
  62. * - long endian handle
  63. * - no use of wlan hardware capability to swap endian
  64. *
  65. * Indirect Slave mode:
  66. * -------------------
  67. *
  68. * 1. 08 bit function
  69. * - access 16 bit (WA100 has no access to 8 bits)
  70. * - set/get the relevant byte according to the address (odd or even)
  71. * + ((char *)&DataLong)[Addr&0x3]
  72. * - no endian handle
  73. * 2. 16 bit function
  74. * - access 32 bit (set addr reg , get data reg)
  75. * - set/get the relevant short according to the address (00 or 02)
  76. * + ((short *)&DataLong)[(Addr>>1)&0x1])
  77. * - short endian handle
  78. * 3. 32 bit function
  79. * - access 32 bit (set addr reg , get data reg)
  80. * - long endian handle
  81. * 4. buffers copy to (stream of bytes)
  82. * - addresses must be even
  83. * - handle case of dest(wlan hardware) address ends with 0x2 - read 32 from 0x0, set only high short
  84. * - now the dest(wlan hardware) address is long address
  85. * - use Auto Increment Mode
  86. * - copy buffer as stream of 16 bits (in case of source address ends with 0x2)
  87. * - handle case of more bytes to copy
  88. * * i=0..Len&3 ==> ((char *)&DataLong)[i] = ((char *)shortSrc)[i]
  89. * - no endian handle
  90. * 5. buffers copy from (stream of bytes)
  91. * - addresses must be even
  92. * - handle case of source(wlan hardware) address ends with 0x2 - read 32 from 0x0, set only high short
  93. * - now the source(wlan hardware) address is long address
  94. * - use Auto Increment Mode
  95. * - copy buffer as stream of 16 bits (in case of dest address ends with 0x2)
  96. * - handle case of more bytes to copy
  97. * * i=0..Len&3 ==> ((char *)shortDest)[i] = ((char *)&DataLong)[i]
  98. * - no endian handle
  99. * 6. registers
  100. * - access 32 bit
  101. * - long endian handle
  102. * - no use of wlan hardware capability to swap endian
  103. *
  104. ****************************************************************************/
  105. #include "osTIType.h"
  106. #include "osApi.h"
  107. #include "whalCommon.h"
  108. #include "whalHwDefs.h"
  109. #ifdef HW_ACCESS_SDIO
  110. #ifndef _WINDOWS /*Linux, Symbian, RVCT */
  111. #include "mmc_omap_api.h"
  112. #include "mmc_tnetw1150_api.h"
  113. #else /* ifdef _WINDOWS */
  114. #endif /* ifdef _WINDOWS */
  115. #elif defined(HW_ACCESS_WSPI)
  116. #include "wspi.h"
  117. #endif
  118. #include "TNETWIF.h"
  119. #include "whalHwAccess.h"
  120. /* #define __HWACCESS_DEBUG__ */
  121. /*
  122. * Define this flag to support SDIO asynchronous mode
  123. */
  124. #undef HW_ACCESS_SDIO_ASYNC_SUPPORT
  125. /************************************************************************
  126. * Types
  127. ************************************************************************/
  128. typedef struct _HWAccess_CB_T
  129. {
  130. HwAccess_callback_t CBFunc;
  131. void* CBArg;
  132. } HWAccess_CB_T;
  133. typedef void (*HwAccessErrorHandle)(TI_HANDLE theObjectHandle,char* Report , UINT32 strLen);
  134. typedef struct _partition_t
  135. {
  136. UINT32 size;
  137. UINT32 start;
  138. } partition_t;
  139. /* HwAccess context */
  140. typedef struct _HwAccess_T_new
  141. {
  142. void *hProtect;
  143. TI_HANDLE hOs;
  144. TI_HANDLE hReport;
  145. #if (defined(HW_ACCESS_SDIO)|defined(HW_ACCESS_WSPI))
  146. TI_HANDLE hDriver;
  147. UINT32 MemRegionAddr;
  148. UINT32 RegisterRegionAddr;
  149. UINT32 workingPartUpperLimit;
  150. UINT32 registerPartUpperLimit;
  151. #else /* HW_ACCESS_CARDBUS */
  152. UINT32 RegBaseAddr;
  153. UINT32 MemBaseAddr;
  154. #endif
  155. HWAccess_CB_T CB;
  156. UINT8 AsyncMode;
  157. UINT32 uBusError;
  158. HwAccessErrorHandle hwAccesserror_Cb;
  159. TI_HANDLE hBackReference;
  160. PADDING (partition_t partition [2])
  161. } HwAccess_T_new;
  162. /************************************************************************
  163. * Defines
  164. ************************************************************************/
  165. #ifdef HW_ACCESS_WSPI
  166. /*
  167. * Converts status from WSPI into TI_STATUS
  168. */
  169. #define WSPI2TNETWIF(pHwAccess,status,addr) \
  170. switch(status) { \
  171. case WSPI_TXN_PENDING: status = TNETWIF_PENDING; break; \
  172. case WSPI_TXN_COMPLETE: status = TNETWIF_COMPLETE; break; \
  173. default: \
  174. WLAN_REPORT_ERROR (pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG, \
  175. ("whal_hwAccess: Error in read/write async, addr=0x%08x status=%d\n", \
  176. addr, status)); \
  177. status = TNETWIF_ERROR; break; \
  178. }
  179. /*
  180. * Indicate the index position at which we should check if the HW is up -
  181. * i.e. (buf[HW_ACCESS_WSPI_FIXED_BUSY_LEN] & 0x1 == TRUE)
  182. */
  183. #ifdef TNETW1251
  184. #define HW_ACCESS_WSPI_FIXED_BUSY_LEN ((TNETWIF_READ_OFFSET_BYTES - 4 ) / sizeof(UINT32))
  185. #else
  186. #define HW_ACCESS_WSPI_FIXED_BUSY_LEN 0
  187. #endif
  188. #endif /* HW_ACCESS_WSPI */
  189. #define HW_ACCESS_WSPI_INIT_CMD_MASK 0
  190. #define HW_ACCESS_WSPI_ALIGNED_SIZE 4
  191. #define HW_ACCESS_NUM_OF_BIT_IN_BYTE 8
  192. #define HW_ACCESS_REGISTER_SIZE 4
  193. /* ELP CTRL register */
  194. #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
  195. #define HW_ACCESS_1_BYTE_REMINDE_MASK 0x000000FF
  196. #define HW_ACCESS_2_BYTE_REMINDE_MASK 0x0000FFFF
  197. #define HW_ACCESS_3_BYTE_REMINDE_MASK 0x00FFFFFF
  198. /* translation registers */
  199. #define HW_ACCESS_PART0_SIZE_ADDR 0x1FFC0
  200. #define HW_ACCESS_PART0_START_ADDR 0x1FFC4
  201. #define HW_ACCESS_PART1_SIZE_ADDR 0x1FFC8
  202. #define HW_ACCESS_PART1_START_ADDR 0x1FFCC
  203. /************************************************************************
  204. * Macros
  205. ************************************************************************/
  206. #define EXTRACT_BYTE_FROM_WORD(DataShort, Addr) (((char *)&DataShort)[((int)Addr)&0x1])
  207. #define EXTRACT_BYTE_FROM_LONG(DataLong, Addr) (((char *)&DataLong )[((int)Addr)&0x3])
  208. #define EXTRACT_WORD_FROM_LONG(DataLong, Addr) (((short *)&DataLong)[(((int)Addr>>1))&0x1])
  209. #define EXTRACT_BYTE_LONG(DataLong, i) (((char *)&DataLong)[i])
  210. #define HW_MEM_SHORT(pHwAccess, Addr) (*(volatile UINT16 *)(pHwAccess->MemBaseAddr + (UINT32)(Addr)))
  211. #define HW_MEM_LONG(pHwAccess, Addr) (*(volatile UINT32 *)(pHwAccess->MemBaseAddr + (UINT32)(Addr)))
  212. #define TRANSLATE_ADDRESS_MEM(addr) ((addr) - pHwAccess->MemRegionAddr)
  213. #define TRANSLATE_ADDRESS_REG(addr) ((addr) + pHwAccess->RegisterRegionAddr)
  214. #if 1 /* 0 */
  215. #if (defined(HW_ACCESS_SDIO)|defined(HW_ACCESS_WSPI)) /* 1 */
  216. void HW_REG_LONG_WRITE(HwAccess_T_new *pHwAccess, UINT32 RegAddr, UINT32 BitVal);
  217. void HW_REG_LONG_READ(HwAccess_T_new *pHwAccess, UINT32 RegAddr, UINT32 *Val);
  218. #else /* 1 */
  219. #define HW_REG_SHORT_WRITE(pHwAccess, Addr, Data) ((*(volatile UINT16 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) = (UINT16)(Data))
  220. #define HW_REG_SHORT_READ(pHwAccess, Addr, Data) ((*(Data)) = (*(volatile UINT16 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) )
  221. #ifdef NOT_SUPPORT_32_BIT_ACCESS_COMMAND /* for example: iPAQ model 38xx */ /* 2 */
  222. #define HW_REG_LONG_WRITE(pHwAccess, Addr, Data) HW_REG_SHORT_WRITE(pHwAccess, Addr, Data); HW_REG_SHORT_WRITE(pHwAccess, Addr+2, ((UINT16)(Data>>16)))
  223. #define HW_REG_LONG_READ(pHwAccess, Addr, pData) HW_REG_SHORT_READ(pHwAccess, Addr, pData); HW_REG_SHORT_READ(pHwAccess, Addr+2, ((UINT16 *)pData+1))
  224. #else /* 2 */
  225. #define HW_REG_LONG_WRITE(pHwAccess, Addr, Data) ((*(volatile UINT32 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) = (UINT32)(Data))
  226. #define HW_REG_LONG_READ(pHwAccess, Addr, Data) ((*(Data)) = (*(volatile UINT32 *)(pHwAccess->RegBaseAddr + (UINT32)(Addr))) )
  227. #endif /* 2 */
  228. #endif /* 1 */
  229. #else /* 0 */
  230. #endif /* 0 */
  231. /************************************************************************
  232. * Functions
  233. ************************************************************************/
  234. #if !defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_WSPI)
  235. static void whal_hwAccess_DirectCopy_new(HwAccess_T_new *pHwAccess, UINT8* Dest, UINT8* Src, UINT32 Len);
  236. #endif
  237. #ifdef HW_ACCESS_SDIO
  238. static void sdio_transaction_notify_read(struct SDIO_Request *req, int status);
  239. static void sdio_transaction_notify_write(struct SDIO_Request *req, int status);
  240. static void sdio_transaction_error(struct SDIO_Request *req, int stat);
  241. #ifdef CONFIG_ASYNC_API
  242. static void sdio_async_transaction_notify(struct SDIO_Request *req, int status);
  243. static void sdio_async_transaction_error(struct SDIO_Request *req, int status);
  244. #endif
  245. #endif
  246. /*
  247. ** Read/Write interface
  248. **----------------------------
  249. **
  250. ** the memory space shell be divided to 2 Partions: Memory, and Registers.
  251. ** 1. The memory Region will be set at init to point to the FW Ram,
  252. ** and after FW init complete, the Memory Region will be set to point the Packet Ram.
  253. ** 2. Registry Region.
  254. **
  255. **
  256. */
  257. /************************************************************************
  258. * new API
  259. ************************************************************************/
  260. /****************************************************************************
  261. * whal_hwAccess_Create
  262. ****************************************************************************
  263. * DESCRIPTION: create the HwAccess module. allocate the module context and create the sublayers
  264. *
  265. * INPUTS: hOs - handle to the OS module
  266. *
  267. * OUTPUT: TI_HANDLE - the handle to the context that was created
  268. *
  269. * RETURNS: NULL = failure.
  270. * otherwise = success
  271. ****************************************************************************/
  272. TI_HANDLE whal_hwAccess_Create(TI_HANDLE hOs)
  273. {
  274. HwAccess_T_new *pHwAccess;
  275. int status = OK;
  276. #ifdef HW_ACCESS_SDIO
  277. SDIO_ConfigParams configParams;
  278. #endif
  279. pHwAccess = os_memoryAlloc(hOs, sizeof(HwAccess_T_new));
  280. if (pHwAccess == NULL)
  281. return NULL;
  282. os_memoryZero(hOs, pHwAccess, sizeof(HwAccess_T_new));
  283. pHwAccess->hOs = hOs;
  284. pHwAccess->hProtect = os_protectCreate(pHwAccess->hOs);
  285. if (pHwAccess->hProtect == NULL)
  286. {
  287. whal_hwAccess_Destroy(pHwAccess);
  288. return NULL;
  289. }
  290. #ifdef HW_ACCESS_SDIO
  291. pHwAccess->AsyncMode = FALSE;
  292. os_memoryZero(hOs, &configParams, sizeof(SDIO_ConfigParams));
  293. configParams.fnotify_read = sdio_transaction_notify_read;
  294. configParams.fnotify_write = sdio_transaction_notify_write;
  295. configParams.ferror = sdio_transaction_error;
  296. configParams.fconfig_peripheral = SDIO_TNETWConfig;
  297. configParams.fconvert = NULL;
  298. configParams.owner = pHwAccess;
  299. status = SDIO_Init(&configParams, &pHwAccess->hDriver);
  300. #elif defined(HW_ACCESS_WSPI)
  301. pHwAccess->AsyncMode = TRUE;
  302. pHwAccess->hDriver = WSPI_Open (pHwAccess->hOs);
  303. status = pHwAccess->hDriver == NULL;
  304. #else
  305. pHwAccess->AsyncMode = FALSE;
  306. #endif
  307. if (status != 0)
  308. {
  309. if (pHwAccess->hProtect)
  310. os_protectDestroy(pHwAccess->hOs, pHwAccess->hProtect);
  311. os_memoryFree(pHwAccess->hOs, pHwAccess, sizeof(HwAccess_T_new));
  312. return NULL;
  313. }
  314. return pHwAccess;
  315. }
  316. /****************************************************************************
  317. * whal_hwAccess_Destroy
  318. ****************************************************************************
  319. * DESCRIPTION: destroy the module. deallocate the cmodule context.
  320. *
  321. * INPUTS: hHwAccess - handle to the module context
  322. *
  323. * OUTPUT: none.
  324. *
  325. * RETURNS: one of the error codes (0 => OK)
  326. ****************************************************************************/
  327. int whal_hwAccess_Destroy(TI_HANDLE hHwAccess)
  328. {
  329. HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
  330. if (pHwAccess)
  331. {
  332. #ifdef HW_ACCESS_SDIO
  333. SDIO_Stop(pHwAccess->hDriver, 0);
  334. SDIO_Shutdown(pHwAccess->hDriver);
  335. #elif defined(HW_ACCESS_WSPI)
  336. WSPI_Close(pHwAccess->hDriver);
  337. #endif
  338. if (pHwAccess->hProtect)
  339. os_protectDestroy(pHwAccess->hOs, pHwAccess->hProtect);
  340. os_memoryFree(pHwAccess->hOs, pHwAccess, sizeof(HwAccess_T_new));
  341. }
  342. return OK;
  343. }
  344. /****************************************************************************
  345. * whal_hwAccess_Config
  346. ****************************************************************************
  347. * DESCRIPTION: config the module.
  348. *
  349. * INPUTS: hHwAccess - handle to the module context
  350. * hReport - handle to report module context that is used when we output debug messages
  351. *
  352. * OUTPUT: none.
  353. *
  354. * RETURNS: one of the error codes (0 => OK)
  355. ****************************************************************************/
  356. int whal_hwAccess_Config(TI_HANDLE hHwAccess, TI_HANDLE hReport,UINT32 RegBaseAddr, UINT32 MemBaseAddr, HwAccess_callback_t CBFunc,void* CBArg)
  357. {
  358. HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
  359. int status = OK;
  360. #ifdef HW_ACCESS_WSPI
  361. WSPIConfig_t wspi_config;
  362. #endif
  363. pHwAccess->hReport = hReport;
  364. #ifdef GWSI_SPI_TEST
  365. /* For GWSI_API_TEST this parameter should be maximum allowed because we don't use setPartition */
  366. pHwAccess->workingPartUpperLimit = 0xFFFFFFFF;
  367. #endif /* GWSI_API_TEST */
  368. /*
  369. Wait 200 usec for memory repair process to finish and device is ready.
  370. */
  371. os_StalluSec(pHwAccess->hOs, 200);
  372. pHwAccess->CB.CBFunc = CBFunc;
  373. pHwAccess->CB.CBArg = CBArg;
  374. #ifdef HW_ACCESS_SDIO
  375. pHwAccess->RegisterRegionAddr = HW_ACCESS_DOWN_PART0_SIZE;
  376. pHwAccess->MemRegionAddr = HW_ACCESS_DOWN_PART0_ADDR;
  377. pHwAccess->uBusError = 0;
  378. status = SDIO_Start (pHwAccess->hDriver);
  379. status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
  380. #elif defined(HW_ACCESS_WSPI)
  381. wspi_config.isFixedAddress = FALSE;
  382. wspi_config.fixedBusyLength = HW_ACCESS_WSPI_FIXED_BUSY_LEN;
  383. wspi_config.mask = HW_ACCESS_WSPI_INIT_CMD_MASK;
  384. status = WSPI_Configure (pHwAccess->hDriver,
  385. pHwAccess->hReport,
  386. &wspi_config,
  387. (WSPI_CB_T*)&pHwAccess->CB);
  388. WSPI_SetErrLog(pHwAccess->hDriver, TNETWIF_printErrorLog);
  389. WSPI2TNETWIF (pHwAccess, status, 0x0);
  390. #else /* HW_ACCESS_CARDBUS */
  391. pHwAccess->RegBaseAddr = RegBaseAddr;
  392. pHwAccess->MemBaseAddr = MemBaseAddr;
  393. #endif
  394. return status;
  395. }
  396. /****************************************************************************
  397. * whal_hwAccess_ReConfig()
  398. ****************************************************************************
  399. * DESCRIPTION:
  400. *
  401. * INPUTS: None
  402. *
  403. * OUTPUT: None
  404. *
  405. * RETURNS:
  406. ****************************************************************************/
  407. int whal_hwAccess_ReConfig(TI_HANDLE hHwAccess)
  408. {
  409. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  410. #ifdef _WINDOWS
  411. #else /* _WINDOWS */
  412. /* unbclock the access to the bus */
  413. pHwAccess->uBusError = 0;
  414. #ifdef HW_ACCESS_SDIO
  415. SDIO_Stop (pHwAccess->hDriver, 0);
  416. SDIO_Start (pHwAccess->hDriver);
  417. #elif defined(HW_ACCESS_WSPI)
  418. /* TODO*/
  419. #endif
  420. #endif /* _WINDOWS */
  421. return OK;
  422. }
  423. #ifdef USE_SYNC_API
  424. /****************************************************************************
  425. * whal_hwAccess_WriteELP
  426. ****************************************************************************
  427. * DESCRIPTION: write data synchronously to the TNET ELP register (1byte)
  428. *
  429. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  430. * data - UINT8 - the data to write
  431. *
  432. * OUTPUT: none
  433. *
  434. * RETURNS: one of the error codes (0 => OK)
  435. ****************************************************************************/
  436. int whal_hwAccess_WriteELP (TI_HANDLE hHwAccess, UINT32 data)
  437. {
  438. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  439. int status = OK;
  440. os_profile (pHwAccess->hOs, 2, 0);
  441. #ifdef HW_ACCESS_SDIO
  442. status = SDIO_TNETW_Set_ELP_Reg(pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, data);
  443. #elif defined(HW_ACCESS_WSPI)
  444. status = WSPI_WriteSync (pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, (UINT8*)&data, HW_ACCESS_REGISTER_SIZE);
  445. #endif
  446. os_profile (pHwAccess->hOs, 3, 0);
  447. if (status != OK)
  448. {
  449. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  450. ("whal_hwAccess_WriteReg_ELP: Error in ELP reg write status=%d\n",
  451. status));
  452. return NOK;
  453. }
  454. return OK;
  455. }
  456. #endif /* USE_SYNC_API */
  457. /****************************************************************************
  458. * whal_hwAccess_WriteELPAsync
  459. ****************************************************************************
  460. * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
  461. * the length of data is always 4bytes cause this is the size of the TNET registers
  462. * the function is passed a call-back function that will be called after the read request ends.
  463. *
  464. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  465. * addr - UINT32 - the address offset inside the TNET
  466. * data - UINT8* - a pointer to the buffer that holds the data to write
  467. * bMore - indicate whether more txn on the bus are about to happen (FALSE only when setting
  468. * the HW to sleep).
  469. *
  470. * OUTPUT: none
  471. *
  472. * RETURNS: one of the error codes (0 => OK)
  473. ****************************************************************************/
  474. int whal_hwAccess_WriteELPAsync (TI_HANDLE hHwAccess, UINT32 data, BOOL bCb, BOOL bMore)
  475. {
  476. #if defined(HW_ACCESS_SDIO)
  477. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  478. #error "SDIO asynchronous mode is not supported"
  479. /* Not implemented yet */
  480. return OK;
  481. #else
  482. /* Just call to synchronous API */
  483. return (whal_hwAccess_WriteELP (hHwAccess, data) == OK) ?
  484. TNETWIF_COMPLETE :
  485. TNETWIF_ERROR;
  486. #endif
  487. #else /* HW_ACCESS_WSPI */
  488. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  489. WSPI_CB_T Cb = { NULL, NULL }, *pCb;
  490. int status;
  491. pCb = (bCb) ? ((WSPI_CB_T*)&pHwAccess->CB) : &Cb;
  492. os_profile (pHwAccess->hOs, 2, 0);
  493. /* since we are writing a register - no extra space is needed */
  494. status = WSPI_WriteAsync (pHwAccess->hDriver,
  495. HW_ACCESS_ELP_CTRL_REG_ADDR,
  496. (UINT8*)&data,
  497. HW_ACCESS_REGISTER_SIZE,
  498. pCb,
  499. bMore,
  500. FALSE);
  501. os_profile (pHwAccess->hOs, 3, 0);
  502. WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_ELP_CTRL_REG_ADDR);
  503. return status;
  504. #endif
  505. }
  506. /****************************************************************************
  507. * whal_hwAccess_ReadELPAsync
  508. ****************************************************************************
  509. * DESCRIPTION: Read the ELP register
  510. *
  511. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  512. * addr - UINT32 - the address offset inside the TNET
  513. * data - UINT8* - a pointer to the buffer to read data into
  514. * bMore - indicate whether more txn on the bus are about to happen (FALSE only when setting
  515. * the HW to sleep).
  516. *
  517. * OUTPUT: none
  518. *
  519. * RETURNS: one of the error codes (0 => OK)
  520. ****************************************************************************/
  521. int whal_hwAccess_ReadELPAsync (TI_HANDLE hHwAccess, UINT8 *data, BOOL bCb, BOOL bMore)
  522. {
  523. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  524. int status;
  525. #ifdef HW_ACCESS_SDIO
  526. #ifndef _WINDOWS
  527. status = SDIO_TNETW_Get_ELP_Reg(pHwAccess->hDriver, HW_ACCESS_ELP_CTRL_REG_ADDR, (UINT32*)data);
  528. #else
  529. #endif
  530. if (status != OK)
  531. {
  532. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  533. ("whal_hwAccess_ReadELPAsync: Error in ELP reg raed status=%d\n",
  534. status));
  535. return TNETWIF_ERROR;
  536. }
  537. return TNETWIF_COMPLETE;
  538. #else /* HW_ACCESS_WSPI */
  539. os_profile (pHwAccess->hOs, 2, 0);
  540. /* In registers we don't save place */
  541. status = WSPI_ReadAsync (pHwAccess->hDriver,
  542. HW_ACCESS_ELP_CTRL_REG_ADDR,
  543. (UINT8*)data,
  544. HW_ACCESS_REGISTER_SIZE,
  545. (WSPI_CB_T*)&pHwAccess->CB,
  546. TRUE,
  547. FALSE);
  548. os_profile (pHwAccess->hOs, 3, 0);
  549. WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_ELP_CTRL_REG_ADDR);
  550. return status;
  551. #endif
  552. }
  553. #ifdef USE_SYNC_API
  554. /****************************************************************************
  555. * whal_hwAccess_ReadMem_Align
  556. ****************************************************************************
  557. * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
  558. * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
  559. *
  560. * INPUTS: hHwAccess - the handle of HwAccess module
  561. * addr - UINT32 - the address offset inside the TNET
  562. * len - int - the length of the data to read
  563. *
  564. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  565. *
  566. * RETURNS: one of the error codes (0 => OK)
  567. ****************************************************************************/
  568. int whal_hwAccess_ReadMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  569. {
  570. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  571. int status = OK;
  572. #ifdef HW_ACCESS_SDIO
  573. struct SDIO_Request request;
  574. #endif
  575. /* round up the length so it will be multiple of 4bytes */
  576. if(len&0x3)
  577. len = (len&0xFFFFFFFC)+4;
  578. #ifdef HW_ACCESS_SDIO
  579. /* check address */
  580. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  581. {
  582. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  583. ("whal_hwAccess_ReadMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  584. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  585. return ERROR_HW_ACCEESS_ADDR;
  586. }
  587. request.buffer = data; /* Pointer to the data buffer aligned address. */
  588. request.buffer_len = len; /* Data buffer length in bytes */
  589. request.status = SDIO_Request_None;
  590. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  591. request.acquire_window = 0; /*Time out value is not set*/
  592. request.block_len = 0; /*Block length. Assigned by driver*/
  593. request.physical_buffer = 0; /*Physical address of data buffer is not set*/
  594. request.owner = (SDIO_Owner) pHwAccess;
  595. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  596. request.access_flag = 1;
  597. os_profile (pHwAccess->hOs, 2, 0);
  598. status = SDIO_SyncRead(pHwAccess->hDriver, &request);
  599. os_profile (pHwAccess->hOs, 3, 0);
  600. #elif defined(HW_ACCESS_WSPI)
  601. /* check address */
  602. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  603. {
  604. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  605. ("whal_hwAccess_ReadMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  606. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  607. return ERROR_HW_ACCEESS_ADDR;
  608. }
  609. os_profile (pHwAccess->hOs, 2, 0);
  610. status = WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,len);
  611. os_profile (pHwAccess->hOs, 3, 0);
  612. #else
  613. whal_hwAccess_DirectCopy_new(pHwAccess, data, (UINT8*)addr, len);
  614. #endif
  615. if (status != OK)
  616. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  617. ("whal_hwAccess_ReadMem_Align: Error in read, addr=0x%08x status=%d\n",
  618. addr, status));
  619. #ifdef HW_ACCESS_SDIO
  620. if (pHwAccess->uBusError)
  621. {
  622. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  623. ("whal_hwAccess_ReadMem_Align: SDIO Error status=%d\n",
  624. request.status));
  625. if (pHwAccess->hwAccesserror_Cb)
  626. {
  627. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  628. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
  629. }
  630. else
  631. pHwAccess->uBusError = 0;
  632. }
  633. #endif
  634. return status;
  635. }
  636. /****************************************************************************
  637. * whal_hwAccess_WriteMem_Align
  638. ****************************************************************************
  639. * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
  640. * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
  641. *
  642. * INPUTS: hHwAccess - the handle of HwAccess module
  643. * addr - UINT32 - the address offset inside the TNET
  644. * data - UINT8* - a pointer to the buffer that holds the data to write
  645. * len - int - the length of the data to read
  646. *
  647. * OUTPUT: none
  648. *
  649. * RETURNS: one of the error codes (0 => OK)
  650. ****************************************************************************/
  651. int whal_hwAccess_WriteMem_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  652. {
  653. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  654. int status = OK;
  655. #ifdef HW_ACCESS_SDIO
  656. struct SDIO_Request request;
  657. #endif
  658. /* round the length so it will be multiple of 4bytes */
  659. if(len&0x3)
  660. len = (len&0xFFFFFFFC)+4;
  661. #ifdef HW_ACCESS_SDIO
  662. /* check address */
  663. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  664. {
  665. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  666. ("whal_hwAccess_WriteMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  667. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  668. return ERROR_HW_ACCEESS_ADDR;
  669. }
  670. request.buffer = data; /* Pointer to the data buffer aligned address. */
  671. request.buffer_len = len; /* Data buffer length in bytes */
  672. request.status = SDIO_Request_None;
  673. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  674. request.acquire_window = 0; /*Time out value is not set*/
  675. request.block_len = 0; /*Block length. Assigned by driver*/
  676. request.physical_buffer = 0; /*Physical address of data buffer is not set*/
  677. request.owner = (SDIO_Owner) pHwAccess;
  678. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  679. request.access_flag = 0;
  680. os_profile (pHwAccess->hOs, 2, 0);
  681. status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
  682. os_profile (pHwAccess->hOs, 3, 0);
  683. #elif defined(HW_ACCESS_WSPI)
  684. /* check address */
  685. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  686. {
  687. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  688. ("whal_hwAccess_WriteMem_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  689. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  690. return ERROR_HW_ACCEESS_ADDR;
  691. }
  692. os_profile (pHwAccess->hOs, 2, 0);
  693. status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,len);
  694. os_profile (pHwAccess->hOs, 3, 0);
  695. #else
  696. whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)addr, data, len);
  697. #endif
  698. if (status != OK)
  699. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  700. ("whal_hwAccess_WriteMem_Align: Error in write, addr=0x%08x status=%d\n",
  701. addr, status));
  702. #ifdef HW_ACCESS_SDIO
  703. if (pHwAccess->uBusError)
  704. {
  705. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  706. ("whal_hwAccess_WriteMem_Align: SDIO Error in write status=%d\n",
  707. request.status));
  708. if (pHwAccess->hwAccesserror_Cb)
  709. {
  710. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  711. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
  712. }
  713. else
  714. pHwAccess->uBusError = 0;
  715. }
  716. #endif
  717. return status;
  718. }
  719. #endif /* USE_SYNC_API */
  720. /****************************************************************************
  721. * whal_hwAccess_ReadMemAsync_Align
  722. ****************************************************************************
  723. * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
  724. * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
  725. * the function is passed a call-back function that will be called after the read request ends.
  726. *
  727. * INPUTS: hHwAccess - the handle of HwAccess module
  728. * addr - UINT32 - the address offset inside the TNET
  729. * len - int - the length of the data to read
  730. * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
  731. *
  732. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  733. *
  734. * RETURNS: one of the error codes (0 => OK)
  735. ****************************************************************************/
  736. int whal_hwAccess_ReadMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  737. {
  738. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  739. /* Round the length so it will be multiple of 4bytes */
  740. if ((len & 0x3) != 0)
  741. len = (len & ~3) + 4;
  742. /* Check address */
  743. if (addr + len > pHwAccess->workingPartUpperLimit || addr < pHwAccess->MemRegionAddr)
  744. {
  745. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  746. ("whal_hwAccess_ReadMemAsync_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  747. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  748. return ERROR_HW_ACCEESS_ADDR;
  749. }
  750. #if defined(HW_ACCESS_SDIO)
  751. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  752. {
  753. struct SDIO_Request request;
  754. int status = OK;
  755. request.buffer = data; /* Pointer to the data buffer aligned address. */
  756. request.buffer_len = len; /* Data buffer length in bytes */
  757. request.status = SDIO_Request_None;
  758. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  759. request.acquire_window = 0; /*Time out value is not set*/
  760. request.block_len = 0; /*Block length. Assigned by driver*/
  761. request.physical_buffer = 0; /*Physical address of data buffer is not set*/
  762. request.owner = (SDIO_Owner) pHwAccess;
  763. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  764. request.access_flag = 1;
  765. request.fnotify = sdio_async_transaction_notify; /* completion notification */
  766. request.ferror = sdio_async_transaction_error; /* error notification */
  767. os_profile (pHwAccess->hOs, 2, 0);
  768. status = SDIO_AsyncRead (pHwAccess->hDriver, &request);
  769. os_profile (pHwAccess->hOs, 3, 0);
  770. if (status != OK)
  771. {
  772. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  773. ("whal_hwAccess_ReadMemAsync_Align: Error in read async, addr=0x%08x status=%d\n",
  774. addr, status));
  775. return TNETWIF_ERROR;
  776. }
  777. if (pHwAccess->uBusError)
  778. {
  779. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  780. ("whal_hwAccess_ReadMemAsync_Align: SDIO Error status=%d\n",
  781. request.status));
  782. if (pHwAccess->hwAccesserror_Cb)
  783. {
  784. UINT16 failure_reason = HEALTH_REPORT_BUS_ERROR;
  785. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
  786. }
  787. else
  788. pHwAccess->uBusError = 0;
  789. }
  790. return TNETWIF_COMPLETE;
  791. }
  792. #else
  793. return TNETWIF_COMPLETE;
  794. #endif
  795. #else /*HW_ACCESS_WSPI*/
  796. {
  797. int status;
  798. os_profile (pHwAccess->hOs, 2, 0);
  799. status = WSPI_ReadAsync (pHwAccess->hDriver,
  800. TRANSLATE_ADDRESS_MEM(addr),
  801. data,
  802. len,
  803. (WSPI_CB_T*)&pHwAccess->CB,
  804. TRUE,
  805. 0);
  806. os_profile (pHwAccess->hOs, 3, 0);
  807. WSPI2TNETWIF (pHwAccess, status, addr);
  808. return status;
  809. }
  810. #endif
  811. }
  812. /****************************************************************************
  813. * whal_hwAccess_WriteAsync_Align
  814. ****************************************************************************
  815. * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
  816. * the length of data specified is rounded up so the length will be multiple of 4 (bytes)
  817. * the function is passed a call-back function that will be called after the read request ends.
  818. *
  819. * INPUTS: pHwAccess - HwAccess_T* - the HwAccess context
  820. * addr - UINT32 - the address offset inside the TNET
  821. * data - UINT8* - a pointer to the buffer that holds the data to write
  822. * Len - int - the length of the data to read
  823. * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
  824. *
  825. * OUTPUT: none
  826. *
  827. * RETURNS: one of the error codes (0 => OK)
  828. ****************************************************************************/
  829. int whal_hwAccess_WriteMemAsync_Align(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  830. {
  831. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  832. /* Round the length so it will be multiple of 4bytes */
  833. if ((len & 0x3) != 0)
  834. len = (len & ~3) + 4;
  835. /* Check address */
  836. if (addr + len > pHwAccess->workingPartUpperLimit || addr < pHwAccess->MemRegionAddr)
  837. {
  838. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  839. ("whal_hwAccess_WriteMemAsync_Align: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  840. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  841. return ERROR_HW_ACCEESS_ADDR;
  842. }
  843. #if defined(HW_ACCESS_SDIO)
  844. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  845. {
  846. struct SDIO_Request request;
  847. int status = OK;
  848. request.buffer = data; /*Pointer to the data buffer aligned address*/
  849. request.buffer_len = len; /*Data buffer length in bytes*/
  850. request.status = SDIO_Request_None;
  851. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  852. request.acquire_window = 0; /* Time out value is not set */
  853. request.block_len = 0; /* Block length. Assigned by driver */
  854. request.physical_buffer = 0; /* Physical address of data buffer is not set */
  855. request.owner = (SDIO_Owner) pHwAccess;
  856. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  857. request.access_flag = 0;
  858. request.fnotify = sdio_async_transaction_notify; /* completion notification */
  859. request.ferror = sdio_async_transaction_error; /* error notification */
  860. os_profile (pHwAccess->hOs, 2, 0);
  861. status = SDIO_AsyncWrite (pHwAccess->hDriver, &request);
  862. os_profile (pHwAccess->hOs, 3, 0);
  863. if (status != OK)
  864. {
  865. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  866. ("whal_hwAccess_WriteMemAsync_Align: Error in write async, addr=0x%08x status=%d\n",
  867. addr, status));
  868. return TNETWIF_ERROR;
  869. }
  870. return TNETWIF_COMPLETE;
  871. }
  872. #else
  873. return TNETWIF_COMPLETE;
  874. #endif
  875. #else /*HW_ACCESS_WSPI*/
  876. {
  877. int status;
  878. os_profile (pHwAccess->hOs, 2, 0);
  879. status = WSPI_WriteAsync (pHwAccess->hDriver,
  880. TRANSLATE_ADDRESS_MEM(addr),
  881. data,
  882. len,
  883. (WSPI_CB_T*)&pHwAccess->CB,
  884. TRUE,
  885. FALSE);
  886. os_profile (pHwAccess->hOs, 3, 0);
  887. WSPI2TNETWIF (pHwAccess, status, addr);
  888. return status;
  889. }
  890. #endif
  891. }
  892. #ifdef USE_SYNC_API
  893. /****************************************************************************
  894. * whal_hwAccess_ReadMem
  895. ****************************************************************************
  896. * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
  897. * the length of data is checked and the remnant (length%4) is completed with read-modify
  898. *
  899. * INPUTS: pHwAccess - HwAccess_T* - the HwAccess context
  900. * AddrOffset - UINT32 - the address offset inside the TNET
  901. * Len - int - the length of the data to read
  902. *
  903. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  904. *
  905. * RETURNS: one of the error codes (0 => OK)
  906. ****************************************************************************/
  907. int whal_hwAccess_ReadMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  908. {
  909. int status = OK;
  910. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  911. #ifdef HW_ACCESS_SDIO
  912. struct SDIO_Request request;
  913. #elif defined(HW_ACCESS_WSPI)
  914. int reminder = len%HW_ACCESS_WSPI_ALIGNED_SIZE;
  915. int tempLen = len - reminder;
  916. UINT32 mask = 0;
  917. status = whal_hwAccess_ReadMemAsync(hHwAccess, addr, data, len);
  918. if (status == TNETWIF_COMPLETE)
  919. {
  920. status = OK;
  921. }
  922. return status;
  923. #endif
  924. /* access is blocked */
  925. if (pHwAccess->uBusError)
  926. {
  927. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
  928. ("Bus is blocked \n"));
  929. return ERROR_HW_ACCEESS_ADDR;
  930. }
  931. #ifdef __HWACCESS_DEBUG__
  932. /* check address alignment */
  933. if(addr & 0x3)
  934. {
  935. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  936. ("whal_hwAccess_ReadMem: addr is not aligned 0x%x\n",
  937. addr));
  938. }
  939. #endif
  940. #ifdef HW_ACCESS_SDIO
  941. /* check address */
  942. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  943. {
  944. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  945. ("whal_hwAccess_ReadMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  946. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  947. return ERROR_HW_ACCEESS_ADDR;
  948. }
  949. request.buffer = data; /* Pointer to the data buffer aligned address. */
  950. request.buffer_len = len; /* Data buffer length in bytes */
  951. request.status = SDIO_Request_None;
  952. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  953. request.acquire_window = 0; /*Time out value is not set*/
  954. request.block_len = 0; /*Block length. Assigned by driver*/
  955. request.physical_buffer = 0; /*Physical address of data buffer is not set*/
  956. request.owner = (SDIO_Owner) pHwAccess;
  957. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  958. request.access_flag = 1;
  959. os_profile (pHwAccess->hOs, 2, 0);
  960. status = SDIO_SyncRead(pHwAccess->hDriver, &request);
  961. os_profile (pHwAccess->hOs, 3, 0);
  962. if (status != OK)
  963. {
  964. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  965. ("whal_hwAccess_ReadMem: SDIO Error in read\n"));
  966. return status;
  967. }
  968. #elif defined(HW_ACCESS_WSPI)
  969. /* check address */
  970. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  971. {
  972. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  973. ("whal_hwAccess_ReadMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  974. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  975. return ERROR_HW_ACCEESS_ADDR;
  976. }
  977. os_profile (pHwAccess->hOs, 2, 0);
  978. /* read the aligned size */
  979. status = WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,tempLen);
  980. os_profile (pHwAccess->hOs, 3, 0);
  981. if (status != OK)
  982. {
  983. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  984. ("whal_hwAccess_ReadMem: WSPI Error in read\n"));
  985. return status;
  986. }
  987. /* read the non aligned reminder */
  988. if(reminder)
  989. {
  990. UINT32 tempVal = 0;
  991. os_profile (pHwAccess->hOs, 2, 0);
  992. /* read the extra data*/
  993. status |= WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr+tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
  994. os_profile (pHwAccess->hOs, 3, 0);
  995. if (status != OK)
  996. {
  997. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  998. ("whal_hwAccess_ReadMem: WSPI Error in read\n"));
  999. return status;
  1000. }
  1001. /* extract the relevant data */
  1002. switch(reminder)
  1003. {
  1004. case 1:
  1005. mask = HW_ACCESS_1_BYTE_REMINDE_MASK;
  1006. break;
  1007. case 2:
  1008. mask = HW_ACCESS_2_BYTE_REMINDE_MASK;
  1009. break;
  1010. case 3:
  1011. mask = HW_ACCESS_3_BYTE_REMINDE_MASK;
  1012. break;
  1013. }
  1014. *(UINT32*)&data[tempLen] &= ~mask;
  1015. *(UINT32*)&data[tempLen] |= tempVal & mask;
  1016. }
  1017. #else
  1018. whal_hwAccess_DirectCopy_new(pHwAccess, data, (UINT8*)(pHwAccess->MemBaseAddr+addr), len);
  1019. #endif
  1020. #ifdef HW_ACCESS_SDIO
  1021. if (pHwAccess->uBusError)
  1022. {
  1023. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1024. ("whal_hwAccess_ReadMem: SDIO Error status=%d\n",
  1025. request.status));
  1026. if (pHwAccess->hwAccesserror_Cb)
  1027. {
  1028. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1029. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
  1030. }
  1031. else
  1032. pHwAccess->uBusError = 0;
  1033. }
  1034. #endif
  1035. return OK;
  1036. }
  1037. /****************************************************************************
  1038. * whal_hwAccess_WriteMem
  1039. ****************************************************************************
  1040. * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
  1041. * the length of data is checked and the remnant (length%4) is completed with read-modify-write
  1042. *
  1043. * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
  1044. * addr - UINT32 - the address offset inside the TNET
  1045. * data - UINT8* - a pointer to the buffer that holds the data to write
  1046. * Len - int - the length of the data to read
  1047. *
  1048. * OUTPUT: none
  1049. *
  1050. * RETURNS: one of the error codes (0 => OK)
  1051. ****************************************************************************/
  1052. int whal_hwAccess_WriteMem(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  1053. {
  1054. int status = OK;
  1055. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1056. #ifdef HW_ACCESS_SDIO
  1057. struct SDIO_Request request;
  1058. #elif defined(HW_ACCESS_WSPI)
  1059. int reminder = len % HW_ACCESS_WSPI_ALIGNED_SIZE;
  1060. int tempLen = len - reminder;
  1061. UINT32 mask = 0;
  1062. status = whal_hwAccess_WriteMemAsync(hHwAccess, addr, data, len);
  1063. if (status == TNETWIF_COMPLETE)
  1064. {
  1065. status = OK;
  1066. }
  1067. return status;
  1068. #endif
  1069. /* access is blocked */
  1070. if (pHwAccess->uBusError)
  1071. {
  1072. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
  1073. ("Bus is blocked \n"));
  1074. return ERROR_HW_ACCEESS_ADDR;
  1075. }
  1076. #ifdef __HWACCESS_DEBUG__
  1077. /* check address alignment */
  1078. if(addr & 0x3)
  1079. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1080. ("whal_hwAccess_WriteMem: addr is not aligned 0x%x\n",
  1081. addr));
  1082. #endif
  1083. #ifdef HW_ACCESS_SDIO
  1084. /* check address */
  1085. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  1086. {
  1087. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1088. ("whal_hwAccess_WriteMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1089. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  1090. return ERROR_HW_ACCEESS_ADDR;
  1091. }
  1092. request.buffer = data; /* Pointer to the data buffer aligned address. */
  1093. request.buffer_len = len; /* Data buffer length in bytes */
  1094. request.status = SDIO_Request_None;
  1095. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  1096. request.acquire_window = 0; /*Time out value is not set*/
  1097. request.block_len = 0; /*Block length. Assigned by driver*/
  1098. request.physical_buffer = 0; /*Physical address of data buffer is not set*/
  1099. request.owner = (SDIO_Owner) pHwAccess;
  1100. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  1101. request.access_flag = 0;
  1102. os_profile (pHwAccess->hOs, 2, 0);
  1103. status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
  1104. os_profile (pHwAccess->hOs, 3, 0);
  1105. if (status != OK)
  1106. {
  1107. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1108. ("whal_hwAccess_WriteMem: SDIO Error in write (%d)\n", status));
  1109. return status;
  1110. }
  1111. #elif defined(HW_ACCESS_WSPI)
  1112. /* check address */
  1113. if (((addr+len) > pHwAccess->workingPartUpperLimit) || (addr < pHwAccess->MemRegionAddr))
  1114. {
  1115. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1116. ("whal_hwAccess_WriteMem: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1117. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  1118. return ERROR_HW_ACCEESS_ADDR;
  1119. }
  1120. os_profile (pHwAccess->hOs, 2, 0);
  1121. /* write the aligned size */
  1122. status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr),data,tempLen);
  1123. os_profile (pHwAccess->hOs, 3, 0);
  1124. if (status != OK)
  1125. {
  1126. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1127. ("whal_hwAccess_WriteMem: WSPI Error in write\n"));
  1128. return status;
  1129. }
  1130. /* read the non aligned reminder */
  1131. if(reminder)
  1132. {
  1133. UINT32 tempVal;
  1134. os_profile (pHwAccess->hOs, 2, 0);
  1135. /* read the extra data*/
  1136. status |= WSPI_ReadSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr + tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
  1137. os_profile (pHwAccess->hOs, 3, 0);
  1138. if (status != OK)
  1139. {
  1140. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1141. ("whal_hwAccess_WriteMem: WSPI Error in read\n"));
  1142. return status;
  1143. }
  1144. /* extract the relevant data */
  1145. switch(reminder)
  1146. {
  1147. case 1:
  1148. mask = HW_ACCESS_1_BYTE_REMINDE_MASK;
  1149. break;
  1150. case 2:
  1151. mask = HW_ACCESS_2_BYTE_REMINDE_MASK;
  1152. break;
  1153. case 3:
  1154. mask = HW_ACCESS_3_BYTE_REMINDE_MASK;
  1155. break;
  1156. }
  1157. tempVal &= ~mask;
  1158. tempVal |= *(UINT32*)&data[tempLen] & mask;
  1159. os_profile (pHwAccess->hOs, 2, 0);
  1160. /* write the modified extra data */
  1161. status = WSPI_WriteSync(pHwAccess->hDriver,TRANSLATE_ADDRESS_MEM(addr + tempLen),(UINT8*)&tempVal,HW_ACCESS_WSPI_ALIGNED_SIZE);
  1162. os_profile (pHwAccess->hOs, 3, 0);
  1163. if (status != OK)
  1164. {
  1165. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1166. ("whal_hwAccess_WriteMem: WSPI Error in write\n"));
  1167. return status;
  1168. }
  1169. }
  1170. #else
  1171. whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)(pHwAccess->MemBaseAddr+addr), data, len);
  1172. #endif
  1173. #ifdef HW_ACCESS_SDIO
  1174. if (pHwAccess->uBusError)
  1175. {
  1176. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1177. ("whal_hwAccess_WriteMem: SDIO Error in write status=%d\n",
  1178. request.status));
  1179. if (pHwAccess->hwAccesserror_Cb)
  1180. {
  1181. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1182. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char*)&failure_reason,2);
  1183. }
  1184. else
  1185. pHwAccess->uBusError = 0;
  1186. }
  1187. #endif
  1188. return OK;
  1189. }
  1190. #endif /* USE_SYNC_API */
  1191. /****************************************************************************
  1192. * whal_hwAccess_WriteMemAsync
  1193. ****************************************************************************
  1194. * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
  1195. * the length of data is checked and the remnant (length%4) is completed with read-modify-write
  1196. * the function is passed a call-back function that will be called after the read request ends.
  1197. *
  1198. * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
  1199. * addr - UINT32 - the address offset inside the TNET
  1200. * data - UINT8* - a pointer to the buffer that holds the data to write
  1201. * Len - int - the length of the data to read
  1202. * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
  1203. *
  1204. * OUTPUT: none
  1205. *
  1206. * RETURNS: one of the error codes (0 => OK)
  1207. ****************************************************************************/
  1208. TI_STATUS whal_hwAccess_WriteMemAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  1209. {
  1210. #if defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  1211. /* Just call to synchronous API - add the offset that was added to the WSPI bus - only if it was reserved*/
  1212. return (whal_hwAccess_WriteMem (hHwAccess, addr, data + TNETWIF_WRITE_OFFSET_BYTES, len) == OK)
  1213. ? TNETWIF_COMPLETE
  1214. : TNETWIF_ERROR;
  1215. #else
  1216. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1217. int status = OK;
  1218. /* Access is blocked */
  1219. if (pHwAccess->uBusError)
  1220. {
  1221. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
  1222. ("Bus is blocked \n"));
  1223. return (TI_STATUS)ERROR_HW_ACCEESS_ADDR;
  1224. }
  1225. /* Check length */
  1226. if ((len & 0x3) != 0)
  1227. {
  1228. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1229. ("whal_hwAccess_WriteMemAsync: Error in length = %d\n",
  1230. len));
  1231. return (TI_STATUS)ERROR_HW_ACCEESS_LEN;
  1232. }
  1233. /* Check address */
  1234. if (addr + len > pHwAccess->workingPartUpperLimit ||
  1235. addr < pHwAccess->MemRegionAddr)
  1236. {
  1237. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1238. ("whal_hwAccess_WriteMemAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1239. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  1240. return (TI_STATUS)ERROR_HW_ACCEESS_ADDR;
  1241. }
  1242. #if defined(HW_ACCESS_SDIO)
  1243. {
  1244. struct SDIO_Request request;
  1245. request.buffer = data + TNETWIF_WRITE_OFFSET_BYTES; /*Pointer to the data buffer aligned address*/
  1246. request.buffer_len = len; /*Data buffer length in bytes*/
  1247. request.status = SDIO_Request_None;
  1248. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  1249. request.acquire_window = 0; /* Time out value is not set */
  1250. request.block_len = 0; /* Block length. Assigned by driver */
  1251. request.physical_buffer = 0; /* Physical address of data buffer is not set */
  1252. request.owner = (SDIO_Owner) pHwAccess;
  1253. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  1254. request.access_flag = 0;
  1255. request.fnotify = sdio_async_transaction_notify; /* completion notification */
  1256. request.ferror = sdio_async_transaction_error; /* error notification */
  1257. os_profile (pHwAccess->hOs, 2, 0);
  1258. status = SDIO_AsyncWrite (pHwAccess->hDriver, &request);
  1259. os_profile (pHwAccess->hOs, 3, 0);
  1260. if (status != OK)
  1261. {
  1262. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1263. ("whal_hwAccess_WriteMemAsync: Error in write async, addr=0x%08x status=%d\n",
  1264. addr, status));
  1265. return TNETWIF_ERROR;
  1266. }
  1267. if (pHwAccess->uBusError)
  1268. {
  1269. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1270. ("whal_hwAccess_WriteMemAsync: SDIO Error in write status=%d\n",
  1271. request.status));
  1272. if (pHwAccess->hwAccesserror_Cb)
  1273. {
  1274. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1275. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
  1276. }
  1277. else
  1278. pHwAccess->uBusError = 0;
  1279. }
  1280. return TNETWIF_COMPLETE;
  1281. }
  1282. #elif defined(HW_ACCESS_WSPI)
  1283. os_profile (pHwAccess->hOs, 2, 0);
  1284. status = WSPI_WriteAsync (pHwAccess->hDriver,
  1285. TRANSLATE_ADDRESS_MEM(addr),
  1286. data,
  1287. len,
  1288. (WSPI_CB_T*)&pHwAccess->CB,
  1289. TRUE,
  1290. TRUE); /* place is always reserved in write mem operation */
  1291. os_profile (pHwAccess->hOs, 3, 0);
  1292. WSPI2TNETWIF (pHwAccess, status, addr);
  1293. return (TI_STATUS)status;
  1294. #else
  1295. /* By now since the CB is a SYNCH interface then call the SYNCH interface */
  1296. whal_hwAccess_DirectCopy_new(pHwAccess, (UINT8*)(pHwAccess->MemBaseAddr+addr), data, len);
  1297. return OK;
  1298. #endif
  1299. #endif
  1300. }
  1301. /****************************************************************************
  1302. * whal_hwAccess_ReadMemAsync
  1303. ****************************************************************************
  1304. * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
  1305. * the length of data is checked and the remnant (length%4) is completed with read-modify
  1306. * the function is passed a call-back function that will be called after the read request ends.
  1307. *
  1308. * INPUTS: pHwAccess - TI_HANDLE* - the HwAccess context
  1309. * addr - UINT32 - the address offset inside the TNET
  1310. * Len - int - the length of the data to read
  1311. * CB - HWAccess_CB_T* - a pointer to a structure that holds the CB function and the passed arg.
  1312. *
  1313. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  1314. *
  1315. * RETURNS: one of the error codes (0 => OK)
  1316. ****************************************************************************/
  1317. int whal_hwAccess_ReadMemAsync (TI_HANDLE hHwAccess, UINT32 addr, UINT8* data, UINT16 len)
  1318. {
  1319. #if defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  1320. /* Just call to synchronous API - add the offset that was added to the WSPI bus */
  1321. return (whal_hwAccess_ReadMem (hHwAccess, addr, data + TNETWIF_READ_OFFSET_BYTES, len) == OK)
  1322. ? TNETWIF_COMPLETE
  1323. : TNETWIF_ERROR;
  1324. #else
  1325. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1326. int status = OK;
  1327. /* Access is blocked */
  1328. if (pHwAccess->uBusError)
  1329. {
  1330. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_CTRL_MODULE_LOG,
  1331. ("Bus is blocked \n"));
  1332. return ERROR_HW_ACCEESS_ADDR;
  1333. }
  1334. /* Check length */
  1335. if ((len & 0x3) != 0)
  1336. {
  1337. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1338. ("whal_hwAccess_ReadMemAsync: Error in length = %d\n",
  1339. len));
  1340. return ERROR_HW_ACCEESS_LEN;
  1341. }
  1342. /* Check address */
  1343. if (addr + len > pHwAccess->workingPartUpperLimit ||
  1344. addr < pHwAccess->MemRegionAddr)
  1345. {
  1346. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1347. ("whal_hwAccess_ReadMemAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1348. addr, pHwAccess->MemRegionAddr, pHwAccess->workingPartUpperLimit));
  1349. return ERROR_HW_ACCEESS_ADDR;
  1350. }
  1351. #if defined(HW_ACCESS_SDIO)
  1352. {
  1353. struct SDIO_Request request;
  1354. request.buffer = data + TNETWIF_READ_OFFSET_BYTES; /*Pointer to the data buffer aligned address*/
  1355. request.buffer_len = len; /*Data buffer length in bytes*/
  1356. request.status = SDIO_Request_None;
  1357. request.peripheral_addr = (SDIO_Address)TRANSLATE_ADDRESS_MEM(addr); /*SDIO peripheral address*/
  1358. request.acquire_window = 0; /* Time out value is not set */
  1359. request.block_len = 0; /* Block length. Assigned by driver */
  1360. request.physical_buffer = 0; /* Physical address of data buffer is not set */
  1361. request.owner = (SDIO_Owner) pHwAccess;
  1362. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  1363. request.access_flag = 0;
  1364. request.fnotify = sdio_async_transaction_notify; /* completion notification */
  1365. request.ferror = sdio_async_transaction_error; /* error notification */
  1366. os_profile (pHwAccess->hOs, 2, 0);
  1367. status = SDIO_AsyncRead (pHwAccess->hDriver, &request);
  1368. os_profile (pHwAccess->hOs, 3, 0);
  1369. if (status != OK)
  1370. {
  1371. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1372. ("whal_hwAccess_ReadMemAsync: Error in write async, addr=0x%08x status=%d\n",
  1373. addr, status));
  1374. return TNETWIF_ERROR;
  1375. }
  1376. if (pHwAccess->uBusError)
  1377. {
  1378. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1379. ("whal_hwAccess_ReadMemAsync: SDIO Error in write SrcOffset=0x%08x status=%d\n",
  1380. SrcOffset, request.status));
  1381. if (pHwAccess->hwAccesserror_Cb)
  1382. {
  1383. UINT16 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1384. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,&failure_reason,2);
  1385. }
  1386. else
  1387. pHwAccess->uBusError = 0;
  1388. }
  1389. return TNETWIF_COMPLETE;
  1390. }
  1391. #elif defined(HW_ACCESS_WSPI)
  1392. os_profile (pHwAccess->hOs, 2, 0);
  1393. status = WSPI_ReadAsync (pHwAccess->hDriver,
  1394. TRANSLATE_ADDRESS_MEM(addr),
  1395. data,
  1396. len,
  1397. (WSPI_CB_T*)&pHwAccess->CB,
  1398. TRUE,
  1399. TRUE); /* place is always reserved in readMem */
  1400. os_profile (pHwAccess->hOs, 3, 0);
  1401. WSPI2TNETWIF (pHwAccess, status, addr);
  1402. return status;
  1403. #endif
  1404. #endif
  1405. }
  1406. #ifdef USE_SYNC_API
  1407. /****************************************************************************
  1408. * whal_hwAccess_ReadReg
  1409. ****************************************************************************
  1410. * DESCRIPTION: read data synchronously from the TNET using the defined access (WSPI/SDIO).
  1411. * the length of data is always 4bytes cause this is the size of the TNET registers
  1412. *
  1413. * INPUTS: pHwAccess - HwAccess_T_new* - the HwAccess context
  1414. * addr - UINT32 - the address offset inside the TNET
  1415. * Len - int - the length of the data to read
  1416. *
  1417. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  1418. *
  1419. * RETURNS: one of the error codes (0 => OK)
  1420. ****************************************************************************/
  1421. int whal_hwAccess_ReadReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data)
  1422. {
  1423. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1424. int status = OK;
  1425. #ifdef HW_ACCESS_SDIO
  1426. struct SDIO_Request request;
  1427. /* check address */
  1428. if (addr > pHwAccess->registerPartUpperLimit)
  1429. {
  1430. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1431. ("whal_hwAccess_ReadReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1432. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1433. return ERROR_HW_ACCEESS_ADDR;
  1434. }
  1435. request.buffer = (UINT8*)data; /*Pointer to the data buffer aligned address.*/
  1436. request.buffer_len = HW_ACCESS_REGISTER_SIZE; /*Data buffer length in bytes*/
  1437. request.status = SDIO_Request_None;
  1438. request.peripheral_addr = TRANSLATE_ADDRESS_REG(addr);
  1439. request.acquire_window = 0; /* Time out value is not set */
  1440. request.block_len = 0; /* Block length. Assigned by driver */
  1441. request.owner = (SDIO_Owner) pHwAccess;
  1442. request.physical_buffer = 0; /* Physical address of data buffer is not set */
  1443. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  1444. request.access_flag = 1;
  1445. os_profile (pHwAccess->hOs, 2, 0);
  1446. status = SDIO_SyncRead(pHwAccess->hDriver, &request);
  1447. os_profile (pHwAccess->hOs, 3, 0);
  1448. #elif defined(HW_ACCESS_WSPI)
  1449. status = whal_hwAccess_ReadRegAsync(hHwAccess, addr, data);
  1450. if (status == TNETWIF_COMPLETE)
  1451. {
  1452. status = OK;
  1453. }
  1454. return status;
  1455. /* check address */
  1456. if ((addr > pHwAccess->registerPartUpperLimit) || (addr < 0))
  1457. {
  1458. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1459. ("whal_hwAccess_ReadReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1460. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1461. return ERROR_HW_ACCEESS_ADDR;
  1462. }
  1463. os_profile (pHwAccess->hOs, 2, 0);
  1464. status = WSPI_ReadSync(pHwAccess->hDriver, TRANSLATE_ADDRESS_REG(addr), (UINT8*)data, HW_ACCESS_REGISTER_SIZE);
  1465. os_profile (pHwAccess->hOs, 3, 0);
  1466. #else
  1467. HW_REG_LONG_READ(pHwAccess,addr,data);
  1468. #endif
  1469. if (status != OK)
  1470. {
  1471. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1472. ("whal_hwAccess_ReadReg: Error in reg read RegAddr=0x%08x status=%d\n",
  1473. addr, status));
  1474. }
  1475. #ifdef HW_ACCESS_SDIO
  1476. if (pHwAccess->uBusError)
  1477. {
  1478. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1479. ("whal_hwAccess_ReadReg: SDIO Error status=%d\n",
  1480. request.status));
  1481. if (pHwAccess->hwAccesserror_Cb)
  1482. {
  1483. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1484. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char *)&failure_reason,2);
  1485. }
  1486. else
  1487. pHwAccess->uBusError = 0;
  1488. }
  1489. #endif
  1490. return status;
  1491. }
  1492. #endif /* USE_SYNC_API */
  1493. /****************************************************************************
  1494. * whal_hwAccess_Stop()
  1495. ****************************************************************************
  1496. * DESCRIPTION: stops the bus driver
  1497. *
  1498. * INPUTS: None
  1499. *
  1500. * OUTPUT: None
  1501. *
  1502. * RETURNS:
  1503. ****************************************************************************/
  1504. int whal_hwAccess_Stop(TI_HANDLE hHwAccess)
  1505. {
  1506. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1507. /* unbclock the access to the bus */
  1508. pHwAccess->uBusError = 0;
  1509. #ifdef HW_ACCESS_SDIO
  1510. SDIO_Stop(pHwAccess->hDriver,0);
  1511. #elif defined(HW_ACCESS_WSPI)
  1512. /* TODO*/
  1513. #endif
  1514. return OK;
  1515. }
  1516. #ifdef USE_SYNC_API
  1517. /****************************************************************************
  1518. * whal_hwAccess_WriteReg
  1519. ****************************************************************************
  1520. * DESCRIPTION: write data synchronously to the TNET using the defined access (WSPI/SDIO).
  1521. * the length of data is always 4bytes cause this is the size of the TNET registers
  1522. *
  1523. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  1524. * addr - UINT32 - the address offset inside the TNET
  1525. * data - UINT8* - a pointer to the buffer that holds the data to write
  1526. * Len - int - the length of the data to read
  1527. *
  1528. * OUTPUT: none
  1529. *
  1530. * RETURNS: one of the error codes (0 => OK)
  1531. ****************************************************************************/
  1532. int whal_hwAccess_WriteReg(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data)
  1533. {
  1534. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1535. int status = OK;
  1536. #ifdef HW_ACCESS_SDIO
  1537. struct SDIO_Request request;
  1538. /* check address */
  1539. if (addr > pHwAccess->registerPartUpperLimit)
  1540. {
  1541. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1542. ("whal_hwAccess_WriteReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1543. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1544. return ERROR_HW_ACCEESS_ADDR;
  1545. }
  1546. request.buffer = (UINT8*)&data; /*Pointer to the data buffer aligned address.*/
  1547. request.buffer_len = HW_ACCESS_REGISTER_SIZE; /*Data buffer length in bytes*/
  1548. request.status = SDIO_Request_None;
  1549. request.peripheral_addr = TRANSLATE_ADDRESS_REG(addr);
  1550. request.acquire_window = 0; /* Time out value is not set */
  1551. request.block_len = 0; /* Block length. Assigned by driver */
  1552. request.owner = (SDIO_Owner) pHwAccess;
  1553. request.physical_buffer = 0; /* Physical address of data buffer is not set */
  1554. request.mode = MMC_DEV_BYTE_INCREMENTAL_MODE;
  1555. request.access_flag = 0;
  1556. os_profile (pHwAccess->hOs, 2, 0);
  1557. status = SDIO_SyncWrite(pHwAccess->hDriver, &request);
  1558. os_profile (pHwAccess->hOs, 3, 0);
  1559. #elif defined(HW_ACCESS_WSPI)
  1560. status = whal_hwAccess_WriteRegAsync(hHwAccess, addr, data);
  1561. if (status == TNETWIF_COMPLETE)
  1562. {
  1563. status = OK;
  1564. }
  1565. return status;
  1566. /* check address */
  1567. if ((addr > pHwAccess->registerPartUpperLimit) || (addr < 0))
  1568. {
  1569. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1570. ("whal_hwAccess_WriteReg: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1571. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1572. return ERROR_HW_ACCEESS_ADDR;
  1573. }
  1574. os_profile (pHwAccess->hOs, 2, 0);
  1575. status = WSPI_WriteSync(pHwAccess->hDriver, TRANSLATE_ADDRESS_REG(addr), (UINT8*)&data, HW_ACCESS_REGISTER_SIZE);
  1576. os_profile (pHwAccess->hOs, 3, 0);
  1577. #else
  1578. HW_REG_LONG_WRITE(pHwAccess, addr, data);
  1579. #endif
  1580. if (status != OK)
  1581. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1582. ("whal_hwAccess_WriteReg: Error in reg write RegAddr=0x%08x status=%d\n",
  1583. addr, status));
  1584. #ifdef HW_ACCESS_SDIO
  1585. if (pHwAccess->uBusError)
  1586. {
  1587. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1588. ("whal_hwAccess_WriteReg: SDIO Error in write status=%d\n",
  1589. request.status));
  1590. if (pHwAccess->hwAccesserror_Cb)
  1591. {
  1592. UINT8 failure_reason = HEALTH_REPORT_BUS_ERROR;
  1593. pHwAccess->hwAccesserror_Cb(pHwAccess->hBackReference,(char *)&failure_reason,2);
  1594. }
  1595. else
  1596. pHwAccess->uBusError = 0;
  1597. }
  1598. #endif
  1599. return status;
  1600. }
  1601. #endif /* USE_SYNC_API */
  1602. /****************************************************************************
  1603. * whal_hwAccess_ReadRegAsync
  1604. ****************************************************************************
  1605. * DESCRIPTION: read data asynchronously from the TNET using the defined access (WSPI/SDIO).
  1606. * the length of data is always 4bytes cause this is the size of the TNET registers
  1607. * the function is passed a call-back function that will be called after the read request ends.
  1608. *
  1609. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  1610. * addr - UINT32 - the address offset inside the TNET
  1611. *
  1612. * OUTPUT: data - UINT8* - a pointer to the buffer to fill with the read data
  1613. *
  1614. * RETURNS: one of the error codes (0 => OK)
  1615. ****************************************************************************/
  1616. int whal_hwAccess_ReadRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32* data)
  1617. {
  1618. #if defined(HW_ACCESS_SDIO)
  1619. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  1620. #error "SDIO asynchronous mode is not supported"
  1621. /* Not implemented yet */
  1622. return OK;
  1623. #else
  1624. /* Just call to synchronous API */
  1625. return (whal_hwAccess_ReadReg (hHwAccess, addr, data) == OK)
  1626. ? TNETWIF_COMPLETE
  1627. : TNETWIF_ERROR;
  1628. #endif
  1629. #else /* HW_ACCESS_WSPI */
  1630. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1631. int status;
  1632. /* Check address */
  1633. if (addr > pHwAccess->registerPartUpperLimit)
  1634. {
  1635. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1636. ("whal_hwAccess_ReadRegAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1637. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1638. return ERROR_HW_ACCEESS_ADDR;
  1639. }
  1640. os_profile (pHwAccess->hOs, 2, 0);
  1641. /* In registers we don't save place */
  1642. status = WSPI_ReadAsync (pHwAccess->hDriver,
  1643. TRANSLATE_ADDRESS_REG(addr),
  1644. (UINT8*)data,
  1645. HW_ACCESS_REGISTER_SIZE,
  1646. (WSPI_CB_T*)&pHwAccess->CB,
  1647. TRUE,
  1648. FALSE);
  1649. os_profile (pHwAccess->hOs, 3, 0);
  1650. WSPI2TNETWIF (pHwAccess, status, addr);
  1651. return status;
  1652. #endif
  1653. }
  1654. /****************************************************************************
  1655. * whal_hwAccess_WriteRegAsync
  1656. ****************************************************************************
  1657. * DESCRIPTION: write data synchronously from the TNET using the defined access (WSPI/SDIO).
  1658. * the length of data is always 4bytes cause this is the size of the TNET registers
  1659. * the function is passed a call-back function that will be called after the read request ends.
  1660. *
  1661. * INPUTS: pHwAccess - TI_HANDLE * - the HwAccess context
  1662. * addr - UINT32 - the address offset inside the TNET
  1663. * data - UINT8* - a pointer to the buffer that holds the data to write
  1664. *
  1665. * OUTPUT: none
  1666. *
  1667. * RETURNS: one of the error codes (0 => OK)
  1668. ****************************************************************************/
  1669. int whal_hwAccess_WriteRegAsync(TI_HANDLE hHwAccess, UINT32 addr, UINT32 data)
  1670. {
  1671. #if defined(HW_ACCESS_SDIO)
  1672. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  1673. #error "SDIO asynchronous mode is not supported"
  1674. /* Not implemented yet */
  1675. return OK;
  1676. #else
  1677. /* Just call to synchronous API */
  1678. return (whal_hwAccess_WriteReg (hHwAccess, addr, data) == OK)
  1679. ? TNETWIF_COMPLETE
  1680. : TNETWIF_ERROR;
  1681. #endif
  1682. #else /* HW_ACCESS_WSPI */
  1683. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)hHwAccess;
  1684. int status;
  1685. /* Check address */
  1686. if (addr > pHwAccess->registerPartUpperLimit)
  1687. {
  1688. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1689. ("whal_hwAccess_WriteRegAsync: Error in addr 0x%x (lower:0x%x,upper:0x%x)\n",
  1690. addr, pHwAccess->RegisterRegionAddr, pHwAccess->registerPartUpperLimit));
  1691. return ERROR_HW_ACCEESS_ADDR;
  1692. }
  1693. os_profile (pHwAccess->hOs, 2, 0);
  1694. status = WSPI_WriteAsync (pHwAccess->hDriver,
  1695. TRANSLATE_ADDRESS_REG(addr),
  1696. (UINT8*)&data,
  1697. HW_ACCESS_REGISTER_SIZE,
  1698. (WSPI_CB_T*)&pHwAccess->CB,
  1699. TRUE,
  1700. FALSE);
  1701. os_profile (pHwAccess->hOs, 3, 0);
  1702. WSPI2TNETWIF (pHwAccess, status, addr);
  1703. return status;
  1704. #endif
  1705. }
  1706. #ifdef USE_SYNC_API
  1707. /****************************************************************************
  1708. * whal_hwAccess_SetPartitions
  1709. ****************************************************************************
  1710. * DESCRIPTION: the client always sees two partitions
  1711. * 1 - the working partition that the client access it with mem functions (for this partition the client supplies the base address)
  1712. * 2 - the registers partition that is always set on HW_ACCESS_REG_ADDR and its size is HW_ACCESS_REG_SIZE.
  1713. *
  1714. * INPUTS: pHwAccess - a pointer to the module context
  1715. * partitionMode - the mode to set the partitions
  1716. * partition_start - the start address of the working partition
  1717. *
  1718. * OUTPUT: none
  1719. *
  1720. * RETURNS: one of the error codes (0 => OK)
  1721. ****************************************************************************/
  1722. int whal_hwAccess_SetPartitions (TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start)
  1723. {
  1724. HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
  1725. int status = OK;
  1726. #ifdef HW_ACCESS_SDIO
  1727. SDIO_TNETWConfigParams sdioConfParam;
  1728. Peripheral_ConfigParams *cfg;
  1729. #endif
  1730. pHwAccess->partition[0].size = 0;
  1731. pHwAccess->partition[0].start = partition_start;
  1732. pHwAccess->partition[1].size = 0;
  1733. pHwAccess->partition[1].start = 0;
  1734. switch(partitionMode)
  1735. {
  1736. case HW_ACCESS_DOWNLOAD:
  1737. pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_DOWN_PART1_SIZE;
  1738. pHwAccess->partition[1].start = HW_ACCESS_DOWN_PART1_ADDR;
  1739. pHwAccess->partition[1].size = HW_ACCESS_DOWN_PART1_SIZE;
  1740. break;
  1741. case HW_ACCESS_WORKING:
  1742. pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_WORK_PART1_SIZE;
  1743. pHwAccess->partition[1].start = HW_ACCESS_WORK_PART1_ADDR;
  1744. pHwAccess->partition[1].size = HW_ACCESS_WORK_PART1_SIZE;
  1745. break;
  1746. }
  1747. #if (defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI))
  1748. /* guarantee that the working partition wont overlap the registers partition */
  1749. if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > pHwAccess->partition[1].start)
  1750. pHwAccess->partition[0].size = pHwAccess->partition[1].start - pHwAccess->partition[0].start;
  1751. /* guarantee that the working partition won't exceed the packet RAM */
  1752. if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > HW_ACCESS_PRAM_MAX_RANGE)
  1753. pHwAccess->partition[0].size = HW_ACCESS_PRAM_MAX_RANGE - pHwAccess->partition[0].start;
  1754. pHwAccess->workingPartUpperLimit = pHwAccess->partition[0].start + pHwAccess->partition[0].size;
  1755. pHwAccess->registerPartUpperLimit = pHwAccess->partition[1].size;
  1756. pHwAccess->RegisterRegionAddr = pHwAccess->partition[0].size;
  1757. pHwAccess->MemRegionAddr = pHwAccess->partition[0].start;
  1758. #ifdef HW_ACCESS_SDIO
  1759. os_memoryZero (pHwAccess->hOs, &sdioConfParam, sizeof(SDIO_TNETWConfigParams));
  1760. sdioConfParam.num_of_parts = 2;
  1761. sdioConfParam.map_reg[0].reg_size = pHwAccess->partition[0].size;
  1762. sdioConfParam.map_reg[0].scr_offset = pHwAccess->partition[0].start;
  1763. sdioConfParam.map_reg[1].reg_size = pHwAccess->partition[1].size;
  1764. sdioConfParam.map_reg[1].scr_offset = pHwAccess->partition[1].start;
  1765. status = SDIO_TNETWInit(&sdioConfParam);
  1766. status = (status == SDIO_SUCCESS) ? SDIO_TNETWConfig(pHwAccess->hDriver, &cfg) : status;
  1767. status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
  1768. #elif defined(HW_ACCESS_WSPI)
  1769. /*
  1770. * IMPORTANT NOTE (TODO): the ASYNC API is used here assuming the call will always
  1771. * be completed synchronously. This is done because only the Async API is wokring
  1772. * in 4.0.4. In future versions, the whole recovery process should be made asynchronous.
  1773. */
  1774. /* May use only one write because the addresses in the firmware are sequential */
  1775. status = WSPI_WriteAsync (pHwAccess->hDriver,
  1776. HW_ACCESS_PART0_SIZE_ADDR,
  1777. PADWRITE (pHwAccess->partition),
  1778. sizeof(partition_t) * 2,
  1779. (WSPI_CB_T*)&pHwAccess->CB,
  1780. TRUE, TRUE);
  1781. WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_PART0_SIZE_ADDR);
  1782. #endif
  1783. #endif
  1784. return status;
  1785. }
  1786. #endif /* USE_SYNC_API */
  1787. /****************************************************************************
  1788. * whal_hwAccess_SetPartitionsAsync
  1789. ****************************************************************************
  1790. * DESCRIPTION: the client always sees two partitions
  1791. * 1 - the working partition that the client access it with mem functions (for this partition the client supplies the base address)
  1792. * 2 - the registers partition that is always set on HW_ACCESS_REG_ADDR and its size is HW_ACCESS_REG_SIZE.
  1793. *
  1794. * INPUTS: pHwAccess - a pointer to the module context
  1795. * partitionMode - the mode to set the partitions
  1796. * partition_start - the start address of the working partition
  1797. *
  1798. * OUTPUT: none
  1799. *
  1800. * RETURNS: one of the error codes (0 => OK)
  1801. ****************************************************************************/
  1802. int whal_hwAccess_SetPartitionsAsync (TI_HANDLE hHwAccess, TNETIF_HwAccess_SetPartition_mode_e partitionMode, UINT32 partition_start)
  1803. {
  1804. HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
  1805. int status = OK;
  1806. #ifdef HW_ACCESS_SDIO
  1807. SDIO_TNETWConfigParams sdioConfParam;
  1808. Peripheral_ConfigParams *cfg;
  1809. #endif
  1810. pHwAccess->partition[0].size = 0;
  1811. pHwAccess->partition[0].start = partition_start;
  1812. pHwAccess->partition[1].size = 0;
  1813. pHwAccess->partition[1].start = 0;
  1814. switch(partitionMode)
  1815. {
  1816. case HW_ACCESS_DOWNLOAD:
  1817. pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_DOWN_PART1_SIZE;
  1818. pHwAccess->partition[1].start = HW_ACCESS_DOWN_PART1_ADDR;
  1819. pHwAccess->partition[1].size = HW_ACCESS_DOWN_PART1_SIZE;
  1820. break;
  1821. case HW_ACCESS_WORKING:
  1822. pHwAccess->partition[0].size = HW_ACCESS_MEMORY_MAX_RANGE - HW_ACCESS_WORK_PART1_SIZE;
  1823. pHwAccess->partition[1].start = HW_ACCESS_WORK_PART1_ADDR;
  1824. pHwAccess->partition[1].size = HW_ACCESS_WORK_PART1_SIZE;
  1825. break;
  1826. }
  1827. #if (defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI))
  1828. /* guarantee that the working partition wont overlap the registers partition */
  1829. if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > pHwAccess->partition[1].start)
  1830. pHwAccess->partition[0].size = pHwAccess->partition[1].start - pHwAccess->partition[0].start;
  1831. /* guarantee that the working partition won't exceed the packet RAM */
  1832. if((pHwAccess->partition[0].start + pHwAccess->partition[0].size) > HW_ACCESS_PRAM_MAX_RANGE)
  1833. pHwAccess->partition[0].size = HW_ACCESS_PRAM_MAX_RANGE - pHwAccess->partition[0].start;
  1834. pHwAccess->workingPartUpperLimit = pHwAccess->partition[0].start + pHwAccess->partition[0].size;
  1835. pHwAccess->registerPartUpperLimit = pHwAccess->partition[1].size;
  1836. pHwAccess->RegisterRegionAddr = pHwAccess->partition[0].size;
  1837. pHwAccess->MemRegionAddr = pHwAccess->partition[0].start;
  1838. #ifdef HW_ACCESS_SDIO
  1839. os_memoryZero (pHwAccess->hOs, &sdioConfParam, sizeof(SDIO_TNETWConfigParams));
  1840. sdioConfParam.num_of_parts = 2;
  1841. sdioConfParam.map_reg[0].reg_size = pHwAccess->partition[0].size;
  1842. sdioConfParam.map_reg[0].scr_offset = pHwAccess->partition[0].start;
  1843. sdioConfParam.map_reg[1].reg_size = pHwAccess->partition[1].size;
  1844. sdioConfParam.map_reg[1].scr_offset = pHwAccess->partition[1].start;
  1845. status = SDIO_TNETWInit(&sdioConfParam);
  1846. status = (status == SDIO_SUCCESS) ? SDIO_TNETWConfig(pHwAccess->hDriver, &cfg) : status;
  1847. status = (status == SDIO_SUCCESS) ? TNETWIF_COMPLETE : TNETWIF_ERROR;
  1848. #elif defined(HW_ACCESS_WSPI)
  1849. /* May use only one write because the addresses in the firmware are sequential */
  1850. status = WSPI_WriteAsync (pHwAccess->hDriver,
  1851. HW_ACCESS_PART0_SIZE_ADDR,
  1852. PADWRITE (pHwAccess->partition),
  1853. sizeof(partition_t) * 2,
  1854. (WSPI_CB_T*)&pHwAccess->CB,
  1855. TRUE,
  1856. TRUE);
  1857. WSPI2TNETWIF (pHwAccess, status, HW_ACCESS_PART0_SIZE_ADDR);
  1858. #endif
  1859. #endif
  1860. return status;
  1861. }
  1862. #if !defined(HW_ACCESS_SDIO) && !defined(HW_ACCESS_WSPI)
  1863. /****************************************************************************
  1864. * whal_hwAccess_DirectCopy_new()
  1865. ****************************************************************************
  1866. * DESCRIPTION: Direct Copy sequence of bytes to/from the hardware
  1867. *
  1868. * INPUTS:
  1869. * pHwAccess The object
  1870. * Dest Destination address
  1871. * Src Source address
  1872. * Len The length of the data to copy
  1873. *
  1874. * OUTPUT: None
  1875. *
  1876. * RETURNS: OK or NOK
  1877. ****************************************************************************/
  1878. static void whal_hwAccess_DirectCopy_new(HwAccess_T_new *pHwAccess, UINT8* Dest, UINT8* Src, UINT32 Len)
  1879. {
  1880. #ifdef NOT_SUPPORT_08_BIT_ACCESS_COMMAND
  1881. /* first see if dest addr is 4 bytes
  1882. align if not we are using local copy and not
  1883. os_memoryCopy
  1884. */
  1885. if(((UINT32)Dest & 0x00000001))
  1886. {
  1887. /* TBD - Currently unaligned destination address is not handled.
  1888. it means that CKIP will not work currently.
  1889. */
  1890. }else
  1891. if(((UINT32)Dest & 0x00000002))
  1892. {
  1893. register volatile unsigned short *shortDest = (volatile unsigned short *)Dest;
  1894. register volatile unsigned short *shortSrc = (unsigned short *)Src;
  1895. register int Size = Len >> 1;
  1896. unsigned short TempWord;
  1897. while (Size--)
  1898. *shortDest++ = *shortSrc++;
  1899. if (Len&1)
  1900. {
  1901. TempWord = ENDIAN_HANDLE_WORD((*shortSrc & 0x00ff) | (*shortDest & 0xff00));
  1902. *shortDest = TempWord;
  1903. }
  1904. }else
  1905. {
  1906. /* The address line A0 is not connected
  1907. For arm/linux sake not 2, but 4-alignment is enforced.
  1908. (Linux memcpy uses longs copy logic)
  1909. */
  1910. int Len1 = Len & 0xfffffffc;
  1911. os_memoryCopy(pHwAccess->hOs, (void*)Dest, (void*)Src, Len1);
  1912. if (Len1 != Len)
  1913. {
  1914. int ShortSize=Len1 >> 1;
  1915. volatile unsigned short *shortDest = ((unsigned short *)Dest) + ShortSize;
  1916. volatile unsigned short *shortSrc = ((unsigned short *)Src) + ShortSize;
  1917. if (Len - Len1 >= 2)
  1918. *shortDest++ = *shortSrc++;
  1919. if (Len & 1)
  1920. *shortDest = ENDIAN_HANDLE_WORD((*shortSrc & 0x00ff) | (*shortDest & 0xff00));
  1921. }
  1922. }
  1923. #else
  1924. os_memoryCopy(pHwAccess->hOs, (void*)Dest, (void*)Src, Len);
  1925. #endif
  1926. }
  1927. #endif
  1928. #ifdef HW_ACCESS_SDIO
  1929. /* callback notify read/write transaction function */
  1930. static void sdio_transaction_notify_read(struct SDIO_Request *req, int status)
  1931. {
  1932. }
  1933. static void sdio_transaction_notify_write(struct SDIO_Request *req, int status)
  1934. {
  1935. }
  1936. /* callback notify error read/write transaction function */
  1937. static void sdio_transaction_error(struct SDIO_Request *req, int stat)
  1938. {
  1939. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
  1940. WLAN_REPORT_ERROR (pHwAccess->hReport, HAL_CTRL_MODULE_LOG, ("sdio_transaction_error\n"));
  1941. pHwAccess->uBusError = 1;
  1942. }
  1943. #if defined(HW_ACCESS_SDIO_ASYNC_SUPPORT)
  1944. static void sdio_async_transaction_notify(struct SDIO_Request *req, int status)
  1945. {
  1946. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
  1947. /* call the CB */
  1948. pHwAccess->CB.CBFunc(pHwAccess->CB.CBArg,status);
  1949. WLAN_REPORT_INFORMATION(pHwAccess->hReport,
  1950. HAL_HW_CTRL_MODULE_LOG,
  1951. ("sdio_async_transaction_notify - request=%p, buf=%p, sdio_addr=0x%08lx, len=%u\n",
  1952. req, req->buffer, req->peripheral_addr, req->block_len));
  1953. }
  1954. /* callback notify error read/write transaction function */
  1955. static void sdio_async_transaction_error(struct SDIO_Request *req, int status)
  1956. {
  1957. HwAccess_T_new* pHwAccess = (HwAccess_T_new*)req->owner;
  1958. WLAN_REPORT_ERROR(pHwAccess->hReport, HAL_HW_CTRL_MODULE_LOG,
  1959. ("sdio_async_transaction_error: request=%p, buf=%p, sdio_addr=0x%08lx, len=%u\n",
  1960. req, req->buffer, req->peripheral_addr, req->block_len));
  1961. }
  1962. #endif /*HW_ACCESS_SDIO_ASYNC_SUPPORT*/
  1963. #endif /*HW_ACCESS_SDIO*/
  1964. TI_STATUS whal_hwAccess_RegisterForErrorCB(TI_HANDLE hHwAccess,
  1965. void* CbFunc,
  1966. TI_HANDLE CbObj)
  1967. {
  1968. HwAccess_T_new *pHwAccess = (HwAccess_T_new *)hHwAccess;
  1969. pHwAccess->hwAccesserror_Cb = (HwAccessErrorHandle)CbFunc;
  1970. pHwAccess->hBackReference = CbObj;
  1971. return OK;
  1972. }
  1973. /***********************************************************/
  1974. #ifdef USE_SYNC_API
  1975. /****************************************************************************
  1976. * whal_hwAccess_RegSetBitVal()
  1977. ****************************************************************************
  1978. * DESCRIPTION: wlan hardware registers bits access
  1979. *
  1980. * INPUTS:
  1981. *
  1982. * OUTPUT: None
  1983. *
  1984. * RETURNS: OK or NOK
  1985. ****************************************************************************/
  1986. void whal_hwAccess_RegSetBitVal(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
  1987. {
  1988. UINT32 rVal;
  1989. whal_hwAccess_ReadReg(hHwAccess,RegAddr,&rVal);
  1990. rVal |= BitVal;
  1991. whal_hwAccess_WriteReg(hHwAccess, RegAddr, rVal);
  1992. }
  1993. /****************************************************************************
  1994. * whal_hwAccess_RegResetBitVal()
  1995. ****************************************************************************
  1996. * DESCRIPTION: wlan hardware registers bits access
  1997. *
  1998. * INPUTS:
  1999. *
  2000. * OUTPUT: None
  2001. *
  2002. * RETURNS: OK or NOK
  2003. ****************************************************************************/
  2004. void whal_hwAccess_RegResetBitVal(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
  2005. {
  2006. UINT32 rVal;
  2007. whal_hwAccess_ReadReg(hHwAccess,RegAddr,&rVal);
  2008. rVal &= ~BitVal;
  2009. whal_hwAccess_WriteReg(hHwAccess, RegAddr, rVal);
  2010. }
  2011. /****************************************************************************
  2012. * whal_hwAccess_RegIsBitSet()
  2013. ****************************************************************************
  2014. * DESCRIPTION: wlan hardware registers bits access
  2015. *
  2016. * INPUTS:
  2017. *
  2018. * OUTPUT: None
  2019. *
  2020. * RETURNS: OK or NOK
  2021. ****************************************************************************/
  2022. int whal_hwAccess_RegIsBitSet(TI_HANDLE hHwAccess, UINT32 RegAddr, UINT32 BitVal)
  2023. {
  2024. UINT32 RegVal;
  2025. whal_hwAccess_ReadReg(hHwAccess,RegAddr,&RegVal);
  2026. if (RegVal & BitVal)
  2027. return 1;
  2028. return 0;
  2029. }
  2030. /****************************************************************************
  2031. * whal_hwAccess_(Get/Set/SetBits/ResetBits)U08()
  2032. ****************************************************************************
  2033. * DESCRIPTION: wlan hardware memory access to bytes
  2034. *
  2035. * INPUTS:
  2036. *
  2037. * OUTPUT: None
  2038. *
  2039. * RETURNS: OK or NOK
  2040. ****************************************************************************/
  2041. UINT8 whal_hwAccess_GetU08(TI_HANDLE hHwAccess, UINT32 Addr)
  2042. {
  2043. #ifdef HW_ACCESS_SDIO
  2044. UINT32 SrcOffset ;
  2045. UINT16 DataShort;
  2046. SrcOffset = (Addr & 0xfffffffe);
  2047. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)SrcOffset),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2048. return (EXTRACT_BYTE_FROM_WORD(DataShort, Addr));
  2049. #else /* HW_ACCESS_SDIO */
  2050. UINT32 data = 0;
  2051. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2052. return (data & 0x000000FF);
  2053. #endif /* HW_ACCESS_SDIO */
  2054. }
  2055. void whal_hwAccess_SetU08(TI_HANDLE hHwAccess, UINT32 Addr, UINT8 Val)
  2056. {
  2057. #ifdef HW_ACCESS_SDIO
  2058. UINT32 sdioAddr;
  2059. UINT16 DataShort;
  2060. sdioAddr = (Addr & 0xfffffffe);
  2061. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2062. EXTRACT_BYTE_FROM_WORD(DataShort, Addr) = Val;
  2063. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2064. #else /* HW_ACCESS_SDIO */
  2065. UINT32 data = 0;
  2066. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2067. data &= 0xFFFFFF00;
  2068. data |= Val;
  2069. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2070. #endif /* HW_ACCESS_SDIO */
  2071. }
  2072. void whal_hwAccess_ResetU08_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT8 BitsVal)
  2073. {
  2074. #ifdef HW_ACCESS_SDIO
  2075. UINT32 sdioAddr;
  2076. UINT16 DataShort;
  2077. sdioAddr = (Addr & 0xfffffffe);
  2078. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2079. EXTRACT_BYTE_FROM_WORD(DataShort, Addr) &= ~BitsVal;
  2080. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2081. #else /* HW_ACCESS_SDIO */
  2082. UINT32 data = 0;
  2083. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2084. data &= ~BitsVal;
  2085. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2086. #endif /* HW_ACCESS_SDIO */
  2087. }
  2088. /****************************************************************************
  2089. * whal_hwAccess_(Get/Set/SetBits/ResetBits)U16()
  2090. ****************************************************************************
  2091. * DESCRIPTION: wlan hardware memory access to shorts
  2092. *
  2093. * INPUTS:
  2094. *
  2095. * OUTPUT: None
  2096. *
  2097. * RETURNS: OK or NOK
  2098. ****************************************************************************/
  2099. UINT16 whal_hwAccess_GetU16(TI_HANDLE hHwAccess, UINT32 Addr)
  2100. {
  2101. #ifdef HW_ACCESS_SDIO
  2102. UINT32 sdioAddr;
  2103. UINT16 DataShort;
  2104. sdioAddr = Addr;
  2105. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT16));
  2106. return (ENDIAN_HANDLE_WORD(DataShort));
  2107. #else /* HW_ACCESS_SDIO */
  2108. UINT32 data = 0;
  2109. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2110. return (data & 0x0000FFFF);
  2111. #endif /* HW_ACCESS_SDIO */
  2112. }
  2113. void whal_hwAccess_SetU16(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
  2114. {
  2115. #ifdef HW_ACCESS_SDIO
  2116. UINT32 sdioAddr;
  2117. UINT16 sdioVal;
  2118. sdioAddr = (Addr & 0xfffffffe);
  2119. sdioVal = ENDIAN_HANDLE_WORD(Val);
  2120. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
  2121. #else /* HW_ACCESS_SDIO */
  2122. UINT32 data = 0;
  2123. UINT32 sdioAddr;
  2124. sdioAddr = (Addr & 0xfffffffc);
  2125. whal_hwAccess_ReadMem(hHwAccess,(UINT32)sdioAddr,(UINT8*)&data,sizeof(data));
  2126. if((Addr&0x3) == 2)
  2127. {
  2128. data &= 0x0000FFFF;
  2129. data |= ((UINT32)Val)<<16;
  2130. }
  2131. else
  2132. {
  2133. data &= 0xFFFF0000;
  2134. data |= Val;
  2135. }
  2136. whal_hwAccess_WriteMem(hHwAccess,(UINT32)sdioAddr,(UINT8*)&data,sizeof(data));
  2137. #endif /* HW_ACCESS_SDIO */
  2138. }
  2139. void whal_hwAccess_SetU16_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
  2140. {
  2141. #ifdef HW_ACCESS_SDIO
  2142. UINT32 sdioAddr;
  2143. UINT16 sdioVal;
  2144. sdioAddr = Addr;
  2145. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
  2146. sdioVal |= ENDIAN_HANDLE_WORD(Val);
  2147. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
  2148. #else /* HW_ACCESS_SDIO */
  2149. UINT32 data = 0;
  2150. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2151. data |= Val;
  2152. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2153. #endif /* HW_ACCESS_SDIO */
  2154. }
  2155. void whal_hwAccess_ResetU16_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT16 Val)
  2156. {
  2157. #ifdef HW_ACCESS_SDIO
  2158. UINT32 sdioAddr;
  2159. UINT16 sdioVal;
  2160. sdioAddr = Addr;
  2161. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
  2162. sdioVal &= ~ENDIAN_HANDLE_WORD(Val);
  2163. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT16));
  2164. #else /* HW_ACCESS_SDIO */
  2165. UINT32 data = 0;
  2166. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2167. data &= ~Val;
  2168. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2169. #endif /* HW_ACCESS_SDIO */
  2170. }
  2171. /****************************************************************************
  2172. * whal_hwAccess_(Get/Set/SetBits/ResetBits)U32()
  2173. ****************************************************************************
  2174. * DESCRIPTION: wlan hardware memory access to longs
  2175. *
  2176. * INPUTS:
  2177. *
  2178. * OUTPUT: None
  2179. *
  2180. * RETURNS: OK or NOK
  2181. ****************************************************************************/
  2182. UINT32 whal_hwAccess_GetU32(TI_HANDLE hHwAccess, UINT32 Addr)
  2183. {
  2184. #ifdef HW_ACCESS_SDIO
  2185. UINT32 DataLong;
  2186. UINT32 sdioAddr;
  2187. sdioAddr = Addr;
  2188. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataLong),sizeof(UINT32));
  2189. return (ENDIAN_HANDLE_LONG(DataLong));
  2190. #else /* HW_ACCESS_SDIO */
  2191. UINT32 data = 0;
  2192. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2193. return data;
  2194. #endif /* HW_ACCESS_SDIO */
  2195. }
  2196. void whal_hwAccess_SetU32(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
  2197. {
  2198. #ifdef HW_ACCESS_SDIO
  2199. UINT32 sdioAddr;
  2200. UINT32 sdioVal;
  2201. sdioAddr = Addr;
  2202. sdioVal = ENDIAN_HANDLE_WORD(Val);
  2203. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&sdioVal),sizeof(UINT32));
  2204. #else /* HW_ACCESS_SDIO */
  2205. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&Val,sizeof(Val));
  2206. #endif /* HW_ACCESS_SDIO */
  2207. }
  2208. void whal_hwAccess_SetU32_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
  2209. {
  2210. #ifdef HW_ACCESS_SDIO
  2211. UINT32 sdioAddr;
  2212. UINT32 DataShort;
  2213. sdioAddr = (Addr & 0xfffffffe);
  2214. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
  2215. DataShort |= ENDIAN_HANDLE_LONG(Val);
  2216. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
  2217. #else /* HW_ACCESS_SDIO */
  2218. UINT32 data = 0;
  2219. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2220. data |= Val;
  2221. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2222. #endif /* HW_ACCESS_SDIO */
  2223. }
  2224. void whal_hwAccess_ResetU32_Bits(TI_HANDLE hHwAccess, UINT32 Addr, UINT32 Val)
  2225. {
  2226. #ifdef HW_ACCESS_SDIO
  2227. UINT32 sdioAddr;
  2228. UINT32 DataShort;
  2229. sdioAddr = (Addr & 0xfffffffe);
  2230. whal_hwAccess_ReadMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
  2231. DataShort &= ~ENDIAN_HANDLE_LONG(Val);
  2232. whal_hwAccess_WriteMem(hHwAccess,(UINT32)((char *)sdioAddr),(UINT8*)((char *)&DataShort),sizeof(UINT32));
  2233. #else /* HW_ACCESS_SDIO */
  2234. UINT32 data = 0;
  2235. whal_hwAccess_ReadMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2236. data &= ~Val;
  2237. whal_hwAccess_WriteMem(hHwAccess,(UINT32)Addr,(UINT8*)&data,sizeof(data));
  2238. #endif /* HW_ACCESS_SDIO */
  2239. }
  2240. #endif /* USE_SYNC_API */
  2241. /****************************************************************************
  2242. * whal_hwAccess_Print()
  2243. ****************************************************************************
  2244. * DESCRIPTION: Print interrupts information
  2245. *
  2246. * INPUTS: None
  2247. *
  2248. * OUTPUT: None
  2249. *
  2250. * RETURNS:
  2251. ****************************************************************************/
  2252. void whal_hwAccess_Print(TI_HANDLE hHwAccess)
  2253. {
  2254. /* will be in use only if a print function will be neaded.
  2255. HwAccess_T_new *pHwAccess = (HwAccess_T_new*) hHwAccess;
  2256. */
  2257. WLAN_OS_REPORT(("whal_hwAccess_Print ----------------------------\n"));
  2258. WLAN_OS_REPORT((" NOTHING RIGHTNOW\n"));
  2259. }
  2260. /************************************************************************
  2261. * Internal functions
  2262. ************************************************************************/
  2263. #ifdef HW_ACCESS_SDIO
  2264. TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
  2265. {
  2266. SDIO_ConfigParams configParams;
  2267. HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
  2268. SDIO_Status status;
  2269. os_memoryZero( pHwAccess->hOs, &configParams, sizeof(SDIO_ConfigParams));
  2270. configParams.fnotify_read = sdio_transaction_notify_read;
  2271. configParams.fnotify_write = sdio_transaction_notify_write;
  2272. configParams.ferror = sdio_transaction_error;
  2273. configParams.fconfig_peripheral = SDIO_TNETWConfig;
  2274. configParams.fconvert = NULL;
  2275. configParams.owner = pHwAccess;
  2276. status = SDIO_Init(&configParams, &pHwAccess->hDriver);
  2277. return (status == SDIO_SUCCESS) ? OK : NOK;
  2278. }
  2279. #elif defined(HW_ACCESS_WSPI)
  2280. TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
  2281. {
  2282. HwAccess_T_new *pHwAccess = (HwAccess_T_new*)hHwAccess;
  2283. int status;
  2284. /* re-configure the WSPi interface, using NULL to keep old parameters */
  2285. status = WSPI_Configure (pHwAccess->hDriver , NULL, NULL, NULL);
  2286. #ifndef _WINDOWS
  2287. WSPI2TNETWIF (pHwAccess, status, 0x0);
  2288. return (TI_STATUS)status;
  2289. #else
  2290. #endif
  2291. }
  2292. #else /* ifdef HW_ACCESS_SDIO */
  2293. TI_STATUS whal_hwAccess_RecreateInterface(TI_HANDLE hHwAccess)
  2294. {
  2295. TI_STATUS status = NOK;
  2296. /*#error whal_hwAccess_RecreateInterface function is not implemented for HW interface other than SDIO.*/
  2297. return (status);
  2298. }
  2299. #endif /* ifdef HW_ACCESS_SDIO */