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/drivers/staging/rtl8192u/r819xU_phy.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 1773 lines | 1130 code | 207 blank | 436 comment | 146 complexity | b933c17582a0175e435e2dead88fd0ad MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. #include "r8192U.h"
  2. #include "r8192U_hw.h"
  3. #include "r819xU_phy.h"
  4. #include "r819xU_phyreg.h"
  5. #include "r8190_rtl8256.h"
  6. #include "r8192U_dm.h"
  7. #include "r819xU_firmware_img.h"
  8. #include "dot11d.h"
  9. static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  10. 0,
  11. 0x085c, //2412 1
  12. 0x08dc, //2417 2
  13. 0x095c, //2422 3
  14. 0x09dc, //2427 4
  15. 0x0a5c, //2432 5
  16. 0x0adc, //2437 6
  17. 0x0b5c, //2442 7
  18. 0x0bdc, //2447 8
  19. 0x0c5c, //2452 9
  20. 0x0cdc, //2457 10
  21. 0x0d5c, //2462 11
  22. 0x0ddc, //2467 12
  23. 0x0e5c, //2472 13
  24. 0x0f72, //2484
  25. };
  26. #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  27. #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  28. #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  29. #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
  30. #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  31. #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  32. #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  33. #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  34. /******************************************************************************
  35. *function: This function read BB parameters from Header file we gen,
  36. * and do register read/write
  37. * input: u32 dwBitMask //taget bit pos in the addr to be modified
  38. * output: none
  39. * return: u32 return the shift bit bit position of the mask
  40. * ****************************************************************************/
  41. u32 rtl8192_CalculateBitShift(u32 dwBitMask)
  42. {
  43. u32 i;
  44. for (i=0; i<=31; i++)
  45. {
  46. if (((dwBitMask>>i)&0x1) == 1)
  47. break;
  48. }
  49. return i;
  50. }
  51. /******************************************************************************
  52. *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
  53. * input: none
  54. * output: none
  55. * return: 0(illegal, false), 1(legal,true)
  56. * ***************************************************************************/
  57. u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
  58. {
  59. u8 ret = 1;
  60. struct r8192_priv *priv = ieee80211_priv(dev);
  61. if (priv->rf_type == RF_2T4R)
  62. ret = 0;
  63. else if (priv->rf_type == RF_1T2R)
  64. {
  65. if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  66. ret = 1;
  67. else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  68. ret = 0;
  69. }
  70. return ret;
  71. }
  72. /******************************************************************************
  73. *function: This function set specific bits to BB register
  74. * input: net_device dev
  75. * u32 dwRegAddr //target addr to be modified
  76. * u32 dwBitMask //taget bit pos in the addr to be modified
  77. * u32 dwData //value to be write
  78. * output: none
  79. * return: none
  80. * notice:
  81. * ****************************************************************************/
  82. void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
  83. {
  84. u32 OriginalValue, BitShift, NewValue;
  85. if(dwBitMask!= bMaskDWord)
  86. {//if not "double word" write
  87. OriginalValue = read_nic_dword(dev, dwRegAddr);
  88. BitShift = rtl8192_CalculateBitShift(dwBitMask);
  89. NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
  90. write_nic_dword(dev, dwRegAddr, NewValue);
  91. }else
  92. write_nic_dword(dev, dwRegAddr, dwData);
  93. return;
  94. }
  95. /******************************************************************************
  96. *function: This function reads specific bits from BB register
  97. * input: net_device dev
  98. * u32 dwRegAddr //target addr to be readback
  99. * u32 dwBitMask //taget bit pos in the addr to be readback
  100. * output: none
  101. * return: u32 Data //the readback register value
  102. * notice:
  103. * ****************************************************************************/
  104. u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
  105. {
  106. u32 Ret = 0, OriginalValue, BitShift;
  107. OriginalValue = read_nic_dword(dev, dwRegAddr);
  108. BitShift = rtl8192_CalculateBitShift(dwBitMask);
  109. Ret =(OriginalValue & dwBitMask) >> BitShift;
  110. return (Ret);
  111. }
  112. static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset );
  113. static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
  114. /******************************************************************************
  115. *function: This function read register from RF chip
  116. * input: net_device dev
  117. * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
  118. * u32 Offset //target address to be read
  119. * output: none
  120. * return: u32 readback value
  121. * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
  122. * ****************************************************************************/
  123. u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
  124. {
  125. struct r8192_priv *priv = ieee80211_priv(dev);
  126. u32 ret = 0;
  127. u32 NewOffset = 0;
  128. BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
  129. rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
  130. //make sure RF register offset is correct
  131. Offset &= 0x3f;
  132. //switch page for 8256 RF IC
  133. if (priv->rf_chip == RF_8256)
  134. {
  135. if (Offset >= 31)
  136. {
  137. priv->RfReg0Value[eRFPath] |= 0x140;
  138. //Switch to Reg_Mode2 for Reg 31-45
  139. rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
  140. //modify offset
  141. NewOffset = Offset -30;
  142. }
  143. else if (Offset >= 16)
  144. {
  145. priv->RfReg0Value[eRFPath] |= 0x100;
  146. priv->RfReg0Value[eRFPath] &= (~0x40);
  147. //Switch to Reg_Mode 1 for Reg16-30
  148. rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
  149. NewOffset = Offset - 15;
  150. }
  151. else
  152. NewOffset = Offset;
  153. }
  154. else
  155. {
  156. RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
  157. NewOffset = Offset;
  158. }
  159. //put desired read addr to LSSI control Register
  160. rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
  161. //Issue a posedge trigger
  162. //
  163. rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
  164. rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
  165. // TODO: we should not delay such a long time. Ask help from SD3
  166. msleep(1);
  167. ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
  168. // Switch back to Reg_Mode0;
  169. if(priv->rf_chip == RF_8256)
  170. {
  171. priv->RfReg0Value[eRFPath] &= 0xebf;
  172. rtl8192_setBBreg(
  173. dev,
  174. pPhyReg->rf3wireOffset,
  175. bMaskDWord,
  176. (priv->RfReg0Value[eRFPath] << 16));
  177. }
  178. return ret;
  179. }
  180. /******************************************************************************
  181. *function: This function write data to RF register
  182. * input: net_device dev
  183. * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
  184. * u32 Offset //target address to be written
  185. * u32 Data //The new register data to be written
  186. * output: none
  187. * return: none
  188. * notice: For RF8256 only.
  189. ===========================================================
  190. *Reg Mode RegCTL[1] RegCTL[0] Note
  191. * (Reg00[12]) (Reg00[10])
  192. *===========================================================
  193. *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
  194. *------------------------------------------------------------------
  195. *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
  196. *------------------------------------------------------------------
  197. * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
  198. *------------------------------------------------------------------
  199. * ****************************************************************************/
  200. void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
  201. {
  202. struct r8192_priv *priv = ieee80211_priv(dev);
  203. u32 DataAndAddr = 0, NewOffset = 0;
  204. BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
  205. Offset &= 0x3f;
  206. //spin_lock_irqsave(&priv->rf_lock, flags);
  207. // down(&priv->rf_sem);
  208. if (priv->rf_chip == RF_8256)
  209. {
  210. if (Offset >= 31)
  211. {
  212. priv->RfReg0Value[eRFPath] |= 0x140;
  213. rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
  214. NewOffset = Offset - 30;
  215. }
  216. else if (Offset >= 16)
  217. {
  218. priv->RfReg0Value[eRFPath] |= 0x100;
  219. priv->RfReg0Value[eRFPath] &= (~0x40);
  220. rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
  221. NewOffset = Offset - 15;
  222. }
  223. else
  224. NewOffset = Offset;
  225. }
  226. else
  227. {
  228. RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
  229. NewOffset = Offset;
  230. }
  231. // Put write addr in [5:0] and write data in [31:16]
  232. DataAndAddr = (Data<<16) | (NewOffset&0x3f);
  233. // Write Operation
  234. rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
  235. if(Offset==0x0)
  236. priv->RfReg0Value[eRFPath] = Data;
  237. // Switch back to Reg_Mode0;
  238. if(priv->rf_chip == RF_8256)
  239. {
  240. if(Offset != 0)
  241. {
  242. priv->RfReg0Value[eRFPath] &= 0xebf;
  243. rtl8192_setBBreg(
  244. dev,
  245. pPhyReg->rf3wireOffset,
  246. bMaskDWord,
  247. (priv->RfReg0Value[eRFPath] << 16));
  248. }
  249. }
  250. //spin_unlock_irqrestore(&priv->rf_lock, flags);
  251. // up(&priv->rf_sem);
  252. return;
  253. }
  254. /******************************************************************************
  255. *function: This function set specific bits to RF register
  256. * input: net_device dev
  257. * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
  258. * u32 RegAddr //target addr to be modified
  259. * u32 BitMask //taget bit pos in the addr to be modified
  260. * u32 Data //value to be write
  261. * output: none
  262. * return: none
  263. * notice:
  264. * ****************************************************************************/
  265. void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
  266. {
  267. struct r8192_priv *priv = ieee80211_priv(dev);
  268. u32 Original_Value, BitShift, New_Value;
  269. // u8 time = 0;
  270. if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  271. return;
  272. if (priv->Rf_Mode == RF_OP_By_FW)
  273. {
  274. if (BitMask != bMask12Bits) // RF data is 12 bits only
  275. {
  276. Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
  277. BitShift = rtl8192_CalculateBitShift(BitMask);
  278. New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift);
  279. phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
  280. }else
  281. phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
  282. udelay(200);
  283. }
  284. else
  285. {
  286. if (BitMask != bMask12Bits) // RF data is 12 bits only
  287. {
  288. Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
  289. BitShift = rtl8192_CalculateBitShift(BitMask);
  290. New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
  291. rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
  292. }else
  293. rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
  294. }
  295. return;
  296. }
  297. /******************************************************************************
  298. *function: This function reads specific bits from RF register
  299. * input: net_device dev
  300. * u32 RegAddr //target addr to be readback
  301. * u32 BitMask //taget bit pos in the addr to be readback
  302. * output: none
  303. * return: u32 Data //the readback register value
  304. * notice:
  305. * ****************************************************************************/
  306. u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
  307. {
  308. u32 Original_Value, Readback_Value, BitShift;
  309. struct r8192_priv *priv = ieee80211_priv(dev);
  310. if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  311. return 0;
  312. if (priv->Rf_Mode == RF_OP_By_FW)
  313. {
  314. Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
  315. BitShift = rtl8192_CalculateBitShift(BitMask);
  316. Readback_Value = (Original_Value & BitMask) >> BitShift;
  317. udelay(200);
  318. return (Readback_Value);
  319. }
  320. else
  321. {
  322. Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
  323. BitShift = rtl8192_CalculateBitShift(BitMask);
  324. Readback_Value = (Original_Value & BitMask) >> BitShift;
  325. return (Readback_Value);
  326. }
  327. }
  328. /******************************************************************************
  329. *function: We support firmware to execute RF-R/W.
  330. * input: dev
  331. * output: none
  332. * return: none
  333. * notice:
  334. * ***************************************************************************/
  335. static u32
  336. phy_FwRFSerialRead(
  337. struct net_device* dev,
  338. RF90_RADIO_PATH_E eRFPath,
  339. u32 Offset )
  340. {
  341. u32 retValue = 0;
  342. u32 Data = 0;
  343. u8 time = 0;
  344. //DbgPrint("FW RF CTRL\n\r");
  345. /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
  346. not execute the scheme in the initial step. Otherwise, RF-R/W will waste
  347. much time. This is only for site survey. */
  348. // 1. Read operation need not insert data. bit 0-11
  349. //Data &= bMask12Bits;
  350. // 2. Write RF register address. Bit 12-19
  351. Data |= ((Offset&0xFF)<<12);
  352. // 3. Write RF path. bit 20-21
  353. Data |= ((eRFPath&0x3)<<20);
  354. // 4. Set RF read indicator. bit 22=0
  355. //Data |= 0x00000;
  356. // 5. Trigger Fw to operate the command. bit 31
  357. Data |= 0x80000000;
  358. // 6. We can not execute read operation if bit 31 is 1.
  359. while (read_nic_dword(dev, QPNR)&0x80000000)
  360. {
  361. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
  362. if (time++ < 100)
  363. {
  364. //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
  365. udelay(10);
  366. }
  367. else
  368. break;
  369. }
  370. // 7. Execute read operation.
  371. write_nic_dword(dev, QPNR, Data);
  372. // 8. Check if firmawre send back RF content.
  373. while (read_nic_dword(dev, QPNR)&0x80000000)
  374. {
  375. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
  376. if (time++ < 100)
  377. {
  378. //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
  379. udelay(10);
  380. }
  381. else
  382. return (0);
  383. }
  384. retValue = read_nic_dword(dev, RF_DATA);
  385. return (retValue);
  386. } /* phy_FwRFSerialRead */
  387. /******************************************************************************
  388. *function: We support firmware to execute RF-R/W.
  389. * input: dev
  390. * output: none
  391. * return: none
  392. * notice:
  393. * ***************************************************************************/
  394. static void
  395. phy_FwRFSerialWrite(
  396. struct net_device* dev,
  397. RF90_RADIO_PATH_E eRFPath,
  398. u32 Offset,
  399. u32 Data )
  400. {
  401. u8 time = 0;
  402. //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
  403. /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
  404. not execute the scheme in the initial step. Otherwise, RF-R/W will waste
  405. much time. This is only for site survey. */
  406. // 1. Set driver write bit and 12 bit data. bit 0-11
  407. //Data &= bMask12Bits; // Done by uper layer.
  408. // 2. Write RF register address. bit 12-19
  409. Data |= ((Offset&0xFF)<<12);
  410. // 3. Write RF path. bit 20-21
  411. Data |= ((eRFPath&0x3)<<20);
  412. // 4. Set RF write indicator. bit 22=1
  413. Data |= 0x400000;
  414. // 5. Trigger Fw to operate the command. bit 31=1
  415. Data |= 0x80000000;
  416. // 6. Write operation. We can not write if bit 31 is 1.
  417. while (read_nic_dword(dev, QPNR)&0x80000000)
  418. {
  419. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
  420. if (time++ < 100)
  421. {
  422. //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
  423. udelay(10);
  424. }
  425. else
  426. break;
  427. }
  428. // 7. No matter check bit. We always force the write. Because FW will
  429. // not accept the command.
  430. write_nic_dword(dev, QPNR, Data);
  431. /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
  432. to finish RF write operation. */
  433. /* 2008/01/17 MH We support delay in firmware side now. */
  434. //delay_us(20);
  435. } /* phy_FwRFSerialWrite */
  436. /******************************************************************************
  437. *function: This function read BB parameters from Header file we gen,
  438. * and do register read/write
  439. * input: dev
  440. * output: none
  441. * return: none
  442. * notice: BB parameters may change all the time, so please make
  443. * sure it has been synced with the newest.
  444. * ***************************************************************************/
  445. void rtl8192_phy_configmac(struct net_device* dev)
  446. {
  447. u32 dwArrayLen = 0, i;
  448. u32* pdwArray = NULL;
  449. struct r8192_priv *priv = ieee80211_priv(dev);
  450. if(priv->btxpowerdata_readfromEEPORM)
  451. {
  452. RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
  453. dwArrayLen = MACPHY_Array_PGLength;
  454. pdwArray = rtl819XMACPHY_Array_PG;
  455. }
  456. else
  457. {
  458. RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
  459. dwArrayLen = MACPHY_ArrayLength;
  460. pdwArray = rtl819XMACPHY_Array;
  461. }
  462. for(i = 0; i<dwArrayLen; i=i+3){
  463. if(pdwArray[i] == 0x318)
  464. {
  465. pdwArray[i+2] = 0x00000800;
  466. //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
  467. // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
  468. }
  469. RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
  470. pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
  471. rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
  472. }
  473. return;
  474. }
  475. /******************************************************************************
  476. *function: This function do dirty work
  477. * input: dev
  478. * output: none
  479. * return: none
  480. * notice: BB parameters may change all the time, so please make
  481. * sure it has been synced with the newest.
  482. * ***************************************************************************/
  483. void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
  484. {
  485. u32 i;
  486. #ifdef TO_DO_LIST
  487. u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
  488. if(Adapter->bInHctTest)
  489. {
  490. PHY_REGArrayLen = PHY_REGArrayLengthDTM;
  491. AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
  492. Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
  493. Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
  494. }
  495. #endif
  496. if (ConfigType == BaseBand_Config_PHY_REG)
  497. {
  498. for (i=0; i<PHY_REG_1T2RArrayLength; i+=2)
  499. {
  500. rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]);
  501. RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]);
  502. }
  503. }
  504. else if (ConfigType == BaseBand_Config_AGC_TAB)
  505. {
  506. for (i=0; i<AGCTAB_ArrayLength; i+=2)
  507. {
  508. rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]);
  509. RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]);
  510. }
  511. }
  512. return;
  513. }
  514. /******************************************************************************
  515. *function: This function initialize Register definition offset for Radio Path
  516. * A/B/C/D
  517. * input: net_device dev
  518. * output: none
  519. * return: none
  520. * notice: Initialization value here is constant and it should never be changed
  521. * ***************************************************************************/
  522. void rtl8192_InitBBRFRegDef(struct net_device* dev)
  523. {
  524. struct r8192_priv *priv = ieee80211_priv(dev);
  525. // RF Interface Sowrtware Control
  526. priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
  527. priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
  528. priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
  529. priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
  530. // RF Interface Readback Value
  531. priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
  532. priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
  533. priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
  534. priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
  535. // RF Interface Output (and Enable)
  536. priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
  537. priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
  538. priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
  539. priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
  540. // RF Interface (Output and) Enable
  541. priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
  542. priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
  543. priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
  544. priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
  545. //Addr of LSSI. Wirte RF register by driver
  546. priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
  547. priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
  548. priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
  549. priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
  550. // RF parameter
  551. priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
  552. priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
  553. priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
  554. priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
  555. // Tx AGC Gain Stage (same for all path. Should we remove this?)
  556. priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
  557. priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
  558. priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
  559. priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
  560. // Tranceiver A~D HSSI Parameter-1
  561. priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
  562. priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
  563. priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
  564. priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
  565. // Tranceiver A~D HSSI Parameter-2
  566. priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
  567. priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
  568. priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
  569. priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
  570. // RF switch Control
  571. priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
  572. priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
  573. priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
  574. priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
  575. // AGC control 1
  576. priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
  577. priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
  578. priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
  579. priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
  580. // AGC control 2
  581. priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
  582. priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
  583. priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
  584. priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
  585. // RX AFE control 1
  586. priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
  587. priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
  588. priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
  589. priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
  590. // RX AFE control 1
  591. priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
  592. priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
  593. priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
  594. priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
  595. // Tx AFE control 1
  596. priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
  597. priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
  598. priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
  599. priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
  600. // Tx AFE control 2
  601. priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
  602. priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
  603. priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
  604. priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
  605. // Tranceiver LSSI Readback
  606. priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
  607. priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
  608. priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
  609. priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
  610. }
  611. /******************************************************************************
  612. *function: This function is to write register and then readback to make sure whether BB and RF is OK
  613. * input: net_device dev
  614. * HW90_BLOCK_E CheckBlock
  615. * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
  616. * output: none
  617. * return: return whether BB and RF is ok(0:OK; 1:Fail)
  618. * notice: This function may be removed in the ASIC
  619. * ***************************************************************************/
  620. u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
  621. {
  622. // struct r8192_priv *priv = ieee80211_priv(dev);
  623. // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
  624. u8 ret = 0;
  625. u32 i, CheckTimes = 4, dwRegRead = 0;
  626. u32 WriteAddr[4];
  627. u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
  628. // Initialize register address offset to be checked
  629. WriteAddr[HW90_BLOCK_MAC] = 0x100;
  630. WriteAddr[HW90_BLOCK_PHY0] = 0x900;
  631. WriteAddr[HW90_BLOCK_PHY1] = 0x800;
  632. WriteAddr[HW90_BLOCK_RF] = 0x3;
  633. RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
  634. for(i=0 ; i < CheckTimes ; i++)
  635. {
  636. //
  637. // Write Data to register and readback
  638. //
  639. switch(CheckBlock)
  640. {
  641. case HW90_BLOCK_MAC:
  642. RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
  643. break;
  644. case HW90_BLOCK_PHY0:
  645. case HW90_BLOCK_PHY1:
  646. write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
  647. dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
  648. break;
  649. case HW90_BLOCK_RF:
  650. WriteData[i] &= 0xfff;
  651. rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
  652. // TODO: we should not delay for such a long time. Ask SD3
  653. msleep(1);
  654. dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
  655. msleep(1);
  656. break;
  657. default:
  658. ret = 1;
  659. break;
  660. }
  661. //
  662. // Check whether readback data is correct
  663. //
  664. if(dwRegRead != WriteData[i])
  665. {
  666. RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
  667. ret = 1;
  668. break;
  669. }
  670. }
  671. return ret;
  672. }
  673. /******************************************************************************
  674. *function: This function initialize BB&RF
  675. * input: net_device dev
  676. * output: none
  677. * return: none
  678. * notice: Initialization value may change all the time, so please make
  679. * sure it has been synced with the newest.
  680. * ***************************************************************************/
  681. void rtl8192_BB_Config_ParaFile(struct net_device* dev)
  682. {
  683. struct r8192_priv *priv = ieee80211_priv(dev);
  684. u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0;
  685. u32 dwRegValue = 0;
  686. /**************************************
  687. //<1>Initialize BaseBand
  688. **************************************/
  689. /*--set BB Global Reset--*/
  690. bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
  691. write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
  692. mdelay(50);
  693. /*---set BB reset Active---*/
  694. dwRegValue = read_nic_dword(dev, CPU_GEN);
  695. write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
  696. /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
  697. // TODO: this function should be removed on ASIC , Emily 2007.2.2
  698. for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
  699. {
  700. rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
  701. if(rtStatus != 0)
  702. {
  703. RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
  704. return ;
  705. }
  706. }
  707. /*---- Set CCK and OFDM Block "OFF"----*/
  708. rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
  709. /*----BB Register Initilazation----*/
  710. //==m==>Set PHY REG From Header<==m==
  711. rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
  712. /*----Set BB reset de-Active----*/
  713. dwRegValue = read_nic_dword(dev, CPU_GEN);
  714. write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
  715. /*----BB AGC table Initialization----*/
  716. //==m==>Set PHY REG From Header<==m==
  717. rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
  718. /*----Enable XSTAL ----*/
  719. write_nic_byte_E(dev, 0x5e, 0x00);
  720. if (priv->card_8192_version == (u8)VERSION_819xU_A)
  721. {
  722. //Antenna gain offset from B/C/D to A
  723. dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
  724. rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue);
  725. //XSTALLCap
  726. dwRegValue = priv->CrystalCap & 0xf;
  727. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue);
  728. }
  729. // Check if the CCK HighPower is turned ON.
  730. // This is used to calculate PWDB.
  731. priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
  732. return;
  733. }
  734. /******************************************************************************
  735. *function: This function initialize BB&RF
  736. * input: net_device dev
  737. * output: none
  738. * return: none
  739. * notice: Initialization value may change all the time, so please make
  740. * sure it has been synced with the newest.
  741. * ***************************************************************************/
  742. void rtl8192_BBConfig(struct net_device* dev)
  743. {
  744. rtl8192_InitBBRFRegDef(dev);
  745. //config BB&RF. As hardCode based initialization has not been well
  746. //implemented, so use file first.FIXME:should implement it for hardcode?
  747. rtl8192_BB_Config_ParaFile(dev);
  748. return;
  749. }
  750. /******************************************************************************
  751. *function: This function obtains the initialization value of Tx power Level offset
  752. * input: net_device dev
  753. * output: none
  754. * return: none
  755. * ***************************************************************************/
  756. void rtl8192_phy_getTxPower(struct net_device* dev)
  757. {
  758. struct r8192_priv *priv = ieee80211_priv(dev);
  759. priv->MCSTxPowerLevelOriginalOffset[0] =
  760. read_nic_dword(dev, rTxAGC_Rate18_06);
  761. priv->MCSTxPowerLevelOriginalOffset[1] =
  762. read_nic_dword(dev, rTxAGC_Rate54_24);
  763. priv->MCSTxPowerLevelOriginalOffset[2] =
  764. read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
  765. priv->MCSTxPowerLevelOriginalOffset[3] =
  766. read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
  767. priv->MCSTxPowerLevelOriginalOffset[4] =
  768. read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
  769. priv->MCSTxPowerLevelOriginalOffset[5] =
  770. read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
  771. // read rx initial gain
  772. priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
  773. priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
  774. priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
  775. priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
  776. RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
  777. priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
  778. priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
  779. // read framesync
  780. priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
  781. priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2);
  782. RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
  783. rOFDM0_RxDetector3, priv->framesync);
  784. // read SIFS (save the value read fome MACPHY_REG.txt)
  785. priv->SifsTime = read_nic_word(dev, SIFS);
  786. return;
  787. }
  788. /******************************************************************************
  789. *function: This function obtains the initialization value of Tx power Level offset
  790. * input: net_device dev
  791. * output: none
  792. * return: none
  793. * ***************************************************************************/
  794. void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
  795. {
  796. struct r8192_priv *priv = ieee80211_priv(dev);
  797. u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
  798. u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
  799. switch(priv->rf_chip)
  800. {
  801. case RF_8256:
  802. PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
  803. PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
  804. break;
  805. default:
  806. // case RF_8225:
  807. // case RF_8258:
  808. RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__);
  809. break;
  810. }
  811. return;
  812. }
  813. /******************************************************************************
  814. *function: This function check Rf chip to do RF config
  815. * input: net_device dev
  816. * output: none
  817. * return: only 8256 is supported
  818. * ***************************************************************************/
  819. void rtl8192_phy_RFConfig(struct net_device* dev)
  820. {
  821. struct r8192_priv *priv = ieee80211_priv(dev);
  822. switch(priv->rf_chip)
  823. {
  824. case RF_8256:
  825. PHY_RF8256_Config(dev);
  826. break;
  827. // case RF_8225:
  828. // case RF_8258:
  829. default:
  830. RT_TRACE(COMP_ERR, "error chip id\n");
  831. break;
  832. }
  833. return;
  834. }
  835. /******************************************************************************
  836. *function: This function update Initial gain
  837. * input: net_device dev
  838. * output: none
  839. * return: As Windows has not implemented this, wait for complement
  840. * ***************************************************************************/
  841. void rtl8192_phy_updateInitGain(struct net_device* dev)
  842. {
  843. return;
  844. }
  845. /******************************************************************************
  846. *function: This function read RF parameters from general head file, and do RF 3-wire
  847. * input: net_device dev
  848. * output: none
  849. * return: return code show if RF configuration is successful(0:pass, 1:fail)
  850. * Note: Delay may be required for RF configuration
  851. * ***************************************************************************/
  852. u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
  853. {
  854. int i;
  855. //u32* pRFArray;
  856. u8 ret = 0;
  857. switch(eRFPath){
  858. case RF90_PATH_A:
  859. for(i = 0;i<RadioA_ArrayLength; i=i+2){
  860. if(rtl819XRadioA_Array[i] == 0xfe){
  861. mdelay(100);
  862. continue;
  863. }
  864. rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]);
  865. mdelay(1);
  866. }
  867. break;
  868. case RF90_PATH_B:
  869. for(i = 0;i<RadioB_ArrayLength; i=i+2){
  870. if(rtl819XRadioB_Array[i] == 0xfe){
  871. mdelay(100);
  872. continue;
  873. }
  874. rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]);
  875. mdelay(1);
  876. }
  877. break;
  878. case RF90_PATH_C:
  879. for(i = 0;i<RadioC_ArrayLength; i=i+2){
  880. if(rtl819XRadioC_Array[i] == 0xfe){
  881. mdelay(100);
  882. continue;
  883. }
  884. rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]);
  885. mdelay(1);
  886. }
  887. break;
  888. case RF90_PATH_D:
  889. for(i = 0;i<RadioD_ArrayLength; i=i+2){
  890. if(rtl819XRadioD_Array[i] == 0xfe){
  891. mdelay(100);
  892. continue;
  893. }
  894. rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]);
  895. mdelay(1);
  896. }
  897. break;
  898. default:
  899. break;
  900. }
  901. return ret;
  902. }
  903. /******************************************************************************
  904. *function: This function set Tx Power of the channel
  905. * input: struct net_device *dev
  906. * u8 channel
  907. * output: none
  908. * return: none
  909. * Note:
  910. * ***************************************************************************/
  911. void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
  912. {
  913. struct r8192_priv *priv = ieee80211_priv(dev);
  914. u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
  915. u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
  916. switch(priv->rf_chip)
  917. {
  918. case RF_8225:
  919. #ifdef TO_DO_LIST
  920. PHY_SetRF8225CckTxPower(Adapter, powerlevel);
  921. PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
  922. #endif
  923. break;
  924. case RF_8256:
  925. PHY_SetRF8256CCKTxPower(dev, powerlevel);
  926. PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
  927. break;
  928. case RF_8258:
  929. break;
  930. default:
  931. RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
  932. break;
  933. }
  934. return;
  935. }
  936. /******************************************************************************
  937. *function: This function set RF state on or off
  938. * input: struct net_device *dev
  939. * RT_RF_POWER_STATE eRFPowerState //Power State to set
  940. * output: none
  941. * return: none
  942. * Note:
  943. * ***************************************************************************/
  944. bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
  945. {
  946. bool bResult = true;
  947. // u8 eRFPath;
  948. struct r8192_priv *priv = ieee80211_priv(dev);
  949. if(eRFPowerState == priv->ieee80211->eRFPowerState)
  950. return false;
  951. if(priv->SetRFPowerStateInProgress == true)
  952. return false;
  953. priv->SetRFPowerStateInProgress = true;
  954. switch(priv->rf_chip)
  955. {
  956. case RF_8256:
  957. switch( eRFPowerState )
  958. {
  959. case eRfOn:
  960. //RF-A, RF-B
  961. //enable RF-Chip A/B
  962. rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
  963. //analog to digital on
  964. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
  965. //digital to analog on
  966. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
  967. //rx antenna on
  968. rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
  969. //rx antenna on
  970. rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
  971. //analog to digital part2 on
  972. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
  973. break;
  974. case eRfSleep:
  975. break;
  976. case eRfOff:
  977. //RF-A, RF-B
  978. //disable RF-Chip A/B
  979. rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4]
  980. //analog to digital off, for power save
  981. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
  982. //digital to analog off, for power save
  983. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
  984. //rx antenna off
  985. rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
  986. //rx antenna off
  987. rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
  988. //analog to digital part2 off, for power save
  989. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
  990. break;
  991. default:
  992. bResult = false;
  993. RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState);
  994. break;
  995. }
  996. break;
  997. default:
  998. RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
  999. break;
  1000. }
  1001. #ifdef TO_DO_LIST
  1002. if(bResult)
  1003. {
  1004. // Update current RF state variable.
  1005. pHalData->eRFPowerState = eRFPowerState;
  1006. switch(pHalData->RFChipID )
  1007. {
  1008. case RF_8256:
  1009. switch(pHalData->eRFPowerState)
  1010. {
  1011. case eRfOff:
  1012. //
  1013. //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
  1014. //
  1015. if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
  1016. {
  1017. Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
  1018. }
  1019. else
  1020. {
  1021. // Turn off LED if RF is not ON.
  1022. Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
  1023. }
  1024. break;
  1025. case eRfOn:
  1026. // Turn on RF we are still linked, which might happen when
  1027. // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
  1028. if( pMgntInfo->bMediaConnect == TRUE )
  1029. {
  1030. Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
  1031. }
  1032. else
  1033. {
  1034. // Turn off LED if RF is not ON.
  1035. Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
  1036. }
  1037. break;
  1038. default:
  1039. // do nothing.
  1040. break;
  1041. }// Switch RF state
  1042. break;
  1043. default:
  1044. RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n"));
  1045. break;
  1046. }
  1047. }
  1048. #endif
  1049. priv->SetRFPowerStateInProgress = false;
  1050. return bResult;
  1051. }
  1052. /****************************************************************************************
  1053. *function: This function set command table variable(struct SwChnlCmd).
  1054. * input: SwChnlCmd* CmdTable //table to be set.
  1055. * u32 CmdTableIdx //variable index in table to be set
  1056. * u32 CmdTableSz //table size.
  1057. * SwChnlCmdID CmdID //command ID to set.
  1058. * u32 Para1
  1059. * u32 Para2
  1060. * u32 msDelay
  1061. * output:
  1062. * return: true if finished, false otherwise
  1063. * Note:
  1064. * ************************************************************************************/
  1065. u8 rtl8192_phy_SetSwChnlCmdArray(
  1066. SwChnlCmd* CmdTable,
  1067. u32 CmdTableIdx,
  1068. u32 CmdTableSz,
  1069. SwChnlCmdID CmdID,
  1070. u32 Para1,
  1071. u32 Para2,
  1072. u32 msDelay
  1073. )
  1074. {
  1075. SwChnlCmd* pCmd;
  1076. if(CmdTable == NULL)
  1077. {
  1078. RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
  1079. return false;
  1080. }
  1081. if(CmdTableIdx >= CmdTableSz)
  1082. {
  1083. RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
  1084. CmdTableIdx, CmdTableSz);
  1085. return false;
  1086. }
  1087. pCmd = CmdTable + CmdTableIdx;
  1088. pCmd->CmdID = CmdID;
  1089. pCmd->Para1 = Para1;
  1090. pCmd->Para2 = Para2;
  1091. pCmd->msDelay = msDelay;
  1092. return true;
  1093. }
  1094. /******************************************************************************
  1095. *function: This function set channel step by step
  1096. * input: struct net_device *dev
  1097. * u8 channel
  1098. * u8* stage //3 stages
  1099. * u8* step //
  1100. * u32* delay //whether need to delay
  1101. * output: store new stage, step and delay for next step(combine with function above)
  1102. * return: true if finished, false otherwise
  1103. * Note: Wait for simpler function to replace it //wb
  1104. * ***************************************************************************/
  1105. u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
  1106. {
  1107. struct r8192_priv *priv = ieee80211_priv(dev);
  1108. // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
  1109. SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
  1110. u32 PreCommonCmdCnt;
  1111. SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
  1112. u32 PostCommonCmdCnt;
  1113. SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
  1114. u32 RfDependCmdCnt;
  1115. SwChnlCmd *CurrentCmd = NULL;
  1116. //RF90_RADIO_PATH_E eRFPath;
  1117. u8 eRFPath;
  1118. // u32 RfRetVal;
  1119. // u8 RetryCnt;
  1120. RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
  1121. // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
  1122. if (!IsLegalChannel(priv->ieee80211, channel))
  1123. {
  1124. RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
  1125. return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
  1126. }
  1127. //FIXME:need to check whether channel is legal or not here.WB
  1128. //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
  1129. // for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
  1130. // {
  1131. // if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  1132. // continue;
  1133. // <1> Fill up pre common command.
  1134. PreCommonCmdCnt = 0;
  1135. rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
  1136. CmdID_SetTxPowerLevel, 0, 0, 0);
  1137. rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
  1138. CmdID_End, 0, 0, 0);
  1139. // <2> Fill up post common command.
  1140. PostCommonCmdCnt = 0;
  1141. rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
  1142. CmdID_End, 0, 0, 0);
  1143. // <3> Fill up RF dependent command.
  1144. RfDependCmdCnt = 0;
  1145. switch( priv->rf_chip )
  1146. {
  1147. case RF_8225:
  1148. if (!(channel >= 1 && channel <= 14))
  1149. {
  1150. RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
  1151. return true;
  1152. }
  1153. rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
  1154. CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
  1155. rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
  1156. CmdID_End, 0, 0, 0);
  1157. break;
  1158. case RF_8256:
  1159. // TEST!! This is not the table for 8256!!
  1160. if (!(channel >= 1 && channel <= 14))
  1161. {
  1162. RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
  1163. return true;
  1164. }
  1165. rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
  1166. CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
  1167. rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
  1168. CmdID_End, 0, 0, 0);
  1169. break;
  1170. case RF_8258:
  1171. break;
  1172. default:
  1173. RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
  1174. return true;
  1175. break;
  1176. }
  1177. do{
  1178. switch(*stage)
  1179. {
  1180. case 0:
  1181. CurrentCmd=&PreCommonCmd[*step];
  1182. break;
  1183. case 1:
  1184. CurrentCmd=&RfDependCmd[*step];
  1185. break;
  1186. case 2:
  1187. CurrentCmd=&PostCommonCmd[*step];
  1188. break;
  1189. }
  1190. if(CurrentCmd->CmdID==CmdID_End)
  1191. {
  1192. if((*stage)==2)
  1193. {
  1194. (*delay)=CurrentCmd->msDelay;
  1195. return true;
  1196. }
  1197. else
  1198. {
  1199. (*stage)++;
  1200. (*step)=0;
  1201. continue;
  1202. }
  1203. }
  1204. switch(CurrentCmd->CmdID)
  1205. {
  1206. case CmdID_SetTxPowerLevel:
  1207. if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
  1208. rtl8192_SetTxPowerLevel(dev,channel);
  1209. break;
  1210. case CmdID_WritePortUlong:
  1211. write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
  1212. break;
  1213. case CmdID_WritePortUshort:
  1214. write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
  1215. break;
  1216. case CmdID_WritePortUchar:
  1217. write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
  1218. break;
  1219. case CmdID_RF_WriteReg:
  1220. for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++)
  1221. {
  1222. rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
  1223. }
  1224. break;
  1225. default:
  1226. break;
  1227. }
  1228. break;
  1229. }while(true);
  1230. // }/*for(Number of RF paths)*/
  1231. (*delay)=CurrentCmd->msDelay;
  1232. (*step)++;
  1233. return false;
  1234. }
  1235. /******************************************************************************
  1236. *function: This function does acturally set channel work
  1237. * input: struct net_device *dev
  1238. * u8 channel
  1239. * output: none
  1240. * return: noin
  1241. * Note: We should not call this function directly
  1242. * ***************************************************************************/
  1243. void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
  1244. {
  1245. struct r8192_priv *priv = ieee80211_priv(dev);
  1246. u32 delay = 0;
  1247. while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
  1248. {
  1249. // if(delay>0)
  1250. // msleep(delay);//or mdelay? need further consideration
  1251. if(!priv->up)
  1252. break;
  1253. }
  1254. }
  1255. /******************************************************************************
  1256. *function: Callback routine of the work item for switch channel.
  1257. * input:
  1258. *
  1259. * output: none
  1260. * return: noin
  1261. * ***************************************************************************/
  1262. void rtl8192_SwChnl_WorkItem(struct net_device *dev)
  1263. {
  1264. struct r8192_priv *priv = ieee80211_priv(dev);
  1265. RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan);
  1266. rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
  1267. RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
  1268. }
  1269. /******************************************************************************
  1270. *function: This function scheduled actural workitem to set channel
  1271. * input: net_device dev
  1272. * u8 channel //channel to set
  1273. * output: none
  1274. * return: return code show if workitem is scheduled(1:pass, 0:fail)
  1275. * Note: Delay may be required for RF configuration
  1276. * ***************************************************************************/
  1277. u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
  1278. {
  1279. struct r8192_priv *priv = ieee80211_priv(dev);
  1280. RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress);
  1281. if(!priv->up)
  1282. return false;
  1283. if(priv->SwChnlInProgress)
  1284. return false;
  1285. // if(pHalData->SetBWModeInProgress)
  1286. // return;
  1287. if (0) //to test current channel from RF reg 0x7.
  1288. {
  1289. u8 eRFPath;
  1290. for(eRFPath = 0; eRFPath < 2; eRFPath++){
  1291. printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum));
  1292. udelay(10);
  1293. }
  1294. }
  1295. //--------------------------------------------
  1296. switch(priv->ieee80211->mode)
  1297. {
  1298. case WIRELESS_MODE_A:
  1299. case WIRELESS_MODE_N_5G:
  1300. if (channel<=14){
  1301. RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
  1302. return false;
  1303. }
  1304. break;
  1305. case WIRELESS_MODE_B:
  1306. if (channel>14){
  1307. RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
  1308. return false;
  1309. }
  1310. break;
  1311. case WIRELESS_MODE_G:
  1312. case WIRELESS_MODE_N_24G:
  1313. if (channel>14){
  1314. RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
  1315. return false;
  1316. }
  1317. break;
  1318. }
  1319. //--------------------------------------------
  1320. priv->SwChnlInProgress = true;
  1321. if(channel == 0)
  1322. channel = 1;
  1323. priv->chan=channel;
  1324. priv->SwChnlStage=0;
  1325. priv->SwChnlStep=0;
  1326. // schedule_work(&(priv->SwChnlWorkItem));
  1327. // rtl8192_SwChnl_WorkItem(dev);
  1328. if(priv->up) {
  1329. // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
  1330. rtl8192_SwChnl_WorkItem(dev);
  1331. }
  1332. priv->SwChnlInProgress = false;
  1333. return true;
  1334. }
  1335. //
  1336. /******************************************************************************
  1337. *function: Callback routine of the work item for set bandwidth mode.
  1338. * input: struct net_device *dev
  1339. * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
  1340. * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
  1341. * output: none
  1342. * return: none
  1343. * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
  1344. * test whether current work in the queue or not.//do I?
  1345. * ***************************************************************************/
  1346. void rtl8192_SetBWModeWorkItem(struct net_device *dev)
  1347. {
  1348. struct r8192_priv *priv = ieee80211_priv(dev);
  1349. u8 regBwOpMode;
  1350. RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
  1351. priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
  1352. if(priv->rf_chip == RF_PSEUDO_11N)
  1353. {
  1354. priv->SetBWModeInProgress= false;
  1355. return;
  1356. }
  1357. //<1>Set MAC register
  1358. regBwOpMode = read_nic_byte(dev, BW_OPMODE);
  1359. switch(priv->CurrentChannelBW)
  1360. {
  1361. case HT_CHANNEL_WIDTH_20:
  1362. regBwOpMode |= BW_OPMODE_20MHZ;
  1363. // 2007/02/07 Mark by Emily because we have not verify whether this register works
  1364. write_nic_byte(dev, BW_OPMODE, regBwOpMode);
  1365. break;
  1366. case HT_CHANNEL_WIDTH_20_40:
  1367. regBwOpMode &= ~BW_OPMODE_20MHZ;
  1368. // 2007/02/07 Mark by Emily because we have not verify whether this register works
  1369. write_nic_byte(dev, BW_OPMODE, regBwOpMode);
  1370. break;
  1371. default:
  1372. RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
  1373. break;
  1374. }
  1375. //<2>Set PHY related register
  1376. switch(priv->CurrentChannelBW)
  1377. {
  1378. case HT_CHANNEL_WIDTH_20:
  1379. // Add by Vivi 20071119
  1380. rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
  1381. rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
  1382. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
  1383. // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
  1384. priv->cck_present_attentuation =
  1385. priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
  1386. if(priv->cck_present_attentuation > 22)
  1387. priv->cck_present_attentuation= 22;
  1388. if(priv->cck_present_attentuation< 0)
  1389. priv->cck_present_attentuation = 0;
  1390. RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
  1391. if(priv->chan == 14 && !priv->bcck_in_ch14)
  1392. {
  1393. priv->bcck_in_ch14 = TRUE;
  1394. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1395. }
  1396. else if(priv->chan != 14 && priv->bcck_in_ch14)
  1397. {
  1398. priv->bcck_in_ch14 = FALSE;
  1399. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1400. }
  1401. else
  1402. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1403. break;
  1404. case HT_CHANNEL_WIDTH_20_40:
  1405. // Add by Vivi 20071119
  1406. rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
  1407. rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
  1408. rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
  1409. rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
  1410. rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
  1411. priv->cck_present_attentuation =
  1412. priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
  1413. if(priv->cck_present_attentuation > 22)
  1414. priv->cck_present_attentuation = 22;
  1415. if(priv->cck_present_attentuation < 0)
  1416. priv->cck_present_attentuation = 0;
  1417. RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation);
  1418. if(priv->chan == 14 && !priv->bcck_in_ch14)
  1419. {
  1420. priv->bcck_in_ch14 = true;
  1421. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1422. }
  1423. else if(priv->chan!= 14 && priv->bcck_in_ch14)
  1424. {
  1425. priv->bcck_in_ch14 = false;
  1426. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1427. }
  1428. else
  1429. dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
  1430. break;
  1431. default:
  1432. RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
  1433. break;
  1434. }
  1435. //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
  1436. //<3>Set RF related register
  1437. switch( priv->rf_chip )
  1438. {
  1439. case RF_8225:
  1440. #ifdef TO_DO_LIST
  1441. PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
  1442. #endif
  1443. break;
  1444. case RF_8256:
  1445. PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
  1446. break;
  1447. case RF_8258:
  1448. // PHY_SetRF8258Bandwidth();
  1449. break;
  1450. case RF_PSEUDO_11N:
  1451. // Do Nothing
  1452. break;
  1453. default:
  1454. RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
  1455. break;
  1456. }
  1457. priv->SetBWModeInProgress= false;
  1458. RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) );
  1459. }
  1460. /******************************************************************************
  1461. *function: This function schedules bandwidth switch work.
  1462. * input: struct net_device *dev
  1463. * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
  1464. * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
  1465. * output: none
  1466. * return: none
  1467. * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
  1468. * test whether current work in the queue or not.//do I?
  1469. * ***************************************************************************/
  1470. void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
  1471. {
  1472. struct r8192_priv *priv = ieee80211_priv(dev);
  1473. if(priv->SetBWModeInProgress)
  1474. return;
  1475. priv->SetBWModeInProgress= true;
  1476. priv->CurrentChannelBW = Bandwidth;
  1477. if(Offset==HT_EXTCHNL_OFFSET_LOWER)
  1478. priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
  1479. else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
  1480. priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
  1481. else
  1482. priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
  1483. //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
  1484. // schedule_work(&(priv->SetBWModeWorkItem));
  1485. rtl8192_SetBWModeWorkItem(dev);
  1486. }
  1487. void InitialGain819xUsb(struct net_device *dev, u8 Operation)
  1488. {
  1489. struct r8192_priv *priv = ieee80211_priv(dev);
  1490. priv->InitialGainOperateType = Operation;
  1491. if(priv->up)
  1492. {
  1493. queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
  1494. }
  1495. }
  1496. extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
  1497. {
  1498. struct delayed_work *dwork = container_of(work,struct delayed_work,work);
  1499. struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
  1500. struct net_device *dev = priv->ieee80211->dev;
  1501. #define SCAN_RX_INITIAL_GAIN 0x17
  1502. #define POWER_DETECTION_TH 0x08
  1503. u32 BitMask;
  1504. u8 initial_gain;
  1505. u8 Operation;
  1506. Operation = priv->InitialGainOperateType;
  1507. switch(Operation)
  1508. {
  1509. case IG_Backup:
  1510. RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
  1511. initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
  1512. BitMask = bMaskByte0;
  1513. if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
  1514. rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
  1515. priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
  1516. priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
  1517. priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
  1518. priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
  1519. BitMask = bMaskByte2;
  1520. priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
  1521. RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
  1522. RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
  1523. RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
  1524. RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
  1525. RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
  1526. RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
  1527. write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
  1528. write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
  1529. write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
  1530. write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
  1531. RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
  1532. write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
  1533. break;
  1534. case IG_Restore:
  1535. RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
  1536. BitMask = 0x7f; //Bit0~ Bit6
  1537. if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
  1538. rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
  1539. rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
  1540. rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
  1541. rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
  1542. rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
  1543. BitMask = bMaskByte2;
  1544. rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
  1545. RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
  1546. RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
  1547. RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
  1548. RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
  1549. RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
  1550. #ifdef RTL8190P
  1551. SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
  1552. #endif
  1553. #ifdef RTL8192E
  1554. SetTxPowerLevel8190(Adapter,priv->CurrentChannel);
  1555. #endif
  1556. //#ifdef RTL8192U
  1557. rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
  1558. //#endif
  1559. if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
  1560. rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
  1561. break;
  1562. default:
  1563. RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
  1564. break;
  1565. }
  1566. }