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/drivers/net/forcedeth.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 6010 lines | 4811 code | 707 blank | 492 comment | 928 complexity | 70cf9487e9803ef5670962268cc00f5c MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
  3. *
  4. * Note: This driver is a cleanroom reimplementation based on reverse
  5. * engineered documentation written by Carl-Daniel Hailfinger
  6. * and Andrew de Quincey.
  7. *
  8. * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  9. * trademarks of NVIDIA Corporation in the United States and other
  10. * countries.
  11. *
  12. * Copyright (C) 2003,4,5 Manfred Spraul
  13. * Copyright (C) 2004 Andrew de Quincey (wol support)
  14. * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15. * IRQ rate fixes, bigendian fixes, cleanups, verification)
  16. * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. * Known bugs:
  33. * We suspect that on some hardware no TX done interrupts are generated.
  34. * This means recovery from netif_stop_queue only happens if the hw timer
  35. * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36. * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37. * If your hardware reliably generates tx done interrupts, then you can remove
  38. * DEV_NEED_TIMERIRQ from the driver_data flags.
  39. * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40. * superfluous timer interrupts from the nic.
  41. */
  42. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43. #define FORCEDETH_VERSION "0.64"
  44. #define DRV_NAME "forcedeth"
  45. #include <linux/module.h>
  46. #include <linux/types.h>
  47. #include <linux/pci.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/netdevice.h>
  50. #include <linux/etherdevice.h>
  51. #include <linux/delay.h>
  52. #include <linux/sched.h>
  53. #include <linux/spinlock.h>
  54. #include <linux/ethtool.h>
  55. #include <linux/timer.h>
  56. #include <linux/skbuff.h>
  57. #include <linux/mii.h>
  58. #include <linux/random.h>
  59. #include <linux/init.h>
  60. #include <linux/if_vlan.h>
  61. #include <linux/dma-mapping.h>
  62. #include <linux/slab.h>
  63. #include <linux/uaccess.h>
  64. #include <linux/prefetch.h>
  65. #include <linux/io.h>
  66. #include <asm/irq.h>
  67. #include <asm/system.h>
  68. #define TX_WORK_PER_LOOP 64
  69. #define RX_WORK_PER_LOOP 64
  70. /*
  71. * Hardware access:
  72. */
  73. #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
  74. #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
  75. #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
  76. #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
  77. #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
  78. #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
  79. #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
  80. #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
  81. #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
  82. #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
  83. #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
  84. #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
  85. #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
  86. #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
  87. #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
  88. #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
  89. #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
  90. #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
  91. #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
  92. #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
  93. #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
  94. #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
  95. #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
  96. #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
  97. #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
  98. #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
  99. #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
  100. enum {
  101. NvRegIrqStatus = 0x000,
  102. #define NVREG_IRQSTAT_MIIEVENT 0x040
  103. #define NVREG_IRQSTAT_MASK 0x83ff
  104. NvRegIrqMask = 0x004,
  105. #define NVREG_IRQ_RX_ERROR 0x0001
  106. #define NVREG_IRQ_RX 0x0002
  107. #define NVREG_IRQ_RX_NOBUF 0x0004
  108. #define NVREG_IRQ_TX_ERR 0x0008
  109. #define NVREG_IRQ_TX_OK 0x0010
  110. #define NVREG_IRQ_TIMER 0x0020
  111. #define NVREG_IRQ_LINK 0x0040
  112. #define NVREG_IRQ_RX_FORCED 0x0080
  113. #define NVREG_IRQ_TX_FORCED 0x0100
  114. #define NVREG_IRQ_RECOVER_ERROR 0x8200
  115. #define NVREG_IRQMASK_THROUGHPUT 0x00df
  116. #define NVREG_IRQMASK_CPU 0x0060
  117. #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
  118. #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
  119. #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
  120. NvRegUnknownSetupReg6 = 0x008,
  121. #define NVREG_UNKSETUP6_VAL 3
  122. /*
  123. * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
  124. * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
  125. */
  126. NvRegPollingInterval = 0x00c,
  127. #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
  128. #define NVREG_POLL_DEFAULT_CPU 13
  129. NvRegMSIMap0 = 0x020,
  130. NvRegMSIMap1 = 0x024,
  131. NvRegMSIIrqMask = 0x030,
  132. #define NVREG_MSI_VECTOR_0_ENABLED 0x01
  133. NvRegMisc1 = 0x080,
  134. #define NVREG_MISC1_PAUSE_TX 0x01
  135. #define NVREG_MISC1_HD 0x02
  136. #define NVREG_MISC1_FORCE 0x3b0f3c
  137. NvRegMacReset = 0x34,
  138. #define NVREG_MAC_RESET_ASSERT 0x0F3
  139. NvRegTransmitterControl = 0x084,
  140. #define NVREG_XMITCTL_START 0x01
  141. #define NVREG_XMITCTL_MGMT_ST 0x40000000
  142. #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
  143. #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
  144. #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
  145. #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
  146. #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
  147. #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
  148. #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
  149. #define NVREG_XMITCTL_HOST_LOADED 0x00004000
  150. #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
  151. #define NVREG_XMITCTL_DATA_START 0x00100000
  152. #define NVREG_XMITCTL_DATA_READY 0x00010000
  153. #define NVREG_XMITCTL_DATA_ERROR 0x00020000
  154. NvRegTransmitterStatus = 0x088,
  155. #define NVREG_XMITSTAT_BUSY 0x01
  156. NvRegPacketFilterFlags = 0x8c,
  157. #define NVREG_PFF_PAUSE_RX 0x08
  158. #define NVREG_PFF_ALWAYS 0x7F0000
  159. #define NVREG_PFF_PROMISC 0x80
  160. #define NVREG_PFF_MYADDR 0x20
  161. #define NVREG_PFF_LOOPBACK 0x10
  162. NvRegOffloadConfig = 0x90,
  163. #define NVREG_OFFLOAD_HOMEPHY 0x601
  164. #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
  165. NvRegReceiverControl = 0x094,
  166. #define NVREG_RCVCTL_START 0x01
  167. #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
  168. NvRegReceiverStatus = 0x98,
  169. #define NVREG_RCVSTAT_BUSY 0x01
  170. NvRegSlotTime = 0x9c,
  171. #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
  172. #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
  173. #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
  174. #define NVREG_SLOTTIME_HALF 0x0000ff00
  175. #define NVREG_SLOTTIME_DEFAULT 0x00007f00
  176. #define NVREG_SLOTTIME_MASK 0x000000ff
  177. NvRegTxDeferral = 0xA0,
  178. #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
  179. #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
  180. #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
  181. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
  182. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
  183. #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
  184. NvRegRxDeferral = 0xA4,
  185. #define NVREG_RX_DEFERRAL_DEFAULT 0x16
  186. NvRegMacAddrA = 0xA8,
  187. NvRegMacAddrB = 0xAC,
  188. NvRegMulticastAddrA = 0xB0,
  189. #define NVREG_MCASTADDRA_FORCE 0x01
  190. NvRegMulticastAddrB = 0xB4,
  191. NvRegMulticastMaskA = 0xB8,
  192. #define NVREG_MCASTMASKA_NONE 0xffffffff
  193. NvRegMulticastMaskB = 0xBC,
  194. #define NVREG_MCASTMASKB_NONE 0xffff
  195. NvRegPhyInterface = 0xC0,
  196. #define PHY_RGMII 0x10000000
  197. NvRegBackOffControl = 0xC4,
  198. #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
  199. #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
  200. #define NVREG_BKOFFCTRL_SELECT 24
  201. #define NVREG_BKOFFCTRL_GEAR 12
  202. NvRegTxRingPhysAddr = 0x100,
  203. NvRegRxRingPhysAddr = 0x104,
  204. NvRegRingSizes = 0x108,
  205. #define NVREG_RINGSZ_TXSHIFT 0
  206. #define NVREG_RINGSZ_RXSHIFT 16
  207. NvRegTransmitPoll = 0x10c,
  208. #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
  209. NvRegLinkSpeed = 0x110,
  210. #define NVREG_LINKSPEED_FORCE 0x10000
  211. #define NVREG_LINKSPEED_10 1000
  212. #define NVREG_LINKSPEED_100 100
  213. #define NVREG_LINKSPEED_1000 50
  214. #define NVREG_LINKSPEED_MASK (0xFFF)
  215. NvRegUnknownSetupReg5 = 0x130,
  216. #define NVREG_UNKSETUP5_BIT31 (1<<31)
  217. NvRegTxWatermark = 0x13c,
  218. #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
  219. #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
  220. #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
  221. NvRegTxRxControl = 0x144,
  222. #define NVREG_TXRXCTL_KICK 0x0001
  223. #define NVREG_TXRXCTL_BIT1 0x0002
  224. #define NVREG_TXRXCTL_BIT2 0x0004
  225. #define NVREG_TXRXCTL_IDLE 0x0008
  226. #define NVREG_TXRXCTL_RESET 0x0010
  227. #define NVREG_TXRXCTL_RXCHECK 0x0400
  228. #define NVREG_TXRXCTL_DESC_1 0
  229. #define NVREG_TXRXCTL_DESC_2 0x002100
  230. #define NVREG_TXRXCTL_DESC_3 0xc02200
  231. #define NVREG_TXRXCTL_VLANSTRIP 0x00040
  232. #define NVREG_TXRXCTL_VLANINS 0x00080
  233. NvRegTxRingPhysAddrHigh = 0x148,
  234. NvRegRxRingPhysAddrHigh = 0x14C,
  235. NvRegTxPauseFrame = 0x170,
  236. #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
  237. #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
  238. #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
  239. #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
  240. NvRegTxPauseFrameLimit = 0x174,
  241. #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
  242. NvRegMIIStatus = 0x180,
  243. #define NVREG_MIISTAT_ERROR 0x0001
  244. #define NVREG_MIISTAT_LINKCHANGE 0x0008
  245. #define NVREG_MIISTAT_MASK_RW 0x0007
  246. #define NVREG_MIISTAT_MASK_ALL 0x000f
  247. NvRegMIIMask = 0x184,
  248. #define NVREG_MII_LINKCHANGE 0x0008
  249. NvRegAdapterControl = 0x188,
  250. #define NVREG_ADAPTCTL_START 0x02
  251. #define NVREG_ADAPTCTL_LINKUP 0x04
  252. #define NVREG_ADAPTCTL_PHYVALID 0x40000
  253. #define NVREG_ADAPTCTL_RUNNING 0x100000
  254. #define NVREG_ADAPTCTL_PHYSHIFT 24
  255. NvRegMIISpeed = 0x18c,
  256. #define NVREG_MIISPEED_BIT8 (1<<8)
  257. #define NVREG_MIIDELAY 5
  258. NvRegMIIControl = 0x190,
  259. #define NVREG_MIICTL_INUSE 0x08000
  260. #define NVREG_MIICTL_WRITE 0x00400
  261. #define NVREG_MIICTL_ADDRSHIFT 5
  262. NvRegMIIData = 0x194,
  263. NvRegTxUnicast = 0x1a0,
  264. NvRegTxMulticast = 0x1a4,
  265. NvRegTxBroadcast = 0x1a8,
  266. NvRegWakeUpFlags = 0x200,
  267. #define NVREG_WAKEUPFLAGS_VAL 0x7770
  268. #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
  269. #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
  270. #define NVREG_WAKEUPFLAGS_D3SHIFT 12
  271. #define NVREG_WAKEUPFLAGS_D2SHIFT 8
  272. #define NVREG_WAKEUPFLAGS_D1SHIFT 4
  273. #define NVREG_WAKEUPFLAGS_D0SHIFT 0
  274. #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
  275. #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
  276. #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
  277. #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
  278. NvRegMgmtUnitGetVersion = 0x204,
  279. #define NVREG_MGMTUNITGETVERSION 0x01
  280. NvRegMgmtUnitVersion = 0x208,
  281. #define NVREG_MGMTUNITVERSION 0x08
  282. NvRegPowerCap = 0x268,
  283. #define NVREG_POWERCAP_D3SUPP (1<<30)
  284. #define NVREG_POWERCAP_D2SUPP (1<<26)
  285. #define NVREG_POWERCAP_D1SUPP (1<<25)
  286. NvRegPowerState = 0x26c,
  287. #define NVREG_POWERSTATE_POWEREDUP 0x8000
  288. #define NVREG_POWERSTATE_VALID 0x0100
  289. #define NVREG_POWERSTATE_MASK 0x0003
  290. #define NVREG_POWERSTATE_D0 0x0000
  291. #define NVREG_POWERSTATE_D1 0x0001
  292. #define NVREG_POWERSTATE_D2 0x0002
  293. #define NVREG_POWERSTATE_D3 0x0003
  294. NvRegMgmtUnitControl = 0x278,
  295. #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
  296. NvRegTxCnt = 0x280,
  297. NvRegTxZeroReXmt = 0x284,
  298. NvRegTxOneReXmt = 0x288,
  299. NvRegTxManyReXmt = 0x28c,
  300. NvRegTxLateCol = 0x290,
  301. NvRegTxUnderflow = 0x294,
  302. NvRegTxLossCarrier = 0x298,
  303. NvRegTxExcessDef = 0x29c,
  304. NvRegTxRetryErr = 0x2a0,
  305. NvRegRxFrameErr = 0x2a4,
  306. NvRegRxExtraByte = 0x2a8,
  307. NvRegRxLateCol = 0x2ac,
  308. NvRegRxRunt = 0x2b0,
  309. NvRegRxFrameTooLong = 0x2b4,
  310. NvRegRxOverflow = 0x2b8,
  311. NvRegRxFCSErr = 0x2bc,
  312. NvRegRxFrameAlignErr = 0x2c0,
  313. NvRegRxLenErr = 0x2c4,
  314. NvRegRxUnicast = 0x2c8,
  315. NvRegRxMulticast = 0x2cc,
  316. NvRegRxBroadcast = 0x2d0,
  317. NvRegTxDef = 0x2d4,
  318. NvRegTxFrame = 0x2d8,
  319. NvRegRxCnt = 0x2dc,
  320. NvRegTxPause = 0x2e0,
  321. NvRegRxPause = 0x2e4,
  322. NvRegRxDropFrame = 0x2e8,
  323. NvRegVlanControl = 0x300,
  324. #define NVREG_VLANCONTROL_ENABLE 0x2000
  325. NvRegMSIXMap0 = 0x3e0,
  326. NvRegMSIXMap1 = 0x3e4,
  327. NvRegMSIXIrqStatus = 0x3f0,
  328. NvRegPowerState2 = 0x600,
  329. #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
  330. #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
  331. #define NVREG_POWERSTATE2_PHY_RESET 0x0004
  332. #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
  333. };
  334. /* Big endian: should work, but is untested */
  335. struct ring_desc {
  336. __le32 buf;
  337. __le32 flaglen;
  338. };
  339. struct ring_desc_ex {
  340. __le32 bufhigh;
  341. __le32 buflow;
  342. __le32 txvlan;
  343. __le32 flaglen;
  344. };
  345. union ring_type {
  346. struct ring_desc *orig;
  347. struct ring_desc_ex *ex;
  348. };
  349. #define FLAG_MASK_V1 0xffff0000
  350. #define FLAG_MASK_V2 0xffffc000
  351. #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
  352. #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
  353. #define NV_TX_LASTPACKET (1<<16)
  354. #define NV_TX_RETRYERROR (1<<19)
  355. #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
  356. #define NV_TX_FORCED_INTERRUPT (1<<24)
  357. #define NV_TX_DEFERRED (1<<26)
  358. #define NV_TX_CARRIERLOST (1<<27)
  359. #define NV_TX_LATECOLLISION (1<<28)
  360. #define NV_TX_UNDERFLOW (1<<29)
  361. #define NV_TX_ERROR (1<<30)
  362. #define NV_TX_VALID (1<<31)
  363. #define NV_TX2_LASTPACKET (1<<29)
  364. #define NV_TX2_RETRYERROR (1<<18)
  365. #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
  366. #define NV_TX2_FORCED_INTERRUPT (1<<30)
  367. #define NV_TX2_DEFERRED (1<<25)
  368. #define NV_TX2_CARRIERLOST (1<<26)
  369. #define NV_TX2_LATECOLLISION (1<<27)
  370. #define NV_TX2_UNDERFLOW (1<<28)
  371. /* error and valid are the same for both */
  372. #define NV_TX2_ERROR (1<<30)
  373. #define NV_TX2_VALID (1<<31)
  374. #define NV_TX2_TSO (1<<28)
  375. #define NV_TX2_TSO_SHIFT 14
  376. #define NV_TX2_TSO_MAX_SHIFT 14
  377. #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
  378. #define NV_TX2_CHECKSUM_L3 (1<<27)
  379. #define NV_TX2_CHECKSUM_L4 (1<<26)
  380. #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
  381. #define NV_RX_DESCRIPTORVALID (1<<16)
  382. #define NV_RX_MISSEDFRAME (1<<17)
  383. #define NV_RX_SUBSTRACT1 (1<<18)
  384. #define NV_RX_ERROR1 (1<<23)
  385. #define NV_RX_ERROR2 (1<<24)
  386. #define NV_RX_ERROR3 (1<<25)
  387. #define NV_RX_ERROR4 (1<<26)
  388. #define NV_RX_CRCERR (1<<27)
  389. #define NV_RX_OVERFLOW (1<<28)
  390. #define NV_RX_FRAMINGERR (1<<29)
  391. #define NV_RX_ERROR (1<<30)
  392. #define NV_RX_AVAIL (1<<31)
  393. #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
  394. #define NV_RX2_CHECKSUMMASK (0x1C000000)
  395. #define NV_RX2_CHECKSUM_IP (0x10000000)
  396. #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
  397. #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
  398. #define NV_RX2_DESCRIPTORVALID (1<<29)
  399. #define NV_RX2_SUBSTRACT1 (1<<25)
  400. #define NV_RX2_ERROR1 (1<<18)
  401. #define NV_RX2_ERROR2 (1<<19)
  402. #define NV_RX2_ERROR3 (1<<20)
  403. #define NV_RX2_ERROR4 (1<<21)
  404. #define NV_RX2_CRCERR (1<<22)
  405. #define NV_RX2_OVERFLOW (1<<23)
  406. #define NV_RX2_FRAMINGERR (1<<24)
  407. /* error and avail are the same for both */
  408. #define NV_RX2_ERROR (1<<30)
  409. #define NV_RX2_AVAIL (1<<31)
  410. #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
  411. #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
  412. #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
  413. /* Miscellaneous hardware related defines: */
  414. #define NV_PCI_REGSZ_VER1 0x270
  415. #define NV_PCI_REGSZ_VER2 0x2d4
  416. #define NV_PCI_REGSZ_VER3 0x604
  417. #define NV_PCI_REGSZ_MAX 0x604
  418. /* various timeout delays: all in usec */
  419. #define NV_TXRX_RESET_DELAY 4
  420. #define NV_TXSTOP_DELAY1 10
  421. #define NV_TXSTOP_DELAY1MAX 500000
  422. #define NV_TXSTOP_DELAY2 100
  423. #define NV_RXSTOP_DELAY1 10
  424. #define NV_RXSTOP_DELAY1MAX 500000
  425. #define NV_RXSTOP_DELAY2 100
  426. #define NV_SETUP5_DELAY 5
  427. #define NV_SETUP5_DELAYMAX 50000
  428. #define NV_POWERUP_DELAY 5
  429. #define NV_POWERUP_DELAYMAX 5000
  430. #define NV_MIIBUSY_DELAY 50
  431. #define NV_MIIPHY_DELAY 10
  432. #define NV_MIIPHY_DELAYMAX 10000
  433. #define NV_MAC_RESET_DELAY 64
  434. #define NV_WAKEUPPATTERNS 5
  435. #define NV_WAKEUPMASKENTRIES 4
  436. /* General driver defaults */
  437. #define NV_WATCHDOG_TIMEO (5*HZ)
  438. #define RX_RING_DEFAULT 512
  439. #define TX_RING_DEFAULT 256
  440. #define RX_RING_MIN 128
  441. #define TX_RING_MIN 64
  442. #define RING_MAX_DESC_VER_1 1024
  443. #define RING_MAX_DESC_VER_2_3 16384
  444. /* rx/tx mac addr + type + vlan + align + slack*/
  445. #define NV_RX_HEADERS (64)
  446. /* even more slack. */
  447. #define NV_RX_ALLOC_PAD (64)
  448. /* maximum mtu size */
  449. #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
  450. #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
  451. #define OOM_REFILL (1+HZ/20)
  452. #define POLL_WAIT (1+HZ/100)
  453. #define LINK_TIMEOUT (3*HZ)
  454. #define STATS_INTERVAL (10*HZ)
  455. /*
  456. * desc_ver values:
  457. * The nic supports three different descriptor types:
  458. * - DESC_VER_1: Original
  459. * - DESC_VER_2: support for jumbo frames.
  460. * - DESC_VER_3: 64-bit format.
  461. */
  462. #define DESC_VER_1 1
  463. #define DESC_VER_2 2
  464. #define DESC_VER_3 3
  465. /* PHY defines */
  466. #define PHY_OUI_MARVELL 0x5043
  467. #define PHY_OUI_CICADA 0x03f1
  468. #define PHY_OUI_VITESSE 0x01c1
  469. #define PHY_OUI_REALTEK 0x0732
  470. #define PHY_OUI_REALTEK2 0x0020
  471. #define PHYID1_OUI_MASK 0x03ff
  472. #define PHYID1_OUI_SHFT 6
  473. #define PHYID2_OUI_MASK 0xfc00
  474. #define PHYID2_OUI_SHFT 10
  475. #define PHYID2_MODEL_MASK 0x03f0
  476. #define PHY_MODEL_REALTEK_8211 0x0110
  477. #define PHY_REV_MASK 0x0001
  478. #define PHY_REV_REALTEK_8211B 0x0000
  479. #define PHY_REV_REALTEK_8211C 0x0001
  480. #define PHY_MODEL_REALTEK_8201 0x0200
  481. #define PHY_MODEL_MARVELL_E3016 0x0220
  482. #define PHY_MARVELL_E3016_INITMASK 0x0300
  483. #define PHY_CICADA_INIT1 0x0f000
  484. #define PHY_CICADA_INIT2 0x0e00
  485. #define PHY_CICADA_INIT3 0x01000
  486. #define PHY_CICADA_INIT4 0x0200
  487. #define PHY_CICADA_INIT5 0x0004
  488. #define PHY_CICADA_INIT6 0x02000
  489. #define PHY_VITESSE_INIT_REG1 0x1f
  490. #define PHY_VITESSE_INIT_REG2 0x10
  491. #define PHY_VITESSE_INIT_REG3 0x11
  492. #define PHY_VITESSE_INIT_REG4 0x12
  493. #define PHY_VITESSE_INIT_MSK1 0xc
  494. #define PHY_VITESSE_INIT_MSK2 0x0180
  495. #define PHY_VITESSE_INIT1 0x52b5
  496. #define PHY_VITESSE_INIT2 0xaf8a
  497. #define PHY_VITESSE_INIT3 0x8
  498. #define PHY_VITESSE_INIT4 0x8f8a
  499. #define PHY_VITESSE_INIT5 0xaf86
  500. #define PHY_VITESSE_INIT6 0x8f86
  501. #define PHY_VITESSE_INIT7 0xaf82
  502. #define PHY_VITESSE_INIT8 0x0100
  503. #define PHY_VITESSE_INIT9 0x8f82
  504. #define PHY_VITESSE_INIT10 0x0
  505. #define PHY_REALTEK_INIT_REG1 0x1f
  506. #define PHY_REALTEK_INIT_REG2 0x19
  507. #define PHY_REALTEK_INIT_REG3 0x13
  508. #define PHY_REALTEK_INIT_REG4 0x14
  509. #define PHY_REALTEK_INIT_REG5 0x18
  510. #define PHY_REALTEK_INIT_REG6 0x11
  511. #define PHY_REALTEK_INIT_REG7 0x01
  512. #define PHY_REALTEK_INIT1 0x0000
  513. #define PHY_REALTEK_INIT2 0x8e00
  514. #define PHY_REALTEK_INIT3 0x0001
  515. #define PHY_REALTEK_INIT4 0xad17
  516. #define PHY_REALTEK_INIT5 0xfb54
  517. #define PHY_REALTEK_INIT6 0xf5c7
  518. #define PHY_REALTEK_INIT7 0x1000
  519. #define PHY_REALTEK_INIT8 0x0003
  520. #define PHY_REALTEK_INIT9 0x0008
  521. #define PHY_REALTEK_INIT10 0x0005
  522. #define PHY_REALTEK_INIT11 0x0200
  523. #define PHY_REALTEK_INIT_MSK1 0x0003
  524. #define PHY_GIGABIT 0x0100
  525. #define PHY_TIMEOUT 0x1
  526. #define PHY_ERROR 0x2
  527. #define PHY_100 0x1
  528. #define PHY_1000 0x2
  529. #define PHY_HALF 0x100
  530. #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
  531. #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
  532. #define NV_PAUSEFRAME_RX_ENABLE 0x0004
  533. #define NV_PAUSEFRAME_TX_ENABLE 0x0008
  534. #define NV_PAUSEFRAME_RX_REQ 0x0010
  535. #define NV_PAUSEFRAME_TX_REQ 0x0020
  536. #define NV_PAUSEFRAME_AUTONEG 0x0040
  537. /* MSI/MSI-X defines */
  538. #define NV_MSI_X_MAX_VECTORS 8
  539. #define NV_MSI_X_VECTORS_MASK 0x000f
  540. #define NV_MSI_CAPABLE 0x0010
  541. #define NV_MSI_X_CAPABLE 0x0020
  542. #define NV_MSI_ENABLED 0x0040
  543. #define NV_MSI_X_ENABLED 0x0080
  544. #define NV_MSI_X_VECTOR_ALL 0x0
  545. #define NV_MSI_X_VECTOR_RX 0x0
  546. #define NV_MSI_X_VECTOR_TX 0x1
  547. #define NV_MSI_X_VECTOR_OTHER 0x2
  548. #define NV_MSI_PRIV_OFFSET 0x68
  549. #define NV_MSI_PRIV_VALUE 0xffffffff
  550. #define NV_RESTART_TX 0x1
  551. #define NV_RESTART_RX 0x2
  552. #define NV_TX_LIMIT_COUNT 16
  553. #define NV_DYNAMIC_THRESHOLD 4
  554. #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
  555. /* statistics */
  556. struct nv_ethtool_str {
  557. char name[ETH_GSTRING_LEN];
  558. };
  559. static const struct nv_ethtool_str nv_estats_str[] = {
  560. { "tx_bytes" },
  561. { "tx_zero_rexmt" },
  562. { "tx_one_rexmt" },
  563. { "tx_many_rexmt" },
  564. { "tx_late_collision" },
  565. { "tx_fifo_errors" },
  566. { "tx_carrier_errors" },
  567. { "tx_excess_deferral" },
  568. { "tx_retry_error" },
  569. { "rx_frame_error" },
  570. { "rx_extra_byte" },
  571. { "rx_late_collision" },
  572. { "rx_runt" },
  573. { "rx_frame_too_long" },
  574. { "rx_over_errors" },
  575. { "rx_crc_errors" },
  576. { "rx_frame_align_error" },
  577. { "rx_length_error" },
  578. { "rx_unicast" },
  579. { "rx_multicast" },
  580. { "rx_broadcast" },
  581. { "rx_packets" },
  582. { "rx_errors_total" },
  583. { "tx_errors_total" },
  584. /* version 2 stats */
  585. { "tx_deferral" },
  586. { "tx_packets" },
  587. { "rx_bytes" },
  588. { "tx_pause" },
  589. { "rx_pause" },
  590. { "rx_drop_frame" },
  591. /* version 3 stats */
  592. { "tx_unicast" },
  593. { "tx_multicast" },
  594. { "tx_broadcast" }
  595. };
  596. struct nv_ethtool_stats {
  597. u64 tx_bytes;
  598. u64 tx_zero_rexmt;
  599. u64 tx_one_rexmt;
  600. u64 tx_many_rexmt;
  601. u64 tx_late_collision;
  602. u64 tx_fifo_errors;
  603. u64 tx_carrier_errors;
  604. u64 tx_excess_deferral;
  605. u64 tx_retry_error;
  606. u64 rx_frame_error;
  607. u64 rx_extra_byte;
  608. u64 rx_late_collision;
  609. u64 rx_runt;
  610. u64 rx_frame_too_long;
  611. u64 rx_over_errors;
  612. u64 rx_crc_errors;
  613. u64 rx_frame_align_error;
  614. u64 rx_length_error;
  615. u64 rx_unicast;
  616. u64 rx_multicast;
  617. u64 rx_broadcast;
  618. u64 rx_packets;
  619. u64 rx_errors_total;
  620. u64 tx_errors_total;
  621. /* version 2 stats */
  622. u64 tx_deferral;
  623. u64 tx_packets;
  624. u64 rx_bytes;
  625. u64 tx_pause;
  626. u64 rx_pause;
  627. u64 rx_drop_frame;
  628. /* version 3 stats */
  629. u64 tx_unicast;
  630. u64 tx_multicast;
  631. u64 tx_broadcast;
  632. };
  633. #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
  634. #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
  635. #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
  636. /* diagnostics */
  637. #define NV_TEST_COUNT_BASE 3
  638. #define NV_TEST_COUNT_EXTENDED 4
  639. static const struct nv_ethtool_str nv_etests_str[] = {
  640. { "link (online/offline)" },
  641. { "register (offline) " },
  642. { "interrupt (offline) " },
  643. { "loopback (offline) " }
  644. };
  645. struct register_test {
  646. __u32 reg;
  647. __u32 mask;
  648. };
  649. static const struct register_test nv_registers_test[] = {
  650. { NvRegUnknownSetupReg6, 0x01 },
  651. { NvRegMisc1, 0x03c },
  652. { NvRegOffloadConfig, 0x03ff },
  653. { NvRegMulticastAddrA, 0xffffffff },
  654. { NvRegTxWatermark, 0x0ff },
  655. { NvRegWakeUpFlags, 0x07777 },
  656. { 0, 0 }
  657. };
  658. struct nv_skb_map {
  659. struct sk_buff *skb;
  660. dma_addr_t dma;
  661. unsigned int dma_len:31;
  662. unsigned int dma_single:1;
  663. struct ring_desc_ex *first_tx_desc;
  664. struct nv_skb_map *next_tx_ctx;
  665. };
  666. /*
  667. * SMP locking:
  668. * All hardware access under netdev_priv(dev)->lock, except the performance
  669. * critical parts:
  670. * - rx is (pseudo-) lockless: it relies on the single-threading provided
  671. * by the arch code for interrupts.
  672. * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
  673. * needs netdev_priv(dev)->lock :-(
  674. * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
  675. */
  676. /* in dev: base, irq */
  677. struct fe_priv {
  678. spinlock_t lock;
  679. struct net_device *dev;
  680. struct napi_struct napi;
  681. /* General data:
  682. * Locking: spin_lock(&np->lock); */
  683. struct nv_ethtool_stats estats;
  684. int in_shutdown;
  685. u32 linkspeed;
  686. int duplex;
  687. int autoneg;
  688. int fixed_mode;
  689. int phyaddr;
  690. int wolenabled;
  691. unsigned int phy_oui;
  692. unsigned int phy_model;
  693. unsigned int phy_rev;
  694. u16 gigabit;
  695. int intr_test;
  696. int recover_error;
  697. int quiet_count;
  698. /* General data: RO fields */
  699. dma_addr_t ring_addr;
  700. struct pci_dev *pci_dev;
  701. u32 orig_mac[2];
  702. u32 events;
  703. u32 irqmask;
  704. u32 desc_ver;
  705. u32 txrxctl_bits;
  706. u32 vlanctl_bits;
  707. u32 driver_data;
  708. u32 device_id;
  709. u32 register_size;
  710. u32 mac_in_use;
  711. int mgmt_version;
  712. int mgmt_sema;
  713. void __iomem *base;
  714. /* rx specific fields.
  715. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  716. */
  717. union ring_type get_rx, put_rx, first_rx, last_rx;
  718. struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
  719. struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
  720. struct nv_skb_map *rx_skb;
  721. union ring_type rx_ring;
  722. unsigned int rx_buf_sz;
  723. unsigned int pkt_limit;
  724. struct timer_list oom_kick;
  725. struct timer_list nic_poll;
  726. struct timer_list stats_poll;
  727. u32 nic_poll_irq;
  728. int rx_ring_size;
  729. /* media detection workaround.
  730. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  731. */
  732. int need_linktimer;
  733. unsigned long link_timeout;
  734. /*
  735. * tx specific fields.
  736. */
  737. union ring_type get_tx, put_tx, first_tx, last_tx;
  738. struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
  739. struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
  740. struct nv_skb_map *tx_skb;
  741. union ring_type tx_ring;
  742. u32 tx_flags;
  743. int tx_ring_size;
  744. int tx_limit;
  745. u32 tx_pkts_in_progress;
  746. struct nv_skb_map *tx_change_owner;
  747. struct nv_skb_map *tx_end_flip;
  748. int tx_stop;
  749. /* vlan fields */
  750. struct vlan_group *vlangrp;
  751. /* msi/msi-x fields */
  752. u32 msi_flags;
  753. struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
  754. /* flow control */
  755. u32 pause_flags;
  756. /* power saved state */
  757. u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
  758. /* for different msi-x irq type */
  759. char name_rx[IFNAMSIZ + 3]; /* -rx */
  760. char name_tx[IFNAMSIZ + 3]; /* -tx */
  761. char name_other[IFNAMSIZ + 6]; /* -other */
  762. };
  763. /*
  764. * Maximum number of loops until we assume that a bit in the irq mask
  765. * is stuck. Overridable with module param.
  766. */
  767. static int max_interrupt_work = 4;
  768. /*
  769. * Optimization can be either throuput mode or cpu mode
  770. *
  771. * Throughput Mode: Every tx and rx packet will generate an interrupt.
  772. * CPU Mode: Interrupts are controlled by a timer.
  773. */
  774. enum {
  775. NV_OPTIMIZATION_MODE_THROUGHPUT,
  776. NV_OPTIMIZATION_MODE_CPU,
  777. NV_OPTIMIZATION_MODE_DYNAMIC
  778. };
  779. static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
  780. /*
  781. * Poll interval for timer irq
  782. *
  783. * This interval determines how frequent an interrupt is generated.
  784. * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
  785. * Min = 0, and Max = 65535
  786. */
  787. static int poll_interval = -1;
  788. /*
  789. * MSI interrupts
  790. */
  791. enum {
  792. NV_MSI_INT_DISABLED,
  793. NV_MSI_INT_ENABLED
  794. };
  795. static int msi = NV_MSI_INT_ENABLED;
  796. /*
  797. * MSIX interrupts
  798. */
  799. enum {
  800. NV_MSIX_INT_DISABLED,
  801. NV_MSIX_INT_ENABLED
  802. };
  803. static int msix = NV_MSIX_INT_ENABLED;
  804. /*
  805. * DMA 64bit
  806. */
  807. enum {
  808. NV_DMA_64BIT_DISABLED,
  809. NV_DMA_64BIT_ENABLED
  810. };
  811. static int dma_64bit = NV_DMA_64BIT_ENABLED;
  812. /*
  813. * Crossover Detection
  814. * Realtek 8201 phy + some OEM boards do not work properly.
  815. */
  816. enum {
  817. NV_CROSSOVER_DETECTION_DISABLED,
  818. NV_CROSSOVER_DETECTION_ENABLED
  819. };
  820. static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
  821. /*
  822. * Power down phy when interface is down (persists through reboot;
  823. * older Linux and other OSes may not power it up again)
  824. */
  825. static int phy_power_down;
  826. static inline struct fe_priv *get_nvpriv(struct net_device *dev)
  827. {
  828. return netdev_priv(dev);
  829. }
  830. static inline u8 __iomem *get_hwbase(struct net_device *dev)
  831. {
  832. return ((struct fe_priv *)netdev_priv(dev))->base;
  833. }
  834. static inline void pci_push(u8 __iomem *base)
  835. {
  836. /* force out pending posted writes */
  837. readl(base);
  838. }
  839. static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
  840. {
  841. return le32_to_cpu(prd->flaglen)
  842. & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
  843. }
  844. static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
  845. {
  846. return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
  847. }
  848. static bool nv_optimized(struct fe_priv *np)
  849. {
  850. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  851. return false;
  852. return true;
  853. }
  854. static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
  855. int delay, int delaymax)
  856. {
  857. u8 __iomem *base = get_hwbase(dev);
  858. pci_push(base);
  859. do {
  860. udelay(delay);
  861. delaymax -= delay;
  862. if (delaymax < 0)
  863. return 1;
  864. } while ((readl(base + offset) & mask) != target);
  865. return 0;
  866. }
  867. #define NV_SETUP_RX_RING 0x01
  868. #define NV_SETUP_TX_RING 0x02
  869. static inline u32 dma_low(dma_addr_t addr)
  870. {
  871. return addr;
  872. }
  873. static inline u32 dma_high(dma_addr_t addr)
  874. {
  875. return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
  876. }
  877. static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
  878. {
  879. struct fe_priv *np = get_nvpriv(dev);
  880. u8 __iomem *base = get_hwbase(dev);
  881. if (!nv_optimized(np)) {
  882. if (rxtx_flags & NV_SETUP_RX_RING)
  883. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  884. if (rxtx_flags & NV_SETUP_TX_RING)
  885. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  886. } else {
  887. if (rxtx_flags & NV_SETUP_RX_RING) {
  888. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  889. writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
  890. }
  891. if (rxtx_flags & NV_SETUP_TX_RING) {
  892. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
  893. writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
  894. }
  895. }
  896. }
  897. static void free_rings(struct net_device *dev)
  898. {
  899. struct fe_priv *np = get_nvpriv(dev);
  900. if (!nv_optimized(np)) {
  901. if (np->rx_ring.orig)
  902. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  903. np->rx_ring.orig, np->ring_addr);
  904. } else {
  905. if (np->rx_ring.ex)
  906. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  907. np->rx_ring.ex, np->ring_addr);
  908. }
  909. kfree(np->rx_skb);
  910. kfree(np->tx_skb);
  911. }
  912. static int using_multi_irqs(struct net_device *dev)
  913. {
  914. struct fe_priv *np = get_nvpriv(dev);
  915. if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
  916. ((np->msi_flags & NV_MSI_X_ENABLED) &&
  917. ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
  918. return 0;
  919. else
  920. return 1;
  921. }
  922. static void nv_txrx_gate(struct net_device *dev, bool gate)
  923. {
  924. struct fe_priv *np = get_nvpriv(dev);
  925. u8 __iomem *base = get_hwbase(dev);
  926. u32 powerstate;
  927. if (!np->mac_in_use &&
  928. (np->driver_data & DEV_HAS_POWER_CNTRL)) {
  929. powerstate = readl(base + NvRegPowerState2);
  930. if (gate)
  931. powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
  932. else
  933. powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
  934. writel(powerstate, base + NvRegPowerState2);
  935. }
  936. }
  937. static void nv_enable_irq(struct net_device *dev)
  938. {
  939. struct fe_priv *np = get_nvpriv(dev);
  940. if (!using_multi_irqs(dev)) {
  941. if (np->msi_flags & NV_MSI_X_ENABLED)
  942. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  943. else
  944. enable_irq(np->pci_dev->irq);
  945. } else {
  946. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  947. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  948. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  949. }
  950. }
  951. static void nv_disable_irq(struct net_device *dev)
  952. {
  953. struct fe_priv *np = get_nvpriv(dev);
  954. if (!using_multi_irqs(dev)) {
  955. if (np->msi_flags & NV_MSI_X_ENABLED)
  956. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  957. else
  958. disable_irq(np->pci_dev->irq);
  959. } else {
  960. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  961. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  962. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  963. }
  964. }
  965. /* In MSIX mode, a write to irqmask behaves as XOR */
  966. static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
  967. {
  968. u8 __iomem *base = get_hwbase(dev);
  969. writel(mask, base + NvRegIrqMask);
  970. }
  971. static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
  972. {
  973. struct fe_priv *np = get_nvpriv(dev);
  974. u8 __iomem *base = get_hwbase(dev);
  975. if (np->msi_flags & NV_MSI_X_ENABLED) {
  976. writel(mask, base + NvRegIrqMask);
  977. } else {
  978. if (np->msi_flags & NV_MSI_ENABLED)
  979. writel(0, base + NvRegMSIIrqMask);
  980. writel(0, base + NvRegIrqMask);
  981. }
  982. }
  983. static void nv_napi_enable(struct net_device *dev)
  984. {
  985. struct fe_priv *np = get_nvpriv(dev);
  986. napi_enable(&np->napi);
  987. }
  988. static void nv_napi_disable(struct net_device *dev)
  989. {
  990. struct fe_priv *np = get_nvpriv(dev);
  991. napi_disable(&np->napi);
  992. }
  993. #define MII_READ (-1)
  994. /* mii_rw: read/write a register on the PHY.
  995. *
  996. * Caller must guarantee serialization
  997. */
  998. static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
  999. {
  1000. u8 __iomem *base = get_hwbase(dev);
  1001. u32 reg;
  1002. int retval;
  1003. writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
  1004. reg = readl(base + NvRegMIIControl);
  1005. if (reg & NVREG_MIICTL_INUSE) {
  1006. writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
  1007. udelay(NV_MIIBUSY_DELAY);
  1008. }
  1009. reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
  1010. if (value != MII_READ) {
  1011. writel(value, base + NvRegMIIData);
  1012. reg |= NVREG_MIICTL_WRITE;
  1013. }
  1014. writel(reg, base + NvRegMIIControl);
  1015. if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
  1016. NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
  1017. retval = -1;
  1018. } else if (value != MII_READ) {
  1019. /* it was a write operation - fewer failures are detectable */
  1020. retval = 0;
  1021. } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
  1022. retval = -1;
  1023. } else {
  1024. retval = readl(base + NvRegMIIData);
  1025. }
  1026. return retval;
  1027. }
  1028. static int phy_reset(struct net_device *dev, u32 bmcr_setup)
  1029. {
  1030. struct fe_priv *np = netdev_priv(dev);
  1031. u32 miicontrol;
  1032. unsigned int tries = 0;
  1033. miicontrol = BMCR_RESET | bmcr_setup;
  1034. if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
  1035. return -1;
  1036. /* wait for 500ms */
  1037. msleep(500);
  1038. /* must wait till reset is deasserted */
  1039. while (miicontrol & BMCR_RESET) {
  1040. usleep_range(10000, 20000);
  1041. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1042. /* FIXME: 100 tries seem excessive */
  1043. if (tries++ > 100)
  1044. return -1;
  1045. }
  1046. return 0;
  1047. }
  1048. static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
  1049. {
  1050. static const struct {
  1051. int reg;
  1052. int init;
  1053. } ri[] = {
  1054. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
  1055. { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
  1056. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
  1057. { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
  1058. { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
  1059. { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
  1060. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
  1061. };
  1062. int i;
  1063. for (i = 0; i < ARRAY_SIZE(ri); i++) {
  1064. if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
  1065. return PHY_ERROR;
  1066. }
  1067. return 0;
  1068. }
  1069. static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
  1070. {
  1071. u32 reg;
  1072. u8 __iomem *base = get_hwbase(dev);
  1073. u32 powerstate = readl(base + NvRegPowerState2);
  1074. /* need to perform hw phy reset */
  1075. powerstate |= NVREG_POWERSTATE2_PHY_RESET;
  1076. writel(powerstate, base + NvRegPowerState2);
  1077. msleep(25);
  1078. powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
  1079. writel(powerstate, base + NvRegPowerState2);
  1080. msleep(25);
  1081. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
  1082. reg |= PHY_REALTEK_INIT9;
  1083. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
  1084. return PHY_ERROR;
  1085. if (mii_rw(dev, np->phyaddr,
  1086. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
  1087. return PHY_ERROR;
  1088. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
  1089. if (!(reg & PHY_REALTEK_INIT11)) {
  1090. reg |= PHY_REALTEK_INIT11;
  1091. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
  1092. return PHY_ERROR;
  1093. }
  1094. if (mii_rw(dev, np->phyaddr,
  1095. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
  1096. return PHY_ERROR;
  1097. return 0;
  1098. }
  1099. static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
  1100. {
  1101. u32 phy_reserved;
  1102. if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
  1103. phy_reserved = mii_rw(dev, np->phyaddr,
  1104. PHY_REALTEK_INIT_REG6, MII_READ);
  1105. phy_reserved |= PHY_REALTEK_INIT7;
  1106. if (mii_rw(dev, np->phyaddr,
  1107. PHY_REALTEK_INIT_REG6, phy_reserved))
  1108. return PHY_ERROR;
  1109. }
  1110. return 0;
  1111. }
  1112. static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
  1113. {
  1114. u32 phy_reserved;
  1115. if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  1116. if (mii_rw(dev, np->phyaddr,
  1117. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
  1118. return PHY_ERROR;
  1119. phy_reserved = mii_rw(dev, np->phyaddr,
  1120. PHY_REALTEK_INIT_REG2, MII_READ);
  1121. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  1122. phy_reserved |= PHY_REALTEK_INIT3;
  1123. if (mii_rw(dev, np->phyaddr,
  1124. PHY_REALTEK_INIT_REG2, phy_reserved))
  1125. return PHY_ERROR;
  1126. if (mii_rw(dev, np->phyaddr,
  1127. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
  1128. return PHY_ERROR;
  1129. }
  1130. return 0;
  1131. }
  1132. static int init_cicada(struct net_device *dev, struct fe_priv *np,
  1133. u32 phyinterface)
  1134. {
  1135. u32 phy_reserved;
  1136. if (phyinterface & PHY_RGMII) {
  1137. phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
  1138. phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
  1139. phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
  1140. if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
  1141. return PHY_ERROR;
  1142. phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1143. phy_reserved |= PHY_CICADA_INIT5;
  1144. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
  1145. return PHY_ERROR;
  1146. }
  1147. phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
  1148. phy_reserved |= PHY_CICADA_INIT6;
  1149. if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
  1150. return PHY_ERROR;
  1151. return 0;
  1152. }
  1153. static int init_vitesse(struct net_device *dev, struct fe_priv *np)
  1154. {
  1155. u32 phy_reserved;
  1156. if (mii_rw(dev, np->phyaddr,
  1157. PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
  1158. return PHY_ERROR;
  1159. if (mii_rw(dev, np->phyaddr,
  1160. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
  1161. return PHY_ERROR;
  1162. phy_reserved = mii_rw(dev, np->phyaddr,
  1163. PHY_VITESSE_INIT_REG4, MII_READ);
  1164. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1165. return PHY_ERROR;
  1166. phy_reserved = mii_rw(dev, np->phyaddr,
  1167. PHY_VITESSE_INIT_REG3, MII_READ);
  1168. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1169. phy_reserved |= PHY_VITESSE_INIT3;
  1170. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1171. return PHY_ERROR;
  1172. if (mii_rw(dev, np->phyaddr,
  1173. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
  1174. return PHY_ERROR;
  1175. if (mii_rw(dev, np->phyaddr,
  1176. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
  1177. return PHY_ERROR;
  1178. phy_reserved = mii_rw(dev, np->phyaddr,
  1179. PHY_VITESSE_INIT_REG4, MII_READ);
  1180. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1181. phy_reserved |= PHY_VITESSE_INIT3;
  1182. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1183. return PHY_ERROR;
  1184. phy_reserved = mii_rw(dev, np->phyaddr,
  1185. PHY_VITESSE_INIT_REG3, MII_READ);
  1186. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1187. return PHY_ERROR;
  1188. if (mii_rw(dev, np->phyaddr,
  1189. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
  1190. return PHY_ERROR;
  1191. if (mii_rw(dev, np->phyaddr,
  1192. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
  1193. return PHY_ERROR;
  1194. phy_reserved = mii_rw(dev, np->phyaddr,
  1195. PHY_VITESSE_INIT_REG4, MII_READ);
  1196. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1197. return PHY_ERROR;
  1198. phy_reserved = mii_rw(dev, np->phyaddr,
  1199. PHY_VITESSE_INIT_REG3, MII_READ);
  1200. phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
  1201. phy_reserved |= PHY_VITESSE_INIT8;
  1202. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1203. return PHY_ERROR;
  1204. if (mii_rw(dev, np->phyaddr,
  1205. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
  1206. return PHY_ERROR;
  1207. if (mii_rw(dev, np->phyaddr,
  1208. PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
  1209. return PHY_ERROR;
  1210. return 0;
  1211. }
  1212. static int phy_init(struct net_device *dev)
  1213. {
  1214. struct fe_priv *np = get_nvpriv(dev);
  1215. u8 __iomem *base = get_hwbase(dev);
  1216. u32 phyinterface;
  1217. u32 mii_status, mii_control, mii_control_1000, reg;
  1218. /* phy errata for E3016 phy */
  1219. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  1220. reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1221. reg &= ~PHY_MARVELL_E3016_INITMASK;
  1222. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
  1223. netdev_info(dev, "%s: phy write to errata reg failed\n",
  1224. pci_name(np->pci_dev));
  1225. return PHY_ERROR;
  1226. }
  1227. }
  1228. if (np->phy_oui == PHY_OUI_REALTEK) {
  1229. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1230. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1231. if (init_realtek_8211b(dev, np)) {
  1232. netdev_info(dev, "%s: phy init failed\n",
  1233. pci_name(np->pci_dev));
  1234. return PHY_ERROR;
  1235. }
  1236. } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1237. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1238. if (init_realtek_8211c(dev, np)) {
  1239. netdev_info(dev, "%s: phy init failed\n",
  1240. pci_name(np->pci_dev));
  1241. return PHY_ERROR;
  1242. }
  1243. } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1244. if (init_realtek_8201(dev, np)) {
  1245. netdev_info(dev, "%s: phy init failed\n",
  1246. pci_name(np->pci_dev));
  1247. return PHY_ERROR;
  1248. }
  1249. }
  1250. }
  1251. /* set advertise register */
  1252. reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1253. reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1254. ADVERTISE_100HALF | ADVERTISE_100FULL |
  1255. ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
  1256. if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
  1257. netdev_info(dev, "%s: phy write to advertise failed\n",
  1258. pci_name(np->pci_dev));
  1259. return PHY_ERROR;
  1260. }
  1261. /* get phy interface type */
  1262. phyinterface = readl(base + NvRegPhyInterface);
  1263. /* see if gigabit phy */
  1264. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1265. if (mii_status & PHY_GIGABIT) {
  1266. np->gigabit = PHY_GIGABIT;
  1267. mii_control_1000 = mii_rw(dev, np->phyaddr,
  1268. MII_CTRL1000, MII_READ);
  1269. mii_control_1000 &= ~ADVERTISE_1000HALF;
  1270. if (phyinterface & PHY_RGMII)
  1271. mii_control_1000 |= ADVERTISE_1000FULL;
  1272. else
  1273. mii_control_1000 &= ~ADVERTISE_1000FULL;
  1274. if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
  1275. netdev_info(dev, "%s: phy init failed\n",
  1276. pci_name(np->pci_dev));
  1277. return PHY_ERROR;
  1278. }
  1279. } else
  1280. np->gigabit = 0;
  1281. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1282. mii_control |= BMCR_ANENABLE;
  1283. if (np->phy_oui == PHY_OUI_REALTEK &&
  1284. np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1285. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1286. /* start autoneg since we already performed hw reset above */
  1287. mii_control |= BMCR_ANRESTART;
  1288. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  1289. netdev_info(dev, "%s: phy init failed\n",
  1290. pci_name(np->pci_dev));
  1291. return PHY_ERROR;
  1292. }
  1293. } else {
  1294. /* reset the phy
  1295. * (certain phys need bmcr to be setup with reset)
  1296. */
  1297. if (phy_reset(dev, mii_control)) {
  1298. netdev_info(dev, "%s: phy reset failed\n",
  1299. pci_name(np->pci_dev));
  1300. return PHY_ERROR;
  1301. }
  1302. }
  1303. /* phy vendor specific configuration */
  1304. if ((np->phy_oui == PHY_OUI_CICADA)) {
  1305. if (init_cicada(dev, np, phyinterface)) {
  1306. netdev_info(dev, "%s: phy init failed\n",
  1307. pci_name(np->pci_dev));
  1308. return PHY_ERROR;
  1309. }
  1310. } else if (np->phy_oui == PHY_OUI_VITESSE) {
  1311. if (init_vitesse(dev, np)) {
  1312. netdev_info(dev, "%s: phy init failed\n",
  1313. pci_name(np->pci_dev));
  1314. return PHY_ERROR;
  1315. }
  1316. } else if (np->phy_oui == PHY_OUI_REALTEK) {
  1317. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1318. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1319. /* reset could have cleared these out, set them back */
  1320. if (init_realtek_8211b(dev, np)) {
  1321. netdev_info(dev, "%s: phy init failed\n",
  1322. pci_name(np->pci_dev));
  1323. return PHY_ERROR;
  1324. }
  1325. } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1326. if (init_realtek_8201(dev, np) ||
  1327. init_realtek_8201_cross(dev, np)) {
  1328. netdev_info(dev, "%s: phy init failed\n",
  1329. pci_name(np->pci_dev));
  1330. return PHY_ERROR;
  1331. }
  1332. }
  1333. }
  1334. /* some phys clear out pause advertisement on reset, set it back */
  1335. mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
  1336. /* restart auto negotiation, power down phy */
  1337. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1338. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  1339. if (phy_power_down)
  1340. mii_control |= BMCR_PDOWN;
  1341. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
  1342. return PHY_ERROR;
  1343. return 0;
  1344. }
  1345. static void nv_start_rx(struct net_device *dev)
  1346. {
  1347. struct fe_priv *np = netdev_priv(dev);
  1348. u8 __iomem *base = get_hwbase(dev);
  1349. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1350. /* Already running? Stop it. */
  1351. if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
  1352. rx_ctrl &= ~NVREG_RCVCTL_START;
  1353. writel(rx_ctrl, base + NvRegReceiverControl);
  1354. pci_push(base);
  1355. }
  1356. writel(np->linkspeed, base + NvRegLinkSpeed);
  1357. pci_push(base);
  1358. rx_ctrl |= NVREG_RCVCTL_START;
  1359. if (np->mac_in_use)
  1360. rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
  1361. writel(rx_ctrl, base + NvRegReceiverControl);
  1362. pci_push(base);
  1363. }
  1364. static void nv_stop_rx(struct net_device *dev)
  1365. {
  1366. struct fe_priv *np = netdev_priv(dev);
  1367. u8 __iomem *base = get_hwbase(dev);
  1368. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1369. if (!np->mac_in_use)
  1370. rx_ctrl &= ~NVREG_RCVCTL_START;
  1371. else
  1372. rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
  1373. writel(rx_ctrl, base + NvRegReceiverControl);
  1374. if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
  1375. NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
  1376. netdev_info(dev, "%s: ReceiverStatus remained busy\n",
  1377. __func__);
  1378. udelay(NV_RXSTOP_DELAY2);
  1379. if (!np->mac_in_use)
  1380. writel(0, base + NvRegLinkSpeed);
  1381. }
  1382. static void nv_start_tx(struct net_device *dev)
  1383. {
  1384. struct fe_priv *np = netdev_priv(dev);
  1385. u8 __iomem *base = get_hwbase(dev);
  1386. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1387. tx_ctrl |= NVREG_XMITCTL_START;
  1388. if (np->mac_in_use)
  1389. tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
  1390. writel(tx_ctrl, base + NvRegTransmitterControl);
  1391. pci_push(base);
  1392. }
  1393. static void nv_stop_tx(struct net_device *dev)
  1394. {
  1395. struct fe_priv *np = netdev_priv(dev);
  1396. u8 __iomem *base = get_hwbase(dev);
  1397. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1398. if (!np->mac_in_use)
  1399. tx_ctrl &= ~NVREG_XMITCTL_START;
  1400. else
  1401. tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
  1402. writel(tx_ctrl, base + NvRegTransmitterControl);
  1403. if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
  1404. NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
  1405. netdev_info(dev, "%s: TransmitterStatus remained busy\n",
  1406. __func__);
  1407. udelay(NV_TXSTOP_DELAY2);
  1408. if (!np->mac_in_use)
  1409. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  1410. base + NvRegTransmitPoll);
  1411. }
  1412. static void nv_start_rxtx(struct net_device *dev)
  1413. {
  1414. nv_start_rx(dev);
  1415. nv_start_tx(dev);
  1416. }
  1417. static void nv_stop_rxtx(struct net_device *dev)
  1418. {
  1419. nv_stop_rx(dev);
  1420. nv_stop_tx(dev);
  1421. }
  1422. static void nv_txrx_reset(struct net_device *dev)
  1423. {
  1424. struct fe_priv *np = netdev_priv(dev);
  1425. u8 __iomem *base = get_hwbase(dev);
  1426. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1427. pci_push(base);
  1428. udelay(NV_TXRX_RESET_DELAY);
  1429. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1430. pci_push(base);
  1431. }
  1432. static void nv_mac_reset(struct net_device *dev)
  1433. {
  1434. struct fe_priv *np = netdev_priv(dev);
  1435. u8 __iomem *base = get_hwbase(dev);
  1436. u32 temp1, temp2, temp3;
  1437. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1438. pci_push(base);
  1439. /* save registers since they will be cleared on reset */
  1440. temp1 = readl(base + NvRegMacAddrA);
  1441. temp2 = readl(base + NvRegMacAddrB);
  1442. temp3 = readl(base + NvRegTransmitPoll);
  1443. writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
  1444. pci_push(base);
  1445. udelay(NV_MAC_RESET_DELAY);
  1446. writel(0, base + NvRegMacReset);
  1447. pci_push(base);
  1448. udelay(NV_MAC_RESET_DELAY);
  1449. /* restore saved registers */
  1450. writel(temp1, base + NvRegMacAddrA);
  1451. writel(temp2, base + NvRegMacAddrB);
  1452. writel(temp3, base + NvRegTransmitPoll);
  1453. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1454. pci_push(base);
  1455. }
  1456. static void nv_get_hw_stats(struct net_device *dev)
  1457. {
  1458. struct fe_priv *np = netdev_priv(dev);
  1459. u8 __iomem *base = get_hwbase(dev);
  1460. np->estats.tx_bytes += readl(base + NvRegTxCnt);
  1461. np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
  1462. np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
  1463. np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
  1464. np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
  1465. np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
  1466. np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
  1467. np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
  1468. np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
  1469. np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
  1470. np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
  1471. np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
  1472. np->estats.rx_runt += readl(base + NvRegRxRunt);
  1473. np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
  1474. np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
  1475. np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
  1476. np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
  1477. np->estats.rx_length_error += readl(base + NvRegRxLenErr);
  1478. np->estats.rx_unicast += readl(base + NvRegRxUnicast);
  1479. np->estats.rx_multicast += readl(base + NvRegRxMulticast);
  1480. np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
  1481. np->estats.rx_packets =
  1482. np->estats.rx_unicast +
  1483. np->estats.rx_multicast +
  1484. np->estats.rx_broadcast;
  1485. np->estats.rx_errors_total =
  1486. np->estats.rx_crc_errors +
  1487. np->estats.rx_over_errors +
  1488. np->estats.rx_frame_error +
  1489. (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
  1490. np->estats.rx_late_collision +
  1491. np->estats.rx_runt +
  1492. np->estats.rx_frame_too_long;
  1493. np->estats.tx_errors_total =
  1494. np->estats.tx_late_collision +
  1495. np->estats.tx_fifo_errors +
  1496. np->estats.tx_carrier_errors +
  1497. np->estats.tx_excess_deferral +
  1498. np->estats.tx_retry_error;
  1499. if (np->driver_data & DEV_HAS_STATISTICS_V2) {
  1500. np->estats.tx_deferral += readl(base + NvRegTxDef);
  1501. np->estats.tx_packets += readl(base + NvRegTxFrame);
  1502. np->estats.rx_bytes += readl(base + NvRegRxCnt);
  1503. np->estats.tx_pause += readl(base + NvRegTxPause);
  1504. np->estats.rx_pause += readl(base + NvRegRxPause);
  1505. np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
  1506. }
  1507. if (np->driver_data & DEV_HAS_STATISTICS_V3) {
  1508. np->estats.tx_unicast += readl(base + NvRegTxUnicast);
  1509. np->estats.tx_multicast += readl(base + NvRegTxMulticast);
  1510. np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
  1511. }
  1512. }
  1513. /*
  1514. * nv_get_stats: dev->get_stats function
  1515. * Get latest stats value from the nic.
  1516. * Called with read_lock(&dev_base_lock) held for read -
  1517. * only synchronized against unregister_netdevice.
  1518. */
  1519. static struct net_device_stats *nv_get_stats(struct net_device *dev)
  1520. {
  1521. struct fe_priv *np = netdev_priv(dev);
  1522. /* If the nic supports hw counters then retrieve latest values */
  1523. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
  1524. nv_get_hw_stats(dev);
  1525. /* copy to net_device stats */
  1526. dev->stats.tx_bytes = np->estats.tx_bytes;
  1527. dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
  1528. dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
  1529. dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
  1530. dev->stats.rx_over_errors = np->estats.rx_over_errors;
  1531. dev->stats.rx_errors = np->estats.rx_errors_total;
  1532. dev->stats.tx_errors = np->estats.tx_errors_total;
  1533. }
  1534. return &dev->stats;
  1535. }
  1536. /*
  1537. * nv_alloc_rx: fill rx ring entries.
  1538. * Return 1 if the allocations for the skbs failed and the
  1539. * rx engine is without Available descriptors
  1540. */
  1541. static int nv_alloc_rx(struct net_device *dev)
  1542. {
  1543. struct fe_priv *np = netdev_priv(dev);
  1544. struct ring_desc *less_rx;
  1545. less_rx = np->get_rx.orig;
  1546. if (less_rx-- == np->first_rx.orig)
  1547. less_rx = np->last_rx.orig;
  1548. while (np->put_rx.orig != less_rx) {
  1549. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1550. if (skb) {
  1551. np->put_rx_ctx->skb = skb;
  1552. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1553. skb->data,
  1554. skb_tailroom(skb),
  1555. PCI_DMA_FROMDEVICE);
  1556. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1557. np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
  1558. wmb();
  1559. np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
  1560. if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
  1561. np->put_rx.orig = np->first_rx.orig;
  1562. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1563. np->put_rx_ctx = np->first_rx_ctx;
  1564. } else
  1565. return 1;
  1566. }
  1567. return 0;
  1568. }
  1569. static int nv_alloc_rx_optimized(struct net_device *dev)
  1570. {
  1571. struct fe_priv *np = netdev_priv(dev);
  1572. struct ring_desc_ex *less_rx;
  1573. less_rx = np->get_rx.ex;
  1574. if (less_rx-- == np->first_rx.ex)
  1575. less_rx = np->last_rx.ex;
  1576. while (np->put_rx.ex != less_rx) {
  1577. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1578. if (skb) {
  1579. np->put_rx_ctx->skb = skb;
  1580. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1581. skb->data,
  1582. skb_tailroom(skb),
  1583. PCI_DMA_FROMDEVICE);
  1584. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1585. np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
  1586. np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
  1587. wmb();
  1588. np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
  1589. if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
  1590. np->put_rx.ex = np->first_rx.ex;
  1591. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1592. np->put_rx_ctx = np->first_rx_ctx;
  1593. } else
  1594. return 1;
  1595. }
  1596. return 0;
  1597. }
  1598. /* If rx bufs are exhausted called after 50ms to attempt to refresh */
  1599. static void nv_do_rx_refill(unsigned long data)
  1600. {
  1601. struct net_device *dev = (struct net_device *) data;
  1602. struct fe_priv *np = netdev_priv(dev);
  1603. /* Just reschedule NAPI rx processing */
  1604. napi_schedule(&np->napi);
  1605. }
  1606. static void nv_init_rx(struct net_device *dev)
  1607. {
  1608. struct fe_priv *np = netdev_priv(dev);
  1609. int i;
  1610. np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
  1611. if (!nv_optimized(np))
  1612. np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
  1613. else
  1614. np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
  1615. np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
  1616. np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
  1617. for (i = 0; i < np->rx_ring_size; i++) {
  1618. if (!nv_optimized(np)) {
  1619. np->rx_ring.orig[i].flaglen = 0;
  1620. np->rx_ring.orig[i].buf = 0;
  1621. } else {
  1622. np->rx_ring.ex[i].flaglen = 0;
  1623. np->rx_ring.ex[i].txvlan = 0;
  1624. np->rx_ring.ex[i].bufhigh = 0;
  1625. np->rx_ring.ex[i].buflow = 0;
  1626. }
  1627. np->rx_skb[i].skb = NULL;
  1628. np->rx_skb[i].dma = 0;
  1629. }
  1630. }
  1631. static void nv_init_tx(struct net_device *dev)
  1632. {
  1633. struct fe_priv *np = netdev_priv(dev);
  1634. int i;
  1635. np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
  1636. if (!nv_optimized(np))
  1637. np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
  1638. else
  1639. np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
  1640. np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
  1641. np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
  1642. np->tx_pkts_in_progress = 0;
  1643. np->tx_change_owner = NULL;
  1644. np->tx_end_flip = NULL;
  1645. np->tx_stop = 0;
  1646. for (i = 0; i < np->tx_ring_size; i++) {
  1647. if (!nv_optimized(np)) {
  1648. np->tx_ring.orig[i].flaglen = 0;
  1649. np->tx_ring.orig[i].buf = 0;
  1650. } else {
  1651. np->tx_ring.ex[i].flaglen = 0;
  1652. np->tx_ring.ex[i].txvlan = 0;
  1653. np->tx_ring.ex[i].bufhigh = 0;
  1654. np->tx_ring.ex[i].buflow = 0;
  1655. }
  1656. np->tx_skb[i].skb = NULL;
  1657. np->tx_skb[i].dma = 0;
  1658. np->tx_skb[i].dma_len = 0;
  1659. np->tx_skb[i].dma_single = 0;
  1660. np->tx_skb[i].first_tx_desc = NULL;
  1661. np->tx_skb[i].next_tx_ctx = NULL;
  1662. }
  1663. }
  1664. static int nv_init_ring(struct net_device *dev)
  1665. {
  1666. struct fe_priv *np = netdev_priv(dev);
  1667. nv_init_tx(dev);
  1668. nv_init_rx(dev);
  1669. if (!nv_optimized(np))
  1670. return nv_alloc_rx(dev);
  1671. else
  1672. return nv_alloc_rx_optimized(dev);
  1673. }
  1674. static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1675. {
  1676. if (tx_skb->dma) {
  1677. if (tx_skb->dma_single)
  1678. pci_unmap_single(np->pci_dev, tx_skb->dma,
  1679. tx_skb->dma_len,
  1680. PCI_DMA_TODEVICE);
  1681. else
  1682. pci_unmap_page(np->pci_dev, tx_skb->dma,
  1683. tx_skb->dma_len,
  1684. PCI_DMA_TODEVICE);
  1685. tx_skb->dma = 0;
  1686. }
  1687. }
  1688. static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1689. {
  1690. nv_unmap_txskb(np, tx_skb);
  1691. if (tx_skb->skb) {
  1692. dev_kfree_skb_any(tx_skb->skb);
  1693. tx_skb->skb = NULL;
  1694. return 1;
  1695. }
  1696. return 0;
  1697. }
  1698. static void nv_drain_tx(struct net_device *dev)
  1699. {
  1700. struct fe_priv *np = netdev_priv(dev);
  1701. unsigned int i;
  1702. for (i = 0; i < np->tx_ring_size; i++) {
  1703. if (!nv_optimized(np)) {
  1704. np->tx_ring.orig[i].flaglen = 0;
  1705. np->tx_ring.orig[i].buf = 0;
  1706. } else {
  1707. np->tx_ring.ex[i].flaglen = 0;
  1708. np->tx_ring.ex[i].txvlan = 0;
  1709. np->tx_ring.ex[i].bufhigh = 0;
  1710. np->tx_ring.ex[i].buflow = 0;
  1711. }
  1712. if (nv_release_txskb(np, &np->tx_skb[i]))
  1713. dev->stats.tx_dropped++;
  1714. np->tx_skb[i].dma = 0;
  1715. np->tx_skb[i].dma_len = 0;
  1716. np->tx_skb[i].dma_single = 0;
  1717. np->tx_skb[i].first_tx_desc = NULL;
  1718. np->tx_skb[i].next_tx_ctx = NULL;
  1719. }
  1720. np->tx_pkts_in_progress = 0;
  1721. np->tx_change_owner = NULL;
  1722. np->tx_end_flip = NULL;
  1723. }
  1724. static void nv_drain_rx(struct net_device *dev)
  1725. {
  1726. struct fe_priv *np = netdev_priv(dev);
  1727. int i;
  1728. for (i = 0; i < np->rx_ring_size; i++) {
  1729. if (!nv_optimized(np)) {
  1730. np->rx_ring.orig[i].flaglen = 0;
  1731. np->rx_ring.orig[i].buf = 0;
  1732. } else {
  1733. np->rx_ring.ex[i].flaglen = 0;
  1734. np->rx_ring.ex[i].txvlan = 0;
  1735. np->rx_ring.ex[i].bufhigh = 0;
  1736. np->rx_ring.ex[i].buflow = 0;
  1737. }
  1738. wmb();
  1739. if (np->rx_skb[i].skb) {
  1740. pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
  1741. (skb_end_pointer(np->rx_skb[i].skb) -
  1742. np->rx_skb[i].skb->data),
  1743. PCI_DMA_FROMDEVICE);
  1744. dev_kfree_skb(np->rx_skb[i].skb);
  1745. np->rx_skb[i].skb = NULL;
  1746. }
  1747. }
  1748. }
  1749. static void nv_drain_rxtx(struct net_device *dev)
  1750. {
  1751. nv_drain_tx(dev);
  1752. nv_drain_rx(dev);
  1753. }
  1754. static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
  1755. {
  1756. return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
  1757. }
  1758. static void nv_legacybackoff_reseed(struct net_device *dev)
  1759. {
  1760. u8 __iomem *base = get_hwbase(dev);
  1761. u32 reg;
  1762. u32 low;
  1763. int tx_status = 0;
  1764. reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
  1765. get_random_bytes(&low, sizeof(low));
  1766. reg |= low & NVREG_SLOTTIME_MASK;
  1767. /* Need to stop tx before change takes effect.
  1768. * Caller has already gained np->lock.
  1769. */
  1770. tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
  1771. if (tx_status)
  1772. nv_stop_tx(dev);
  1773. nv_stop_rx(dev);
  1774. writel(reg, base + NvRegSlotTime);
  1775. if (tx_status)
  1776. nv_start_tx(dev);
  1777. nv_start_rx(dev);
  1778. }
  1779. /* Gear Backoff Seeds */
  1780. #define BACKOFF_SEEDSET_ROWS 8
  1781. #define BACKOFF_SEEDSET_LFSRS 15
  1782. /* Known Good seed sets */
  1783. static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1784. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1785. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
  1786. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1787. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
  1788. {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
  1789. {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
  1790. {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
  1791. {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
  1792. static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1793. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1794. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1795. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
  1796. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1797. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1798. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1799. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1800. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
  1801. static void nv_gear_backoff_reseed(struct net_device *dev)
  1802. {
  1803. u8 __iomem *base = get_hwbase(dev);
  1804. u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
  1805. u32 temp, seedset, combinedSeed;
  1806. int i;
  1807. /* Setup seed for free running LFSR */
  1808. /* We are going to read the time stamp counter 3 times
  1809. and swizzle bits around to increase randomness */
  1810. get_random_bytes(&miniseed1, sizeof(miniseed1));
  1811. miniseed1 &= 0x0fff;
  1812. if (miniseed1 == 0)
  1813. miniseed1 = 0xabc;
  1814. get_random_bytes(&miniseed2, sizeof(miniseed2));
  1815. miniseed2 &= 0x0fff;
  1816. if (miniseed2 == 0)
  1817. miniseed2 = 0xabc;
  1818. miniseed2_reversed =
  1819. ((miniseed2 & 0xF00) >> 8) |
  1820. (miniseed2 & 0x0F0) |
  1821. ((miniseed2 & 0x00F) << 8);
  1822. get_random_bytes(&miniseed3, sizeof(miniseed3));
  1823. miniseed3 &= 0x0fff;
  1824. if (miniseed3 == 0)
  1825. miniseed3 = 0xabc;
  1826. miniseed3_reversed =
  1827. ((miniseed3 & 0xF00) >> 8) |
  1828. (miniseed3 & 0x0F0) |
  1829. ((miniseed3 & 0x00F) << 8);
  1830. combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
  1831. (miniseed2 ^ miniseed3_reversed);
  1832. /* Seeds can not be zero */
  1833. if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
  1834. combinedSeed |= 0x08;
  1835. if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
  1836. combinedSeed |= 0x8000;
  1837. /* No need to disable tx here */
  1838. temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
  1839. temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
  1840. temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
  1841. writel(temp, base + NvRegBackOffControl);
  1842. /* Setup seeds for all gear LFSRs. */
  1843. get_random_bytes(&seedset, sizeof(seedset));
  1844. seedset = seedset % BACKOFF_SEEDSET_ROWS;
  1845. for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
  1846. temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
  1847. temp |= main_seedset[seedset][i-1] & 0x3ff;
  1848. temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
  1849. writel(temp, base + NvRegBackOffControl);
  1850. }
  1851. }
  1852. /*
  1853. * nv_start_xmit: dev->hard_start_xmit function
  1854. * Called with netif_tx_lock held.
  1855. */
  1856. static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1857. {
  1858. struct fe_priv *np = netdev_priv(dev);
  1859. u32 tx_flags = 0;
  1860. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  1861. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1862. unsigned int i;
  1863. u32 offset = 0;
  1864. u32 bcnt;
  1865. u32 size = skb_headlen(skb);
  1866. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1867. u32 empty_slots;
  1868. struct ring_desc *put_tx;
  1869. struct ring_desc *start_tx;
  1870. struct ring_desc *prev_tx;
  1871. struct nv_skb_map *prev_tx_ctx;
  1872. unsigned long flags;
  1873. /* add fragments to entries count */
  1874. for (i = 0; i < fragments; i++) {
  1875. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1876. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1877. }
  1878. spin_lock_irqsave(&np->lock, flags);
  1879. empty_slots = nv_get_empty_tx_slots(np);
  1880. if (unlikely(empty_slots <= entries)) {
  1881. netif_stop_queue(dev);
  1882. np->tx_stop = 1;
  1883. spin_unlock_irqrestore(&np->lock, flags);
  1884. return NETDEV_TX_BUSY;
  1885. }
  1886. spin_unlock_irqrestore(&np->lock, flags);
  1887. start_tx = put_tx = np->put_tx.orig;
  1888. /* setup the header buffer */
  1889. do {
  1890. prev_tx = put_tx;
  1891. prev_tx_ctx = np->put_tx_ctx;
  1892. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1893. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1894. PCI_DMA_TODEVICE);
  1895. np->put_tx_ctx->dma_len = bcnt;
  1896. np->put_tx_ctx->dma_single = 1;
  1897. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1898. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1899. tx_flags = np->tx_flags;
  1900. offset += bcnt;
  1901. size -= bcnt;
  1902. if (unlikely(put_tx++ == np->last_tx.orig))
  1903. put_tx = np->first_tx.orig;
  1904. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1905. np->put_tx_ctx = np->first_tx_ctx;
  1906. } while (size);
  1907. /* setup the fragments */
  1908. for (i = 0; i < fragments; i++) {
  1909. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1910. u32 size = frag->size;
  1911. offset = 0;
  1912. do {
  1913. prev_tx = put_tx;
  1914. prev_tx_ctx = np->put_tx_ctx;
  1915. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1916. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  1917. PCI_DMA_TODEVICE);
  1918. np->put_tx_ctx->dma_len = bcnt;
  1919. np->put_tx_ctx->dma_single = 0;
  1920. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1921. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1922. offset += bcnt;
  1923. size -= bcnt;
  1924. if (unlikely(put_tx++ == np->last_tx.orig))
  1925. put_tx = np->first_tx.orig;
  1926. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1927. np->put_tx_ctx = np->first_tx_ctx;
  1928. } while (size);
  1929. }
  1930. /* set last fragment flag */
  1931. prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
  1932. /* save skb in this slot's context area */
  1933. prev_tx_ctx->skb = skb;
  1934. if (skb_is_gso(skb))
  1935. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  1936. else
  1937. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  1938. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  1939. spin_lock_irqsave(&np->lock, flags);
  1940. /* set tx flags */
  1941. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  1942. np->put_tx.orig = put_tx;
  1943. spin_unlock_irqrestore(&np->lock, flags);
  1944. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  1945. return NETDEV_TX_OK;
  1946. }
  1947. static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
  1948. struct net_device *dev)
  1949. {
  1950. struct fe_priv *np = netdev_priv(dev);
  1951. u32 tx_flags = 0;
  1952. u32 tx_flags_extra;
  1953. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1954. unsigned int i;
  1955. u32 offset = 0;
  1956. u32 bcnt;
  1957. u32 size = skb_headlen(skb);
  1958. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1959. u32 empty_slots;
  1960. struct ring_desc_ex *put_tx;
  1961. struct ring_desc_ex *start_tx;
  1962. struct ring_desc_ex *prev_tx;
  1963. struct nv_skb_map *prev_tx_ctx;
  1964. struct nv_skb_map *start_tx_ctx;
  1965. unsigned long flags;
  1966. /* add fragments to entries count */
  1967. for (i = 0; i < fragments; i++) {
  1968. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1969. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1970. }
  1971. spin_lock_irqsave(&np->lock, flags);
  1972. empty_slots = nv_get_empty_tx_slots(np);
  1973. if (unlikely(empty_slots <= entries)) {
  1974. netif_stop_queue(dev);
  1975. np->tx_stop = 1;
  1976. spin_unlock_irqrestore(&np->lock, flags);
  1977. return NETDEV_TX_BUSY;
  1978. }
  1979. spin_unlock_irqrestore(&np->lock, flags);
  1980. start_tx = put_tx = np->put_tx.ex;
  1981. start_tx_ctx = np->put_tx_ctx;
  1982. /* setup the header buffer */
  1983. do {
  1984. prev_tx = put_tx;
  1985. prev_tx_ctx = np->put_tx_ctx;
  1986. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1987. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1988. PCI_DMA_TODEVICE);
  1989. np->put_tx_ctx->dma_len = bcnt;
  1990. np->put_tx_ctx->dma_single = 1;
  1991. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  1992. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  1993. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1994. tx_flags = NV_TX2_VALID;
  1995. offset += bcnt;
  1996. size -= bcnt;
  1997. if (unlikely(put_tx++ == np->last_tx.ex))
  1998. put_tx = np->first_tx.ex;
  1999. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2000. np->put_tx_ctx = np->first_tx_ctx;
  2001. } while (size);
  2002. /* setup the fragments */
  2003. for (i = 0; i < fragments; i++) {
  2004. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2005. u32 size = frag->size;
  2006. offset = 0;
  2007. do {
  2008. prev_tx = put_tx;
  2009. prev_tx_ctx = np->put_tx_ctx;
  2010. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  2011. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  2012. PCI_DMA_TODEVICE);
  2013. np->put_tx_ctx->dma_len = bcnt;
  2014. np->put_tx_ctx->dma_single = 0;
  2015. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  2016. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  2017. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  2018. offset += bcnt;
  2019. size -= bcnt;
  2020. if (unlikely(put_tx++ == np->last_tx.ex))
  2021. put_tx = np->first_tx.ex;
  2022. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2023. np->put_tx_ctx = np->first_tx_ctx;
  2024. } while (size);
  2025. }
  2026. /* set last fragment flag */
  2027. prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
  2028. /* save skb in this slot's context area */
  2029. prev_tx_ctx->skb = skb;
  2030. if (skb_is_gso(skb))
  2031. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  2032. else
  2033. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  2034. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  2035. /* vlan tag */
  2036. if (vlan_tx_tag_present(skb))
  2037. start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
  2038. vlan_tx_tag_get(skb));
  2039. else
  2040. start_tx->txvlan = 0;
  2041. spin_lock_irqsave(&np->lock, flags);
  2042. if (np->tx_limit) {
  2043. /* Limit the number of outstanding tx. Setup all fragments, but
  2044. * do not set the VALID bit on the first descriptor. Save a pointer
  2045. * to that descriptor and also for next skb_map element.
  2046. */
  2047. if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
  2048. if (!np->tx_change_owner)
  2049. np->tx_change_owner = start_tx_ctx;
  2050. /* remove VALID bit */
  2051. tx_flags &= ~NV_TX2_VALID;
  2052. start_tx_ctx->first_tx_desc = start_tx;
  2053. start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
  2054. np->tx_end_flip = np->put_tx_ctx;
  2055. } else {
  2056. np->tx_pkts_in_progress++;
  2057. }
  2058. }
  2059. /* set tx flags */
  2060. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  2061. np->put_tx.ex = put_tx;
  2062. spin_unlock_irqrestore(&np->lock, flags);
  2063. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2064. return NETDEV_TX_OK;
  2065. }
  2066. static inline void nv_tx_flip_ownership(struct net_device *dev)
  2067. {
  2068. struct fe_priv *np = netdev_priv(dev);
  2069. np->tx_pkts_in_progress--;
  2070. if (np->tx_change_owner) {
  2071. np->tx_change_owner->first_tx_desc->flaglen |=
  2072. cpu_to_le32(NV_TX2_VALID);
  2073. np->tx_pkts_in_progress++;
  2074. np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
  2075. if (np->tx_change_owner == np->tx_end_flip)
  2076. np->tx_change_owner = NULL;
  2077. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2078. }
  2079. }
  2080. /*
  2081. * nv_tx_done: check for completed packets, release the skbs.
  2082. *
  2083. * Caller must own np->lock.
  2084. */
  2085. static int nv_tx_done(struct net_device *dev, int limit)
  2086. {
  2087. struct fe_priv *np = netdev_priv(dev);
  2088. u32 flags;
  2089. int tx_work = 0;
  2090. struct ring_desc *orig_get_tx = np->get_tx.orig;
  2091. while ((np->get_tx.orig != np->put_tx.orig) &&
  2092. !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
  2093. (tx_work < limit)) {
  2094. nv_unmap_txskb(np, np->get_tx_ctx);
  2095. if (np->desc_ver == DESC_VER_1) {
  2096. if (flags & NV_TX_LASTPACKET) {
  2097. if (flags & NV_TX_ERROR) {
  2098. if (flags & NV_TX_UNDERFLOW)
  2099. dev->stats.tx_fifo_errors++;
  2100. if (flags & NV_TX_CARRIERLOST)
  2101. dev->stats.tx_carrier_errors++;
  2102. if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
  2103. nv_legacybackoff_reseed(dev);
  2104. dev->stats.tx_errors++;
  2105. } else {
  2106. dev->stats.tx_packets++;
  2107. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2108. }
  2109. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2110. np->get_tx_ctx->skb = NULL;
  2111. tx_work++;
  2112. }
  2113. } else {
  2114. if (flags & NV_TX2_LASTPACKET) {
  2115. if (flags & NV_TX2_ERROR) {
  2116. if (flags & NV_TX2_UNDERFLOW)
  2117. dev->stats.tx_fifo_errors++;
  2118. if (flags & NV_TX2_CARRIERLOST)
  2119. dev->stats.tx_carrier_errors++;
  2120. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
  2121. nv_legacybackoff_reseed(dev);
  2122. dev->stats.tx_errors++;
  2123. } else {
  2124. dev->stats.tx_packets++;
  2125. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2126. }
  2127. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2128. np->get_tx_ctx->skb = NULL;
  2129. tx_work++;
  2130. }
  2131. }
  2132. if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
  2133. np->get_tx.orig = np->first_tx.orig;
  2134. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2135. np->get_tx_ctx = np->first_tx_ctx;
  2136. }
  2137. if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
  2138. np->tx_stop = 0;
  2139. netif_wake_queue(dev);
  2140. }
  2141. return tx_work;
  2142. }
  2143. static int nv_tx_done_optimized(struct net_device *dev, int limit)
  2144. {
  2145. struct fe_priv *np = netdev_priv(dev);
  2146. u32 flags;
  2147. int tx_work = 0;
  2148. struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
  2149. while ((np->get_tx.ex != np->put_tx.ex) &&
  2150. !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
  2151. (tx_work < limit)) {
  2152. nv_unmap_txskb(np, np->get_tx_ctx);
  2153. if (flags & NV_TX2_LASTPACKET) {
  2154. if (!(flags & NV_TX2_ERROR))
  2155. dev->stats.tx_packets++;
  2156. else {
  2157. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
  2158. if (np->driver_data & DEV_HAS_GEAR_MODE)
  2159. nv_gear_backoff_reseed(dev);
  2160. else
  2161. nv_legacybackoff_reseed(dev);
  2162. }
  2163. }
  2164. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2165. np->get_tx_ctx->skb = NULL;
  2166. tx_work++;
  2167. if (np->tx_limit)
  2168. nv_tx_flip_ownership(dev);
  2169. }
  2170. if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
  2171. np->get_tx.ex = np->first_tx.ex;
  2172. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2173. np->get_tx_ctx = np->first_tx_ctx;
  2174. }
  2175. if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
  2176. np->tx_stop = 0;
  2177. netif_wake_queue(dev);
  2178. }
  2179. return tx_work;
  2180. }
  2181. /*
  2182. * nv_tx_timeout: dev->tx_timeout function
  2183. * Called with netif_tx_lock held.
  2184. */
  2185. static void nv_tx_timeout(struct net_device *dev)
  2186. {
  2187. struct fe_priv *np = netdev_priv(dev);
  2188. u8 __iomem *base = get_hwbase(dev);
  2189. u32 status;
  2190. union ring_type put_tx;
  2191. int saved_tx_limit;
  2192. int i;
  2193. if (np->msi_flags & NV_MSI_X_ENABLED)
  2194. status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2195. else
  2196. status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2197. netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
  2198. netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
  2199. netdev_info(dev, "Dumping tx registers\n");
  2200. for (i = 0; i <= np->register_size; i += 32) {
  2201. netdev_info(dev,
  2202. "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  2203. i,
  2204. readl(base + i + 0), readl(base + i + 4),
  2205. readl(base + i + 8), readl(base + i + 12),
  2206. readl(base + i + 16), readl(base + i + 20),
  2207. readl(base + i + 24), readl(base + i + 28));
  2208. }
  2209. netdev_info(dev, "Dumping tx ring\n");
  2210. for (i = 0; i < np->tx_ring_size; i += 4) {
  2211. if (!nv_optimized(np)) {
  2212. netdev_info(dev,
  2213. "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
  2214. i,
  2215. le32_to_cpu(np->tx_ring.orig[i].buf),
  2216. le32_to_cpu(np->tx_ring.orig[i].flaglen),
  2217. le32_to_cpu(np->tx_ring.orig[i+1].buf),
  2218. le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
  2219. le32_to_cpu(np->tx_ring.orig[i+2].buf),
  2220. le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
  2221. le32_to_cpu(np->tx_ring.orig[i+3].buf),
  2222. le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
  2223. } else {
  2224. netdev_info(dev,
  2225. "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
  2226. i,
  2227. le32_to_cpu(np->tx_ring.ex[i].bufhigh),
  2228. le32_to_cpu(np->tx_ring.ex[i].buflow),
  2229. le32_to_cpu(np->tx_ring.ex[i].flaglen),
  2230. le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
  2231. le32_to_cpu(np->tx_ring.ex[i+1].buflow),
  2232. le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
  2233. le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
  2234. le32_to_cpu(np->tx_ring.ex[i+2].buflow),
  2235. le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
  2236. le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
  2237. le32_to_cpu(np->tx_ring.ex[i+3].buflow),
  2238. le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
  2239. }
  2240. }
  2241. spin_lock_irq(&np->lock);
  2242. /* 1) stop tx engine */
  2243. nv_stop_tx(dev);
  2244. /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
  2245. saved_tx_limit = np->tx_limit;
  2246. np->tx_limit = 0; /* prevent giving HW any limited pkts */
  2247. np->tx_stop = 0; /* prevent waking tx queue */
  2248. if (!nv_optimized(np))
  2249. nv_tx_done(dev, np->tx_ring_size);
  2250. else
  2251. nv_tx_done_optimized(dev, np->tx_ring_size);
  2252. /* save current HW position */
  2253. if (np->tx_change_owner)
  2254. put_tx.ex = np->tx_change_owner->first_tx_desc;
  2255. else
  2256. put_tx = np->put_tx;
  2257. /* 3) clear all tx state */
  2258. nv_drain_tx(dev);
  2259. nv_init_tx(dev);
  2260. /* 4) restore state to current HW position */
  2261. np->get_tx = np->put_tx = put_tx;
  2262. np->tx_limit = saved_tx_limit;
  2263. /* 5) restart tx engine */
  2264. nv_start_tx(dev);
  2265. netif_wake_queue(dev);
  2266. spin_unlock_irq(&np->lock);
  2267. }
  2268. /*
  2269. * Called when the nic notices a mismatch between the actual data len on the
  2270. * wire and the len indicated in the 802 header
  2271. */
  2272. static int nv_getlen(struct net_device *dev, void *packet, int datalen)
  2273. {
  2274. int hdrlen; /* length of the 802 header */
  2275. int protolen; /* length as stored in the proto field */
  2276. /* 1) calculate len according to header */
  2277. if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
  2278. protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
  2279. hdrlen = VLAN_HLEN;
  2280. } else {
  2281. protolen = ntohs(((struct ethhdr *)packet)->h_proto);
  2282. hdrlen = ETH_HLEN;
  2283. }
  2284. if (protolen > ETH_DATA_LEN)
  2285. return datalen; /* Value in proto field not a len, no checks possible */
  2286. protolen += hdrlen;
  2287. /* consistency checks: */
  2288. if (datalen > ETH_ZLEN) {
  2289. if (datalen >= protolen) {
  2290. /* more data on wire than in 802 header, trim of
  2291. * additional data.
  2292. */
  2293. return protolen;
  2294. } else {
  2295. /* less data on wire than mentioned in header.
  2296. * Discard the packet.
  2297. */
  2298. return -1;
  2299. }
  2300. } else {
  2301. /* short packet. Accept only if 802 values are also short */
  2302. if (protolen > ETH_ZLEN) {
  2303. return -1;
  2304. }
  2305. return datalen;
  2306. }
  2307. }
  2308. static int nv_rx_process(struct net_device *dev, int limit)
  2309. {
  2310. struct fe_priv *np = netdev_priv(dev);
  2311. u32 flags;
  2312. int rx_work = 0;
  2313. struct sk_buff *skb;
  2314. int len;
  2315. while ((np->get_rx.orig != np->put_rx.orig) &&
  2316. !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
  2317. (rx_work < limit)) {
  2318. /*
  2319. * the packet is for us - immediately tear down the pci mapping.
  2320. * TODO: check if a prefetch of the first cacheline improves
  2321. * the performance.
  2322. */
  2323. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2324. np->get_rx_ctx->dma_len,
  2325. PCI_DMA_FROMDEVICE);
  2326. skb = np->get_rx_ctx->skb;
  2327. np->get_rx_ctx->skb = NULL;
  2328. /* look at what we actually got: */
  2329. if (np->desc_ver == DESC_VER_1) {
  2330. if (likely(flags & NV_RX_DESCRIPTORVALID)) {
  2331. len = flags & LEN_MASK_V1;
  2332. if (unlikely(flags & NV_RX_ERROR)) {
  2333. if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
  2334. len = nv_getlen(dev, skb->data, len);
  2335. if (len < 0) {
  2336. dev->stats.rx_errors++;
  2337. dev_kfree_skb(skb);
  2338. goto next_pkt;
  2339. }
  2340. }
  2341. /* framing errors are soft errors */
  2342. else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
  2343. if (flags & NV_RX_SUBSTRACT1)
  2344. len--;
  2345. }
  2346. /* the rest are hard errors */
  2347. else {
  2348. if (flags & NV_RX_MISSEDFRAME)
  2349. dev->stats.rx_missed_errors++;
  2350. if (flags & NV_RX_CRCERR)
  2351. dev->stats.rx_crc_errors++;
  2352. if (flags & NV_RX_OVERFLOW)
  2353. dev->stats.rx_over_errors++;
  2354. dev->stats.rx_errors++;
  2355. dev_kfree_skb(skb);
  2356. goto next_pkt;
  2357. }
  2358. }
  2359. } else {
  2360. dev_kfree_skb(skb);
  2361. goto next_pkt;
  2362. }
  2363. } else {
  2364. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2365. len = flags & LEN_MASK_V2;
  2366. if (unlikely(flags & NV_RX2_ERROR)) {
  2367. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2368. len = nv_getlen(dev, skb->data, len);
  2369. if (len < 0) {
  2370. dev->stats.rx_errors++;
  2371. dev_kfree_skb(skb);
  2372. goto next_pkt;
  2373. }
  2374. }
  2375. /* framing errors are soft errors */
  2376. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2377. if (flags & NV_RX2_SUBSTRACT1)
  2378. len--;
  2379. }
  2380. /* the rest are hard errors */
  2381. else {
  2382. if (flags & NV_RX2_CRCERR)
  2383. dev->stats.rx_crc_errors++;
  2384. if (flags & NV_RX2_OVERFLOW)
  2385. dev->stats.rx_over_errors++;
  2386. dev->stats.rx_errors++;
  2387. dev_kfree_skb(skb);
  2388. goto next_pkt;
  2389. }
  2390. }
  2391. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2392. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2393. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2394. } else {
  2395. dev_kfree_skb(skb);
  2396. goto next_pkt;
  2397. }
  2398. }
  2399. /* got a valid packet - forward it to the network core */
  2400. skb_put(skb, len);
  2401. skb->protocol = eth_type_trans(skb, dev);
  2402. napi_gro_receive(&np->napi, skb);
  2403. dev->stats.rx_packets++;
  2404. dev->stats.rx_bytes += len;
  2405. next_pkt:
  2406. if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
  2407. np->get_rx.orig = np->first_rx.orig;
  2408. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2409. np->get_rx_ctx = np->first_rx_ctx;
  2410. rx_work++;
  2411. }
  2412. return rx_work;
  2413. }
  2414. static int nv_rx_process_optimized(struct net_device *dev, int limit)
  2415. {
  2416. struct fe_priv *np = netdev_priv(dev);
  2417. u32 flags;
  2418. u32 vlanflags = 0;
  2419. int rx_work = 0;
  2420. struct sk_buff *skb;
  2421. int len;
  2422. while ((np->get_rx.ex != np->put_rx.ex) &&
  2423. !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
  2424. (rx_work < limit)) {
  2425. /*
  2426. * the packet is for us - immediately tear down the pci mapping.
  2427. * TODO: check if a prefetch of the first cacheline improves
  2428. * the performance.
  2429. */
  2430. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2431. np->get_rx_ctx->dma_len,
  2432. PCI_DMA_FROMDEVICE);
  2433. skb = np->get_rx_ctx->skb;
  2434. np->get_rx_ctx->skb = NULL;
  2435. /* look at what we actually got: */
  2436. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2437. len = flags & LEN_MASK_V2;
  2438. if (unlikely(flags & NV_RX2_ERROR)) {
  2439. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2440. len = nv_getlen(dev, skb->data, len);
  2441. if (len < 0) {
  2442. dev_kfree_skb(skb);
  2443. goto next_pkt;
  2444. }
  2445. }
  2446. /* framing errors are soft errors */
  2447. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2448. if (flags & NV_RX2_SUBSTRACT1)
  2449. len--;
  2450. }
  2451. /* the rest are hard errors */
  2452. else {
  2453. dev_kfree_skb(skb);
  2454. goto next_pkt;
  2455. }
  2456. }
  2457. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2458. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2459. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2460. /* got a valid packet - forward it to the network core */
  2461. skb_put(skb, len);
  2462. skb->protocol = eth_type_trans(skb, dev);
  2463. prefetch(skb->data);
  2464. if (likely(!np->vlangrp)) {
  2465. napi_gro_receive(&np->napi, skb);
  2466. } else {
  2467. vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
  2468. if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
  2469. vlan_gro_receive(&np->napi, np->vlangrp,
  2470. vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
  2471. } else {
  2472. napi_gro_receive(&np->napi, skb);
  2473. }
  2474. }
  2475. dev->stats.rx_packets++;
  2476. dev->stats.rx_bytes += len;
  2477. } else {
  2478. dev_kfree_skb(skb);
  2479. }
  2480. next_pkt:
  2481. if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
  2482. np->get_rx.ex = np->first_rx.ex;
  2483. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2484. np->get_rx_ctx = np->first_rx_ctx;
  2485. rx_work++;
  2486. }
  2487. return rx_work;
  2488. }
  2489. static void set_bufsize(struct net_device *dev)
  2490. {
  2491. struct fe_priv *np = netdev_priv(dev);
  2492. if (dev->mtu <= ETH_DATA_LEN)
  2493. np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
  2494. else
  2495. np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
  2496. }
  2497. /*
  2498. * nv_change_mtu: dev->change_mtu function
  2499. * Called with dev_base_lock held for read.
  2500. */
  2501. static int nv_change_mtu(struct net_device *dev, int new_mtu)
  2502. {
  2503. struct fe_priv *np = netdev_priv(dev);
  2504. int old_mtu;
  2505. if (new_mtu < 64 || new_mtu > np->pkt_limit)
  2506. return -EINVAL;
  2507. old_mtu = dev->mtu;
  2508. dev->mtu = new_mtu;
  2509. /* return early if the buffer sizes will not change */
  2510. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  2511. return 0;
  2512. if (old_mtu == new_mtu)
  2513. return 0;
  2514. /* synchronized against open : rtnl_lock() held by caller */
  2515. if (netif_running(dev)) {
  2516. u8 __iomem *base = get_hwbase(dev);
  2517. /*
  2518. * It seems that the nic preloads valid ring entries into an
  2519. * internal buffer. The procedure for flushing everything is
  2520. * guessed, there is probably a simpler approach.
  2521. * Changing the MTU is a rare event, it shouldn't matter.
  2522. */
  2523. nv_disable_irq(dev);
  2524. nv_napi_disable(dev);
  2525. netif_tx_lock_bh(dev);
  2526. netif_addr_lock(dev);
  2527. spin_lock(&np->lock);
  2528. /* stop engines */
  2529. nv_stop_rxtx(dev);
  2530. nv_txrx_reset(dev);
  2531. /* drain rx queue */
  2532. nv_drain_rxtx(dev);
  2533. /* reinit driver view of the rx queue */
  2534. set_bufsize(dev);
  2535. if (nv_init_ring(dev)) {
  2536. if (!np->in_shutdown)
  2537. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2538. }
  2539. /* reinit nic view of the rx queue */
  2540. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  2541. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  2542. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  2543. base + NvRegRingSizes);
  2544. pci_push(base);
  2545. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2546. pci_push(base);
  2547. /* restart rx engine */
  2548. nv_start_rxtx(dev);
  2549. spin_unlock(&np->lock);
  2550. netif_addr_unlock(dev);
  2551. netif_tx_unlock_bh(dev);
  2552. nv_napi_enable(dev);
  2553. nv_enable_irq(dev);
  2554. }
  2555. return 0;
  2556. }
  2557. static void nv_copy_mac_to_hw(struct net_device *dev)
  2558. {
  2559. u8 __iomem *base = get_hwbase(dev);
  2560. u32 mac[2];
  2561. mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  2562. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  2563. mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  2564. writel(mac[0], base + NvRegMacAddrA);
  2565. writel(mac[1], base + NvRegMacAddrB);
  2566. }
  2567. /*
  2568. * nv_set_mac_address: dev->set_mac_address function
  2569. * Called with rtnl_lock() held.
  2570. */
  2571. static int nv_set_mac_address(struct net_device *dev, void *addr)
  2572. {
  2573. struct fe_priv *np = netdev_priv(dev);
  2574. struct sockaddr *macaddr = (struct sockaddr *)addr;
  2575. if (!is_valid_ether_addr(macaddr->sa_data))
  2576. return -EADDRNOTAVAIL;
  2577. /* synchronized against open : rtnl_lock() held by caller */
  2578. memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
  2579. if (netif_running(dev)) {
  2580. netif_tx_lock_bh(dev);
  2581. netif_addr_lock(dev);
  2582. spin_lock_irq(&np->lock);
  2583. /* stop rx engine */
  2584. nv_stop_rx(dev);
  2585. /* set mac address */
  2586. nv_copy_mac_to_hw(dev);
  2587. /* restart rx engine */
  2588. nv_start_rx(dev);
  2589. spin_unlock_irq(&np->lock);
  2590. netif_addr_unlock(dev);
  2591. netif_tx_unlock_bh(dev);
  2592. } else {
  2593. nv_copy_mac_to_hw(dev);
  2594. }
  2595. return 0;
  2596. }
  2597. /*
  2598. * nv_set_multicast: dev->set_multicast function
  2599. * Called with netif_tx_lock held.
  2600. */
  2601. static void nv_set_multicast(struct net_device *dev)
  2602. {
  2603. struct fe_priv *np = netdev_priv(dev);
  2604. u8 __iomem *base = get_hwbase(dev);
  2605. u32 addr[2];
  2606. u32 mask[2];
  2607. u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
  2608. memset(addr, 0, sizeof(addr));
  2609. memset(mask, 0, sizeof(mask));
  2610. if (dev->flags & IFF_PROMISC) {
  2611. pff |= NVREG_PFF_PROMISC;
  2612. } else {
  2613. pff |= NVREG_PFF_MYADDR;
  2614. if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
  2615. u32 alwaysOff[2];
  2616. u32 alwaysOn[2];
  2617. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
  2618. if (dev->flags & IFF_ALLMULTI) {
  2619. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
  2620. } else {
  2621. struct netdev_hw_addr *ha;
  2622. netdev_for_each_mc_addr(ha, dev) {
  2623. unsigned char *addr = ha->addr;
  2624. u32 a, b;
  2625. a = le32_to_cpu(*(__le32 *) addr);
  2626. b = le16_to_cpu(*(__le16 *) (&addr[4]));
  2627. alwaysOn[0] &= a;
  2628. alwaysOff[0] &= ~a;
  2629. alwaysOn[1] &= b;
  2630. alwaysOff[1] &= ~b;
  2631. }
  2632. }
  2633. addr[0] = alwaysOn[0];
  2634. addr[1] = alwaysOn[1];
  2635. mask[0] = alwaysOn[0] | alwaysOff[0];
  2636. mask[1] = alwaysOn[1] | alwaysOff[1];
  2637. } else {
  2638. mask[0] = NVREG_MCASTMASKA_NONE;
  2639. mask[1] = NVREG_MCASTMASKB_NONE;
  2640. }
  2641. }
  2642. addr[0] |= NVREG_MCASTADDRA_FORCE;
  2643. pff |= NVREG_PFF_ALWAYS;
  2644. spin_lock_irq(&np->lock);
  2645. nv_stop_rx(dev);
  2646. writel(addr[0], base + NvRegMulticastAddrA);
  2647. writel(addr[1], base + NvRegMulticastAddrB);
  2648. writel(mask[0], base + NvRegMulticastMaskA);
  2649. writel(mask[1], base + NvRegMulticastMaskB);
  2650. writel(pff, base + NvRegPacketFilterFlags);
  2651. nv_start_rx(dev);
  2652. spin_unlock_irq(&np->lock);
  2653. }
  2654. static void nv_update_pause(struct net_device *dev, u32 pause_flags)
  2655. {
  2656. struct fe_priv *np = netdev_priv(dev);
  2657. u8 __iomem *base = get_hwbase(dev);
  2658. np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
  2659. if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
  2660. u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
  2661. if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
  2662. writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
  2663. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2664. } else {
  2665. writel(pff, base + NvRegPacketFilterFlags);
  2666. }
  2667. }
  2668. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
  2669. u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
  2670. if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
  2671. u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
  2672. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
  2673. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
  2674. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
  2675. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
  2676. /* limit the number of tx pause frames to a default of 8 */
  2677. writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
  2678. }
  2679. writel(pause_enable, base + NvRegTxPauseFrame);
  2680. writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
  2681. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2682. } else {
  2683. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  2684. writel(regmisc, base + NvRegMisc1);
  2685. }
  2686. }
  2687. }
  2688. /**
  2689. * nv_update_linkspeed: Setup the MAC according to the link partner
  2690. * @dev: Network device to be configured
  2691. *
  2692. * The function queries the PHY and checks if there is a link partner.
  2693. * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
  2694. * set to 10 MBit HD.
  2695. *
  2696. * The function returns 0 if there is no link partner and 1 if there is
  2697. * a good link partner.
  2698. */
  2699. static int nv_update_linkspeed(struct net_device *dev)
  2700. {
  2701. struct fe_priv *np = netdev_priv(dev);
  2702. u8 __iomem *base = get_hwbase(dev);
  2703. int adv = 0;
  2704. int lpa = 0;
  2705. int adv_lpa, adv_pause, lpa_pause;
  2706. int newls = np->linkspeed;
  2707. int newdup = np->duplex;
  2708. int mii_status;
  2709. int retval = 0;
  2710. u32 control_1000, status_1000, phyreg, pause_flags, txreg;
  2711. u32 txrxFlags = 0;
  2712. u32 phy_exp;
  2713. /* BMSR_LSTATUS is latched, read it twice:
  2714. * we want the current value.
  2715. */
  2716. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2717. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2718. if (!(mii_status & BMSR_LSTATUS)) {
  2719. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2720. newdup = 0;
  2721. retval = 0;
  2722. goto set_speed;
  2723. }
  2724. if (np->autoneg == 0) {
  2725. if (np->fixed_mode & LPA_100FULL) {
  2726. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2727. newdup = 1;
  2728. } else if (np->fixed_mode & LPA_100HALF) {
  2729. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2730. newdup = 0;
  2731. } else if (np->fixed_mode & LPA_10FULL) {
  2732. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2733. newdup = 1;
  2734. } else {
  2735. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2736. newdup = 0;
  2737. }
  2738. retval = 1;
  2739. goto set_speed;
  2740. }
  2741. /* check auto negotiation is complete */
  2742. if (!(mii_status & BMSR_ANEGCOMPLETE)) {
  2743. /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
  2744. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2745. newdup = 0;
  2746. retval = 0;
  2747. goto set_speed;
  2748. }
  2749. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  2750. lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
  2751. retval = 1;
  2752. if (np->gigabit == PHY_GIGABIT) {
  2753. control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  2754. status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
  2755. if ((control_1000 & ADVERTISE_1000FULL) &&
  2756. (status_1000 & LPA_1000FULL)) {
  2757. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
  2758. newdup = 1;
  2759. goto set_speed;
  2760. }
  2761. }
  2762. /* FIXME: handle parallel detection properly */
  2763. adv_lpa = lpa & adv;
  2764. if (adv_lpa & LPA_100FULL) {
  2765. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2766. newdup = 1;
  2767. } else if (adv_lpa & LPA_100HALF) {
  2768. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2769. newdup = 0;
  2770. } else if (adv_lpa & LPA_10FULL) {
  2771. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2772. newdup = 1;
  2773. } else if (adv_lpa & LPA_10HALF) {
  2774. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2775. newdup = 0;
  2776. } else {
  2777. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2778. newdup = 0;
  2779. }
  2780. set_speed:
  2781. if (np->duplex == newdup && np->linkspeed == newls)
  2782. return retval;
  2783. np->duplex = newdup;
  2784. np->linkspeed = newls;
  2785. /* The transmitter and receiver must be restarted for safe update */
  2786. if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
  2787. txrxFlags |= NV_RESTART_TX;
  2788. nv_stop_tx(dev);
  2789. }
  2790. if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
  2791. txrxFlags |= NV_RESTART_RX;
  2792. nv_stop_rx(dev);
  2793. }
  2794. if (np->gigabit == PHY_GIGABIT) {
  2795. phyreg = readl(base + NvRegSlotTime);
  2796. phyreg &= ~(0x3FF00);
  2797. if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
  2798. ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
  2799. phyreg |= NVREG_SLOTTIME_10_100_FULL;
  2800. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
  2801. phyreg |= NVREG_SLOTTIME_1000_FULL;
  2802. writel(phyreg, base + NvRegSlotTime);
  2803. }
  2804. phyreg = readl(base + NvRegPhyInterface);
  2805. phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
  2806. if (np->duplex == 0)
  2807. phyreg |= PHY_HALF;
  2808. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
  2809. phyreg |= PHY_100;
  2810. else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2811. phyreg |= PHY_1000;
  2812. writel(phyreg, base + NvRegPhyInterface);
  2813. phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
  2814. if (phyreg & PHY_RGMII) {
  2815. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
  2816. txreg = NVREG_TX_DEFERRAL_RGMII_1000;
  2817. } else {
  2818. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
  2819. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
  2820. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
  2821. else
  2822. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
  2823. } else {
  2824. txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
  2825. }
  2826. }
  2827. } else {
  2828. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
  2829. txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
  2830. else
  2831. txreg = NVREG_TX_DEFERRAL_DEFAULT;
  2832. }
  2833. writel(txreg, base + NvRegTxDeferral);
  2834. if (np->desc_ver == DESC_VER_1) {
  2835. txreg = NVREG_TX_WM_DESC1_DEFAULT;
  2836. } else {
  2837. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2838. txreg = NVREG_TX_WM_DESC2_3_1000;
  2839. else
  2840. txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
  2841. }
  2842. writel(txreg, base + NvRegTxWatermark);
  2843. writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
  2844. base + NvRegMisc1);
  2845. pci_push(base);
  2846. writel(np->linkspeed, base + NvRegLinkSpeed);
  2847. pci_push(base);
  2848. pause_flags = 0;
  2849. /* setup pause frame */
  2850. if (np->duplex != 0) {
  2851. if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
  2852. adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2853. lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  2854. switch (adv_pause) {
  2855. case ADVERTISE_PAUSE_CAP:
  2856. if (lpa_pause & LPA_PAUSE_CAP) {
  2857. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2858. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2859. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2860. }
  2861. break;
  2862. case ADVERTISE_PAUSE_ASYM:
  2863. if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
  2864. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2865. break;
  2866. case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
  2867. if (lpa_pause & LPA_PAUSE_CAP) {
  2868. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2869. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2870. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2871. }
  2872. if (lpa_pause == LPA_PAUSE_ASYM)
  2873. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2874. break;
  2875. }
  2876. } else {
  2877. pause_flags = np->pause_flags;
  2878. }
  2879. }
  2880. nv_update_pause(dev, pause_flags);
  2881. if (txrxFlags & NV_RESTART_TX)
  2882. nv_start_tx(dev);
  2883. if (txrxFlags & NV_RESTART_RX)
  2884. nv_start_rx(dev);
  2885. return retval;
  2886. }
  2887. static void nv_linkchange(struct net_device *dev)
  2888. {
  2889. if (nv_update_linkspeed(dev)) {
  2890. if (!netif_carrier_ok(dev)) {
  2891. netif_carrier_on(dev);
  2892. netdev_info(dev, "link up\n");
  2893. nv_txrx_gate(dev, false);
  2894. nv_start_rx(dev);
  2895. }
  2896. } else {
  2897. if (netif_carrier_ok(dev)) {
  2898. netif_carrier_off(dev);
  2899. netdev_info(dev, "link down\n");
  2900. nv_txrx_gate(dev, true);
  2901. nv_stop_rx(dev);
  2902. }
  2903. }
  2904. }
  2905. static void nv_link_irq(struct net_device *dev)
  2906. {
  2907. u8 __iomem *base = get_hwbase(dev);
  2908. u32 miistat;
  2909. miistat = readl(base + NvRegMIIStatus);
  2910. writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
  2911. if (miistat & (NVREG_MIISTAT_LINKCHANGE))
  2912. nv_linkchange(dev);
  2913. }
  2914. static void nv_msi_workaround(struct fe_priv *np)
  2915. {
  2916. /* Need to toggle the msi irq mask within the ethernet device,
  2917. * otherwise, future interrupts will not be detected.
  2918. */
  2919. if (np->msi_flags & NV_MSI_ENABLED) {
  2920. u8 __iomem *base = np->base;
  2921. writel(0, base + NvRegMSIIrqMask);
  2922. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  2923. }
  2924. }
  2925. static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
  2926. {
  2927. struct fe_priv *np = netdev_priv(dev);
  2928. if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
  2929. if (total_work > NV_DYNAMIC_THRESHOLD) {
  2930. /* transition to poll based interrupts */
  2931. np->quiet_count = 0;
  2932. if (np->irqmask != NVREG_IRQMASK_CPU) {
  2933. np->irqmask = NVREG_IRQMASK_CPU;
  2934. return 1;
  2935. }
  2936. } else {
  2937. if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
  2938. np->quiet_count++;
  2939. } else {
  2940. /* reached a period of low activity, switch
  2941. to per tx/rx packet interrupts */
  2942. if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
  2943. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  2944. return 1;
  2945. }
  2946. }
  2947. }
  2948. }
  2949. return 0;
  2950. }
  2951. static irqreturn_t nv_nic_irq(int foo, void *data)
  2952. {
  2953. struct net_device *dev = (struct net_device *) data;
  2954. struct fe_priv *np = netdev_priv(dev);
  2955. u8 __iomem *base = get_hwbase(dev);
  2956. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2957. np->events = readl(base + NvRegIrqStatus);
  2958. writel(np->events, base + NvRegIrqStatus);
  2959. } else {
  2960. np->events = readl(base + NvRegMSIXIrqStatus);
  2961. writel(np->events, base + NvRegMSIXIrqStatus);
  2962. }
  2963. if (!(np->events & np->irqmask))
  2964. return IRQ_NONE;
  2965. nv_msi_workaround(np);
  2966. if (napi_schedule_prep(&np->napi)) {
  2967. /*
  2968. * Disable further irq's (msix not enabled with napi)
  2969. */
  2970. writel(0, base + NvRegIrqMask);
  2971. __napi_schedule(&np->napi);
  2972. }
  2973. return IRQ_HANDLED;
  2974. }
  2975. /**
  2976. * All _optimized functions are used to help increase performance
  2977. * (reduce CPU and increase throughput). They use descripter version 3,
  2978. * compiler directives, and reduce memory accesses.
  2979. */
  2980. static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
  2981. {
  2982. struct net_device *dev = (struct net_device *) data;
  2983. struct fe_priv *np = netdev_priv(dev);
  2984. u8 __iomem *base = get_hwbase(dev);
  2985. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2986. np->events = readl(base + NvRegIrqStatus);
  2987. writel(np->events, base + NvRegIrqStatus);
  2988. } else {
  2989. np->events = readl(base + NvRegMSIXIrqStatus);
  2990. writel(np->events, base + NvRegMSIXIrqStatus);
  2991. }
  2992. if (!(np->events & np->irqmask))
  2993. return IRQ_NONE;
  2994. nv_msi_workaround(np);
  2995. if (napi_schedule_prep(&np->napi)) {
  2996. /*
  2997. * Disable further irq's (msix not enabled with napi)
  2998. */
  2999. writel(0, base + NvRegIrqMask);
  3000. __napi_schedule(&np->napi);
  3001. }
  3002. return IRQ_HANDLED;
  3003. }
  3004. static irqreturn_t nv_nic_irq_tx(int foo, void *data)
  3005. {
  3006. struct net_device *dev = (struct net_device *) data;
  3007. struct fe_priv *np = netdev_priv(dev);
  3008. u8 __iomem *base = get_hwbase(dev);
  3009. u32 events;
  3010. int i;
  3011. unsigned long flags;
  3012. for (i = 0;; i++) {
  3013. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
  3014. writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
  3015. if (!(events & np->irqmask))
  3016. break;
  3017. spin_lock_irqsave(&np->lock, flags);
  3018. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3019. spin_unlock_irqrestore(&np->lock, flags);
  3020. if (unlikely(i > max_interrupt_work)) {
  3021. spin_lock_irqsave(&np->lock, flags);
  3022. /* disable interrupts on the nic */
  3023. writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
  3024. pci_push(base);
  3025. if (!np->in_shutdown) {
  3026. np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
  3027. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3028. }
  3029. spin_unlock_irqrestore(&np->lock, flags);
  3030. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3031. __func__, i);
  3032. break;
  3033. }
  3034. }
  3035. return IRQ_RETVAL(i);
  3036. }
  3037. static int nv_napi_poll(struct napi_struct *napi, int budget)
  3038. {
  3039. struct fe_priv *np = container_of(napi, struct fe_priv, napi);
  3040. struct net_device *dev = np->dev;
  3041. u8 __iomem *base = get_hwbase(dev);
  3042. unsigned long flags;
  3043. int retcode;
  3044. int rx_count, tx_work = 0, rx_work = 0;
  3045. do {
  3046. if (!nv_optimized(np)) {
  3047. spin_lock_irqsave(&np->lock, flags);
  3048. tx_work += nv_tx_done(dev, np->tx_ring_size);
  3049. spin_unlock_irqrestore(&np->lock, flags);
  3050. rx_count = nv_rx_process(dev, budget - rx_work);
  3051. retcode = nv_alloc_rx(dev);
  3052. } else {
  3053. spin_lock_irqsave(&np->lock, flags);
  3054. tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
  3055. spin_unlock_irqrestore(&np->lock, flags);
  3056. rx_count = nv_rx_process_optimized(dev,
  3057. budget - rx_work);
  3058. retcode = nv_alloc_rx_optimized(dev);
  3059. }
  3060. } while (retcode == 0 &&
  3061. rx_count > 0 && (rx_work += rx_count) < budget);
  3062. if (retcode) {
  3063. spin_lock_irqsave(&np->lock, flags);
  3064. if (!np->in_shutdown)
  3065. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3066. spin_unlock_irqrestore(&np->lock, flags);
  3067. }
  3068. nv_change_interrupt_mode(dev, tx_work + rx_work);
  3069. if (unlikely(np->events & NVREG_IRQ_LINK)) {
  3070. spin_lock_irqsave(&np->lock, flags);
  3071. nv_link_irq(dev);
  3072. spin_unlock_irqrestore(&np->lock, flags);
  3073. }
  3074. if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
  3075. spin_lock_irqsave(&np->lock, flags);
  3076. nv_linkchange(dev);
  3077. spin_unlock_irqrestore(&np->lock, flags);
  3078. np->link_timeout = jiffies + LINK_TIMEOUT;
  3079. }
  3080. if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
  3081. spin_lock_irqsave(&np->lock, flags);
  3082. if (!np->in_shutdown) {
  3083. np->nic_poll_irq = np->irqmask;
  3084. np->recover_error = 1;
  3085. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3086. }
  3087. spin_unlock_irqrestore(&np->lock, flags);
  3088. napi_complete(napi);
  3089. return rx_work;
  3090. }
  3091. if (rx_work < budget) {
  3092. /* re-enable interrupts
  3093. (msix not enabled in napi) */
  3094. napi_complete(napi);
  3095. writel(np->irqmask, base + NvRegIrqMask);
  3096. }
  3097. return rx_work;
  3098. }
  3099. static irqreturn_t nv_nic_irq_rx(int foo, void *data)
  3100. {
  3101. struct net_device *dev = (struct net_device *) data;
  3102. struct fe_priv *np = netdev_priv(dev);
  3103. u8 __iomem *base = get_hwbase(dev);
  3104. u32 events;
  3105. int i;
  3106. unsigned long flags;
  3107. for (i = 0;; i++) {
  3108. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
  3109. writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
  3110. if (!(events & np->irqmask))
  3111. break;
  3112. if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
  3113. if (unlikely(nv_alloc_rx_optimized(dev))) {
  3114. spin_lock_irqsave(&np->lock, flags);
  3115. if (!np->in_shutdown)
  3116. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3117. spin_unlock_irqrestore(&np->lock, flags);
  3118. }
  3119. }
  3120. if (unlikely(i > max_interrupt_work)) {
  3121. spin_lock_irqsave(&np->lock, flags);
  3122. /* disable interrupts on the nic */
  3123. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  3124. pci_push(base);
  3125. if (!np->in_shutdown) {
  3126. np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
  3127. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3128. }
  3129. spin_unlock_irqrestore(&np->lock, flags);
  3130. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3131. __func__, i);
  3132. break;
  3133. }
  3134. }
  3135. return IRQ_RETVAL(i);
  3136. }
  3137. static irqreturn_t nv_nic_irq_other(int foo, void *data)
  3138. {
  3139. struct net_device *dev = (struct net_device *) data;
  3140. struct fe_priv *np = netdev_priv(dev);
  3141. u8 __iomem *base = get_hwbase(dev);
  3142. u32 events;
  3143. int i;
  3144. unsigned long flags;
  3145. for (i = 0;; i++) {
  3146. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
  3147. writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
  3148. if (!(events & np->irqmask))
  3149. break;
  3150. /* check tx in case we reached max loop limit in tx isr */
  3151. spin_lock_irqsave(&np->lock, flags);
  3152. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3153. spin_unlock_irqrestore(&np->lock, flags);
  3154. if (events & NVREG_IRQ_LINK) {
  3155. spin_lock_irqsave(&np->lock, flags);
  3156. nv_link_irq(dev);
  3157. spin_unlock_irqrestore(&np->lock, flags);
  3158. }
  3159. if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
  3160. spin_lock_irqsave(&np->lock, flags);
  3161. nv_linkchange(dev);
  3162. spin_unlock_irqrestore(&np->lock, flags);
  3163. np->link_timeout = jiffies + LINK_TIMEOUT;
  3164. }
  3165. if (events & NVREG_IRQ_RECOVER_ERROR) {
  3166. spin_lock_irq(&np->lock);
  3167. /* disable interrupts on the nic */
  3168. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3169. pci_push(base);
  3170. if (!np->in_shutdown) {
  3171. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3172. np->recover_error = 1;
  3173. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3174. }
  3175. spin_unlock_irq(&np->lock);
  3176. break;
  3177. }
  3178. if (unlikely(i > max_interrupt_work)) {
  3179. spin_lock_irqsave(&np->lock, flags);
  3180. /* disable interrupts on the nic */
  3181. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3182. pci_push(base);
  3183. if (!np->in_shutdown) {
  3184. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3185. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3186. }
  3187. spin_unlock_irqrestore(&np->lock, flags);
  3188. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3189. __func__, i);
  3190. break;
  3191. }
  3192. }
  3193. return IRQ_RETVAL(i);
  3194. }
  3195. static irqreturn_t nv_nic_irq_test(int foo, void *data)
  3196. {
  3197. struct net_device *dev = (struct net_device *) data;
  3198. struct fe_priv *np = netdev_priv(dev);
  3199. u8 __iomem *base = get_hwbase(dev);
  3200. u32 events;
  3201. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3202. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  3203. writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
  3204. } else {
  3205. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  3206. writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
  3207. }
  3208. pci_push(base);
  3209. if (!(events & NVREG_IRQ_TIMER))
  3210. return IRQ_RETVAL(0);
  3211. nv_msi_workaround(np);
  3212. spin_lock(&np->lock);
  3213. np->intr_test = 1;
  3214. spin_unlock(&np->lock);
  3215. return IRQ_RETVAL(1);
  3216. }
  3217. static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
  3218. {
  3219. u8 __iomem *base = get_hwbase(dev);
  3220. int i;
  3221. u32 msixmap = 0;
  3222. /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
  3223. * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
  3224. * the remaining 8 interrupts.
  3225. */
  3226. for (i = 0; i < 8; i++) {
  3227. if ((irqmask >> i) & 0x1)
  3228. msixmap |= vector << (i << 2);
  3229. }
  3230. writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
  3231. msixmap = 0;
  3232. for (i = 0; i < 8; i++) {
  3233. if ((irqmask >> (i + 8)) & 0x1)
  3234. msixmap |= vector << (i << 2);
  3235. }
  3236. writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
  3237. }
  3238. static int nv_request_irq(struct net_device *dev, int intr_test)
  3239. {
  3240. struct fe_priv *np = get_nvpriv(dev);
  3241. u8 __iomem *base = get_hwbase(dev);
  3242. int ret = 1;
  3243. int i;
  3244. irqreturn_t (*handler)(int foo, void *data);
  3245. if (intr_test) {
  3246. handler = nv_nic_irq_test;
  3247. } else {
  3248. if (nv_optimized(np))
  3249. handler = nv_nic_irq_optimized;
  3250. else
  3251. handler = nv_nic_irq;
  3252. }
  3253. if (np->msi_flags & NV_MSI_X_CAPABLE) {
  3254. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
  3255. np->msi_x_entry[i].entry = i;
  3256. ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
  3257. if (ret == 0) {
  3258. np->msi_flags |= NV_MSI_X_ENABLED;
  3259. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
  3260. /* Request irq for rx handling */
  3261. sprintf(np->name_rx, "%s-rx", dev->name);
  3262. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
  3263. nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
  3264. netdev_info(dev,
  3265. "request_irq failed for rx %d\n",
  3266. ret);
  3267. pci_disable_msix(np->pci_dev);
  3268. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3269. goto out_err;
  3270. }
  3271. /* Request irq for tx handling */
  3272. sprintf(np->name_tx, "%s-tx", dev->name);
  3273. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
  3274. nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
  3275. netdev_info(dev,
  3276. "request_irq failed for tx %d\n",
  3277. ret);
  3278. pci_disable_msix(np->pci_dev);
  3279. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3280. goto out_free_rx;
  3281. }
  3282. /* Request irq for link and timer handling */
  3283. sprintf(np->name_other, "%s-other", dev->name);
  3284. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
  3285. nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
  3286. netdev_info(dev,
  3287. "request_irq failed for link %d\n",
  3288. ret);
  3289. pci_disable_msix(np->pci_dev);
  3290. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3291. goto out_free_tx;
  3292. }
  3293. /* map interrupts to their respective vector */
  3294. writel(0, base + NvRegMSIXMap0);
  3295. writel(0, base + NvRegMSIXMap1);
  3296. set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
  3297. set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
  3298. set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
  3299. } else {
  3300. /* Request irq for all interrupts */
  3301. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3302. netdev_info(dev,
  3303. "request_irq failed %d\n",
  3304. ret);
  3305. pci_disable_msix(np->pci_dev);
  3306. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3307. goto out_err;
  3308. }
  3309. /* map interrupts to vector 0 */
  3310. writel(0, base + NvRegMSIXMap0);
  3311. writel(0, base + NvRegMSIXMap1);
  3312. }
  3313. }
  3314. }
  3315. if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
  3316. ret = pci_enable_msi(np->pci_dev);
  3317. if (ret == 0) {
  3318. np->msi_flags |= NV_MSI_ENABLED;
  3319. dev->irq = np->pci_dev->irq;
  3320. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3321. netdev_info(dev, "request_irq failed %d\n",
  3322. ret);
  3323. pci_disable_msi(np->pci_dev);
  3324. np->msi_flags &= ~NV_MSI_ENABLED;
  3325. dev->irq = np->pci_dev->irq;
  3326. goto out_err;
  3327. }
  3328. /* map interrupts to vector 0 */
  3329. writel(0, base + NvRegMSIMap0);
  3330. writel(0, base + NvRegMSIMap1);
  3331. /* enable msi vector 0 */
  3332. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  3333. }
  3334. }
  3335. if (ret != 0) {
  3336. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
  3337. goto out_err;
  3338. }
  3339. return 0;
  3340. out_free_tx:
  3341. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
  3342. out_free_rx:
  3343. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
  3344. out_err:
  3345. return 1;
  3346. }
  3347. static void nv_free_irq(struct net_device *dev)
  3348. {
  3349. struct fe_priv *np = get_nvpriv(dev);
  3350. int i;
  3351. if (np->msi_flags & NV_MSI_X_ENABLED) {
  3352. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
  3353. free_irq(np->msi_x_entry[i].vector, dev);
  3354. pci_disable_msix(np->pci_dev);
  3355. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3356. } else {
  3357. free_irq(np->pci_dev->irq, dev);
  3358. if (np->msi_flags & NV_MSI_ENABLED) {
  3359. pci_disable_msi(np->pci_dev);
  3360. np->msi_flags &= ~NV_MSI_ENABLED;
  3361. }
  3362. }
  3363. }
  3364. static void nv_do_nic_poll(unsigned long data)
  3365. {
  3366. struct net_device *dev = (struct net_device *) data;
  3367. struct fe_priv *np = netdev_priv(dev);
  3368. u8 __iomem *base = get_hwbase(dev);
  3369. u32 mask = 0;
  3370. /*
  3371. * First disable irq(s) and then
  3372. * reenable interrupts on the nic, we have to do this before calling
  3373. * nv_nic_irq because that may decide to do otherwise
  3374. */
  3375. if (!using_multi_irqs(dev)) {
  3376. if (np->msi_flags & NV_MSI_X_ENABLED)
  3377. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3378. else
  3379. disable_irq_lockdep(np->pci_dev->irq);
  3380. mask = np->irqmask;
  3381. } else {
  3382. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3383. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3384. mask |= NVREG_IRQ_RX_ALL;
  3385. }
  3386. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3387. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3388. mask |= NVREG_IRQ_TX_ALL;
  3389. }
  3390. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3391. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3392. mask |= NVREG_IRQ_OTHER;
  3393. }
  3394. }
  3395. /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
  3396. if (np->recover_error) {
  3397. np->recover_error = 0;
  3398. netdev_info(dev, "MAC in recoverable error state\n");
  3399. if (netif_running(dev)) {
  3400. netif_tx_lock_bh(dev);
  3401. netif_addr_lock(dev);
  3402. spin_lock(&np->lock);
  3403. /* stop engines */
  3404. nv_stop_rxtx(dev);
  3405. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  3406. nv_mac_reset(dev);
  3407. nv_txrx_reset(dev);
  3408. /* drain rx queue */
  3409. nv_drain_rxtx(dev);
  3410. /* reinit driver view of the rx queue */
  3411. set_bufsize(dev);
  3412. if (nv_init_ring(dev)) {
  3413. if (!np->in_shutdown)
  3414. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3415. }
  3416. /* reinit nic view of the rx queue */
  3417. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3418. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3419. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3420. base + NvRegRingSizes);
  3421. pci_push(base);
  3422. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3423. pci_push(base);
  3424. /* clear interrupts */
  3425. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  3426. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  3427. else
  3428. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  3429. /* restart rx engine */
  3430. nv_start_rxtx(dev);
  3431. spin_unlock(&np->lock);
  3432. netif_addr_unlock(dev);
  3433. netif_tx_unlock_bh(dev);
  3434. }
  3435. }
  3436. writel(mask, base + NvRegIrqMask);
  3437. pci_push(base);
  3438. if (!using_multi_irqs(dev)) {
  3439. np->nic_poll_irq = 0;
  3440. if (nv_optimized(np))
  3441. nv_nic_irq_optimized(0, dev);
  3442. else
  3443. nv_nic_irq(0, dev);
  3444. if (np->msi_flags & NV_MSI_X_ENABLED)
  3445. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3446. else
  3447. enable_irq_lockdep(np->pci_dev->irq);
  3448. } else {
  3449. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3450. np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
  3451. nv_nic_irq_rx(0, dev);
  3452. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3453. }
  3454. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3455. np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
  3456. nv_nic_irq_tx(0, dev);
  3457. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3458. }
  3459. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3460. np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
  3461. nv_nic_irq_other(0, dev);
  3462. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3463. }
  3464. }
  3465. }
  3466. #ifdef CONFIG_NET_POLL_CONTROLLER
  3467. static void nv_poll_controller(struct net_device *dev)
  3468. {
  3469. nv_do_nic_poll((unsigned long) dev);
  3470. }
  3471. #endif
  3472. static void nv_do_stats_poll(unsigned long data)
  3473. {
  3474. struct net_device *dev = (struct net_device *) data;
  3475. struct fe_priv *np = netdev_priv(dev);
  3476. nv_get_hw_stats(dev);
  3477. if (!np->in_shutdown)
  3478. mod_timer(&np->stats_poll,
  3479. round_jiffies(jiffies + STATS_INTERVAL));
  3480. }
  3481. static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3482. {
  3483. struct fe_priv *np = netdev_priv(dev);
  3484. strcpy(info->driver, DRV_NAME);
  3485. strcpy(info->version, FORCEDETH_VERSION);
  3486. strcpy(info->bus_info, pci_name(np->pci_dev));
  3487. }
  3488. static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3489. {
  3490. struct fe_priv *np = netdev_priv(dev);
  3491. wolinfo->supported = WAKE_MAGIC;
  3492. spin_lock_irq(&np->lock);
  3493. if (np->wolenabled)
  3494. wolinfo->wolopts = WAKE_MAGIC;
  3495. spin_unlock_irq(&np->lock);
  3496. }
  3497. static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3498. {
  3499. struct fe_priv *np = netdev_priv(dev);
  3500. u8 __iomem *base = get_hwbase(dev);
  3501. u32 flags = 0;
  3502. if (wolinfo->wolopts == 0) {
  3503. np->wolenabled = 0;
  3504. } else if (wolinfo->wolopts & WAKE_MAGIC) {
  3505. np->wolenabled = 1;
  3506. flags = NVREG_WAKEUPFLAGS_ENABLE;
  3507. }
  3508. if (netif_running(dev)) {
  3509. spin_lock_irq(&np->lock);
  3510. writel(flags, base + NvRegWakeUpFlags);
  3511. spin_unlock_irq(&np->lock);
  3512. }
  3513. device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
  3514. return 0;
  3515. }
  3516. static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3517. {
  3518. struct fe_priv *np = netdev_priv(dev);
  3519. u32 speed;
  3520. int adv;
  3521. spin_lock_irq(&np->lock);
  3522. ecmd->port = PORT_MII;
  3523. if (!netif_running(dev)) {
  3524. /* We do not track link speed / duplex setting if the
  3525. * interface is disabled. Force a link check */
  3526. if (nv_update_linkspeed(dev)) {
  3527. if (!netif_carrier_ok(dev))
  3528. netif_carrier_on(dev);
  3529. } else {
  3530. if (netif_carrier_ok(dev))
  3531. netif_carrier_off(dev);
  3532. }
  3533. }
  3534. if (netif_carrier_ok(dev)) {
  3535. switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
  3536. case NVREG_LINKSPEED_10:
  3537. speed = SPEED_10;
  3538. break;
  3539. case NVREG_LINKSPEED_100:
  3540. speed = SPEED_100;
  3541. break;
  3542. case NVREG_LINKSPEED_1000:
  3543. speed = SPEED_1000;
  3544. break;
  3545. default:
  3546. speed = -1;
  3547. break;
  3548. }
  3549. ecmd->duplex = DUPLEX_HALF;
  3550. if (np->duplex)
  3551. ecmd->duplex = DUPLEX_FULL;
  3552. } else {
  3553. speed = -1;
  3554. ecmd->duplex = -1;
  3555. }
  3556. ethtool_cmd_speed_set(ecmd, speed);
  3557. ecmd->autoneg = np->autoneg;
  3558. ecmd->advertising = ADVERTISED_MII;
  3559. if (np->autoneg) {
  3560. ecmd->advertising |= ADVERTISED_Autoneg;
  3561. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3562. if (adv & ADVERTISE_10HALF)
  3563. ecmd->advertising |= ADVERTISED_10baseT_Half;
  3564. if (adv & ADVERTISE_10FULL)
  3565. ecmd->advertising |= ADVERTISED_10baseT_Full;
  3566. if (adv & ADVERTISE_100HALF)
  3567. ecmd->advertising |= ADVERTISED_100baseT_Half;
  3568. if (adv & ADVERTISE_100FULL)
  3569. ecmd->advertising |= ADVERTISED_100baseT_Full;
  3570. if (np->gigabit == PHY_GIGABIT) {
  3571. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3572. if (adv & ADVERTISE_1000FULL)
  3573. ecmd->advertising |= ADVERTISED_1000baseT_Full;
  3574. }
  3575. }
  3576. ecmd->supported = (SUPPORTED_Autoneg |
  3577. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  3578. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  3579. SUPPORTED_MII);
  3580. if (np->gigabit == PHY_GIGABIT)
  3581. ecmd->supported |= SUPPORTED_1000baseT_Full;
  3582. ecmd->phy_address = np->phyaddr;
  3583. ecmd->transceiver = XCVR_EXTERNAL;
  3584. /* ignore maxtxpkt, maxrxpkt for now */
  3585. spin_unlock_irq(&np->lock);
  3586. return 0;
  3587. }
  3588. static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3589. {
  3590. struct fe_priv *np = netdev_priv(dev);
  3591. u32 speed = ethtool_cmd_speed(ecmd);
  3592. if (ecmd->port != PORT_MII)
  3593. return -EINVAL;
  3594. if (ecmd->transceiver != XCVR_EXTERNAL)
  3595. return -EINVAL;
  3596. if (ecmd->phy_address != np->phyaddr) {
  3597. /* TODO: support switching between multiple phys. Should be
  3598. * trivial, but not enabled due to lack of test hardware. */
  3599. return -EINVAL;
  3600. }
  3601. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3602. u32 mask;
  3603. mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3604. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3605. if (np->gigabit == PHY_GIGABIT)
  3606. mask |= ADVERTISED_1000baseT_Full;
  3607. if ((ecmd->advertising & mask) == 0)
  3608. return -EINVAL;
  3609. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  3610. /* Note: autonegotiation disable, speed 1000 intentionally
  3611. * forbidden - no one should need that. */
  3612. if (speed != SPEED_10 && speed != SPEED_100)
  3613. return -EINVAL;
  3614. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  3615. return -EINVAL;
  3616. } else {
  3617. return -EINVAL;
  3618. }
  3619. netif_carrier_off(dev);
  3620. if (netif_running(dev)) {
  3621. unsigned long flags;
  3622. nv_disable_irq(dev);
  3623. netif_tx_lock_bh(dev);
  3624. netif_addr_lock(dev);
  3625. /* with plain spinlock lockdep complains */
  3626. spin_lock_irqsave(&np->lock, flags);
  3627. /* stop engines */
  3628. /* FIXME:
  3629. * this can take some time, and interrupts are disabled
  3630. * due to spin_lock_irqsave, but let's hope no daemon
  3631. * is going to change the settings very often...
  3632. * Worst case:
  3633. * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
  3634. * + some minor delays, which is up to a second approximately
  3635. */
  3636. nv_stop_rxtx(dev);
  3637. spin_unlock_irqrestore(&np->lock, flags);
  3638. netif_addr_unlock(dev);
  3639. netif_tx_unlock_bh(dev);
  3640. }
  3641. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3642. int adv, bmcr;
  3643. np->autoneg = 1;
  3644. /* advertise only what has been requested */
  3645. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3646. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3647. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  3648. adv |= ADVERTISE_10HALF;
  3649. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  3650. adv |= ADVERTISE_10FULL;
  3651. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  3652. adv |= ADVERTISE_100HALF;
  3653. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  3654. adv |= ADVERTISE_100FULL;
  3655. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
  3656. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3657. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3658. adv |= ADVERTISE_PAUSE_ASYM;
  3659. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3660. if (np->gigabit == PHY_GIGABIT) {
  3661. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3662. adv &= ~ADVERTISE_1000FULL;
  3663. if (ecmd->advertising & ADVERTISED_1000baseT_Full)
  3664. adv |= ADVERTISE_1000FULL;
  3665. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3666. }
  3667. if (netif_running(dev))
  3668. netdev_info(dev, "link down\n");
  3669. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3670. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3671. bmcr |= BMCR_ANENABLE;
  3672. /* reset the phy in order for settings to stick,
  3673. * and cause autoneg to start */
  3674. if (phy_reset(dev, bmcr)) {
  3675. netdev_info(dev, "phy reset failed\n");
  3676. return -EINVAL;
  3677. }
  3678. } else {
  3679. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3680. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3681. }
  3682. } else {
  3683. int adv, bmcr;
  3684. np->autoneg = 0;
  3685. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3686. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3687. if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
  3688. adv |= ADVERTISE_10HALF;
  3689. if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
  3690. adv |= ADVERTISE_10FULL;
  3691. if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
  3692. adv |= ADVERTISE_100HALF;
  3693. if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
  3694. adv |= ADVERTISE_100FULL;
  3695. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3696. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
  3697. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3698. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3699. }
  3700. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
  3701. adv |= ADVERTISE_PAUSE_ASYM;
  3702. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3703. }
  3704. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3705. np->fixed_mode = adv;
  3706. if (np->gigabit == PHY_GIGABIT) {
  3707. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3708. adv &= ~ADVERTISE_1000FULL;
  3709. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3710. }
  3711. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3712. bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
  3713. if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
  3714. bmcr |= BMCR_FULLDPLX;
  3715. if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
  3716. bmcr |= BMCR_SPEED100;
  3717. if (np->phy_oui == PHY_OUI_MARVELL) {
  3718. /* reset the phy in order for forced mode settings to stick */
  3719. if (phy_reset(dev, bmcr)) {
  3720. netdev_info(dev, "phy reset failed\n");
  3721. return -EINVAL;
  3722. }
  3723. } else {
  3724. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3725. if (netif_running(dev)) {
  3726. /* Wait a bit and then reconfigure the nic. */
  3727. udelay(10);
  3728. nv_linkchange(dev);
  3729. }
  3730. }
  3731. }
  3732. if (netif_running(dev)) {
  3733. nv_start_rxtx(dev);
  3734. nv_enable_irq(dev);
  3735. }
  3736. return 0;
  3737. }
  3738. #define FORCEDETH_REGS_VER 1
  3739. static int nv_get_regs_len(struct net_device *dev)
  3740. {
  3741. struct fe_priv *np = netdev_priv(dev);
  3742. return np->register_size;
  3743. }
  3744. static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  3745. {
  3746. struct fe_priv *np = netdev_priv(dev);
  3747. u8 __iomem *base = get_hwbase(dev);
  3748. u32 *rbuf = buf;
  3749. int i;
  3750. regs->version = FORCEDETH_REGS_VER;
  3751. spin_lock_irq(&np->lock);
  3752. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  3753. rbuf[i] = readl(base + i*sizeof(u32));
  3754. spin_unlock_irq(&np->lock);
  3755. }
  3756. static int nv_nway_reset(struct net_device *dev)
  3757. {
  3758. struct fe_priv *np = netdev_priv(dev);
  3759. int ret;
  3760. if (np->autoneg) {
  3761. int bmcr;
  3762. netif_carrier_off(dev);
  3763. if (netif_running(dev)) {
  3764. nv_disable_irq(dev);
  3765. netif_tx_lock_bh(dev);
  3766. netif_addr_lock(dev);
  3767. spin_lock(&np->lock);
  3768. /* stop engines */
  3769. nv_stop_rxtx(dev);
  3770. spin_unlock(&np->lock);
  3771. netif_addr_unlock(dev);
  3772. netif_tx_unlock_bh(dev);
  3773. netdev_info(dev, "link down\n");
  3774. }
  3775. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3776. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3777. bmcr |= BMCR_ANENABLE;
  3778. /* reset the phy in order for settings to stick*/
  3779. if (phy_reset(dev, bmcr)) {
  3780. netdev_info(dev, "phy reset failed\n");
  3781. return -EINVAL;
  3782. }
  3783. } else {
  3784. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3785. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3786. }
  3787. if (netif_running(dev)) {
  3788. nv_start_rxtx(dev);
  3789. nv_enable_irq(dev);
  3790. }
  3791. ret = 0;
  3792. } else {
  3793. ret = -EINVAL;
  3794. }
  3795. return ret;
  3796. }
  3797. static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3798. {
  3799. struct fe_priv *np = netdev_priv(dev);
  3800. ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3801. ring->rx_mini_max_pending = 0;
  3802. ring->rx_jumbo_max_pending = 0;
  3803. ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3804. ring->rx_pending = np->rx_ring_size;
  3805. ring->rx_mini_pending = 0;
  3806. ring->rx_jumbo_pending = 0;
  3807. ring->tx_pending = np->tx_ring_size;
  3808. }
  3809. static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3810. {
  3811. struct fe_priv *np = netdev_priv(dev);
  3812. u8 __iomem *base = get_hwbase(dev);
  3813. u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
  3814. dma_addr_t ring_addr;
  3815. if (ring->rx_pending < RX_RING_MIN ||
  3816. ring->tx_pending < TX_RING_MIN ||
  3817. ring->rx_mini_pending != 0 ||
  3818. ring->rx_jumbo_pending != 0 ||
  3819. (np->desc_ver == DESC_VER_1 &&
  3820. (ring->rx_pending > RING_MAX_DESC_VER_1 ||
  3821. ring->tx_pending > RING_MAX_DESC_VER_1)) ||
  3822. (np->desc_ver != DESC_VER_1 &&
  3823. (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
  3824. ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
  3825. return -EINVAL;
  3826. }
  3827. /* allocate new rings */
  3828. if (!nv_optimized(np)) {
  3829. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3830. sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3831. &ring_addr);
  3832. } else {
  3833. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3834. sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3835. &ring_addr);
  3836. }
  3837. rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
  3838. tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
  3839. if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
  3840. /* fall back to old rings */
  3841. if (!nv_optimized(np)) {
  3842. if (rxtx_ring)
  3843. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3844. rxtx_ring, ring_addr);
  3845. } else {
  3846. if (rxtx_ring)
  3847. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3848. rxtx_ring, ring_addr);
  3849. }
  3850. kfree(rx_skbuff);
  3851. kfree(tx_skbuff);
  3852. goto exit;
  3853. }
  3854. if (netif_running(dev)) {
  3855. nv_disable_irq(dev);
  3856. nv_napi_disable(dev);
  3857. netif_tx_lock_bh(dev);
  3858. netif_addr_lock(dev);
  3859. spin_lock(&np->lock);
  3860. /* stop engines */
  3861. nv_stop_rxtx(dev);
  3862. nv_txrx_reset(dev);
  3863. /* drain queues */
  3864. nv_drain_rxtx(dev);
  3865. /* delete queues */
  3866. free_rings(dev);
  3867. }
  3868. /* set new values */
  3869. np->rx_ring_size = ring->rx_pending;
  3870. np->tx_ring_size = ring->tx_pending;
  3871. if (!nv_optimized(np)) {
  3872. np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
  3873. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  3874. } else {
  3875. np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
  3876. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  3877. }
  3878. np->rx_skb = (struct nv_skb_map *)rx_skbuff;
  3879. np->tx_skb = (struct nv_skb_map *)tx_skbuff;
  3880. np->ring_addr = ring_addr;
  3881. memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
  3882. memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
  3883. if (netif_running(dev)) {
  3884. /* reinit driver view of the queues */
  3885. set_bufsize(dev);
  3886. if (nv_init_ring(dev)) {
  3887. if (!np->in_shutdown)
  3888. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3889. }
  3890. /* reinit nic view of the queues */
  3891. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3892. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3893. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3894. base + NvRegRingSizes);
  3895. pci_push(base);
  3896. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3897. pci_push(base);
  3898. /* restart engines */
  3899. nv_start_rxtx(dev);
  3900. spin_unlock(&np->lock);
  3901. netif_addr_unlock(dev);
  3902. netif_tx_unlock_bh(dev);
  3903. nv_napi_enable(dev);
  3904. nv_enable_irq(dev);
  3905. }
  3906. return 0;
  3907. exit:
  3908. return -ENOMEM;
  3909. }
  3910. static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3911. {
  3912. struct fe_priv *np = netdev_priv(dev);
  3913. pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
  3914. pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
  3915. pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
  3916. }
  3917. static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3918. {
  3919. struct fe_priv *np = netdev_priv(dev);
  3920. int adv, bmcr;
  3921. if ((!np->autoneg && np->duplex == 0) ||
  3922. (np->autoneg && !pause->autoneg && np->duplex == 0)) {
  3923. netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
  3924. return -EINVAL;
  3925. }
  3926. if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
  3927. netdev_info(dev, "hardware does not support tx pause frames\n");
  3928. return -EINVAL;
  3929. }
  3930. netif_carrier_off(dev);
  3931. if (netif_running(dev)) {
  3932. nv_disable_irq(dev);
  3933. netif_tx_lock_bh(dev);
  3934. netif_addr_lock(dev);
  3935. spin_lock(&np->lock);
  3936. /* stop engines */
  3937. nv_stop_rxtx(dev);
  3938. spin_unlock(&np->lock);
  3939. netif_addr_unlock(dev);
  3940. netif_tx_unlock_bh(dev);
  3941. }
  3942. np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
  3943. if (pause->rx_pause)
  3944. np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
  3945. if (pause->tx_pause)
  3946. np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
  3947. if (np->autoneg && pause->autoneg) {
  3948. np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
  3949. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3950. adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3951. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
  3952. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3953. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3954. adv |= ADVERTISE_PAUSE_ASYM;
  3955. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3956. if (netif_running(dev))
  3957. netdev_info(dev, "link down\n");
  3958. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3959. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3960. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3961. } else {
  3962. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3963. if (pause->rx_pause)
  3964. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3965. if (pause->tx_pause)
  3966. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3967. if (!netif_running(dev))
  3968. nv_update_linkspeed(dev);
  3969. else
  3970. nv_update_pause(dev, np->pause_flags);
  3971. }
  3972. if (netif_running(dev)) {
  3973. nv_start_rxtx(dev);
  3974. nv_enable_irq(dev);
  3975. }
  3976. return 0;
  3977. }
  3978. static u32 nv_fix_features(struct net_device *dev, u32 features)
  3979. {
  3980. /* vlan is dependent on rx checksum offload */
  3981. if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
  3982. features |= NETIF_F_RXCSUM;
  3983. return features;
  3984. }
  3985. static int nv_set_features(struct net_device *dev, u32 features)
  3986. {
  3987. struct fe_priv *np = netdev_priv(dev);
  3988. u8 __iomem *base = get_hwbase(dev);
  3989. u32 changed = dev->features ^ features;
  3990. if (changed & NETIF_F_RXCSUM) {
  3991. spin_lock_irq(&np->lock);
  3992. if (features & NETIF_F_RXCSUM)
  3993. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  3994. else
  3995. np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
  3996. if (netif_running(dev))
  3997. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  3998. spin_unlock_irq(&np->lock);
  3999. }
  4000. return 0;
  4001. }
  4002. static int nv_get_sset_count(struct net_device *dev, int sset)
  4003. {
  4004. struct fe_priv *np = netdev_priv(dev);
  4005. switch (sset) {
  4006. case ETH_SS_TEST:
  4007. if (np->driver_data & DEV_HAS_TEST_EXTENDED)
  4008. return NV_TEST_COUNT_EXTENDED;
  4009. else
  4010. return NV_TEST_COUNT_BASE;
  4011. case ETH_SS_STATS:
  4012. if (np->driver_data & DEV_HAS_STATISTICS_V3)
  4013. return NV_DEV_STATISTICS_V3_COUNT;
  4014. else if (np->driver_data & DEV_HAS_STATISTICS_V2)
  4015. return NV_DEV_STATISTICS_V2_COUNT;
  4016. else if (np->driver_data & DEV_HAS_STATISTICS_V1)
  4017. return NV_DEV_STATISTICS_V1_COUNT;
  4018. else
  4019. return 0;
  4020. default:
  4021. return -EOPNOTSUPP;
  4022. }
  4023. }
  4024. static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
  4025. {
  4026. struct fe_priv *np = netdev_priv(dev);
  4027. /* update stats */
  4028. nv_do_stats_poll((unsigned long)dev);
  4029. memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
  4030. }
  4031. static int nv_link_test(struct net_device *dev)
  4032. {
  4033. struct fe_priv *np = netdev_priv(dev);
  4034. int mii_status;
  4035. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4036. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4037. /* check phy link status */
  4038. if (!(mii_status & BMSR_LSTATUS))
  4039. return 0;
  4040. else
  4041. return 1;
  4042. }
  4043. static int nv_register_test(struct net_device *dev)
  4044. {
  4045. u8 __iomem *base = get_hwbase(dev);
  4046. int i = 0;
  4047. u32 orig_read, new_read;
  4048. do {
  4049. orig_read = readl(base + nv_registers_test[i].reg);
  4050. /* xor with mask to toggle bits */
  4051. orig_read ^= nv_registers_test[i].mask;
  4052. writel(orig_read, base + nv_registers_test[i].reg);
  4053. new_read = readl(base + nv_registers_test[i].reg);
  4054. if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
  4055. return 0;
  4056. /* restore original value */
  4057. orig_read ^= nv_registers_test[i].mask;
  4058. writel(orig_read, base + nv_registers_test[i].reg);
  4059. } while (nv_registers_test[++i].reg != 0);
  4060. return 1;
  4061. }
  4062. static int nv_interrupt_test(struct net_device *dev)
  4063. {
  4064. struct fe_priv *np = netdev_priv(dev);
  4065. u8 __iomem *base = get_hwbase(dev);
  4066. int ret = 1;
  4067. int testcnt;
  4068. u32 save_msi_flags, save_poll_interval = 0;
  4069. if (netif_running(dev)) {
  4070. /* free current irq */
  4071. nv_free_irq(dev);
  4072. save_poll_interval = readl(base+NvRegPollingInterval);
  4073. }
  4074. /* flag to test interrupt handler */
  4075. np->intr_test = 0;
  4076. /* setup test irq */
  4077. save_msi_flags = np->msi_flags;
  4078. np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
  4079. np->msi_flags |= 0x001; /* setup 1 vector */
  4080. if (nv_request_irq(dev, 1))
  4081. return 0;
  4082. /* setup timer interrupt */
  4083. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4084. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4085. nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4086. /* wait for at least one interrupt */
  4087. msleep(100);
  4088. spin_lock_irq(&np->lock);
  4089. /* flag should be set within ISR */
  4090. testcnt = np->intr_test;
  4091. if (!testcnt)
  4092. ret = 2;
  4093. nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4094. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  4095. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4096. else
  4097. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4098. spin_unlock_irq(&np->lock);
  4099. nv_free_irq(dev);
  4100. np->msi_flags = save_msi_flags;
  4101. if (netif_running(dev)) {
  4102. writel(save_poll_interval, base + NvRegPollingInterval);
  4103. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4104. /* restore original irq */
  4105. if (nv_request_irq(dev, 0))
  4106. return 0;
  4107. }
  4108. return ret;
  4109. }
  4110. static int nv_loopback_test(struct net_device *dev)
  4111. {
  4112. struct fe_priv *np = netdev_priv(dev);
  4113. u8 __iomem *base = get_hwbase(dev);
  4114. struct sk_buff *tx_skb, *rx_skb;
  4115. dma_addr_t test_dma_addr;
  4116. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  4117. u32 flags;
  4118. int len, i, pkt_len;
  4119. u8 *pkt_data;
  4120. u32 filter_flags = 0;
  4121. u32 misc1_flags = 0;
  4122. int ret = 1;
  4123. if (netif_running(dev)) {
  4124. nv_disable_irq(dev);
  4125. filter_flags = readl(base + NvRegPacketFilterFlags);
  4126. misc1_flags = readl(base + NvRegMisc1);
  4127. } else {
  4128. nv_txrx_reset(dev);
  4129. }
  4130. /* reinit driver view of the rx queue */
  4131. set_bufsize(dev);
  4132. nv_init_ring(dev);
  4133. /* setup hardware for loopback */
  4134. writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
  4135. writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
  4136. /* reinit nic view of the rx queue */
  4137. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4138. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4139. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4140. base + NvRegRingSizes);
  4141. pci_push(base);
  4142. /* restart rx engine */
  4143. nv_start_rxtx(dev);
  4144. /* setup packet for tx */
  4145. pkt_len = ETH_DATA_LEN;
  4146. tx_skb = dev_alloc_skb(pkt_len);
  4147. if (!tx_skb) {
  4148. netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
  4149. ret = 0;
  4150. goto out;
  4151. }
  4152. test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
  4153. skb_tailroom(tx_skb),
  4154. PCI_DMA_FROMDEVICE);
  4155. pkt_data = skb_put(tx_skb, pkt_len);
  4156. for (i = 0; i < pkt_len; i++)
  4157. pkt_data[i] = (u8)(i & 0xff);
  4158. if (!nv_optimized(np)) {
  4159. np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
  4160. np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4161. } else {
  4162. np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
  4163. np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
  4164. np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4165. }
  4166. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4167. pci_push(get_hwbase(dev));
  4168. msleep(500);
  4169. /* check for rx of the packet */
  4170. if (!nv_optimized(np)) {
  4171. flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
  4172. len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
  4173. } else {
  4174. flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
  4175. len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
  4176. }
  4177. if (flags & NV_RX_AVAIL) {
  4178. ret = 0;
  4179. } else if (np->desc_ver == DESC_VER_1) {
  4180. if (flags & NV_RX_ERROR)
  4181. ret = 0;
  4182. } else {
  4183. if (flags & NV_RX2_ERROR)
  4184. ret = 0;
  4185. }
  4186. if (ret) {
  4187. if (len != pkt_len) {
  4188. ret = 0;
  4189. } else {
  4190. rx_skb = np->rx_skb[0].skb;
  4191. for (i = 0; i < pkt_len; i++) {
  4192. if (rx_skb->data[i] != (u8)(i & 0xff)) {
  4193. ret = 0;
  4194. break;
  4195. }
  4196. }
  4197. }
  4198. }
  4199. pci_unmap_single(np->pci_dev, test_dma_addr,
  4200. (skb_end_pointer(tx_skb) - tx_skb->data),
  4201. PCI_DMA_TODEVICE);
  4202. dev_kfree_skb_any(tx_skb);
  4203. out:
  4204. /* stop engines */
  4205. nv_stop_rxtx(dev);
  4206. nv_txrx_reset(dev);
  4207. /* drain rx queue */
  4208. nv_drain_rxtx(dev);
  4209. if (netif_running(dev)) {
  4210. writel(misc1_flags, base + NvRegMisc1);
  4211. writel(filter_flags, base + NvRegPacketFilterFlags);
  4212. nv_enable_irq(dev);
  4213. }
  4214. return ret;
  4215. }
  4216. static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
  4217. {
  4218. struct fe_priv *np = netdev_priv(dev);
  4219. u8 __iomem *base = get_hwbase(dev);
  4220. int result;
  4221. memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
  4222. if (!nv_link_test(dev)) {
  4223. test->flags |= ETH_TEST_FL_FAILED;
  4224. buffer[0] = 1;
  4225. }
  4226. if (test->flags & ETH_TEST_FL_OFFLINE) {
  4227. if (netif_running(dev)) {
  4228. netif_stop_queue(dev);
  4229. nv_napi_disable(dev);
  4230. netif_tx_lock_bh(dev);
  4231. netif_addr_lock(dev);
  4232. spin_lock_irq(&np->lock);
  4233. nv_disable_hw_interrupts(dev, np->irqmask);
  4234. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  4235. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4236. else
  4237. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4238. /* stop engines */
  4239. nv_stop_rxtx(dev);
  4240. nv_txrx_reset(dev);
  4241. /* drain rx queue */
  4242. nv_drain_rxtx(dev);
  4243. spin_unlock_irq(&np->lock);
  4244. netif_addr_unlock(dev);
  4245. netif_tx_unlock_bh(dev);
  4246. }
  4247. if (!nv_register_test(dev)) {
  4248. test->flags |= ETH_TEST_FL_FAILED;
  4249. buffer[1] = 1;
  4250. }
  4251. result = nv_interrupt_test(dev);
  4252. if (result != 1) {
  4253. test->flags |= ETH_TEST_FL_FAILED;
  4254. buffer[2] = 1;
  4255. }
  4256. if (result == 0) {
  4257. /* bail out */
  4258. return;
  4259. }
  4260. if (!nv_loopback_test(dev)) {
  4261. test->flags |= ETH_TEST_FL_FAILED;
  4262. buffer[3] = 1;
  4263. }
  4264. if (netif_running(dev)) {
  4265. /* reinit driver view of the rx queue */
  4266. set_bufsize(dev);
  4267. if (nv_init_ring(dev)) {
  4268. if (!np->in_shutdown)
  4269. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4270. }
  4271. /* reinit nic view of the rx queue */
  4272. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4273. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4274. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4275. base + NvRegRingSizes);
  4276. pci_push(base);
  4277. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4278. pci_push(base);
  4279. /* restart rx engine */
  4280. nv_start_rxtx(dev);
  4281. netif_start_queue(dev);
  4282. nv_napi_enable(dev);
  4283. nv_enable_hw_interrupts(dev, np->irqmask);
  4284. }
  4285. }
  4286. }
  4287. static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
  4288. {
  4289. switch (stringset) {
  4290. case ETH_SS_STATS:
  4291. memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
  4292. break;
  4293. case ETH_SS_TEST:
  4294. memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
  4295. break;
  4296. }
  4297. }
  4298. static const struct ethtool_ops ops = {
  4299. .get_drvinfo = nv_get_drvinfo,
  4300. .get_link = ethtool_op_get_link,
  4301. .get_wol = nv_get_wol,
  4302. .set_wol = nv_set_wol,
  4303. .get_settings = nv_get_settings,
  4304. .set_settings = nv_set_settings,
  4305. .get_regs_len = nv_get_regs_len,
  4306. .get_regs = nv_get_regs,
  4307. .nway_reset = nv_nway_reset,
  4308. .get_ringparam = nv_get_ringparam,
  4309. .set_ringparam = nv_set_ringparam,
  4310. .get_pauseparam = nv_get_pauseparam,
  4311. .set_pauseparam = nv_set_pauseparam,
  4312. .get_strings = nv_get_strings,
  4313. .get_ethtool_stats = nv_get_ethtool_stats,
  4314. .get_sset_count = nv_get_sset_count,
  4315. .self_test = nv_self_test,
  4316. };
  4317. static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  4318. {
  4319. struct fe_priv *np = get_nvpriv(dev);
  4320. spin_lock_irq(&np->lock);
  4321. /* save vlan group */
  4322. np->vlangrp = grp;
  4323. if (grp) {
  4324. /* enable vlan on MAC */
  4325. np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
  4326. } else {
  4327. /* disable vlan on MAC */
  4328. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
  4329. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
  4330. }
  4331. writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4332. spin_unlock_irq(&np->lock);
  4333. }
  4334. /* The mgmt unit and driver use a semaphore to access the phy during init */
  4335. static int nv_mgmt_acquire_sema(struct net_device *dev)
  4336. {
  4337. struct fe_priv *np = netdev_priv(dev);
  4338. u8 __iomem *base = get_hwbase(dev);
  4339. int i;
  4340. u32 tx_ctrl, mgmt_sema;
  4341. for (i = 0; i < 10; i++) {
  4342. mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
  4343. if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
  4344. break;
  4345. msleep(500);
  4346. }
  4347. if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
  4348. return 0;
  4349. for (i = 0; i < 2; i++) {
  4350. tx_ctrl = readl(base + NvRegTransmitterControl);
  4351. tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
  4352. writel(tx_ctrl, base + NvRegTransmitterControl);
  4353. /* verify that semaphore was acquired */
  4354. tx_ctrl = readl(base + NvRegTransmitterControl);
  4355. if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
  4356. ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
  4357. np->mgmt_sema = 1;
  4358. return 1;
  4359. } else
  4360. udelay(50);
  4361. }
  4362. return 0;
  4363. }
  4364. static void nv_mgmt_release_sema(struct net_device *dev)
  4365. {
  4366. struct fe_priv *np = netdev_priv(dev);
  4367. u8 __iomem *base = get_hwbase(dev);
  4368. u32 tx_ctrl;
  4369. if (np->driver_data & DEV_HAS_MGMT_UNIT) {
  4370. if (np->mgmt_sema) {
  4371. tx_ctrl = readl(base + NvRegTransmitterControl);
  4372. tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
  4373. writel(tx_ctrl, base + NvRegTransmitterControl);
  4374. }
  4375. }
  4376. }
  4377. static int nv_mgmt_get_version(struct net_device *dev)
  4378. {
  4379. struct fe_priv *np = netdev_priv(dev);
  4380. u8 __iomem *base = get_hwbase(dev);
  4381. u32 data_ready = readl(base + NvRegTransmitterControl);
  4382. u32 data_ready2 = 0;
  4383. unsigned long start;
  4384. int ready = 0;
  4385. writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
  4386. writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
  4387. start = jiffies;
  4388. while (time_before(jiffies, start + 5*HZ)) {
  4389. data_ready2 = readl(base + NvRegTransmitterControl);
  4390. if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
  4391. ready = 1;
  4392. break;
  4393. }
  4394. schedule_timeout_uninterruptible(1);
  4395. }
  4396. if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
  4397. return 0;
  4398. np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
  4399. return 1;
  4400. }
  4401. static int nv_open(struct net_device *dev)
  4402. {
  4403. struct fe_priv *np = netdev_priv(dev);
  4404. u8 __iomem *base = get_hwbase(dev);
  4405. int ret = 1;
  4406. int oom, i;
  4407. u32 low;
  4408. /* power up phy */
  4409. mii_rw(dev, np->phyaddr, MII_BMCR,
  4410. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
  4411. nv_txrx_gate(dev, false);
  4412. /* erase previous misconfiguration */
  4413. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  4414. nv_mac_reset(dev);
  4415. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4416. writel(0, base + NvRegMulticastAddrB);
  4417. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4418. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4419. writel(0, base + NvRegPacketFilterFlags);
  4420. writel(0, base + NvRegTransmitterControl);
  4421. writel(0, base + NvRegReceiverControl);
  4422. writel(0, base + NvRegAdapterControl);
  4423. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
  4424. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  4425. /* initialize descriptor rings */
  4426. set_bufsize(dev);
  4427. oom = nv_init_ring(dev);
  4428. writel(0, base + NvRegLinkSpeed);
  4429. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4430. nv_txrx_reset(dev);
  4431. writel(0, base + NvRegUnknownSetupReg6);
  4432. np->in_shutdown = 0;
  4433. /* give hw rings */
  4434. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4435. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4436. base + NvRegRingSizes);
  4437. writel(np->linkspeed, base + NvRegLinkSpeed);
  4438. if (np->desc_ver == DESC_VER_1)
  4439. writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
  4440. else
  4441. writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
  4442. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4443. writel(np->vlanctl_bits, base + NvRegVlanControl);
  4444. pci_push(base);
  4445. writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
  4446. if (reg_delay(dev, NvRegUnknownSetupReg5,
  4447. NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
  4448. NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
  4449. netdev_info(dev,
  4450. "%s: SetupReg5, Bit 31 remained off\n", __func__);
  4451. writel(0, base + NvRegMIIMask);
  4452. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4453. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4454. writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
  4455. writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
  4456. writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
  4457. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4458. writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
  4459. get_random_bytes(&low, sizeof(low));
  4460. low &= NVREG_SLOTTIME_MASK;
  4461. if (np->desc_ver == DESC_VER_1) {
  4462. writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
  4463. } else {
  4464. if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
  4465. /* setup legacy backoff */
  4466. writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
  4467. } else {
  4468. writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
  4469. nv_gear_backoff_reseed(dev);
  4470. }
  4471. }
  4472. writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
  4473. writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
  4474. if (poll_interval == -1) {
  4475. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
  4476. writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
  4477. else
  4478. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4479. } else
  4480. writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
  4481. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4482. writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
  4483. base + NvRegAdapterControl);
  4484. writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
  4485. writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
  4486. if (np->wolenabled)
  4487. writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
  4488. i = readl(base + NvRegPowerState);
  4489. if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
  4490. writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
  4491. pci_push(base);
  4492. udelay(10);
  4493. writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
  4494. nv_disable_hw_interrupts(dev, np->irqmask);
  4495. pci_push(base);
  4496. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4497. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4498. pci_push(base);
  4499. if (nv_request_irq(dev, 0))
  4500. goto out_drain;
  4501. /* ask for interrupts */
  4502. nv_enable_hw_interrupts(dev, np->irqmask);
  4503. spin_lock_irq(&np->lock);
  4504. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4505. writel(0, base + NvRegMulticastAddrB);
  4506. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4507. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4508. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4509. /* One manual link speed update: Interrupts are enabled, future link
  4510. * speed changes cause interrupts and are handled by nv_link_irq().
  4511. */
  4512. {
  4513. u32 miistat;
  4514. miistat = readl(base + NvRegMIIStatus);
  4515. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4516. }
  4517. /* set linkspeed to invalid value, thus force nv_update_linkspeed
  4518. * to init hw */
  4519. np->linkspeed = 0;
  4520. ret = nv_update_linkspeed(dev);
  4521. nv_start_rxtx(dev);
  4522. netif_start_queue(dev);
  4523. nv_napi_enable(dev);
  4524. if (ret) {
  4525. netif_carrier_on(dev);
  4526. } else {
  4527. netdev_info(dev, "no link during initialization\n");
  4528. netif_carrier_off(dev);
  4529. }
  4530. if (oom)
  4531. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4532. /* start statistics timer */
  4533. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4534. mod_timer(&np->stats_poll,
  4535. round_jiffies(jiffies + STATS_INTERVAL));
  4536. spin_unlock_irq(&np->lock);
  4537. return 0;
  4538. out_drain:
  4539. nv_drain_rxtx(dev);
  4540. return ret;
  4541. }
  4542. static int nv_close(struct net_device *dev)
  4543. {
  4544. struct fe_priv *np = netdev_priv(dev);
  4545. u8 __iomem *base;
  4546. spin_lock_irq(&np->lock);
  4547. np->in_shutdown = 1;
  4548. spin_unlock_irq(&np->lock);
  4549. nv_napi_disable(dev);
  4550. synchronize_irq(np->pci_dev->irq);
  4551. del_timer_sync(&np->oom_kick);
  4552. del_timer_sync(&np->nic_poll);
  4553. del_timer_sync(&np->stats_poll);
  4554. netif_stop_queue(dev);
  4555. spin_lock_irq(&np->lock);
  4556. nv_stop_rxtx(dev);
  4557. nv_txrx_reset(dev);
  4558. /* disable interrupts on the nic or we will lock up */
  4559. base = get_hwbase(dev);
  4560. nv_disable_hw_interrupts(dev, np->irqmask);
  4561. pci_push(base);
  4562. spin_unlock_irq(&np->lock);
  4563. nv_free_irq(dev);
  4564. nv_drain_rxtx(dev);
  4565. if (np->wolenabled || !phy_power_down) {
  4566. nv_txrx_gate(dev, false);
  4567. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4568. nv_start_rx(dev);
  4569. } else {
  4570. /* power down phy */
  4571. mii_rw(dev, np->phyaddr, MII_BMCR,
  4572. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
  4573. nv_txrx_gate(dev, true);
  4574. }
  4575. /* FIXME: power down nic */
  4576. return 0;
  4577. }
  4578. static const struct net_device_ops nv_netdev_ops = {
  4579. .ndo_open = nv_open,
  4580. .ndo_stop = nv_close,
  4581. .ndo_get_stats = nv_get_stats,
  4582. .ndo_start_xmit = nv_start_xmit,
  4583. .ndo_tx_timeout = nv_tx_timeout,
  4584. .ndo_change_mtu = nv_change_mtu,
  4585. .ndo_fix_features = nv_fix_features,
  4586. .ndo_set_features = nv_set_features,
  4587. .ndo_validate_addr = eth_validate_addr,
  4588. .ndo_set_mac_address = nv_set_mac_address,
  4589. .ndo_set_multicast_list = nv_set_multicast,
  4590. .ndo_vlan_rx_register = nv_vlan_rx_register,
  4591. #ifdef CONFIG_NET_POLL_CONTROLLER
  4592. .ndo_poll_controller = nv_poll_controller,
  4593. #endif
  4594. };
  4595. static const struct net_device_ops nv_netdev_ops_optimized = {
  4596. .ndo_open = nv_open,
  4597. .ndo_stop = nv_close,
  4598. .ndo_get_stats = nv_get_stats,
  4599. .ndo_start_xmit = nv_start_xmit_optimized,
  4600. .ndo_tx_timeout = nv_tx_timeout,
  4601. .ndo_change_mtu = nv_change_mtu,
  4602. .ndo_fix_features = nv_fix_features,
  4603. .ndo_set_features = nv_set_features,
  4604. .ndo_validate_addr = eth_validate_addr,
  4605. .ndo_set_mac_address = nv_set_mac_address,
  4606. .ndo_set_multicast_list = nv_set_multicast,
  4607. .ndo_vlan_rx_register = nv_vlan_rx_register,
  4608. #ifdef CONFIG_NET_POLL_CONTROLLER
  4609. .ndo_poll_controller = nv_poll_controller,
  4610. #endif
  4611. };
  4612. static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  4613. {
  4614. struct net_device *dev;
  4615. struct fe_priv *np;
  4616. unsigned long addr;
  4617. u8 __iomem *base;
  4618. int err, i;
  4619. u32 powerstate, txreg;
  4620. u32 phystate_orig = 0, phystate;
  4621. int phyinitialized = 0;
  4622. static int printed_version;
  4623. if (!printed_version++)
  4624. pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
  4625. FORCEDETH_VERSION);
  4626. dev = alloc_etherdev(sizeof(struct fe_priv));
  4627. err = -ENOMEM;
  4628. if (!dev)
  4629. goto out;
  4630. np = netdev_priv(dev);
  4631. np->dev = dev;
  4632. np->pci_dev = pci_dev;
  4633. spin_lock_init(&np->lock);
  4634. SET_NETDEV_DEV(dev, &pci_dev->dev);
  4635. init_timer(&np->oom_kick);
  4636. np->oom_kick.data = (unsigned long) dev;
  4637. np->oom_kick.function = nv_do_rx_refill; /* timer handler */
  4638. init_timer(&np->nic_poll);
  4639. np->nic_poll.data = (unsigned long) dev;
  4640. np->nic_poll.function = nv_do_nic_poll; /* timer handler */
  4641. init_timer(&np->stats_poll);
  4642. np->stats_poll.data = (unsigned long) dev;
  4643. np->stats_poll.function = nv_do_stats_poll; /* timer handler */
  4644. err = pci_enable_device(pci_dev);
  4645. if (err)
  4646. goto out_free;
  4647. pci_set_master(pci_dev);
  4648. err = pci_request_regions(pci_dev, DRV_NAME);
  4649. if (err < 0)
  4650. goto out_disable;
  4651. if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4652. np->register_size = NV_PCI_REGSZ_VER3;
  4653. else if (id->driver_data & DEV_HAS_STATISTICS_V1)
  4654. np->register_size = NV_PCI_REGSZ_VER2;
  4655. else
  4656. np->register_size = NV_PCI_REGSZ_VER1;
  4657. err = -EINVAL;
  4658. addr = 0;
  4659. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  4660. if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
  4661. pci_resource_len(pci_dev, i) >= np->register_size) {
  4662. addr = pci_resource_start(pci_dev, i);
  4663. break;
  4664. }
  4665. }
  4666. if (i == DEVICE_COUNT_RESOURCE) {
  4667. dev_info(&pci_dev->dev, "Couldn't find register window\n");
  4668. goto out_relreg;
  4669. }
  4670. /* copy of driver data */
  4671. np->driver_data = id->driver_data;
  4672. /* copy of device id */
  4673. np->device_id = id->device;
  4674. /* handle different descriptor versions */
  4675. if (id->driver_data & DEV_HAS_HIGH_DMA) {
  4676. /* packet format 3: supports 40-bit addressing */
  4677. np->desc_ver = DESC_VER_3;
  4678. np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
  4679. if (dma_64bit) {
  4680. if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
  4681. dev_info(&pci_dev->dev,
  4682. "64-bit DMA failed, using 32-bit addressing\n");
  4683. else
  4684. dev->features |= NETIF_F_HIGHDMA;
  4685. if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
  4686. dev_info(&pci_dev->dev,
  4687. "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
  4688. }
  4689. }
  4690. } else if (id->driver_data & DEV_HAS_LARGEDESC) {
  4691. /* packet format 2: supports jumbo frames */
  4692. np->desc_ver = DESC_VER_2;
  4693. np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
  4694. } else {
  4695. /* original packet format */
  4696. np->desc_ver = DESC_VER_1;
  4697. np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
  4698. }
  4699. np->pkt_limit = NV_PKTLIMIT_1;
  4700. if (id->driver_data & DEV_HAS_LARGEDESC)
  4701. np->pkt_limit = NV_PKTLIMIT_2;
  4702. if (id->driver_data & DEV_HAS_CHECKSUM) {
  4703. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4704. dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
  4705. NETIF_F_TSO | NETIF_F_RXCSUM;
  4706. dev->features |= dev->hw_features;
  4707. }
  4708. np->vlanctl_bits = 0;
  4709. if (id->driver_data & DEV_HAS_VLAN) {
  4710. np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
  4711. dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
  4712. }
  4713. np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
  4714. if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
  4715. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
  4716. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
  4717. np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
  4718. }
  4719. err = -ENOMEM;
  4720. np->base = ioremap(addr, np->register_size);
  4721. if (!np->base)
  4722. goto out_relreg;
  4723. dev->base_addr = (unsigned long)np->base;
  4724. dev->irq = pci_dev->irq;
  4725. np->rx_ring_size = RX_RING_DEFAULT;
  4726. np->tx_ring_size = TX_RING_DEFAULT;
  4727. if (!nv_optimized(np)) {
  4728. np->rx_ring.orig = pci_alloc_consistent(pci_dev,
  4729. sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  4730. &np->ring_addr);
  4731. if (!np->rx_ring.orig)
  4732. goto out_unmap;
  4733. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  4734. } else {
  4735. np->rx_ring.ex = pci_alloc_consistent(pci_dev,
  4736. sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  4737. &np->ring_addr);
  4738. if (!np->rx_ring.ex)
  4739. goto out_unmap;
  4740. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  4741. }
  4742. np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4743. np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4744. if (!np->rx_skb || !np->tx_skb)
  4745. goto out_freering;
  4746. if (!nv_optimized(np))
  4747. dev->netdev_ops = &nv_netdev_ops;
  4748. else
  4749. dev->netdev_ops = &nv_netdev_ops_optimized;
  4750. netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
  4751. SET_ETHTOOL_OPS(dev, &ops);
  4752. dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
  4753. pci_set_drvdata(pci_dev, dev);
  4754. /* read the mac address */
  4755. base = get_hwbase(dev);
  4756. np->orig_mac[0] = readl(base + NvRegMacAddrA);
  4757. np->orig_mac[1] = readl(base + NvRegMacAddrB);
  4758. /* check the workaround bit for correct mac address order */
  4759. txreg = readl(base + NvRegTransmitPoll);
  4760. if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
  4761. /* mac address is already in correct order */
  4762. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4763. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4764. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4765. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4766. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4767. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4768. } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
  4769. /* mac address is already in correct order */
  4770. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4771. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4772. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4773. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4774. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4775. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4776. /*
  4777. * Set orig mac address back to the reversed version.
  4778. * This flag will be cleared during low power transition.
  4779. * Therefore, we should always put back the reversed address.
  4780. */
  4781. np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
  4782. (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
  4783. np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
  4784. } else {
  4785. /* need to reverse mac address to correct order */
  4786. dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
  4787. dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
  4788. dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
  4789. dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
  4790. dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
  4791. dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
  4792. writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4793. dev_dbg(&pci_dev->dev,
  4794. "%s: set workaround bit for reversed mac addr\n",
  4795. __func__);
  4796. }
  4797. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  4798. if (!is_valid_ether_addr(dev->perm_addr)) {
  4799. /*
  4800. * Bad mac address. At least one bios sets the mac address
  4801. * to 01:23:45:67:89:ab
  4802. */
  4803. dev_err(&pci_dev->dev,
  4804. "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
  4805. dev->dev_addr);
  4806. random_ether_addr(dev->dev_addr);
  4807. dev_err(&pci_dev->dev,
  4808. "Using random MAC address: %pM\n", dev->dev_addr);
  4809. }
  4810. /* set mac address */
  4811. nv_copy_mac_to_hw(dev);
  4812. /* disable WOL */
  4813. writel(0, base + NvRegWakeUpFlags);
  4814. np->wolenabled = 0;
  4815. device_set_wakeup_enable(&pci_dev->dev, false);
  4816. if (id->driver_data & DEV_HAS_POWER_CNTRL) {
  4817. /* take phy and nic out of low power mode */
  4818. powerstate = readl(base + NvRegPowerState2);
  4819. powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
  4820. if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
  4821. pci_dev->revision >= 0xA3)
  4822. powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
  4823. writel(powerstate, base + NvRegPowerState2);
  4824. }
  4825. if (np->desc_ver == DESC_VER_1)
  4826. np->tx_flags = NV_TX_VALID;
  4827. else
  4828. np->tx_flags = NV_TX2_VALID;
  4829. np->msi_flags = 0;
  4830. if ((id->driver_data & DEV_HAS_MSI) && msi)
  4831. np->msi_flags |= NV_MSI_CAPABLE;
  4832. if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
  4833. /* msix has had reported issues when modifying irqmask
  4834. as in the case of napi, therefore, disable for now
  4835. */
  4836. #if 0
  4837. np->msi_flags |= NV_MSI_X_CAPABLE;
  4838. #endif
  4839. }
  4840. if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
  4841. np->irqmask = NVREG_IRQMASK_CPU;
  4842. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4843. np->msi_flags |= 0x0001;
  4844. } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
  4845. !(id->driver_data & DEV_NEED_TIMERIRQ)) {
  4846. /* start off in throughput mode */
  4847. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  4848. /* remove support for msix mode */
  4849. np->msi_flags &= ~NV_MSI_X_CAPABLE;
  4850. } else {
  4851. optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
  4852. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  4853. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4854. np->msi_flags |= 0x0003;
  4855. }
  4856. if (id->driver_data & DEV_NEED_TIMERIRQ)
  4857. np->irqmask |= NVREG_IRQ_TIMER;
  4858. if (id->driver_data & DEV_NEED_LINKTIMER) {
  4859. np->need_linktimer = 1;
  4860. np->link_timeout = jiffies + LINK_TIMEOUT;
  4861. } else {
  4862. np->need_linktimer = 0;
  4863. }
  4864. /* Limit the number of tx's outstanding for hw bug */
  4865. if (id->driver_data & DEV_NEED_TX_LIMIT) {
  4866. np->tx_limit = 1;
  4867. if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
  4868. pci_dev->revision >= 0xA2)
  4869. np->tx_limit = 0;
  4870. }
  4871. /* clear phy state and temporarily halt phy interrupts */
  4872. writel(0, base + NvRegMIIMask);
  4873. phystate = readl(base + NvRegAdapterControl);
  4874. if (phystate & NVREG_ADAPTCTL_RUNNING) {
  4875. phystate_orig = 1;
  4876. phystate &= ~NVREG_ADAPTCTL_RUNNING;
  4877. writel(phystate, base + NvRegAdapterControl);
  4878. }
  4879. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4880. if (id->driver_data & DEV_HAS_MGMT_UNIT) {
  4881. /* management unit running on the mac? */
  4882. if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
  4883. (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
  4884. nv_mgmt_acquire_sema(dev) &&
  4885. nv_mgmt_get_version(dev)) {
  4886. np->mac_in_use = 1;
  4887. if (np->mgmt_version > 0)
  4888. np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
  4889. /* management unit setup the phy already? */
  4890. if (np->mac_in_use &&
  4891. ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
  4892. NVREG_XMITCTL_SYNC_PHY_INIT)) {
  4893. /* phy is inited by mgmt unit */
  4894. phyinitialized = 1;
  4895. } else {
  4896. /* we need to init the phy */
  4897. }
  4898. }
  4899. }
  4900. /* find a suitable phy */
  4901. for (i = 1; i <= 32; i++) {
  4902. int id1, id2;
  4903. int phyaddr = i & 0x1F;
  4904. spin_lock_irq(&np->lock);
  4905. id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
  4906. spin_unlock_irq(&np->lock);
  4907. if (id1 < 0 || id1 == 0xffff)
  4908. continue;
  4909. spin_lock_irq(&np->lock);
  4910. id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
  4911. spin_unlock_irq(&np->lock);
  4912. if (id2 < 0 || id2 == 0xffff)
  4913. continue;
  4914. np->phy_model = id2 & PHYID2_MODEL_MASK;
  4915. id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
  4916. id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
  4917. np->phyaddr = phyaddr;
  4918. np->phy_oui = id1 | id2;
  4919. /* Realtek hardcoded phy id1 to all zero's on certain phys */
  4920. if (np->phy_oui == PHY_OUI_REALTEK2)
  4921. np->phy_oui = PHY_OUI_REALTEK;
  4922. /* Setup phy revision for Realtek */
  4923. if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
  4924. np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
  4925. break;
  4926. }
  4927. if (i == 33) {
  4928. dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
  4929. goto out_error;
  4930. }
  4931. if (!phyinitialized) {
  4932. /* reset it */
  4933. phy_init(dev);
  4934. } else {
  4935. /* see if it is a gigabit phy */
  4936. u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4937. if (mii_status & PHY_GIGABIT)
  4938. np->gigabit = PHY_GIGABIT;
  4939. }
  4940. /* set default link speed settings */
  4941. np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  4942. np->duplex = 0;
  4943. np->autoneg = 1;
  4944. err = register_netdev(dev);
  4945. if (err) {
  4946. dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
  4947. goto out_error;
  4948. }
  4949. netif_carrier_off(dev);
  4950. dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
  4951. dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
  4952. dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
  4953. dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
  4954. dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
  4955. "csum " : "",
  4956. dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
  4957. "vlan " : "",
  4958. id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
  4959. id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
  4960. id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
  4961. np->gigabit == PHY_GIGABIT ? "gbit " : "",
  4962. np->need_linktimer ? "lnktim " : "",
  4963. np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
  4964. np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
  4965. np->desc_ver);
  4966. return 0;
  4967. out_error:
  4968. if (phystate_orig)
  4969. writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
  4970. pci_set_drvdata(pci_dev, NULL);
  4971. out_freering:
  4972. free_rings(dev);
  4973. out_unmap:
  4974. iounmap(get_hwbase(dev));
  4975. out_relreg:
  4976. pci_release_regions(pci_dev);
  4977. out_disable:
  4978. pci_disable_device(pci_dev);
  4979. out_free:
  4980. free_netdev(dev);
  4981. out:
  4982. return err;
  4983. }
  4984. static void nv_restore_phy(struct net_device *dev)
  4985. {
  4986. struct fe_priv *np = netdev_priv(dev);
  4987. u16 phy_reserved, mii_control;
  4988. if (np->phy_oui == PHY_OUI_REALTEK &&
  4989. np->phy_model == PHY_MODEL_REALTEK_8201 &&
  4990. phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  4991. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
  4992. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
  4993. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  4994. phy_reserved |= PHY_REALTEK_INIT8;
  4995. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
  4996. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
  4997. /* restart auto negotiation */
  4998. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  4999. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  5000. mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
  5001. }
  5002. }
  5003. static void nv_restore_mac_addr(struct pci_dev *pci_dev)
  5004. {
  5005. struct net_device *dev = pci_get_drvdata(pci_dev);
  5006. struct fe_priv *np = netdev_priv(dev);
  5007. u8 __iomem *base = get_hwbase(dev);
  5008. /* special op: write back the misordered MAC address - otherwise
  5009. * the next nv_probe would see a wrong address.
  5010. */
  5011. writel(np->orig_mac[0], base + NvRegMacAddrA);
  5012. writel(np->orig_mac[1], base + NvRegMacAddrB);
  5013. writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  5014. base + NvRegTransmitPoll);
  5015. }
  5016. static void __devexit nv_remove(struct pci_dev *pci_dev)
  5017. {
  5018. struct net_device *dev = pci_get_drvdata(pci_dev);
  5019. unregister_netdev(dev);
  5020. nv_restore_mac_addr(pci_dev);
  5021. /* restore any phy related changes */
  5022. nv_restore_phy(dev);
  5023. nv_mgmt_release_sema(dev);
  5024. /* free all structures */
  5025. free_rings(dev);
  5026. iounmap(get_hwbase(dev));
  5027. pci_release_regions(pci_dev);
  5028. pci_disable_device(pci_dev);
  5029. free_netdev(dev);
  5030. pci_set_drvdata(pci_dev, NULL);
  5031. }
  5032. #ifdef CONFIG_PM_SLEEP
  5033. static int nv_suspend(struct device *device)
  5034. {
  5035. struct pci_dev *pdev = to_pci_dev(device);
  5036. struct net_device *dev = pci_get_drvdata(pdev);
  5037. struct fe_priv *np = netdev_priv(dev);
  5038. u8 __iomem *base = get_hwbase(dev);
  5039. int i;
  5040. if (netif_running(dev)) {
  5041. /* Gross. */
  5042. nv_close(dev);
  5043. }
  5044. netif_device_detach(dev);
  5045. /* save non-pci configuration space */
  5046. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  5047. np->saved_config_space[i] = readl(base + i*sizeof(u32));
  5048. return 0;
  5049. }
  5050. static int nv_resume(struct device *device)
  5051. {
  5052. struct pci_dev *pdev = to_pci_dev(device);
  5053. struct net_device *dev = pci_get_drvdata(pdev);
  5054. struct fe_priv *np = netdev_priv(dev);
  5055. u8 __iomem *base = get_hwbase(dev);
  5056. int i, rc = 0;
  5057. /* restore non-pci configuration space */
  5058. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  5059. writel(np->saved_config_space[i], base+i*sizeof(u32));
  5060. if (np->driver_data & DEV_NEED_MSI_FIX)
  5061. pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
  5062. /* restore phy state, including autoneg */
  5063. phy_init(dev);
  5064. netif_device_attach(dev);
  5065. if (netif_running(dev)) {
  5066. rc = nv_open(dev);
  5067. nv_set_multicast(dev);
  5068. }
  5069. return rc;
  5070. }
  5071. static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
  5072. #define NV_PM_OPS (&nv_pm_ops)
  5073. #else
  5074. #define NV_PM_OPS NULL
  5075. #endif /* CONFIG_PM_SLEEP */
  5076. #ifdef CONFIG_PM
  5077. static void nv_shutdown(struct pci_dev *pdev)
  5078. {
  5079. struct net_device *dev = pci_get_drvdata(pdev);
  5080. struct fe_priv *np = netdev_priv(dev);
  5081. if (netif_running(dev))
  5082. nv_close(dev);
  5083. /*
  5084. * Restore the MAC so a kernel started by kexec won't get confused.
  5085. * If we really go for poweroff, we must not restore the MAC,
  5086. * otherwise the MAC for WOL will be reversed at least on some boards.
  5087. */
  5088. if (system_state != SYSTEM_POWER_OFF)
  5089. nv_restore_mac_addr(pdev);
  5090. pci_disable_device(pdev);
  5091. /*
  5092. * Apparently it is not possible to reinitialise from D3 hot,
  5093. * only put the device into D3 if we really go for poweroff.
  5094. */
  5095. if (system_state == SYSTEM_POWER_OFF) {
  5096. pci_wake_from_d3(pdev, np->wolenabled);
  5097. pci_set_power_state(pdev, PCI_D3hot);
  5098. }
  5099. }
  5100. #else
  5101. #define nv_shutdown NULL
  5102. #endif /* CONFIG_PM */
  5103. static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
  5104. { /* nForce Ethernet Controller */
  5105. PCI_DEVICE(0x10DE, 0x01C3),
  5106. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5107. },
  5108. { /* nForce2 Ethernet Controller */
  5109. PCI_DEVICE(0x10DE, 0x0066),
  5110. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5111. },
  5112. { /* nForce3 Ethernet Controller */
  5113. PCI_DEVICE(0x10DE, 0x00D6),
  5114. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5115. },
  5116. { /* nForce3 Ethernet Controller */
  5117. PCI_DEVICE(0x10DE, 0x0086),
  5118. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5119. },
  5120. { /* nForce3 Ethernet Controller */
  5121. PCI_DEVICE(0x10DE, 0x008C),
  5122. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5123. },
  5124. { /* nForce3 Ethernet Controller */
  5125. PCI_DEVICE(0x10DE, 0x00E6),
  5126. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5127. },
  5128. { /* nForce3 Ethernet Controller */
  5129. PCI_DEVICE(0x10DE, 0x00DF),
  5130. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5131. },
  5132. { /* CK804 Ethernet Controller */
  5133. PCI_DEVICE(0x10DE, 0x0056),
  5134. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5135. },
  5136. { /* CK804 Ethernet Controller */
  5137. PCI_DEVICE(0x10DE, 0x0057),
  5138. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5139. },
  5140. { /* MCP04 Ethernet Controller */
  5141. PCI_DEVICE(0x10DE, 0x0037),
  5142. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5143. },
  5144. { /* MCP04 Ethernet Controller */
  5145. PCI_DEVICE(0x10DE, 0x0038),
  5146. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5147. },
  5148. { /* MCP51 Ethernet Controller */
  5149. PCI_DEVICE(0x10DE, 0x0268),
  5150. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5151. },
  5152. { /* MCP51 Ethernet Controller */
  5153. PCI_DEVICE(0x10DE, 0x0269),
  5154. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5155. },
  5156. { /* MCP55 Ethernet Controller */
  5157. PCI_DEVICE(0x10DE, 0x0372),
  5158. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5159. },
  5160. { /* MCP55 Ethernet Controller */
  5161. PCI_DEVICE(0x10DE, 0x0373),
  5162. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5163. },
  5164. { /* MCP61 Ethernet Controller */
  5165. PCI_DEVICE(0x10DE, 0x03E5),
  5166. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5167. },
  5168. { /* MCP61 Ethernet Controller */
  5169. PCI_DEVICE(0x10DE, 0x03E6),
  5170. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5171. },
  5172. { /* MCP61 Ethernet Controller */
  5173. PCI_DEVICE(0x10DE, 0x03EE),
  5174. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5175. },
  5176. { /* MCP61 Ethernet Controller */
  5177. PCI_DEVICE(0x10DE, 0x03EF),
  5178. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5179. },
  5180. { /* MCP65 Ethernet Controller */
  5181. PCI_DEVICE(0x10DE, 0x0450),
  5182. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5183. },
  5184. { /* MCP65 Ethernet Controller */
  5185. PCI_DEVICE(0x10DE, 0x0451),
  5186. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5187. },
  5188. { /* MCP65 Ethernet Controller */
  5189. PCI_DEVICE(0x10DE, 0x0452),
  5190. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5191. },
  5192. { /* MCP65 Ethernet Controller */
  5193. PCI_DEVICE(0x10DE, 0x0453),
  5194. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5195. },
  5196. { /* MCP67 Ethernet Controller */
  5197. PCI_DEVICE(0x10DE, 0x054C),
  5198. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5199. },
  5200. { /* MCP67 Ethernet Controller */
  5201. PCI_DEVICE(0x10DE, 0x054D),
  5202. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5203. },
  5204. { /* MCP67 Ethernet Controller */
  5205. PCI_DEVICE(0x10DE, 0x054E),
  5206. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5207. },
  5208. { /* MCP67 Ethernet Controller */
  5209. PCI_DEVICE(0x10DE, 0x054F),
  5210. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5211. },
  5212. { /* MCP73 Ethernet Controller */
  5213. PCI_DEVICE(0x10DE, 0x07DC),
  5214. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5215. },
  5216. { /* MCP73 Ethernet Controller */
  5217. PCI_DEVICE(0x10DE, 0x07DD),
  5218. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5219. },
  5220. { /* MCP73 Ethernet Controller */
  5221. PCI_DEVICE(0x10DE, 0x07DE),
  5222. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5223. },
  5224. { /* MCP73 Ethernet Controller */
  5225. PCI_DEVICE(0x10DE, 0x07DF),
  5226. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5227. },
  5228. { /* MCP77 Ethernet Controller */
  5229. PCI_DEVICE(0x10DE, 0x0760),
  5230. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5231. },
  5232. { /* MCP77 Ethernet Controller */
  5233. PCI_DEVICE(0x10DE, 0x0761),
  5234. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5235. },
  5236. { /* MCP77 Ethernet Controller */
  5237. PCI_DEVICE(0x10DE, 0x0762),
  5238. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5239. },
  5240. { /* MCP77 Ethernet Controller */
  5241. PCI_DEVICE(0x10DE, 0x0763),
  5242. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5243. },
  5244. { /* MCP79 Ethernet Controller */
  5245. PCI_DEVICE(0x10DE, 0x0AB0),
  5246. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5247. },
  5248. { /* MCP79 Ethernet Controller */
  5249. PCI_DEVICE(0x10DE, 0x0AB1),
  5250. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5251. },
  5252. { /* MCP79 Ethernet Controller */
  5253. PCI_DEVICE(0x10DE, 0x0AB2),
  5254. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5255. },
  5256. { /* MCP79 Ethernet Controller */
  5257. PCI_DEVICE(0x10DE, 0x0AB3),
  5258. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5259. },
  5260. { /* MCP89 Ethernet Controller */
  5261. PCI_DEVICE(0x10DE, 0x0D7D),
  5262. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
  5263. },
  5264. {0,},
  5265. };
  5266. static struct pci_driver driver = {
  5267. .name = DRV_NAME,
  5268. .id_table = pci_tbl,
  5269. .probe = nv_probe,
  5270. .remove = __devexit_p(nv_remove),
  5271. .shutdown = nv_shutdown,
  5272. .driver.pm = NV_PM_OPS,
  5273. };
  5274. static int __init init_nic(void)
  5275. {
  5276. return pci_register_driver(&driver);
  5277. }
  5278. static void __exit exit_nic(void)
  5279. {
  5280. pci_unregister_driver(&driver);
  5281. }
  5282. module_param(max_interrupt_work, int, 0);
  5283. MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
  5284. module_param(optimization_mode, int, 0);
  5285. MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
  5286. module_param(poll_interval, int, 0);
  5287. MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
  5288. module_param(msi, int, 0);
  5289. MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5290. module_param(msix, int, 0);
  5291. MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5292. module_param(dma_64bit, int, 0);
  5293. MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
  5294. module_param(phy_cross, int, 0);
  5295. MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
  5296. module_param(phy_power_down, int, 0);
  5297. MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
  5298. MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
  5299. MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
  5300. MODULE_LICENSE("GPL");
  5301. MODULE_DEVICE_TABLE(pci, pci_tbl);
  5302. module_init(init_nic);
  5303. module_exit(exit_nic);