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/drivers/net/cnic.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 5454 lines | 4415 code | 972 blank | 67 comment | 632 complexity | 3e06451f8280a2f355f843f82eb02300 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  29. #define BCM_VLAN 1
  30. #endif
  31. #include <net/ip.h>
  32. #include <net/tcp.h>
  33. #include <net/route.h>
  34. #include <net/ipv6.h>
  35. #include <net/ip6_route.h>
  36. #include <net/ip6_checksum.h>
  37. #include <scsi/iscsi_if.h>
  38. #include "cnic_if.h"
  39. #include "bnx2.h"
  40. #include "bnx2x/bnx2x_reg.h"
  41. #include "bnx2x/bnx2x_fw_defs.h"
  42. #include "bnx2x/bnx2x_hsi.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  45. #include "cnic.h"
  46. #include "cnic_defs.h"
  47. #define DRV_MODULE_NAME "cnic"
  48. static char version[] __devinitdata =
  49. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  50. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  51. "Chen (zongxi@broadcom.com");
  52. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  53. MODULE_LICENSE("GPL");
  54. MODULE_VERSION(CNIC_MODULE_VERSION);
  55. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  56. static LIST_HEAD(cnic_dev_list);
  57. static LIST_HEAD(cnic_udev_list);
  58. static DEFINE_RWLOCK(cnic_dev_lock);
  59. static DEFINE_MUTEX(cnic_lock);
  60. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  61. /* helper function, assuming cnic_lock is held */
  62. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  63. {
  64. return rcu_dereference_protected(cnic_ulp_tbl[type],
  65. lockdep_is_held(&cnic_lock));
  66. }
  67. static int cnic_service_bnx2(void *, void *);
  68. static int cnic_service_bnx2x(void *, void *);
  69. static int cnic_ctl(void *, struct cnic_ctl_info *);
  70. static struct cnic_ops cnic_bnx2_ops = {
  71. .cnic_owner = THIS_MODULE,
  72. .cnic_handler = cnic_service_bnx2,
  73. .cnic_ctl = cnic_ctl,
  74. };
  75. static struct cnic_ops cnic_bnx2x_ops = {
  76. .cnic_owner = THIS_MODULE,
  77. .cnic_handler = cnic_service_bnx2x,
  78. .cnic_ctl = cnic_ctl,
  79. };
  80. static struct workqueue_struct *cnic_wq;
  81. static void cnic_shutdown_rings(struct cnic_dev *);
  82. static void cnic_init_rings(struct cnic_dev *);
  83. static int cnic_cm_set_pg(struct cnic_sock *);
  84. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  85. {
  86. struct cnic_uio_dev *udev = uinfo->priv;
  87. struct cnic_dev *dev;
  88. if (!capable(CAP_NET_ADMIN))
  89. return -EPERM;
  90. if (udev->uio_dev != -1)
  91. return -EBUSY;
  92. rtnl_lock();
  93. dev = udev->dev;
  94. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  95. rtnl_unlock();
  96. return -ENODEV;
  97. }
  98. udev->uio_dev = iminor(inode);
  99. cnic_shutdown_rings(dev);
  100. cnic_init_rings(dev);
  101. rtnl_unlock();
  102. return 0;
  103. }
  104. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  105. {
  106. struct cnic_uio_dev *udev = uinfo->priv;
  107. udev->uio_dev = -1;
  108. return 0;
  109. }
  110. static inline void cnic_hold(struct cnic_dev *dev)
  111. {
  112. atomic_inc(&dev->ref_count);
  113. }
  114. static inline void cnic_put(struct cnic_dev *dev)
  115. {
  116. atomic_dec(&dev->ref_count);
  117. }
  118. static inline void csk_hold(struct cnic_sock *csk)
  119. {
  120. atomic_inc(&csk->ref_count);
  121. }
  122. static inline void csk_put(struct cnic_sock *csk)
  123. {
  124. atomic_dec(&csk->ref_count);
  125. }
  126. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  127. {
  128. struct cnic_dev *cdev;
  129. read_lock(&cnic_dev_lock);
  130. list_for_each_entry(cdev, &cnic_dev_list, list) {
  131. if (netdev == cdev->netdev) {
  132. cnic_hold(cdev);
  133. read_unlock(&cnic_dev_lock);
  134. return cdev;
  135. }
  136. }
  137. read_unlock(&cnic_dev_lock);
  138. return NULL;
  139. }
  140. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  141. {
  142. atomic_inc(&ulp_ops->ref_count);
  143. }
  144. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_dec(&ulp_ops->ref_count);
  147. }
  148. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  149. {
  150. struct cnic_local *cp = dev->cnic_priv;
  151. struct cnic_eth_dev *ethdev = cp->ethdev;
  152. struct drv_ctl_info info;
  153. struct drv_ctl_io *io = &info.data.io;
  154. info.cmd = DRV_CTL_CTX_WR_CMD;
  155. io->cid_addr = cid_addr;
  156. io->offset = off;
  157. io->data = val;
  158. ethdev->drv_ctl(dev->netdev, &info);
  159. }
  160. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  161. {
  162. struct cnic_local *cp = dev->cnic_priv;
  163. struct cnic_eth_dev *ethdev = cp->ethdev;
  164. struct drv_ctl_info info;
  165. struct drv_ctl_io *io = &info.data.io;
  166. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  167. io->offset = off;
  168. io->dma_addr = addr;
  169. ethdev->drv_ctl(dev->netdev, &info);
  170. }
  171. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  172. {
  173. struct cnic_local *cp = dev->cnic_priv;
  174. struct cnic_eth_dev *ethdev = cp->ethdev;
  175. struct drv_ctl_info info;
  176. struct drv_ctl_l2_ring *ring = &info.data.ring;
  177. if (start)
  178. info.cmd = DRV_CTL_START_L2_CMD;
  179. else
  180. info.cmd = DRV_CTL_STOP_L2_CMD;
  181. ring->cid = cid;
  182. ring->client_id = cl_id;
  183. ethdev->drv_ctl(dev->netdev, &info);
  184. }
  185. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  186. {
  187. struct cnic_local *cp = dev->cnic_priv;
  188. struct cnic_eth_dev *ethdev = cp->ethdev;
  189. struct drv_ctl_info info;
  190. struct drv_ctl_io *io = &info.data.io;
  191. info.cmd = DRV_CTL_IO_WR_CMD;
  192. io->offset = off;
  193. io->data = val;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. }
  196. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  197. {
  198. struct cnic_local *cp = dev->cnic_priv;
  199. struct cnic_eth_dev *ethdev = cp->ethdev;
  200. struct drv_ctl_info info;
  201. struct drv_ctl_io *io = &info.data.io;
  202. info.cmd = DRV_CTL_IO_RD_CMD;
  203. io->offset = off;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. return io->data;
  206. }
  207. static int cnic_in_use(struct cnic_sock *csk)
  208. {
  209. return test_bit(SK_F_INUSE, &csk->flags);
  210. }
  211. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. info.cmd = cmd;
  217. info.data.credit.credit_count = count;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  221. {
  222. u32 i;
  223. for (i = 0; i < cp->max_cid_space; i++) {
  224. if (cp->ctx_tbl[i].cid == cid) {
  225. *l5_cid = i;
  226. return 0;
  227. }
  228. }
  229. return -EINVAL;
  230. }
  231. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  232. struct cnic_sock *csk)
  233. {
  234. struct iscsi_path path_req;
  235. char *buf = NULL;
  236. u16 len = 0;
  237. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  238. struct cnic_ulp_ops *ulp_ops;
  239. struct cnic_uio_dev *udev = cp->udev;
  240. int rc = 0, retry = 0;
  241. if (!udev || udev->uio_dev == -1)
  242. return -ENODEV;
  243. if (csk) {
  244. len = sizeof(path_req);
  245. buf = (char *) &path_req;
  246. memset(&path_req, 0, len);
  247. msg_type = ISCSI_KEVENT_PATH_REQ;
  248. path_req.handle = (u64) csk->l5_cid;
  249. if (test_bit(SK_F_IPV6, &csk->flags)) {
  250. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  251. sizeof(struct in6_addr));
  252. path_req.ip_addr_len = 16;
  253. } else {
  254. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  255. sizeof(struct in_addr));
  256. path_req.ip_addr_len = 4;
  257. }
  258. path_req.vlan_id = csk->vlan_id;
  259. path_req.pmtu = csk->mtu;
  260. }
  261. while (retry < 3) {
  262. rc = 0;
  263. rcu_read_lock();
  264. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  265. if (ulp_ops)
  266. rc = ulp_ops->iscsi_nl_send_msg(
  267. cp->ulp_handle[CNIC_ULP_ISCSI],
  268. msg_type, buf, len);
  269. rcu_read_unlock();
  270. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  271. break;
  272. msleep(100);
  273. retry++;
  274. }
  275. return 0;
  276. }
  277. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  278. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  279. char *buf, u16 len)
  280. {
  281. int rc = -EINVAL;
  282. switch (msg_type) {
  283. case ISCSI_UEVENT_PATH_UPDATE: {
  284. struct cnic_local *cp;
  285. u32 l5_cid;
  286. struct cnic_sock *csk;
  287. struct iscsi_path *path_resp;
  288. if (len < sizeof(*path_resp))
  289. break;
  290. path_resp = (struct iscsi_path *) buf;
  291. cp = dev->cnic_priv;
  292. l5_cid = (u32) path_resp->handle;
  293. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  294. break;
  295. rcu_read_lock();
  296. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  297. rc = -ENODEV;
  298. rcu_read_unlock();
  299. break;
  300. }
  301. csk = &cp->csk_tbl[l5_cid];
  302. csk_hold(csk);
  303. if (cnic_in_use(csk) &&
  304. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. memcpy(csk->ha, path_resp->mac_addr, 6);
  306. if (test_bit(SK_F_IPV6, &csk->flags))
  307. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  308. sizeof(struct in6_addr));
  309. else
  310. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  311. sizeof(struct in_addr));
  312. if (is_valid_ether_addr(csk->ha)) {
  313. cnic_cm_set_pg(csk);
  314. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  315. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  316. cnic_cm_upcall(cp, csk,
  317. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  318. clear_bit(SK_F_CONNECT_START, &csk->flags);
  319. }
  320. }
  321. csk_put(csk);
  322. rcu_read_unlock();
  323. rc = 0;
  324. }
  325. }
  326. return rc;
  327. }
  328. static int cnic_offld_prep(struct cnic_sock *csk)
  329. {
  330. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  331. return 0;
  332. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  334. return 0;
  335. }
  336. return 1;
  337. }
  338. static int cnic_close_prep(struct cnic_sock *csk)
  339. {
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. smp_mb__after_clear_bit();
  342. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  343. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. msleep(1);
  345. return 1;
  346. }
  347. return 0;
  348. }
  349. static int cnic_abort_prep(struct cnic_sock *csk)
  350. {
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. smp_mb__after_clear_bit();
  353. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. msleep(1);
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  357. return 1;
  358. }
  359. return 0;
  360. }
  361. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  362. {
  363. struct cnic_dev *dev;
  364. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  365. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  366. return -EINVAL;
  367. }
  368. mutex_lock(&cnic_lock);
  369. if (cnic_ulp_tbl_prot(ulp_type)) {
  370. pr_err("%s: Type %d has already been registered\n",
  371. __func__, ulp_type);
  372. mutex_unlock(&cnic_lock);
  373. return -EBUSY;
  374. }
  375. read_lock(&cnic_dev_lock);
  376. list_for_each_entry(dev, &cnic_dev_list, list) {
  377. struct cnic_local *cp = dev->cnic_priv;
  378. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  379. }
  380. read_unlock(&cnic_dev_lock);
  381. atomic_set(&ulp_ops->ref_count, 0);
  382. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  383. mutex_unlock(&cnic_lock);
  384. /* Prevent race conditions with netdev_event */
  385. rtnl_lock();
  386. list_for_each_entry(dev, &cnic_dev_list, list) {
  387. struct cnic_local *cp = dev->cnic_priv;
  388. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  389. ulp_ops->cnic_init(dev);
  390. }
  391. rtnl_unlock();
  392. return 0;
  393. }
  394. int cnic_unregister_driver(int ulp_type)
  395. {
  396. struct cnic_dev *dev;
  397. struct cnic_ulp_ops *ulp_ops;
  398. int i = 0;
  399. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  400. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  401. return -EINVAL;
  402. }
  403. mutex_lock(&cnic_lock);
  404. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  405. if (!ulp_ops) {
  406. pr_err("%s: Type %d has not been registered\n",
  407. __func__, ulp_type);
  408. goto out_unlock;
  409. }
  410. read_lock(&cnic_dev_lock);
  411. list_for_each_entry(dev, &cnic_dev_list, list) {
  412. struct cnic_local *cp = dev->cnic_priv;
  413. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  414. pr_err("%s: Type %d still has devices registered\n",
  415. __func__, ulp_type);
  416. read_unlock(&cnic_dev_lock);
  417. goto out_unlock;
  418. }
  419. }
  420. read_unlock(&cnic_dev_lock);
  421. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  422. mutex_unlock(&cnic_lock);
  423. synchronize_rcu();
  424. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  425. msleep(100);
  426. i++;
  427. }
  428. if (atomic_read(&ulp_ops->ref_count) != 0)
  429. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  430. return 0;
  431. out_unlock:
  432. mutex_unlock(&cnic_lock);
  433. return -EINVAL;
  434. }
  435. static int cnic_start_hw(struct cnic_dev *);
  436. static void cnic_stop_hw(struct cnic_dev *);
  437. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  438. void *ulp_ctx)
  439. {
  440. struct cnic_local *cp = dev->cnic_priv;
  441. struct cnic_ulp_ops *ulp_ops;
  442. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  443. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  444. return -EINVAL;
  445. }
  446. mutex_lock(&cnic_lock);
  447. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  448. pr_err("%s: Driver with type %d has not been registered\n",
  449. __func__, ulp_type);
  450. mutex_unlock(&cnic_lock);
  451. return -EAGAIN;
  452. }
  453. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  454. pr_err("%s: Type %d has already been registered to this device\n",
  455. __func__, ulp_type);
  456. mutex_unlock(&cnic_lock);
  457. return -EBUSY;
  458. }
  459. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  460. cp->ulp_handle[ulp_type] = ulp_ctx;
  461. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  462. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  463. cnic_hold(dev);
  464. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  465. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  466. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  467. mutex_unlock(&cnic_lock);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(cnic_register_driver);
  471. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. int i = 0;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  482. cnic_put(dev);
  483. } else {
  484. pr_err("%s: device not registered to this ulp type %d\n",
  485. __func__, ulp_type);
  486. mutex_unlock(&cnic_lock);
  487. return -EINVAL;
  488. }
  489. mutex_unlock(&cnic_lock);
  490. if (ulp_type == CNIC_ULP_ISCSI)
  491. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  492. synchronize_rcu();
  493. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  494. i < 20) {
  495. msleep(100);
  496. i++;
  497. }
  498. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  499. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(cnic_unregister_driver);
  503. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  504. u32 next)
  505. {
  506. id_tbl->start = start_id;
  507. id_tbl->max = size;
  508. id_tbl->next = next;
  509. spin_lock_init(&id_tbl->lock);
  510. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  511. if (!id_tbl->table)
  512. return -ENOMEM;
  513. return 0;
  514. }
  515. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  516. {
  517. kfree(id_tbl->table);
  518. id_tbl->table = NULL;
  519. }
  520. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  521. {
  522. int ret = -1;
  523. id -= id_tbl->start;
  524. if (id >= id_tbl->max)
  525. return ret;
  526. spin_lock(&id_tbl->lock);
  527. if (!test_bit(id, id_tbl->table)) {
  528. set_bit(id, id_tbl->table);
  529. ret = 0;
  530. }
  531. spin_unlock(&id_tbl->lock);
  532. return ret;
  533. }
  534. /* Returns -1 if not successful */
  535. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  536. {
  537. u32 id;
  538. spin_lock(&id_tbl->lock);
  539. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  540. if (id >= id_tbl->max) {
  541. id = -1;
  542. if (id_tbl->next != 0) {
  543. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  544. if (id >= id_tbl->next)
  545. id = -1;
  546. }
  547. }
  548. if (id < id_tbl->max) {
  549. set_bit(id, id_tbl->table);
  550. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  551. id += id_tbl->start;
  552. }
  553. spin_unlock(&id_tbl->lock);
  554. return id;
  555. }
  556. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  557. {
  558. if (id == -1)
  559. return;
  560. id -= id_tbl->start;
  561. if (id >= id_tbl->max)
  562. return;
  563. clear_bit(id, id_tbl->table);
  564. }
  565. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  566. {
  567. int i;
  568. if (!dma->pg_arr)
  569. return;
  570. for (i = 0; i < dma->num_pages; i++) {
  571. if (dma->pg_arr[i]) {
  572. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  573. dma->pg_arr[i], dma->pg_map_arr[i]);
  574. dma->pg_arr[i] = NULL;
  575. }
  576. }
  577. if (dma->pgtbl) {
  578. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  579. dma->pgtbl, dma->pgtbl_map);
  580. dma->pgtbl = NULL;
  581. }
  582. kfree(dma->pg_arr);
  583. dma->pg_arr = NULL;
  584. dma->num_pages = 0;
  585. }
  586. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  587. {
  588. int i;
  589. __le32 *page_table = (__le32 *) dma->pgtbl;
  590. for (i = 0; i < dma->num_pages; i++) {
  591. /* Each entry needs to be in big endian format. */
  592. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  593. page_table++;
  594. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  595. page_table++;
  596. }
  597. }
  598. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  599. {
  600. int i;
  601. __le32 *page_table = (__le32 *) dma->pgtbl;
  602. for (i = 0; i < dma->num_pages; i++) {
  603. /* Each entry needs to be in little endian format. */
  604. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  605. page_table++;
  606. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  607. page_table++;
  608. }
  609. }
  610. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  611. int pages, int use_pg_tbl)
  612. {
  613. int i, size;
  614. struct cnic_local *cp = dev->cnic_priv;
  615. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  616. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  617. if (dma->pg_arr == NULL)
  618. return -ENOMEM;
  619. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  620. dma->num_pages = pages;
  621. for (i = 0; i < pages; i++) {
  622. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  623. BCM_PAGE_SIZE,
  624. &dma->pg_map_arr[i],
  625. GFP_ATOMIC);
  626. if (dma->pg_arr[i] == NULL)
  627. goto error;
  628. }
  629. if (!use_pg_tbl)
  630. return 0;
  631. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  632. ~(BCM_PAGE_SIZE - 1);
  633. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  634. &dma->pgtbl_map, GFP_ATOMIC);
  635. if (dma->pgtbl == NULL)
  636. goto error;
  637. cp->setup_pgtbl(dev, dma);
  638. return 0;
  639. error:
  640. cnic_free_dma(dev, dma);
  641. return -ENOMEM;
  642. }
  643. static void cnic_free_context(struct cnic_dev *dev)
  644. {
  645. struct cnic_local *cp = dev->cnic_priv;
  646. int i;
  647. for (i = 0; i < cp->ctx_blks; i++) {
  648. if (cp->ctx_arr[i].ctx) {
  649. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  650. cp->ctx_arr[i].ctx,
  651. cp->ctx_arr[i].mapping);
  652. cp->ctx_arr[i].ctx = NULL;
  653. }
  654. }
  655. }
  656. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  657. {
  658. uio_unregister_device(&udev->cnic_uinfo);
  659. if (udev->l2_buf) {
  660. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  661. udev->l2_buf, udev->l2_buf_map);
  662. udev->l2_buf = NULL;
  663. }
  664. if (udev->l2_ring) {
  665. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  666. udev->l2_ring, udev->l2_ring_map);
  667. udev->l2_ring = NULL;
  668. }
  669. pci_dev_put(udev->pdev);
  670. kfree(udev);
  671. }
  672. static void cnic_free_uio(struct cnic_uio_dev *udev)
  673. {
  674. if (!udev)
  675. return;
  676. write_lock(&cnic_dev_lock);
  677. list_del_init(&udev->list);
  678. write_unlock(&cnic_dev_lock);
  679. __cnic_free_uio(udev);
  680. }
  681. static void cnic_free_resc(struct cnic_dev *dev)
  682. {
  683. struct cnic_local *cp = dev->cnic_priv;
  684. struct cnic_uio_dev *udev = cp->udev;
  685. if (udev) {
  686. udev->dev = NULL;
  687. cp->udev = NULL;
  688. }
  689. cnic_free_context(dev);
  690. kfree(cp->ctx_arr);
  691. cp->ctx_arr = NULL;
  692. cp->ctx_blks = 0;
  693. cnic_free_dma(dev, &cp->gbl_buf_info);
  694. cnic_free_dma(dev, &cp->conn_buf_info);
  695. cnic_free_dma(dev, &cp->kwq_info);
  696. cnic_free_dma(dev, &cp->kwq_16_data_info);
  697. cnic_free_dma(dev, &cp->kcq2.dma);
  698. cnic_free_dma(dev, &cp->kcq1.dma);
  699. kfree(cp->iscsi_tbl);
  700. cp->iscsi_tbl = NULL;
  701. kfree(cp->ctx_tbl);
  702. cp->ctx_tbl = NULL;
  703. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  704. cnic_free_id_tbl(&cp->cid_tbl);
  705. }
  706. static int cnic_alloc_context(struct cnic_dev *dev)
  707. {
  708. struct cnic_local *cp = dev->cnic_priv;
  709. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  710. int i, k, arr_size;
  711. cp->ctx_blk_size = BCM_PAGE_SIZE;
  712. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  713. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  714. sizeof(struct cnic_ctx);
  715. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  716. if (cp->ctx_arr == NULL)
  717. return -ENOMEM;
  718. k = 0;
  719. for (i = 0; i < 2; i++) {
  720. u32 j, reg, off, lo, hi;
  721. if (i == 0)
  722. off = BNX2_PG_CTX_MAP;
  723. else
  724. off = BNX2_ISCSI_CTX_MAP;
  725. reg = cnic_reg_rd_ind(dev, off);
  726. lo = reg >> 16;
  727. hi = reg & 0xffff;
  728. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  729. cp->ctx_arr[k].cid = j;
  730. }
  731. cp->ctx_blks = k;
  732. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  733. cp->ctx_blks = 0;
  734. return -ENOMEM;
  735. }
  736. for (i = 0; i < cp->ctx_blks; i++) {
  737. cp->ctx_arr[i].ctx =
  738. dma_alloc_coherent(&dev->pcidev->dev,
  739. BCM_PAGE_SIZE,
  740. &cp->ctx_arr[i].mapping,
  741. GFP_KERNEL);
  742. if (cp->ctx_arr[i].ctx == NULL)
  743. return -ENOMEM;
  744. }
  745. }
  746. return 0;
  747. }
  748. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  749. {
  750. int err, i, is_bnx2 = 0;
  751. struct kcqe **kcq;
  752. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  753. is_bnx2 = 1;
  754. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  755. if (err)
  756. return err;
  757. kcq = (struct kcqe **) info->dma.pg_arr;
  758. info->kcq = kcq;
  759. if (is_bnx2)
  760. return 0;
  761. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  762. struct bnx2x_bd_chain_next *next =
  763. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  764. int j = i + 1;
  765. if (j >= KCQ_PAGE_CNT)
  766. j = 0;
  767. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  768. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  769. }
  770. return 0;
  771. }
  772. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  773. {
  774. struct cnic_local *cp = dev->cnic_priv;
  775. struct cnic_uio_dev *udev;
  776. read_lock(&cnic_dev_lock);
  777. list_for_each_entry(udev, &cnic_udev_list, list) {
  778. if (udev->pdev == dev->pcidev) {
  779. udev->dev = dev;
  780. cp->udev = udev;
  781. read_unlock(&cnic_dev_lock);
  782. return 0;
  783. }
  784. }
  785. read_unlock(&cnic_dev_lock);
  786. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  787. if (!udev)
  788. return -ENOMEM;
  789. udev->uio_dev = -1;
  790. udev->dev = dev;
  791. udev->pdev = dev->pcidev;
  792. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  793. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  794. &udev->l2_ring_map,
  795. GFP_KERNEL | __GFP_COMP);
  796. if (!udev->l2_ring)
  797. goto err_udev;
  798. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  799. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  800. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  801. &udev->l2_buf_map,
  802. GFP_KERNEL | __GFP_COMP);
  803. if (!udev->l2_buf)
  804. goto err_dma;
  805. write_lock(&cnic_dev_lock);
  806. list_add(&udev->list, &cnic_udev_list);
  807. write_unlock(&cnic_dev_lock);
  808. pci_dev_get(udev->pdev);
  809. cp->udev = udev;
  810. return 0;
  811. err_dma:
  812. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  813. udev->l2_ring, udev->l2_ring_map);
  814. err_udev:
  815. kfree(udev);
  816. return -ENOMEM;
  817. }
  818. static int cnic_init_uio(struct cnic_dev *dev)
  819. {
  820. struct cnic_local *cp = dev->cnic_priv;
  821. struct cnic_uio_dev *udev = cp->udev;
  822. struct uio_info *uinfo;
  823. int ret = 0;
  824. if (!udev)
  825. return -ENOMEM;
  826. uinfo = &udev->cnic_uinfo;
  827. uinfo->mem[0].addr = dev->netdev->base_addr;
  828. uinfo->mem[0].internal_addr = dev->regview;
  829. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  830. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  831. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  832. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  833. PAGE_MASK;
  834. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  835. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  836. else
  837. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  838. uinfo->name = "bnx2_cnic";
  839. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  840. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  841. PAGE_MASK;
  842. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  843. uinfo->name = "bnx2x_cnic";
  844. }
  845. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  846. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  847. uinfo->mem[2].size = udev->l2_ring_size;
  848. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  849. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  850. uinfo->mem[3].size = udev->l2_buf_size;
  851. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  852. uinfo->version = CNIC_MODULE_VERSION;
  853. uinfo->irq = UIO_IRQ_CUSTOM;
  854. uinfo->open = cnic_uio_open;
  855. uinfo->release = cnic_uio_close;
  856. if (udev->uio_dev == -1) {
  857. if (!uinfo->priv) {
  858. uinfo->priv = udev;
  859. ret = uio_register_device(&udev->pdev->dev, uinfo);
  860. }
  861. } else {
  862. cnic_init_rings(dev);
  863. }
  864. return ret;
  865. }
  866. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  867. {
  868. struct cnic_local *cp = dev->cnic_priv;
  869. int ret;
  870. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  871. if (ret)
  872. goto error;
  873. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  874. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  875. if (ret)
  876. goto error;
  877. ret = cnic_alloc_context(dev);
  878. if (ret)
  879. goto error;
  880. ret = cnic_alloc_uio_rings(dev, 2);
  881. if (ret)
  882. goto error;
  883. ret = cnic_init_uio(dev);
  884. if (ret)
  885. goto error;
  886. return 0;
  887. error:
  888. cnic_free_resc(dev);
  889. return ret;
  890. }
  891. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  892. {
  893. struct cnic_local *cp = dev->cnic_priv;
  894. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  895. int total_mem, blks, i;
  896. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  897. blks = total_mem / ctx_blk_size;
  898. if (total_mem % ctx_blk_size)
  899. blks++;
  900. if (blks > cp->ethdev->ctx_tbl_len)
  901. return -ENOMEM;
  902. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  903. if (cp->ctx_arr == NULL)
  904. return -ENOMEM;
  905. cp->ctx_blks = blks;
  906. cp->ctx_blk_size = ctx_blk_size;
  907. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  908. cp->ctx_align = 0;
  909. else
  910. cp->ctx_align = ctx_blk_size;
  911. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  912. for (i = 0; i < blks; i++) {
  913. cp->ctx_arr[i].ctx =
  914. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  915. &cp->ctx_arr[i].mapping,
  916. GFP_KERNEL);
  917. if (cp->ctx_arr[i].ctx == NULL)
  918. return -ENOMEM;
  919. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  920. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  921. cnic_free_context(dev);
  922. cp->ctx_blk_size += cp->ctx_align;
  923. i = -1;
  924. continue;
  925. }
  926. }
  927. }
  928. return 0;
  929. }
  930. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  931. {
  932. struct cnic_local *cp = dev->cnic_priv;
  933. struct cnic_eth_dev *ethdev = cp->ethdev;
  934. u32 start_cid = ethdev->starting_cid;
  935. int i, j, n, ret, pages;
  936. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  937. cp->iro_arr = ethdev->iro_arr;
  938. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  939. cp->iscsi_start_cid = start_cid;
  940. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  941. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  942. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  943. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  944. if (!cp->fcoe_init_cid)
  945. cp->fcoe_init_cid = 0x10;
  946. }
  947. if (start_cid < BNX2X_ISCSI_START_CID) {
  948. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  949. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  950. cp->fcoe_start_cid += delta;
  951. cp->max_cid_space += delta;
  952. }
  953. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  954. GFP_KERNEL);
  955. if (!cp->iscsi_tbl)
  956. goto error;
  957. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  958. cp->max_cid_space, GFP_KERNEL);
  959. if (!cp->ctx_tbl)
  960. goto error;
  961. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  962. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  963. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  964. }
  965. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  966. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  967. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  968. PAGE_SIZE;
  969. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  970. if (ret)
  971. return -ENOMEM;
  972. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  973. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  974. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  975. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  976. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  977. off;
  978. if ((i % n) == (n - 1))
  979. j++;
  980. }
  981. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  982. if (ret)
  983. goto error;
  984. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  985. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  986. if (ret)
  987. goto error;
  988. }
  989. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  990. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  991. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  992. if (ret)
  993. goto error;
  994. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  995. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  996. if (ret)
  997. goto error;
  998. ret = cnic_alloc_bnx2x_context(dev);
  999. if (ret)
  1000. goto error;
  1001. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1002. cp->l2_rx_ring_size = 15;
  1003. ret = cnic_alloc_uio_rings(dev, 4);
  1004. if (ret)
  1005. goto error;
  1006. ret = cnic_init_uio(dev);
  1007. if (ret)
  1008. goto error;
  1009. return 0;
  1010. error:
  1011. cnic_free_resc(dev);
  1012. return -ENOMEM;
  1013. }
  1014. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1015. {
  1016. return cp->max_kwq_idx -
  1017. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1018. }
  1019. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1020. u32 num_wqes)
  1021. {
  1022. struct cnic_local *cp = dev->cnic_priv;
  1023. struct kwqe *prod_qe;
  1024. u16 prod, sw_prod, i;
  1025. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1026. return -EAGAIN; /* bnx2 is down */
  1027. spin_lock_bh(&cp->cnic_ulp_lock);
  1028. if (num_wqes > cnic_kwq_avail(cp) &&
  1029. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1030. spin_unlock_bh(&cp->cnic_ulp_lock);
  1031. return -EAGAIN;
  1032. }
  1033. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1034. prod = cp->kwq_prod_idx;
  1035. sw_prod = prod & MAX_KWQ_IDX;
  1036. for (i = 0; i < num_wqes; i++) {
  1037. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1038. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1039. prod++;
  1040. sw_prod = prod & MAX_KWQ_IDX;
  1041. }
  1042. cp->kwq_prod_idx = prod;
  1043. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1044. spin_unlock_bh(&cp->cnic_ulp_lock);
  1045. return 0;
  1046. }
  1047. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1048. union l5cm_specific_data *l5_data)
  1049. {
  1050. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1051. dma_addr_t map;
  1052. map = ctx->kwqe_data_mapping;
  1053. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1054. l5_data->phy_address.hi = (u64) map >> 32;
  1055. return ctx->kwqe_data;
  1056. }
  1057. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1058. u32 type, union l5cm_specific_data *l5_data)
  1059. {
  1060. struct cnic_local *cp = dev->cnic_priv;
  1061. struct l5cm_spe kwqe;
  1062. struct kwqe_16 *kwq[1];
  1063. u16 type_16;
  1064. int ret;
  1065. kwqe.hdr.conn_and_cmd_data =
  1066. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1067. BNX2X_HW_CID(cp, cid)));
  1068. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1069. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1070. SPE_HDR_FUNCTION_ID;
  1071. kwqe.hdr.type = cpu_to_le16(type_16);
  1072. kwqe.hdr.reserved1 = 0;
  1073. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1074. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1075. kwq[0] = (struct kwqe_16 *) &kwqe;
  1076. spin_lock_bh(&cp->cnic_ulp_lock);
  1077. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1078. spin_unlock_bh(&cp->cnic_ulp_lock);
  1079. if (ret == 1)
  1080. return 0;
  1081. return -EBUSY;
  1082. }
  1083. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1084. struct kcqe *cqes[], u32 num_cqes)
  1085. {
  1086. struct cnic_local *cp = dev->cnic_priv;
  1087. struct cnic_ulp_ops *ulp_ops;
  1088. rcu_read_lock();
  1089. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1090. if (likely(ulp_ops)) {
  1091. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1092. cqes, num_cqes);
  1093. }
  1094. rcu_read_unlock();
  1095. }
  1096. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1097. {
  1098. struct cnic_local *cp = dev->cnic_priv;
  1099. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1100. int hq_bds, pages;
  1101. u32 pfid = cp->pfid;
  1102. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1103. cp->num_ccells = req1->num_ccells_per_conn;
  1104. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1105. cp->num_iscsi_tasks;
  1106. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1107. BNX2X_ISCSI_R2TQE_SIZE;
  1108. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1109. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1110. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1111. cp->num_cqs = req1->num_cqs;
  1112. if (!dev->max_iscsi_conn)
  1113. return 0;
  1114. /* init Tstorm RAM */
  1115. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1116. req1->rq_num_wqes);
  1117. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1118. PAGE_SIZE);
  1119. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1120. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1121. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1122. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1123. req1->num_tasks_per_conn);
  1124. /* init Ustorm RAM */
  1125. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1126. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1127. req1->rq_buffer_size);
  1128. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1129. PAGE_SIZE);
  1130. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1131. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1132. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1133. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1134. req1->num_tasks_per_conn);
  1135. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1136. req1->rq_num_wqes);
  1137. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1138. req1->cq_num_wqes);
  1139. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1140. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1141. /* init Xstorm RAM */
  1142. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1143. PAGE_SIZE);
  1144. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1145. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1146. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1147. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1148. req1->num_tasks_per_conn);
  1149. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1150. hq_bds);
  1151. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1152. req1->num_tasks_per_conn);
  1153. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1154. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1155. /* init Cstorm RAM */
  1156. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1157. PAGE_SIZE);
  1158. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1159. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1160. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1161. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1162. req1->num_tasks_per_conn);
  1163. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1164. req1->cq_num_wqes);
  1165. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1166. hq_bds);
  1167. return 0;
  1168. }
  1169. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1170. {
  1171. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1172. struct cnic_local *cp = dev->cnic_priv;
  1173. u32 pfid = cp->pfid;
  1174. struct iscsi_kcqe kcqe;
  1175. struct kcqe *cqes[1];
  1176. memset(&kcqe, 0, sizeof(kcqe));
  1177. if (!dev->max_iscsi_conn) {
  1178. kcqe.completion_status =
  1179. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1180. goto done;
  1181. }
  1182. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1183. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1184. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1185. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1186. req2->error_bit_map[1]);
  1187. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1188. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1189. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1190. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1191. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1192. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1193. req2->error_bit_map[1]);
  1194. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1195. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1196. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1197. done:
  1198. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1199. cqes[0] = (struct kcqe *) &kcqe;
  1200. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1201. return 0;
  1202. }
  1203. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1204. {
  1205. struct cnic_local *cp = dev->cnic_priv;
  1206. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1207. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1208. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1209. cnic_free_dma(dev, &iscsi->hq_info);
  1210. cnic_free_dma(dev, &iscsi->r2tq_info);
  1211. cnic_free_dma(dev, &iscsi->task_array_info);
  1212. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1213. } else {
  1214. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1215. }
  1216. ctx->cid = 0;
  1217. }
  1218. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1219. {
  1220. u32 cid;
  1221. int ret, pages;
  1222. struct cnic_local *cp = dev->cnic_priv;
  1223. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1224. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1225. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1226. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1227. if (cid == -1) {
  1228. ret = -ENOMEM;
  1229. goto error;
  1230. }
  1231. ctx->cid = cid;
  1232. return 0;
  1233. }
  1234. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1235. if (cid == -1) {
  1236. ret = -ENOMEM;
  1237. goto error;
  1238. }
  1239. ctx->cid = cid;
  1240. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1241. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1242. if (ret)
  1243. goto error;
  1244. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1245. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1246. if (ret)
  1247. goto error;
  1248. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1249. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1250. if (ret)
  1251. goto error;
  1252. return 0;
  1253. error:
  1254. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1255. return ret;
  1256. }
  1257. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1258. struct regpair *ctx_addr)
  1259. {
  1260. struct cnic_local *cp = dev->cnic_priv;
  1261. struct cnic_eth_dev *ethdev = cp->ethdev;
  1262. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1263. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1264. unsigned long align_off = 0;
  1265. dma_addr_t ctx_map;
  1266. void *ctx;
  1267. if (cp->ctx_align) {
  1268. unsigned long mask = cp->ctx_align - 1;
  1269. if (cp->ctx_arr[blk].mapping & mask)
  1270. align_off = cp->ctx_align -
  1271. (cp->ctx_arr[blk].mapping & mask);
  1272. }
  1273. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1274. (off * BNX2X_CONTEXT_MEM_SIZE);
  1275. ctx = cp->ctx_arr[blk].ctx + align_off +
  1276. (off * BNX2X_CONTEXT_MEM_SIZE);
  1277. if (init)
  1278. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1279. ctx_addr->lo = ctx_map & 0xffffffff;
  1280. ctx_addr->hi = (u64) ctx_map >> 32;
  1281. return ctx;
  1282. }
  1283. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1284. u32 num)
  1285. {
  1286. struct cnic_local *cp = dev->cnic_priv;
  1287. struct iscsi_kwqe_conn_offload1 *req1 =
  1288. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1289. struct iscsi_kwqe_conn_offload2 *req2 =
  1290. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1291. struct iscsi_kwqe_conn_offload3 *req3;
  1292. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1293. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1294. u32 cid = ctx->cid;
  1295. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1296. struct iscsi_context *ictx;
  1297. struct regpair context_addr;
  1298. int i, j, n = 2, n_max;
  1299. ctx->ctx_flags = 0;
  1300. if (!req2->num_additional_wqes)
  1301. return -EINVAL;
  1302. n_max = req2->num_additional_wqes + 2;
  1303. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1304. if (ictx == NULL)
  1305. return -ENOMEM;
  1306. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1307. ictx->xstorm_ag_context.hq_prod = 1;
  1308. ictx->xstorm_st_context.iscsi.first_burst_length =
  1309. ISCSI_DEF_FIRST_BURST_LEN;
  1310. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1311. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1312. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1313. req1->sq_page_table_addr_lo;
  1314. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1315. req1->sq_page_table_addr_hi;
  1316. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1317. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1318. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1319. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1320. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1321. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1322. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1323. iscsi->hq_info.pgtbl[0];
  1324. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1325. iscsi->hq_info.pgtbl[1];
  1326. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1327. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1328. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1329. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1330. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1331. iscsi->r2tq_info.pgtbl[0];
  1332. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1333. iscsi->r2tq_info.pgtbl[1];
  1334. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1335. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1336. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1337. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1338. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1339. BNX2X_ISCSI_PBL_NOT_CACHED;
  1340. ictx->xstorm_st_context.iscsi.flags.flags |=
  1341. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1342. ictx->xstorm_st_context.iscsi.flags.flags |=
  1343. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1344. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1345. /* TSTORM requires the base address of RQ DB & not PTE */
  1346. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1347. req2->rq_page_table_addr_lo & PAGE_MASK;
  1348. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1349. req2->rq_page_table_addr_hi;
  1350. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1351. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1352. ictx->tstorm_st_context.tcp.flags2 |=
  1353. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1354. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1355. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1356. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1357. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1358. req2->rq_page_table_addr_lo;
  1359. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1360. req2->rq_page_table_addr_hi;
  1361. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1362. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1363. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1364. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1365. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1366. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1367. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1368. iscsi->r2tq_info.pgtbl[0];
  1369. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1370. iscsi->r2tq_info.pgtbl[1];
  1371. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1372. req1->cq_page_table_addr_lo;
  1373. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1374. req1->cq_page_table_addr_hi;
  1375. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1376. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1377. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1378. ictx->ustorm_st_context.task_pbe_cache_index =
  1379. BNX2X_ISCSI_PBL_NOT_CACHED;
  1380. ictx->ustorm_st_context.task_pdu_cache_index =
  1381. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1382. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1383. if (j == 3) {
  1384. if (n >= n_max)
  1385. break;
  1386. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1387. j = 0;
  1388. }
  1389. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1390. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1391. req3->qp_first_pte[j].hi;
  1392. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1393. req3->qp_first_pte[j].lo;
  1394. }
  1395. ictx->ustorm_st_context.task_pbl_base.lo =
  1396. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1397. ictx->ustorm_st_context.task_pbl_base.hi =
  1398. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1399. ictx->ustorm_st_context.tce_phy_addr.lo =
  1400. iscsi->task_array_info.pgtbl[0];
  1401. ictx->ustorm_st_context.tce_phy_addr.hi =
  1402. iscsi->task_array_info.pgtbl[1];
  1403. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1404. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1405. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1406. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1407. ISCSI_DEF_MAX_BURST_LEN;
  1408. ictx->ustorm_st_context.negotiated_rx |=
  1409. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1410. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1411. ictx->cstorm_st_context.hq_pbl_base.lo =
  1412. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1413. ictx->cstorm_st_context.hq_pbl_base.hi =
  1414. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1415. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1416. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1417. ictx->cstorm_st_context.task_pbl_base.lo =
  1418. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1419. ictx->cstorm_st_context.task_pbl_base.hi =
  1420. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1421. /* CSTORM and USTORM initialization is different, CSTORM requires
  1422. * CQ DB base & not PTE addr */
  1423. ictx->cstorm_st_context.cq_db_base.lo =
  1424. req1->cq_page_table_addr_lo & PAGE_MASK;
  1425. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1426. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1427. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1428. for (i = 0; i < cp->num_cqs; i++) {
  1429. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1430. ISCSI_INITIAL_SN;
  1431. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1432. ISCSI_INITIAL_SN;
  1433. }
  1434. ictx->xstorm_ag_context.cdu_reserved =
  1435. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1436. ISCSI_CONNECTION_TYPE);
  1437. ictx->ustorm_ag_context.cdu_usage =
  1438. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1439. ISCSI_CONNECTION_TYPE);
  1440. return 0;
  1441. }
  1442. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1443. u32 num, int *work)
  1444. {
  1445. struct iscsi_kwqe_conn_offload1 *req1;
  1446. struct iscsi_kwqe_conn_offload2 *req2;
  1447. struct cnic_local *cp = dev->cnic_priv;
  1448. struct cnic_context *ctx;
  1449. struct iscsi_kcqe kcqe;
  1450. struct kcqe *cqes[1];
  1451. u32 l5_cid;
  1452. int ret = 0;
  1453. if (num < 2) {
  1454. *work = num;
  1455. return -EINVAL;
  1456. }
  1457. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1458. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1459. if ((num - 2) < req2->num_additional_wqes) {
  1460. *work = num;
  1461. return -EINVAL;
  1462. }
  1463. *work = 2 + req2->num_additional_wqes;
  1464. l5_cid = req1->iscsi_conn_id;
  1465. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1466. return -EINVAL;
  1467. memset(&kcqe, 0, sizeof(kcqe));
  1468. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1469. kcqe.iscsi_conn_id = l5_cid;
  1470. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1471. ctx = &cp->ctx_tbl[l5_cid];
  1472. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1473. kcqe.completion_status =
  1474. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1475. goto done;
  1476. }
  1477. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1478. atomic_dec(&cp->iscsi_conn);
  1479. goto done;
  1480. }
  1481. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1482. if (ret) {
  1483. atomic_dec(&cp->iscsi_conn);
  1484. ret = 0;
  1485. goto done;
  1486. }
  1487. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1488. if (ret < 0) {
  1489. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1490. atomic_dec(&cp->iscsi_conn);
  1491. goto done;
  1492. }
  1493. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1494. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1495. done:
  1496. cqes[0] = (struct kcqe *) &kcqe;
  1497. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1498. return ret;
  1499. }
  1500. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1501. {
  1502. struct cnic_local *cp = dev->cnic_priv;
  1503. struct iscsi_kwqe_conn_update *req =
  1504. (struct iscsi_kwqe_conn_update *) kwqe;
  1505. void *data;
  1506. union l5cm_specific_data l5_data;
  1507. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1508. int ret;
  1509. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1510. return -EINVAL;
  1511. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1512. if (!data)
  1513. return -ENOMEM;
  1514. memcpy(data, kwqe, sizeof(struct kwqe));
  1515. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1516. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1517. return ret;
  1518. }
  1519. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1520. {
  1521. struct cnic_local *cp = dev->cnic_priv;
  1522. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1523. union l5cm_specific_data l5_data;
  1524. int ret;
  1525. u32 hw_cid;
  1526. init_waitqueue_head(&ctx->waitq);
  1527. ctx->wait_cond = 0;
  1528. memset(&l5_data, 0, sizeof(l5_data));
  1529. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1530. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1531. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1532. if (ret == 0)
  1533. wait_event(ctx->waitq, ctx->wait_cond);
  1534. return ret;
  1535. }
  1536. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1537. {
  1538. struct cnic_local *cp = dev->cnic_priv;
  1539. struct iscsi_kwqe_conn_destroy *req =
  1540. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1541. u32 l5_cid = req->reserved0;
  1542. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1543. int ret = 0;
  1544. struct iscsi_kcqe kcqe;
  1545. struct kcqe *cqes[1];
  1546. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1547. goto skip_cfc_delete;
  1548. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1549. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1550. if (delta > (2 * HZ))
  1551. delta = 0;
  1552. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1553. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1554. goto destroy_reply;
  1555. }
  1556. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1557. skip_cfc_delete:
  1558. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1559. atomic_dec(&cp->iscsi_conn);
  1560. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1561. destroy_reply:
  1562. memset(&kcqe, 0, sizeof(kcqe));
  1563. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1564. kcqe.iscsi_conn_id = l5_cid;
  1565. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1566. kcqe.iscsi_conn_context_id = req->context_id;
  1567. cqes[0] = (struct kcqe *) &kcqe;
  1568. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1569. return ret;
  1570. }
  1571. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1572. struct l4_kwq_connect_req1 *kwqe1,
  1573. struct l4_kwq_connect_req3 *kwqe3,
  1574. struct l5cm_active_conn_buffer *conn_buf)
  1575. {
  1576. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1577. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1578. &conn_buf->xstorm_conn_buffer;
  1579. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1580. &conn_buf->tstorm_conn_buffer;
  1581. struct regpair context_addr;
  1582. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1583. struct in6_addr src_ip, dst_ip;
  1584. int i;
  1585. u32 *addrp;
  1586. addrp = (u32 *) &conn_addr->local_ip_addr;
  1587. for (i = 0; i < 4; i++, addrp++)
  1588. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1589. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1590. for (i = 0; i < 4; i++, addrp++)
  1591. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1592. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1593. xstorm_buf->context_addr.hi = context_addr.hi;
  1594. xstorm_buf->context_addr.lo = context_addr.lo;
  1595. xstorm_buf->mss = 0xffff;
  1596. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1597. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1598. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1599. xstorm_buf->pseudo_header_checksum =
  1600. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1601. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1602. tstorm_buf->params |=
  1603. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1604. if (kwqe3->ka_timeout) {
  1605. tstorm_buf->ka_enable = 1;
  1606. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1607. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1608. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1609. }
  1610. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1611. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1612. tstorm_buf->max_rt_time = 0xffffffff;
  1613. }
  1614. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1615. {
  1616. struct cnic_local *cp = dev->cnic_priv;
  1617. u32 pfid = cp->pfid;
  1618. u8 *mac = dev->mac_addr;
  1619. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1620. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1621. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1622. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1623. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1624. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1625. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1626. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1627. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1628. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1629. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1630. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1631. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1632. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1633. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1634. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1635. mac[4]);
  1636. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1637. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1638. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1639. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1640. mac[2]);
  1641. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1642. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1643. mac[1]);
  1644. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1645. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1646. mac[0]);
  1647. }
  1648. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1649. {
  1650. struct cnic_local *cp = dev->cnic_priv;
  1651. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1652. u16 tstorm_flags = 0;
  1653. if (tcp_ts) {
  1654. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1655. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1656. }
  1657. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1658. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1659. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1660. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1661. }
  1662. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1663. u32 num, int *work)
  1664. {
  1665. struct cnic_local *cp = dev->cnic_priv;
  1666. struct l4_kwq_connect_req1 *kwqe1 =
  1667. (struct l4_kwq_connect_req1 *) wqes[0];
  1668. struct l4_kwq_connect_req3 *kwqe3;
  1669. struct l5cm_active_conn_buffer *conn_buf;
  1670. struct l5cm_conn_addr_params *conn_addr;
  1671. union l5cm_specific_data l5_data;
  1672. u32 l5_cid = kwqe1->pg_cid;
  1673. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1674. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1675. int ret;
  1676. if (num < 2) {
  1677. *work = num;
  1678. return -EINVAL;
  1679. }
  1680. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1681. *work = 3;
  1682. else
  1683. *work = 2;
  1684. if (num < *work) {
  1685. *work = num;
  1686. return -EINVAL;
  1687. }
  1688. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1689. netdev_err(dev->netdev, "conn_buf size too big\n");
  1690. return -ENOMEM;
  1691. }
  1692. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1693. if (!conn_buf)
  1694. return -ENOMEM;
  1695. memset(conn_buf, 0, sizeof(*conn_buf));
  1696. conn_addr = &conn_buf->conn_addr_buf;
  1697. conn_addr->remote_addr_0 = csk->ha[0];
  1698. conn_addr->remote_addr_1 = csk->ha[1];
  1699. conn_addr->remote_addr_2 = csk->ha[2];
  1700. conn_addr->remote_addr_3 = csk->ha[3];
  1701. conn_addr->remote_addr_4 = csk->ha[4];
  1702. conn_addr->remote_addr_5 = csk->ha[5];
  1703. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1704. struct l4_kwq_connect_req2 *kwqe2 =
  1705. (struct l4_kwq_connect_req2 *) wqes[1];
  1706. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1707. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1708. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1709. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1710. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1711. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1712. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1713. }
  1714. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1715. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1716. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1717. conn_addr->local_tcp_port = kwqe1->src_port;
  1718. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1719. conn_addr->pmtu = kwqe3->pmtu;
  1720. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1721. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1722. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1723. cnic_bnx2x_set_tcp_timestamp(dev,
  1724. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1725. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1726. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1727. if (!ret)
  1728. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1729. return ret;
  1730. }
  1731. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1732. {
  1733. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1734. union l5cm_specific_data l5_data;
  1735. int ret;
  1736. memset(&l5_data, 0, sizeof(l5_data));
  1737. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1738. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1739. return ret;
  1740. }
  1741. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1742. {
  1743. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1744. union l5cm_specific_data l5_data;
  1745. int ret;
  1746. memset(&l5_data, 0, sizeof(l5_data));
  1747. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1748. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1749. return ret;
  1750. }
  1751. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1752. {
  1753. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1754. struct l4_kcq kcqe;
  1755. struct kcqe *cqes[1];
  1756. memset(&kcqe, 0, sizeof(kcqe));
  1757. kcqe.pg_host_opaque = req->host_opaque;
  1758. kcqe.pg_cid = req->host_opaque;
  1759. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1760. cqes[0] = (struct kcqe *) &kcqe;
  1761. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1762. return 0;
  1763. }
  1764. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1765. {
  1766. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1767. struct l4_kcq kcqe;
  1768. struct kcqe *cqes[1];
  1769. memset(&kcqe, 0, sizeof(kcqe));
  1770. kcqe.pg_host_opaque = req->pg_host_opaque;
  1771. kcqe.pg_cid = req->pg_cid;
  1772. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1773. cqes[0] = (struct kcqe *) &kcqe;
  1774. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1775. return 0;
  1776. }
  1777. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1778. {
  1779. struct fcoe_kwqe_stat *req;
  1780. struct fcoe_stat_ramrod_params *fcoe_stat;
  1781. union l5cm_specific_data l5_data;
  1782. struct cnic_local *cp = dev->cnic_priv;
  1783. int ret;
  1784. u32 cid;
  1785. req = (struct fcoe_kwqe_stat *) kwqe;
  1786. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1787. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1788. if (!fcoe_stat)
  1789. return -ENOMEM;
  1790. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1791. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1792. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1793. FCOE_CONNECTION_TYPE, &l5_data);
  1794. return ret;
  1795. }
  1796. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1797. u32 num, int *work)
  1798. {
  1799. int ret;
  1800. struct cnic_local *cp = dev->cnic_priv;
  1801. u32 cid;
  1802. struct fcoe_init_ramrod_params *fcoe_init;
  1803. struct fcoe_kwqe_init1 *req1;
  1804. struct fcoe_kwqe_init2 *req2;
  1805. struct fcoe_kwqe_init3 *req3;
  1806. union l5cm_specific_data l5_data;
  1807. if (num < 3) {
  1808. *work = num;
  1809. return -EINVAL;
  1810. }
  1811. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1812. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1813. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1814. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1815. *work = 1;
  1816. return -EINVAL;
  1817. }
  1818. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1819. *work = 2;
  1820. return -EINVAL;
  1821. }
  1822. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1823. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1824. return -ENOMEM;
  1825. }
  1826. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1827. if (!fcoe_init)
  1828. return -ENOMEM;
  1829. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1830. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1831. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1832. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1833. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1834. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1835. fcoe_init->eq_next_page_addr.lo =
  1836. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1837. fcoe_init->eq_next_page_addr.hi =
  1838. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1839. fcoe_init->sb_num = cp->status_blk_num;
  1840. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1841. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1842. cp->kcq2.sw_prod_idx = 0;
  1843. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1844. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1845. FCOE_CONNECTION_TYPE, &l5_data);
  1846. *work = 3;
  1847. return ret;
  1848. }
  1849. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1850. u32 num, int *work)
  1851. {
  1852. int ret = 0;
  1853. u32 cid = -1, l5_cid;
  1854. struct cnic_local *cp = dev->cnic_priv;
  1855. struct fcoe_kwqe_conn_offload1 *req1;
  1856. struct fcoe_kwqe_conn_offload2 *req2;
  1857. struct fcoe_kwqe_conn_offload3 *req3;
  1858. struct fcoe_kwqe_conn_offload4 *req4;
  1859. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1860. struct cnic_context *ctx;
  1861. struct fcoe_context *fctx;
  1862. struct regpair ctx_addr;
  1863. union l5cm_specific_data l5_data;
  1864. struct fcoe_kcqe kcqe;
  1865. struct kcqe *cqes[1];
  1866. if (num < 4) {
  1867. *work = num;
  1868. return -EINVAL;
  1869. }
  1870. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1871. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1872. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1873. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1874. *work = 4;
  1875. l5_cid = req1->fcoe_conn_id;
  1876. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1877. goto err_reply;
  1878. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1879. ctx = &cp->ctx_tbl[l5_cid];
  1880. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1881. goto err_reply;
  1882. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1883. if (ret) {
  1884. ret = 0;
  1885. goto err_reply;
  1886. }
  1887. cid = ctx->cid;
  1888. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1889. if (fctx) {
  1890. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1891. u32 val;
  1892. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1893. FCOE_CONNECTION_TYPE);
  1894. fctx->xstorm_ag_context.cdu_reserved = val;
  1895. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1896. FCOE_CONNECTION_TYPE);
  1897. fctx->ustorm_ag_context.cdu_usage = val;
  1898. }
  1899. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1900. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1901. goto err_reply;
  1902. }
  1903. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1904. if (!fcoe_offload)
  1905. goto err_reply;
  1906. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1907. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1908. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1909. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1910. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1911. cid = BNX2X_HW_CID(cp, cid);
  1912. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1913. FCOE_CONNECTION_TYPE, &l5_data);
  1914. if (!ret)
  1915. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1916. return ret;
  1917. err_reply:
  1918. if (cid != -1)
  1919. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1920. memset(&kcqe, 0, sizeof(kcqe));
  1921. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1922. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1923. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1924. cqes[0] = (struct kcqe *) &kcqe;
  1925. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1926. return ret;
  1927. }
  1928. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1929. {
  1930. struct fcoe_kwqe_conn_enable_disable *req;
  1931. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1932. union l5cm_specific_data l5_data;
  1933. int ret;
  1934. u32 cid, l5_cid;
  1935. struct cnic_local *cp = dev->cnic_priv;
  1936. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1937. cid = req->context_id;
  1938. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1939. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1940. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1941. return -ENOMEM;
  1942. }
  1943. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1944. if (!fcoe_enable)
  1945. return -ENOMEM;
  1946. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1947. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1948. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1949. FCOE_CONNECTION_TYPE, &l5_data);
  1950. return ret;
  1951. }
  1952. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1953. {
  1954. struct fcoe_kwqe_conn_enable_disable *req;
  1955. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1956. union l5cm_specific_data l5_data;
  1957. int ret;
  1958. u32 cid, l5_cid;
  1959. struct cnic_local *cp = dev->cnic_priv;
  1960. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1961. cid = req->context_id;
  1962. l5_cid = req->conn_id;
  1963. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1964. return -EINVAL;
  1965. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1966. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1967. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1968. return -ENOMEM;
  1969. }
  1970. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1971. if (!fcoe_disable)
  1972. return -ENOMEM;
  1973. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1974. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  1975. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  1976. FCOE_CONNECTION_TYPE, &l5_data);
  1977. return ret;
  1978. }
  1979. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1980. {
  1981. struct fcoe_kwqe_conn_destroy *req;
  1982. union l5cm_specific_data l5_data;
  1983. int ret;
  1984. u32 cid, l5_cid;
  1985. struct cnic_local *cp = dev->cnic_priv;
  1986. struct cnic_context *ctx;
  1987. struct fcoe_kcqe kcqe;
  1988. struct kcqe *cqes[1];
  1989. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  1990. cid = req->context_id;
  1991. l5_cid = req->conn_id;
  1992. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1993. return -EINVAL;
  1994. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1995. ctx = &cp->ctx_tbl[l5_cid];
  1996. init_waitqueue_head(&ctx->waitq);
  1997. ctx->wait_cond = 0;
  1998. memset(&l5_data, 0, sizeof(l5_data));
  1999. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2000. FCOE_CONNECTION_TYPE, &l5_data);
  2001. if (ret == 0) {
  2002. wait_event(ctx->waitq, ctx->wait_cond);
  2003. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2004. queue_delayed_work(cnic_wq, &cp->delete_task,
  2005. msecs_to_jiffies(2000));
  2006. }
  2007. memset(&kcqe, 0, sizeof(kcqe));
  2008. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2009. kcqe.fcoe_conn_id = req->conn_id;
  2010. kcqe.fcoe_conn_context_id = cid;
  2011. cqes[0] = (struct kcqe *) &kcqe;
  2012. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2013. return ret;
  2014. }
  2015. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2016. {
  2017. struct fcoe_kwqe_destroy *req;
  2018. union l5cm_specific_data l5_data;
  2019. struct cnic_local *cp = dev->cnic_priv;
  2020. int ret;
  2021. u32 cid;
  2022. req = (struct fcoe_kwqe_destroy *) kwqe;
  2023. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2024. memset(&l5_data, 0, sizeof(l5_data));
  2025. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2026. FCOE_CONNECTION_TYPE, &l5_data);
  2027. return ret;
  2028. }
  2029. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2030. struct kwqe *wqes[], u32 num_wqes)
  2031. {
  2032. int i, work, ret;
  2033. u32 opcode;
  2034. struct kwqe *kwqe;
  2035. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2036. return -EAGAIN; /* bnx2 is down */
  2037. for (i = 0; i < num_wqes; ) {
  2038. kwqe = wqes[i];
  2039. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2040. work = 1;
  2041. switch (opcode) {
  2042. case ISCSI_KWQE_OPCODE_INIT1:
  2043. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2044. break;
  2045. case ISCSI_KWQE_OPCODE_INIT2:
  2046. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2047. break;
  2048. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2049. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2050. num_wqes - i, &work);
  2051. break;
  2052. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2053. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2054. break;
  2055. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2056. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2057. break;
  2058. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2059. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2060. &work);
  2061. break;
  2062. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2063. ret = cnic_bnx2x_close(dev, kwqe);
  2064. break;
  2065. case L4_KWQE_OPCODE_VALUE_RESET:
  2066. ret = cnic_bnx2x_reset(dev, kwqe);
  2067. break;
  2068. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2069. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2070. break;
  2071. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2072. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2073. break;
  2074. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2075. ret = 0;
  2076. break;
  2077. default:
  2078. ret = 0;
  2079. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2080. opcode);
  2081. break;
  2082. }
  2083. if (ret < 0)
  2084. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2085. opcode);
  2086. i += work;
  2087. }
  2088. return 0;
  2089. }
  2090. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2091. struct kwqe *wqes[], u32 num_wqes)
  2092. {
  2093. struct cnic_local *cp = dev->cnic_priv;
  2094. int i, work, ret;
  2095. u32 opcode;
  2096. struct kwqe *kwqe;
  2097. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2098. return -EAGAIN; /* bnx2 is down */
  2099. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2100. return -EINVAL;
  2101. for (i = 0; i < num_wqes; ) {
  2102. kwqe = wqes[i];
  2103. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2104. work = 1;
  2105. switch (opcode) {
  2106. case FCOE_KWQE_OPCODE_INIT1:
  2107. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2108. num_wqes - i, &work);
  2109. break;
  2110. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2111. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2112. num_wqes - i, &work);
  2113. break;
  2114. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2115. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2116. break;
  2117. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2118. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2119. break;
  2120. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2121. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2122. break;
  2123. case FCOE_KWQE_OPCODE_DESTROY:
  2124. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2125. break;
  2126. case FCOE_KWQE_OPCODE_STAT:
  2127. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2128. break;
  2129. default:
  2130. ret = 0;
  2131. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2132. opcode);
  2133. break;
  2134. }
  2135. if (ret < 0)
  2136. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2137. opcode);
  2138. i += work;
  2139. }
  2140. return 0;
  2141. }
  2142. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2143. u32 num_wqes)
  2144. {
  2145. int ret = -EINVAL;
  2146. u32 layer_code;
  2147. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2148. return -EAGAIN; /* bnx2x is down */
  2149. if (!num_wqes)
  2150. return 0;
  2151. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2152. switch (layer_code) {
  2153. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2154. case KWQE_FLAGS_LAYER_MASK_L4:
  2155. case KWQE_FLAGS_LAYER_MASK_L2:
  2156. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2157. break;
  2158. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2159. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2160. break;
  2161. }
  2162. return ret;
  2163. }
  2164. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2165. {
  2166. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2167. return KCQE_FLAGS_LAYER_MASK_L4;
  2168. return opflag & KCQE_FLAGS_LAYER_MASK;
  2169. }
  2170. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2171. {
  2172. struct cnic_local *cp = dev->cnic_priv;
  2173. int i, j, comp = 0;
  2174. i = 0;
  2175. j = 1;
  2176. while (num_cqes) {
  2177. struct cnic_ulp_ops *ulp_ops;
  2178. int ulp_type;
  2179. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2180. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2181. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2182. comp++;
  2183. while (j < num_cqes) {
  2184. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2185. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2186. break;
  2187. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2188. comp++;
  2189. j++;
  2190. }
  2191. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2192. ulp_type = CNIC_ULP_RDMA;
  2193. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2194. ulp_type = CNIC_ULP_ISCSI;
  2195. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2196. ulp_type = CNIC_ULP_FCOE;
  2197. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2198. ulp_type = CNIC_ULP_L4;
  2199. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2200. goto end;
  2201. else {
  2202. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2203. kcqe_op_flag);
  2204. goto end;
  2205. }
  2206. rcu_read_lock();
  2207. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2208. if (likely(ulp_ops)) {
  2209. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2210. cp->completed_kcq + i, j);
  2211. }
  2212. rcu_read_unlock();
  2213. end:
  2214. num_cqes -= j;
  2215. i += j;
  2216. j = 1;
  2217. }
  2218. if (unlikely(comp))
  2219. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2220. }
  2221. static u16 cnic_bnx2_next_idx(u16 idx)
  2222. {
  2223. return idx + 1;
  2224. }
  2225. static u16 cnic_bnx2_hw_idx(u16 idx)
  2226. {
  2227. return idx;
  2228. }
  2229. static u16 cnic_bnx2x_next_idx(u16 idx)
  2230. {
  2231. idx++;
  2232. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2233. idx++;
  2234. return idx;
  2235. }
  2236. static u16 cnic_bnx2x_hw_idx(u16 idx)
  2237. {
  2238. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2239. idx++;
  2240. return idx;
  2241. }
  2242. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2243. {
  2244. struct cnic_local *cp = dev->cnic_priv;
  2245. u16 i, ri, hw_prod, last;
  2246. struct kcqe *kcqe;
  2247. int kcqe_cnt = 0, last_cnt = 0;
  2248. i = ri = last = info->sw_prod_idx;
  2249. ri &= MAX_KCQ_IDX;
  2250. hw_prod = *info->hw_prod_idx_ptr;
  2251. hw_prod = cp->hw_idx(hw_prod);
  2252. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2253. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2254. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2255. i = cp->next_idx(i);
  2256. ri = i & MAX_KCQ_IDX;
  2257. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2258. last_cnt = kcqe_cnt;
  2259. last = i;
  2260. }
  2261. }
  2262. info->sw_prod_idx = last;
  2263. return last_cnt;
  2264. }
  2265. static int cnic_l2_completion(struct cnic_local *cp)
  2266. {
  2267. u16 hw_cons, sw_cons;
  2268. struct cnic_uio_dev *udev = cp->udev;
  2269. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2270. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2271. u32 cmd;
  2272. int comp = 0;
  2273. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2274. return 0;
  2275. hw_cons = *cp->rx_cons_ptr;
  2276. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2277. hw_cons++;
  2278. sw_cons = cp->rx_cons;
  2279. while (sw_cons != hw_cons) {
  2280. u8 cqe_fp_flags;
  2281. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2282. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2283. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2284. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2285. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2286. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2287. cmd == RAMROD_CMD_ID_ETH_HALT)
  2288. comp++;
  2289. }
  2290. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2291. }
  2292. return comp;
  2293. }
  2294. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2295. {
  2296. u16 rx_cons, tx_cons;
  2297. int comp = 0;
  2298. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2299. return;
  2300. rx_cons = *cp->rx_cons_ptr;
  2301. tx_cons = *cp->tx_cons_ptr;
  2302. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2303. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2304. comp = cnic_l2_completion(cp);
  2305. cp->tx_cons = tx_cons;
  2306. cp->rx_cons = rx_cons;
  2307. if (cp->udev)
  2308. uio_event_notify(&cp->udev->cnic_uinfo);
  2309. }
  2310. if (comp)
  2311. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2312. }
  2313. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2314. {
  2315. struct cnic_local *cp = dev->cnic_priv;
  2316. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2317. int kcqe_cnt;
  2318. /* status block index must be read before reading other fields */
  2319. rmb();
  2320. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2321. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2322. service_kcqes(dev, kcqe_cnt);
  2323. /* Tell compiler that status_blk fields can change. */
  2324. barrier();
  2325. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2326. /* status block index must be read first */
  2327. rmb();
  2328. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2329. }
  2330. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2331. cnic_chk_pkt_rings(cp);
  2332. return status_idx;
  2333. }
  2334. static int cnic_service_bnx2(void *data, void *status_blk)
  2335. {
  2336. struct cnic_dev *dev = data;
  2337. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2338. struct status_block *sblk = status_blk;
  2339. return sblk->status_idx;
  2340. }
  2341. return cnic_service_bnx2_queues(dev);
  2342. }
  2343. static void cnic_service_bnx2_msix(unsigned long data)
  2344. {
  2345. struct cnic_dev *dev = (struct cnic_dev *) data;
  2346. struct cnic_local *cp = dev->cnic_priv;
  2347. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2348. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2349. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2350. }
  2351. static void cnic_doirq(struct cnic_dev *dev)
  2352. {
  2353. struct cnic_local *cp = dev->cnic_priv;
  2354. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2355. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2356. prefetch(cp->status_blk.gen);
  2357. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2358. tasklet_schedule(&cp->cnic_irq_task);
  2359. }
  2360. }
  2361. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2362. {
  2363. struct cnic_dev *dev = dev_instance;
  2364. struct cnic_local *cp = dev->cnic_priv;
  2365. if (cp->ack_int)
  2366. cp->ack_int(dev);
  2367. cnic_doirq(dev);
  2368. return IRQ_HANDLED;
  2369. }
  2370. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2371. u16 index, u8 op, u8 update)
  2372. {
  2373. struct cnic_local *cp = dev->cnic_priv;
  2374. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2375. COMMAND_REG_INT_ACK);
  2376. struct igu_ack_register igu_ack;
  2377. igu_ack.status_block_index = index;
  2378. igu_ack.sb_id_and_flags =
  2379. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2380. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2381. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2382. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2383. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2384. }
  2385. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2386. u16 index, u8 op, u8 update)
  2387. {
  2388. struct igu_regular cmd_data;
  2389. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2390. cmd_data.sb_id_and_flags =
  2391. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2392. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2393. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2394. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2395. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2396. }
  2397. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2398. {
  2399. struct cnic_local *cp = dev->cnic_priv;
  2400. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2401. IGU_INT_DISABLE, 0);
  2402. }
  2403. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2404. {
  2405. struct cnic_local *cp = dev->cnic_priv;
  2406. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2407. IGU_INT_DISABLE, 0);
  2408. }
  2409. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2410. {
  2411. u32 last_status = *info->status_idx_ptr;
  2412. int kcqe_cnt;
  2413. /* status block index must be read before reading the KCQ */
  2414. rmb();
  2415. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2416. service_kcqes(dev, kcqe_cnt);
  2417. /* Tell compiler that sblk fields can change. */
  2418. barrier();
  2419. last_status = *info->status_idx_ptr;
  2420. /* status block index must be read before reading the KCQ */
  2421. rmb();
  2422. }
  2423. return last_status;
  2424. }
  2425. static void cnic_service_bnx2x_bh(unsigned long data)
  2426. {
  2427. struct cnic_dev *dev = (struct cnic_dev *) data;
  2428. struct cnic_local *cp = dev->cnic_priv;
  2429. u32 status_idx, new_status_idx;
  2430. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2431. return;
  2432. while (1) {
  2433. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2434. CNIC_WR16(dev, cp->kcq1.io_addr,
  2435. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2436. if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2437. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2438. status_idx, IGU_INT_ENABLE, 1);
  2439. break;
  2440. }
  2441. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2442. if (new_status_idx != status_idx)
  2443. continue;
  2444. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2445. MAX_KCQ_IDX);
  2446. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2447. status_idx, IGU_INT_ENABLE, 1);
  2448. break;
  2449. }
  2450. }
  2451. static int cnic_service_bnx2x(void *data, void *status_blk)
  2452. {
  2453. struct cnic_dev *dev = data;
  2454. struct cnic_local *cp = dev->cnic_priv;
  2455. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2456. cnic_doirq(dev);
  2457. cnic_chk_pkt_rings(cp);
  2458. return 0;
  2459. }
  2460. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2461. {
  2462. struct cnic_ulp_ops *ulp_ops;
  2463. if (if_type == CNIC_ULP_ISCSI)
  2464. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2465. mutex_lock(&cnic_lock);
  2466. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2467. lockdep_is_held(&cnic_lock));
  2468. if (!ulp_ops) {
  2469. mutex_unlock(&cnic_lock);
  2470. return;
  2471. }
  2472. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2473. mutex_unlock(&cnic_lock);
  2474. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2475. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2476. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2477. }
  2478. static void cnic_ulp_stop(struct cnic_dev *dev)
  2479. {
  2480. struct cnic_local *cp = dev->cnic_priv;
  2481. int if_type;
  2482. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2483. cnic_ulp_stop_one(cp, if_type);
  2484. }
  2485. static void cnic_ulp_start(struct cnic_dev *dev)
  2486. {
  2487. struct cnic_local *cp = dev->cnic_priv;
  2488. int if_type;
  2489. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2490. struct cnic_ulp_ops *ulp_ops;
  2491. mutex_lock(&cnic_lock);
  2492. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2493. lockdep_is_held(&cnic_lock));
  2494. if (!ulp_ops || !ulp_ops->cnic_start) {
  2495. mutex_unlock(&cnic_lock);
  2496. continue;
  2497. }
  2498. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2499. mutex_unlock(&cnic_lock);
  2500. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2501. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2502. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2503. }
  2504. }
  2505. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2506. {
  2507. struct cnic_dev *dev = data;
  2508. switch (info->cmd) {
  2509. case CNIC_CTL_STOP_CMD:
  2510. cnic_hold(dev);
  2511. cnic_ulp_stop(dev);
  2512. cnic_stop_hw(dev);
  2513. cnic_put(dev);
  2514. break;
  2515. case CNIC_CTL_START_CMD:
  2516. cnic_hold(dev);
  2517. if (!cnic_start_hw(dev))
  2518. cnic_ulp_start(dev);
  2519. cnic_put(dev);
  2520. break;
  2521. case CNIC_CTL_STOP_ISCSI_CMD: {
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2524. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2525. break;
  2526. }
  2527. case CNIC_CTL_COMPLETION_CMD: {
  2528. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2529. u32 l5_cid;
  2530. struct cnic_local *cp = dev->cnic_priv;
  2531. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2532. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2533. ctx->wait_cond = 1;
  2534. wake_up(&ctx->waitq);
  2535. }
  2536. break;
  2537. }
  2538. default:
  2539. return -EINVAL;
  2540. }
  2541. return 0;
  2542. }
  2543. static void cnic_ulp_init(struct cnic_dev *dev)
  2544. {
  2545. int i;
  2546. struct cnic_local *cp = dev->cnic_priv;
  2547. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2548. struct cnic_ulp_ops *ulp_ops;
  2549. mutex_lock(&cnic_lock);
  2550. ulp_ops = cnic_ulp_tbl_prot(i);
  2551. if (!ulp_ops || !ulp_ops->cnic_init) {
  2552. mutex_unlock(&cnic_lock);
  2553. continue;
  2554. }
  2555. ulp_get(ulp_ops);
  2556. mutex_unlock(&cnic_lock);
  2557. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2558. ulp_ops->cnic_init(dev);
  2559. ulp_put(ulp_ops);
  2560. }
  2561. }
  2562. static void cnic_ulp_exit(struct cnic_dev *dev)
  2563. {
  2564. int i;
  2565. struct cnic_local *cp = dev->cnic_priv;
  2566. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2567. struct cnic_ulp_ops *ulp_ops;
  2568. mutex_lock(&cnic_lock);
  2569. ulp_ops = cnic_ulp_tbl_prot(i);
  2570. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2571. mutex_unlock(&cnic_lock);
  2572. continue;
  2573. }
  2574. ulp_get(ulp_ops);
  2575. mutex_unlock(&cnic_lock);
  2576. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2577. ulp_ops->cnic_exit(dev);
  2578. ulp_put(ulp_ops);
  2579. }
  2580. }
  2581. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2582. {
  2583. struct cnic_dev *dev = csk->dev;
  2584. struct l4_kwq_offload_pg *l4kwqe;
  2585. struct kwqe *wqes[1];
  2586. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2587. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2588. wqes[0] = (struct kwqe *) l4kwqe;
  2589. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2590. l4kwqe->flags =
  2591. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2592. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2593. l4kwqe->da0 = csk->ha[0];
  2594. l4kwqe->da1 = csk->ha[1];
  2595. l4kwqe->da2 = csk->ha[2];
  2596. l4kwqe->da3 = csk->ha[3];
  2597. l4kwqe->da4 = csk->ha[4];
  2598. l4kwqe->da5 = csk->ha[5];
  2599. l4kwqe->sa0 = dev->mac_addr[0];
  2600. l4kwqe->sa1 = dev->mac_addr[1];
  2601. l4kwqe->sa2 = dev->mac_addr[2];
  2602. l4kwqe->sa3 = dev->mac_addr[3];
  2603. l4kwqe->sa4 = dev->mac_addr[4];
  2604. l4kwqe->sa5 = dev->mac_addr[5];
  2605. l4kwqe->etype = ETH_P_IP;
  2606. l4kwqe->ipid_start = DEF_IPID_START;
  2607. l4kwqe->host_opaque = csk->l5_cid;
  2608. if (csk->vlan_id) {
  2609. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2610. l4kwqe->vlan_tag = csk->vlan_id;
  2611. l4kwqe->l2hdr_nbytes += 4;
  2612. }
  2613. return dev->submit_kwqes(dev, wqes, 1);
  2614. }
  2615. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2616. {
  2617. struct cnic_dev *dev = csk->dev;
  2618. struct l4_kwq_update_pg *l4kwqe;
  2619. struct kwqe *wqes[1];
  2620. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2621. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2622. wqes[0] = (struct kwqe *) l4kwqe;
  2623. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2624. l4kwqe->flags =
  2625. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2626. l4kwqe->pg_cid = csk->pg_cid;
  2627. l4kwqe->da0 = csk->ha[0];
  2628. l4kwqe->da1 = csk->ha[1];
  2629. l4kwqe->da2 = csk->ha[2];
  2630. l4kwqe->da3 = csk->ha[3];
  2631. l4kwqe->da4 = csk->ha[4];
  2632. l4kwqe->da5 = csk->ha[5];
  2633. l4kwqe->pg_host_opaque = csk->l5_cid;
  2634. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2635. return dev->submit_kwqes(dev, wqes, 1);
  2636. }
  2637. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2638. {
  2639. struct cnic_dev *dev = csk->dev;
  2640. struct l4_kwq_upload *l4kwqe;
  2641. struct kwqe *wqes[1];
  2642. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2643. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2644. wqes[0] = (struct kwqe *) l4kwqe;
  2645. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2646. l4kwqe->flags =
  2647. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2648. l4kwqe->cid = csk->pg_cid;
  2649. return dev->submit_kwqes(dev, wqes, 1);
  2650. }
  2651. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2652. {
  2653. struct cnic_dev *dev = csk->dev;
  2654. struct l4_kwq_connect_req1 *l4kwqe1;
  2655. struct l4_kwq_connect_req2 *l4kwqe2;
  2656. struct l4_kwq_connect_req3 *l4kwqe3;
  2657. struct kwqe *wqes[3];
  2658. u8 tcp_flags = 0;
  2659. int num_wqes = 2;
  2660. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2661. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2662. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2663. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2664. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2665. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2666. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2667. l4kwqe3->flags =
  2668. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2669. l4kwqe3->ka_timeout = csk->ka_timeout;
  2670. l4kwqe3->ka_interval = csk->ka_interval;
  2671. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2672. l4kwqe3->tos = csk->tos;
  2673. l4kwqe3->ttl = csk->ttl;
  2674. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2675. l4kwqe3->pmtu = csk->mtu;
  2676. l4kwqe3->rcv_buf = csk->rcv_buf;
  2677. l4kwqe3->snd_buf = csk->snd_buf;
  2678. l4kwqe3->seed = csk->seed;
  2679. wqes[0] = (struct kwqe *) l4kwqe1;
  2680. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2681. wqes[1] = (struct kwqe *) l4kwqe2;
  2682. wqes[2] = (struct kwqe *) l4kwqe3;
  2683. num_wqes = 3;
  2684. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2685. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2686. l4kwqe2->flags =
  2687. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2688. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2689. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2690. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2691. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2692. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2693. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2694. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2695. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2696. sizeof(struct tcphdr);
  2697. } else {
  2698. wqes[1] = (struct kwqe *) l4kwqe3;
  2699. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2700. sizeof(struct tcphdr);
  2701. }
  2702. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2703. l4kwqe1->flags =
  2704. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2705. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2706. l4kwqe1->cid = csk->cid;
  2707. l4kwqe1->pg_cid = csk->pg_cid;
  2708. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2709. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2710. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2711. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2712. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2713. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2714. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2715. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2716. if (csk->tcp_flags & SK_TCP_NAGLE)
  2717. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2718. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2719. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2720. if (csk->tcp_flags & SK_TCP_SACK)
  2721. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2722. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2723. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2724. l4kwqe1->tcp_flags = tcp_flags;
  2725. return dev->submit_kwqes(dev, wqes, num_wqes);
  2726. }
  2727. static int cnic_cm_close_req(struct cnic_sock *csk)
  2728. {
  2729. struct cnic_dev *dev = csk->dev;
  2730. struct l4_kwq_close_req *l4kwqe;
  2731. struct kwqe *wqes[1];
  2732. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2733. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2734. wqes[0] = (struct kwqe *) l4kwqe;
  2735. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2736. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2737. l4kwqe->cid = csk->cid;
  2738. return dev->submit_kwqes(dev, wqes, 1);
  2739. }
  2740. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2741. {
  2742. struct cnic_dev *dev = csk->dev;
  2743. struct l4_kwq_reset_req *l4kwqe;
  2744. struct kwqe *wqes[1];
  2745. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2746. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2747. wqes[0] = (struct kwqe *) l4kwqe;
  2748. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2749. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2750. l4kwqe->cid = csk->cid;
  2751. return dev->submit_kwqes(dev, wqes, 1);
  2752. }
  2753. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2754. u32 l5_cid, struct cnic_sock **csk, void *context)
  2755. {
  2756. struct cnic_local *cp = dev->cnic_priv;
  2757. struct cnic_sock *csk1;
  2758. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2759. return -EINVAL;
  2760. if (cp->ctx_tbl) {
  2761. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2762. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2763. return -EAGAIN;
  2764. }
  2765. csk1 = &cp->csk_tbl[l5_cid];
  2766. if (atomic_read(&csk1->ref_count))
  2767. return -EAGAIN;
  2768. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2769. return -EBUSY;
  2770. csk1->dev = dev;
  2771. csk1->cid = cid;
  2772. csk1->l5_cid = l5_cid;
  2773. csk1->ulp_type = ulp_type;
  2774. csk1->context = context;
  2775. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2776. csk1->ka_interval = DEF_KA_INTERVAL;
  2777. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2778. csk1->tos = DEF_TOS;
  2779. csk1->ttl = DEF_TTL;
  2780. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2781. csk1->rcv_buf = DEF_RCV_BUF;
  2782. csk1->snd_buf = DEF_SND_BUF;
  2783. csk1->seed = DEF_SEED;
  2784. *csk = csk1;
  2785. return 0;
  2786. }
  2787. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2788. {
  2789. if (csk->src_port) {
  2790. struct cnic_dev *dev = csk->dev;
  2791. struct cnic_local *cp = dev->cnic_priv;
  2792. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2793. csk->src_port = 0;
  2794. }
  2795. }
  2796. static void cnic_close_conn(struct cnic_sock *csk)
  2797. {
  2798. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2799. cnic_cm_upload_pg(csk);
  2800. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2801. }
  2802. cnic_cm_cleanup(csk);
  2803. }
  2804. static int cnic_cm_destroy(struct cnic_sock *csk)
  2805. {
  2806. if (!cnic_in_use(csk))
  2807. return -EINVAL;
  2808. csk_hold(csk);
  2809. clear_bit(SK_F_INUSE, &csk->flags);
  2810. smp_mb__after_clear_bit();
  2811. while (atomic_read(&csk->ref_count) != 1)
  2812. msleep(1);
  2813. cnic_cm_cleanup(csk);
  2814. csk->flags = 0;
  2815. csk_put(csk);
  2816. return 0;
  2817. }
  2818. static inline u16 cnic_get_vlan(struct net_device *dev,
  2819. struct net_device **vlan_dev)
  2820. {
  2821. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2822. *vlan_dev = vlan_dev_real_dev(dev);
  2823. return vlan_dev_vlan_id(dev);
  2824. }
  2825. *vlan_dev = dev;
  2826. return 0;
  2827. }
  2828. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2829. struct dst_entry **dst)
  2830. {
  2831. #if defined(CONFIG_INET)
  2832. struct rtable *rt;
  2833. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2834. if (!IS_ERR(rt)) {
  2835. *dst = &rt->dst;
  2836. return 0;
  2837. }
  2838. return PTR_ERR(rt);
  2839. #else
  2840. return -ENETUNREACH;
  2841. #endif
  2842. }
  2843. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2844. struct dst_entry **dst)
  2845. {
  2846. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2847. struct flowi6 fl6;
  2848. memset(&fl6, 0, sizeof(fl6));
  2849. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2850. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2851. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2852. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2853. if (*dst)
  2854. return 0;
  2855. #endif
  2856. return -ENETUNREACH;
  2857. }
  2858. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2859. int ulp_type)
  2860. {
  2861. struct cnic_dev *dev = NULL;
  2862. struct dst_entry *dst;
  2863. struct net_device *netdev = NULL;
  2864. int err = -ENETUNREACH;
  2865. if (dst_addr->sin_family == AF_INET)
  2866. err = cnic_get_v4_route(dst_addr, &dst);
  2867. else if (dst_addr->sin_family == AF_INET6) {
  2868. struct sockaddr_in6 *dst_addr6 =
  2869. (struct sockaddr_in6 *) dst_addr;
  2870. err = cnic_get_v6_route(dst_addr6, &dst);
  2871. } else
  2872. return NULL;
  2873. if (err)
  2874. return NULL;
  2875. if (!dst->dev)
  2876. goto done;
  2877. cnic_get_vlan(dst->dev, &netdev);
  2878. dev = cnic_from_netdev(netdev);
  2879. done:
  2880. dst_release(dst);
  2881. if (dev)
  2882. cnic_put(dev);
  2883. return dev;
  2884. }
  2885. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2886. {
  2887. struct cnic_dev *dev = csk->dev;
  2888. struct cnic_local *cp = dev->cnic_priv;
  2889. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2890. }
  2891. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2892. {
  2893. struct cnic_dev *dev = csk->dev;
  2894. struct cnic_local *cp = dev->cnic_priv;
  2895. int is_v6, rc = 0;
  2896. struct dst_entry *dst = NULL;
  2897. struct net_device *realdev;
  2898. __be16 local_port;
  2899. u32 port_id;
  2900. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2901. saddr->remote.v6.sin6_family == AF_INET6)
  2902. is_v6 = 1;
  2903. else if (saddr->local.v4.sin_family == AF_INET &&
  2904. saddr->remote.v4.sin_family == AF_INET)
  2905. is_v6 = 0;
  2906. else
  2907. return -EINVAL;
  2908. clear_bit(SK_F_IPV6, &csk->flags);
  2909. if (is_v6) {
  2910. set_bit(SK_F_IPV6, &csk->flags);
  2911. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2912. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2913. sizeof(struct in6_addr));
  2914. csk->dst_port = saddr->remote.v6.sin6_port;
  2915. local_port = saddr->local.v6.sin6_port;
  2916. } else {
  2917. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2918. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2919. csk->dst_port = saddr->remote.v4.sin_port;
  2920. local_port = saddr->local.v4.sin_port;
  2921. }
  2922. csk->vlan_id = 0;
  2923. csk->mtu = dev->netdev->mtu;
  2924. if (dst && dst->dev) {
  2925. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2926. if (realdev == dev->netdev) {
  2927. csk->vlan_id = vlan;
  2928. csk->mtu = dst_mtu(dst);
  2929. }
  2930. }
  2931. port_id = be16_to_cpu(local_port);
  2932. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2933. port_id < CNIC_LOCAL_PORT_MAX) {
  2934. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2935. port_id = 0;
  2936. } else
  2937. port_id = 0;
  2938. if (!port_id) {
  2939. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2940. if (port_id == -1) {
  2941. rc = -ENOMEM;
  2942. goto err_out;
  2943. }
  2944. local_port = cpu_to_be16(port_id);
  2945. }
  2946. csk->src_port = local_port;
  2947. err_out:
  2948. dst_release(dst);
  2949. return rc;
  2950. }
  2951. static void cnic_init_csk_state(struct cnic_sock *csk)
  2952. {
  2953. csk->state = 0;
  2954. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2955. clear_bit(SK_F_CLOSING, &csk->flags);
  2956. }
  2957. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2958. {
  2959. struct cnic_local *cp = csk->dev->cnic_priv;
  2960. int err = 0;
  2961. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2962. return -EOPNOTSUPP;
  2963. if (!cnic_in_use(csk))
  2964. return -EINVAL;
  2965. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2966. return -EINVAL;
  2967. cnic_init_csk_state(csk);
  2968. err = cnic_get_route(csk, saddr);
  2969. if (err)
  2970. goto err_out;
  2971. err = cnic_resolve_addr(csk, saddr);
  2972. if (!err)
  2973. return 0;
  2974. err_out:
  2975. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2976. return err;
  2977. }
  2978. static int cnic_cm_abort(struct cnic_sock *csk)
  2979. {
  2980. struct cnic_local *cp = csk->dev->cnic_priv;
  2981. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2982. if (!cnic_in_use(csk))
  2983. return -EINVAL;
  2984. if (cnic_abort_prep(csk))
  2985. return cnic_cm_abort_req(csk);
  2986. /* Getting here means that we haven't started connect, or
  2987. * connect was not successful.
  2988. */
  2989. cp->close_conn(csk, opcode);
  2990. if (csk->state != opcode)
  2991. return -EALREADY;
  2992. return 0;
  2993. }
  2994. static int cnic_cm_close(struct cnic_sock *csk)
  2995. {
  2996. if (!cnic_in_use(csk))
  2997. return -EINVAL;
  2998. if (cnic_close_prep(csk)) {
  2999. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3000. return cnic_cm_close_req(csk);
  3001. } else {
  3002. return -EALREADY;
  3003. }
  3004. return 0;
  3005. }
  3006. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3007. u8 opcode)
  3008. {
  3009. struct cnic_ulp_ops *ulp_ops;
  3010. int ulp_type = csk->ulp_type;
  3011. rcu_read_lock();
  3012. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3013. if (ulp_ops) {
  3014. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3015. ulp_ops->cm_connect_complete(csk);
  3016. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3017. ulp_ops->cm_close_complete(csk);
  3018. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3019. ulp_ops->cm_remote_abort(csk);
  3020. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3021. ulp_ops->cm_abort_complete(csk);
  3022. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3023. ulp_ops->cm_remote_close(csk);
  3024. }
  3025. rcu_read_unlock();
  3026. }
  3027. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3028. {
  3029. if (cnic_offld_prep(csk)) {
  3030. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3031. cnic_cm_update_pg(csk);
  3032. else
  3033. cnic_cm_offload_pg(csk);
  3034. }
  3035. return 0;
  3036. }
  3037. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3038. {
  3039. struct cnic_local *cp = dev->cnic_priv;
  3040. u32 l5_cid = kcqe->pg_host_opaque;
  3041. u8 opcode = kcqe->op_code;
  3042. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3043. csk_hold(csk);
  3044. if (!cnic_in_use(csk))
  3045. goto done;
  3046. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3047. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3048. goto done;
  3049. }
  3050. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3051. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3052. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3053. cnic_cm_upcall(cp, csk,
  3054. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3055. goto done;
  3056. }
  3057. csk->pg_cid = kcqe->pg_cid;
  3058. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3059. cnic_cm_conn_req(csk);
  3060. done:
  3061. csk_put(csk);
  3062. }
  3063. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3064. {
  3065. struct cnic_local *cp = dev->cnic_priv;
  3066. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3067. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3068. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3069. ctx->timestamp = jiffies;
  3070. ctx->wait_cond = 1;
  3071. wake_up(&ctx->waitq);
  3072. }
  3073. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3074. {
  3075. struct cnic_local *cp = dev->cnic_priv;
  3076. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3077. u8 opcode = l4kcqe->op_code;
  3078. u32 l5_cid;
  3079. struct cnic_sock *csk;
  3080. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3081. cnic_process_fcoe_term_conn(dev, kcqe);
  3082. return;
  3083. }
  3084. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3085. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3086. cnic_cm_process_offld_pg(dev, l4kcqe);
  3087. return;
  3088. }
  3089. l5_cid = l4kcqe->conn_id;
  3090. if (opcode & 0x80)
  3091. l5_cid = l4kcqe->cid;
  3092. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3093. return;
  3094. csk = &cp->csk_tbl[l5_cid];
  3095. csk_hold(csk);
  3096. if (!cnic_in_use(csk)) {
  3097. csk_put(csk);
  3098. return;
  3099. }
  3100. switch (opcode) {
  3101. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3102. if (l4kcqe->status != 0) {
  3103. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3104. cnic_cm_upcall(cp, csk,
  3105. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3106. }
  3107. break;
  3108. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3109. if (l4kcqe->status == 0)
  3110. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3111. smp_mb__before_clear_bit();
  3112. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3113. cnic_cm_upcall(cp, csk, opcode);
  3114. break;
  3115. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3116. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3117. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3118. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3119. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3120. cp->close_conn(csk, opcode);
  3121. break;
  3122. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3123. /* after we already sent CLOSE_REQ */
  3124. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3125. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3126. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3127. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3128. else
  3129. cnic_cm_upcall(cp, csk, opcode);
  3130. break;
  3131. }
  3132. csk_put(csk);
  3133. }
  3134. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3135. {
  3136. struct cnic_dev *dev = data;
  3137. int i;
  3138. for (i = 0; i < num; i++)
  3139. cnic_cm_process_kcqe(dev, kcqe[i]);
  3140. }
  3141. static struct cnic_ulp_ops cm_ulp_ops = {
  3142. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3143. };
  3144. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3145. {
  3146. struct cnic_local *cp = dev->cnic_priv;
  3147. kfree(cp->csk_tbl);
  3148. cp->csk_tbl = NULL;
  3149. cnic_free_id_tbl(&cp->csk_port_tbl);
  3150. }
  3151. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3152. {
  3153. struct cnic_local *cp = dev->cnic_priv;
  3154. u32 port_id;
  3155. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3156. GFP_KERNEL);
  3157. if (!cp->csk_tbl)
  3158. return -ENOMEM;
  3159. get_random_bytes(&port_id, sizeof(port_id));
  3160. port_id %= CNIC_LOCAL_PORT_RANGE;
  3161. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3162. CNIC_LOCAL_PORT_MIN, port_id)) {
  3163. cnic_cm_free_mem(dev);
  3164. return -ENOMEM;
  3165. }
  3166. return 0;
  3167. }
  3168. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3169. {
  3170. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3171. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3172. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3173. csk->state = opcode;
  3174. }
  3175. /* 1. If event opcode matches the expected event in csk->state
  3176. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3177. * event
  3178. * 3. If the expected event is 0, meaning the connection was never
  3179. * never established, we accept the opcode from cm_abort.
  3180. */
  3181. if (opcode == csk->state || csk->state == 0 ||
  3182. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3183. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3184. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3185. if (csk->state == 0)
  3186. csk->state = opcode;
  3187. return 1;
  3188. }
  3189. }
  3190. return 0;
  3191. }
  3192. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3193. {
  3194. struct cnic_dev *dev = csk->dev;
  3195. struct cnic_local *cp = dev->cnic_priv;
  3196. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3197. cnic_cm_upcall(cp, csk, opcode);
  3198. return;
  3199. }
  3200. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3201. cnic_close_conn(csk);
  3202. csk->state = opcode;
  3203. cnic_cm_upcall(cp, csk, opcode);
  3204. }
  3205. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3206. {
  3207. }
  3208. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3209. {
  3210. u32 seed;
  3211. get_random_bytes(&seed, 4);
  3212. cnic_ctx_wr(dev, 45, 0, seed);
  3213. return 0;
  3214. }
  3215. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3216. {
  3217. struct cnic_dev *dev = csk->dev;
  3218. struct cnic_local *cp = dev->cnic_priv;
  3219. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3220. union l5cm_specific_data l5_data;
  3221. u32 cmd = 0;
  3222. int close_complete = 0;
  3223. switch (opcode) {
  3224. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3225. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3226. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3227. if (cnic_ready_to_close(csk, opcode)) {
  3228. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3229. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3230. else
  3231. close_complete = 1;
  3232. }
  3233. break;
  3234. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3235. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3236. break;
  3237. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3238. close_complete = 1;
  3239. break;
  3240. }
  3241. if (cmd) {
  3242. memset(&l5_data, 0, sizeof(l5_data));
  3243. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3244. &l5_data);
  3245. } else if (close_complete) {
  3246. ctx->timestamp = jiffies;
  3247. cnic_close_conn(csk);
  3248. cnic_cm_upcall(cp, csk, csk->state);
  3249. }
  3250. }
  3251. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3252. {
  3253. struct cnic_local *cp = dev->cnic_priv;
  3254. int i;
  3255. if (!cp->ctx_tbl)
  3256. return;
  3257. if (!netif_running(dev->netdev))
  3258. return;
  3259. for (i = 0; i < cp->max_cid_space; i++) {
  3260. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3261. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3262. msleep(10);
  3263. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3264. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3265. ctx->cid);
  3266. }
  3267. cancel_delayed_work(&cp->delete_task);
  3268. flush_workqueue(cnic_wq);
  3269. if (atomic_read(&cp->iscsi_conn) != 0)
  3270. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3271. atomic_read(&cp->iscsi_conn));
  3272. }
  3273. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3274. {
  3275. struct cnic_local *cp = dev->cnic_priv;
  3276. u32 pfid = cp->pfid;
  3277. u32 port = CNIC_PORT(cp);
  3278. cnic_init_bnx2x_mac(dev);
  3279. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3280. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3281. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3282. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3283. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3284. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3285. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3286. DEF_MAX_DA_COUNT);
  3287. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3288. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3289. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3290. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3291. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3292. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3293. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3294. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3295. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3296. DEF_MAX_CWND);
  3297. return 0;
  3298. }
  3299. static void cnic_delete_task(struct work_struct *work)
  3300. {
  3301. struct cnic_local *cp;
  3302. struct cnic_dev *dev;
  3303. u32 i;
  3304. int need_resched = 0;
  3305. cp = container_of(work, struct cnic_local, delete_task.work);
  3306. dev = cp->dev;
  3307. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3308. struct drv_ctl_info info;
  3309. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3310. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3311. cp->ethdev->drv_ctl(dev->netdev, &info);
  3312. }
  3313. for (i = 0; i < cp->max_cid_space; i++) {
  3314. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3315. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3316. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3317. continue;
  3318. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3319. need_resched = 1;
  3320. continue;
  3321. }
  3322. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3323. continue;
  3324. cnic_bnx2x_destroy_ramrod(dev, i);
  3325. cnic_free_bnx2x_conn_resc(dev, i);
  3326. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3327. atomic_dec(&cp->iscsi_conn);
  3328. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3329. }
  3330. if (need_resched)
  3331. queue_delayed_work(cnic_wq, &cp->delete_task,
  3332. msecs_to_jiffies(10));
  3333. }
  3334. static int cnic_cm_open(struct cnic_dev *dev)
  3335. {
  3336. struct cnic_local *cp = dev->cnic_priv;
  3337. int err;
  3338. err = cnic_cm_alloc_mem(dev);
  3339. if (err)
  3340. return err;
  3341. err = cp->start_cm(dev);
  3342. if (err)
  3343. goto err_out;
  3344. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3345. dev->cm_create = cnic_cm_create;
  3346. dev->cm_destroy = cnic_cm_destroy;
  3347. dev->cm_connect = cnic_cm_connect;
  3348. dev->cm_abort = cnic_cm_abort;
  3349. dev->cm_close = cnic_cm_close;
  3350. dev->cm_select_dev = cnic_cm_select_dev;
  3351. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3352. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3353. return 0;
  3354. err_out:
  3355. cnic_cm_free_mem(dev);
  3356. return err;
  3357. }
  3358. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3359. {
  3360. struct cnic_local *cp = dev->cnic_priv;
  3361. int i;
  3362. cp->stop_cm(dev);
  3363. if (!cp->csk_tbl)
  3364. return 0;
  3365. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3366. struct cnic_sock *csk = &cp->csk_tbl[i];
  3367. clear_bit(SK_F_INUSE, &csk->flags);
  3368. cnic_cm_cleanup(csk);
  3369. }
  3370. cnic_cm_free_mem(dev);
  3371. return 0;
  3372. }
  3373. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3374. {
  3375. u32 cid_addr;
  3376. int i;
  3377. cid_addr = GET_CID_ADDR(cid);
  3378. for (i = 0; i < CTX_SIZE; i += 4)
  3379. cnic_ctx_wr(dev, cid_addr, i, 0);
  3380. }
  3381. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3382. {
  3383. struct cnic_local *cp = dev->cnic_priv;
  3384. int ret = 0, i;
  3385. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3386. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3387. return 0;
  3388. for (i = 0; i < cp->ctx_blks; i++) {
  3389. int j;
  3390. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3391. u32 val;
  3392. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3393. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3394. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3395. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3396. (u64) cp->ctx_arr[i].mapping >> 32);
  3397. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3398. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3399. for (j = 0; j < 10; j++) {
  3400. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3401. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3402. break;
  3403. udelay(5);
  3404. }
  3405. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3406. ret = -EBUSY;
  3407. break;
  3408. }
  3409. }
  3410. return ret;
  3411. }
  3412. static void cnic_free_irq(struct cnic_dev *dev)
  3413. {
  3414. struct cnic_local *cp = dev->cnic_priv;
  3415. struct cnic_eth_dev *ethdev = cp->ethdev;
  3416. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3417. cp->disable_int_sync(dev);
  3418. tasklet_kill(&cp->cnic_irq_task);
  3419. free_irq(ethdev->irq_arr[0].vector, dev);
  3420. }
  3421. }
  3422. static int cnic_request_irq(struct cnic_dev *dev)
  3423. {
  3424. struct cnic_local *cp = dev->cnic_priv;
  3425. struct cnic_eth_dev *ethdev = cp->ethdev;
  3426. int err;
  3427. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3428. if (err)
  3429. tasklet_disable(&cp->cnic_irq_task);
  3430. return err;
  3431. }
  3432. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3433. {
  3434. struct cnic_local *cp = dev->cnic_priv;
  3435. struct cnic_eth_dev *ethdev = cp->ethdev;
  3436. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3437. int err, i = 0;
  3438. int sblk_num = cp->status_blk_num;
  3439. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3440. BNX2_HC_SB_CONFIG_1;
  3441. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3442. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3443. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3444. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3445. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3446. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3447. (unsigned long) dev);
  3448. err = cnic_request_irq(dev);
  3449. if (err)
  3450. return err;
  3451. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3452. i < 10) {
  3453. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3454. 1 << (11 + sblk_num));
  3455. udelay(10);
  3456. i++;
  3457. barrier();
  3458. }
  3459. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3460. cnic_free_irq(dev);
  3461. goto failed;
  3462. }
  3463. } else {
  3464. struct status_block *sblk = cp->status_blk.gen;
  3465. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3466. int i = 0;
  3467. while (sblk->status_completion_producer_index && i < 10) {
  3468. CNIC_WR(dev, BNX2_HC_COMMAND,
  3469. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3470. udelay(10);
  3471. i++;
  3472. barrier();
  3473. }
  3474. if (sblk->status_completion_producer_index)
  3475. goto failed;
  3476. }
  3477. return 0;
  3478. failed:
  3479. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3480. return -EBUSY;
  3481. }
  3482. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3483. {
  3484. struct cnic_local *cp = dev->cnic_priv;
  3485. struct cnic_eth_dev *ethdev = cp->ethdev;
  3486. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3487. return;
  3488. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3489. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3490. }
  3491. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3492. {
  3493. struct cnic_local *cp = dev->cnic_priv;
  3494. struct cnic_eth_dev *ethdev = cp->ethdev;
  3495. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3496. return;
  3497. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3498. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3499. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3500. synchronize_irq(ethdev->irq_arr[0].vector);
  3501. }
  3502. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3503. {
  3504. struct cnic_local *cp = dev->cnic_priv;
  3505. struct cnic_eth_dev *ethdev = cp->ethdev;
  3506. struct cnic_uio_dev *udev = cp->udev;
  3507. u32 cid_addr, tx_cid, sb_id;
  3508. u32 val, offset0, offset1, offset2, offset3;
  3509. int i;
  3510. struct tx_bd *txbd;
  3511. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3512. struct status_block *s_blk = cp->status_blk.gen;
  3513. sb_id = cp->status_blk_num;
  3514. tx_cid = 20;
  3515. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3516. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3517. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3518. tx_cid = TX_TSS_CID + sb_id - 1;
  3519. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3520. (TX_TSS_CID << 7));
  3521. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3522. }
  3523. cp->tx_cons = *cp->tx_cons_ptr;
  3524. cid_addr = GET_CID_ADDR(tx_cid);
  3525. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3526. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3527. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3528. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3529. offset0 = BNX2_L2CTX_TYPE_XI;
  3530. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3531. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3532. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3533. } else {
  3534. cnic_init_context(dev, tx_cid);
  3535. cnic_init_context(dev, tx_cid + 1);
  3536. offset0 = BNX2_L2CTX_TYPE;
  3537. offset1 = BNX2_L2CTX_CMD_TYPE;
  3538. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3539. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3540. }
  3541. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3542. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3543. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3544. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3545. txbd = (struct tx_bd *) udev->l2_ring;
  3546. buf_map = udev->l2_buf_map;
  3547. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3548. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3549. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3550. }
  3551. val = (u64) ring_map >> 32;
  3552. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3553. txbd->tx_bd_haddr_hi = val;
  3554. val = (u64) ring_map & 0xffffffff;
  3555. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3556. txbd->tx_bd_haddr_lo = val;
  3557. }
  3558. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3559. {
  3560. struct cnic_local *cp = dev->cnic_priv;
  3561. struct cnic_eth_dev *ethdev = cp->ethdev;
  3562. struct cnic_uio_dev *udev = cp->udev;
  3563. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3564. int i;
  3565. struct rx_bd *rxbd;
  3566. struct status_block *s_blk = cp->status_blk.gen;
  3567. dma_addr_t ring_map = udev->l2_ring_map;
  3568. sb_id = cp->status_blk_num;
  3569. cnic_init_context(dev, 2);
  3570. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3571. coal_reg = BNX2_HC_COMMAND;
  3572. coal_val = CNIC_RD(dev, coal_reg);
  3573. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3574. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3575. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3576. coal_reg = BNX2_HC_COALESCE_NOW;
  3577. coal_val = 1 << (11 + sb_id);
  3578. }
  3579. i = 0;
  3580. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3581. CNIC_WR(dev, coal_reg, coal_val);
  3582. udelay(10);
  3583. i++;
  3584. barrier();
  3585. }
  3586. cp->rx_cons = *cp->rx_cons_ptr;
  3587. cid_addr = GET_CID_ADDR(2);
  3588. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3589. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3590. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3591. if (sb_id == 0)
  3592. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3593. else
  3594. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3595. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3596. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3597. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3598. dma_addr_t buf_map;
  3599. int n = (i % cp->l2_rx_ring_size) + 1;
  3600. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3601. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3602. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3603. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3604. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3605. }
  3606. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3607. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3608. rxbd->rx_bd_haddr_hi = val;
  3609. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3610. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3611. rxbd->rx_bd_haddr_lo = val;
  3612. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3613. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3614. }
  3615. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3616. {
  3617. struct kwqe *wqes[1], l2kwqe;
  3618. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3619. wqes[0] = &l2kwqe;
  3620. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3621. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3622. KWQE_OPCODE_SHIFT) | 2;
  3623. dev->submit_kwqes(dev, wqes, 1);
  3624. }
  3625. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3626. {
  3627. struct cnic_local *cp = dev->cnic_priv;
  3628. u32 val;
  3629. val = cp->func << 2;
  3630. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3631. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3632. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3633. dev->mac_addr[0] = (u8) (val >> 8);
  3634. dev->mac_addr[1] = (u8) val;
  3635. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3636. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3637. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3638. dev->mac_addr[2] = (u8) (val >> 24);
  3639. dev->mac_addr[3] = (u8) (val >> 16);
  3640. dev->mac_addr[4] = (u8) (val >> 8);
  3641. dev->mac_addr[5] = (u8) val;
  3642. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3643. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3644. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3645. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3646. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3647. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3648. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3649. }
  3650. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3651. {
  3652. struct cnic_local *cp = dev->cnic_priv;
  3653. struct cnic_eth_dev *ethdev = cp->ethdev;
  3654. struct status_block *sblk = cp->status_blk.gen;
  3655. u32 val, kcq_cid_addr, kwq_cid_addr;
  3656. int err;
  3657. cnic_set_bnx2_mac(dev);
  3658. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3659. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3660. if (BCM_PAGE_BITS > 12)
  3661. val |= (12 - 8) << 4;
  3662. else
  3663. val |= (BCM_PAGE_BITS - 8) << 4;
  3664. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3665. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3666. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3667. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3668. err = cnic_setup_5709_context(dev, 1);
  3669. if (err)
  3670. return err;
  3671. cnic_init_context(dev, KWQ_CID);
  3672. cnic_init_context(dev, KCQ_CID);
  3673. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3674. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3675. cp->max_kwq_idx = MAX_KWQ_IDX;
  3676. cp->kwq_prod_idx = 0;
  3677. cp->kwq_con_idx = 0;
  3678. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3679. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3680. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3681. else
  3682. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3683. /* Initialize the kernel work queue context. */
  3684. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3685. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3686. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3687. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3688. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3689. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3690. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3691. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3692. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3693. val = (u32) cp->kwq_info.pgtbl_map;
  3694. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3695. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3696. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3697. cp->kcq1.sw_prod_idx = 0;
  3698. cp->kcq1.hw_prod_idx_ptr =
  3699. (u16 *) &sblk->status_completion_producer_index;
  3700. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3701. /* Initialize the kernel complete queue context. */
  3702. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3703. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3704. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3705. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3706. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3707. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3708. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3709. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3710. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3711. val = (u32) cp->kcq1.dma.pgtbl_map;
  3712. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3713. cp->int_num = 0;
  3714. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3715. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3716. u32 sb_id = cp->status_blk_num;
  3717. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3718. cp->kcq1.hw_prod_idx_ptr =
  3719. (u16 *) &msblk->status_completion_producer_index;
  3720. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3721. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3722. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3723. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3724. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3725. }
  3726. /* Enable Commnad Scheduler notification when we write to the
  3727. * host producer index of the kernel contexts. */
  3728. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3729. /* Enable Command Scheduler notification when we write to either
  3730. * the Send Queue or Receive Queue producer indexes of the kernel
  3731. * bypass contexts. */
  3732. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3733. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3734. /* Notify COM when the driver post an application buffer. */
  3735. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3736. /* Set the CP and COM doorbells. These two processors polls the
  3737. * doorbell for a non zero value before running. This must be done
  3738. * after setting up the kernel queue contexts. */
  3739. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3740. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3741. cnic_init_bnx2_tx_ring(dev);
  3742. cnic_init_bnx2_rx_ring(dev);
  3743. err = cnic_init_bnx2_irq(dev);
  3744. if (err) {
  3745. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3746. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3747. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3748. return err;
  3749. }
  3750. return 0;
  3751. }
  3752. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3753. {
  3754. struct cnic_local *cp = dev->cnic_priv;
  3755. struct cnic_eth_dev *ethdev = cp->ethdev;
  3756. u32 start_offset = ethdev->ctx_tbl_offset;
  3757. int i;
  3758. for (i = 0; i < cp->ctx_blks; i++) {
  3759. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3760. dma_addr_t map = ctx->mapping;
  3761. if (cp->ctx_align) {
  3762. unsigned long mask = cp->ctx_align - 1;
  3763. map = (map + mask) & ~mask;
  3764. }
  3765. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3766. }
  3767. }
  3768. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3769. {
  3770. struct cnic_local *cp = dev->cnic_priv;
  3771. struct cnic_eth_dev *ethdev = cp->ethdev;
  3772. int err = 0;
  3773. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3774. (unsigned long) dev);
  3775. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3776. err = cnic_request_irq(dev);
  3777. return err;
  3778. }
  3779. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3780. u16 sb_id, u8 sb_index,
  3781. u8 disable)
  3782. {
  3783. u32 addr = BAR_CSTRORM_INTMEM +
  3784. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3785. offsetof(struct hc_status_block_data_e1x, index_data) +
  3786. sizeof(struct hc_index_data)*sb_index +
  3787. offsetof(struct hc_index_data, flags);
  3788. u16 flags = CNIC_RD16(dev, addr);
  3789. /* clear and set */
  3790. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3791. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3792. HC_INDEX_DATA_HC_ENABLED);
  3793. CNIC_WR16(dev, addr, flags);
  3794. }
  3795. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3796. {
  3797. struct cnic_local *cp = dev->cnic_priv;
  3798. u8 sb_id = cp->status_blk_num;
  3799. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3800. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3801. offsetof(struct hc_status_block_data_e1x, index_data) +
  3802. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3803. offsetof(struct hc_index_data, timeout), 64 / 12);
  3804. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3805. }
  3806. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3807. {
  3808. }
  3809. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3810. struct client_init_ramrod_data *data)
  3811. {
  3812. struct cnic_local *cp = dev->cnic_priv;
  3813. struct cnic_uio_dev *udev = cp->udev;
  3814. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3815. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3816. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3817. int port = CNIC_PORT(cp);
  3818. int i;
  3819. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3820. u32 val;
  3821. memset(txbd, 0, BCM_PAGE_SIZE);
  3822. buf_map = udev->l2_buf_map;
  3823. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3824. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3825. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3826. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3827. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3828. reg_bd->addr_hi = start_bd->addr_hi;
  3829. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3830. start_bd->nbytes = cpu_to_le16(0x10);
  3831. start_bd->nbd = cpu_to_le16(3);
  3832. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3833. start_bd->general_data = (UNICAST_ADDRESS <<
  3834. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3835. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3836. }
  3837. val = (u64) ring_map >> 32;
  3838. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3839. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3840. val = (u64) ring_map & 0xffffffff;
  3841. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3842. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3843. /* Other ramrod params */
  3844. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3845. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3846. /* reset xstorm per client statistics */
  3847. if (cli < MAX_STAT_COUNTER_ID) {
  3848. val = BAR_XSTRORM_INTMEM +
  3849. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3850. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3851. CNIC_WR(dev, val + i * 4, 0);
  3852. }
  3853. cp->tx_cons_ptr =
  3854. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3855. }
  3856. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3857. struct client_init_ramrod_data *data)
  3858. {
  3859. struct cnic_local *cp = dev->cnic_priv;
  3860. struct cnic_uio_dev *udev = cp->udev;
  3861. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3862. BCM_PAGE_SIZE);
  3863. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3864. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3865. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3866. int i;
  3867. int port = CNIC_PORT(cp);
  3868. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3869. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3870. u32 val;
  3871. dma_addr_t ring_map = udev->l2_ring_map;
  3872. /* General data */
  3873. data->general.client_id = cli;
  3874. data->general.statistics_en_flg = 1;
  3875. data->general.statistics_counter_id = cli;
  3876. data->general.activate_flg = 1;
  3877. data->general.sp_client_id = cli;
  3878. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3879. dma_addr_t buf_map;
  3880. int n = (i % cp->l2_rx_ring_size) + 1;
  3881. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3882. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3883. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3884. }
  3885. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3886. rxbd->addr_hi = cpu_to_le32(val);
  3887. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3888. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3889. rxbd->addr_lo = cpu_to_le32(val);
  3890. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3891. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3892. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3893. rxcqe->addr_hi = cpu_to_le32(val);
  3894. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3895. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3896. rxcqe->addr_lo = cpu_to_le32(val);
  3897. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3898. /* Other ramrod params */
  3899. data->rx.client_qzone_id = cl_qzone_id;
  3900. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3901. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3902. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3903. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3904. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3905. data->rx.outer_vlan_removal_enable_flg = 1;
  3906. /* reset tstorm and ustorm per client statistics */
  3907. if (cli < MAX_STAT_COUNTER_ID) {
  3908. val = BAR_TSTRORM_INTMEM +
  3909. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3910. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3911. CNIC_WR(dev, val + i * 4, 0);
  3912. val = BAR_USTRORM_INTMEM +
  3913. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3914. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3915. CNIC_WR(dev, val + i * 4, 0);
  3916. }
  3917. cp->rx_cons_ptr =
  3918. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3919. cp->rx_cons = *cp->rx_cons_ptr;
  3920. }
  3921. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3922. {
  3923. struct cnic_local *cp = dev->cnic_priv;
  3924. u32 pfid = cp->pfid;
  3925. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3926. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3927. cp->kcq1.sw_prod_idx = 0;
  3928. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3929. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3930. cp->kcq1.hw_prod_idx_ptr =
  3931. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3932. cp->kcq1.status_idx_ptr =
  3933. &sb->sb.running_index[SM_RX_ID];
  3934. } else {
  3935. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3936. cp->kcq1.hw_prod_idx_ptr =
  3937. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3938. cp->kcq1.status_idx_ptr =
  3939. &sb->sb.running_index[SM_RX_ID];
  3940. }
  3941. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3942. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3943. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3944. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3945. cp->kcq2.sw_prod_idx = 0;
  3946. cp->kcq2.hw_prod_idx_ptr =
  3947. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3948. cp->kcq2.status_idx_ptr =
  3949. &sb->sb.running_index[SM_RX_ID];
  3950. }
  3951. }
  3952. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3953. {
  3954. struct cnic_local *cp = dev->cnic_priv;
  3955. struct cnic_eth_dev *ethdev = cp->ethdev;
  3956. int func = CNIC_FUNC(cp), ret, i;
  3957. u32 pfid;
  3958. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3959. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3960. if (!(val & 1))
  3961. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3962. else
  3963. val = (val >> 1) & 1;
  3964. if (val)
  3965. cp->pfid = func >> 1;
  3966. else
  3967. cp->pfid = func & 0x6;
  3968. } else {
  3969. cp->pfid = func;
  3970. }
  3971. pfid = cp->pfid;
  3972. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3973. cp->iscsi_start_cid, 0);
  3974. if (ret)
  3975. return -ENOMEM;
  3976. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3977. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3978. BNX2X_FCOE_NUM_CONNECTIONS,
  3979. cp->fcoe_start_cid, 0);
  3980. if (ret)
  3981. return -ENOMEM;
  3982. }
  3983. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3984. cnic_init_bnx2x_kcq(dev);
  3985. /* Only 1 EQ */
  3986. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3987. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3988. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3989. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3990. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3991. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3992. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3993. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3994. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3995. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3996. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3997. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3998. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3999. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4000. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4001. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4002. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4003. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4004. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4005. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4006. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4007. HC_INDEX_ISCSI_EQ_CONS);
  4008. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  4009. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4010. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  4011. cp->conn_buf_info.pgtbl[2 * i]);
  4012. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4013. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  4014. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  4015. }
  4016. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4017. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4018. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4019. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4020. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4021. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4022. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4023. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4024. cnic_setup_bnx2x_context(dev);
  4025. ret = cnic_init_bnx2x_irq(dev);
  4026. if (ret)
  4027. return ret;
  4028. return 0;
  4029. }
  4030. static void cnic_init_rings(struct cnic_dev *dev)
  4031. {
  4032. struct cnic_local *cp = dev->cnic_priv;
  4033. struct cnic_uio_dev *udev = cp->udev;
  4034. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4035. return;
  4036. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4037. cnic_init_bnx2_tx_ring(dev);
  4038. cnic_init_bnx2_rx_ring(dev);
  4039. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4040. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4041. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4042. u32 cid = cp->ethdev->iscsi_l2_cid;
  4043. u32 cl_qzone_id;
  4044. struct client_init_ramrod_data *data;
  4045. union l5cm_specific_data l5_data;
  4046. struct ustorm_eth_rx_producers rx_prods = {0};
  4047. u32 off, i;
  4048. rx_prods.bd_prod = 0;
  4049. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4050. barrier();
  4051. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4052. off = BAR_USTRORM_INTMEM +
  4053. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4054. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4055. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4056. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4057. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4058. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4059. data = udev->l2_buf;
  4060. memset(data, 0, sizeof(*data));
  4061. cnic_init_bnx2x_tx_ring(dev, data);
  4062. cnic_init_bnx2x_rx_ring(dev, data);
  4063. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4064. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4065. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4066. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4067. cid, ETH_CONNECTION_TYPE, &l5_data);
  4068. i = 0;
  4069. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4070. ++i < 10)
  4071. msleep(1);
  4072. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4073. netdev_err(dev->netdev,
  4074. "iSCSI CLIENT_SETUP did not complete\n");
  4075. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4076. cnic_ring_ctl(dev, cid, cli, 1);
  4077. }
  4078. }
  4079. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4080. {
  4081. struct cnic_local *cp = dev->cnic_priv;
  4082. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4083. return;
  4084. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4085. cnic_shutdown_bnx2_rx_ring(dev);
  4086. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4087. struct cnic_local *cp = dev->cnic_priv;
  4088. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4089. u32 cid = cp->ethdev->iscsi_l2_cid;
  4090. union l5cm_specific_data l5_data;
  4091. int i;
  4092. cnic_ring_ctl(dev, cid, cli, 0);
  4093. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4094. l5_data.phy_address.lo = cli;
  4095. l5_data.phy_address.hi = 0;
  4096. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4097. cid, ETH_CONNECTION_TYPE, &l5_data);
  4098. i = 0;
  4099. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4100. ++i < 10)
  4101. msleep(1);
  4102. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4103. netdev_err(dev->netdev,
  4104. "iSCSI CLIENT_HALT did not complete\n");
  4105. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4106. memset(&l5_data, 0, sizeof(l5_data));
  4107. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4108. cid, NONE_CONNECTION_TYPE, &l5_data);
  4109. msleep(10);
  4110. }
  4111. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4112. }
  4113. static int cnic_register_netdev(struct cnic_dev *dev)
  4114. {
  4115. struct cnic_local *cp = dev->cnic_priv;
  4116. struct cnic_eth_dev *ethdev = cp->ethdev;
  4117. int err;
  4118. if (!ethdev)
  4119. return -ENODEV;
  4120. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4121. return 0;
  4122. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4123. if (err)
  4124. netdev_err(dev->netdev, "register_cnic failed\n");
  4125. return err;
  4126. }
  4127. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4128. {
  4129. struct cnic_local *cp = dev->cnic_priv;
  4130. struct cnic_eth_dev *ethdev = cp->ethdev;
  4131. if (!ethdev)
  4132. return;
  4133. ethdev->drv_unregister_cnic(dev->netdev);
  4134. }
  4135. static int cnic_start_hw(struct cnic_dev *dev)
  4136. {
  4137. struct cnic_local *cp = dev->cnic_priv;
  4138. struct cnic_eth_dev *ethdev = cp->ethdev;
  4139. int err;
  4140. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4141. return -EALREADY;
  4142. dev->regview = ethdev->io_base;
  4143. pci_dev_get(dev->pcidev);
  4144. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4145. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4146. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4147. err = cp->alloc_resc(dev);
  4148. if (err) {
  4149. netdev_err(dev->netdev, "allocate resource failure\n");
  4150. goto err1;
  4151. }
  4152. err = cp->start_hw(dev);
  4153. if (err)
  4154. goto err1;
  4155. err = cnic_cm_open(dev);
  4156. if (err)
  4157. goto err1;
  4158. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4159. cp->enable_int(dev);
  4160. return 0;
  4161. err1:
  4162. cp->free_resc(dev);
  4163. pci_dev_put(dev->pcidev);
  4164. return err;
  4165. }
  4166. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4167. {
  4168. cnic_disable_bnx2_int_sync(dev);
  4169. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4170. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4171. cnic_init_context(dev, KWQ_CID);
  4172. cnic_init_context(dev, KCQ_CID);
  4173. cnic_setup_5709_context(dev, 0);
  4174. cnic_free_irq(dev);
  4175. cnic_free_resc(dev);
  4176. }
  4177. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4178. {
  4179. struct cnic_local *cp = dev->cnic_priv;
  4180. cnic_free_irq(dev);
  4181. *cp->kcq1.hw_prod_idx_ptr = 0;
  4182. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4183. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4184. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4185. cnic_free_resc(dev);
  4186. }
  4187. static void cnic_stop_hw(struct cnic_dev *dev)
  4188. {
  4189. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4190. struct cnic_local *cp = dev->cnic_priv;
  4191. int i = 0;
  4192. /* Need to wait for the ring shutdown event to complete
  4193. * before clearing the CNIC_UP flag.
  4194. */
  4195. while (cp->udev->uio_dev != -1 && i < 15) {
  4196. msleep(100);
  4197. i++;
  4198. }
  4199. cnic_shutdown_rings(dev);
  4200. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4201. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4202. synchronize_rcu();
  4203. cnic_cm_shutdown(dev);
  4204. cp->stop_hw(dev);
  4205. pci_dev_put(dev->pcidev);
  4206. }
  4207. }
  4208. static void cnic_free_dev(struct cnic_dev *dev)
  4209. {
  4210. int i = 0;
  4211. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4212. msleep(100);
  4213. i++;
  4214. }
  4215. if (atomic_read(&dev->ref_count) != 0)
  4216. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4217. netdev_info(dev->netdev, "Removed CNIC device\n");
  4218. dev_put(dev->netdev);
  4219. kfree(dev);
  4220. }
  4221. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4222. struct pci_dev *pdev)
  4223. {
  4224. struct cnic_dev *cdev;
  4225. struct cnic_local *cp;
  4226. int alloc_size;
  4227. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4228. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4229. if (cdev == NULL) {
  4230. netdev_err(dev, "allocate dev struct failure\n");
  4231. return NULL;
  4232. }
  4233. cdev->netdev = dev;
  4234. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4235. cdev->register_device = cnic_register_device;
  4236. cdev->unregister_device = cnic_unregister_device;
  4237. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4238. cp = cdev->cnic_priv;
  4239. cp->dev = cdev;
  4240. cp->l2_single_buf_size = 0x400;
  4241. cp->l2_rx_ring_size = 3;
  4242. spin_lock_init(&cp->cnic_ulp_lock);
  4243. netdev_info(dev, "Added CNIC device\n");
  4244. return cdev;
  4245. }
  4246. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4247. {
  4248. struct pci_dev *pdev;
  4249. struct cnic_dev *cdev;
  4250. struct cnic_local *cp;
  4251. struct cnic_eth_dev *ethdev = NULL;
  4252. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4253. probe = symbol_get(bnx2_cnic_probe);
  4254. if (probe) {
  4255. ethdev = (*probe)(dev);
  4256. symbol_put(bnx2_cnic_probe);
  4257. }
  4258. if (!ethdev)
  4259. return NULL;
  4260. pdev = ethdev->pdev;
  4261. if (!pdev)
  4262. return NULL;
  4263. dev_hold(dev);
  4264. pci_dev_get(pdev);
  4265. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4266. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4267. (pdev->revision < 0x10)) {
  4268. pci_dev_put(pdev);
  4269. goto cnic_err;
  4270. }
  4271. pci_dev_put(pdev);
  4272. cdev = cnic_alloc_dev(dev, pdev);
  4273. if (cdev == NULL)
  4274. goto cnic_err;
  4275. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4276. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4277. cp = cdev->cnic_priv;
  4278. cp->ethdev = ethdev;
  4279. cdev->pcidev = pdev;
  4280. cp->chip_id = ethdev->chip_id;
  4281. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4282. cp->cnic_ops = &cnic_bnx2_ops;
  4283. cp->start_hw = cnic_start_bnx2_hw;
  4284. cp->stop_hw = cnic_stop_bnx2_hw;
  4285. cp->setup_pgtbl = cnic_setup_page_tbl;
  4286. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4287. cp->free_resc = cnic_free_resc;
  4288. cp->start_cm = cnic_cm_init_bnx2_hw;
  4289. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4290. cp->enable_int = cnic_enable_bnx2_int;
  4291. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4292. cp->close_conn = cnic_close_bnx2_conn;
  4293. cp->next_idx = cnic_bnx2_next_idx;
  4294. cp->hw_idx = cnic_bnx2_hw_idx;
  4295. return cdev;
  4296. cnic_err:
  4297. dev_put(dev);
  4298. return NULL;
  4299. }
  4300. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4301. {
  4302. struct pci_dev *pdev;
  4303. struct cnic_dev *cdev;
  4304. struct cnic_local *cp;
  4305. struct cnic_eth_dev *ethdev = NULL;
  4306. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4307. probe = symbol_get(bnx2x_cnic_probe);
  4308. if (probe) {
  4309. ethdev = (*probe)(dev);
  4310. symbol_put(bnx2x_cnic_probe);
  4311. }
  4312. if (!ethdev)
  4313. return NULL;
  4314. pdev = ethdev->pdev;
  4315. if (!pdev)
  4316. return NULL;
  4317. dev_hold(dev);
  4318. cdev = cnic_alloc_dev(dev, pdev);
  4319. if (cdev == NULL) {
  4320. dev_put(dev);
  4321. return NULL;
  4322. }
  4323. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4324. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4325. cp = cdev->cnic_priv;
  4326. cp->ethdev = ethdev;
  4327. cdev->pcidev = pdev;
  4328. cp->chip_id = ethdev->chip_id;
  4329. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4330. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4331. if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
  4332. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4333. cdev->max_fcoe_conn = ethdev-