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/drivers/net/cassini.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 5304 lines | 3807 code | 715 blank | 782 comment | 712 complexity | 721c6ff0c6b6841be5c326fb80e861ca MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
  2. *
  3. * Copyright (C) 2004 Sun Microsystems Inc.
  4. * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  19. * 02111-1307, USA.
  20. *
  21. * This driver uses the sungem driver (c) David Miller
  22. * (davem@redhat.com) as its basis.
  23. *
  24. * The cassini chip has a number of features that distinguish it from
  25. * the gem chip:
  26. * 4 transmit descriptor rings that are used for either QoS (VLAN) or
  27. * load balancing (non-VLAN mode)
  28. * batching of multiple packets
  29. * multiple CPU dispatching
  30. * page-based RX descriptor engine with separate completion rings
  31. * Gigabit support (GMII and PCS interface)
  32. * MIF link up/down detection works
  33. *
  34. * RX is handled by page sized buffers that are attached as fragments to
  35. * the skb. here's what's done:
  36. * -- driver allocates pages at a time and keeps reference counts
  37. * on them.
  38. * -- the upper protocol layers assume that the header is in the skb
  39. * itself. as a result, cassini will copy a small amount (64 bytes)
  40. * to make them happy.
  41. * -- driver appends the rest of the data pages as frags to skbuffs
  42. * and increments the reference count
  43. * -- on page reclamation, the driver swaps the page with a spare page.
  44. * if that page is still in use, it frees its reference to that page,
  45. * and allocates a new page for use. otherwise, it just recycles the
  46. * the page.
  47. *
  48. * NOTE: cassini can parse the header. however, it's not worth it
  49. * as long as the network stack requires a header copy.
  50. *
  51. * TX has 4 queues. currently these queues are used in a round-robin
  52. * fashion for load balancing. They can also be used for QoS. for that
  53. * to work, however, QoS information needs to be exposed down to the driver
  54. * level so that subqueues get targeted to particular transmit rings.
  55. * alternatively, the queues can be configured via use of the all-purpose
  56. * ioctl.
  57. *
  58. * RX DATA: the rx completion ring has all the info, but the rx desc
  59. * ring has all of the data. RX can conceivably come in under multiple
  60. * interrupts, but the INT# assignment needs to be set up properly by
  61. * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
  62. * that. also, the two descriptor rings are designed to distinguish between
  63. * encrypted and non-encrypted packets, but we use them for buffering
  64. * instead.
  65. *
  66. * by default, the selective clear mask is set up to process rx packets.
  67. */
  68. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  69. #include <linux/module.h>
  70. #include <linux/kernel.h>
  71. #include <linux/types.h>
  72. #include <linux/compiler.h>
  73. #include <linux/slab.h>
  74. #include <linux/delay.h>
  75. #include <linux/init.h>
  76. #include <linux/vmalloc.h>
  77. #include <linux/ioport.h>
  78. #include <linux/pci.h>
  79. #include <linux/mm.h>
  80. #include <linux/highmem.h>
  81. #include <linux/list.h>
  82. #include <linux/dma-mapping.h>
  83. #include <linux/netdevice.h>
  84. #include <linux/etherdevice.h>
  85. #include <linux/skbuff.h>
  86. #include <linux/ethtool.h>
  87. #include <linux/crc32.h>
  88. #include <linux/random.h>
  89. #include <linux/mii.h>
  90. #include <linux/ip.h>
  91. #include <linux/tcp.h>
  92. #include <linux/mutex.h>
  93. #include <linux/firmware.h>
  94. #include <net/checksum.h>
  95. #include <asm/atomic.h>
  96. #include <asm/system.h>
  97. #include <asm/io.h>
  98. #include <asm/byteorder.h>
  99. #include <asm/uaccess.h>
  100. #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
  101. #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
  102. #define CAS_NCPUS num_online_cpus()
  103. #define cas_skb_release(x) netif_rx(x)
  104. /* select which firmware to use */
  105. #define USE_HP_WORKAROUND
  106. #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
  107. #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
  108. #include "cassini.h"
  109. #define USE_TX_COMPWB /* use completion writeback registers */
  110. #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
  111. #define USE_RX_BLANK /* hw interrupt mitigation */
  112. #undef USE_ENTROPY_DEV /* don't test for entropy device */
  113. /* NOTE: these aren't useable unless PCI interrupts can be assigned.
  114. * also, we need to make cp->lock finer-grained.
  115. */
  116. #undef USE_PCI_INTB
  117. #undef USE_PCI_INTC
  118. #undef USE_PCI_INTD
  119. #undef USE_QOS
  120. #undef USE_VPD_DEBUG /* debug vpd information if defined */
  121. /* rx processing options */
  122. #define USE_PAGE_ORDER /* specify to allocate large rx pages */
  123. #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
  124. #define RX_COPY_ALWAYS 0 /* if 0, use frags */
  125. #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
  126. #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
  127. #define DRV_MODULE_NAME "cassini"
  128. #define DRV_MODULE_VERSION "1.6"
  129. #define DRV_MODULE_RELDATE "21 May 2008"
  130. #define CAS_DEF_MSG_ENABLE \
  131. (NETIF_MSG_DRV | \
  132. NETIF_MSG_PROBE | \
  133. NETIF_MSG_LINK | \
  134. NETIF_MSG_TIMER | \
  135. NETIF_MSG_IFDOWN | \
  136. NETIF_MSG_IFUP | \
  137. NETIF_MSG_RX_ERR | \
  138. NETIF_MSG_TX_ERR)
  139. /* length of time before we decide the hardware is borked,
  140. * and dev->tx_timeout() should be called to fix the problem
  141. */
  142. #define CAS_TX_TIMEOUT (HZ)
  143. #define CAS_LINK_TIMEOUT (22*HZ/10)
  144. #define CAS_LINK_FAST_TIMEOUT (1)
  145. /* timeout values for state changing. these specify the number
  146. * of 10us delays to be used before giving up.
  147. */
  148. #define STOP_TRIES_PHY 1000
  149. #define STOP_TRIES 5000
  150. /* specify a minimum frame size to deal with some fifo issues
  151. * max mtu == 2 * page size - ethernet header - 64 - swivel =
  152. * 2 * page_size - 0x50
  153. */
  154. #define CAS_MIN_FRAME 97
  155. #define CAS_1000MB_MIN_FRAME 255
  156. #define CAS_MIN_MTU 60
  157. #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
  158. #if 1
  159. /*
  160. * Eliminate these and use separate atomic counters for each, to
  161. * avoid a race condition.
  162. */
  163. #else
  164. #define CAS_RESET_MTU 1
  165. #define CAS_RESET_ALL 2
  166. #define CAS_RESET_SPARE 3
  167. #endif
  168. static char version[] __devinitdata =
  169. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  170. static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
  171. static int link_mode;
  172. MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
  173. MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
  174. MODULE_LICENSE("GPL");
  175. MODULE_FIRMWARE("sun/cassini.bin");
  176. module_param(cassini_debug, int, 0);
  177. MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
  178. module_param(link_mode, int, 0);
  179. MODULE_PARM_DESC(link_mode, "default link mode");
  180. /*
  181. * Work around for a PCS bug in which the link goes down due to the chip
  182. * being confused and never showing a link status of "up."
  183. */
  184. #define DEFAULT_LINKDOWN_TIMEOUT 5
  185. /*
  186. * Value in seconds, for user input.
  187. */
  188. static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
  189. module_param(linkdown_timeout, int, 0);
  190. MODULE_PARM_DESC(linkdown_timeout,
  191. "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
  192. /*
  193. * value in 'ticks' (units used by jiffies). Set when we init the
  194. * module because 'HZ' in actually a function call on some flavors of
  195. * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
  196. */
  197. static int link_transition_timeout;
  198. static u16 link_modes[] __devinitdata = {
  199. BMCR_ANENABLE, /* 0 : autoneg */
  200. 0, /* 1 : 10bt half duplex */
  201. BMCR_SPEED100, /* 2 : 100bt half duplex */
  202. BMCR_FULLDPLX, /* 3 : 10bt full duplex */
  203. BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
  204. CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
  205. };
  206. static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
  207. { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
  208. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  209. { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
  210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  211. { 0, }
  212. };
  213. MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
  214. static void cas_set_link_modes(struct cas *cp);
  215. static inline void cas_lock_tx(struct cas *cp)
  216. {
  217. int i;
  218. for (i = 0; i < N_TX_RINGS; i++)
  219. spin_lock(&cp->tx_lock[i]);
  220. }
  221. static inline void cas_lock_all(struct cas *cp)
  222. {
  223. spin_lock_irq(&cp->lock);
  224. cas_lock_tx(cp);
  225. }
  226. /* WTZ: QA was finding deadlock problems with the previous
  227. * versions after long test runs with multiple cards per machine.
  228. * See if replacing cas_lock_all with safer versions helps. The
  229. * symptoms QA is reporting match those we'd expect if interrupts
  230. * aren't being properly restored, and we fixed a previous deadlock
  231. * with similar symptoms by using save/restore versions in other
  232. * places.
  233. */
  234. #define cas_lock_all_save(cp, flags) \
  235. do { \
  236. struct cas *xxxcp = (cp); \
  237. spin_lock_irqsave(&xxxcp->lock, flags); \
  238. cas_lock_tx(xxxcp); \
  239. } while (0)
  240. static inline void cas_unlock_tx(struct cas *cp)
  241. {
  242. int i;
  243. for (i = N_TX_RINGS; i > 0; i--)
  244. spin_unlock(&cp->tx_lock[i - 1]);
  245. }
  246. static inline void cas_unlock_all(struct cas *cp)
  247. {
  248. cas_unlock_tx(cp);
  249. spin_unlock_irq(&cp->lock);
  250. }
  251. #define cas_unlock_all_restore(cp, flags) \
  252. do { \
  253. struct cas *xxxcp = (cp); \
  254. cas_unlock_tx(xxxcp); \
  255. spin_unlock_irqrestore(&xxxcp->lock, flags); \
  256. } while (0)
  257. static void cas_disable_irq(struct cas *cp, const int ring)
  258. {
  259. /* Make sure we won't get any more interrupts */
  260. if (ring == 0) {
  261. writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
  262. return;
  263. }
  264. /* disable completion interrupts and selectively mask */
  265. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  266. switch (ring) {
  267. #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  268. #ifdef USE_PCI_INTB
  269. case 1:
  270. #endif
  271. #ifdef USE_PCI_INTC
  272. case 2:
  273. #endif
  274. #ifdef USE_PCI_INTD
  275. case 3:
  276. #endif
  277. writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
  278. cp->regs + REG_PLUS_INTRN_MASK(ring));
  279. break;
  280. #endif
  281. default:
  282. writel(INTRN_MASK_CLEAR_ALL, cp->regs +
  283. REG_PLUS_INTRN_MASK(ring));
  284. break;
  285. }
  286. }
  287. }
  288. static inline void cas_mask_intr(struct cas *cp)
  289. {
  290. int i;
  291. for (i = 0; i < N_RX_COMP_RINGS; i++)
  292. cas_disable_irq(cp, i);
  293. }
  294. static void cas_enable_irq(struct cas *cp, const int ring)
  295. {
  296. if (ring == 0) { /* all but TX_DONE */
  297. writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
  298. return;
  299. }
  300. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  301. switch (ring) {
  302. #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  303. #ifdef USE_PCI_INTB
  304. case 1:
  305. #endif
  306. #ifdef USE_PCI_INTC
  307. case 2:
  308. #endif
  309. #ifdef USE_PCI_INTD
  310. case 3:
  311. #endif
  312. writel(INTRN_MASK_RX_EN, cp->regs +
  313. REG_PLUS_INTRN_MASK(ring));
  314. break;
  315. #endif
  316. default:
  317. break;
  318. }
  319. }
  320. }
  321. static inline void cas_unmask_intr(struct cas *cp)
  322. {
  323. int i;
  324. for (i = 0; i < N_RX_COMP_RINGS; i++)
  325. cas_enable_irq(cp, i);
  326. }
  327. static inline void cas_entropy_gather(struct cas *cp)
  328. {
  329. #ifdef USE_ENTROPY_DEV
  330. if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
  331. return;
  332. batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
  333. readl(cp->regs + REG_ENTROPY_IV),
  334. sizeof(uint64_t)*8);
  335. #endif
  336. }
  337. static inline void cas_entropy_reset(struct cas *cp)
  338. {
  339. #ifdef USE_ENTROPY_DEV
  340. if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
  341. return;
  342. writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
  343. cp->regs + REG_BIM_LOCAL_DEV_EN);
  344. writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
  345. writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
  346. /* if we read back 0x0, we don't have an entropy device */
  347. if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
  348. cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
  349. #endif
  350. }
  351. /* access to the phy. the following assumes that we've initialized the MIF to
  352. * be in frame rather than bit-bang mode
  353. */
  354. static u16 cas_phy_read(struct cas *cp, int reg)
  355. {
  356. u32 cmd;
  357. int limit = STOP_TRIES_PHY;
  358. cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
  359. cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
  360. cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
  361. cmd |= MIF_FRAME_TURN_AROUND_MSB;
  362. writel(cmd, cp->regs + REG_MIF_FRAME);
  363. /* poll for completion */
  364. while (limit-- > 0) {
  365. udelay(10);
  366. cmd = readl(cp->regs + REG_MIF_FRAME);
  367. if (cmd & MIF_FRAME_TURN_AROUND_LSB)
  368. return cmd & MIF_FRAME_DATA_MASK;
  369. }
  370. return 0xFFFF; /* -1 */
  371. }
  372. static int cas_phy_write(struct cas *cp, int reg, u16 val)
  373. {
  374. int limit = STOP_TRIES_PHY;
  375. u32 cmd;
  376. cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
  377. cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
  378. cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
  379. cmd |= MIF_FRAME_TURN_AROUND_MSB;
  380. cmd |= val & MIF_FRAME_DATA_MASK;
  381. writel(cmd, cp->regs + REG_MIF_FRAME);
  382. /* poll for completion */
  383. while (limit-- > 0) {
  384. udelay(10);
  385. cmd = readl(cp->regs + REG_MIF_FRAME);
  386. if (cmd & MIF_FRAME_TURN_AROUND_LSB)
  387. return 0;
  388. }
  389. return -1;
  390. }
  391. static void cas_phy_powerup(struct cas *cp)
  392. {
  393. u16 ctl = cas_phy_read(cp, MII_BMCR);
  394. if ((ctl & BMCR_PDOWN) == 0)
  395. return;
  396. ctl &= ~BMCR_PDOWN;
  397. cas_phy_write(cp, MII_BMCR, ctl);
  398. }
  399. static void cas_phy_powerdown(struct cas *cp)
  400. {
  401. u16 ctl = cas_phy_read(cp, MII_BMCR);
  402. if (ctl & BMCR_PDOWN)
  403. return;
  404. ctl |= BMCR_PDOWN;
  405. cas_phy_write(cp, MII_BMCR, ctl);
  406. }
  407. /* cp->lock held. note: the last put_page will free the buffer */
  408. static int cas_page_free(struct cas *cp, cas_page_t *page)
  409. {
  410. pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
  411. PCI_DMA_FROMDEVICE);
  412. __free_pages(page->buffer, cp->page_order);
  413. kfree(page);
  414. return 0;
  415. }
  416. #ifdef RX_COUNT_BUFFERS
  417. #define RX_USED_ADD(x, y) ((x)->used += (y))
  418. #define RX_USED_SET(x, y) ((x)->used = (y))
  419. #else
  420. #define RX_USED_ADD(x, y)
  421. #define RX_USED_SET(x, y)
  422. #endif
  423. /* local page allocation routines for the receive buffers. jumbo pages
  424. * require at least 8K contiguous and 8K aligned buffers.
  425. */
  426. static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
  427. {
  428. cas_page_t *page;
  429. page = kmalloc(sizeof(cas_page_t), flags);
  430. if (!page)
  431. return NULL;
  432. INIT_LIST_HEAD(&page->list);
  433. RX_USED_SET(page, 0);
  434. page->buffer = alloc_pages(flags, cp->page_order);
  435. if (!page->buffer)
  436. goto page_err;
  437. page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
  438. cp->page_size, PCI_DMA_FROMDEVICE);
  439. return page;
  440. page_err:
  441. kfree(page);
  442. return NULL;
  443. }
  444. /* initialize spare pool of rx buffers, but allocate during the open */
  445. static void cas_spare_init(struct cas *cp)
  446. {
  447. spin_lock(&cp->rx_inuse_lock);
  448. INIT_LIST_HEAD(&cp->rx_inuse_list);
  449. spin_unlock(&cp->rx_inuse_lock);
  450. spin_lock(&cp->rx_spare_lock);
  451. INIT_LIST_HEAD(&cp->rx_spare_list);
  452. cp->rx_spares_needed = RX_SPARE_COUNT;
  453. spin_unlock(&cp->rx_spare_lock);
  454. }
  455. /* used on close. free all the spare buffers. */
  456. static void cas_spare_free(struct cas *cp)
  457. {
  458. struct list_head list, *elem, *tmp;
  459. /* free spare buffers */
  460. INIT_LIST_HEAD(&list);
  461. spin_lock(&cp->rx_spare_lock);
  462. list_splice_init(&cp->rx_spare_list, &list);
  463. spin_unlock(&cp->rx_spare_lock);
  464. list_for_each_safe(elem, tmp, &list) {
  465. cas_page_free(cp, list_entry(elem, cas_page_t, list));
  466. }
  467. INIT_LIST_HEAD(&list);
  468. #if 1
  469. /*
  470. * Looks like Adrian had protected this with a different
  471. * lock than used everywhere else to manipulate this list.
  472. */
  473. spin_lock(&cp->rx_inuse_lock);
  474. list_splice_init(&cp->rx_inuse_list, &list);
  475. spin_unlock(&cp->rx_inuse_lock);
  476. #else
  477. spin_lock(&cp->rx_spare_lock);
  478. list_splice_init(&cp->rx_inuse_list, &list);
  479. spin_unlock(&cp->rx_spare_lock);
  480. #endif
  481. list_for_each_safe(elem, tmp, &list) {
  482. cas_page_free(cp, list_entry(elem, cas_page_t, list));
  483. }
  484. }
  485. /* replenish spares if needed */
  486. static void cas_spare_recover(struct cas *cp, const gfp_t flags)
  487. {
  488. struct list_head list, *elem, *tmp;
  489. int needed, i;
  490. /* check inuse list. if we don't need any more free buffers,
  491. * just free it
  492. */
  493. /* make a local copy of the list */
  494. INIT_LIST_HEAD(&list);
  495. spin_lock(&cp->rx_inuse_lock);
  496. list_splice_init(&cp->rx_inuse_list, &list);
  497. spin_unlock(&cp->rx_inuse_lock);
  498. list_for_each_safe(elem, tmp, &list) {
  499. cas_page_t *page = list_entry(elem, cas_page_t, list);
  500. /*
  501. * With the lockless pagecache, cassini buffering scheme gets
  502. * slightly less accurate: we might find that a page has an
  503. * elevated reference count here, due to a speculative ref,
  504. * and skip it as in-use. Ideally we would be able to reclaim
  505. * it. However this would be such a rare case, it doesn't
  506. * matter too much as we should pick it up the next time round.
  507. *
  508. * Importantly, if we find that the page has a refcount of 1
  509. * here (our refcount), then we know it is definitely not inuse
  510. * so we can reuse it.
  511. */
  512. if (page_count(page->buffer) > 1)
  513. continue;
  514. list_del(elem);
  515. spin_lock(&cp->rx_spare_lock);
  516. if (cp->rx_spares_needed > 0) {
  517. list_add(elem, &cp->rx_spare_list);
  518. cp->rx_spares_needed--;
  519. spin_unlock(&cp->rx_spare_lock);
  520. } else {
  521. spin_unlock(&cp->rx_spare_lock);
  522. cas_page_free(cp, page);
  523. }
  524. }
  525. /* put any inuse buffers back on the list */
  526. if (!list_empty(&list)) {
  527. spin_lock(&cp->rx_inuse_lock);
  528. list_splice(&list, &cp->rx_inuse_list);
  529. spin_unlock(&cp->rx_inuse_lock);
  530. }
  531. spin_lock(&cp->rx_spare_lock);
  532. needed = cp->rx_spares_needed;
  533. spin_unlock(&cp->rx_spare_lock);
  534. if (!needed)
  535. return;
  536. /* we still need spares, so try to allocate some */
  537. INIT_LIST_HEAD(&list);
  538. i = 0;
  539. while (i < needed) {
  540. cas_page_t *spare = cas_page_alloc(cp, flags);
  541. if (!spare)
  542. break;
  543. list_add(&spare->list, &list);
  544. i++;
  545. }
  546. spin_lock(&cp->rx_spare_lock);
  547. list_splice(&list, &cp->rx_spare_list);
  548. cp->rx_spares_needed -= i;
  549. spin_unlock(&cp->rx_spare_lock);
  550. }
  551. /* pull a page from the list. */
  552. static cas_page_t *cas_page_dequeue(struct cas *cp)
  553. {
  554. struct list_head *entry;
  555. int recover;
  556. spin_lock(&cp->rx_spare_lock);
  557. if (list_empty(&cp->rx_spare_list)) {
  558. /* try to do a quick recovery */
  559. spin_unlock(&cp->rx_spare_lock);
  560. cas_spare_recover(cp, GFP_ATOMIC);
  561. spin_lock(&cp->rx_spare_lock);
  562. if (list_empty(&cp->rx_spare_list)) {
  563. netif_err(cp, rx_err, cp->dev,
  564. "no spare buffers available\n");
  565. spin_unlock(&cp->rx_spare_lock);
  566. return NULL;
  567. }
  568. }
  569. entry = cp->rx_spare_list.next;
  570. list_del(entry);
  571. recover = ++cp->rx_spares_needed;
  572. spin_unlock(&cp->rx_spare_lock);
  573. /* trigger the timer to do the recovery */
  574. if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
  575. #if 1
  576. atomic_inc(&cp->reset_task_pending);
  577. atomic_inc(&cp->reset_task_pending_spare);
  578. schedule_work(&cp->reset_task);
  579. #else
  580. atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
  581. schedule_work(&cp->reset_task);
  582. #endif
  583. }
  584. return list_entry(entry, cas_page_t, list);
  585. }
  586. static void cas_mif_poll(struct cas *cp, const int enable)
  587. {
  588. u32 cfg;
  589. cfg = readl(cp->regs + REG_MIF_CFG);
  590. cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
  591. if (cp->phy_type & CAS_PHY_MII_MDIO1)
  592. cfg |= MIF_CFG_PHY_SELECT;
  593. /* poll and interrupt on link status change. */
  594. if (enable) {
  595. cfg |= MIF_CFG_POLL_EN;
  596. cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
  597. cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
  598. }
  599. writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
  600. cp->regs + REG_MIF_MASK);
  601. writel(cfg, cp->regs + REG_MIF_CFG);
  602. }
  603. /* Must be invoked under cp->lock */
  604. static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
  605. {
  606. u16 ctl;
  607. #if 1
  608. int lcntl;
  609. int changed = 0;
  610. int oldstate = cp->lstate;
  611. int link_was_not_down = !(oldstate == link_down);
  612. #endif
  613. /* Setup link parameters */
  614. if (!ep)
  615. goto start_aneg;
  616. lcntl = cp->link_cntl;
  617. if (ep->autoneg == AUTONEG_ENABLE)
  618. cp->link_cntl = BMCR_ANENABLE;
  619. else {
  620. u32 speed = ethtool_cmd_speed(ep);
  621. cp->link_cntl = 0;
  622. if (speed == SPEED_100)
  623. cp->link_cntl |= BMCR_SPEED100;
  624. else if (speed == SPEED_1000)
  625. cp->link_cntl |= CAS_BMCR_SPEED1000;
  626. if (ep->duplex == DUPLEX_FULL)
  627. cp->link_cntl |= BMCR_FULLDPLX;
  628. }
  629. #if 1
  630. changed = (lcntl != cp->link_cntl);
  631. #endif
  632. start_aneg:
  633. if (cp->lstate == link_up) {
  634. netdev_info(cp->dev, "PCS link down\n");
  635. } else {
  636. if (changed) {
  637. netdev_info(cp->dev, "link configuration changed\n");
  638. }
  639. }
  640. cp->lstate = link_down;
  641. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  642. if (!cp->hw_running)
  643. return;
  644. #if 1
  645. /*
  646. * WTZ: If the old state was link_up, we turn off the carrier
  647. * to replicate everything we do elsewhere on a link-down
  648. * event when we were already in a link-up state..
  649. */
  650. if (oldstate == link_up)
  651. netif_carrier_off(cp->dev);
  652. if (changed && link_was_not_down) {
  653. /*
  654. * WTZ: This branch will simply schedule a full reset after
  655. * we explicitly changed link modes in an ioctl. See if this
  656. * fixes the link-problems we were having for forced mode.
  657. */
  658. atomic_inc(&cp->reset_task_pending);
  659. atomic_inc(&cp->reset_task_pending_all);
  660. schedule_work(&cp->reset_task);
  661. cp->timer_ticks = 0;
  662. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  663. return;
  664. }
  665. #endif
  666. if (cp->phy_type & CAS_PHY_SERDES) {
  667. u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
  668. if (cp->link_cntl & BMCR_ANENABLE) {
  669. val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
  670. cp->lstate = link_aneg;
  671. } else {
  672. if (cp->link_cntl & BMCR_FULLDPLX)
  673. val |= PCS_MII_CTRL_DUPLEX;
  674. val &= ~PCS_MII_AUTONEG_EN;
  675. cp->lstate = link_force_ok;
  676. }
  677. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  678. writel(val, cp->regs + REG_PCS_MII_CTRL);
  679. } else {
  680. cas_mif_poll(cp, 0);
  681. ctl = cas_phy_read(cp, MII_BMCR);
  682. ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
  683. CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
  684. ctl |= cp->link_cntl;
  685. if (ctl & BMCR_ANENABLE) {
  686. ctl |= BMCR_ANRESTART;
  687. cp->lstate = link_aneg;
  688. } else {
  689. cp->lstate = link_force_ok;
  690. }
  691. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  692. cas_phy_write(cp, MII_BMCR, ctl);
  693. cas_mif_poll(cp, 1);
  694. }
  695. cp->timer_ticks = 0;
  696. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  697. }
  698. /* Must be invoked under cp->lock. */
  699. static int cas_reset_mii_phy(struct cas *cp)
  700. {
  701. int limit = STOP_TRIES_PHY;
  702. u16 val;
  703. cas_phy_write(cp, MII_BMCR, BMCR_RESET);
  704. udelay(100);
  705. while (--limit) {
  706. val = cas_phy_read(cp, MII_BMCR);
  707. if ((val & BMCR_RESET) == 0)
  708. break;
  709. udelay(10);
  710. }
  711. return limit <= 0;
  712. }
  713. static int cas_saturn_firmware_init(struct cas *cp)
  714. {
  715. const struct firmware *fw;
  716. const char fw_name[] = "sun/cassini.bin";
  717. int err;
  718. if (PHY_NS_DP83065 != cp->phy_id)
  719. return 0;
  720. err = request_firmware(&fw, fw_name, &cp->pdev->dev);
  721. if (err) {
  722. pr_err("Failed to load firmware \"%s\"\n",
  723. fw_name);
  724. return err;
  725. }
  726. if (fw->size < 2) {
  727. pr_err("bogus length %zu in \"%s\"\n",
  728. fw->size, fw_name);
  729. err = -EINVAL;
  730. goto out;
  731. }
  732. cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
  733. cp->fw_size = fw->size - 2;
  734. cp->fw_data = vmalloc(cp->fw_size);
  735. if (!cp->fw_data) {
  736. err = -ENOMEM;
  737. pr_err("\"%s\" Failed %d\n", fw_name, err);
  738. goto out;
  739. }
  740. memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
  741. out:
  742. release_firmware(fw);
  743. return err;
  744. }
  745. static void cas_saturn_firmware_load(struct cas *cp)
  746. {
  747. int i;
  748. cas_phy_powerdown(cp);
  749. /* expanded memory access mode */
  750. cas_phy_write(cp, DP83065_MII_MEM, 0x0);
  751. /* pointer configuration for new firmware */
  752. cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
  753. cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
  754. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
  755. cas_phy_write(cp, DP83065_MII_REGD, 0x82);
  756. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
  757. cas_phy_write(cp, DP83065_MII_REGD, 0x0);
  758. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
  759. cas_phy_write(cp, DP83065_MII_REGD, 0x39);
  760. /* download new firmware */
  761. cas_phy_write(cp, DP83065_MII_MEM, 0x1);
  762. cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
  763. for (i = 0; i < cp->fw_size; i++)
  764. cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
  765. /* enable firmware */
  766. cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
  767. cas_phy_write(cp, DP83065_MII_REGD, 0x1);
  768. }
  769. /* phy initialization */
  770. static void cas_phy_init(struct cas *cp)
  771. {
  772. u16 val;
  773. /* if we're in MII/GMII mode, set up phy */
  774. if (CAS_PHY_MII(cp->phy_type)) {
  775. writel(PCS_DATAPATH_MODE_MII,
  776. cp->regs + REG_PCS_DATAPATH_MODE);
  777. cas_mif_poll(cp, 0);
  778. cas_reset_mii_phy(cp); /* take out of isolate mode */
  779. if (PHY_LUCENT_B0 == cp->phy_id) {
  780. /* workaround link up/down issue with lucent */
  781. cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
  782. cas_phy_write(cp, MII_BMCR, 0x00f1);
  783. cas_phy_write(cp, LUCENT_MII_REG, 0x0);
  784. } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
  785. /* workarounds for broadcom phy */
  786. cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
  787. cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
  788. cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
  789. cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
  790. cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
  791. cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
  792. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
  793. cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
  794. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
  795. cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
  796. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
  797. } else if (PHY_BROADCOM_5411 == cp->phy_id) {
  798. val = cas_phy_read(cp, BROADCOM_MII_REG4);
  799. val = cas_phy_read(cp, BROADCOM_MII_REG4);
  800. if (val & 0x0080) {
  801. /* link workaround */
  802. cas_phy_write(cp, BROADCOM_MII_REG4,
  803. val & ~0x0080);
  804. }
  805. } else if (cp->cas_flags & CAS_FLAG_SATURN) {
  806. writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
  807. SATURN_PCFG_FSI : 0x0,
  808. cp->regs + REG_SATURN_PCFG);
  809. /* load firmware to address 10Mbps auto-negotiation
  810. * issue. NOTE: this will need to be changed if the
  811. * default firmware gets fixed.
  812. */
  813. if (PHY_NS_DP83065 == cp->phy_id) {
  814. cas_saturn_firmware_load(cp);
  815. }
  816. cas_phy_powerup(cp);
  817. }
  818. /* advertise capabilities */
  819. val = cas_phy_read(cp, MII_BMCR);
  820. val &= ~BMCR_ANENABLE;
  821. cas_phy_write(cp, MII_BMCR, val);
  822. udelay(10);
  823. cas_phy_write(cp, MII_ADVERTISE,
  824. cas_phy_read(cp, MII_ADVERTISE) |
  825. (ADVERTISE_10HALF | ADVERTISE_10FULL |
  826. ADVERTISE_100HALF | ADVERTISE_100FULL |
  827. CAS_ADVERTISE_PAUSE |
  828. CAS_ADVERTISE_ASYM_PAUSE));
  829. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  830. /* make sure that we don't advertise half
  831. * duplex to avoid a chip issue
  832. */
  833. val = cas_phy_read(cp, CAS_MII_1000_CTRL);
  834. val &= ~CAS_ADVERTISE_1000HALF;
  835. val |= CAS_ADVERTISE_1000FULL;
  836. cas_phy_write(cp, CAS_MII_1000_CTRL, val);
  837. }
  838. } else {
  839. /* reset pcs for serdes */
  840. u32 val;
  841. int limit;
  842. writel(PCS_DATAPATH_MODE_SERDES,
  843. cp->regs + REG_PCS_DATAPATH_MODE);
  844. /* enable serdes pins on saturn */
  845. if (cp->cas_flags & CAS_FLAG_SATURN)
  846. writel(0, cp->regs + REG_SATURN_PCFG);
  847. /* Reset PCS unit. */
  848. val = readl(cp->regs + REG_PCS_MII_CTRL);
  849. val |= PCS_MII_RESET;
  850. writel(val, cp->regs + REG_PCS_MII_CTRL);
  851. limit = STOP_TRIES;
  852. while (--limit > 0) {
  853. udelay(10);
  854. if ((readl(cp->regs + REG_PCS_MII_CTRL) &
  855. PCS_MII_RESET) == 0)
  856. break;
  857. }
  858. if (limit <= 0)
  859. netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
  860. readl(cp->regs + REG_PCS_STATE_MACHINE));
  861. /* Make sure PCS is disabled while changing advertisement
  862. * configuration.
  863. */
  864. writel(0x0, cp->regs + REG_PCS_CFG);
  865. /* Advertise all capabilities except half-duplex. */
  866. val = readl(cp->regs + REG_PCS_MII_ADVERT);
  867. val &= ~PCS_MII_ADVERT_HD;
  868. val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
  869. PCS_MII_ADVERT_ASYM_PAUSE);
  870. writel(val, cp->regs + REG_PCS_MII_ADVERT);
  871. /* enable PCS */
  872. writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
  873. /* pcs workaround: enable sync detect */
  874. writel(PCS_SERDES_CTRL_SYNCD_EN,
  875. cp->regs + REG_PCS_SERDES_CTRL);
  876. }
  877. }
  878. static int cas_pcs_link_check(struct cas *cp)
  879. {
  880. u32 stat, state_machine;
  881. int retval = 0;
  882. /* The link status bit latches on zero, so you must
  883. * read it twice in such a case to see a transition
  884. * to the link being up.
  885. */
  886. stat = readl(cp->regs + REG_PCS_MII_STATUS);
  887. if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
  888. stat = readl(cp->regs + REG_PCS_MII_STATUS);
  889. /* The remote-fault indication is only valid
  890. * when autoneg has completed.
  891. */
  892. if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
  893. PCS_MII_STATUS_REMOTE_FAULT)) ==
  894. (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
  895. netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
  896. /* work around link detection issue by querying the PCS state
  897. * machine directly.
  898. */
  899. state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
  900. if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
  901. stat &= ~PCS_MII_STATUS_LINK_STATUS;
  902. } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
  903. stat |= PCS_MII_STATUS_LINK_STATUS;
  904. }
  905. if (stat & PCS_MII_STATUS_LINK_STATUS) {
  906. if (cp->lstate != link_up) {
  907. if (cp->opened) {
  908. cp->lstate = link_up;
  909. cp->link_transition = LINK_TRANSITION_LINK_UP;
  910. cas_set_link_modes(cp);
  911. netif_carrier_on(cp->dev);
  912. }
  913. }
  914. } else if (cp->lstate == link_up) {
  915. cp->lstate = link_down;
  916. if (link_transition_timeout != 0 &&
  917. cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
  918. !cp->link_transition_jiffies_valid) {
  919. /*
  920. * force a reset, as a workaround for the
  921. * link-failure problem. May want to move this to a
  922. * point a bit earlier in the sequence. If we had
  923. * generated a reset a short time ago, we'll wait for
  924. * the link timer to check the status until a
  925. * timer expires (link_transistion_jiffies_valid is
  926. * true when the timer is running.) Instead of using
  927. * a system timer, we just do a check whenever the
  928. * link timer is running - this clears the flag after
  929. * a suitable delay.
  930. */
  931. retval = 1;
  932. cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
  933. cp->link_transition_jiffies = jiffies;
  934. cp->link_transition_jiffies_valid = 1;
  935. } else {
  936. cp->link_transition = LINK_TRANSITION_ON_FAILURE;
  937. }
  938. netif_carrier_off(cp->dev);
  939. if (cp->opened)
  940. netif_info(cp, link, cp->dev, "PCS link down\n");
  941. /* Cassini only: if you force a mode, there can be
  942. * sync problems on link down. to fix that, the following
  943. * things need to be checked:
  944. * 1) read serialink state register
  945. * 2) read pcs status register to verify link down.
  946. * 3) if link down and serial link == 0x03, then you need
  947. * to global reset the chip.
  948. */
  949. if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
  950. /* should check to see if we're in a forced mode */
  951. stat = readl(cp->regs + REG_PCS_SERDES_STATE);
  952. if (stat == 0x03)
  953. return 1;
  954. }
  955. } else if (cp->lstate == link_down) {
  956. if (link_transition_timeout != 0 &&
  957. cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
  958. !cp->link_transition_jiffies_valid) {
  959. /* force a reset, as a workaround for the
  960. * link-failure problem. May want to move
  961. * this to a point a bit earlier in the
  962. * sequence.
  963. */
  964. retval = 1;
  965. cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
  966. cp->link_transition_jiffies = jiffies;
  967. cp->link_transition_jiffies_valid = 1;
  968. } else {
  969. cp->link_transition = LINK_TRANSITION_STILL_FAILED;
  970. }
  971. }
  972. return retval;
  973. }
  974. static int cas_pcs_interrupt(struct net_device *dev,
  975. struct cas *cp, u32 status)
  976. {
  977. u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
  978. if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
  979. return 0;
  980. return cas_pcs_link_check(cp);
  981. }
  982. static int cas_txmac_interrupt(struct net_device *dev,
  983. struct cas *cp, u32 status)
  984. {
  985. u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
  986. if (!txmac_stat)
  987. return 0;
  988. netif_printk(cp, intr, KERN_DEBUG, cp->dev,
  989. "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
  990. /* Defer timer expiration is quite normal,
  991. * don't even log the event.
  992. */
  993. if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
  994. !(txmac_stat & ~MAC_TX_DEFER_TIMER))
  995. return 0;
  996. spin_lock(&cp->stat_lock[0]);
  997. if (txmac_stat & MAC_TX_UNDERRUN) {
  998. netdev_err(dev, "TX MAC xmit underrun\n");
  999. cp->net_stats[0].tx_fifo_errors++;
  1000. }
  1001. if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
  1002. netdev_err(dev, "TX MAC max packet size error\n");
  1003. cp->net_stats[0].tx_errors++;
  1004. }
  1005. /* The rest are all cases of one of the 16-bit TX
  1006. * counters expiring.
  1007. */
  1008. if (txmac_stat & MAC_TX_COLL_NORMAL)
  1009. cp->net_stats[0].collisions += 0x10000;
  1010. if (txmac_stat & MAC_TX_COLL_EXCESS) {
  1011. cp->net_stats[0].tx_aborted_errors += 0x10000;
  1012. cp->net_stats[0].collisions += 0x10000;
  1013. }
  1014. if (txmac_stat & MAC_TX_COLL_LATE) {
  1015. cp->net_stats[0].tx_aborted_errors += 0x10000;
  1016. cp->net_stats[0].collisions += 0x10000;
  1017. }
  1018. spin_unlock(&cp->stat_lock[0]);
  1019. /* We do not keep track of MAC_TX_COLL_FIRST and
  1020. * MAC_TX_PEAK_ATTEMPTS events.
  1021. */
  1022. return 0;
  1023. }
  1024. static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
  1025. {
  1026. cas_hp_inst_t *inst;
  1027. u32 val;
  1028. int i;
  1029. i = 0;
  1030. while ((inst = firmware) && inst->note) {
  1031. writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
  1032. val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
  1033. val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
  1034. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
  1035. val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
  1036. val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
  1037. val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
  1038. val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
  1039. val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
  1040. val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
  1041. val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
  1042. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
  1043. val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
  1044. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
  1045. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
  1046. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
  1047. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
  1048. ++firmware;
  1049. ++i;
  1050. }
  1051. }
  1052. static void cas_init_rx_dma(struct cas *cp)
  1053. {
  1054. u64 desc_dma = cp->block_dvma;
  1055. u32 val;
  1056. int i, size;
  1057. /* rx free descriptors */
  1058. val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
  1059. val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
  1060. val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
  1061. if ((N_RX_DESC_RINGS > 1) &&
  1062. (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
  1063. val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
  1064. writel(val, cp->regs + REG_RX_CFG);
  1065. val = (unsigned long) cp->init_rxds[0] -
  1066. (unsigned long) cp->init_block;
  1067. writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
  1068. writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
  1069. writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
  1070. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1071. /* rx desc 2 is for IPSEC packets. however,
  1072. * we don't it that for that purpose.
  1073. */
  1074. val = (unsigned long) cp->init_rxds[1] -
  1075. (unsigned long) cp->init_block;
  1076. writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
  1077. writel((desc_dma + val) & 0xffffffff, cp->regs +
  1078. REG_PLUS_RX_DB1_LOW);
  1079. writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
  1080. REG_PLUS_RX_KICK1);
  1081. }
  1082. /* rx completion registers */
  1083. val = (unsigned long) cp->init_rxcs[0] -
  1084. (unsigned long) cp->init_block;
  1085. writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
  1086. writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
  1087. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1088. /* rx comp 2-4 */
  1089. for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
  1090. val = (unsigned long) cp->init_rxcs[i] -
  1091. (unsigned long) cp->init_block;
  1092. writel((desc_dma + val) >> 32, cp->regs +
  1093. REG_PLUS_RX_CBN_HI(i));
  1094. writel((desc_dma + val) & 0xffffffff, cp->regs +
  1095. REG_PLUS_RX_CBN_LOW(i));
  1096. }
  1097. }
  1098. /* read selective clear regs to prevent spurious interrupts
  1099. * on reset because complete == kick.
  1100. * selective clear set up to prevent interrupts on resets
  1101. */
  1102. readl(cp->regs + REG_INTR_STATUS_ALIAS);
  1103. writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
  1104. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1105. for (i = 1; i < N_RX_COMP_RINGS; i++)
  1106. readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
  1107. /* 2 is different from 3 and 4 */
  1108. if (N_RX_COMP_RINGS > 1)
  1109. writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
  1110. cp->regs + REG_PLUS_ALIASN_CLEAR(1));
  1111. for (i = 2; i < N_RX_COMP_RINGS; i++)
  1112. writel(INTR_RX_DONE_ALT,
  1113. cp->regs + REG_PLUS_ALIASN_CLEAR(i));
  1114. }
  1115. /* set up pause thresholds */
  1116. val = CAS_BASE(RX_PAUSE_THRESH_OFF,
  1117. cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
  1118. val |= CAS_BASE(RX_PAUSE_THRESH_ON,
  1119. cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
  1120. writel(val, cp->regs + REG_RX_PAUSE_THRESH);
  1121. /* zero out dma reassembly buffers */
  1122. for (i = 0; i < 64; i++) {
  1123. writel(i, cp->regs + REG_RX_TABLE_ADDR);
  1124. writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
  1125. writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
  1126. writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
  1127. }
  1128. /* make sure address register is 0 for normal operation */
  1129. writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
  1130. writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
  1131. /* interrupt mitigation */
  1132. #ifdef USE_RX_BLANK
  1133. val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
  1134. val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
  1135. writel(val, cp->regs + REG_RX_BLANK);
  1136. #else
  1137. writel(0x0, cp->regs + REG_RX_BLANK);
  1138. #endif
  1139. /* interrupt generation as a function of low water marks for
  1140. * free desc and completion entries. these are used to trigger
  1141. * housekeeping for rx descs. we don't use the free interrupt
  1142. * as it's not very useful
  1143. */
  1144. /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
  1145. val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
  1146. writel(val, cp->regs + REG_RX_AE_THRESH);
  1147. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1148. val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
  1149. writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
  1150. }
  1151. /* Random early detect registers. useful for congestion avoidance.
  1152. * this should be tunable.
  1153. */
  1154. writel(0x0, cp->regs + REG_RX_RED);
  1155. /* receive page sizes. default == 2K (0x800) */
  1156. val = 0;
  1157. if (cp->page_size == 0x1000)
  1158. val = 0x1;
  1159. else if (cp->page_size == 0x2000)
  1160. val = 0x2;
  1161. else if (cp->page_size == 0x4000)
  1162. val = 0x3;
  1163. /* round mtu + offset. constrain to page size. */
  1164. size = cp->dev->mtu + 64;
  1165. if (size > cp->page_size)
  1166. size = cp->page_size;
  1167. if (size <= 0x400)
  1168. i = 0x0;
  1169. else if (size <= 0x800)
  1170. i = 0x1;
  1171. else if (size <= 0x1000)
  1172. i = 0x2;
  1173. else
  1174. i = 0x3;
  1175. cp->mtu_stride = 1 << (i + 10);
  1176. val = CAS_BASE(RX_PAGE_SIZE, val);
  1177. val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
  1178. val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
  1179. val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
  1180. writel(val, cp->regs + REG_RX_PAGE_SIZE);
  1181. /* enable the header parser if desired */
  1182. if (CAS_HP_FIRMWARE == cas_prog_null)
  1183. return;
  1184. val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
  1185. val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
  1186. val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
  1187. writel(val, cp->regs + REG_HP_CFG);
  1188. }
  1189. static inline void cas_rxc_init(struct cas_rx_comp *rxc)
  1190. {
  1191. memset(rxc, 0, sizeof(*rxc));
  1192. rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
  1193. }
  1194. /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
  1195. * flipping is protected by the fact that the chip will not
  1196. * hand back the same page index while it's being processed.
  1197. */
  1198. static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
  1199. {
  1200. cas_page_t *page = cp->rx_pages[1][index];
  1201. cas_page_t *new;
  1202. if (page_count(page->buffer) == 1)
  1203. return page;
  1204. new = cas_page_dequeue(cp);
  1205. if (new) {
  1206. spin_lock(&cp->rx_inuse_lock);
  1207. list_add(&page->list, &cp->rx_inuse_list);
  1208. spin_unlock(&cp->rx_inuse_lock);
  1209. }
  1210. return new;
  1211. }
  1212. /* this needs to be changed if we actually use the ENC RX DESC ring */
  1213. static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
  1214. const int index)
  1215. {
  1216. cas_page_t **page0 = cp->rx_pages[0];
  1217. cas_page_t **page1 = cp->rx_pages[1];
  1218. /* swap if buffer is in use */
  1219. if (page_count(page0[index]->buffer) > 1) {
  1220. cas_page_t *new = cas_page_spare(cp, index);
  1221. if (new) {
  1222. page1[index] = page0[index];
  1223. page0[index] = new;
  1224. }
  1225. }
  1226. RX_USED_SET(page0[index], 0);
  1227. return page0[index];
  1228. }
  1229. static void cas_clean_rxds(struct cas *cp)
  1230. {
  1231. /* only clean ring 0 as ring 1 is used for spare buffers */
  1232. struct cas_rx_desc *rxd = cp->init_rxds[0];
  1233. int i, size;
  1234. /* release all rx flows */
  1235. for (i = 0; i < N_RX_FLOWS; i++) {
  1236. struct sk_buff *skb;
  1237. while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
  1238. cas_skb_release(skb);
  1239. }
  1240. }
  1241. /* initialize descriptors */
  1242. size = RX_DESC_RINGN_SIZE(0);
  1243. for (i = 0; i < size; i++) {
  1244. cas_page_t *page = cas_page_swap(cp, 0, i);
  1245. rxd[i].buffer = cpu_to_le64(page->dma_addr);
  1246. rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
  1247. CAS_BASE(RX_INDEX_RING, 0));
  1248. }
  1249. cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
  1250. cp->rx_last[0] = 0;
  1251. cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
  1252. }
  1253. static void cas_clean_rxcs(struct cas *cp)
  1254. {
  1255. int i, j;
  1256. /* take ownership of rx comp descriptors */
  1257. memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
  1258. memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
  1259. for (i = 0; i < N_RX_COMP_RINGS; i++) {
  1260. struct cas_rx_comp *rxc = cp->init_rxcs[i];
  1261. for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
  1262. cas_rxc_init(rxc + j);
  1263. }
  1264. }
  1265. }
  1266. #if 0
  1267. /* When we get a RX fifo overflow, the RX unit is probably hung
  1268. * so we do the following.
  1269. *
  1270. * If any part of the reset goes wrong, we return 1 and that causes the
  1271. * whole chip to be reset.
  1272. */
  1273. static int cas_rxmac_reset(struct cas *cp)
  1274. {
  1275. struct net_device *dev = cp->dev;
  1276. int limit;
  1277. u32 val;
  1278. /* First, reset MAC RX. */
  1279. writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  1280. for (limit = 0; limit < STOP_TRIES; limit++) {
  1281. if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
  1282. break;
  1283. udelay(10);
  1284. }
  1285. if (limit == STOP_TRIES) {
  1286. netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
  1287. return 1;
  1288. }
  1289. /* Second, disable RX DMA. */
  1290. writel(0, cp->regs + REG_RX_CFG);
  1291. for (limit = 0; limit < STOP_TRIES; limit++) {
  1292. if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
  1293. break;
  1294. udelay(10);
  1295. }
  1296. if (limit == STOP_TRIES) {
  1297. netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
  1298. return 1;
  1299. }
  1300. mdelay(5);
  1301. /* Execute RX reset command. */
  1302. writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
  1303. for (limit = 0; limit < STOP_TRIES; limit++) {
  1304. if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
  1305. break;
  1306. udelay(10);
  1307. }
  1308. if (limit == STOP_TRIES) {
  1309. netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
  1310. return 1;
  1311. }
  1312. /* reset driver rx state */
  1313. cas_clean_rxds(cp);
  1314. cas_clean_rxcs(cp);
  1315. /* Now, reprogram the rest of RX unit. */
  1316. cas_init_rx_dma(cp);
  1317. /* re-enable */
  1318. val = readl(cp->regs + REG_RX_CFG);
  1319. writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
  1320. writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
  1321. val = readl(cp->regs + REG_MAC_RX_CFG);
  1322. writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  1323. return 0;
  1324. }
  1325. #endif
  1326. static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
  1327. u32 status)
  1328. {
  1329. u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
  1330. if (!stat)
  1331. return 0;
  1332. netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
  1333. /* these are all rollovers */
  1334. spin_lock(&cp->stat_lock[0]);
  1335. if (stat & MAC_RX_ALIGN_ERR)
  1336. cp->net_stats[0].rx_frame_errors += 0x10000;
  1337. if (stat & MAC_RX_CRC_ERR)
  1338. cp->net_stats[0].rx_crc_errors += 0x10000;
  1339. if (stat & MAC_RX_LEN_ERR)
  1340. cp->net_stats[0].rx_length_errors += 0x10000;
  1341. if (stat & MAC_RX_OVERFLOW) {
  1342. cp->net_stats[0].rx_over_errors++;
  1343. cp->net_stats[0].rx_fifo_errors++;
  1344. }
  1345. /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
  1346. * events.
  1347. */
  1348. spin_unlock(&cp->stat_lock[0]);
  1349. return 0;
  1350. }
  1351. static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
  1352. u32 status)
  1353. {
  1354. u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
  1355. if (!stat)
  1356. return 0;
  1357. netif_printk(cp, intr, KERN_DEBUG, cp->dev,
  1358. "mac interrupt, stat: 0x%x\n", stat);
  1359. /* This interrupt is just for pause frame and pause
  1360. * tracking. It is useful for diagnostics and debug
  1361. * but probably by default we will mask these events.
  1362. */
  1363. if (stat & MAC_CTRL_PAUSE_STATE)
  1364. cp->pause_entered++;
  1365. if (stat & MAC_CTRL_PAUSE_RECEIVED)
  1366. cp->pause_last_time_recvd = (stat >> 16);
  1367. return 0;
  1368. }
  1369. /* Must be invoked under cp->lock. */
  1370. static inline int cas_mdio_link_not_up(struct cas *cp)
  1371. {
  1372. u16 val;
  1373. switch (cp->lstate) {
  1374. case link_force_ret:
  1375. netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
  1376. cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
  1377. cp->timer_ticks = 5;
  1378. cp->lstate = link_force_ok;
  1379. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1380. break;
  1381. case link_aneg:
  1382. val = cas_phy_read(cp, MII_BMCR);
  1383. /* Try forced modes. we try things in the following order:
  1384. * 1000 full -> 100 full/half -> 10 half
  1385. */
  1386. val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
  1387. val |= BMCR_FULLDPLX;
  1388. val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
  1389. CAS_BMCR_SPEED1000 : BMCR_SPEED100;
  1390. cas_phy_write(cp, MII_BMCR, val);
  1391. cp->timer_ticks = 5;
  1392. cp->lstate = link_force_try;
  1393. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1394. break;
  1395. case link_force_try:
  1396. /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
  1397. val = cas_phy_read(cp, MII_BMCR);
  1398. cp->timer_ticks = 5;
  1399. if (val & CAS_BMCR_SPEED1000) { /* gigabit */
  1400. val &= ~CAS_BMCR_SPEED1000;
  1401. val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
  1402. cas_phy_write(cp, MII_BMCR, val);
  1403. break;
  1404. }
  1405. if (val & BMCR_SPEED100) {
  1406. if (val & BMCR_FULLDPLX) /* fd failed */
  1407. val &= ~BMCR_FULLDPLX;
  1408. else { /* 100Mbps failed */
  1409. val &= ~BMCR_SPEED100;
  1410. }
  1411. cas_phy_write(cp, MII_BMCR, val);
  1412. break;
  1413. }
  1414. default:
  1415. break;
  1416. }
  1417. return 0;
  1418. }
  1419. /* must be invoked with cp->lock held */
  1420. static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
  1421. {
  1422. int restart;
  1423. if (bmsr & BMSR_LSTATUS) {
  1424. /* Ok, here we got a link. If we had it due to a forced
  1425. * fallback, and we were configured for autoneg, we
  1426. * retry a short autoneg pass. If you know your hub is
  1427. * broken, use ethtool ;)
  1428. */
  1429. if ((cp->lstate == link_force_try) &&
  1430. (cp->link_cntl & BMCR_ANENABLE)) {
  1431. cp->lstate = link_force_ret;
  1432. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1433. cas_mif_poll(cp, 0);
  1434. cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
  1435. cp->timer_ticks = 5;
  1436. if (cp->opened)
  1437. netif_info(cp, link, cp->dev,
  1438. "Got link after fallback, retrying autoneg once...\n");
  1439. cas_phy_write(cp, MII_BMCR,
  1440. cp->link_fcntl | BMCR_ANENABLE |
  1441. BMCR_ANRESTART);
  1442. cas_mif_poll(cp, 1);
  1443. } else if (cp->lstate != link_up) {
  1444. cp->lstate = link_up;
  1445. cp->link_transition = LINK_TRANSITION_LINK_UP;
  1446. if (cp->opened) {
  1447. cas_set_link_modes(cp);
  1448. netif_carrier_on(cp->dev);
  1449. }
  1450. }
  1451. return 0;
  1452. }
  1453. /* link not up. if the link was previously up, we restart the
  1454. * whole process
  1455. */
  1456. restart = 0;
  1457. if (cp->lstate == link_up) {
  1458. cp->lstate = link_down;
  1459. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  1460. netif_carrier_off(cp->dev);
  1461. if (cp->opened)
  1462. netif_info(cp, link, cp->dev, "Link down\n");
  1463. restart = 1;
  1464. } else if (++cp->timer_ticks > 10)
  1465. cas_mdio_link_not_up(cp);
  1466. return restart;
  1467. }
  1468. static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
  1469. u32 status)
  1470. {
  1471. u32 stat = readl(cp->regs + REG_MIF_STATUS);
  1472. u16 bmsr;
  1473. /* check for a link change */
  1474. if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
  1475. return 0;
  1476. bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
  1477. return cas_mii_link_check(cp, bmsr);
  1478. }
  1479. static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
  1480. u32 status)
  1481. {
  1482. u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
  1483. if (!stat)
  1484. return 0;
  1485. netdev_err(dev, "PCI error [%04x:%04x]",
  1486. stat, readl(cp->regs + REG_BIM_DIAG));
  1487. /* cassini+ has this reserved */
  1488. if ((stat & PCI_ERR_BADACK) &&
  1489. ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
  1490. pr_cont(" <No ACK64# during ABS64 cycle>");
  1491. if (stat & PCI_ERR_DTRTO)
  1492. pr_cont(" <Delayed transaction timeout>");
  1493. if (stat & PCI_ERR_OTHER)
  1494. pr_cont(" <other>");
  1495. if (stat & PCI_ERR_BIM_DMA_WRITE)
  1496. pr_cont(" <BIM DMA 0 write req>");
  1497. if (stat & PCI_ERR_BIM_DMA_READ)
  1498. pr_cont(" <BIM DMA 0 read req>");
  1499. pr_cont("\n");
  1500. if (stat & PCI_ERR_OTHER) {
  1501. u16 cfg;
  1502. /* Interrogate PCI config space for the
  1503. * true cause.
  1504. */
  1505. pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
  1506. netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
  1507. if (cfg & PCI_STATUS_PARITY)
  1508. netdev_err(dev, "PCI parity error detected\n");
  1509. if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
  1510. netdev_err(dev, "PCI target abort\n");
  1511. if (cfg & PCI_STATUS_REC_TARGET_ABORT)
  1512. netdev_err(dev, "PCI master acks target abort\n");
  1513. if (cfg & PCI_STATUS_REC_MASTER_ABORT)
  1514. netdev_err(dev, "PCI master abort\n");
  1515. if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
  1516. netdev_err(dev, "PCI system error SERR#\n");
  1517. if (cfg & PCI_STATUS_DETECTED_PARITY)
  1518. netdev_err(dev, "PCI parity error\n");
  1519. /* Write the error bits back to clear them. */
  1520. cfg &= (PCI_STATUS_PARITY |
  1521. PCI_STATUS_SIG_TARGET_ABORT |
  1522. PCI_STATUS_REC_TARGET_ABORT |
  1523. PCI_STATUS_REC_MASTER_ABORT |
  1524. PCI_STATUS_SIG_SYSTEM_ERROR |
  1525. PCI_STATUS_DETECTED_PARITY);
  1526. pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
  1527. }
  1528. /* For all PCI errors, we should reset the chip. */
  1529. return 1;
  1530. }
  1531. /* All non-normal interrupt conditions get serviced here.
  1532. * Returns non-zero if we should just exit the interrupt
  1533. * handler right now (ie. if we reset the card which invalidates
  1534. * all of the other original irq status bits).
  1535. */
  1536. static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
  1537. u32 status)
  1538. {
  1539. if (status & INTR_RX_TAG_ERROR) {
  1540. /* corrupt RX tag framing */
  1541. netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
  1542. "corrupt rx tag framing\n");
  1543. spin_lock(&cp->stat_lock[0]);
  1544. cp->net_stats[0].rx_errors++;
  1545. spin_unlock(&cp->stat_lock[0]);
  1546. goto do_reset;
  1547. }
  1548. if (status & INTR_RX_LEN_MISMATCH) {
  1549. /* length mismatch. */
  1550. netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
  1551. "length mismatch for rx frame\n");
  1552. spin_lock(&cp->stat_lock[0]);
  1553. cp->net_stats[0].rx_errors++;
  1554. spin_unlock(&cp->stat_lock[0]);
  1555. goto do_reset;
  1556. }
  1557. if (status & INTR_PCS_STATUS) {
  1558. if (cas_pcs_interrupt(dev, cp, status))
  1559. goto do_reset;
  1560. }
  1561. if (status & INTR_TX_MAC_STATUS) {
  1562. if (cas_txmac_interrupt(dev, cp, status))
  1563. goto do_reset;
  1564. }
  1565. if (status & INTR_RX_MAC_STATUS) {
  1566. if (cas_rxmac_interrupt(dev, cp, status))
  1567. goto do_reset;
  1568. }
  1569. if (status & INTR_MAC_CTRL_STATUS) {
  1570. if (cas_mac_interrupt(dev, cp, status))
  1571. goto do_reset;
  1572. }
  1573. if (status & INTR_MIF_STATUS) {
  1574. if (cas_mif_interrupt(dev, cp, status))
  1575. goto do_reset;
  1576. }
  1577. if (status & INTR_PCI_ERROR_STATUS) {
  1578. if (cas_pci_interrupt(dev, cp, status))
  1579. goto do_reset;
  1580. }
  1581. return 0;
  1582. do_reset:
  1583. #if 1
  1584. atomic_inc(&cp->reset_task_pending);
  1585. atomic_inc(&cp->reset_task_pending_all);
  1586. netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
  1587. schedule_work(&cp->reset_task);
  1588. #else
  1589. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  1590. netdev_err(dev, "reset called in cas_abnormal_irq\n");
  1591. schedule_work(&cp->reset_task);
  1592. #endif
  1593. return 1;
  1594. }
  1595. /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
  1596. * determining whether to do a netif_stop/wakeup
  1597. */
  1598. #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
  1599. #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
  1600. static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
  1601. const int len)
  1602. {
  1603. unsigned long off = addr + len;
  1604. if (CAS_TABORT(cp) == 1)
  1605. return 0;
  1606. if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
  1607. return 0;
  1608. return TX_TARGET_ABORT_LEN;
  1609. }
  1610. static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
  1611. {
  1612. struct cas_tx_desc *txds;
  1613. struct sk_buff **skbs;
  1614. struct net_device *dev = cp->dev;
  1615. int entry, count;
  1616. spin_lock(&cp->tx_lock[ring]);
  1617. txds = cp->init_txds[ring];
  1618. skbs = cp->tx_skbs[ring];
  1619. entry = cp->tx_old[ring];
  1620. count = TX_BUFF_COUNT(ring, entry, limit);
  1621. while (entry != limit) {
  1622. struct sk_buff *skb = skbs[entry];
  1623. dma_addr_t daddr;
  1624. u32 dlen;
  1625. int frag;
  1626. if (!skb) {
  1627. /* this should never occur */
  1628. entry = TX_DESC_NEXT(ring, entry);
  1629. continue;
  1630. }
  1631. /* however, we might get only a partial skb release. */
  1632. count -= skb_shinfo(skb)->nr_frags +
  1633. + cp->tx_tiny_use[ring][entry].nbufs + 1;
  1634. if (count < 0)
  1635. break;
  1636. netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
  1637. "tx[%d] done, slot %d\n", ring, entry);
  1638. skbs[entry] = NULL;
  1639. cp->tx_tiny_use[ring][entry].nbufs = 0;
  1640. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  1641. struct cas_tx_desc *txd = txds + entry;
  1642. daddr = le64_to_cpu(txd->buffer);
  1643. dlen = CAS_VAL(TX_DESC_BUFLEN,
  1644. le64_to_cpu(txd->control));
  1645. pci_unmap_page(cp->pdev, daddr, dlen,
  1646. PCI_DMA_TODEVICE);
  1647. entry = TX_DESC_NEXT(ring, entry);
  1648. /* tiny buffer may follow */
  1649. if (cp->tx_tiny_use[ring][entry].used) {
  1650. cp->tx_tiny_use[ring][entry].used = 0;
  1651. entry = TX_DESC_NEXT(ring, entry);
  1652. }
  1653. }
  1654. spin_lock(&cp->stat_lock[ring]);
  1655. cp->net_stats[ring].tx_packets++;
  1656. cp->net_stats[ring].tx_bytes += skb->len;
  1657. spin_unlock(&cp->stat_lock[ring]);
  1658. dev_kfree_skb_irq(skb);
  1659. }
  1660. cp->tx_old[ring] = entry;
  1661. /* this is wrong for multiple tx rings. the net device needs
  1662. * multiple queues for this to do the right thing. we wait
  1663. * for 2*packets to be available when using tiny buffers
  1664. */
  1665. if (netif_queue_stopped(dev) &&
  1666. (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
  1667. netif_wake_queue(dev);
  1668. spin_unlock(&cp->tx_lock[ring]);
  1669. }
  1670. static void cas_tx(struct net_device *dev, struct cas *cp,
  1671. u32 status)
  1672. {
  1673. int limit, ring;
  1674. #ifdef USE_TX_COMPWB
  1675. u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
  1676. #endif
  1677. netif_printk(cp, intr, KERN_DEBUG, cp->dev,
  1678. "tx interrupt, status: 0x%x, %llx\n",
  1679. status, (unsigned long long)compwb);
  1680. /* process all the rings */
  1681. for (ring = 0; ring < N_TX_RINGS; ring++) {
  1682. #ifdef USE_TX_COMPWB
  1683. /* use the completion writeback registers */
  1684. limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
  1685. CAS_VAL(TX_COMPWB_LSB, compwb);
  1686. compwb = TX_COMPWB_NEXT(compwb);
  1687. #else
  1688. limit = readl(cp->regs + REG_TX_COMPN(ring));
  1689. #endif
  1690. if (cp->tx_old[ring] != limit)
  1691. cas_tx_ringN(cp, ring, limit);
  1692. }
  1693. }
  1694. static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
  1695. int entry, const u64 *words,
  1696. struct sk_buff **skbref)
  1697. {
  1698. int dlen, hlen, len, i, alloclen;
  1699. int off, swivel = RX_SWIVEL_OFF_VAL;
  1700. struct cas_page *page;
  1701. struct sk_buff *skb;
  1702. void *addr, *crcaddr;
  1703. __sum16 csum;
  1704. char *p;
  1705. hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
  1706. dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
  1707. len = hlen + dlen;
  1708. if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
  1709. alloclen = len;
  1710. else
  1711. alloclen = max(hlen, RX_COPY_MIN);
  1712. skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
  1713. if (skb == NULL)
  1714. return -1;
  1715. *skbref = skb;
  1716. skb_reserve(skb, swivel);
  1717. p = skb->data;
  1718. addr = crcaddr = NULL;
  1719. if (hlen) { /* always copy header pages */
  1720. i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
  1721. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1722. off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
  1723. swivel;
  1724. i = hlen;
  1725. if (!dlen) /* attach FCS */
  1726. i += cp->crc_size;
  1727. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1728. PCI_DMA_FROMDEVICE);
  1729. addr = cas_page_map(page->buffer);
  1730. memcpy(p, addr + off, i);
  1731. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1732. PCI_DMA_FROMDEVICE);
  1733. cas_page_unmap(addr);
  1734. RX_USED_ADD(page, 0x100);
  1735. p += hlen;
  1736. swivel = 0;
  1737. }
  1738. if (alloclen < (hlen + dlen)) {
  1739. skb_frag_t *frag = skb_shinfo(skb)->frags;
  1740. /* normal or jumbo packets. we use frags */
  1741. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  1742. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1743. off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
  1744. hlen = min(cp->page_size - off, dlen);
  1745. if (hlen < 0) {
  1746. netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
  1747. "rx page overflow: %d\n", hlen);
  1748. dev_kfree_skb_irq(skb);
  1749. return -1;
  1750. }
  1751. i = hlen;
  1752. if (i == dlen) /* attach FCS */
  1753. i += cp->crc_size;
  1754. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1755. PCI_DMA_FROMDEVICE);
  1756. /* make sure we always copy a header */
  1757. swivel = 0;
  1758. if (p == (char *) skb->data) { /* not split */
  1759. addr = cas_page_map(page->buffer);
  1760. memcpy(p, addr + off, RX_COPY_MIN);
  1761. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1762. PCI_DMA_FROMDEVICE);
  1763. cas_page_unmap(addr);
  1764. off += RX_COPY_MIN;
  1765. swivel = RX_COPY_MIN;
  1766. RX_USED_ADD(page, cp->mtu_stride);
  1767. } else {
  1768. RX_USED_ADD(page, hlen);
  1769. }
  1770. skb_put(skb, alloclen);
  1771. skb_shinfo(skb)->nr_frags++;
  1772. skb->data_len += hlen - swivel;
  1773. skb->truesize += hlen - swivel;
  1774. skb->len += hlen - swivel;
  1775. get_page(page->buffer);
  1776. frag->page = page->buffer;
  1777. frag->page_offset = off;
  1778. frag->size = hlen - swivel;
  1779. /* any more data? */
  1780. if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
  1781. hlen = dlen;
  1782. off = 0;
  1783. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  1784. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1785. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
  1786. hlen + cp->crc_size,
  1787. PCI_DMA_FROMDEVICE);
  1788. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
  1789. hlen + cp->crc_size,
  1790. PCI_DMA_FROMDEVICE);
  1791. skb_shinfo(skb)->nr_frags++;
  1792. skb->data_len += hlen;
  1793. skb->len += hlen;
  1794. frag++;
  1795. get_page(page->buffer);
  1796. frag->page = page->buffer;
  1797. frag->page_offset = 0;
  1798. frag->size = hlen;
  1799. RX_USED_ADD(page, hlen + cp->crc_size);
  1800. }
  1801. if (cp->crc_size) {
  1802. addr = cas_page_map(page->buffer);
  1803. crcaddr = addr + off + hlen;
  1804. }
  1805. } else {
  1806. /* copying packet */
  1807. if (!dlen)
  1808. goto end_copy_pkt;
  1809. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  1810. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1811. off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
  1812. hlen = min(cp->page_size - off, dlen);
  1813. if (hlen < 0) {
  1814. netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
  1815. "rx page overflow: %d\n", hlen);
  1816. dev_kfree_skb_irq(skb);
  1817. return -1;
  1818. }
  1819. i = hlen;
  1820. if (i == dlen) /* attach FCS */
  1821. i += cp->crc_size;
  1822. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1823. PCI_DMA_FROMDEVICE);
  1824. addr = cas_page_map(page->buffer);
  1825. memcpy(p, addr + off, i);
  1826. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1827. PCI_DMA_FROMDEVICE);
  1828. cas_page_unmap(addr);
  1829. if (p == (char *) skb->data) /* not split */
  1830. RX_USED_ADD(page, cp->mtu_stride);
  1831. else
  1832. RX_USED_ADD(page, i);
  1833. /* any more data? */
  1834. if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
  1835. p += hlen;
  1836. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  1837. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1838. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
  1839. dlen + cp->crc_size,
  1840. PCI_DMA_FROMDEVICE);
  1841. addr = cas_page_map(page->buffer);
  1842. memcpy(p, addr, dlen + cp->crc_size);
  1843. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
  1844. dlen + cp->crc_size,
  1845. PCI_DMA_FROMDEVICE);
  1846. cas_page_unmap(addr);
  1847. RX_USED_ADD(page, dlen + cp->crc_size);
  1848. }
  1849. end_copy_pkt:
  1850. if (cp->crc_size) {
  1851. addr = NULL;
  1852. crcaddr = skb->data + alloclen;
  1853. }
  1854. skb_put(skb, alloclen);
  1855. }
  1856. csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
  1857. if (cp->crc_size) {
  1858. /* checksum includes FCS. strip it out. */
  1859. csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
  1860. csum_unfold(csum)));
  1861. if (addr)
  1862. cas_page_unmap(addr);
  1863. }
  1864. skb->protocol = eth_type_trans(skb, cp->dev);
  1865. if (skb->protocol == htons(ETH_P_IP)) {
  1866. skb->csum = csum_unfold(~csum);
  1867. skb->ip_summed = CHECKSUM_COMPLETE;
  1868. } else
  1869. skb_checksum_none_assert(skb);
  1870. return len;
  1871. }
  1872. /* we can handle up to 64 rx flows at a time. we do the same thing
  1873. * as nonreassm except that we batch up the buffers.
  1874. * NOTE: we currently just treat each flow as a bunch of packets that
  1875. * we pass up. a better way would be to coalesce the packets
  1876. * into a jumbo packet. to do that, we need to do the following:
  1877. * 1) the first packet will have a clean split between header and
  1878. * data. save both.
  1879. * 2) each time the next flow packet comes in, extend the
  1880. * data length and merge the checksums.
  1881. * 3) on flow release, fix up the header.
  1882. * 4) make sure the higher layer doesn't care.
  1883. * because packets get coalesced, we shouldn't run into fragment count
  1884. * issues.
  1885. */
  1886. static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
  1887. struct sk_buff *skb)
  1888. {
  1889. int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
  1890. struct sk_buff_head *flow = &cp->rx_flows[flowid];
  1891. /* this is protected at a higher layer, so no need to
  1892. * do any additional locking here. stick the buffer
  1893. * at the end.
  1894. */
  1895. __skb_queue_tail(flow, skb);
  1896. if (words[0] & RX_COMP1_RELEASE_FLOW) {
  1897. while ((skb = __skb_dequeue(flow))) {
  1898. cas_skb_release(skb);
  1899. }
  1900. }
  1901. }
  1902. /* put rx descriptor back on ring. if a buffer is in use by a higher
  1903. * layer, this will need to put in a replacement.
  1904. */
  1905. static void cas_post_page(struct cas *cp, const int ring, const int index)
  1906. {
  1907. cas_page_t *new;
  1908. int entry;
  1909. entry = cp->rx_old[ring];
  1910. new = cas_page_swap(cp, ring, index);
  1911. cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
  1912. cp->init_rxds[ring][entry].index =
  1913. cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
  1914. CAS_BASE(RX_INDEX_RING, ring));
  1915. entry = RX_DESC_ENTRY(ring, entry + 1);
  1916. cp->rx_old[ring] = entry;
  1917. if (entry % 4)
  1918. return;
  1919. if (ring == 0)
  1920. writel(entry, cp->regs + REG_RX_KICK);
  1921. else if ((N_RX_DESC_RINGS > 1) &&
  1922. (cp->cas_flags & CAS_FLAG_REG_PLUS))
  1923. writel(entry, cp->regs + REG_PLUS_RX_KICK1);
  1924. }
  1925. /* only when things are bad */
  1926. static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
  1927. {
  1928. unsigned int entry, last, count, released;
  1929. int cluster;
  1930. cas_page_t **page = cp->rx_pages[ring];
  1931. entry = cp->rx_old[ring];
  1932. netif_printk(cp, intr, KERN_DEBUG, cp->dev,
  1933. "rxd[%d] interrupt, done: %d\n", ring, entry);
  1934. cluster = -1;
  1935. count = entry & 0x3;
  1936. last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
  1937. released = 0;
  1938. while (entry != last) {
  1939. /* make a new buffer if it's still in use */
  1940. if (page_count(page[entry]->buffer) > 1) {
  1941. cas_page_t *new = cas_page_dequeue(cp);
  1942. if (!new) {
  1943. /* let the timer know that we need to
  1944. * do this again
  1945. */
  1946. cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
  1947. if (!timer_pending(&cp->link_timer))
  1948. mod_timer(&cp->link_timer, jiffies +
  1949. CAS_LINK_FAST_TIMEOUT);
  1950. cp->rx_old[ring] = entry;
  1951. cp->rx_last[ring] = num ? num - released : 0;
  1952. return -ENOMEM;
  1953. }
  1954. spin_lock(&cp->rx_inuse_lock);
  1955. list_add(&page[entry]->list, &cp->rx_inuse_list);
  1956. spin_unlock(&cp->rx_inuse_lock);
  1957. cp->init_rxds[ring][entry].buffer =
  1958. cpu_to_le64(new->dma_addr);
  1959. page[entry] = new;
  1960. }
  1961. if (++count == 4) {
  1962. cluster = entry;
  1963. count = 0;
  1964. }
  1965. released++;
  1966. entry = RX_DESC_ENTRY(ring, entry + 1);
  1967. }
  1968. cp->rx_old[ring] = entry;
  1969. if (cluster < 0)
  1970. return 0;
  1971. if (ring == 0)
  1972. writel(cluster, cp->regs + REG_RX_KICK);
  1973. else if ((N_RX_DESC_RINGS > 1) &&
  1974. (cp->cas_flags & CAS_FLAG_REG_PLUS))
  1975. writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
  1976. return 0;
  1977. }
  1978. /* process a completion ring. packets are set up in three basic ways:
  1979. * small packets: should be copied header + data in single buffer.
  1980. * large packets: header and data in a single buffer.
  1981. * split packets: header in a separate buffer from data.
  1982. * data may be in multiple pages. data may be > 256
  1983. * bytes but in a single page.
  1984. *
  1985. * NOTE: RX page posting is done in this routine as well. while there's
  1986. * the capability of using multiple RX completion rings, it isn't
  1987. * really worthwhile due to the fact that the page posting will
  1988. * force serialization on the single descriptor ring.
  1989. */
  1990. static int cas_rx_ringN(struct cas *cp, int ring, int budget)
  1991. {
  1992. struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
  1993. int entry, drops;
  1994. int npackets = 0;
  1995. netif_printk(cp, intr, KERN_DEBUG, cp->dev,
  1996. "rx[%d] interrupt, done: %d/%d\n",
  1997. ring,
  1998. readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
  1999. entry = cp->rx_new[ring];
  2000. drops = 0;
  2001. while (1) {
  2002. struct cas_rx_comp *rxc = rxcs + entry;
  2003. struct sk_buff *uninitialized_var(skb);
  2004. int type, len;
  2005. u64 words[4];
  2006. int i, dring;
  2007. words[0] = le64_to_cpu(rxc->word1);
  2008. words[1] = le64_to_cpu(rxc->word2);
  2009. words[2] = le64_to_cpu(rxc->word3);
  2010. words[3] = le64_to_cpu(rxc->word4);
  2011. /* don't touch if still owned by hw */
  2012. type = CAS_VAL(RX_COMP1_TYPE, words[0]);
  2013. if (type == 0)
  2014. break;
  2015. /* hw hasn't cleared the zero bit yet */
  2016. if (words[3] & RX_COMP4_ZERO) {
  2017. break;
  2018. }
  2019. /* get info on the packet */
  2020. if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
  2021. spin_lock(&cp->stat_lock[ring]);
  2022. cp->net_stats[ring].rx_errors++;
  2023. if (words[3] & RX_COMP4_LEN_MISMATCH)
  2024. cp->net_stats[ring].rx_length_errors++;
  2025. if (words[3] & RX_COMP4_BAD)
  2026. cp->net_stats[ring].rx_crc_errors++;
  2027. spin_unlock(&cp->stat_lock[ring]);
  2028. /* We'll just return it to Cassini. */
  2029. drop_it:
  2030. spin_lock(&cp->stat_lock[ring]);
  2031. ++cp->net_stats[ring].rx_dropped;
  2032. spin_unlock(&cp->stat_lock[ring]);
  2033. goto next;
  2034. }
  2035. len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
  2036. if (len < 0) {
  2037. ++drops;
  2038. goto drop_it;
  2039. }
  2040. /* see if it's a flow re-assembly or not. the driver
  2041. * itself handles release back up.
  2042. */
  2043. if (RX_DONT_BATCH || (type == 0x2)) {
  2044. /* non-reassm: these always get released */
  2045. cas_skb_release(skb);
  2046. } else {
  2047. cas_rx_flow_pkt(cp, words, skb);
  2048. }
  2049. spin_lock(&cp->stat_lock[ring]);
  2050. cp->net_stats[ring].rx_packets++;
  2051. cp->net_stats[ring].rx_bytes += len;
  2052. spin_unlock(&cp->stat_lock[ring]);
  2053. next:
  2054. npackets++;
  2055. /* should it be released? */
  2056. if (words[0] & RX_COMP1_RELEASE_HDR) {
  2057. i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
  2058. dring = CAS_VAL(RX_INDEX_RING, i);
  2059. i = CAS_VAL(RX_INDEX_NUM, i);
  2060. cas_post_page(cp, dring, i);
  2061. }
  2062. if (words[0] & RX_COMP1_RELEASE_DATA) {
  2063. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  2064. dring = CAS_VAL(RX_INDEX_RING, i);
  2065. i = CAS_VAL(RX_INDEX_NUM, i);
  2066. cas_post_page(cp, dring, i);
  2067. }
  2068. if (words[0] & RX_COMP1_RELEASE_NEXT) {
  2069. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  2070. dring = CAS_VAL(RX_INDEX_RING, i);
  2071. i = CAS_VAL(RX_INDEX_NUM, i);
  2072. cas_post_page(cp, dring, i);
  2073. }
  2074. /* skip to the next entry */
  2075. entry = RX_COMP_ENTRY(ring, entry + 1 +
  2076. CAS_VAL(RX_COMP1_SKIP, words[0]));
  2077. #ifdef USE_NAPI
  2078. if (budget && (npackets >= budget))
  2079. break;
  2080. #endif
  2081. }
  2082. cp->rx_new[ring] = entry;
  2083. if (drops)
  2084. netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
  2085. return npackets;
  2086. }
  2087. /* put completion entries back on the ring */
  2088. static void cas_post_rxcs_ringN(struct net_device *dev,
  2089. struct cas *cp, int ring)
  2090. {
  2091. struct cas_rx_comp *rxc = cp->init_rxcs[ring];
  2092. int last, entry;
  2093. last = cp->rx_cur[ring];
  2094. entry = cp->rx_new[ring];
  2095. netif_printk(cp, intr, KERN_DEBUG, dev,
  2096. "rxc[%d] interrupt, done: %d/%d\n",
  2097. ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
  2098. /* zero and re-mark descriptors */
  2099. while (last != entry) {
  2100. cas_rxc_init(rxc + last);
  2101. last = RX_COMP_ENTRY(ring, last + 1);
  2102. }
  2103. cp->rx_cur[ring] = last;
  2104. if (ring == 0)
  2105. writel(last, cp->regs + REG_RX_COMP_TAIL);
  2106. else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
  2107. writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
  2108. }
  2109. /* cassini can use all four PCI interrupts for the completion ring.
  2110. * rings 3 and 4 are identical
  2111. */
  2112. #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  2113. static inline void cas_handle_irqN(struct net_device *dev,
  2114. struct cas *cp, const u32 status,
  2115. const int ring)
  2116. {
  2117. if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
  2118. cas_post_rxcs_ringN(dev, cp, ring);
  2119. }
  2120. static irqreturn_t cas_interruptN(int irq, void *dev_id)
  2121. {
  2122. struct net_device *dev = dev_id;
  2123. struct cas *cp = netdev_priv(dev);
  2124. unsigned long flags;
  2125. int ring;
  2126. u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
  2127. /* check for shared irq */
  2128. if (status == 0)
  2129. return IRQ_NONE;
  2130. ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
  2131. spin_lock_irqsave(&cp->lock, flags);
  2132. if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
  2133. #ifdef USE_NAPI
  2134. cas_mask_intr(cp);
  2135. napi_schedule(&cp->napi);
  2136. #else
  2137. cas_rx_ringN(cp, ring, 0);
  2138. #endif
  2139. status &= ~INTR_RX_DONE_ALT;
  2140. }
  2141. if (status)
  2142. cas_handle_irqN(dev, cp, status, ring);
  2143. spin_unlock_irqrestore(&cp->lock, flags);
  2144. return IRQ_HANDLED;
  2145. }
  2146. #endif
  2147. #ifdef USE_PCI_INTB
  2148. /* everything but rx packets */
  2149. static inline void cas_handle_irq1(struct cas *cp, const u32 status)
  2150. {
  2151. if (status & INTR_RX_BUF_UNAVAIL_1) {
  2152. /* Frame arrived, no free RX buffers available.
  2153. * NOTE: we can get this on a link transition. */
  2154. cas_post_rxds_ringN(cp, 1, 0);
  2155. spin_lock(&cp->stat_lock[1]);
  2156. cp->net_stats[1].rx_dropped++;
  2157. spin_unlock(&cp->stat_lock[1]);
  2158. }
  2159. if (status & INTR_RX_BUF_AE_1)
  2160. cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
  2161. RX_AE_FREEN_VAL(1));
  2162. if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
  2163. cas_post_rxcs_ringN(cp, 1);
  2164. }
  2165. /* ring 2 handles a few more events than 3 and 4 */
  2166. static irqreturn_t cas_interrupt1(int irq, void *dev_id)
  2167. {
  2168. struct net_device *dev = dev_id;
  2169. struct cas *cp = netdev_priv(dev);
  2170. unsigned long flags;
  2171. u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
  2172. /* check for shared interrupt */
  2173. if (status == 0)
  2174. return IRQ_NONE;
  2175. spin_lock_irqsave(&cp->lock, flags);
  2176. if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
  2177. #ifdef USE_NAPI
  2178. cas_mask_intr(cp);
  2179. napi_schedule(&cp->napi);
  2180. #else
  2181. cas_rx_ringN(cp, 1, 0);
  2182. #endif
  2183. status &= ~INTR_RX_DONE_ALT;
  2184. }
  2185. if (status)
  2186. cas_handle_irq1(cp, status);
  2187. spin_unlock_irqrestore(&cp->lock, flags);
  2188. return IRQ_HANDLED;
  2189. }
  2190. #endif
  2191. static inline void cas_handle_irq(struct net_device *dev,
  2192. struct cas *cp, const u32 status)
  2193. {
  2194. /* housekeeping interrupts */
  2195. if (status & INTR_ERROR_MASK)
  2196. cas_abnormal_irq(dev, cp, status);
  2197. if (status & INTR_RX_BUF_UNAVAIL) {
  2198. /* Frame arrived, no free RX buffers available.
  2199. * NOTE: we can get this on a link transition.
  2200. */
  2201. cas_post_rxds_ringN(cp, 0, 0);
  2202. spin_lock(&cp->stat_lock[0]);
  2203. cp->net_stats[0].rx_dropped++;
  2204. spin_unlock(&cp->stat_lock[0]);
  2205. } else if (status & INTR_RX_BUF_AE) {
  2206. cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
  2207. RX_AE_FREEN_VAL(0));
  2208. }
  2209. if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
  2210. cas_post_rxcs_ringN(dev, cp, 0);
  2211. }
  2212. static irqreturn_t cas_interrupt(int irq, void *dev_id)
  2213. {
  2214. struct net_device *dev = dev_id;
  2215. struct cas *cp = netdev_priv(dev);
  2216. unsigned long flags;
  2217. u32 status = readl(cp->regs + REG_INTR_STATUS);
  2218. if (status == 0)
  2219. return IRQ_NONE;
  2220. spin_lock_irqsave(&cp->lock, flags);
  2221. if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
  2222. cas_tx(dev, cp, status);
  2223. status &= ~(INTR_TX_ALL | INTR_TX_INTME);
  2224. }
  2225. if (status & INTR_RX_DONE) {
  2226. #ifdef USE_NAPI
  2227. cas_mask_intr(cp);
  2228. napi_schedule(&cp->napi);
  2229. #else
  2230. cas_rx_ringN(cp, 0, 0);
  2231. #endif
  2232. status &= ~INTR_RX_DONE;
  2233. }
  2234. if (status)
  2235. cas_handle_irq(dev, cp, status);
  2236. spin_unlock_irqrestore(&cp->lock, flags);
  2237. return IRQ_HANDLED;
  2238. }
  2239. #ifdef USE_NAPI
  2240. static int cas_poll(struct napi_struct *napi, int budget)
  2241. {
  2242. struct cas *cp = container_of(napi, struct cas, napi);
  2243. struct net_device *dev = cp->dev;
  2244. int i, enable_intr, credits;
  2245. u32 status = readl(cp->regs + REG_INTR_STATUS);
  2246. unsigned long flags;
  2247. spin_lock_irqsave(&cp->lock, flags);
  2248. cas_tx(dev, cp, status);
  2249. spin_unlock_irqrestore(&cp->lock, flags);
  2250. /* NAPI rx packets. we spread the credits across all of the
  2251. * rxc rings
  2252. *
  2253. * to make sure we're fair with the work we loop through each
  2254. * ring N_RX_COMP_RING times with a request of
  2255. * budget / N_RX_COMP_RINGS
  2256. */
  2257. enable_intr = 1;
  2258. credits = 0;
  2259. for (i = 0; i < N_RX_COMP_RINGS; i++) {
  2260. int j;
  2261. for (j = 0; j < N_RX_COMP_RINGS; j++) {
  2262. credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
  2263. if (credits >= budget) {
  2264. enable_intr = 0;
  2265. goto rx_comp;
  2266. }
  2267. }
  2268. }
  2269. rx_comp:
  2270. /* final rx completion */
  2271. spin_lock_irqsave(&cp->lock, flags);
  2272. if (status)
  2273. cas_handle_irq(dev, cp, status);
  2274. #ifdef USE_PCI_INTB
  2275. if (N_RX_COMP_RINGS > 1) {
  2276. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
  2277. if (status)
  2278. cas_handle_irq1(dev, cp, status);
  2279. }
  2280. #endif
  2281. #ifdef USE_PCI_INTC
  2282. if (N_RX_COMP_RINGS > 2) {
  2283. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
  2284. if (status)
  2285. cas_handle_irqN(dev, cp, status, 2);
  2286. }
  2287. #endif
  2288. #ifdef USE_PCI_INTD
  2289. if (N_RX_COMP_RINGS > 3) {
  2290. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
  2291. if (status)
  2292. cas_handle_irqN(dev, cp, status, 3);
  2293. }
  2294. #endif
  2295. spin_unlock_irqrestore(&cp->lock, flags);
  2296. if (enable_intr) {
  2297. napi_complete(napi);
  2298. cas_unmask_intr(cp);
  2299. }
  2300. return credits;
  2301. }
  2302. #endif
  2303. #ifdef CONFIG_NET_POLL_CONTROLLER
  2304. static void cas_netpoll(struct net_device *dev)
  2305. {
  2306. struct cas *cp = netdev_priv(dev);
  2307. cas_disable_irq(cp, 0);
  2308. cas_interrupt(cp->pdev->irq, dev);
  2309. cas_enable_irq(cp, 0);
  2310. #ifdef USE_PCI_INTB
  2311. if (N_RX_COMP_RINGS > 1) {
  2312. /* cas_interrupt1(); */
  2313. }
  2314. #endif
  2315. #ifdef USE_PCI_INTC
  2316. if (N_RX_COMP_RINGS > 2) {
  2317. /* cas_interruptN(); */
  2318. }
  2319. #endif
  2320. #ifdef USE_PCI_INTD
  2321. if (N_RX_COMP_RINGS > 3) {
  2322. /* cas_interruptN(); */
  2323. }
  2324. #endif
  2325. }
  2326. #endif
  2327. static void cas_tx_timeout(struct net_device *dev)
  2328. {
  2329. struct cas *cp = netdev_priv(dev);
  2330. netdev_err(dev, "transmit timed out, resetting\n");
  2331. if (!cp->hw_running) {
  2332. netdev_err(dev, "hrm.. hw not running!\n");
  2333. return;
  2334. }
  2335. netdev_err(dev, "MIF_STATE[%08x]\n",
  2336. readl(cp->regs + REG_MIF_STATE_MACHINE));
  2337. netdev_err(dev, "MAC_STATE[%08x]\n",
  2338. readl(cp->regs + REG_MAC_STATE_MACHINE));
  2339. netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
  2340. readl(cp->regs + REG_TX_CFG),
  2341. readl(cp->regs + REG_MAC_TX_STATUS),
  2342. readl(cp->regs + REG_MAC_TX_CFG),
  2343. readl(cp->regs + REG_TX_FIFO_PKT_CNT),
  2344. readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
  2345. readl(cp->regs + REG_TX_FIFO_READ_PTR),
  2346. readl(cp->regs + REG_TX_SM_1),
  2347. readl(cp->regs + REG_TX_SM_2));
  2348. netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
  2349. readl(cp->regs + REG_RX_CFG),
  2350. readl(cp->regs + REG_MAC_RX_STATUS),
  2351. readl(cp->regs + REG_MAC_RX_CFG));
  2352. netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
  2353. readl(cp->regs + REG_HP_STATE_MACHINE),
  2354. readl(cp->regs + REG_HP_STATUS0),
  2355. readl(cp->regs + REG_HP_STATUS1),
  2356. readl(cp->regs + REG_HP_STATUS2));
  2357. #if 1
  2358. atomic_inc(&cp->reset_task_pending);
  2359. atomic_inc(&cp->reset_task_pending_all);
  2360. schedule_work(&cp->reset_task);
  2361. #else
  2362. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  2363. schedule_work(&cp->reset_task);
  2364. #endif
  2365. }
  2366. static inline int cas_intme(int ring, int entry)
  2367. {
  2368. /* Algorithm: IRQ every 1/2 of descriptors. */
  2369. if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
  2370. return 1;
  2371. return 0;
  2372. }
  2373. static void cas_write_txd(struct cas *cp, int ring, int entry,
  2374. dma_addr_t mapping, int len, u64 ctrl, int last)
  2375. {
  2376. struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
  2377. ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
  2378. if (cas_intme(ring, entry))
  2379. ctrl |= TX_DESC_INTME;
  2380. if (last)
  2381. ctrl |= TX_DESC_EOF;
  2382. txd->control = cpu_to_le64(ctrl);
  2383. txd->buffer = cpu_to_le64(mapping);
  2384. }
  2385. static inline void *tx_tiny_buf(struct cas *cp, const int ring,
  2386. const int entry)
  2387. {
  2388. return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
  2389. }
  2390. static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
  2391. const int entry, const int tentry)
  2392. {
  2393. cp->tx_tiny_use[ring][tentry].nbufs++;
  2394. cp->tx_tiny_use[ring][entry].used = 1;
  2395. return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
  2396. }
  2397. static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
  2398. struct sk_buff *skb)
  2399. {
  2400. struct net_device *dev = cp->dev;
  2401. int entry, nr_frags, frag, tabort, tentry;
  2402. dma_addr_t mapping;
  2403. unsigned long flags;
  2404. u64 ctrl;
  2405. u32 len;
  2406. spin_lock_irqsave(&cp->tx_lock[ring], flags);
  2407. /* This is a hard error, log it. */
  2408. if (TX_BUFFS_AVAIL(cp, ring) <=
  2409. CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
  2410. netif_stop_queue(dev);
  2411. spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
  2412. netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
  2413. return 1;
  2414. }
  2415. ctrl = 0;
  2416. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2417. const u64 csum_start_off = skb_checksum_start_offset(skb);
  2418. const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
  2419. ctrl = TX_DESC_CSUM_EN |
  2420. CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
  2421. CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
  2422. }
  2423. entry = cp->tx_new[ring];
  2424. cp->tx_skbs[ring][entry] = skb;
  2425. nr_frags = skb_shinfo(skb)->nr_frags;
  2426. len = skb_headlen(skb);
  2427. mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
  2428. offset_in_page(skb->data), len,
  2429. PCI_DMA_TODEVICE);
  2430. tentry = entry;
  2431. tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
  2432. if (unlikely(tabort)) {
  2433. /* NOTE: len is always > tabort */
  2434. cas_write_txd(cp, ring, entry, mapping, len - tabort,
  2435. ctrl | TX_DESC_SOF, 0);
  2436. entry = TX_DESC_NEXT(ring, entry);
  2437. skb_copy_from_linear_data_offset(skb, len - tabort,
  2438. tx_tiny_buf(cp, ring, entry), tabort);
  2439. mapping = tx_tiny_map(cp, ring, entry, tentry);
  2440. cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
  2441. (nr_frags == 0));
  2442. } else {
  2443. cas_write_txd(cp, ring, entry, mapping, len, ctrl |
  2444. TX_DESC_SOF, (nr_frags == 0));
  2445. }
  2446. entry = TX_DESC_NEXT(ring, entry);
  2447. for (frag = 0; frag < nr_frags; frag++) {
  2448. skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
  2449. len = fragp->size;
  2450. mapping = pci_map_page(cp->pdev, fragp->page,
  2451. fragp->page_offset, len,
  2452. PCI_DMA_TODEVICE);
  2453. tabort = cas_calc_tabort(cp, fragp->page_offset, len);
  2454. if (unlikely(tabort)) {
  2455. void *addr;
  2456. /* NOTE: len is always > tabort */
  2457. cas_write_txd(cp, ring, entry, mapping, len - tabort,
  2458. ctrl, 0);
  2459. entry = TX_DESC_NEXT(ring, entry);
  2460. addr = cas_page_map(fragp->page);
  2461. memcpy(tx_tiny_buf(cp, ring, entry),
  2462. addr + fragp->page_offset + len - tabort,
  2463. tabort);
  2464. cas_page_unmap(addr);
  2465. mapping = tx_tiny_map(cp, ring, entry, tentry);
  2466. len = tabort;
  2467. }
  2468. cas_write_txd(cp, ring, entry, mapping, len, ctrl,
  2469. (frag + 1 == nr_frags));
  2470. entry = TX_DESC_NEXT(ring, entry);
  2471. }
  2472. cp->tx_new[ring] = entry;
  2473. if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
  2474. netif_stop_queue(dev);
  2475. netif_printk(cp, tx_queued, KERN_DEBUG, dev,
  2476. "tx[%d] queued, slot %d, skblen %d, avail %d\n",
  2477. ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
  2478. writel(entry, cp->regs + REG_TX_KICKN(ring));
  2479. spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
  2480. return 0;
  2481. }
  2482. static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2483. {
  2484. struct cas *cp = netdev_priv(dev);
  2485. /* this is only used as a load-balancing hint, so it doesn't
  2486. * need to be SMP safe
  2487. */
  2488. static int ring;
  2489. if (skb_padto(skb, cp->min_frame_size))
  2490. return NETDEV_TX_OK;
  2491. /* XXX: we need some higher-level QoS hooks to steer packets to
  2492. * individual queues.
  2493. */
  2494. if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
  2495. return NETDEV_TX_BUSY;
  2496. return NETDEV_TX_OK;
  2497. }
  2498. static void cas_init_tx_dma(struct cas *cp)
  2499. {
  2500. u64 desc_dma = cp->block_dvma;
  2501. unsigned long off;
  2502. u32 val;
  2503. int i;
  2504. /* set up tx completion writeback registers. must be 8-byte aligned */
  2505. #ifdef USE_TX_COMPWB
  2506. off = offsetof(struct cas_init_block, tx_compwb);
  2507. writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
  2508. writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
  2509. #endif
  2510. /* enable completion writebacks, enable paced mode,
  2511. * disable read pipe, and disable pre-interrupt compwbs
  2512. */
  2513. val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
  2514. TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
  2515. TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
  2516. TX_CFG_INTR_COMPWB_DIS;
  2517. /* write out tx ring info and tx desc bases */
  2518. for (i = 0; i < MAX_TX_RINGS; i++) {
  2519. off = (unsigned long) cp->init_txds[i] -
  2520. (unsigned long) cp->init_block;
  2521. val |= CAS_TX_RINGN_BASE(i);
  2522. writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
  2523. writel((desc_dma + off) & 0xffffffff, cp->regs +
  2524. REG_TX_DBN_LOW(i));
  2525. /* don't zero out the kick register here as the system
  2526. * will wedge
  2527. */
  2528. }
  2529. writel(val, cp->regs + REG_TX_CFG);
  2530. /* program max burst sizes. these numbers should be different
  2531. * if doing QoS.
  2532. */
  2533. #ifdef USE_QOS
  2534. writel(0x800, cp->regs + REG_TX_MAXBURST_0);
  2535. writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
  2536. writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
  2537. writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
  2538. #else
  2539. writel(0x800, cp->regs + REG_TX_MAXBURST_0);
  2540. writel(0x800, cp->regs + REG_TX_MAXBURST_1);
  2541. writel(0x800, cp->regs + REG_TX_MAXBURST_2);
  2542. writel(0x800, cp->regs + REG_TX_MAXBURST_3);
  2543. #endif
  2544. }
  2545. /* Must be invoked under cp->lock. */
  2546. static inline void cas_init_dma(struct cas *cp)
  2547. {
  2548. cas_init_tx_dma(cp);
  2549. cas_init_rx_dma(cp);
  2550. }
  2551. static void cas_process_mc_list(struct cas *cp)
  2552. {
  2553. u16 hash_table[16];
  2554. u32 crc;
  2555. struct netdev_hw_addr *ha;
  2556. int i = 1;
  2557. memset(hash_table, 0, sizeof(hash_table));
  2558. netdev_for_each_mc_addr(ha, cp->dev) {
  2559. if (i <= CAS_MC_EXACT_MATCH_SIZE) {
  2560. /* use the alternate mac address registers for the
  2561. * first 15 multicast addresses
  2562. */
  2563. writel((ha->addr[4] << 8) | ha->addr[5],
  2564. cp->regs + REG_MAC_ADDRN(i*3 + 0));
  2565. writel((ha->addr[2] << 8) | ha->addr[3],
  2566. cp->regs + REG_MAC_ADDRN(i*3 + 1));
  2567. writel((ha->addr[0] << 8) | ha->addr[1],
  2568. cp->regs + REG_MAC_ADDRN(i*3 + 2));
  2569. i++;
  2570. }
  2571. else {
  2572. /* use hw hash table for the next series of
  2573. * multicast addresses
  2574. */
  2575. crc = ether_crc_le(ETH_ALEN, ha->addr);
  2576. crc >>= 24;
  2577. hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
  2578. }
  2579. }
  2580. for (i = 0; i < 16; i++)
  2581. writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
  2582. }
  2583. /* Must be invoked under cp->lock. */
  2584. static u32 cas_setup_multicast(struct cas *cp)
  2585. {
  2586. u32 rxcfg = 0;
  2587. int i;
  2588. if (cp->dev->flags & IFF_PROMISC) {
  2589. rxcfg |= MAC_RX_CFG_PROMISC_EN;
  2590. } else if (cp->dev->flags & IFF_ALLMULTI) {
  2591. for (i=0; i < 16; i++)
  2592. writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
  2593. rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
  2594. } else {
  2595. cas_process_mc_list(cp);
  2596. rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
  2597. }
  2598. return rxcfg;
  2599. }
  2600. /* must be invoked under cp->stat_lock[N_TX_RINGS] */
  2601. static void cas_clear_mac_err(struct cas *cp)
  2602. {
  2603. writel(0, cp->regs + REG_MAC_COLL_NORMAL);
  2604. writel(0, cp->regs + REG_MAC_COLL_FIRST);
  2605. writel(0, cp->regs + REG_MAC_COLL_EXCESS);
  2606. writel(0, cp->regs + REG_MAC_COLL_LATE);
  2607. writel(0, cp->regs + REG_MAC_TIMER_DEFER);
  2608. writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
  2609. writel(0, cp->regs + REG_MAC_RECV_FRAME);
  2610. writel(0, cp->regs + REG_MAC_LEN_ERR);
  2611. writel(0, cp->regs + REG_MAC_ALIGN_ERR);
  2612. writel(0, cp->regs + REG_MAC_FCS_ERR);
  2613. writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
  2614. }
  2615. static void cas_mac_reset(struct cas *cp)
  2616. {
  2617. int i;
  2618. /* do both TX and RX reset */
  2619. writel(0x1, cp->regs + REG_MAC_TX_RESET);
  2620. writel(0x1, cp->regs + REG_MAC_RX_RESET);
  2621. /* wait for TX */
  2622. i = STOP_TRIES;
  2623. while (i-- > 0) {
  2624. if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
  2625. break;
  2626. udelay(10);
  2627. }
  2628. /* wait for RX */
  2629. i = STOP_TRIES;
  2630. while (i-- > 0) {
  2631. if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
  2632. break;
  2633. udelay(10);
  2634. }
  2635. if (readl(cp->regs + REG_MAC_TX_RESET) |
  2636. readl(cp->regs + REG_MAC_RX_RESET))
  2637. netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
  2638. readl(cp->regs + REG_MAC_TX_RESET),
  2639. readl(cp->regs + REG_MAC_RX_RESET),
  2640. readl(cp->regs + REG_MAC_STATE_MACHINE));
  2641. }
  2642. /* Must be invoked under cp->lock. */
  2643. static void cas_init_mac(struct cas *cp)
  2644. {
  2645. unsigned char *e = &cp->dev->dev_addr[0];
  2646. int i;
  2647. cas_mac_reset(cp);
  2648. /* setup core arbitration weight register */
  2649. writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
  2650. /* XXX Use pci_dma_burst_advice() */
  2651. #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
  2652. /* set the infinite burst register for chips that don't have
  2653. * pci issues.
  2654. */
  2655. if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
  2656. writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
  2657. #endif
  2658. writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
  2659. writel(0x00, cp->regs + REG_MAC_IPG0);
  2660. writel(0x08, cp->regs + REG_MAC_IPG1);
  2661. writel(0x04, cp->regs + REG_MAC_IPG2);
  2662. /* change later for 802.3z */
  2663. writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
  2664. /* min frame + FCS */
  2665. writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
  2666. /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
  2667. * specify the maximum frame size to prevent RX tag errors on
  2668. * oversized frames.
  2669. */
  2670. writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
  2671. CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
  2672. (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
  2673. cp->regs + REG_MAC_FRAMESIZE_MAX);
  2674. /* NOTE: crc_size is used as a surrogate for half-duplex.
  2675. * workaround saturn half-duplex issue by increasing preamble
  2676. * size to 65 bytes.
  2677. */
  2678. if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
  2679. writel(0x41, cp->regs + REG_MAC_PA_SIZE);
  2680. else
  2681. writel(0x07, cp->regs + REG_MAC_PA_SIZE);
  2682. writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
  2683. writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
  2684. writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
  2685. writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
  2686. writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
  2687. writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
  2688. writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
  2689. writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
  2690. writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
  2691. /* setup mac address in perfect filter array */
  2692. for (i = 0; i < 45; i++)
  2693. writel(0x0, cp->regs + REG_MAC_ADDRN(i));
  2694. writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
  2695. writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
  2696. writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
  2697. writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
  2698. writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
  2699. writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
  2700. cp->mac_rx_cfg = cas_setup_multicast(cp);
  2701. spin_lock(&cp->stat_lock[N_TX_RINGS]);
  2702. cas_clear_mac_err(cp);
  2703. spin_unlock(&cp->stat_lock[N_TX_RINGS]);
  2704. /* Setup MAC interrupts. We want to get all of the interesting
  2705. * counter expiration events, but we do not want to hear about
  2706. * normal rx/tx as the DMA engine tells us that.
  2707. */
  2708. writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
  2709. writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
  2710. /* Don't enable even the PAUSE interrupts for now, we
  2711. * make no use of those events other than to record them.
  2712. */
  2713. writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
  2714. }
  2715. /* Must be invoked under cp->lock. */
  2716. static void cas_init_pause_thresholds(struct cas *cp)
  2717. {
  2718. /* Calculate pause thresholds. Setting the OFF threshold to the
  2719. * full RX fifo size effectively disables PAUSE generation
  2720. */
  2721. if (cp->rx_fifo_size <= (2 * 1024)) {
  2722. cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
  2723. } else {
  2724. int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
  2725. if (max_frame * 3 > cp->rx_fifo_size) {
  2726. cp->rx_pause_off = 7104;
  2727. cp->rx_pause_on = 960;
  2728. } else {
  2729. int off = (cp->rx_fifo_size - (max_frame * 2));
  2730. int on = off - max_frame;
  2731. cp->rx_pause_off = off;
  2732. cp->rx_pause_on = on;
  2733. }
  2734. }
  2735. }
  2736. static int cas_vpd_match(const void __iomem *p, const char *str)
  2737. {
  2738. int len = strlen(str) + 1;
  2739. int i;
  2740. for (i = 0; i < len; i++) {
  2741. if (readb(p + i) != str[i])
  2742. return 0;
  2743. }
  2744. return 1;
  2745. }
  2746. /* get the mac address by reading the vpd information in the rom.
  2747. * also get the phy type and determine if there's an entropy generator.
  2748. * NOTE: this is a bit convoluted for the following reasons:
  2749. * 1) vpd info has order-dependent mac addresses for multinic cards
  2750. * 2) the only way to determine the nic order is to use the slot
  2751. * number.
  2752. * 3) fiber cards don't have bridges, so their slot numbers don't
  2753. * mean anything.
  2754. * 4) we don't actually know we have a fiber card until after
  2755. * the mac addresses are parsed.
  2756. */
  2757. static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
  2758. const int offset)
  2759. {
  2760. void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
  2761. void __iomem *base, *kstart;
  2762. int i, len;
  2763. int found = 0;
  2764. #define VPD_FOUND_MAC 0x01
  2765. #define VPD_FOUND_PHY 0x02
  2766. int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
  2767. int mac_off = 0;
  2768. #if defined(CONFIG_SPARC)
  2769. const unsigned char *addr;
  2770. #endif
  2771. /* give us access to the PROM */
  2772. writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
  2773. cp->regs + REG_BIM_LOCAL_DEV_EN);
  2774. /* check for an expansion rom */
  2775. if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
  2776. goto use_random_mac_addr;
  2777. /* search for beginning of vpd */
  2778. base = NULL;
  2779. for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
  2780. /* check for PCIR */
  2781. if ((readb(p + i + 0) == 0x50) &&
  2782. (readb(p + i + 1) == 0x43) &&
  2783. (readb(p + i + 2) == 0x49) &&
  2784. (readb(p + i + 3) == 0x52)) {
  2785. base = p + (readb(p + i + 8) |
  2786. (readb(p + i + 9) << 8));
  2787. break;
  2788. }
  2789. }
  2790. if (!base || (readb(base) != 0x82))
  2791. goto use_random_mac_addr;
  2792. i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
  2793. while (i < EXPANSION_ROM_SIZE) {
  2794. if (readb(base + i) != 0x90) /* no vpd found */
  2795. goto use_random_mac_addr;
  2796. /* found a vpd field */
  2797. len = readb(base + i + 1) | (readb(base + i + 2) << 8);
  2798. /* extract keywords */
  2799. kstart = base + i + 3;
  2800. p = kstart;
  2801. while ((p - kstart) < len) {
  2802. int klen = readb(p + 2);
  2803. int j;
  2804. char type;
  2805. p += 3;
  2806. /* look for the following things:
  2807. * -- correct length == 29
  2808. * 3 (type) + 2 (size) +
  2809. * 18 (strlen("local-mac-address") + 1) +
  2810. * 6 (mac addr)
  2811. * -- VPD Instance 'I'
  2812. * -- VPD Type Bytes 'B'
  2813. * -- VPD data length == 6
  2814. * -- property string == local-mac-address
  2815. *
  2816. * -- correct length == 24
  2817. * 3 (type) + 2 (size) +
  2818. * 12 (strlen("entropy-dev") + 1) +
  2819. * 7 (strlen("vms110") + 1)
  2820. * -- VPD Instance 'I'
  2821. * -- VPD Type String 'B'
  2822. * -- VPD data length == 7
  2823. * -- property string == entropy-dev
  2824. *
  2825. * -- correct length == 18
  2826. * 3 (type) + 2 (size) +
  2827. * 9 (strlen("phy-type") + 1) +
  2828. * 4 (strlen("pcs") + 1)
  2829. * -- VPD Instance 'I'
  2830. * -- VPD Type String 'S'
  2831. * -- VPD data length == 4
  2832. * -- property string == phy-type
  2833. *
  2834. * -- correct length == 23
  2835. * 3 (type) + 2 (size) +
  2836. * 14 (strlen("phy-interface") + 1) +
  2837. * 4 (strlen("pcs") + 1)
  2838. * -- VPD Instance 'I'
  2839. * -- VPD Type String 'S'
  2840. * -- VPD data length == 4
  2841. * -- property string == phy-interface
  2842. */
  2843. if (readb(p) != 'I')
  2844. goto next;
  2845. /* finally, check string and length */
  2846. type = readb(p + 3);
  2847. if (type == 'B') {
  2848. if ((klen == 29) && readb(p + 4) == 6 &&
  2849. cas_vpd_match(p + 5,
  2850. "local-mac-address")) {
  2851. if (mac_off++ > offset)
  2852. goto next;
  2853. /* set mac address */
  2854. for (j = 0; j < 6; j++)
  2855. dev_addr[j] =
  2856. readb(p + 23 + j);
  2857. goto found_mac;
  2858. }
  2859. }
  2860. if (type != 'S')
  2861. goto next;
  2862. #ifdef USE_ENTROPY_DEV
  2863. if ((klen == 24) &&
  2864. cas_vpd_match(p + 5, "entropy-dev") &&
  2865. cas_vpd_match(p + 17, "vms110")) {
  2866. cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
  2867. goto next;
  2868. }
  2869. #endif
  2870. if (found & VPD_FOUND_PHY)
  2871. goto next;
  2872. if ((klen == 18) && readb(p + 4) == 4 &&
  2873. cas_vpd_match(p + 5, "phy-type")) {
  2874. if (cas_vpd_match(p + 14, "pcs")) {
  2875. phy_type = CAS_PHY_SERDES;
  2876. goto found_phy;
  2877. }
  2878. }
  2879. if ((klen == 23) && readb(p + 4) == 4 &&
  2880. cas_vpd_match(p + 5, "phy-interface")) {
  2881. if (cas_vpd_match(p + 19, "pcs")) {
  2882. phy_type = CAS_PHY_SERDES;
  2883. goto found_phy;
  2884. }
  2885. }
  2886. found_mac:
  2887. found |= VPD_FOUND_MAC;
  2888. goto next;
  2889. found_phy:
  2890. found |= VPD_FOUND_PHY;
  2891. next:
  2892. p += klen;
  2893. }
  2894. i += len + 3;
  2895. }
  2896. use_random_mac_addr:
  2897. if (found & VPD_FOUND_MAC)
  2898. goto done;
  2899. #if defined(CONFIG_SPARC)
  2900. addr = of_get_property(cp->of_node, "local-mac-address", NULL);
  2901. if (addr != NULL) {
  2902. memcpy(dev_addr, addr, 6);
  2903. goto done;
  2904. }
  2905. #endif
  2906. /* Sun MAC prefix then 3 random bytes. */
  2907. pr_info("MAC address not found in ROM VPD\n");
  2908. dev_addr[0] = 0x08;
  2909. dev_addr[1] = 0x00;
  2910. dev_addr[2] = 0x20;
  2911. get_random_bytes(dev_addr + 3, 3);
  2912. done:
  2913. writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
  2914. return phy_type;
  2915. }
  2916. /* check pci invariants */
  2917. static void cas_check_pci_invariants(struct cas *cp)
  2918. {
  2919. struct pci_dev *pdev = cp->pdev;
  2920. cp->cas_flags = 0;
  2921. if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
  2922. (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
  2923. if (pdev->revision >= CAS_ID_REVPLUS)
  2924. cp->cas_flags |= CAS_FLAG_REG_PLUS;
  2925. if (pdev->revision < CAS_ID_REVPLUS02u)
  2926. cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
  2927. /* Original Cassini supports HW CSUM, but it's not
  2928. * enabled by default as it can trigger TX hangs.
  2929. */
  2930. if (pdev->revision < CAS_ID_REV2)
  2931. cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
  2932. } else {
  2933. /* Only sun has original cassini chips. */
  2934. cp->cas_flags |= CAS_FLAG_REG_PLUS;
  2935. /* We use a flag because the same phy might be externally
  2936. * connected.
  2937. */
  2938. if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
  2939. (pdev->device == PCI_DEVICE_ID_NS_SATURN))
  2940. cp->cas_flags |= CAS_FLAG_SATURN;
  2941. }
  2942. }
  2943. static int cas_check_invariants(struct cas *cp)
  2944. {
  2945. struct pci_dev *pdev = cp->pdev;
  2946. u32 cfg;
  2947. int i;
  2948. /* get page size for rx buffers. */
  2949. cp->page_order = 0;
  2950. #ifdef USE_PAGE_ORDER
  2951. if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
  2952. /* see if we can allocate larger pages */
  2953. struct page *page = alloc_pages(GFP_ATOMIC,
  2954. CAS_JUMBO_PAGE_SHIFT -
  2955. PAGE_SHIFT);
  2956. if (page) {
  2957. __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
  2958. cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
  2959. } else {
  2960. printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
  2961. }
  2962. }
  2963. #endif
  2964. cp->page_size = (PAGE_SIZE << cp->page_order);
  2965. /* Fetch the FIFO configurations. */
  2966. cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
  2967. cp->rx_fifo_size = RX_FIFO_SIZE;
  2968. /* finish phy determination. MDIO1 takes precedence over MDIO0 if
  2969. * they're both connected.
  2970. */
  2971. cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
  2972. PCI_SLOT(pdev->devfn));
  2973. if (cp->phy_type & CAS_PHY_SERDES) {
  2974. cp->cas_flags |= CAS_FLAG_1000MB_CAP;
  2975. return 0; /* no more checking needed */
  2976. }
  2977. /* MII */
  2978. cfg = readl(cp->regs + REG_MIF_CFG);
  2979. if (cfg & MIF_CFG_MDIO_1) {
  2980. cp->phy_type = CAS_PHY_MII_MDIO1;
  2981. } else if (cfg & MIF_CFG_MDIO_0) {
  2982. cp->phy_type = CAS_PHY_MII_MDIO0;
  2983. }
  2984. cas_mif_poll(cp, 0);
  2985. writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
  2986. for (i = 0; i < 32; i++) {
  2987. u32 phy_id;
  2988. int j;
  2989. for (j = 0; j < 3; j++) {
  2990. cp->phy_addr = i;
  2991. phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
  2992. phy_id |= cas_phy_read(cp, MII_PHYSID2);
  2993. if (phy_id && (phy_id != 0xFFFFFFFF)) {
  2994. cp->phy_id = phy_id;
  2995. goto done;
  2996. }
  2997. }
  2998. }
  2999. pr_err("MII phy did not respond [%08x]\n",
  3000. readl(cp->regs + REG_MIF_STATE_MACHINE));
  3001. return -1;
  3002. done:
  3003. /* see if we can do gigabit */
  3004. cfg = cas_phy_read(cp, MII_BMSR);
  3005. if ((cfg & CAS_BMSR_1000_EXTEND) &&
  3006. cas_phy_read(cp, CAS_MII_1000_EXTEND))
  3007. cp->cas_flags |= CAS_FLAG_1000MB_CAP;
  3008. return 0;
  3009. }
  3010. /* Must be invoked under cp->lock. */
  3011. static inline void cas_start_dma(struct cas *cp)
  3012. {
  3013. int i;
  3014. u32 val;
  3015. int txfailed = 0;
  3016. /* enable dma */
  3017. val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
  3018. writel(val, cp->regs + REG_TX_CFG);
  3019. val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
  3020. writel(val, cp->regs + REG_RX_CFG);
  3021. /* enable the mac */
  3022. val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
  3023. writel(val, cp->regs + REG_MAC_TX_CFG);
  3024. val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
  3025. writel(val, cp->regs + REG_MAC_RX_CFG);
  3026. i = STOP_TRIES;
  3027. while (i-- > 0) {
  3028. val = readl(cp->regs + REG_MAC_TX_CFG);
  3029. if ((val & MAC_TX_CFG_EN))
  3030. break;
  3031. udelay(10);
  3032. }
  3033. if (i < 0) txfailed = 1;
  3034. i = STOP_TRIES;
  3035. while (i-- > 0) {
  3036. val = readl(cp->regs + REG_MAC_RX_CFG);
  3037. if ((val & MAC_RX_CFG_EN)) {
  3038. if (txfailed) {
  3039. netdev_err(cp->dev,
  3040. "enabling mac failed [tx:%08x:%08x]\n",
  3041. readl(cp->regs + REG_MIF_STATE_MACHINE),
  3042. readl(cp->regs + REG_MAC_STATE_MACHINE));
  3043. }
  3044. goto enable_rx_done;
  3045. }
  3046. udelay(10);
  3047. }
  3048. netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
  3049. (txfailed ? "tx,rx" : "rx"),
  3050. readl(cp->regs + REG_MIF_STATE_MACHINE),
  3051. readl(cp->regs + REG_MAC_STATE_MACHINE));
  3052. enable_rx_done:
  3053. cas_unmask_intr(cp); /* enable interrupts */
  3054. writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
  3055. writel(0, cp->regs + REG_RX_COMP_TAIL);
  3056. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  3057. if (N_RX_DESC_RINGS > 1)
  3058. writel(RX_DESC_RINGN_SIZE(1) - 4,
  3059. cp->regs + REG_PLUS_RX_KICK1);
  3060. for (i = 1; i < N_RX_COMP_RINGS; i++)
  3061. writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
  3062. }
  3063. }
  3064. /* Must be invoked under cp->lock. */
  3065. static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
  3066. int *pause)
  3067. {
  3068. u32 val = readl(cp->regs + REG_PCS_MII_LPA);
  3069. *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
  3070. *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
  3071. if (val & PCS_MII_LPA_ASYM_PAUSE)
  3072. *pause |= 0x10;
  3073. *spd = 1000;
  3074. }
  3075. /* Must be invoked under cp->lock. */
  3076. static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
  3077. int *pause)
  3078. {
  3079. u32 val;
  3080. *fd = 0;
  3081. *spd = 10;
  3082. *pause = 0;
  3083. /* use GMII registers */
  3084. val = cas_phy_read(cp, MII_LPA);
  3085. if (val & CAS_LPA_PAUSE)
  3086. *pause = 0x01;
  3087. if (val & CAS_LPA_ASYM_PAUSE)
  3088. *pause |= 0x10;
  3089. if (val & LPA_DUPLEX)
  3090. *fd = 1;
  3091. if (val & LPA_100)
  3092. *spd = 100;
  3093. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  3094. val = cas_phy_read(cp, CAS_MII_1000_STATUS);
  3095. if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
  3096. *spd = 1000;
  3097. if (val & CAS_LPA_1000FULL)
  3098. *fd = 1;
  3099. }
  3100. }
  3101. /* A link-up condition has occurred, initialize and enable the
  3102. * rest of the chip.
  3103. *
  3104. * Must be invoked under cp->lock.
  3105. */
  3106. static void cas_set_link_modes(struct cas *cp)
  3107. {
  3108. u32 val;
  3109. int full_duplex, speed, pause;
  3110. full_duplex = 0;
  3111. speed = 10;
  3112. pause = 0;
  3113. if (CAS_PHY_MII(cp->phy_type)) {
  3114. cas_mif_poll(cp, 0);
  3115. val = cas_phy_read(cp, MII_BMCR);
  3116. if (val & BMCR_ANENABLE) {
  3117. cas_read_mii_link_mode(cp, &full_duplex, &speed,
  3118. &pause);
  3119. } else {
  3120. if (val & BMCR_FULLDPLX)
  3121. full_duplex = 1;
  3122. if (val & BMCR_SPEED100)
  3123. speed = 100;
  3124. else if (val & CAS_BMCR_SPEED1000)
  3125. speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
  3126. 1000 : 100;
  3127. }
  3128. cas_mif_poll(cp, 1);
  3129. } else {
  3130. val = readl(cp->regs + REG_PCS_MII_CTRL);
  3131. cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
  3132. if ((val & PCS_MII_AUTONEG_EN) == 0) {
  3133. if (val & PCS_MII_CTRL_DUPLEX)
  3134. full_duplex = 1;
  3135. }
  3136. }
  3137. netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
  3138. speed, full_duplex ? "full" : "half");
  3139. val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
  3140. if (CAS_PHY_MII(cp->phy_type)) {
  3141. val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
  3142. if (!full_duplex)
  3143. val |= MAC_XIF_DISABLE_ECHO;
  3144. }
  3145. if (full_duplex)
  3146. val |= MAC_XIF_FDPLX_LED;
  3147. if (speed == 1000)
  3148. val |= MAC_XIF_GMII_MODE;
  3149. writel(val, cp->regs + REG_MAC_XIF_CFG);
  3150. /* deal with carrier and collision detect. */
  3151. val = MAC_TX_CFG_IPG_EN;
  3152. if (full_duplex) {
  3153. val |= MAC_TX_CFG_IGNORE_CARRIER;
  3154. val |= MAC_TX_CFG_IGNORE_COLL;
  3155. } else {
  3156. #ifndef USE_CSMA_CD_PROTO
  3157. val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
  3158. val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
  3159. #endif
  3160. }
  3161. /* val now set up for REG_MAC_TX_CFG */
  3162. /* If gigabit and half-duplex, enable carrier extension
  3163. * mode. increase slot time to 512 bytes as well.
  3164. * else, disable it and make sure slot time is 64 bytes.
  3165. * also activate checksum bug workaround
  3166. */
  3167. if ((speed == 1000) && !full_duplex) {
  3168. writel(val | MAC_TX_CFG_CARRIER_EXTEND,
  3169. cp->regs + REG_MAC_TX_CFG);
  3170. val = readl(cp->regs + REG_MAC_RX_CFG);
  3171. val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
  3172. writel(val | MAC_RX_CFG_CARRIER_EXTEND,
  3173. cp->regs + REG_MAC_RX_CFG);
  3174. writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
  3175. cp->crc_size = 4;
  3176. /* minimum size gigabit frame at half duplex */
  3177. cp->min_frame_size = CAS_1000MB_MIN_FRAME;
  3178. } else {
  3179. writel(val, cp->regs + REG_MAC_TX_CFG);
  3180. /* checksum bug workaround. don't strip FCS when in
  3181. * half-duplex mode
  3182. */
  3183. val = readl(cp->regs + REG_MAC_RX_CFG);
  3184. if (full_duplex) {
  3185. val |= MAC_RX_CFG_STRIP_FCS;
  3186. cp->crc_size = 0;
  3187. cp->min_frame_size = CAS_MIN_MTU;
  3188. } else {
  3189. val &= ~MAC_RX_CFG_STRIP_FCS;
  3190. cp->crc_size = 4;
  3191. cp->min_frame_size = CAS_MIN_FRAME;
  3192. }
  3193. writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
  3194. cp->regs + REG_MAC_RX_CFG);
  3195. writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
  3196. }
  3197. if (netif_msg_link(cp)) {
  3198. if (pause & 0x01) {
  3199. netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
  3200. cp->rx_fifo_size,
  3201. cp->rx_pause_off,
  3202. cp->rx_pause_on);
  3203. } else if (pause & 0x10) {
  3204. netdev_info(cp->dev, "TX pause enabled\n");
  3205. } else {
  3206. netdev_info(cp->dev, "Pause is disabled\n");
  3207. }
  3208. }
  3209. val = readl(cp->regs + REG_MAC_CTRL_CFG);
  3210. val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
  3211. if (pause) { /* symmetric or asymmetric pause */
  3212. val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
  3213. if (pause & 0x01) { /* symmetric pause */
  3214. val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
  3215. }
  3216. }
  3217. writel(val, cp->regs + REG_MAC_CTRL_CFG);
  3218. cas_start_dma(cp);
  3219. }
  3220. /* Must be invoked under cp->lock. */
  3221. static void cas_init_hw(struct cas *cp, int restart_link)
  3222. {
  3223. if (restart_link)
  3224. cas_phy_init(cp);
  3225. cas_init_pause_thresholds(cp);
  3226. cas_init_mac(cp);
  3227. cas_init_dma(cp);
  3228. if (restart_link) {
  3229. /* Default aneg parameters */
  3230. cp->timer_ticks = 0;
  3231. cas_begin_auto_negotiation(cp, NULL);
  3232. } else if (cp->lstate == link_up) {
  3233. cas_set_link_modes(cp);
  3234. netif_carrier_on(cp->dev);
  3235. }
  3236. }
  3237. /* Must be invoked under cp->lock. on earlier cassini boards,
  3238. * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
  3239. * let it settle out, and then restore pci state.
  3240. */
  3241. static void cas_hard_reset(struct cas *cp)
  3242. {
  3243. writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
  3244. udelay(20);
  3245. pci_restore_state(cp->pdev);
  3246. }
  3247. static void cas_global_reset(struct cas *cp, int blkflag)
  3248. {
  3249. int limit;
  3250. /* issue a global reset. don't use RSTOUT. */
  3251. if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
  3252. /* For PCS, when the blkflag is set, we should set the
  3253. * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
  3254. * the last autonegotiation from being cleared. We'll
  3255. * need some special handling if the chip is set into a
  3256. * loopback mode.
  3257. */
  3258. writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
  3259. cp->regs + REG_SW_RESET);
  3260. } else {
  3261. writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
  3262. }
  3263. /* need to wait at least 3ms before polling register */
  3264. mdelay(3);
  3265. limit = STOP_TRIES;
  3266. while (limit-- > 0) {
  3267. u32 val = readl(cp->regs + REG_SW_RESET);
  3268. if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
  3269. goto done;
  3270. udelay(10);
  3271. }
  3272. netdev_err(cp->dev, "sw reset failed\n");
  3273. done:
  3274. /* enable various BIM interrupts */
  3275. writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
  3276. BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
  3277. /* clear out pci error status mask for handled errors.
  3278. * we don't deal with DMA counter overflows as they happen
  3279. * all the time.
  3280. */
  3281. writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
  3282. PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
  3283. PCI_ERR_BIM_DMA_READ), cp->regs +
  3284. REG_PCI_ERR_STATUS_MASK);
  3285. /* set up for MII by default to address mac rx reset timeout
  3286. * issue
  3287. */
  3288. writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
  3289. }
  3290. static void cas_reset(struct cas *cp, int blkflag)
  3291. {
  3292. u32 val;
  3293. cas_mask_intr(cp);
  3294. cas_global_reset(cp, blkflag);
  3295. cas_mac_reset(cp);
  3296. cas_entropy_reset(cp);
  3297. /* disable dma engines. */
  3298. val = readl(cp->regs + REG_TX_CFG);
  3299. val &= ~TX_CFG_DMA_EN;
  3300. writel(val, cp->regs + REG_TX_CFG);
  3301. val = readl(cp->regs + REG_RX_CFG);
  3302. val &= ~RX_CFG_DMA_EN;
  3303. writel(val, cp->regs + REG_RX_CFG);
  3304. /* program header parser */
  3305. if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
  3306. (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
  3307. cas_load_firmware(cp, CAS_HP_FIRMWARE);
  3308. } else {
  3309. cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
  3310. }
  3311. /* clear out error registers */
  3312. spin_lock(&cp->stat_lock[N_TX_RINGS]);
  3313. cas_clear_mac_err(cp);
  3314. spin_unlock(&cp->stat_lock[N_TX_RINGS]);
  3315. }
  3316. /* Shut down the chip, must be called with pm_mutex held. */
  3317. static void cas_shutdown(struct cas *cp)
  3318. {
  3319. unsigned long flags;
  3320. /* Make us not-running to avoid timers respawning */
  3321. cp->hw_running = 0;
  3322. del_timer_sync(&cp->link_timer);
  3323. /* Stop the reset task */
  3324. #if 0
  3325. while (atomic_read(&cp->reset_task_pending_mtu) ||
  3326. atomic_read(&cp->reset_task_pending_spare) ||
  3327. atomic_read(&cp->reset_task_pending_all))
  3328. schedule();
  3329. #else
  3330. while (atomic_read(&cp->reset_task_pending))
  3331. schedule();
  3332. #endif
  3333. /* Actually stop the chip */
  3334. cas_lock_all_save(cp, flags);
  3335. cas_reset(cp, 0);
  3336. if (cp->cas_flags & CAS_FLAG_SATURN)
  3337. cas_phy_powerdown(cp);
  3338. cas_unlock_all_restore(cp, flags);
  3339. }
  3340. static int cas_change_mtu(struct net_device *dev, int new_mtu)
  3341. {
  3342. struct cas *cp = netdev_priv(dev);
  3343. if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
  3344. return -EINVAL;
  3345. dev->mtu = new_mtu;
  3346. if (!netif_running(dev) || !netif_device_present(dev))
  3347. return 0;
  3348. /* let the reset task handle it */
  3349. #if 1
  3350. atomic_inc(&cp->reset_task_pending);
  3351. if ((cp->phy_type & CAS_PHY_SERDES)) {
  3352. atomic_inc(&cp->reset_task_pending_all);
  3353. } else {
  3354. atomic_inc(&cp->reset_task_pending_mtu);
  3355. }
  3356. schedule_work(&cp->reset_task);
  3357. #else
  3358. atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
  3359. CAS_RESET_ALL : CAS_RESET_MTU);
  3360. pr_err("reset called in cas_change_mtu\n");
  3361. schedule_work(&cp->reset_task);
  3362. #endif
  3363. flush_work_sync(&cp->reset_task);
  3364. return 0;
  3365. }
  3366. static void cas_clean_txd(struct cas *cp, int ring)
  3367. {
  3368. struct cas_tx_desc *txd = cp->init_txds[ring];
  3369. struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
  3370. u64 daddr, dlen;
  3371. int i, size;
  3372. size = TX_DESC_RINGN_SIZE(ring);
  3373. for (i = 0; i < size; i++) {
  3374. int frag;
  3375. if (skbs[i] == NULL)
  3376. continue;
  3377. skb = skbs[i];
  3378. skbs[i] = NULL;
  3379. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  3380. int ent = i & (size - 1);
  3381. /* first buffer is never a tiny buffer and so
  3382. * needs to be unmapped.
  3383. */
  3384. daddr = le64_to_cpu(txd[ent].buffer);
  3385. dlen = CAS_VAL(TX_DESC_BUFLEN,
  3386. le64_to_cpu(txd[ent].control));
  3387. pci_unmap_page(cp->pdev, daddr, dlen,
  3388. PCI_DMA_TODEVICE);
  3389. if (frag != skb_shinfo(skb)->nr_frags) {
  3390. i++;
  3391. /* next buffer might by a tiny buffer.
  3392. * skip past it.
  3393. */
  3394. ent = i & (size - 1);
  3395. if (cp->tx_tiny_use[ring][ent].used)
  3396. i++;
  3397. }
  3398. }
  3399. dev_kfree_skb_any(skb);
  3400. }
  3401. /* zero out tiny buf usage */
  3402. memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
  3403. }
  3404. /* freed on close */
  3405. static inline void cas_free_rx_desc(struct cas *cp, int ring)
  3406. {
  3407. cas_page_t **page = cp->rx_pages[ring];
  3408. int i, size;
  3409. size = RX_DESC_RINGN_SIZE(ring);
  3410. for (i = 0; i < size; i++) {
  3411. if (page[i]) {
  3412. cas_page_free(cp, page[i]);
  3413. page[i] = NULL;
  3414. }
  3415. }
  3416. }
  3417. static void cas_free_rxds(struct cas *cp)
  3418. {
  3419. int i;
  3420. for (i = 0; i < N_RX_DESC_RINGS; i++)
  3421. cas_free_rx_desc(cp, i);
  3422. }
  3423. /* Must be invoked under cp->lock. */
  3424. static void cas_clean_rings(struct cas *cp)
  3425. {
  3426. int i;
  3427. /* need to clean all tx rings */
  3428. memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
  3429. memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
  3430. for (i = 0; i < N_TX_RINGS; i++)
  3431. cas_clean_txd(cp, i);
  3432. /* zero out init block */
  3433. memset(cp->init_block, 0, sizeof(struct cas_init_block));
  3434. cas_clean_rxds(cp);
  3435. cas_clean_rxcs(cp);
  3436. }
  3437. /* allocated on open */
  3438. static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
  3439. {
  3440. cas_page_t **page = cp->rx_pages[ring];
  3441. int size, i = 0;
  3442. size = RX_DESC_RINGN_SIZE(ring);
  3443. for (i = 0; i < size; i++) {
  3444. if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
  3445. return -1;
  3446. }
  3447. return 0;
  3448. }
  3449. static int cas_alloc_rxds(struct cas *cp)
  3450. {
  3451. int i;
  3452. for (i = 0; i < N_RX_DESC_RINGS; i++) {
  3453. if (cas_alloc_rx_desc(cp, i) < 0) {
  3454. cas_free_rxds(cp);
  3455. return -1;
  3456. }
  3457. }
  3458. return 0;
  3459. }
  3460. static void cas_reset_task(struct work_struct *work)
  3461. {
  3462. struct cas *cp = container_of(work, struct cas, reset_task);
  3463. #if 0
  3464. int pending = atomic_read(&cp->reset_task_pending);
  3465. #else
  3466. int pending_all = atomic_read(&cp->reset_task_pending_all);
  3467. int pending_spare = atomic_read(&cp->reset_task_pending_spare);
  3468. int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
  3469. if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
  3470. /* We can have more tasks scheduled than actually
  3471. * needed.
  3472. */
  3473. atomic_dec(&cp->reset_task_pending);
  3474. return;
  3475. }
  3476. #endif
  3477. /* The link went down, we reset the ring, but keep
  3478. * DMA stopped. Use this function for reset
  3479. * on error as well.
  3480. */
  3481. if (cp->hw_running) {
  3482. unsigned long flags;
  3483. /* Make sure we don't get interrupts or tx packets */
  3484. netif_device_detach(cp->dev);
  3485. cas_lock_all_save(cp, flags);
  3486. if (cp->opened) {
  3487. /* We call cas_spare_recover when we call cas_open.
  3488. * but we do not initialize the lists cas_spare_recover
  3489. * uses until cas_open is called.
  3490. */
  3491. cas_spare_recover(cp, GFP_ATOMIC);
  3492. }
  3493. #if 1
  3494. /* test => only pending_spare set */
  3495. if (!pending_all && !pending_mtu)
  3496. goto done;
  3497. #else
  3498. if (pending == CAS_RESET_SPARE)
  3499. goto done;
  3500. #endif
  3501. /* when pending == CAS_RESET_ALL, the following
  3502. * call to cas_init_hw will restart auto negotiation.
  3503. * Setting the second argument of cas_reset to
  3504. * !(pending == CAS_RESET_ALL) will set this argument
  3505. * to 1 (avoiding reinitializing the PHY for the normal
  3506. * PCS case) when auto negotiation is not restarted.
  3507. */
  3508. #if 1
  3509. cas_reset(cp, !(pending_all > 0));
  3510. if (cp->opened)
  3511. cas_clean_rings(cp);
  3512. cas_init_hw(cp, (pending_all > 0));
  3513. #else
  3514. cas_reset(cp, !(pending == CAS_RESET_ALL));
  3515. if (cp->opened)
  3516. cas_clean_rings(cp);
  3517. cas_init_hw(cp, pending == CAS_RESET_ALL);
  3518. #endif
  3519. done:
  3520. cas_unlock_all_restore(cp, flags);
  3521. netif_device_attach(cp->dev);
  3522. }
  3523. #if 1
  3524. atomic_sub(pending_all, &cp->reset_task_pending_all);
  3525. atomic_sub(pending_spare, &cp->reset_task_pending_spare);
  3526. atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
  3527. atomic_dec(&cp->reset_task_pending);
  3528. #else
  3529. atomic_set(&cp->reset_task_pending, 0);
  3530. #endif
  3531. }
  3532. static void cas_link_timer(unsigned long data)
  3533. {
  3534. struct cas *cp = (struct cas *) data;
  3535. int mask, pending = 0, reset = 0;
  3536. unsigned long flags;
  3537. if (link_transition_timeout != 0 &&
  3538. cp->link_transition_jiffies_valid &&
  3539. ((jiffies - cp->link_transition_jiffies) >
  3540. (link_transition_timeout))) {
  3541. /* One-second counter so link-down workaround doesn't
  3542. * cause resets to occur so fast as to fool the switch
  3543. * into thinking the link is down.
  3544. */
  3545. cp->link_transition_jiffies_valid = 0;
  3546. }
  3547. if (!cp->hw_running)
  3548. return;
  3549. spin_lock_irqsave(&cp->lock, flags);
  3550. cas_lock_tx(cp);
  3551. cas_entropy_gather(cp);
  3552. /* If the link task is still pending, we just
  3553. * reschedule the link timer
  3554. */
  3555. #if 1
  3556. if (atomic_read(&cp->reset_task_pending_all) ||
  3557. atomic_read(&cp->reset_task_pending_spare) ||
  3558. atomic_read(&cp->reset_task_pending_mtu))
  3559. goto done;
  3560. #else
  3561. if (atomic_read(&cp->reset_task_pending))
  3562. goto done;
  3563. #endif
  3564. /* check for rx cleaning */
  3565. if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
  3566. int i, rmask;
  3567. for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
  3568. rmask = CAS_FLAG_RXD_POST(i);
  3569. if ((mask & rmask) == 0)
  3570. continue;
  3571. /* post_rxds will do a mod_timer */
  3572. if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
  3573. pending = 1;
  3574. continue;
  3575. }
  3576. cp->cas_flags &= ~rmask;
  3577. }
  3578. }
  3579. if (CAS_PHY_MII(cp->phy_type)) {
  3580. u16 bmsr;
  3581. cas_mif_poll(cp, 0);
  3582. bmsr = cas_phy_read(cp, MII_BMSR);
  3583. /* WTZ: Solaris driver reads this twice, but that
  3584. * may be due to the PCS case and the use of a
  3585. * common implementation. Read it twice here to be
  3586. * safe.
  3587. */
  3588. bmsr = cas_phy_read(cp, MII_BMSR);
  3589. cas_mif_poll(cp, 1);
  3590. readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
  3591. reset = cas_mii_link_check(cp, bmsr);
  3592. } else {
  3593. reset = cas_pcs_link_check(cp);
  3594. }
  3595. if (reset)
  3596. goto done;
  3597. /* check for tx state machine confusion */
  3598. if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
  3599. u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
  3600. u32 wptr, rptr;
  3601. int tlm = CAS_VAL(MAC_SM_TLM, val);
  3602. if (((tlm == 0x5) || (tlm == 0x3)) &&
  3603. (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
  3604. netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
  3605. "tx err: MAC_STATE[%08x]\n", val);
  3606. reset = 1;
  3607. goto done;
  3608. }
  3609. val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
  3610. wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
  3611. rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
  3612. if ((val == 0) && (wptr != rptr)) {
  3613. netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
  3614. "tx err: TX_FIFO[%08x:%08x:%08x]\n",
  3615. val, wptr, rptr);
  3616. reset = 1;
  3617. }
  3618. if (reset)
  3619. cas_hard_reset(cp);
  3620. }
  3621. done:
  3622. if (reset) {
  3623. #if 1
  3624. atomic_inc(&cp->reset_task_pending);
  3625. atomic_inc(&cp->reset_task_pending_all);
  3626. schedule_work(&cp->reset_task);
  3627. #else
  3628. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  3629. pr_err("reset called in cas_link_timer\n");
  3630. schedule_work(&cp->reset_task);
  3631. #endif
  3632. }
  3633. if (!pending)
  3634. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  3635. cas_unlock_tx(cp);
  3636. spin_unlock_irqrestore(&cp->lock, flags);
  3637. }
  3638. /* tiny buffers are used to avoid target abort issues with
  3639. * older cassini's
  3640. */
  3641. static void cas_tx_tiny_free(struct cas *cp)
  3642. {
  3643. struct pci_dev *pdev = cp->pdev;
  3644. int i;
  3645. for (i = 0; i < N_TX_RINGS; i++) {
  3646. if (!cp->tx_tiny_bufs[i])
  3647. continue;
  3648. pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
  3649. cp->tx_tiny_bufs[i],
  3650. cp->tx_tiny_dvma[i]);
  3651. cp->tx_tiny_bufs[i] = NULL;
  3652. }
  3653. }
  3654. static int cas_tx_tiny_alloc(struct cas *cp)
  3655. {
  3656. struct pci_dev *pdev = cp->pdev;
  3657. int i;
  3658. for (i = 0; i < N_TX_RINGS; i++) {
  3659. cp->tx_tiny_bufs[i] =
  3660. pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
  3661. &cp->tx_tiny_dvma[i]);
  3662. if (!cp->tx_tiny_bufs[i]) {
  3663. cas_tx_tiny_free(cp);
  3664. return -1;
  3665. }
  3666. }
  3667. return 0;
  3668. }
  3669. static int cas_open(struct net_device *dev)
  3670. {
  3671. struct cas *cp = netdev_priv(dev);
  3672. int hw_was_up, err;
  3673. unsigned long flags;
  3674. mutex_lock(&cp->pm_mutex);
  3675. hw_was_up = cp->hw_running;
  3676. /* The power-management mutex protects the hw_running
  3677. * etc. state so it is safe to do this bit without cp->lock
  3678. */
  3679. if (!cp->hw_running) {
  3680. /* Reset the chip */
  3681. cas_lock_all_save(cp, flags);
  3682. /* We set the second arg to cas_reset to zero
  3683. * because cas_init_hw below will have its second
  3684. * argument set to non-zero, which will force
  3685. * autonegotiation to start.
  3686. */
  3687. cas_reset(cp, 0);
  3688. cp->hw_running = 1;
  3689. cas_unlock_all_restore(cp, flags);
  3690. }
  3691. err = -ENOMEM;
  3692. if (cas_tx_tiny_alloc(cp) < 0)
  3693. goto err_unlock;
  3694. /* alloc rx descriptors */
  3695. if (cas_alloc_rxds(cp) < 0)
  3696. goto err_tx_tiny;
  3697. /* allocate spares */
  3698. cas_spare_init(cp);
  3699. cas_spare_recover(cp, GFP_KERNEL);
  3700. /* We can now request the interrupt as we know it's masked
  3701. * on the controller. cassini+ has up to 4 interrupts
  3702. * that can be used, but you need to do explicit pci interrupt
  3703. * mapping to expose them
  3704. */
  3705. if (request_irq(cp->pdev->irq, cas_interrupt,
  3706. IRQF_SHARED, dev->name, (void *) dev)) {
  3707. netdev_err(cp->dev, "failed to request irq !\n");
  3708. err = -EAGAIN;
  3709. goto err_spare;
  3710. }
  3711. #ifdef USE_NAPI
  3712. napi_enable(&cp->napi);
  3713. #endif
  3714. /* init hw */
  3715. cas_lock_all_save(cp, flags);
  3716. cas_clean_rings(cp);
  3717. cas_init_hw(cp, !hw_was_up);
  3718. cp->opened = 1;
  3719. cas_unlock_all_restore(cp, flags);
  3720. netif_start_queue(dev);
  3721. mutex_unlock(&cp->pm_mutex);
  3722. return 0;
  3723. err_spare:
  3724. cas_spare_free(cp);
  3725. cas_free_rxds(cp);
  3726. err_tx_tiny:
  3727. cas_tx_tiny_free(cp);
  3728. err_unlock:
  3729. mutex_unlock(&cp->pm_mutex);
  3730. return err;
  3731. }
  3732. static int cas_close(struct net_device *dev)
  3733. {
  3734. unsigned long flags;
  3735. struct cas *cp = netdev_priv(dev);
  3736. #ifdef USE_NAPI
  3737. napi_disable(&cp->napi);
  3738. #endif
  3739. /* Make sure we don't get distracted by suspend/resume */
  3740. mutex_lock(&cp->pm_mutex);
  3741. netif_stop_queue(dev);
  3742. /* Stop traffic, mark us closed */
  3743. cas_lock_all_save(cp, flags);
  3744. cp->opened = 0;
  3745. cas_reset(cp, 0);
  3746. cas_phy_init(cp);
  3747. cas_begin_auto_negotiation(cp, NULL);
  3748. cas_clean_rings(cp);
  3749. cas_unlock_all_restore(cp, flags);
  3750. free_irq(cp->pdev->irq, (void *) dev);
  3751. cas_spare_free(cp);
  3752. cas_free_rxds(cp);
  3753. cas_tx_tiny_free(cp);
  3754. mutex_unlock(&cp->pm_mutex);
  3755. return 0;
  3756. }
  3757. static struct {
  3758. const char name[ETH_GSTRING_LEN];
  3759. } ethtool_cassini_statnames[] = {
  3760. {"collisions"},
  3761. {"rx_bytes"},
  3762. {"rx_crc_errors"},
  3763. {"rx_dropped"},
  3764. {"rx_errors"},
  3765. {"rx_fifo_errors"},
  3766. {"rx_frame_errors"},
  3767. {"rx_length_errors"},
  3768. {"rx_over_errors"},
  3769. {"rx_packets"},
  3770. {"tx_aborted_errors"},
  3771. {"tx_bytes"},
  3772. {"tx_dropped"},
  3773. {"tx_errors"},
  3774. {"tx_fifo_errors"},
  3775. {"tx_packets"}
  3776. };
  3777. #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
  3778. static struct {
  3779. const int offsets; /* neg. values for 2nd arg to cas_read_phy */
  3780. } ethtool_register_table[] = {
  3781. {-MII_BMSR},
  3782. {-MII_BMCR},
  3783. {REG_CAWR},
  3784. {REG_INF_BURST},
  3785. {REG_BIM_CFG},
  3786. {REG_RX_CFG},
  3787. {REG_HP_CFG},
  3788. {REG_MAC_TX_CFG},
  3789. {REG_MAC_RX_CFG},
  3790. {REG_MAC_CTRL_CFG},
  3791. {REG_MAC_XIF_CFG},
  3792. {REG_MIF_CFG},
  3793. {REG_PCS_CFG},
  3794. {REG_SATURN_PCFG},
  3795. {REG_PCS_MII_STATUS},
  3796. {REG_PCS_STATE_MACHINE},
  3797. {REG_MAC_COLL_EXCESS},
  3798. {REG_MAC_COLL_LATE}
  3799. };
  3800. #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
  3801. #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
  3802. static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
  3803. {
  3804. u8 *p;
  3805. int i;
  3806. unsigned long flags;
  3807. spin_lock_irqsave(&cp->lock, flags);
  3808. for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
  3809. u16 hval;
  3810. u32 val;
  3811. if (ethtool_register_table[i].offsets < 0) {
  3812. hval = cas_phy_read(cp,
  3813. -ethtool_register_table[i].offsets);
  3814. val = hval;
  3815. } else {
  3816. val= readl(cp->regs+ethtool_register_table[i].offsets);
  3817. }
  3818. memcpy(p, (u8 *)&val, sizeof(u32));
  3819. }
  3820. spin_unlock_irqrestore(&cp->lock, flags);
  3821. }
  3822. static struct net_device_stats *cas_get_stats(struct net_device *dev)
  3823. {
  3824. struct cas *cp = netdev_priv(dev);
  3825. struct net_device_stats *stats = cp->net_stats;
  3826. unsigned long flags;
  3827. int i;
  3828. unsigned long tmp;
  3829. /* we collate all of the stats into net_stats[N_TX_RING] */
  3830. if (!cp->hw_running)
  3831. return stats + N_TX_RINGS;
  3832. /* collect outstanding stats */
  3833. /* WTZ: the Cassini spec gives these as 16 bit counters but
  3834. * stored in 32-bit words. Added a mask of 0xffff to be safe,
  3835. * in case the chip somehow puts any garbage in the other bits.
  3836. * Also, counter usage didn't seem to mach what Adrian did
  3837. * in the parts of the code that set these quantities. Made
  3838. * that consistent.
  3839. */
  3840. spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
  3841. stats[N_TX_RINGS].rx_crc_errors +=
  3842. readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
  3843. stats[N_TX_RINGS].rx_frame_errors +=
  3844. readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
  3845. stats[N_TX_RINGS].rx_length_errors +=
  3846. readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
  3847. #if 1
  3848. tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
  3849. (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
  3850. stats[N_TX_RINGS].tx_aborted_errors += tmp;
  3851. stats[N_TX_RINGS].collisions +=
  3852. tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
  3853. #else
  3854. stats[N_TX_RINGS].tx_aborted_errors +=
  3855. readl(cp->regs + REG_MAC_COLL_EXCESS);
  3856. stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
  3857. readl(cp->regs + REG_MAC_COLL_LATE);
  3858. #endif
  3859. cas_clear_mac_err(cp);
  3860. /* saved bits that are unique to ring 0 */
  3861. spin_lock(&cp->stat_lock[0]);
  3862. stats[N_TX_RINGS].collisions += stats[0].collisions;
  3863. stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
  3864. stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
  3865. stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
  3866. stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
  3867. stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
  3868. spin_unlock(&cp->stat_lock[0]);
  3869. for (i = 0; i < N_TX_RINGS; i++) {
  3870. spin_lock(&cp->stat_lock[i]);
  3871. stats[N_TX_RINGS].rx_length_errors +=
  3872. stats[i].rx_length_errors;
  3873. stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
  3874. stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
  3875. stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
  3876. stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
  3877. stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
  3878. stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
  3879. stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
  3880. stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
  3881. stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
  3882. memset(stats + i, 0, sizeof(struct net_device_stats));
  3883. spin_unlock(&cp->stat_lock[i]);
  3884. }
  3885. spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
  3886. return stats + N_TX_RINGS;
  3887. }
  3888. static void cas_set_multicast(struct net_device *dev)
  3889. {
  3890. struct cas *cp = netdev_priv(dev);
  3891. u32 rxcfg, rxcfg_new;
  3892. unsigned long flags;
  3893. int limit = STOP_TRIES;
  3894. if (!cp->hw_running)
  3895. return;
  3896. spin_lock_irqsave(&cp->lock, flags);
  3897. rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
  3898. /* disable RX MAC and wait for completion */
  3899. writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  3900. while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
  3901. if (!limit--)
  3902. break;
  3903. udelay(10);
  3904. }
  3905. /* disable hash filter and wait for completion */
  3906. limit = STOP_TRIES;
  3907. rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
  3908. writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  3909. while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
  3910. if (!limit--)
  3911. break;
  3912. udelay(10);
  3913. }
  3914. /* program hash filters */
  3915. cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
  3916. rxcfg |= rxcfg_new;
  3917. writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
  3918. spin_unlock_irqrestore(&cp->lock, flags);
  3919. }
  3920. static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3921. {
  3922. struct cas *cp = netdev_priv(dev);
  3923. strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
  3924. strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
  3925. info->fw_version[0] = '\0';
  3926. strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
  3927. info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
  3928. cp->casreg_len : CAS_MAX_REGS;
  3929. info->n_stats = CAS_NUM_STAT_KEYS;
  3930. }
  3931. static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3932. {
  3933. struct cas *cp = netdev_priv(dev);
  3934. u16 bmcr;
  3935. int full_duplex, speed, pause;
  3936. unsigned long flags;
  3937. enum link_state linkstate = link_up;
  3938. cmd->advertising = 0;
  3939. cmd->supported = SUPPORTED_Autoneg;
  3940. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  3941. cmd->supported |= SUPPORTED_1000baseT_Full;
  3942. cmd->advertising |= ADVERTISED_1000baseT_Full;
  3943. }
  3944. /* Record PHY settings if HW is on. */
  3945. spin_lock_irqsave(&cp->lock, flags);
  3946. bmcr = 0;
  3947. linkstate = cp->lstate;
  3948. if (CAS_PHY_MII(cp->phy_type)) {
  3949. cmd->port = PORT_MII;
  3950. cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
  3951. XCVR_INTERNAL : XCVR_EXTERNAL;
  3952. cmd->phy_address = cp->phy_addr;
  3953. cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
  3954. ADVERTISED_10baseT_Half |
  3955. ADVERTISED_10baseT_Full |
  3956. ADVERTISED_100baseT_Half |
  3957. ADVERTISED_100baseT_Full;
  3958. cmd->supported |=
  3959. (SUPPORTED_10baseT_Half |
  3960. SUPPORTED_10baseT_Full |
  3961. SUPPORTED_100baseT_Half |
  3962. SUPPORTED_100baseT_Full |
  3963. SUPPORTED_TP | SUPPORTED_MII);
  3964. if (cp->hw_running) {
  3965. cas_mif_poll(cp, 0);
  3966. bmcr = cas_phy_read(cp, MII_BMCR);
  3967. cas_read_mii_link_mode(cp, &full_duplex,
  3968. &speed, &pause);
  3969. cas_mif_poll(cp, 1);
  3970. }
  3971. } else {
  3972. cmd->port = PORT_FIBRE;
  3973. cmd->transceiver = XCVR_INTERNAL;
  3974. cmd->phy_address = 0;
  3975. cmd->supported |= SUPPORTED_FIBRE;
  3976. cmd->advertising |= ADVERTISED_FIBRE;
  3977. if (cp->hw_running) {
  3978. /* pcs uses the same bits as mii */
  3979. bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
  3980. cas_read_pcs_link_mode(cp, &full_duplex,
  3981. &speed, &pause);
  3982. }
  3983. }
  3984. spin_unlock_irqrestore(&cp->lock, flags);
  3985. if (bmcr & BMCR_ANENABLE) {
  3986. cmd->advertising |= ADVERTISED_Autoneg;
  3987. cmd->autoneg = AUTONEG_ENABLE;
  3988. ethtool_cmd_speed_set(cmd, ((speed == 10) ?
  3989. SPEED_10 :
  3990. ((speed == 1000) ?
  3991. SPEED_1000 : SPEED_100)));
  3992. cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  3993. } else {
  3994. cmd->autoneg = AUTONEG_DISABLE;
  3995. ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
  3996. SPEED_1000 :
  3997. ((bmcr & BMCR_SPEED100) ?
  3998. SPEED_100 : SPEED_10)));
  3999. cmd->duplex =
  4000. (bmcr & BMCR_FULLDPLX) ?
  4001. DUPLEX_FULL : DUPLEX_HALF;
  4002. }
  4003. if (linkstate != link_up) {
  4004. /* Force these to "unknown" if the link is not up and
  4005. * autonogotiation in enabled. We can set the link
  4006. * speed to 0, but not cmd->duplex,
  4007. * because its legal values are 0 and 1. Ethtool will
  4008. * print the value reported in parentheses after the
  4009. * word "Unknown" for unrecognized values.
  4010. *
  4011. * If in forced mode, we report the speed and duplex
  4012. * settings that we configured.
  4013. */
  4014. if (cp->link_cntl & BMCR_ANENABLE) {
  4015. ethtool_cmd_speed_set(cmd, 0);
  4016. cmd->duplex = 0xff;
  4017. } else {
  4018. ethtool_cmd_speed_set(cmd, SPEED_10);
  4019. if (cp->link_cntl & BMCR_SPEED100) {
  4020. ethtool_cmd_speed_set(cmd, SPEED_100);
  4021. } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
  4022. ethtool_cmd_speed_set(cmd, SPEED_1000);
  4023. }
  4024. cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
  4025. DUPLEX_FULL : DUPLEX_HALF;
  4026. }
  4027. }
  4028. return 0;
  4029. }
  4030. static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  4031. {
  4032. struct cas *cp = netdev_priv(dev);
  4033. unsigned long flags;
  4034. u32 speed = ethtool_cmd_speed(cmd);
  4035. /* Verify the settings we care about. */
  4036. if (cmd->autoneg != AUTONEG_ENABLE &&
  4037. cmd->autoneg != AUTONEG_DISABLE)
  4038. return -EINVAL;
  4039. if (cmd->autoneg == AUTONEG_DISABLE &&
  4040. ((speed != SPEED_1000 &&
  4041. speed != SPEED_100 &&
  4042. speed != SPEED_10) ||
  4043. (cmd->duplex != DUPLEX_HALF &&
  4044. cmd->duplex != DUPLEX_FULL)))
  4045. return -EINVAL;
  4046. /* Apply settings and restart link process. */
  4047. spin_lock_irqsave(&cp->lock, flags);
  4048. cas_begin_auto_negotiation(cp, cmd);
  4049. spin_unlock_irqrestore(&cp->lock, flags);
  4050. return 0;
  4051. }
  4052. static int cas_nway_reset(struct net_device *dev)
  4053. {
  4054. struct cas *cp = netdev_priv(dev);
  4055. unsigned long flags;
  4056. if ((cp->link_cntl & BMCR_ANENABLE) == 0)
  4057. return -EINVAL;
  4058. /* Restart link process. */
  4059. spin_lock_irqsave(&cp->lock, flags);
  4060. cas_begin_auto_negotiation(cp, NULL);
  4061. spin_unlock_irqrestore(&cp->lock, flags);
  4062. return 0;
  4063. }
  4064. static u32 cas_get_link(struct net_device *dev)
  4065. {
  4066. struct cas *cp = netdev_priv(dev);
  4067. return cp->lstate == link_up;
  4068. }
  4069. static u32 cas_get_msglevel(struct net_device *dev)
  4070. {
  4071. struct cas *cp = netdev_priv(dev);
  4072. return cp->msg_enable;
  4073. }
  4074. static void cas_set_msglevel(struct net_device *dev, u32 value)
  4075. {
  4076. struct cas *cp = netdev_priv(dev);
  4077. cp->msg_enable = value;
  4078. }
  4079. static int cas_get_regs_len(struct net_device *dev)
  4080. {
  4081. struct cas *cp = netdev_priv(dev);
  4082. return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
  4083. }
  4084. static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  4085. void *p)
  4086. {
  4087. struct cas *cp = netdev_priv(dev);
  4088. regs->version = 0;
  4089. /* cas_read_regs handles locks (cp->lock). */
  4090. cas_read_regs(cp, p, regs->len / sizeof(u32));
  4091. }
  4092. static int cas_get_sset_count(struct net_device *dev, int sset)
  4093. {
  4094. switch (sset) {
  4095. case ETH_SS_STATS:
  4096. return CAS_NUM_STAT_KEYS;
  4097. default:
  4098. return -EOPNOTSUPP;
  4099. }
  4100. }
  4101. static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4102. {
  4103. memcpy(data, &ethtool_cassini_statnames,
  4104. CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
  4105. }
  4106. static void cas_get_ethtool_stats(struct net_device *dev,
  4107. struct ethtool_stats *estats, u64 *data)
  4108. {
  4109. struct cas *cp = netdev_priv(dev);
  4110. struct net_device_stats *stats = cas_get_stats(cp->dev);
  4111. int i = 0;
  4112. data[i++] = stats->collisions;
  4113. data[i++] = stats->rx_bytes;
  4114. data[i++] = stats->rx_crc_errors;
  4115. data[i++] = stats->rx_dropped;
  4116. data[i++] = stats->rx_errors;
  4117. data[i++] = stats->rx_fifo_errors;
  4118. data[i++] = stats->rx_frame_errors;
  4119. data[i++] = stats->rx_length_errors;
  4120. data[i++] = stats->rx_over_errors;
  4121. data[i++] = stats->rx_packets;
  4122. data[i++] = stats->tx_aborted_errors;
  4123. data[i++] = stats->tx_bytes;
  4124. data[i++] = stats->tx_dropped;
  4125. data[i++] = stats->tx_errors;
  4126. data[i++] = stats->tx_fifo_errors;
  4127. data[i++] = stats->tx_packets;
  4128. BUG_ON(i != CAS_NUM_STAT_KEYS);
  4129. }
  4130. static const struct ethtool_ops cas_ethtool_ops = {
  4131. .get_drvinfo = cas_get_drvinfo,
  4132. .get_settings = cas_get_settings,
  4133. .set_settings = cas_set_settings,
  4134. .nway_reset = cas_nway_reset,
  4135. .get_link = cas_get_link,
  4136. .get_msglevel = cas_get_msglevel,
  4137. .set_msglevel = cas_set_msglevel,
  4138. .get_regs_len = cas_get_regs_len,
  4139. .get_regs = cas_get_regs,
  4140. .get_sset_count = cas_get_sset_count,
  4141. .get_strings = cas_get_strings,
  4142. .get_ethtool_stats = cas_get_ethtool_stats,
  4143. };
  4144. static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  4145. {
  4146. struct cas *cp = netdev_priv(dev);
  4147. struct mii_ioctl_data *data = if_mii(ifr);
  4148. unsigned long flags;
  4149. int rc = -EOPNOTSUPP;
  4150. /* Hold the PM mutex while doing ioctl's or we may collide
  4151. * with open/close and power management and oops.
  4152. */
  4153. mutex_lock(&cp->pm_mutex);
  4154. switch (cmd) {
  4155. case SIOCGMIIPHY: /* Get address of MII PHY in use. */
  4156. data->phy_id = cp->phy_addr;
  4157. /* Fallthrough... */
  4158. case SIOCGMIIREG: /* Read MII PHY register. */
  4159. spin_lock_irqsave(&cp->lock, flags);
  4160. cas_mif_poll(cp, 0);
  4161. data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
  4162. cas_mif_poll(cp, 1);
  4163. spin_unlock_irqrestore(&cp->lock, flags);
  4164. rc = 0;
  4165. break;
  4166. case SIOCSMIIREG: /* Write MII PHY register. */
  4167. spin_lock_irqsave(&cp->lock, flags);
  4168. cas_mif_poll(cp, 0);
  4169. rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
  4170. cas_mif_poll(cp, 1);
  4171. spin_unlock_irqrestore(&cp->lock, flags);
  4172. break;
  4173. default:
  4174. break;
  4175. }
  4176. mutex_unlock(&cp->pm_mutex);
  4177. return rc;
  4178. }
  4179. /* When this chip sits underneath an Intel 31154 bridge, it is the
  4180. * only subordinate device and we can tweak the bridge settings to
  4181. * reflect that fact.
  4182. */
  4183. static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
  4184. {
  4185. struct pci_dev *pdev = cas_pdev->bus->self;
  4186. u32 val;
  4187. if (!pdev)
  4188. return;
  4189. if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
  4190. return;
  4191. /* Clear bit 10 (Bus Parking Control) in the Secondary
  4192. * Arbiter Control/Status Register which lives at offset
  4193. * 0x41. Using a 32-bit word read/modify/write at 0x40
  4194. * is much simpler so that's how we do this.
  4195. */
  4196. pci_read_config_dword(pdev, 0x40, &val);
  4197. val &= ~0x00040000;
  4198. pci_write_config_dword(pdev, 0x40, val);
  4199. /* Max out the Multi-Transaction Timer settings since
  4200. * Cassini is the only device present.
  4201. *
  4202. * The register is 16-bit and lives at 0x50. When the
  4203. * settings are enabled, it extends the GRANT# signal
  4204. * for a requestor after a transaction is complete. This
  4205. * allows the next request to run without first needing
  4206. * to negotiate the GRANT# signal back.
  4207. *
  4208. * Bits 12:10 define the grant duration:
  4209. *
  4210. * 1 -- 16 clocks
  4211. * 2 -- 32 clocks
  4212. * 3 -- 64 clocks
  4213. * 4 -- 128 clocks
  4214. * 5 -- 256 clocks
  4215. *
  4216. * All other values are illegal.
  4217. *
  4218. * Bits 09:00 define which REQ/GNT signal pairs get the
  4219. * GRANT# signal treatment. We set them all.
  4220. */
  4221. pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
  4222. /* The Read Prefecth Policy register is 16-bit and sits at
  4223. * offset 0x52. It enables a "smart" pre-fetch policy. We
  4224. * enable it and max out all of the settings since only one
  4225. * device is sitting underneath and thus bandwidth sharing is
  4226. * not an issue.
  4227. *
  4228. * The register has several 3 bit fields, which indicates a
  4229. * multiplier applied to the base amount of prefetching the
  4230. * chip would do. These fields are at:
  4231. *
  4232. * 15:13 --- ReRead Primary Bus
  4233. * 12:10 --- FirstRead Primary Bus
  4234. * 09:07 --- ReRead Secondary Bus
  4235. * 06:04 --- FirstRead Secondary Bus
  4236. *
  4237. * Bits 03:00 control which REQ/GNT pairs the prefetch settings
  4238. * get enabled on. Bit 3 is a grouped enabler which controls
  4239. * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
  4240. * the individual REQ/GNT pairs [2:0].
  4241. */
  4242. pci_write_config_word(pdev, 0x52,
  4243. (0x7 << 13) |
  4244. (0x7 << 10) |
  4245. (0x7 << 7) |
  4246. (0x7 << 4) |
  4247. (0xf << 0));
  4248. /* Force cacheline size to 0x8 */
  4249. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  4250. /* Force latency timer to maximum setting so Cassini can
  4251. * sit on the bus as long as it likes.
  4252. */
  4253. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
  4254. }
  4255. static const struct net_device_ops cas_netdev_ops = {
  4256. .ndo_open = cas_open,
  4257. .ndo_stop = cas_close,
  4258. .ndo_start_xmit = cas_start_xmit,
  4259. .ndo_get_stats = cas_get_stats,
  4260. .ndo_set_multicast_list = cas_set_multicast,
  4261. .ndo_do_ioctl = cas_ioctl,
  4262. .ndo_tx_timeout = cas_tx_timeout,
  4263. .ndo_change_mtu = cas_change_mtu,
  4264. .ndo_set_mac_address = eth_mac_addr,
  4265. .ndo_validate_addr = eth_validate_addr,
  4266. #ifdef CONFIG_NET_POLL_CONTROLLER
  4267. .ndo_poll_controller = cas_netpoll,
  4268. #endif
  4269. };
  4270. static int __devinit cas_init_one(struct pci_dev *pdev,
  4271. const struct pci_device_id *ent)
  4272. {
  4273. static int cas_version_printed = 0;
  4274. unsigned long casreg_len;
  4275. struct net_device *dev;
  4276. struct cas *cp;
  4277. int i, err, pci_using_dac;
  4278. u16 pci_cmd;
  4279. u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
  4280. if (cas_version_printed++ == 0)
  4281. pr_info("%s", version);
  4282. err = pci_enable_device(pdev);
  4283. if (err) {
  4284. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  4285. return err;
  4286. }
  4287. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  4288. dev_err(&pdev->dev, "Cannot find proper PCI device "
  4289. "base address, aborting\n");
  4290. err = -ENODEV;
  4291. goto err_out_disable_pdev;
  4292. }
  4293. dev = alloc_etherdev(sizeof(*cp));
  4294. if (!dev) {
  4295. dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
  4296. err = -ENOMEM;
  4297. goto err_out_disable_pdev;
  4298. }
  4299. SET_NETDEV_DEV(dev, &pdev->dev);
  4300. err = pci_request_regions(pdev, dev->name);
  4301. if (err) {
  4302. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  4303. goto err_out_free_netdev;
  4304. }
  4305. pci_set_master(pdev);
  4306. /* we must always turn on parity response or else parity
  4307. * doesn't get generated properly. disable SERR/PERR as well.
  4308. * in addition, we want to turn MWI on.
  4309. */
  4310. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  4311. pci_cmd &= ~PCI_COMMAND_SERR;
  4312. pci_cmd |= PCI_COMMAND_PARITY;
  4313. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  4314. if (pci_try_set_mwi(pdev))
  4315. pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
  4316. cas_program_bridge(pdev);
  4317. /*
  4318. * On some architectures, the default cache line size set
  4319. * by pci_try_set_mwi reduces perforamnce. We have to increase
  4320. * it for this case. To start, we'll print some configuration
  4321. * data.
  4322. */
  4323. #if 1
  4324. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  4325. &orig_cacheline_size);
  4326. if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
  4327. cas_cacheline_size =
  4328. (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
  4329. CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
  4330. if (pci_write_config_byte(pdev,
  4331. PCI_CACHE_LINE_SIZE,
  4332. cas_cacheline_size)) {
  4333. dev_err(&pdev->dev, "Could not set PCI cache "
  4334. "line size\n");
  4335. goto err_write_cacheline;
  4336. }
  4337. }
  4338. #endif
  4339. /* Configure DMA attributes. */
  4340. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4341. pci_using_dac = 1;
  4342. err = pci_set_consistent_dma_mask(pdev,
  4343. DMA_BIT_MASK(64));
  4344. if (err < 0) {
  4345. dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
  4346. "for consistent allocations\n");
  4347. goto err_out_free_res;
  4348. }
  4349. } else {
  4350. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  4351. if (err) {
  4352. dev_err(&pdev->dev, "No usable DMA configuration, "
  4353. "aborting\n");
  4354. goto err_out_free_res;
  4355. }
  4356. pci_using_dac = 0;
  4357. }
  4358. casreg_len = pci_resource_len(pdev, 0);
  4359. cp = netdev_priv(dev);
  4360. cp->pdev = pdev;
  4361. #if 1
  4362. /* A value of 0 indicates we never explicitly set it */
  4363. cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
  4364. #endif
  4365. cp->dev = dev;
  4366. cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
  4367. cassini_debug;
  4368. #if defined(CONFIG_SPARC)
  4369. cp->of_node = pci_device_to_OF_node(pdev);
  4370. #endif
  4371. cp->link_transition = LINK_TRANSITION_UNKNOWN;
  4372. cp->link_transition_jiffies_valid = 0;
  4373. spin_lock_init(&cp->lock);
  4374. spin_lock_init(&cp->rx_inuse_lock);
  4375. spin_lock_init(&cp->rx_spare_lock);
  4376. for (i = 0; i < N_TX_RINGS; i++) {
  4377. spin_lock_init(&cp->stat_lock[i]);
  4378. spin_lock_init(&cp->tx_lock[i]);
  4379. }
  4380. spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
  4381. mutex_init(&cp->pm_mutex);
  4382. init_timer(&cp->link_timer);
  4383. cp->link_timer.function = cas_link_timer;
  4384. cp->link_timer.data = (unsigned long) cp;
  4385. #if 1
  4386. /* Just in case the implementation of atomic operations
  4387. * change so that an explicit initialization is necessary.
  4388. */
  4389. atomic_set(&cp->reset_task_pending, 0);
  4390. atomic_set(&cp->reset_task_pending_all, 0);
  4391. atomic_set(&cp->reset_task_pending_spare, 0);
  4392. atomic_set(&cp->reset_task_pending_mtu, 0);
  4393. #endif
  4394. INIT_WORK(&cp->reset_task, cas_reset_task);
  4395. /* Default link parameters */
  4396. if (link_mode >= 0 && link_mode < 6)
  4397. cp->link_cntl = link_modes[link_mode];
  4398. else
  4399. cp->link_cntl = BMCR_ANENABLE;
  4400. cp->lstate = link_down;
  4401. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  4402. netif_carrier_off(cp->dev);
  4403. cp->timer_ticks = 0;
  4404. /* give us access to cassini registers */
  4405. cp->regs = pci_iomap(pdev, 0, casreg_len);
  4406. if (!cp->regs) {
  4407. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  4408. goto err_out_free_res;
  4409. }
  4410. cp->casreg_len = casreg_len;
  4411. pci_save_state(pdev);
  4412. cas_check_pci_invariants(cp);
  4413. cas_hard_reset(cp);
  4414. cas_reset(cp, 0);
  4415. if (cas_check_invariants(cp))
  4416. goto err_out_iounmap;
  4417. if (cp->cas_flags & CAS_FLAG_SATURN)
  4418. if (cas_saturn_firmware_init(cp))
  4419. goto err_out_iounmap;
  4420. cp->init_block = (struct cas_init_block *)
  4421. pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
  4422. &cp->block_dvma);
  4423. if (!cp->init_block) {
  4424. dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
  4425. goto err_out_iounmap;
  4426. }
  4427. for (i = 0; i < N_TX_RINGS; i++)
  4428. cp->init_txds[i] = cp->init_block->txds[i];
  4429. for (i = 0; i < N_RX_DESC_RINGS; i++)
  4430. cp->init_rxds[i] = cp->init_block->rxds[i];
  4431. for (i = 0; i < N_RX_COMP_RINGS; i++)
  4432. cp->init_rxcs[i] = cp->init_block->rxcs[i];
  4433. for (i = 0; i < N_RX_FLOWS; i++)
  4434. skb_queue_head_init(&cp->rx_flows[i]);
  4435. dev->netdev_ops = &cas_netdev_ops;
  4436. dev->ethtool_ops = &cas_ethtool_ops;
  4437. dev->watchdog_timeo = CAS_TX_TIMEOUT;
  4438. #ifdef USE_NAPI
  4439. netif_napi_add(dev, &cp->napi, cas_poll, 64);
  4440. #endif
  4441. dev->irq = pdev->irq;
  4442. dev->dma = 0;
  4443. /* Cassini features. */
  4444. if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
  4445. dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
  4446. if (pci_using_dac)
  4447. dev->features |= NETIF_F_HIGHDMA;
  4448. if (register_netdev(dev)) {
  4449. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  4450. goto err_out_free_consistent;
  4451. }
  4452. i = readl(cp->regs + REG_BIM_CFG);
  4453. netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
  4454. (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
  4455. (i & BIM_CFG_32BIT) ? "32" : "64",
  4456. (i & BIM_CFG_66MHZ) ? "66" : "33",
  4457. (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
  4458. dev->dev_addr);
  4459. pci_set_drvdata(pdev, dev);
  4460. cp->hw_running = 1;
  4461. cas_entropy_reset(cp);
  4462. cas_phy_init(cp);
  4463. cas_begin_auto_negotiation(cp, NULL);
  4464. return 0;
  4465. err_out_free_consistent:
  4466. pci_free_consistent(pdev, sizeof(struct cas_init_block),
  4467. cp->init_block, cp->block_dvma);
  4468. err_out_iounmap:
  4469. mutex_lock(&cp->pm_mutex);
  4470. if (cp->hw_running)
  4471. cas_shutdown(cp);
  4472. mutex_unlock(&cp->pm_mutex);
  4473. pci_iounmap(pdev, cp->regs);
  4474. err_out_free_res:
  4475. pci_release_regions(pdev);
  4476. err_write_cacheline:
  4477. /* Try to restore it in case the error occurred after we
  4478. * set it.
  4479. */
  4480. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
  4481. err_out_free_netdev:
  4482. free_netdev(dev);
  4483. err_out_disable_pdev:
  4484. pci_disable_device(pdev);
  4485. pci_set_drvdata(pdev, NULL);
  4486. return -ENODEV;
  4487. }
  4488. static void __devexit cas_remove_one(struct pci_dev *pdev)
  4489. {
  4490. struct net_device *dev = pci_get_drvdata(pdev);
  4491. struct cas *cp;
  4492. if (!dev)
  4493. return;
  4494. cp = netdev_priv(dev);
  4495. unregister_netdev(dev);
  4496. if (cp->fw_data)
  4497. vfree(cp->fw_data);
  4498. mutex_lock(&cp->pm_mutex);
  4499. cancel_work_sync(&cp->reset_task);
  4500. if (cp->hw_running)
  4501. cas_shutdown(cp);
  4502. mutex_unlock(&cp->pm_mutex);
  4503. #if 1
  4504. if (cp->orig_cacheline_size) {
  4505. /* Restore the cache line size if we had modified
  4506. * it.
  4507. */
  4508. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  4509. cp->orig_cacheline_size);
  4510. }
  4511. #endif
  4512. pci_free_consistent(pdev, sizeof(struct cas_init_block),
  4513. cp->init_block, cp->block_dvma);
  4514. pci_iounmap(pdev, cp->regs);
  4515. free_netdev(dev);
  4516. pci_release_regions(pdev);
  4517. pci_disable_device(pdev);
  4518. pci_set_drvdata(pdev, NULL);
  4519. }
  4520. #ifdef CONFIG_PM
  4521. static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
  4522. {
  4523. struct net_device *dev = pci_get_drvdata(pdev);
  4524. struct cas *cp = netdev_priv(dev);
  4525. unsigned long flags;
  4526. mutex_lock(&cp->pm_mutex);
  4527. /* If the driver is opened, we stop the DMA */
  4528. if (cp->opened) {
  4529. netif_device_detach(dev);
  4530. cas_lock_all_save(cp, flags);
  4531. /* We can set the second arg of cas_reset to 0
  4532. * because on resume, we'll call cas_init_hw with
  4533. * its second arg set so that autonegotiation is
  4534. * restarted.
  4535. */
  4536. cas_reset(cp, 0);
  4537. cas_clean_rings(cp);
  4538. cas_unlock_all_restore(cp, flags);
  4539. }
  4540. if (cp->hw_running)
  4541. cas_shutdown(cp);
  4542. mutex_unlock(&cp->pm_mutex);
  4543. return 0;
  4544. }
  4545. static int cas_resume(struct pci_dev *pdev)
  4546. {
  4547. struct net_device *dev = pci_get_drvdata(pdev);
  4548. struct cas *cp = netdev_priv(dev);
  4549. netdev_info(dev, "resuming\n");
  4550. mutex_lock(&cp->pm_mutex);
  4551. cas_hard_reset(cp);
  4552. if (cp->opened) {
  4553. unsigned long flags;
  4554. cas_lock_all_save(cp, flags);
  4555. cas_reset(cp, 0);
  4556. cp->hw_running = 1;
  4557. cas_clean_rings(cp);
  4558. cas_init_hw(cp, 1);
  4559. cas_unlock_all_restore(cp, flags);
  4560. netif_device_attach(dev);
  4561. }
  4562. mutex_unlock(&cp->pm_mutex);
  4563. return 0;
  4564. }
  4565. #endif /* CONFIG_PM */
  4566. static struct pci_driver cas_driver = {
  4567. .name = DRV_MODULE_NAME,
  4568. .id_table = cas_pci_tbl,
  4569. .probe = cas_init_one,
  4570. .remove = __devexit_p(cas_remove_one),
  4571. #ifdef CONFIG_PM
  4572. .suspend = cas_suspend,
  4573. .resume = cas_resume
  4574. #endif
  4575. };
  4576. static int __init cas_init(void)
  4577. {
  4578. if (linkdown_timeout > 0)
  4579. link_transition_timeout = linkdown_timeout * HZ;
  4580. else
  4581. link_transition_timeout = 0;
  4582. return pci_register_driver(&cas_driver);
  4583. }
  4584. static void __exit cas_cleanup(void)
  4585. {
  4586. pci_unregister_driver(&cas_driver);
  4587. }
  4588. module_init(cas_init);
  4589. module_exit(cas_cleanup);