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/drivers/net/benet/be_cmds.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 2325 lines | 1790 code | 442 blank | 93 comment | 189 complexity | c69d3aab32ca8b03cf36f5a9b01cd6b7 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@emulex.com
  12. *
  13. * Emulex
  14. * 3333 Susan Street
  15. * Costa Mesa, CA 92626
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. /* Must be a power of 2 or else MODULO will BUG_ON */
  20. static int be_get_temp_freq = 32;
  21. static void be_mcc_notify(struct be_adapter *adapter)
  22. {
  23. struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24. u32 val = 0;
  25. if (adapter->eeh_err) {
  26. dev_info(&adapter->pdev->dev,
  27. "Error in Card Detected! Cannot issue commands\n");
  28. return;
  29. }
  30. val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  31. val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  32. wmb();
  33. iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  34. }
  35. /* To check if valid bit is set, check the entire word as we don't know
  36. * the endianness of the data (old entry is host endian while a new entry is
  37. * little endian) */
  38. static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  39. {
  40. if (compl->flags != 0) {
  41. compl->flags = le32_to_cpu(compl->flags);
  42. BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  43. return true;
  44. } else {
  45. return false;
  46. }
  47. }
  48. /* Need to reset the entire word that houses the valid bit */
  49. static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  50. {
  51. compl->flags = 0;
  52. }
  53. static int be_mcc_compl_process(struct be_adapter *adapter,
  54. struct be_mcc_compl *compl)
  55. {
  56. u16 compl_status, extd_status;
  57. /* Just swap the status to host endian; mcc tag is opaquely copied
  58. * from mcc_wrb */
  59. be_dws_le_to_cpu(compl, 4);
  60. compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  61. CQE_STATUS_COMPL_MASK;
  62. if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  63. (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  64. (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  65. adapter->flash_status = compl_status;
  66. complete(&adapter->flash_compl);
  67. }
  68. if (compl_status == MCC_STATUS_SUCCESS) {
  69. if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  70. (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  71. (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  72. if (adapter->generation == BE_GEN3) {
  73. if (lancer_chip(adapter)) {
  74. struct lancer_cmd_resp_pport_stats
  75. *resp = adapter->stats_cmd.va;
  76. be_dws_le_to_cpu(&resp->pport_stats,
  77. sizeof(resp->pport_stats));
  78. } else {
  79. struct be_cmd_resp_get_stats_v1 *resp =
  80. adapter->stats_cmd.va;
  81. be_dws_le_to_cpu(&resp->hw_stats,
  82. sizeof(resp->hw_stats));
  83. }
  84. } else {
  85. struct be_cmd_resp_get_stats_v0 *resp =
  86. adapter->stats_cmd.va;
  87. be_dws_le_to_cpu(&resp->hw_stats,
  88. sizeof(resp->hw_stats));
  89. }
  90. be_parse_stats(adapter);
  91. netdev_stats_update(adapter);
  92. adapter->stats_cmd_sent = false;
  93. }
  94. } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
  95. (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
  96. extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  97. CQE_STATUS_EXTD_MASK;
  98. dev_warn(&adapter->pdev->dev,
  99. "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  100. compl->tag0, compl_status, extd_status);
  101. }
  102. return compl_status;
  103. }
  104. /* Link state evt is a string of bytes; no need for endian swapping */
  105. static void be_async_link_state_process(struct be_adapter *adapter,
  106. struct be_async_event_link_state *evt)
  107. {
  108. be_link_status_update(adapter,
  109. evt->port_link_status == ASYNC_EVENT_LINK_UP);
  110. }
  111. /* Grp5 CoS Priority evt */
  112. static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
  113. struct be_async_event_grp5_cos_priority *evt)
  114. {
  115. if (evt->valid) {
  116. adapter->vlan_prio_bmap = evt->available_priority_bmap;
  117. adapter->recommended_prio &= ~VLAN_PRIO_MASK;
  118. adapter->recommended_prio =
  119. evt->reco_default_priority << VLAN_PRIO_SHIFT;
  120. }
  121. }
  122. /* Grp5 QOS Speed evt */
  123. static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
  124. struct be_async_event_grp5_qos_link_speed *evt)
  125. {
  126. if (evt->physical_port == adapter->port_num) {
  127. /* qos_link_speed is in units of 10 Mbps */
  128. adapter->link_speed = evt->qos_link_speed * 10;
  129. }
  130. }
  131. /*Grp5 PVID evt*/
  132. static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
  133. struct be_async_event_grp5_pvid_state *evt)
  134. {
  135. if (evt->enabled)
  136. adapter->pvid = le16_to_cpu(evt->tag);
  137. else
  138. adapter->pvid = 0;
  139. }
  140. static void be_async_grp5_evt_process(struct be_adapter *adapter,
  141. u32 trailer, struct be_mcc_compl *evt)
  142. {
  143. u8 event_type = 0;
  144. event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
  145. ASYNC_TRAILER_EVENT_TYPE_MASK;
  146. switch (event_type) {
  147. case ASYNC_EVENT_COS_PRIORITY:
  148. be_async_grp5_cos_priority_process(adapter,
  149. (struct be_async_event_grp5_cos_priority *)evt);
  150. break;
  151. case ASYNC_EVENT_QOS_SPEED:
  152. be_async_grp5_qos_speed_process(adapter,
  153. (struct be_async_event_grp5_qos_link_speed *)evt);
  154. break;
  155. case ASYNC_EVENT_PVID_STATE:
  156. be_async_grp5_pvid_state_process(adapter,
  157. (struct be_async_event_grp5_pvid_state *)evt);
  158. break;
  159. default:
  160. dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
  161. break;
  162. }
  163. }
  164. static inline bool is_link_state_evt(u32 trailer)
  165. {
  166. return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
  167. ASYNC_TRAILER_EVENT_CODE_MASK) ==
  168. ASYNC_EVENT_CODE_LINK_STATE;
  169. }
  170. static inline bool is_grp5_evt(u32 trailer)
  171. {
  172. return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
  173. ASYNC_TRAILER_EVENT_CODE_MASK) ==
  174. ASYNC_EVENT_CODE_GRP_5);
  175. }
  176. static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
  177. {
  178. struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
  179. struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
  180. if (be_mcc_compl_is_new(compl)) {
  181. queue_tail_inc(mcc_cq);
  182. return compl;
  183. }
  184. return NULL;
  185. }
  186. void be_async_mcc_enable(struct be_adapter *adapter)
  187. {
  188. spin_lock_bh(&adapter->mcc_cq_lock);
  189. be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
  190. adapter->mcc_obj.rearm_cq = true;
  191. spin_unlock_bh(&adapter->mcc_cq_lock);
  192. }
  193. void be_async_mcc_disable(struct be_adapter *adapter)
  194. {
  195. adapter->mcc_obj.rearm_cq = false;
  196. }
  197. int be_process_mcc(struct be_adapter *adapter, int *status)
  198. {
  199. struct be_mcc_compl *compl;
  200. int num = 0;
  201. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  202. spin_lock_bh(&adapter->mcc_cq_lock);
  203. while ((compl = be_mcc_compl_get(adapter))) {
  204. if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
  205. /* Interpret flags as an async trailer */
  206. if (is_link_state_evt(compl->flags))
  207. be_async_link_state_process(adapter,
  208. (struct be_async_event_link_state *) compl);
  209. else if (is_grp5_evt(compl->flags))
  210. be_async_grp5_evt_process(adapter,
  211. compl->flags, compl);
  212. } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  213. *status = be_mcc_compl_process(adapter, compl);
  214. atomic_dec(&mcc_obj->q.used);
  215. }
  216. be_mcc_compl_use(compl);
  217. num++;
  218. }
  219. spin_unlock_bh(&adapter->mcc_cq_lock);
  220. return num;
  221. }
  222. /* Wait till no more pending mcc requests are present */
  223. static int be_mcc_wait_compl(struct be_adapter *adapter)
  224. {
  225. #define mcc_timeout 120000 /* 12s timeout */
  226. int i, num, status = 0;
  227. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  228. if (adapter->eeh_err)
  229. return -EIO;
  230. for (i = 0; i < mcc_timeout; i++) {
  231. num = be_process_mcc(adapter, &status);
  232. if (num)
  233. be_cq_notify(adapter, mcc_obj->cq.id,
  234. mcc_obj->rearm_cq, num);
  235. if (atomic_read(&mcc_obj->q.used) == 0)
  236. break;
  237. udelay(100);
  238. }
  239. if (i == mcc_timeout) {
  240. dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
  241. return -1;
  242. }
  243. return status;
  244. }
  245. /* Notify MCC requests and wait for completion */
  246. static int be_mcc_notify_wait(struct be_adapter *adapter)
  247. {
  248. be_mcc_notify(adapter);
  249. return be_mcc_wait_compl(adapter);
  250. }
  251. static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
  252. {
  253. int msecs = 0;
  254. u32 ready;
  255. if (adapter->eeh_err) {
  256. dev_err(&adapter->pdev->dev,
  257. "Error detected in card.Cannot issue commands\n");
  258. return -EIO;
  259. }
  260. do {
  261. ready = ioread32(db);
  262. if (ready == 0xffffffff) {
  263. dev_err(&adapter->pdev->dev,
  264. "pci slot disconnected\n");
  265. return -1;
  266. }
  267. ready &= MPU_MAILBOX_DB_RDY_MASK;
  268. if (ready)
  269. break;
  270. if (msecs > 4000) {
  271. dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
  272. if (!lancer_chip(adapter))
  273. be_detect_dump_ue(adapter);
  274. return -1;
  275. }
  276. msleep(1);
  277. msecs++;
  278. } while (true);
  279. return 0;
  280. }
  281. /*
  282. * Insert the mailbox address into the doorbell in two steps
  283. * Polls on the mbox doorbell till a command completion (or a timeout) occurs
  284. */
  285. static int be_mbox_notify_wait(struct be_adapter *adapter)
  286. {
  287. int status;
  288. u32 val = 0;
  289. void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
  290. struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
  291. struct be_mcc_mailbox *mbox = mbox_mem->va;
  292. struct be_mcc_compl *compl = &mbox->compl;
  293. /* wait for ready to be set */
  294. status = be_mbox_db_ready_wait(adapter, db);
  295. if (status != 0)
  296. return status;
  297. val |= MPU_MAILBOX_DB_HI_MASK;
  298. /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
  299. val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
  300. iowrite32(val, db);
  301. /* wait for ready to be set */
  302. status = be_mbox_db_ready_wait(adapter, db);
  303. if (status != 0)
  304. return status;
  305. val = 0;
  306. /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
  307. val |= (u32)(mbox_mem->dma >> 4) << 2;
  308. iowrite32(val, db);
  309. status = be_mbox_db_ready_wait(adapter, db);
  310. if (status != 0)
  311. return status;
  312. /* A cq entry has been made now */
  313. if (be_mcc_compl_is_new(compl)) {
  314. status = be_mcc_compl_process(adapter, &mbox->compl);
  315. be_mcc_compl_use(compl);
  316. if (status)
  317. return status;
  318. } else {
  319. dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
  320. return -1;
  321. }
  322. return 0;
  323. }
  324. static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
  325. {
  326. u32 sem;
  327. if (lancer_chip(adapter))
  328. sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
  329. else
  330. sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
  331. *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
  332. if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
  333. return -1;
  334. else
  335. return 0;
  336. }
  337. int be_cmd_POST(struct be_adapter *adapter)
  338. {
  339. u16 stage;
  340. int status, timeout = 0;
  341. struct device *dev = &adapter->pdev->dev;
  342. do {
  343. status = be_POST_stage_get(adapter, &stage);
  344. if (status) {
  345. dev_err(dev, "POST error; stage=0x%x\n", stage);
  346. return -1;
  347. } else if (stage != POST_STAGE_ARMFW_RDY) {
  348. if (msleep_interruptible(2000)) {
  349. dev_err(dev, "Waiting for POST aborted\n");
  350. return -EINTR;
  351. }
  352. timeout += 2;
  353. } else {
  354. return 0;
  355. }
  356. } while (timeout < 40);
  357. dev_err(dev, "POST timeout; stage=0x%x\n", stage);
  358. return -1;
  359. }
  360. static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  361. {
  362. return wrb->payload.embedded_payload;
  363. }
  364. static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
  365. {
  366. return &wrb->payload.sgl[0];
  367. }
  368. /* Don't touch the hdr after it's prepared */
  369. static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
  370. bool embedded, u8 sge_cnt, u32 opcode)
  371. {
  372. if (embedded)
  373. wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
  374. else
  375. wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
  376. MCC_WRB_SGE_CNT_SHIFT;
  377. wrb->payload_length = payload_len;
  378. wrb->tag0 = opcode;
  379. be_dws_cpu_to_le(wrb, 8);
  380. }
  381. /* Don't touch the hdr after it's prepared */
  382. static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
  383. u8 subsystem, u8 opcode, int cmd_len)
  384. {
  385. req_hdr->opcode = opcode;
  386. req_hdr->subsystem = subsystem;
  387. req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
  388. req_hdr->version = 0;
  389. }
  390. static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
  391. struct be_dma_mem *mem)
  392. {
  393. int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
  394. u64 dma = (u64)mem->dma;
  395. for (i = 0; i < buf_pages; i++) {
  396. pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
  397. pages[i].hi = cpu_to_le32(upper_32_bits(dma));
  398. dma += PAGE_SIZE_4K;
  399. }
  400. }
  401. /* Converts interrupt delay in microseconds to multiplier value */
  402. static u32 eq_delay_to_mult(u32 usec_delay)
  403. {
  404. #define MAX_INTR_RATE 651042
  405. const u32 round = 10;
  406. u32 multiplier;
  407. if (usec_delay == 0)
  408. multiplier = 0;
  409. else {
  410. u32 interrupt_rate = 1000000 / usec_delay;
  411. /* Max delay, corresponding to the lowest interrupt rate */
  412. if (interrupt_rate == 0)
  413. multiplier = 1023;
  414. else {
  415. multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
  416. multiplier /= interrupt_rate;
  417. /* Round the multiplier to the closest value.*/
  418. multiplier = (multiplier + round/2) / round;
  419. multiplier = min(multiplier, (u32)1023);
  420. }
  421. }
  422. return multiplier;
  423. }
  424. static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
  425. {
  426. struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
  427. struct be_mcc_wrb *wrb
  428. = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
  429. memset(wrb, 0, sizeof(*wrb));
  430. return wrb;
  431. }
  432. static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
  433. {
  434. struct be_queue_info *mccq = &adapter->mcc_obj.q;
  435. struct be_mcc_wrb *wrb;
  436. if (atomic_read(&mccq->used) >= mccq->len) {
  437. dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
  438. return NULL;
  439. }
  440. wrb = queue_head_node(mccq);
  441. queue_head_inc(mccq);
  442. atomic_inc(&mccq->used);
  443. memset(wrb, 0, sizeof(*wrb));
  444. return wrb;
  445. }
  446. /* Tell fw we're about to start firing cmds by writing a
  447. * special pattern across the wrb hdr; uses mbox
  448. */
  449. int be_cmd_fw_init(struct be_adapter *adapter)
  450. {
  451. u8 *wrb;
  452. int status;
  453. if (mutex_lock_interruptible(&adapter->mbox_lock))
  454. return -1;
  455. wrb = (u8 *)wrb_from_mbox(adapter);
  456. *wrb++ = 0xFF;
  457. *wrb++ = 0x12;
  458. *wrb++ = 0x34;
  459. *wrb++ = 0xFF;
  460. *wrb++ = 0xFF;
  461. *wrb++ = 0x56;
  462. *wrb++ = 0x78;
  463. *wrb = 0xFF;
  464. status = be_mbox_notify_wait(adapter);
  465. mutex_unlock(&adapter->mbox_lock);
  466. return status;
  467. }
  468. /* Tell fw we're done with firing cmds by writing a
  469. * special pattern across the wrb hdr; uses mbox
  470. */
  471. int be_cmd_fw_clean(struct be_adapter *adapter)
  472. {
  473. u8 *wrb;
  474. int status;
  475. if (adapter->eeh_err)
  476. return -EIO;
  477. if (mutex_lock_interruptible(&adapter->mbox_lock))
  478. return -1;
  479. wrb = (u8 *)wrb_from_mbox(adapter);
  480. *wrb++ = 0xFF;
  481. *wrb++ = 0xAA;
  482. *wrb++ = 0xBB;
  483. *wrb++ = 0xFF;
  484. *wrb++ = 0xFF;
  485. *wrb++ = 0xCC;
  486. *wrb++ = 0xDD;
  487. *wrb = 0xFF;
  488. status = be_mbox_notify_wait(adapter);
  489. mutex_unlock(&adapter->mbox_lock);
  490. return status;
  491. }
  492. int be_cmd_eq_create(struct be_adapter *adapter,
  493. struct be_queue_info *eq, int eq_delay)
  494. {
  495. struct be_mcc_wrb *wrb;
  496. struct be_cmd_req_eq_create *req;
  497. struct be_dma_mem *q_mem = &eq->dma_mem;
  498. int status;
  499. if (mutex_lock_interruptible(&adapter->mbox_lock))
  500. return -1;
  501. wrb = wrb_from_mbox(adapter);
  502. req = embedded_payload(wrb);
  503. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
  504. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  505. OPCODE_COMMON_EQ_CREATE, sizeof(*req));
  506. req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
  507. AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
  508. /* 4byte eqe*/
  509. AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
  510. AMAP_SET_BITS(struct amap_eq_context, count, req->context,
  511. __ilog2_u32(eq->len/256));
  512. AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
  513. eq_delay_to_mult(eq_delay));
  514. be_dws_cpu_to_le(req->context, sizeof(req->context));
  515. be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
  516. status = be_mbox_notify_wait(adapter);
  517. if (!status) {
  518. struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
  519. eq->id = le16_to_cpu(resp->eq_id);
  520. eq->created = true;
  521. }
  522. mutex_unlock(&adapter->mbox_lock);
  523. return status;
  524. }
  525. /* Uses mbox */
  526. int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
  527. u8 type, bool permanent, u32 if_handle)
  528. {
  529. struct be_mcc_wrb *wrb;
  530. struct be_cmd_req_mac_query *req;
  531. int status;
  532. if (mutex_lock_interruptible(&adapter->mbox_lock))
  533. return -1;
  534. wrb = wrb_from_mbox(adapter);
  535. req = embedded_payload(wrb);
  536. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  537. OPCODE_COMMON_NTWK_MAC_QUERY);
  538. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  539. OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
  540. req->type = type;
  541. if (permanent) {
  542. req->permanent = 1;
  543. } else {
  544. req->if_id = cpu_to_le16((u16) if_handle);
  545. req->permanent = 0;
  546. }
  547. status = be_mbox_notify_wait(adapter);
  548. if (!status) {
  549. struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
  550. memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
  551. }
  552. mutex_unlock(&adapter->mbox_lock);
  553. return status;
  554. }
  555. /* Uses synchronous MCCQ */
  556. int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
  557. u32 if_id, u32 *pmac_id, u32 domain)
  558. {
  559. struct be_mcc_wrb *wrb;
  560. struct be_cmd_req_pmac_add *req;
  561. int status;
  562. spin_lock_bh(&adapter->mcc_lock);
  563. wrb = wrb_from_mccq(adapter);
  564. if (!wrb) {
  565. status = -EBUSY;
  566. goto err;
  567. }
  568. req = embedded_payload(wrb);
  569. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  570. OPCODE_COMMON_NTWK_PMAC_ADD);
  571. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  572. OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
  573. req->hdr.domain = domain;
  574. req->if_id = cpu_to_le32(if_id);
  575. memcpy(req->mac_address, mac_addr, ETH_ALEN);
  576. status = be_mcc_notify_wait(adapter);
  577. if (!status) {
  578. struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
  579. *pmac_id = le32_to_cpu(resp->pmac_id);
  580. }
  581. err:
  582. spin_unlock_bh(&adapter->mcc_lock);
  583. return status;
  584. }
  585. /* Uses synchronous MCCQ */
  586. int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
  587. {
  588. struct be_mcc_wrb *wrb;
  589. struct be_cmd_req_pmac_del *req;
  590. int status;
  591. spin_lock_bh(&adapter->mcc_lock);
  592. wrb = wrb_from_mccq(adapter);
  593. if (!wrb) {
  594. status = -EBUSY;
  595. goto err;
  596. }
  597. req = embedded_payload(wrb);
  598. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  599. OPCODE_COMMON_NTWK_PMAC_DEL);
  600. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  601. OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
  602. req->hdr.domain = dom;
  603. req->if_id = cpu_to_le32(if_id);
  604. req->pmac_id = cpu_to_le32(pmac_id);
  605. status = be_mcc_notify_wait(adapter);
  606. err:
  607. spin_unlock_bh(&adapter->mcc_lock);
  608. return status;
  609. }
  610. /* Uses Mbox */
  611. int be_cmd_cq_create(struct be_adapter *adapter,
  612. struct be_queue_info *cq, struct be_queue_info *eq,
  613. bool sol_evts, bool no_delay, int coalesce_wm)
  614. {
  615. struct be_mcc_wrb *wrb;
  616. struct be_cmd_req_cq_create *req;
  617. struct be_dma_mem *q_mem = &cq->dma_mem;
  618. void *ctxt;
  619. int status;
  620. if (mutex_lock_interruptible(&adapter->mbox_lock))
  621. return -1;
  622. wrb = wrb_from_mbox(adapter);
  623. req = embedded_payload(wrb);
  624. ctxt = &req->context;
  625. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  626. OPCODE_COMMON_CQ_CREATE);
  627. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  628. OPCODE_COMMON_CQ_CREATE, sizeof(*req));
  629. req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
  630. if (lancer_chip(adapter)) {
  631. req->hdr.version = 2;
  632. req->page_size = 1; /* 1 for 4K */
  633. AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
  634. no_delay);
  635. AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
  636. __ilog2_u32(cq->len/256));
  637. AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
  638. AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
  639. ctxt, 1);
  640. AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
  641. ctxt, eq->id);
  642. AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
  643. } else {
  644. AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
  645. coalesce_wm);
  646. AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
  647. ctxt, no_delay);
  648. AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
  649. __ilog2_u32(cq->len/256));
  650. AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
  651. AMAP_SET_BITS(struct amap_cq_context_be, solevent,
  652. ctxt, sol_evts);
  653. AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
  654. AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
  655. AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
  656. }
  657. be_dws_cpu_to_le(ctxt, sizeof(req->context));
  658. be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
  659. status = be_mbox_notify_wait(adapter);
  660. if (!status) {
  661. struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
  662. cq->id = le16_to_cpu(resp->cq_id);
  663. cq->created = true;
  664. }
  665. mutex_unlock(&adapter->mbox_lock);
  666. return status;
  667. }
  668. static u32 be_encoded_q_len(int q_len)
  669. {
  670. u32 len_encoded = fls(q_len); /* log2(len) + 1 */
  671. if (len_encoded == 16)
  672. len_encoded = 0;
  673. return len_encoded;
  674. }
  675. int be_cmd_mccq_create(struct be_adapter *adapter,
  676. struct be_queue_info *mccq,
  677. struct be_queue_info *cq)
  678. {
  679. struct be_mcc_wrb *wrb;
  680. struct be_cmd_req_mcc_create *req;
  681. struct be_dma_mem *q_mem = &mccq->dma_mem;
  682. void *ctxt;
  683. int status;
  684. if (mutex_lock_interruptible(&adapter->mbox_lock))
  685. return -1;
  686. wrb = wrb_from_mbox(adapter);
  687. req = embedded_payload(wrb);
  688. ctxt = &req->context;
  689. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  690. OPCODE_COMMON_MCC_CREATE_EXT);
  691. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  692. OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
  693. req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
  694. if (lancer_chip(adapter)) {
  695. req->hdr.version = 1;
  696. req->cq_id = cpu_to_le16(cq->id);
  697. AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
  698. be_encoded_q_len(mccq->len));
  699. AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
  700. AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
  701. ctxt, cq->id);
  702. AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
  703. ctxt, 1);
  704. } else {
  705. AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
  706. AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
  707. be_encoded_q_len(mccq->len));
  708. AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
  709. }
  710. /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
  711. req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
  712. be_dws_cpu_to_le(ctxt, sizeof(req->context));
  713. be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
  714. status = be_mbox_notify_wait(adapter);
  715. if (!status) {
  716. struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
  717. mccq->id = le16_to_cpu(resp->id);
  718. mccq->created = true;
  719. }
  720. mutex_unlock(&adapter->mbox_lock);
  721. return status;
  722. }
  723. int be_cmd_txq_create(struct be_adapter *adapter,
  724. struct be_queue_info *txq,
  725. struct be_queue_info *cq)
  726. {
  727. struct be_mcc_wrb *wrb;
  728. struct be_cmd_req_eth_tx_create *req;
  729. struct be_dma_mem *q_mem = &txq->dma_mem;
  730. void *ctxt;
  731. int status;
  732. if (mutex_lock_interruptible(&adapter->mbox_lock))
  733. return -1;
  734. wrb = wrb_from_mbox(adapter);
  735. req = embedded_payload(wrb);
  736. ctxt = &req->context;
  737. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  738. OPCODE_ETH_TX_CREATE);
  739. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
  740. sizeof(*req));
  741. if (lancer_chip(adapter)) {
  742. req->hdr.version = 1;
  743. AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
  744. adapter->if_handle);
  745. }
  746. req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
  747. req->ulp_num = BE_ULP1_NUM;
  748. req->type = BE_ETH_TX_RING_TYPE_STANDARD;
  749. AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
  750. be_encoded_q_len(txq->len));
  751. AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
  752. AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
  753. be_dws_cpu_to_le(ctxt, sizeof(req->context));
  754. be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
  755. status = be_mbox_notify_wait(adapter);
  756. if (!status) {
  757. struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
  758. txq->id = le16_to_cpu(resp->cid);
  759. txq->created = true;
  760. }
  761. mutex_unlock(&adapter->mbox_lock);
  762. return status;
  763. }
  764. /* Uses mbox */
  765. int be_cmd_rxq_create(struct be_adapter *adapter,
  766. struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
  767. u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
  768. {
  769. struct be_mcc_wrb *wrb;
  770. struct be_cmd_req_eth_rx_create *req;
  771. struct be_dma_mem *q_mem = &rxq->dma_mem;
  772. int status;
  773. if (mutex_lock_interruptible(&adapter->mbox_lock))
  774. return -1;
  775. wrb = wrb_from_mbox(adapter);
  776. req = embedded_payload(wrb);
  777. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  778. OPCODE_ETH_RX_CREATE);
  779. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
  780. sizeof(*req));
  781. req->cq_id = cpu_to_le16(cq_id);
  782. req->frag_size = fls(frag_size) - 1;
  783. req->num_pages = 2;
  784. be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
  785. req->interface_id = cpu_to_le32(if_id);
  786. req->max_frame_size = cpu_to_le16(max_frame_size);
  787. req->rss_queue = cpu_to_le32(rss);
  788. status = be_mbox_notify_wait(adapter);
  789. if (!status) {
  790. struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
  791. rxq->id = le16_to_cpu(resp->id);
  792. rxq->created = true;
  793. *rss_id = resp->rss_id;
  794. }
  795. mutex_unlock(&adapter->mbox_lock);
  796. return status;
  797. }
  798. /* Generic destroyer function for all types of queues
  799. * Uses Mbox
  800. */
  801. int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
  802. int queue_type)
  803. {
  804. struct be_mcc_wrb *wrb;
  805. struct be_cmd_req_q_destroy *req;
  806. u8 subsys = 0, opcode = 0;
  807. int status;
  808. if (adapter->eeh_err)
  809. return -EIO;
  810. if (mutex_lock_interruptible(&adapter->mbox_lock))
  811. return -1;
  812. wrb = wrb_from_mbox(adapter);
  813. req = embedded_payload(wrb);
  814. switch (queue_type) {
  815. case QTYPE_EQ:
  816. subsys = CMD_SUBSYSTEM_COMMON;
  817. opcode = OPCODE_COMMON_EQ_DESTROY;
  818. break;
  819. case QTYPE_CQ:
  820. subsys = CMD_SUBSYSTEM_COMMON;
  821. opcode = OPCODE_COMMON_CQ_DESTROY;
  822. break;
  823. case QTYPE_TXQ:
  824. subsys = CMD_SUBSYSTEM_ETH;
  825. opcode = OPCODE_ETH_TX_DESTROY;
  826. break;
  827. case QTYPE_RXQ:
  828. subsys = CMD_SUBSYSTEM_ETH;
  829. opcode = OPCODE_ETH_RX_DESTROY;
  830. break;
  831. case QTYPE_MCCQ:
  832. subsys = CMD_SUBSYSTEM_COMMON;
  833. opcode = OPCODE_COMMON_MCC_DESTROY;
  834. break;
  835. default:
  836. BUG();
  837. }
  838. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
  839. be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
  840. req->id = cpu_to_le16(q->id);
  841. status = be_mbox_notify_wait(adapter);
  842. mutex_unlock(&adapter->mbox_lock);
  843. return status;
  844. }
  845. /* Create an rx filtering policy configuration on an i/f
  846. * Uses mbox
  847. */
  848. int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
  849. u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
  850. u32 domain)
  851. {
  852. struct be_mcc_wrb *wrb;
  853. struct be_cmd_req_if_create *req;
  854. int status;
  855. if (mutex_lock_interruptible(&adapter->mbox_lock))
  856. return -1;
  857. wrb = wrb_from_mbox(adapter);
  858. req = embedded_payload(wrb);
  859. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  860. OPCODE_COMMON_NTWK_INTERFACE_CREATE);
  861. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  862. OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
  863. req->hdr.domain = domain;
  864. req->capability_flags = cpu_to_le32(cap_flags);
  865. req->enable_flags = cpu_to_le32(en_flags);
  866. req->pmac_invalid = pmac_invalid;
  867. if (!pmac_invalid)
  868. memcpy(req->mac_addr, mac, ETH_ALEN);
  869. status = be_mbox_notify_wait(adapter);
  870. if (!status) {
  871. struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
  872. *if_handle = le32_to_cpu(resp->interface_id);
  873. if (!pmac_invalid)
  874. *pmac_id = le32_to_cpu(resp->pmac_id);
  875. }
  876. mutex_unlock(&adapter->mbox_lock);
  877. return status;
  878. }
  879. /* Uses mbox */
  880. int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
  881. {
  882. struct be_mcc_wrb *wrb;
  883. struct be_cmd_req_if_destroy *req;
  884. int status;
  885. if (adapter->eeh_err)
  886. return -EIO;
  887. if (mutex_lock_interruptible(&adapter->mbox_lock))
  888. return -1;
  889. wrb = wrb_from_mbox(adapter);
  890. req = embedded_payload(wrb);
  891. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  892. OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
  893. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  894. OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
  895. req->hdr.domain = domain;
  896. req->interface_id = cpu_to_le32(interface_id);
  897. status = be_mbox_notify_wait(adapter);
  898. mutex_unlock(&adapter->mbox_lock);
  899. return status;
  900. }
  901. /* Get stats is a non embedded command: the request is not embedded inside
  902. * WRB but is a separate dma memory block
  903. * Uses asynchronous MCC
  904. */
  905. int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
  906. {
  907. struct be_mcc_wrb *wrb;
  908. struct be_cmd_req_hdr *hdr;
  909. struct be_sge *sge;
  910. int status = 0;
  911. if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
  912. be_cmd_get_die_temperature(adapter);
  913. spin_lock_bh(&adapter->mcc_lock);
  914. wrb = wrb_from_mccq(adapter);
  915. if (!wrb) {
  916. status = -EBUSY;
  917. goto err;
  918. }
  919. hdr = nonemb_cmd->va;
  920. sge = nonembedded_sgl(wrb);
  921. be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
  922. OPCODE_ETH_GET_STATISTICS);
  923. be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
  924. OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
  925. if (adapter->generation == BE_GEN3)
  926. hdr->version = 1;
  927. wrb->tag1 = CMD_SUBSYSTEM_ETH;
  928. sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
  929. sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
  930. sge->len = cpu_to_le32(nonemb_cmd->size);
  931. be_mcc_notify(adapter);
  932. adapter->stats_cmd_sent = true;
  933. err:
  934. spin_unlock_bh(&adapter->mcc_lock);
  935. return status;
  936. }
  937. /* Lancer Stats */
  938. int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
  939. struct be_dma_mem *nonemb_cmd)
  940. {
  941. struct be_mcc_wrb *wrb;
  942. struct lancer_cmd_req_pport_stats *req;
  943. struct be_sge *sge;
  944. int status = 0;
  945. spin_lock_bh(&adapter->mcc_lock);
  946. wrb = wrb_from_mccq(adapter);
  947. if (!wrb) {
  948. status = -EBUSY;
  949. goto err;
  950. }
  951. req = nonemb_cmd->va;
  952. sge = nonembedded_sgl(wrb);
  953. be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
  954. OPCODE_ETH_GET_PPORT_STATS);
  955. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
  956. OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
  957. req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
  958. req->cmd_params.params.reset_stats = 0;
  959. wrb->tag1 = CMD_SUBSYSTEM_ETH;
  960. sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
  961. sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
  962. sge->len = cpu_to_le32(nonemb_cmd->size);
  963. be_mcc_notify(adapter);
  964. adapter->stats_cmd_sent = true;
  965. err:
  966. spin_unlock_bh(&adapter->mcc_lock);
  967. return status;
  968. }
  969. /* Uses synchronous mcc */
  970. int be_cmd_link_status_query(struct be_adapter *adapter,
  971. bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
  972. {
  973. struct be_mcc_wrb *wrb;
  974. struct be_cmd_req_link_status *req;
  975. int status;
  976. spin_lock_bh(&adapter->mcc_lock);
  977. wrb = wrb_from_mccq(adapter);
  978. if (!wrb) {
  979. status = -EBUSY;
  980. goto err;
  981. }
  982. req = embedded_payload(wrb);
  983. *link_up = false;
  984. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  985. OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
  986. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  987. OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
  988. status = be_mcc_notify_wait(adapter);
  989. if (!status) {
  990. struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
  991. if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
  992. *link_up = true;
  993. *link_speed = le16_to_cpu(resp->link_speed);
  994. *mac_speed = resp->mac_speed;
  995. }
  996. }
  997. err:
  998. spin_unlock_bh(&adapter->mcc_lock);
  999. return status;
  1000. }
  1001. /* Uses synchronous mcc */
  1002. int be_cmd_get_die_temperature(struct be_adapter *adapter)
  1003. {
  1004. struct be_mcc_wrb *wrb;
  1005. struct be_cmd_req_get_cntl_addnl_attribs *req;
  1006. int status;
  1007. spin_lock_bh(&adapter->mcc_lock);
  1008. wrb = wrb_from_mccq(adapter);
  1009. if (!wrb) {
  1010. status = -EBUSY;
  1011. goto err;
  1012. }
  1013. req = embedded_payload(wrb);
  1014. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1015. OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
  1016. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1017. OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
  1018. status = be_mcc_notify_wait(adapter);
  1019. if (!status) {
  1020. struct be_cmd_resp_get_cntl_addnl_attribs *resp =
  1021. embedded_payload(wrb);
  1022. adapter->drv_stats.be_on_die_temperature =
  1023. resp->on_die_temperature;
  1024. }
  1025. /* If IOCTL fails once, do not bother issuing it again */
  1026. else
  1027. be_get_temp_freq = 0;
  1028. err:
  1029. spin_unlock_bh(&adapter->mcc_lock);
  1030. return status;
  1031. }
  1032. /* Uses synchronous mcc */
  1033. int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
  1034. {
  1035. struct be_mcc_wrb *wrb;
  1036. struct be_cmd_req_get_fat *req;
  1037. int status;
  1038. spin_lock_bh(&adapter->mcc_lock);
  1039. wrb = wrb_from_mccq(adapter);
  1040. if (!wrb) {
  1041. status = -EBUSY;
  1042. goto err;
  1043. }
  1044. req = embedded_payload(wrb);
  1045. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1046. OPCODE_COMMON_MANAGE_FAT);
  1047. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1048. OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
  1049. req->fat_operation = cpu_to_le32(QUERY_FAT);
  1050. status = be_mcc_notify_wait(adapter);
  1051. if (!status) {
  1052. struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
  1053. if (log_size && resp->log_size)
  1054. *log_size = le32_to_cpu(resp->log_size) -
  1055. sizeof(u32);
  1056. }
  1057. err:
  1058. spin_unlock_bh(&adapter->mcc_lock);
  1059. return status;
  1060. }
  1061. void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
  1062. {
  1063. struct be_dma_mem get_fat_cmd;
  1064. struct be_mcc_wrb *wrb;
  1065. struct be_cmd_req_get_fat *req;
  1066. struct be_sge *sge;
  1067. u32 offset = 0, total_size, buf_size,
  1068. log_offset = sizeof(u32), payload_len;
  1069. int status;
  1070. if (buf_len == 0)
  1071. return;
  1072. total_size = buf_len;
  1073. get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
  1074. get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
  1075. get_fat_cmd.size,
  1076. &get_fat_cmd.dma);
  1077. if (!get_fat_cmd.va) {
  1078. status = -ENOMEM;
  1079. dev_err(&adapter->pdev->dev,
  1080. "Memory allocation failure while retrieving FAT data\n");
  1081. return;
  1082. }
  1083. spin_lock_bh(&adapter->mcc_lock);
  1084. while (total_size) {
  1085. buf_size = min(total_size, (u32)60*1024);
  1086. total_size -= buf_size;
  1087. wrb = wrb_from_mccq(adapter);
  1088. if (!wrb) {
  1089. status = -EBUSY;
  1090. goto err;
  1091. }
  1092. req = get_fat_cmd.va;
  1093. sge = nonembedded_sgl(wrb);
  1094. payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
  1095. be_wrb_hdr_prepare(wrb, payload_len, false, 1,
  1096. OPCODE_COMMON_MANAGE_FAT);
  1097. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1098. OPCODE_COMMON_MANAGE_FAT, payload_len);
  1099. sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
  1100. sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
  1101. sge->len = cpu_to_le32(get_fat_cmd.size);
  1102. req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
  1103. req->read_log_offset = cpu_to_le32(log_offset);
  1104. req->read_log_length = cpu_to_le32(buf_size);
  1105. req->data_buffer_size = cpu_to_le32(buf_size);
  1106. status = be_mcc_notify_wait(adapter);
  1107. if (!status) {
  1108. struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
  1109. memcpy(buf + offset,
  1110. resp->data_buffer,
  1111. resp->read_log_length);
  1112. } else {
  1113. dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
  1114. goto err;
  1115. }
  1116. offset += buf_size;
  1117. log_offset += buf_size;
  1118. }
  1119. err:
  1120. pci_free_consistent(adapter->pdev, get_fat_cmd.size,
  1121. get_fat_cmd.va,
  1122. get_fat_cmd.dma);
  1123. spin_unlock_bh(&adapter->mcc_lock);
  1124. }
  1125. /* Uses Mbox */
  1126. int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
  1127. {
  1128. struct be_mcc_wrb *wrb;
  1129. struct be_cmd_req_get_fw_version *req;
  1130. int status;
  1131. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1132. return -1;
  1133. wrb = wrb_from_mbox(adapter);
  1134. req = embedded_payload(wrb);
  1135. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1136. OPCODE_COMMON_GET_FW_VERSION);
  1137. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1138. OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
  1139. status = be_mbox_notify_wait(adapter);
  1140. if (!status) {
  1141. struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
  1142. strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
  1143. }
  1144. mutex_unlock(&adapter->mbox_lock);
  1145. return status;
  1146. }
  1147. /* set the EQ delay interval of an EQ to specified value
  1148. * Uses async mcc
  1149. */
  1150. int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
  1151. {
  1152. struct be_mcc_wrb *wrb;
  1153. struct be_cmd_req_modify_eq_delay *req;
  1154. int status = 0;
  1155. spin_lock_bh(&adapter->mcc_lock);
  1156. wrb = wrb_from_mccq(adapter);
  1157. if (!wrb) {
  1158. status = -EBUSY;
  1159. goto err;
  1160. }
  1161. req = embedded_payload(wrb);
  1162. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1163. OPCODE_COMMON_MODIFY_EQ_DELAY);
  1164. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1165. OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
  1166. req->num_eq = cpu_to_le32(1);
  1167. req->delay[0].eq_id = cpu_to_le32(eq_id);
  1168. req->delay[0].phase = 0;
  1169. req->delay[0].delay_multiplier = cpu_to_le32(eqd);
  1170. be_mcc_notify(adapter);
  1171. err:
  1172. spin_unlock_bh(&adapter->mcc_lock);
  1173. return status;
  1174. }
  1175. /* Uses sycnhronous mcc */
  1176. int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
  1177. u32 num, bool untagged, bool promiscuous)
  1178. {
  1179. struct be_mcc_wrb *wrb;
  1180. struct be_cmd_req_vlan_config *req;
  1181. int status;
  1182. spin_lock_bh(&adapter->mcc_lock);
  1183. wrb = wrb_from_mccq(adapter);
  1184. if (!wrb) {
  1185. status = -EBUSY;
  1186. goto err;
  1187. }
  1188. req = embedded_payload(wrb);
  1189. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1190. OPCODE_COMMON_NTWK_VLAN_CONFIG);
  1191. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1192. OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
  1193. req->interface_id = if_id;
  1194. req->promiscuous = promiscuous;
  1195. req->untagged = untagged;
  1196. req->num_vlan = num;
  1197. if (!promiscuous) {
  1198. memcpy(req->normal_vlan, vtag_array,
  1199. req->num_vlan * sizeof(vtag_array[0]));
  1200. }
  1201. status = be_mcc_notify_wait(adapter);
  1202. err:
  1203. spin_unlock_bh(&adapter->mcc_lock);
  1204. return status;
  1205. }
  1206. /* Uses MCC for this command as it may be called in BH context
  1207. * Uses synchronous mcc
  1208. */
  1209. int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
  1210. {
  1211. struct be_mcc_wrb *wrb;
  1212. struct be_cmd_req_rx_filter *req;
  1213. struct be_dma_mem promiscous_cmd;
  1214. struct be_sge *sge;
  1215. int status;
  1216. memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
  1217. promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
  1218. promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
  1219. promiscous_cmd.size, &promiscous_cmd.dma);
  1220. if (!promiscous_cmd.va) {
  1221. dev_err(&adapter->pdev->dev,
  1222. "Memory allocation failure\n");
  1223. return -ENOMEM;
  1224. }
  1225. spin_lock_bh(&adapter->mcc_lock);
  1226. wrb = wrb_from_mccq(adapter);
  1227. if (!wrb) {
  1228. status = -EBUSY;
  1229. goto err;
  1230. }
  1231. req = promiscous_cmd.va;
  1232. sge = nonembedded_sgl(wrb);
  1233. be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
  1234. OPCODE_COMMON_NTWK_RX_FILTER);
  1235. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1236. OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
  1237. req->if_id = cpu_to_le32(adapter->if_handle);
  1238. req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
  1239. if (en)
  1240. req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
  1241. sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
  1242. sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
  1243. sge->len = cpu_to_le32(promiscous_cmd.size);
  1244. status = be_mcc_notify_wait(adapter);
  1245. err:
  1246. spin_unlock_bh(&adapter->mcc_lock);
  1247. pci_free_consistent(adapter->pdev, promiscous_cmd.size,
  1248. promiscous_cmd.va, promiscous_cmd.dma);
  1249. return status;
  1250. }
  1251. /*
  1252. * Uses MCC for this command as it may be called in BH context
  1253. * (mc == NULL) => multicast promiscuous
  1254. */
  1255. int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
  1256. struct net_device *netdev, struct be_dma_mem *mem)
  1257. {
  1258. struct be_mcc_wrb *wrb;
  1259. struct be_cmd_req_mcast_mac_config *req = mem->va;
  1260. struct be_sge *sge;
  1261. int status;
  1262. spin_lock_bh(&adapter->mcc_lock);
  1263. wrb = wrb_from_mccq(adapter);
  1264. if (!wrb) {
  1265. status = -EBUSY;
  1266. goto err;
  1267. }
  1268. sge = nonembedded_sgl(wrb);
  1269. memset(req, 0, sizeof(*req));
  1270. be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
  1271. OPCODE_COMMON_NTWK_MULTICAST_SET);
  1272. sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
  1273. sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
  1274. sge->len = cpu_to_le32(mem->size);
  1275. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1276. OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
  1277. req->interface_id = if_id;
  1278. if (netdev) {
  1279. int i;
  1280. struct netdev_hw_addr *ha;
  1281. req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
  1282. i = 0;
  1283. netdev_for_each_mc_addr(ha, netdev)
  1284. memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
  1285. } else {
  1286. req->promiscuous = 1;
  1287. }
  1288. status = be_mcc_notify_wait(adapter);
  1289. err:
  1290. spin_unlock_bh(&adapter->mcc_lock);
  1291. return status;
  1292. }
  1293. /* Uses synchrounous mcc */
  1294. int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
  1295. {
  1296. struct be_mcc_wrb *wrb;
  1297. struct be_cmd_req_set_flow_control *req;
  1298. int status;
  1299. spin_lock_bh(&adapter->mcc_lock);
  1300. wrb = wrb_from_mccq(adapter);
  1301. if (!wrb) {
  1302. status = -EBUSY;
  1303. goto err;
  1304. }
  1305. req = embedded_payload(wrb);
  1306. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1307. OPCODE_COMMON_SET_FLOW_CONTROL);
  1308. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1309. OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
  1310. req->tx_flow_control = cpu_to_le16((u16)tx_fc);
  1311. req->rx_flow_control = cpu_to_le16((u16)rx_fc);
  1312. status = be_mcc_notify_wait(adapter);
  1313. err:
  1314. spin_unlock_bh(&adapter->mcc_lock);
  1315. return status;
  1316. }
  1317. /* Uses sycn mcc */
  1318. int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
  1319. {
  1320. struct be_mcc_wrb *wrb;
  1321. struct be_cmd_req_get_flow_control *req;
  1322. int status;
  1323. spin_lock_bh(&adapter->mcc_lock);
  1324. wrb = wrb_from_mccq(adapter);
  1325. if (!wrb) {
  1326. status = -EBUSY;
  1327. goto err;
  1328. }
  1329. req = embedded_payload(wrb);
  1330. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1331. OPCODE_COMMON_GET_FLOW_CONTROL);
  1332. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1333. OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
  1334. status = be_mcc_notify_wait(adapter);
  1335. if (!status) {
  1336. struct be_cmd_resp_get_flow_control *resp =
  1337. embedded_payload(wrb);
  1338. *tx_fc = le16_to_cpu(resp->tx_flow_control);
  1339. *rx_fc = le16_to_cpu(resp->rx_flow_control);
  1340. }
  1341. err:
  1342. spin_unlock_bh(&adapter->mcc_lock);
  1343. return status;
  1344. }
  1345. /* Uses mbox */
  1346. int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
  1347. u32 *mode, u32 *caps)
  1348. {
  1349. struct be_mcc_wrb *wrb;
  1350. struct be_cmd_req_query_fw_cfg *req;
  1351. int status;
  1352. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1353. return -1;
  1354. wrb = wrb_from_mbox(adapter);
  1355. req = embedded_payload(wrb);
  1356. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1357. OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
  1358. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1359. OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
  1360. status = be_mbox_notify_wait(adapter);
  1361. if (!status) {
  1362. struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
  1363. *port_num = le32_to_cpu(resp->phys_port);
  1364. *mode = le32_to_cpu(resp->function_mode);
  1365. *caps = le32_to_cpu(resp->function_caps);
  1366. }
  1367. mutex_unlock(&adapter->mbox_lock);
  1368. return status;
  1369. }
  1370. /* Uses mbox */
  1371. int be_cmd_reset_function(struct be_adapter *adapter)
  1372. {
  1373. struct be_mcc_wrb *wrb;
  1374. struct be_cmd_req_hdr *req;
  1375. int status;
  1376. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1377. return -1;
  1378. wrb = wrb_from_mbox(adapter);
  1379. req = embedded_payload(wrb);
  1380. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1381. OPCODE_COMMON_FUNCTION_RESET);
  1382. be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
  1383. OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
  1384. status = be_mbox_notify_wait(adapter);
  1385. mutex_unlock(&adapter->mbox_lock);
  1386. return status;
  1387. }
  1388. int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
  1389. {
  1390. struct be_mcc_wrb *wrb;
  1391. struct be_cmd_req_rss_config *req;
  1392. u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
  1393. 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
  1394. int status;
  1395. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1396. return -1;
  1397. wrb = wrb_from_mbox(adapter);
  1398. req = embedded_payload(wrb);
  1399. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1400. OPCODE_ETH_RSS_CONFIG);
  1401. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
  1402. OPCODE_ETH_RSS_CONFIG, sizeof(*req));
  1403. req->if_id = cpu_to_le32(adapter->if_handle);
  1404. req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
  1405. req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
  1406. memcpy(req->cpu_table, rsstable, table_size);
  1407. memcpy(req->hash, myhash, sizeof(myhash));
  1408. be_dws_cpu_to_le(req->hash, sizeof(req->hash));
  1409. status = be_mbox_notify_wait(adapter);
  1410. mutex_unlock(&adapter->mbox_lock);
  1411. return status;
  1412. }
  1413. /* Uses sync mcc */
  1414. int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
  1415. u8 bcn, u8 sts, u8 state)
  1416. {
  1417. struct be_mcc_wrb *wrb;
  1418. struct be_cmd_req_enable_disable_beacon *req;
  1419. int status;
  1420. spin_lock_bh(&adapter->mcc_lock);
  1421. wrb = wrb_from_mccq(adapter);
  1422. if (!wrb) {
  1423. status = -EBUSY;
  1424. goto err;
  1425. }
  1426. req = embedded_payload(wrb);
  1427. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1428. OPCODE_COMMON_ENABLE_DISABLE_BEACON);
  1429. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1430. OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
  1431. req->port_num = port_num;
  1432. req->beacon_state = state;
  1433. req->beacon_duration = bcn;
  1434. req->status_duration = sts;
  1435. status = be_mcc_notify_wait(adapter);
  1436. err:
  1437. spin_unlock_bh(&adapter->mcc_lock);
  1438. return status;
  1439. }
  1440. /* Uses sync mcc */
  1441. int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
  1442. {
  1443. struct be_mcc_wrb *wrb;
  1444. struct be_cmd_req_get_beacon_state *req;
  1445. int status;
  1446. spin_lock_bh(&adapter->mcc_lock);
  1447. wrb = wrb_from_mccq(adapter);
  1448. if (!wrb) {
  1449. status = -EBUSY;
  1450. goto err;
  1451. }
  1452. req = embedded_payload(wrb);
  1453. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1454. OPCODE_COMMON_GET_BEACON_STATE);
  1455. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1456. OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
  1457. req->port_num = port_num;
  1458. status = be_mcc_notify_wait(adapter);
  1459. if (!status) {
  1460. struct be_cmd_resp_get_beacon_state *resp =
  1461. embedded_payload(wrb);
  1462. *state = resp->beacon_state;
  1463. }
  1464. err:
  1465. spin_unlock_bh(&adapter->mcc_lock);
  1466. return status;
  1467. }
  1468. int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
  1469. u32 data_size, u32 data_offset, const char *obj_name,
  1470. u32 *data_written, u8 *addn_status)
  1471. {
  1472. struct be_mcc_wrb *wrb;
  1473. struct lancer_cmd_req_write_object *req;
  1474. struct lancer_cmd_resp_write_object *resp;
  1475. void *ctxt = NULL;
  1476. int status;
  1477. spin_lock_bh(&adapter->mcc_lock);
  1478. adapter->flash_status = 0;
  1479. wrb = wrb_from_mccq(adapter);
  1480. if (!wrb) {
  1481. status = -EBUSY;
  1482. goto err_unlock;
  1483. }
  1484. req = embedded_payload(wrb);
  1485. be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
  1486. true, 1, OPCODE_COMMON_WRITE_OBJECT);
  1487. wrb->tag1 = CMD_SUBSYSTEM_COMMON;
  1488. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1489. OPCODE_COMMON_WRITE_OBJECT,
  1490. sizeof(struct lancer_cmd_req_write_object));
  1491. ctxt = &req->context;
  1492. AMAP_SET_BITS(struct amap_lancer_write_obj_context,
  1493. write_length, ctxt, data_size);
  1494. if (data_size == 0)
  1495. AMAP_SET_BITS(struct amap_lancer_write_obj_context,
  1496. eof, ctxt, 1);
  1497. else
  1498. AMAP_SET_BITS(struct amap_lancer_write_obj_context,
  1499. eof, ctxt, 0);
  1500. be_dws_cpu_to_le(ctxt, sizeof(req->context));
  1501. req->write_offset = cpu_to_le32(data_offset);
  1502. strcpy(req->object_name, obj_name);
  1503. req->descriptor_count = cpu_to_le32(1);
  1504. req->buf_len = cpu_to_le32(data_size);
  1505. req->addr_low = cpu_to_le32((cmd->dma +
  1506. sizeof(struct lancer_cmd_req_write_object))
  1507. & 0xFFFFFFFF);
  1508. req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
  1509. sizeof(struct lancer_cmd_req_write_object)));
  1510. be_mcc_notify(adapter);
  1511. spin_unlock_bh(&adapter->mcc_lock);
  1512. if (!wait_for_completion_timeout(&adapter->flash_compl,
  1513. msecs_to_jiffies(12000)))
  1514. status = -1;
  1515. else
  1516. status = adapter->flash_status;
  1517. resp = embedded_payload(wrb);
  1518. if (!status) {
  1519. *data_written = le32_to_cpu(resp->actual_write_len);
  1520. } else {
  1521. *addn_status = resp->additional_status;
  1522. status = resp->status;
  1523. }
  1524. return status;
  1525. err_unlock:
  1526. spin_unlock_bh(&adapter->mcc_lock);
  1527. return status;
  1528. }
  1529. int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
  1530. u32 flash_type, u32 flash_opcode, u32 buf_size)
  1531. {
  1532. struct be_mcc_wrb *wrb;
  1533. struct be_cmd_write_flashrom *req;
  1534. struct be_sge *sge;
  1535. int status;
  1536. spin_lock_bh(&adapter->mcc_lock);
  1537. adapter->flash_status = 0;
  1538. wrb = wrb_from_mccq(adapter);
  1539. if (!wrb) {
  1540. status = -EBUSY;
  1541. goto err_unlock;
  1542. }
  1543. req = cmd->va;
  1544. sge = nonembedded_sgl(wrb);
  1545. be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
  1546. OPCODE_COMMON_WRITE_FLASHROM);
  1547. wrb->tag1 = CMD_SUBSYSTEM_COMMON;
  1548. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1549. OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
  1550. sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
  1551. sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
  1552. sge->len = cpu_to_le32(cmd->size);
  1553. req->params.op_type = cpu_to_le32(flash_type);
  1554. req->params.op_code = cpu_to_le32(flash_opcode);
  1555. req->params.data_buf_size = cpu_to_le32(buf_size);
  1556. be_mcc_notify(adapter);
  1557. spin_unlock_bh(&adapter->mcc_lock);
  1558. if (!wait_for_completion_timeout(&adapter->flash_compl,
  1559. msecs_to_jiffies(12000)))
  1560. status = -1;
  1561. else
  1562. status = adapter->flash_status;
  1563. return status;
  1564. err_unlock:
  1565. spin_unlock_bh(&adapter->mcc_lock);
  1566. return status;
  1567. }
  1568. int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
  1569. int offset)
  1570. {
  1571. struct be_mcc_wrb *wrb;
  1572. struct be_cmd_write_flashrom *req;
  1573. int status;
  1574. spin_lock_bh(&adapter->mcc_lock);
  1575. wrb = wrb_from_mccq(adapter);
  1576. if (!wrb) {
  1577. status = -EBUSY;
  1578. goto err;
  1579. }
  1580. req = embedded_payload(wrb);
  1581. be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
  1582. OPCODE_COMMON_READ_FLASHROM);
  1583. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1584. OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
  1585. req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
  1586. req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
  1587. req->params.offset = cpu_to_le32(offset);
  1588. req->params.data_buf_size = cpu_to_le32(0x4);
  1589. status = be_mcc_notify_wait(adapter);
  1590. if (!status)
  1591. memcpy(flashed_crc, req->params.data_buf, 4);
  1592. err:
  1593. spin_unlock_bh(&adapter->mcc_lock);
  1594. return status;
  1595. }
  1596. int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
  1597. struct be_dma_mem *nonemb_cmd)
  1598. {
  1599. struct be_mcc_wrb *wrb;
  1600. struct be_cmd_req_acpi_wol_magic_config *req;
  1601. struct be_sge *sge;
  1602. int status;
  1603. spin_lock_bh(&adapter->mcc_lock);
  1604. wrb = wrb_from_mccq(adapter);
  1605. if (!wrb) {
  1606. status = -EBUSY;
  1607. goto err;
  1608. }
  1609. req = nonemb_cmd->va;
  1610. sge = nonembedded_sgl(wrb);
  1611. be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
  1612. OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
  1613. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
  1614. OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
  1615. memcpy(req->magic_mac, mac, ETH_ALEN);
  1616. sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
  1617. sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
  1618. sge->len = cpu_to_le32(nonemb_cmd->size);
  1619. status = be_mcc_notify_wait(adapter);
  1620. err:
  1621. spin_unlock_bh(&adapter->mcc_lock);
  1622. return status;
  1623. }
  1624. int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
  1625. u8 loopback_type, u8 enable)
  1626. {
  1627. struct be_mcc_wrb *wrb;
  1628. struct be_cmd_req_set_lmode *req;
  1629. int status;
  1630. spin_lock_bh(&adapter->mcc_lock);
  1631. wrb = wrb_from_mccq(adapter);
  1632. if (!wrb) {
  1633. status = -EBUSY;
  1634. goto err;
  1635. }
  1636. req = embedded_payload(wrb);
  1637. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1638. OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
  1639. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
  1640. OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  1641. sizeof(*req));
  1642. req->src_port = port_num;
  1643. req->dest_port = port_num;
  1644. req->loopback_type = loopback_type;
  1645. req->loopback_state = enable;
  1646. status = be_mcc_notify_wait(adapter);
  1647. err:
  1648. spin_unlock_bh(&adapter->mcc_lock);
  1649. return status;
  1650. }
  1651. int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
  1652. u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
  1653. {
  1654. struct be_mcc_wrb *wrb;
  1655. struct be_cmd_req_loopback_test *req;
  1656. int status;
  1657. spin_lock_bh(&adapter->mcc_lock);
  1658. wrb = wrb_from_mccq(adapter);
  1659. if (!wrb) {
  1660. status = -EBUSY;
  1661. goto err;
  1662. }
  1663. req = embedded_payload(wrb);
  1664. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1665. OPCODE_LOWLEVEL_LOOPBACK_TEST);
  1666. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
  1667. OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
  1668. req->hdr.timeout = cpu_to_le32(4);
  1669. req->pattern = cpu_to_le64(pattern);
  1670. req->src_port = cpu_to_le32(port_num);
  1671. req->dest_port = cpu_to_le32(port_num);
  1672. req->pkt_size = cpu_to_le32(pkt_size);
  1673. req->num_pkts = cpu_to_le32(num_pkts);
  1674. req->loopback_type = cpu_to_le32(loopback_type);
  1675. status = be_mcc_notify_wait(adapter);
  1676. if (!status) {
  1677. struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
  1678. status = le32_to_cpu(resp->status);
  1679. }
  1680. err:
  1681. spin_unlock_bh(&adapter->mcc_lock);
  1682. return status;
  1683. }
  1684. int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
  1685. u32 byte_cnt, struct be_dma_mem *cmd)
  1686. {
  1687. struct be_mcc_wrb *wrb;
  1688. struct be_cmd_req_ddrdma_test *req;
  1689. struct be_sge *sge;
  1690. int status;
  1691. int i, j = 0;
  1692. spin_lock_bh(&adapter->mcc_lock);
  1693. wrb = wrb_from_mccq(adapter);
  1694. if (!wrb) {
  1695. status = -EBUSY;
  1696. goto err;
  1697. }
  1698. req = cmd->va;
  1699. sge = nonembedded_sgl(wrb);
  1700. be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
  1701. OPCODE_LOWLEVEL_HOST_DDR_DMA);
  1702. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
  1703. OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
  1704. sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
  1705. sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
  1706. sge->len = cpu_to_le32(cmd->size);
  1707. req->pattern = cpu_to_le64(pattern);
  1708. req->byte_count = cpu_to_le32(byte_cnt);
  1709. for (i = 0; i < byte_cnt; i++) {
  1710. req->snd_buff[i] = (u8)(pattern >> (j*8));
  1711. j++;
  1712. if (j > 7)
  1713. j = 0;
  1714. }
  1715. status = be_mcc_notify_wait(adapter);
  1716. if (!status) {
  1717. struct be_cmd_resp_ddrdma_test *resp;
  1718. resp = cmd->va;
  1719. if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
  1720. resp->snd_err) {
  1721. status = -1;
  1722. }
  1723. }
  1724. err:
  1725. spin_unlock_bh(&adapter->mcc_lock);
  1726. return status;
  1727. }
  1728. int be_cmd_get_seeprom_data(struct be_adapter *adapter,
  1729. struct be_dma_mem *nonemb_cmd)
  1730. {
  1731. struct be_mcc_wrb *wrb;
  1732. struct be_cmd_req_seeprom_read *req;
  1733. struct be_sge *sge;
  1734. int status;
  1735. spin_lock_bh(&adapter->mcc_lock);
  1736. wrb = wrb_from_mccq(adapter);
  1737. if (!wrb) {
  1738. status = -EBUSY;
  1739. goto err;
  1740. }
  1741. req = nonemb_cmd->va;
  1742. sge = nonembedded_sgl(wrb);
  1743. be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
  1744. OPCODE_COMMON_SEEPROM_READ);
  1745. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1746. OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
  1747. sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
  1748. sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
  1749. sge->len = cpu_to_le32(nonemb_cmd->size);
  1750. status = be_mcc_notify_wait(adapter);
  1751. err:
  1752. spin_unlock_bh(&adapter->mcc_lock);
  1753. return status;
  1754. }
  1755. int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
  1756. {
  1757. struct be_mcc_wrb *wrb;
  1758. struct be_cmd_req_get_phy_info *req;
  1759. struct be_sge *sge;
  1760. int status;
  1761. spin_lock_bh(&adapter->mcc_lock);
  1762. wrb = wrb_from_mccq(adapter);
  1763. if (!wrb) {
  1764. status = -EBUSY;
  1765. goto err;
  1766. }
  1767. req = cmd->va;
  1768. sge = nonembedded_sgl(wrb);
  1769. be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
  1770. OPCODE_COMMON_GET_PHY_DETAILS);
  1771. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1772. OPCODE_COMMON_GET_PHY_DETAILS,
  1773. sizeof(*req));
  1774. sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
  1775. sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
  1776. sge->len = cpu_to_le32(cmd->size);
  1777. status = be_mcc_notify_wait(adapter);
  1778. err:
  1779. spin_unlock_bh(&adapter->mcc_lock);
  1780. return status;
  1781. }
  1782. int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
  1783. {
  1784. struct be_mcc_wrb *wrb;
  1785. struct be_cmd_req_set_qos *req;
  1786. int status;
  1787. spin_lock_bh(&adapter->mcc_lock);
  1788. wrb = wrb_from_mccq(adapter);
  1789. if (!wrb) {
  1790. status = -EBUSY;
  1791. goto err;
  1792. }
  1793. req = embedded_payload(wrb);
  1794. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1795. OPCODE_COMMON_SET_QOS);
  1796. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1797. OPCODE_COMMON_SET_QOS, sizeof(*req));
  1798. req->hdr.domain = domain;
  1799. req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
  1800. req->max_bps_nic = cpu_to_le32(bps);
  1801. status = be_mcc_notify_wait(adapter);
  1802. err:
  1803. spin_unlock_bh(&adapter->mcc_lock);
  1804. return status;
  1805. }
  1806. int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
  1807. {
  1808. struct be_mcc_wrb *wrb;
  1809. struct be_cmd_req_cntl_attribs *req;
  1810. struct be_cmd_resp_cntl_attribs *resp;
  1811. struct be_sge *sge;
  1812. int status;
  1813. int payload_len = max(sizeof(*req), sizeof(*resp));
  1814. struct mgmt_controller_attrib *attribs;
  1815. struct be_dma_mem attribs_cmd;
  1816. memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
  1817. attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
  1818. attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
  1819. &attribs_cmd.dma);
  1820. if (!attribs_cmd.va) {
  1821. dev_err(&adapter->pdev->dev,
  1822. "Memory allocation failure\n");
  1823. return -ENOMEM;
  1824. }
  1825. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1826. return -1;
  1827. wrb = wrb_from_mbox(adapter);
  1828. if (!wrb) {
  1829. status = -EBUSY;
  1830. goto err;
  1831. }
  1832. req = attribs_cmd.va;
  1833. sge = nonembedded_sgl(wrb);
  1834. be_wrb_hdr_prepare(wrb, payload_len, false, 1,
  1835. OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
  1836. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1837. OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
  1838. sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
  1839. sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
  1840. sge->len = cpu_to_le32(attribs_cmd.size);
  1841. status = be_mbox_notify_wait(adapter);
  1842. if (!status) {
  1843. attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
  1844. sizeof(struct be_cmd_resp_hdr));
  1845. adapter->hba_port_num = attribs->hba_attribs.phy_port;
  1846. }
  1847. err:
  1848. mutex_unlock(&adapter->mbox_lock);
  1849. pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
  1850. attribs_cmd.dma);
  1851. return status;
  1852. }
  1853. /* Uses mbox */
  1854. int be_cmd_check_native_mode(struct be_adapter *adapter)
  1855. {
  1856. struct be_mcc_wrb *wrb;
  1857. struct be_cmd_req_set_func_cap *req;
  1858. int status;
  1859. if (mutex_lock_interruptible(&adapter->mbox_lock))
  1860. return -1;
  1861. wrb = wrb_from_mbox(adapter);
  1862. if (!wrb) {
  1863. status = -EBUSY;
  1864. goto err;
  1865. }
  1866. req = embedded_payload(wrb);
  1867. be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
  1868. OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
  1869. be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
  1870. OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
  1871. req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
  1872. CAPABILITY_BE3_NATIVE_ERX_API);
  1873. req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
  1874. status = be_mbox_notify_wait(adapter);
  1875. if (!status) {
  1876. struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
  1877. adapter->be3_native = le32_to_cpu(resp->cap_flags) &
  1878. CAPABILITY_BE3_NATIVE_ERX_API;
  1879. }
  1880. err:
  1881. mutex_unlock(&adapter->mbox_lock);
  1882. return status;
  1883. }