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/drivers/net/irda/nsc-ircc.c

https://bitbucket.org/ndreys/linux-sunxi
C | 2420 lines | 1484 code | 398 blank | 538 comment | 193 complexity | 3536af27911af34bfca29a1f8b0f9ce4 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*********************************************************************
  2. *
  3. * Filename: nsc-ircc.c
  4. * Version: 1.0
  5. * Description: Driver for the NSC PC'108 and PC'338 IrDA chipsets
  6. * Status: Stable.
  7. * Author: Dag Brattli <dagb@cs.uit.no>
  8. * Created at: Sat Nov 7 21:43:15 1998
  9. * Modified at: Wed Mar 1 11:29:34 2000
  10. * Modified by: Dag Brattli <dagb@cs.uit.no>
  11. *
  12. * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
  13. * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
  14. * Copyright (c) 1998 Actisys Corp., www.actisys.com
  15. * Copyright (c) 2000-2004 Jean Tourrilhes <jt@hpl.hp.com>
  16. * All Rights Reserved
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License as
  20. * published by the Free Software Foundation; either version 2 of
  21. * the License, or (at your option) any later version.
  22. *
  23. * Neither Dag Brattli nor University of Troms?¸ admit liability nor
  24. * provide warranty for any of this software. This material is
  25. * provided "AS-IS" and at no charge.
  26. *
  27. * Notice that all functions that needs to access the chip in _any_
  28. * way, must save BSR register on entry, and restore it on exit.
  29. * It is _very_ important to follow this policy!
  30. *
  31. * __u8 bank;
  32. *
  33. * bank = inb(iobase+BSR);
  34. *
  35. * do_your_stuff_here();
  36. *
  37. * outb(bank, iobase+BSR);
  38. *
  39. * If you find bugs in this file, its very likely that the same bug
  40. * will also be in w83977af_ir.c since the implementations are quite
  41. * similar.
  42. *
  43. ********************************************************************/
  44. #include <linux/module.h>
  45. #include <linux/gfp.h>
  46. #include <linux/kernel.h>
  47. #include <linux/types.h>
  48. #include <linux/skbuff.h>
  49. #include <linux/netdevice.h>
  50. #include <linux/ioport.h>
  51. #include <linux/delay.h>
  52. #include <linux/init.h>
  53. #include <linux/rtnetlink.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/pnp.h>
  56. #include <linux/platform_device.h>
  57. #include <asm/io.h>
  58. #include <asm/dma.h>
  59. #include <asm/byteorder.h>
  60. #include <net/irda/wrapper.h>
  61. #include <net/irda/irda.h>
  62. #include <net/irda/irda_device.h>
  63. #include "nsc-ircc.h"
  64. #define CHIP_IO_EXTENT 8
  65. #define BROKEN_DONGLE_ID
  66. static char *driver_name = "nsc-ircc";
  67. /* Power Management */
  68. #define NSC_IRCC_DRIVER_NAME "nsc-ircc"
  69. static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
  70. static int nsc_ircc_resume(struct platform_device *dev);
  71. static struct platform_driver nsc_ircc_driver = {
  72. .suspend = nsc_ircc_suspend,
  73. .resume = nsc_ircc_resume,
  74. .driver = {
  75. .name = NSC_IRCC_DRIVER_NAME,
  76. },
  77. };
  78. /* Module parameters */
  79. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  80. static int dongle_id;
  81. /* Use BIOS settions by default, but user may supply module parameters */
  82. static unsigned int io[] = { ~0, ~0, ~0, ~0, ~0 };
  83. static unsigned int irq[] = { 0, 0, 0, 0, 0 };
  84. static unsigned int dma[] = { 0, 0, 0, 0, 0 };
  85. static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info);
  86. static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info);
  87. static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info);
  88. static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info);
  89. static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info);
  90. static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info);
  91. #ifdef CONFIG_PNP
  92. static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id);
  93. #endif
  94. /* These are the known NSC chips */
  95. static nsc_chip_t chips[] = {
  96. /* Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */
  97. { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0,
  98. nsc_ircc_probe_108, nsc_ircc_init_108 },
  99. { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8,
  100. nsc_ircc_probe_338, nsc_ircc_init_338 },
  101. /* Contributed by Steffen Pingel - IBM X40 */
  102. { "PC8738x", { 0x164e, 0x4e, 0x2e }, 0x20, 0xf4, 0xff,
  103. nsc_ircc_probe_39x, nsc_ircc_init_39x },
  104. /* Contributed by Jan Frey - IBM A30/A31 */
  105. { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff,
  106. nsc_ircc_probe_39x, nsc_ircc_init_39x },
  107. /* IBM ThinkPads using PC8738x (T60/X60/Z60) */
  108. { "IBM-PC8738x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff,
  109. nsc_ircc_probe_39x, nsc_ircc_init_39x },
  110. /* IBM ThinkPads using PC8394T (T43/R52/?) */
  111. { "IBM-PC8394T", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf9, 0xff,
  112. nsc_ircc_probe_39x, nsc_ircc_init_39x },
  113. { NULL }
  114. };
  115. static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL, NULL };
  116. static char *dongle_types[] = {
  117. "Differential serial interface",
  118. "Differential serial interface",
  119. "Reserved",
  120. "Reserved",
  121. "Sharp RY5HD01",
  122. "Reserved",
  123. "Single-ended serial interface",
  124. "Consumer-IR only",
  125. "HP HSDL-2300, HP HSDL-3600/HSDL-3610",
  126. "IBM31T1100 or Temic TFDS6000/TFDS6500",
  127. "Reserved",
  128. "Reserved",
  129. "HP HSDL-1100/HSDL-2100",
  130. "HP HSDL-1100/HSDL-2100",
  131. "Supports SIR Mode only",
  132. "No dongle connected",
  133. };
  134. /* PNP probing */
  135. static chipio_t pnp_info;
  136. static const struct pnp_device_id nsc_ircc_pnp_table[] = {
  137. { .id = "NSC6001", .driver_data = 0 },
  138. { .id = "HWPC224", .driver_data = 0 },
  139. { .id = "IBM0071", .driver_data = NSC_FORCE_DONGLE_TYPE9 },
  140. { }
  141. };
  142. MODULE_DEVICE_TABLE(pnp, nsc_ircc_pnp_table);
  143. static struct pnp_driver nsc_ircc_pnp_driver = {
  144. #ifdef CONFIG_PNP
  145. .name = "nsc-ircc",
  146. .id_table = nsc_ircc_pnp_table,
  147. .probe = nsc_ircc_pnp_probe,
  148. #endif
  149. };
  150. /* Some prototypes */
  151. static int nsc_ircc_open(chipio_t *info);
  152. static int nsc_ircc_close(struct nsc_ircc_cb *self);
  153. static int nsc_ircc_setup(chipio_t *info);
  154. static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self);
  155. static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self);
  156. static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
  157. static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb,
  158. struct net_device *dev);
  159. static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb,
  160. struct net_device *dev);
  161. static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
  162. static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
  163. static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud);
  164. static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self);
  165. static int nsc_ircc_read_dongle_id (int iobase);
  166. static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
  167. static int nsc_ircc_net_open(struct net_device *dev);
  168. static int nsc_ircc_net_close(struct net_device *dev);
  169. static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  170. /* Globals */
  171. static int pnp_registered;
  172. static int pnp_succeeded;
  173. /*
  174. * Function nsc_ircc_init ()
  175. *
  176. * Initialize chip. Just try to find out how many chips we are dealing with
  177. * and where they are
  178. */
  179. static int __init nsc_ircc_init(void)
  180. {
  181. chipio_t info;
  182. nsc_chip_t *chip;
  183. int ret;
  184. int cfg_base;
  185. int cfg, id;
  186. int reg;
  187. int i = 0;
  188. ret = platform_driver_register(&nsc_ircc_driver);
  189. if (ret) {
  190. IRDA_ERROR("%s, Can't register driver!\n", driver_name);
  191. return ret;
  192. }
  193. /* Register with PnP subsystem to detect disable ports */
  194. ret = pnp_register_driver(&nsc_ircc_pnp_driver);
  195. if (!ret)
  196. pnp_registered = 1;
  197. ret = -ENODEV;
  198. /* Probe for all the NSC chipsets we know about */
  199. for (chip = chips; chip->name ; chip++) {
  200. IRDA_DEBUG(2, "%s(), Probing for %s ...\n", __func__,
  201. chip->name);
  202. /* Try all config registers for this chip */
  203. for (cfg = 0; cfg < ARRAY_SIZE(chip->cfg); cfg++) {
  204. cfg_base = chip->cfg[cfg];
  205. if (!cfg_base)
  206. continue;
  207. /* Read index register */
  208. reg = inb(cfg_base);
  209. if (reg == 0xff) {
  210. IRDA_DEBUG(2, "%s() no chip at 0x%03x\n", __func__, cfg_base);
  211. continue;
  212. }
  213. /* Read chip identification register */
  214. outb(chip->cid_index, cfg_base);
  215. id = inb(cfg_base+1);
  216. if ((id & chip->cid_mask) == chip->cid_value) {
  217. IRDA_DEBUG(2, "%s() Found %s chip, revision=%d\n",
  218. __func__, chip->name, id & ~chip->cid_mask);
  219. /*
  220. * If we found a correct PnP setting,
  221. * we first try it.
  222. */
  223. if (pnp_succeeded) {
  224. memset(&info, 0, sizeof(chipio_t));
  225. info.cfg_base = cfg_base;
  226. info.fir_base = pnp_info.fir_base;
  227. info.dma = pnp_info.dma;
  228. info.irq = pnp_info.irq;
  229. if (info.fir_base < 0x2000) {
  230. IRDA_MESSAGE("%s, chip->init\n", driver_name);
  231. chip->init(chip, &info);
  232. } else
  233. chip->probe(chip, &info);
  234. if (nsc_ircc_open(&info) >= 0)
  235. ret = 0;
  236. }
  237. /*
  238. * Opening based on PnP values failed.
  239. * Let's fallback to user values, or probe
  240. * the chip.
  241. */
  242. if (ret) {
  243. IRDA_DEBUG(2, "%s, PnP init failed\n", driver_name);
  244. memset(&info, 0, sizeof(chipio_t));
  245. info.cfg_base = cfg_base;
  246. info.fir_base = io[i];
  247. info.dma = dma[i];
  248. info.irq = irq[i];
  249. /*
  250. * If the user supplies the base address, then
  251. * we init the chip, if not we probe the values
  252. * set by the BIOS
  253. */
  254. if (io[i] < 0x2000) {
  255. chip->init(chip, &info);
  256. } else
  257. chip->probe(chip, &info);
  258. if (nsc_ircc_open(&info) >= 0)
  259. ret = 0;
  260. }
  261. i++;
  262. } else {
  263. IRDA_DEBUG(2, "%s(), Wrong chip id=0x%02x\n", __func__, id);
  264. }
  265. }
  266. }
  267. if (ret) {
  268. platform_driver_unregister(&nsc_ircc_driver);
  269. pnp_unregister_driver(&nsc_ircc_pnp_driver);
  270. pnp_registered = 0;
  271. }
  272. return ret;
  273. }
  274. /*
  275. * Function nsc_ircc_cleanup ()
  276. *
  277. * Close all configured chips
  278. *
  279. */
  280. static void __exit nsc_ircc_cleanup(void)
  281. {
  282. int i;
  283. for (i = 0; i < ARRAY_SIZE(dev_self); i++) {
  284. if (dev_self[i])
  285. nsc_ircc_close(dev_self[i]);
  286. }
  287. platform_driver_unregister(&nsc_ircc_driver);
  288. if (pnp_registered)
  289. pnp_unregister_driver(&nsc_ircc_pnp_driver);
  290. pnp_registered = 0;
  291. }
  292. static const struct net_device_ops nsc_ircc_sir_ops = {
  293. .ndo_open = nsc_ircc_net_open,
  294. .ndo_stop = nsc_ircc_net_close,
  295. .ndo_start_xmit = nsc_ircc_hard_xmit_sir,
  296. .ndo_do_ioctl = nsc_ircc_net_ioctl,
  297. };
  298. static const struct net_device_ops nsc_ircc_fir_ops = {
  299. .ndo_open = nsc_ircc_net_open,
  300. .ndo_stop = nsc_ircc_net_close,
  301. .ndo_start_xmit = nsc_ircc_hard_xmit_fir,
  302. .ndo_do_ioctl = nsc_ircc_net_ioctl,
  303. };
  304. /*
  305. * Function nsc_ircc_open (iobase, irq)
  306. *
  307. * Open driver instance
  308. *
  309. */
  310. static int __init nsc_ircc_open(chipio_t *info)
  311. {
  312. struct net_device *dev;
  313. struct nsc_ircc_cb *self;
  314. void *ret;
  315. int err, chip_index;
  316. IRDA_DEBUG(2, "%s()\n", __func__);
  317. for (chip_index = 0; chip_index < ARRAY_SIZE(dev_self); chip_index++) {
  318. if (!dev_self[chip_index])
  319. break;
  320. }
  321. if (chip_index == ARRAY_SIZE(dev_self)) {
  322. IRDA_ERROR("%s(), maximum number of supported chips reached!\n", __func__);
  323. return -ENOMEM;
  324. }
  325. IRDA_MESSAGE("%s, Found chip at base=0x%03x\n", driver_name,
  326. info->cfg_base);
  327. if ((nsc_ircc_setup(info)) == -1)
  328. return -1;
  329. IRDA_MESSAGE("%s, driver loaded (Dag Brattli)\n", driver_name);
  330. dev = alloc_irdadev(sizeof(struct nsc_ircc_cb));
  331. if (dev == NULL) {
  332. IRDA_ERROR("%s(), can't allocate memory for "
  333. "control block!\n", __func__);
  334. return -ENOMEM;
  335. }
  336. self = netdev_priv(dev);
  337. self->netdev = dev;
  338. spin_lock_init(&self->lock);
  339. /* Need to store self somewhere */
  340. dev_self[chip_index] = self;
  341. self->index = chip_index;
  342. /* Initialize IO */
  343. self->io.cfg_base = info->cfg_base;
  344. self->io.fir_base = info->fir_base;
  345. self->io.irq = info->irq;
  346. self->io.fir_ext = CHIP_IO_EXTENT;
  347. self->io.dma = info->dma;
  348. self->io.fifo_size = 32;
  349. /* Reserve the ioports that we need */
  350. ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name);
  351. if (!ret) {
  352. IRDA_WARNING("%s(), can't get iobase of 0x%03x\n",
  353. __func__, self->io.fir_base);
  354. err = -ENODEV;
  355. goto out1;
  356. }
  357. /* Initialize QoS for this device */
  358. irda_init_max_qos_capabilies(&self->qos);
  359. /* The only value we must override it the baudrate */
  360. self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
  361. IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8);
  362. self->qos.min_turn_time.bits = qos_mtt_bits;
  363. irda_qos_bits_to_value(&self->qos);
  364. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  365. self->rx_buff.truesize = 14384;
  366. self->tx_buff.truesize = 14384;
  367. /* Allocate memory if needed */
  368. self->rx_buff.head =
  369. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  370. &self->rx_buff_dma, GFP_KERNEL);
  371. if (self->rx_buff.head == NULL) {
  372. err = -ENOMEM;
  373. goto out2;
  374. }
  375. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  376. self->tx_buff.head =
  377. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  378. &self->tx_buff_dma, GFP_KERNEL);
  379. if (self->tx_buff.head == NULL) {
  380. err = -ENOMEM;
  381. goto out3;
  382. }
  383. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  384. self->rx_buff.in_frame = FALSE;
  385. self->rx_buff.state = OUTSIDE_FRAME;
  386. self->tx_buff.data = self->tx_buff.head;
  387. self->rx_buff.data = self->rx_buff.head;
  388. /* Reset Tx queue info */
  389. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  390. self->tx_fifo.tail = self->tx_buff.head;
  391. /* Override the network functions we need to use */
  392. dev->netdev_ops = &nsc_ircc_sir_ops;
  393. err = register_netdev(dev);
  394. if (err) {
  395. IRDA_ERROR("%s(), register_netdev() failed!\n", __func__);
  396. goto out4;
  397. }
  398. IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
  399. /* Check if user has supplied a valid dongle id or not */
  400. if ((dongle_id <= 0) ||
  401. (dongle_id >= ARRAY_SIZE(dongle_types))) {
  402. dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base);
  403. IRDA_MESSAGE("%s, Found dongle: %s\n", driver_name,
  404. dongle_types[dongle_id]);
  405. } else {
  406. IRDA_MESSAGE("%s, Using dongle: %s\n", driver_name,
  407. dongle_types[dongle_id]);
  408. }
  409. self->io.dongle_id = dongle_id;
  410. nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id);
  411. self->pldev = platform_device_register_simple(NSC_IRCC_DRIVER_NAME,
  412. self->index, NULL, 0);
  413. if (IS_ERR(self->pldev)) {
  414. err = PTR_ERR(self->pldev);
  415. goto out5;
  416. }
  417. platform_set_drvdata(self->pldev, self);
  418. return chip_index;
  419. out5:
  420. unregister_netdev(dev);
  421. out4:
  422. dma_free_coherent(NULL, self->tx_buff.truesize,
  423. self->tx_buff.head, self->tx_buff_dma);
  424. out3:
  425. dma_free_coherent(NULL, self->rx_buff.truesize,
  426. self->rx_buff.head, self->rx_buff_dma);
  427. out2:
  428. release_region(self->io.fir_base, self->io.fir_ext);
  429. out1:
  430. free_netdev(dev);
  431. dev_self[chip_index] = NULL;
  432. return err;
  433. }
  434. /*
  435. * Function nsc_ircc_close (self)
  436. *
  437. * Close driver instance
  438. *
  439. */
  440. static int __exit nsc_ircc_close(struct nsc_ircc_cb *self)
  441. {
  442. int iobase;
  443. IRDA_DEBUG(4, "%s()\n", __func__);
  444. IRDA_ASSERT(self != NULL, return -1;);
  445. iobase = self->io.fir_base;
  446. platform_device_unregister(self->pldev);
  447. /* Remove netdevice */
  448. unregister_netdev(self->netdev);
  449. /* Release the PORT that this driver is using */
  450. IRDA_DEBUG(4, "%s(), Releasing Region %03x\n",
  451. __func__, self->io.fir_base);
  452. release_region(self->io.fir_base, self->io.fir_ext);
  453. if (self->tx_buff.head)
  454. dma_free_coherent(NULL, self->tx_buff.truesize,
  455. self->tx_buff.head, self->tx_buff_dma);
  456. if (self->rx_buff.head)
  457. dma_free_coherent(NULL, self->rx_buff.truesize,
  458. self->rx_buff.head, self->rx_buff_dma);
  459. dev_self[self->index] = NULL;
  460. free_netdev(self->netdev);
  461. return 0;
  462. }
  463. /*
  464. * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
  465. *
  466. * Initialize the NSC '108 chip
  467. *
  468. */
  469. static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info)
  470. {
  471. int cfg_base = info->cfg_base;
  472. __u8 temp=0;
  473. outb(2, cfg_base); /* Mode Control Register (MCTL) */
  474. outb(0x00, cfg_base+1); /* Disable device */
  475. /* Base Address and Interrupt Control Register (BAIC) */
  476. outb(CFG_108_BAIC, cfg_base);
  477. switch (info->fir_base) {
  478. case 0x3e8: outb(0x14, cfg_base+1); break;
  479. case 0x2e8: outb(0x15, cfg_base+1); break;
  480. case 0x3f8: outb(0x16, cfg_base+1); break;
  481. case 0x2f8: outb(0x17, cfg_base+1); break;
  482. default: IRDA_ERROR("%s(), invalid base_address", __func__);
  483. }
  484. /* Control Signal Routing Register (CSRT) */
  485. switch (info->irq) {
  486. case 3: temp = 0x01; break;
  487. case 4: temp = 0x02; break;
  488. case 5: temp = 0x03; break;
  489. case 7: temp = 0x04; break;
  490. case 9: temp = 0x05; break;
  491. case 11: temp = 0x06; break;
  492. case 15: temp = 0x07; break;
  493. default: IRDA_ERROR("%s(), invalid irq", __func__);
  494. }
  495. outb(CFG_108_CSRT, cfg_base);
  496. switch (info->dma) {
  497. case 0: outb(0x08+temp, cfg_base+1); break;
  498. case 1: outb(0x10+temp, cfg_base+1); break;
  499. case 3: outb(0x18+temp, cfg_base+1); break;
  500. default: IRDA_ERROR("%s(), invalid dma", __func__);
  501. }
  502. outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */
  503. outb(0x03, cfg_base+1); /* Enable device */
  504. return 0;
  505. }
  506. /*
  507. * Function nsc_ircc_probe_108 (chip, info)
  508. *
  509. *
  510. *
  511. */
  512. static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info)
  513. {
  514. int cfg_base = info->cfg_base;
  515. int reg;
  516. /* Read address and interrupt control register (BAIC) */
  517. outb(CFG_108_BAIC, cfg_base);
  518. reg = inb(cfg_base+1);
  519. switch (reg & 0x03) {
  520. case 0:
  521. info->fir_base = 0x3e8;
  522. break;
  523. case 1:
  524. info->fir_base = 0x2e8;
  525. break;
  526. case 2:
  527. info->fir_base = 0x3f8;
  528. break;
  529. case 3:
  530. info->fir_base = 0x2f8;
  531. break;
  532. }
  533. info->sir_base = info->fir_base;
  534. IRDA_DEBUG(2, "%s(), probing fir_base=0x%03x\n", __func__,
  535. info->fir_base);
  536. /* Read control signals routing register (CSRT) */
  537. outb(CFG_108_CSRT, cfg_base);
  538. reg = inb(cfg_base+1);
  539. switch (reg & 0x07) {
  540. case 0:
  541. info->irq = -1;
  542. break;
  543. case 1:
  544. info->irq = 3;
  545. break;
  546. case 2:
  547. info->irq = 4;
  548. break;
  549. case 3:
  550. info->irq = 5;
  551. break;
  552. case 4:
  553. info->irq = 7;
  554. break;
  555. case 5:
  556. info->irq = 9;
  557. break;
  558. case 6:
  559. info->irq = 11;
  560. break;
  561. case 7:
  562. info->irq = 15;
  563. break;
  564. }
  565. IRDA_DEBUG(2, "%s(), probing irq=%d\n", __func__, info->irq);
  566. /* Currently we only read Rx DMA but it will also be used for Tx */
  567. switch ((reg >> 3) & 0x03) {
  568. case 0:
  569. info->dma = -1;
  570. break;
  571. case 1:
  572. info->dma = 0;
  573. break;
  574. case 2:
  575. info->dma = 1;
  576. break;
  577. case 3:
  578. info->dma = 3;
  579. break;
  580. }
  581. IRDA_DEBUG(2, "%s(), probing dma=%d\n", __func__, info->dma);
  582. /* Read mode control register (MCTL) */
  583. outb(CFG_108_MCTL, cfg_base);
  584. reg = inb(cfg_base+1);
  585. info->enabled = reg & 0x01;
  586. info->suspended = !((reg >> 1) & 0x01);
  587. return 0;
  588. }
  589. /*
  590. * Function nsc_ircc_init_338 (chip, info)
  591. *
  592. * Initialize the NSC '338 chip. Remember that the 87338 needs two
  593. * consecutive writes to the data registers while CPU interrupts are
  594. * disabled. The 97338 does not require this, but shouldn't be any
  595. * harm if we do it anyway.
  596. */
  597. static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info)
  598. {
  599. /* No init yet */
  600. return 0;
  601. }
  602. /*
  603. * Function nsc_ircc_probe_338 (chip, info)
  604. *
  605. *
  606. *
  607. */
  608. static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info)
  609. {
  610. int cfg_base = info->cfg_base;
  611. int reg, com = 0;
  612. int pnp;
  613. /* Read function enable register (FER) */
  614. outb(CFG_338_FER, cfg_base);
  615. reg = inb(cfg_base+1);
  616. info->enabled = (reg >> 2) & 0x01;
  617. /* Check if we are in Legacy or PnP mode */
  618. outb(CFG_338_PNP0, cfg_base);
  619. reg = inb(cfg_base+1);
  620. pnp = (reg >> 3) & 0x01;
  621. if (pnp) {
  622. IRDA_DEBUG(2, "(), Chip is in PnP mode\n");
  623. outb(0x46, cfg_base);
  624. reg = (inb(cfg_base+1) & 0xfe) << 2;
  625. outb(0x47, cfg_base);
  626. reg |= ((inb(cfg_base+1) & 0xfc) << 8);
  627. info->fir_base = reg;
  628. } else {
  629. /* Read function address register (FAR) */
  630. outb(CFG_338_FAR, cfg_base);
  631. reg = inb(cfg_base+1);
  632. switch ((reg >> 4) & 0x03) {
  633. case 0:
  634. info->fir_base = 0x3f8;
  635. break;
  636. case 1:
  637. info->fir_base = 0x2f8;
  638. break;
  639. case 2:
  640. com = 3;
  641. break;
  642. case 3:
  643. com = 4;
  644. break;
  645. }
  646. if (com) {
  647. switch ((reg >> 6) & 0x03) {
  648. case 0:
  649. if (com == 3)
  650. info->fir_base = 0x3e8;
  651. else
  652. info->fir_base = 0x2e8;
  653. break;
  654. case 1:
  655. if (com == 3)
  656. info->fir_base = 0x338;
  657. else
  658. info->fir_base = 0x238;
  659. break;
  660. case 2:
  661. if (com == 3)
  662. info->fir_base = 0x2e8;
  663. else
  664. info->fir_base = 0x2e0;
  665. break;
  666. case 3:
  667. if (com == 3)
  668. info->fir_base = 0x220;
  669. else
  670. info->fir_base = 0x228;
  671. break;
  672. }
  673. }
  674. }
  675. info->sir_base = info->fir_base;
  676. /* Read PnP register 1 (PNP1) */
  677. outb(CFG_338_PNP1, cfg_base);
  678. reg = inb(cfg_base+1);
  679. info->irq = reg >> 4;
  680. /* Read PnP register 3 (PNP3) */
  681. outb(CFG_338_PNP3, cfg_base);
  682. reg = inb(cfg_base+1);
  683. info->dma = (reg & 0x07) - 1;
  684. /* Read power and test register (PTR) */
  685. outb(CFG_338_PTR, cfg_base);
  686. reg = inb(cfg_base+1);
  687. info->suspended = reg & 0x01;
  688. return 0;
  689. }
  690. /*
  691. * Function nsc_ircc_init_39x (chip, info)
  692. *
  693. * Now that we know it's a '39x (see probe below), we need to
  694. * configure it so we can use it.
  695. *
  696. * The NSC '338 chip is a Super I/O chip with a "bank" architecture,
  697. * the configuration of the different functionality (serial, parallel,
  698. * floppy...) are each in a different bank (Logical Device Number).
  699. * The base address, irq and dma configuration registers are common
  700. * to all functionalities (index 0x30 to 0x7F).
  701. * There is only one configuration register specific to the
  702. * serial port, CFG_39X_SPC.
  703. * JeanII
  704. *
  705. * Note : this code was written by Jan Frey <janfrey@web.de>
  706. */
  707. static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info)
  708. {
  709. int cfg_base = info->cfg_base;
  710. int enabled;
  711. /* User is sure about his config... accept it. */
  712. IRDA_DEBUG(2, "%s(): nsc_ircc_init_39x (user settings): "
  713. "io=0x%04x, irq=%d, dma=%d\n",
  714. __func__, info->fir_base, info->irq, info->dma);
  715. /* Access bank for SP2 */
  716. outb(CFG_39X_LDN, cfg_base);
  717. outb(0x02, cfg_base+1);
  718. /* Configure SP2 */
  719. /* We want to enable the device if not enabled */
  720. outb(CFG_39X_ACT, cfg_base);
  721. enabled = inb(cfg_base+1) & 0x01;
  722. if (!enabled) {
  723. /* Enable the device */
  724. outb(CFG_39X_SIOCF1, cfg_base);
  725. outb(0x01, cfg_base+1);
  726. /* May want to update info->enabled. Jean II */
  727. }
  728. /* Enable UART bank switching (bit 7) ; Sets the chip to normal
  729. * power mode (wake up from sleep mode) (bit 1) */
  730. outb(CFG_39X_SPC, cfg_base);
  731. outb(0x82, cfg_base+1);
  732. return 0;
  733. }
  734. /*
  735. * Function nsc_ircc_probe_39x (chip, info)
  736. *
  737. * Test if we really have a '39x chip at the given address
  738. *
  739. * Note : this code was written by Jan Frey <janfrey@web.de>
  740. */
  741. static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info)
  742. {
  743. int cfg_base = info->cfg_base;
  744. int reg1, reg2, irq, irqt, dma1, dma2;
  745. int enabled, susp;
  746. IRDA_DEBUG(2, "%s(), nsc_ircc_probe_39x, base=%d\n",
  747. __func__, cfg_base);
  748. /* This function should be executed with irq off to avoid
  749. * another driver messing with the Super I/O bank - Jean II */
  750. /* Access bank for SP2 */
  751. outb(CFG_39X_LDN, cfg_base);
  752. outb(0x02, cfg_base+1);
  753. /* Read infos about SP2 ; store in info struct */
  754. outb(CFG_39X_BASEH, cfg_base);
  755. reg1 = inb(cfg_base+1);
  756. outb(CFG_39X_BASEL, cfg_base);
  757. reg2 = inb(cfg_base+1);
  758. info->fir_base = (reg1 << 8) | reg2;
  759. outb(CFG_39X_IRQNUM, cfg_base);
  760. irq = inb(cfg_base+1);
  761. outb(CFG_39X_IRQSEL, cfg_base);
  762. irqt = inb(cfg_base+1);
  763. info->irq = irq;
  764. outb(CFG_39X_DMA0, cfg_base);
  765. dma1 = inb(cfg_base+1);
  766. outb(CFG_39X_DMA1, cfg_base);
  767. dma2 = inb(cfg_base+1);
  768. info->dma = dma1 -1;
  769. outb(CFG_39X_ACT, cfg_base);
  770. info->enabled = enabled = inb(cfg_base+1) & 0x01;
  771. outb(CFG_39X_SPC, cfg_base);
  772. susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1);
  773. IRDA_DEBUG(2, "%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", __func__, reg1,reg2,irq,irqt,dma1,dma2,enabled,susp);
  774. /* Configure SP2 */
  775. /* We want to enable the device if not enabled */
  776. outb(CFG_39X_ACT, cfg_base);
  777. enabled = inb(cfg_base+1) & 0x01;
  778. if (!enabled) {
  779. /* Enable the device */
  780. outb(CFG_39X_SIOCF1, cfg_base);
  781. outb(0x01, cfg_base+1);
  782. /* May want to update info->enabled. Jean II */
  783. }
  784. /* Enable UART bank switching (bit 7) ; Sets the chip to normal
  785. * power mode (wake up from sleep mode) (bit 1) */
  786. outb(CFG_39X_SPC, cfg_base);
  787. outb(0x82, cfg_base+1);
  788. return 0;
  789. }
  790. #ifdef CONFIG_PNP
  791. /* PNP probing */
  792. static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
  793. {
  794. memset(&pnp_info, 0, sizeof(chipio_t));
  795. pnp_info.irq = -1;
  796. pnp_info.dma = -1;
  797. pnp_succeeded = 1;
  798. if (id->driver_data & NSC_FORCE_DONGLE_TYPE9)
  799. dongle_id = 0x9;
  800. /* There doesn't seem to be any way of getting the cfg_base.
  801. * On my box, cfg_base is in the PnP descriptor of the
  802. * motherboard. Oh well... Jean II */
  803. if (pnp_port_valid(dev, 0) &&
  804. !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED))
  805. pnp_info.fir_base = pnp_port_start(dev, 0);
  806. if (pnp_irq_valid(dev, 0) &&
  807. !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED))
  808. pnp_info.irq = pnp_irq(dev, 0);
  809. if (pnp_dma_valid(dev, 0) &&
  810. !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED))
  811. pnp_info.dma = pnp_dma(dev, 0);
  812. IRDA_DEBUG(0, "%s() : From PnP, found firbase 0x%03X ; irq %d ; dma %d.\n",
  813. __func__, pnp_info.fir_base, pnp_info.irq, pnp_info.dma);
  814. if((pnp_info.fir_base == 0) ||
  815. (pnp_info.irq == -1) || (pnp_info.dma == -1)) {
  816. /* Returning an error will disable the device. Yuck ! */
  817. //return -EINVAL;
  818. pnp_succeeded = 0;
  819. }
  820. return 0;
  821. }
  822. #endif
  823. /*
  824. * Function nsc_ircc_setup (info)
  825. *
  826. * Returns non-negative on success.
  827. *
  828. */
  829. static int nsc_ircc_setup(chipio_t *info)
  830. {
  831. int version;
  832. int iobase = info->fir_base;
  833. /* Read the Module ID */
  834. switch_bank(iobase, BANK3);
  835. version = inb(iobase+MID);
  836. IRDA_DEBUG(2, "%s() Driver %s Found chip version %02x\n",
  837. __func__, driver_name, version);
  838. /* Should be 0x2? */
  839. if (0x20 != (version & 0xf0)) {
  840. IRDA_ERROR("%s, Wrong chip version %02x\n",
  841. driver_name, version);
  842. return -1;
  843. }
  844. /* Switch to advanced mode */
  845. switch_bank(iobase, BANK2);
  846. outb(ECR1_EXT_SL, iobase+ECR1);
  847. switch_bank(iobase, BANK0);
  848. /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */
  849. switch_bank(iobase, BANK0);
  850. outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
  851. outb(0x03, iobase+LCR); /* 8 bit word length */
  852. outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/
  853. /* Set FIFO size to 32 */
  854. switch_bank(iobase, BANK2);
  855. outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
  856. /* IRCR2: FEND_MD is not set */
  857. switch_bank(iobase, BANK5);
  858. outb(0x02, iobase+4);
  859. /* Make sure that some defaults are OK */
  860. switch_bank(iobase, BANK6);
  861. outb(0x20, iobase+0); /* Set 32 bits FIR CRC */
  862. outb(0x0a, iobase+1); /* Set MIR pulse width */
  863. outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */
  864. outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */
  865. /* Enable receive interrupts */
  866. switch_bank(iobase, BANK0);
  867. outb(IER_RXHDL_IE, iobase+IER);
  868. return 0;
  869. }
  870. /*
  871. * Function nsc_ircc_read_dongle_id (void)
  872. *
  873. * Try to read dongle indentification. This procedure needs to be executed
  874. * once after power-on/reset. It also needs to be used whenever you suspect
  875. * that the user may have plugged/unplugged the IrDA Dongle.
  876. */
  877. static int nsc_ircc_read_dongle_id (int iobase)
  878. {
  879. int dongle_id;
  880. __u8 bank;
  881. bank = inb(iobase+BSR);
  882. /* Select Bank 7 */
  883. switch_bank(iobase, BANK7);
  884. /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */
  885. outb(0x00, iobase+7);
  886. /* ID0, 1, and 2 are pulled up/down very slowly */
  887. udelay(50);
  888. /* IRCFG1: read the ID bits */
  889. dongle_id = inb(iobase+4) & 0x0f;
  890. #ifdef BROKEN_DONGLE_ID
  891. if (dongle_id == 0x0a)
  892. dongle_id = 0x09;
  893. #endif
  894. /* Go back to bank 0 before returning */
  895. switch_bank(iobase, BANK0);
  896. outb(bank, iobase+BSR);
  897. return dongle_id;
  898. }
  899. /*
  900. * Function nsc_ircc_init_dongle_interface (iobase, dongle_id)
  901. *
  902. * This function initializes the dongle for the transceiver that is
  903. * used. This procedure needs to be executed once after
  904. * power-on/reset. It also needs to be used whenever you suspect that
  905. * the dongle is changed.
  906. */
  907. static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id)
  908. {
  909. int bank;
  910. /* Save current bank */
  911. bank = inb(iobase+BSR);
  912. /* Select Bank 7 */
  913. switch_bank(iobase, BANK7);
  914. /* IRCFG4: set according to dongle_id */
  915. switch (dongle_id) {
  916. case 0x00: /* same as */
  917. case 0x01: /* Differential serial interface */
  918. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  919. __func__, dongle_types[dongle_id]);
  920. break;
  921. case 0x02: /* same as */
  922. case 0x03: /* Reserved */
  923. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  924. __func__, dongle_types[dongle_id]);
  925. break;
  926. case 0x04: /* Sharp RY5HD01 */
  927. break;
  928. case 0x05: /* Reserved, but this is what the Thinkpad reports */
  929. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  930. __func__, dongle_types[dongle_id]);
  931. break;
  932. case 0x06: /* Single-ended serial interface */
  933. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  934. __func__, dongle_types[dongle_id]);
  935. break;
  936. case 0x07: /* Consumer-IR only */
  937. IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
  938. __func__, dongle_types[dongle_id]);
  939. break;
  940. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  941. IRDA_DEBUG(0, "%s(), %s\n",
  942. __func__, dongle_types[dongle_id]);
  943. break;
  944. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  945. outb(0x28, iobase+7); /* Set irsl[0-2] as output */
  946. break;
  947. case 0x0A: /* same as */
  948. case 0x0B: /* Reserved */
  949. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  950. __func__, dongle_types[dongle_id]);
  951. break;
  952. case 0x0C: /* same as */
  953. case 0x0D: /* HP HSDL-1100/HSDL-2100 */
  954. /*
  955. * Set irsl0 as input, irsl[1-2] as output, and separate
  956. * inputs are used for SIR and MIR/FIR
  957. */
  958. outb(0x48, iobase+7);
  959. break;
  960. case 0x0E: /* Supports SIR Mode only */
  961. outb(0x28, iobase+7); /* Set irsl[0-2] as output */
  962. break;
  963. case 0x0F: /* No dongle connected */
  964. IRDA_DEBUG(0, "%s(), %s\n",
  965. __func__, dongle_types[dongle_id]);
  966. switch_bank(iobase, BANK0);
  967. outb(0x62, iobase+MCR);
  968. break;
  969. default:
  970. IRDA_DEBUG(0, "%s(), invalid dongle_id %#x",
  971. __func__, dongle_id);
  972. }
  973. /* IRCFG1: IRSL1 and 2 are set to IrDA mode */
  974. outb(0x00, iobase+4);
  975. /* Restore bank register */
  976. outb(bank, iobase+BSR);
  977. } /* set_up_dongle_interface */
  978. /*
  979. * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id)
  980. *
  981. * Change speed of the attach dongle
  982. *
  983. */
  984. static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id)
  985. {
  986. __u8 bank;
  987. /* Save current bank */
  988. bank = inb(iobase+BSR);
  989. /* Select Bank 7 */
  990. switch_bank(iobase, BANK7);
  991. /* IRCFG1: set according to dongle_id */
  992. switch (dongle_id) {
  993. case 0x00: /* same as */
  994. case 0x01: /* Differential serial interface */
  995. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  996. __func__, dongle_types[dongle_id]);
  997. break;
  998. case 0x02: /* same as */
  999. case 0x03: /* Reserved */
  1000. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  1001. __func__, dongle_types[dongle_id]);
  1002. break;
  1003. case 0x04: /* Sharp RY5HD01 */
  1004. break;
  1005. case 0x05: /* Reserved */
  1006. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  1007. __func__, dongle_types[dongle_id]);
  1008. break;
  1009. case 0x06: /* Single-ended serial interface */
  1010. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  1011. __func__, dongle_types[dongle_id]);
  1012. break;
  1013. case 0x07: /* Consumer-IR only */
  1014. IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
  1015. __func__, dongle_types[dongle_id]);
  1016. break;
  1017. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  1018. IRDA_DEBUG(0, "%s(), %s\n",
  1019. __func__, dongle_types[dongle_id]);
  1020. outb(0x00, iobase+4);
  1021. if (speed > 115200)
  1022. outb(0x01, iobase+4);
  1023. break;
  1024. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  1025. outb(0x01, iobase+4);
  1026. if (speed == 4000000) {
  1027. /* There was a cli() there, but we now are already
  1028. * under spin_lock_irqsave() - JeanII */
  1029. outb(0x81, iobase+4);
  1030. outb(0x80, iobase+4);
  1031. } else
  1032. outb(0x00, iobase+4);
  1033. break;
  1034. case 0x0A: /* same as */
  1035. case 0x0B: /* Reserved */
  1036. IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
  1037. __func__, dongle_types[dongle_id]);
  1038. break;
  1039. case 0x0C: /* same as */
  1040. case 0x0D: /* HP HSDL-1100/HSDL-2100 */
  1041. break;
  1042. case 0x0E: /* Supports SIR Mode only */
  1043. break;
  1044. case 0x0F: /* No dongle connected */
  1045. IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
  1046. __func__, dongle_types[dongle_id]);
  1047. switch_bank(iobase, BANK0);
  1048. outb(0x62, iobase+MCR);
  1049. break;
  1050. default:
  1051. IRDA_DEBUG(0, "%s(), invalid data_rate\n", __func__);
  1052. }
  1053. /* Restore bank register */
  1054. outb(bank, iobase+BSR);
  1055. }
  1056. /*
  1057. * Function nsc_ircc_change_speed (self, baud)
  1058. *
  1059. * Change the speed of the device
  1060. *
  1061. * This function *must* be called with irq off and spin-lock.
  1062. */
  1063. static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed)
  1064. {
  1065. struct net_device *dev = self->netdev;
  1066. __u8 mcr = MCR_SIR;
  1067. int iobase;
  1068. __u8 bank;
  1069. __u8 ier; /* Interrupt enable register */
  1070. IRDA_DEBUG(2, "%s(), speed=%d\n", __func__, speed);
  1071. IRDA_ASSERT(self != NULL, return 0;);
  1072. iobase = self->io.fir_base;
  1073. /* Update accounting for new speed */
  1074. self->io.speed = speed;
  1075. /* Save current bank */
  1076. bank = inb(iobase+BSR);
  1077. /* Disable interrupts */
  1078. switch_bank(iobase, BANK0);
  1079. outb(0, iobase+IER);
  1080. /* Select Bank 2 */
  1081. switch_bank(iobase, BANK2);
  1082. outb(0x00, iobase+BGDH);
  1083. switch (speed) {
  1084. case 9600: outb(0x0c, iobase+BGDL); break;
  1085. case 19200: outb(0x06, iobase+BGDL); break;
  1086. case 38400: outb(0x03, iobase+BGDL); break;
  1087. case 57600: outb(0x02, iobase+BGDL); break;
  1088. case 115200: outb(0x01, iobase+BGDL); break;
  1089. case 576000:
  1090. switch_bank(iobase, BANK5);
  1091. /* IRCR2: MDRS is set */
  1092. outb(inb(iobase+4) | 0x04, iobase+4);
  1093. mcr = MCR_MIR;
  1094. IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
  1095. break;
  1096. case 1152000:
  1097. mcr = MCR_MIR;
  1098. IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __func__);
  1099. break;
  1100. case 4000000:
  1101. mcr = MCR_FIR;
  1102. IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __func__);
  1103. break;
  1104. default:
  1105. mcr = MCR_FIR;
  1106. IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n",
  1107. __func__, speed);
  1108. break;
  1109. }
  1110. /* Set appropriate speed mode */
  1111. switch_bank(iobase, BANK0);
  1112. outb(mcr | MCR_TX_DFR, iobase+MCR);
  1113. /* Give some hits to the transceiver */
  1114. nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  1115. /* Set FIFO threshold to TX17, RX16 */
  1116. switch_bank(iobase, BANK0);
  1117. outb(0x00, iobase+FCR);
  1118. outb(FCR_FIFO_EN, iobase+FCR);
  1119. outb(FCR_RXTH| /* Set Rx FIFO threshold */
  1120. FCR_TXTH| /* Set Tx FIFO threshold */
  1121. FCR_TXSR| /* Reset Tx FIFO */
  1122. FCR_RXSR| /* Reset Rx FIFO */
  1123. FCR_FIFO_EN, /* Enable FIFOs */
  1124. iobase+FCR);
  1125. /* Set FIFO size to 32 */
  1126. switch_bank(iobase, BANK2);
  1127. outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
  1128. /* Enable some interrupts so we can receive frames */
  1129. switch_bank(iobase, BANK0);
  1130. if (speed > 115200) {
  1131. /* Install FIR xmit handler */
  1132. dev->netdev_ops = &nsc_ircc_fir_ops;
  1133. ier = IER_SFIF_IE;
  1134. nsc_ircc_dma_receive(self);
  1135. } else {
  1136. /* Install SIR xmit handler */
  1137. dev->netdev_ops = &nsc_ircc_sir_ops;
  1138. ier = IER_RXHDL_IE;
  1139. }
  1140. /* Set our current interrupt mask */
  1141. outb(ier, iobase+IER);
  1142. /* Restore BSR */
  1143. outb(bank, iobase+BSR);
  1144. /* Make sure interrupt handlers keep the proper interrupt mask */
  1145. return ier;
  1146. }
  1147. /*
  1148. * Function nsc_ircc_hard_xmit (skb, dev)
  1149. *
  1150. * Transmit the frame!
  1151. *
  1152. */
  1153. static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb,
  1154. struct net_device *dev)
  1155. {
  1156. struct nsc_ircc_cb *self;
  1157. unsigned long flags;
  1158. int iobase;
  1159. __s32 speed;
  1160. __u8 bank;
  1161. self = netdev_priv(dev);
  1162. IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
  1163. iobase = self->io.fir_base;
  1164. netif_stop_queue(dev);
  1165. /* Make sure tests *& speed change are atomic */
  1166. spin_lock_irqsave(&self->lock, flags);
  1167. /* Check if we need to change the speed */
  1168. speed = irda_get_next_speed(skb);
  1169. if ((speed != self->io.speed) && (speed != -1)) {
  1170. /* Check for empty frame. */
  1171. if (!skb->len) {
  1172. /* If we just sent a frame, we get called before
  1173. * the last bytes get out (because of the SIR FIFO).
  1174. * If this is the case, let interrupt handler change
  1175. * the speed itself... Jean II */
  1176. if (self->io.direction == IO_RECV) {
  1177. nsc_ircc_change_speed(self, speed);
  1178. /* TODO : For SIR->SIR, the next packet
  1179. * may get corrupted - Jean II */
  1180. netif_wake_queue(dev);
  1181. } else {
  1182. self->new_speed = speed;
  1183. /* Queue will be restarted after speed change
  1184. * to make sure packets gets through the
  1185. * proper xmit handler - Jean II */
  1186. }
  1187. dev->trans_start = jiffies;
  1188. spin_unlock_irqrestore(&self->lock, flags);
  1189. dev_kfree_skb(skb);
  1190. return NETDEV_TX_OK;
  1191. } else
  1192. self->new_speed = speed;
  1193. }
  1194. /* Save current bank */
  1195. bank = inb(iobase+BSR);
  1196. self->tx_buff.data = self->tx_buff.head;
  1197. self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
  1198. self->tx_buff.truesize);
  1199. dev->stats.tx_bytes += self->tx_buff.len;
  1200. /* Add interrupt on tx low level (will fire immediately) */
  1201. switch_bank(iobase, BANK0);
  1202. outb(IER_TXLDL_IE, iobase+IER);
  1203. /* Restore bank register */
  1204. outb(bank, iobase+BSR);
  1205. dev->trans_start = jiffies;
  1206. spin_unlock_irqrestore(&self->lock, flags);
  1207. dev_kfree_skb(skb);
  1208. return NETDEV_TX_OK;
  1209. }
  1210. static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb,
  1211. struct net_device *dev)
  1212. {
  1213. struct nsc_ircc_cb *self;
  1214. unsigned long flags;
  1215. int iobase;
  1216. __s32 speed;
  1217. __u8 bank;
  1218. int mtt, diff;
  1219. self = netdev_priv(dev);
  1220. iobase = self->io.fir_base;
  1221. netif_stop_queue(dev);
  1222. /* Make sure tests *& speed change are atomic */
  1223. spin_lock_irqsave(&self->lock, flags);
  1224. /* Check if we need to change the speed */
  1225. speed = irda_get_next_speed(skb);
  1226. if ((speed != self->io.speed) && (speed != -1)) {
  1227. /* Check for empty frame. */
  1228. if (!skb->len) {
  1229. /* If we are currently transmitting, defer to
  1230. * interrupt handler. - Jean II */
  1231. if(self->tx_fifo.len == 0) {
  1232. nsc_ircc_change_speed(self, speed);
  1233. netif_wake_queue(dev);
  1234. } else {
  1235. self->new_speed = speed;
  1236. /* Keep queue stopped :
  1237. * the speed change operation may change the
  1238. * xmit handler, and we want to make sure
  1239. * the next packet get through the proper
  1240. * Tx path, so block the Tx queue until
  1241. * the speed change has been done.
  1242. * Jean II */
  1243. }
  1244. dev->trans_start = jiffies;
  1245. spin_unlock_irqrestore(&self->lock, flags);
  1246. dev_kfree_skb(skb);
  1247. return NETDEV_TX_OK;
  1248. } else {
  1249. /* Change speed after current frame */
  1250. self->new_speed = speed;
  1251. }
  1252. }
  1253. /* Save current bank */
  1254. bank = inb(iobase+BSR);
  1255. /* Register and copy this frame to DMA memory */
  1256. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  1257. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  1258. self->tx_fifo.tail += skb->len;
  1259. dev->stats.tx_bytes += skb->len;
  1260. skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start,
  1261. skb->len);
  1262. self->tx_fifo.len++;
  1263. self->tx_fifo.free++;
  1264. /* Start transmit only if there is currently no transmit going on */
  1265. if (self->tx_fifo.len == 1) {
  1266. /* Check if we must wait the min turn time or not */
  1267. mtt = irda_get_mtt(skb);
  1268. if (mtt) {
  1269. /* Check how much time we have used already */
  1270. do_gettimeofday(&self->now);
  1271. diff = self->now.tv_usec - self->stamp.tv_usec;
  1272. if (diff < 0)
  1273. diff += 1000000;
  1274. /* Check if the mtt is larger than the time we have
  1275. * already used by all the protocol processing
  1276. */
  1277. if (mtt > diff) {
  1278. mtt -= diff;
  1279. /*
  1280. * Use timer if delay larger than 125 us, and
  1281. * use udelay for smaller values which should
  1282. * be acceptable
  1283. */
  1284. if (mtt > 125) {
  1285. /* Adjust for timer resolution */
  1286. mtt = mtt / 125;
  1287. /* Setup timer */
  1288. switch_bank(iobase, BANK4);
  1289. outb(mtt & 0xff, iobase+TMRL);
  1290. outb((mtt >> 8) & 0x0f, iobase+TMRH);
  1291. /* Start timer */
  1292. outb(IRCR1_TMR_EN, iobase+IRCR1);
  1293. self->io.direction = IO_XMIT;
  1294. /* Enable timer interrupt */
  1295. switch_bank(iobase, BANK0);
  1296. outb(IER_TMR_IE, iobase+IER);
  1297. /* Timer will take care of the rest */
  1298. goto out;
  1299. } else
  1300. udelay(mtt);
  1301. }
  1302. }
  1303. /* Enable DMA interrupt */
  1304. switch_bank(iobase, BANK0);
  1305. outb(IER_DMA_IE, iobase+IER);
  1306. /* Transmit frame */
  1307. nsc_ircc_dma_xmit(self, iobase);
  1308. }
  1309. out:
  1310. /* Not busy transmitting anymore if window is not full,
  1311. * and if we don't need to change speed */
  1312. if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0))
  1313. netif_wake_queue(self->netdev);
  1314. /* Restore bank register */
  1315. outb(bank, iobase+BSR);
  1316. dev->trans_start = jiffies;
  1317. spin_unlock_irqrestore(&self->lock, flags);
  1318. dev_kfree_skb(skb);
  1319. return NETDEV_TX_OK;
  1320. }
  1321. /*
  1322. * Function nsc_ircc_dma_xmit (self, iobase)
  1323. *
  1324. * Transmit data using DMA
  1325. *
  1326. */
  1327. static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase)
  1328. {
  1329. int bsr;
  1330. /* Save current bank */
  1331. bsr = inb(iobase+BSR);
  1332. /* Disable DMA */
  1333. switch_bank(iobase, BANK0);
  1334. outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
  1335. self->io.direction = IO_XMIT;
  1336. /* Choose transmit DMA channel */
  1337. switch_bank(iobase, BANK2);
  1338. outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
  1339. irda_setup_dma(self->io.dma,
  1340. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  1341. self->tx_buff.head) + self->tx_buff_dma,
  1342. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  1343. DMA_TX_MODE);
  1344. /* Enable DMA and SIR interaction pulse */
  1345. switch_bank(iobase, BANK0);
  1346. outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR);
  1347. /* Restore bank register */
  1348. outb(bsr, iobase+BSR);
  1349. }
  1350. /*
  1351. * Function nsc_ircc_pio_xmit (self, iobase)
  1352. *
  1353. * Transmit data using PIO. Returns the number of bytes that actually
  1354. * got transferred
  1355. *
  1356. */
  1357. static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
  1358. {
  1359. int actual = 0;
  1360. __u8 bank;
  1361. IRDA_DEBUG(4, "%s()\n", __func__);
  1362. /* Save current bank */
  1363. bank = inb(iobase+BSR);
  1364. switch_bank(iobase, BANK0);
  1365. if (!(inb_p(iobase+LSR) & LSR_TXEMP)) {
  1366. IRDA_DEBUG(4, "%s(), warning, FIFO not empty yet!\n",
  1367. __func__);
  1368. /* FIFO may still be filled to the Tx interrupt threshold */
  1369. fifo_size -= 17;
  1370. }
  1371. /* Fill FIFO with current frame */
  1372. while ((fifo_size-- > 0) && (actual < len)) {
  1373. /* Transmit next byte */
  1374. outb(buf[actual++], iobase+TXD);
  1375. }
  1376. IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
  1377. __func__, fifo_size, actual, len);
  1378. /* Restore bank */
  1379. outb(bank, iobase+BSR);
  1380. return actual;
  1381. }
  1382. /*
  1383. * Function nsc_ircc_dma_xmit_complete (self)
  1384. *
  1385. * The transfer of a frame in finished. This function will only be called
  1386. * by the interrupt handler
  1387. *
  1388. */
  1389. static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self)
  1390. {
  1391. int iobase;
  1392. __u8 bank;
  1393. int ret = TRUE;
  1394. IRDA_DEBUG(2, "%s()\n", __func__);
  1395. iobase = self->io.fir_base;
  1396. /* Save current bank */
  1397. bank = inb(iobase+BSR);
  1398. /* Disable DMA */
  1399. switch_bank(iobase, BANK0);
  1400. outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
  1401. /* Check for underrrun! */
  1402. if (inb(iobase+ASCR) & ASCR_TXUR) {
  1403. self->netdev->stats.tx_errors++;
  1404. self->netdev->stats.tx_fifo_errors++;
  1405. /* Clear bit, by writing 1 into it */
  1406. outb(ASCR_TXUR, iobase+ASCR);
  1407. } else {
  1408. self->netdev->stats.tx_packets++;
  1409. }
  1410. /* Finished with this frame, so prepare for next */
  1411. self->tx_fifo.ptr++;
  1412. self->tx_fifo.len--;
  1413. /* Any frames to be sent back-to-back? */
  1414. if (self->tx_fifo.len) {
  1415. nsc_ircc_dma_xmit(self, iobase);
  1416. /* Not finished yet! */
  1417. ret = FALSE;
  1418. } else {
  1419. /* Reset Tx FIFO info */
  1420. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  1421. self->tx_fifo.tail = self->tx_buff.head;
  1422. }
  1423. /* Make sure we have room for more frames and
  1424. * that we don't need to change speed */
  1425. if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) {
  1426. /* Not busy transmitting anymore */
  1427. /* Tell the network layer, that we can accept more frames */
  1428. netif_wake_queue(self->netdev);
  1429. }
  1430. /* Restore bank */
  1431. outb(bank, iobase+BSR);
  1432. return ret;
  1433. }
  1434. /*
  1435. * Function nsc_ircc_dma_receive (self)
  1436. *
  1437. * Get ready for receiving a frame. The device will initiate a DMA
  1438. * if it starts to receive a frame.
  1439. *
  1440. */
  1441. static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self)
  1442. {
  1443. int iobase;
  1444. __u8 bsr;
  1445. iobase = self->io.fir_base;
  1446. /* Reset Tx FIFO info */
  1447. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  1448. self->tx_fifo.tail = self->tx_buff.head;
  1449. /* Save current bank */
  1450. bsr = inb(iobase+BSR);
  1451. /* Disable DMA */
  1452. switch_bank(iobase, BANK0);
  1453. outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
  1454. /* Choose DMA Rx, DMA Fairness, and Advanced mode */
  1455. switch_bank(iobase, BANK2);
  1456. outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
  1457. self->io.direction = IO_RECV;
  1458. self->rx_buff.data = self->rx_buff.head;
  1459. /* Reset Rx FIFO. This will also flush the ST_FIFO */
  1460. switch_bank(iobase, BANK0);
  1461. outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
  1462. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  1463. self->st_fifo.tail = self->st_fifo.head = 0;
  1464. irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
  1465. DMA_RX_MODE);
  1466. /* Enable DMA */
  1467. switch_bank(iobase, BANK0);
  1468. outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR);
  1469. /* Restore bank register */
  1470. outb(bsr, iobase+BSR);
  1471. return 0;
  1472. }
  1473. /*
  1474. * Function nsc_ircc_dma_receive_complete (self)
  1475. *
  1476. * Finished with receiving frames
  1477. *
  1478. *
  1479. */
  1480. static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase)
  1481. {
  1482. struct st_fifo *st_fifo;
  1483. struct sk_buff *skb;
  1484. __u8 status;
  1485. __u8 bank;
  1486. int len;
  1487. st_fifo = &self->st_fifo;
  1488. /* Save current bank */
  1489. bank = inb(iobase+BSR);
  1490. /* Read all entries in status FIFO */
  1491. switch_bank(iobase, BANK5);
  1492. while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) {
  1493. /* We must empty the status FIFO no matter what */
  1494. len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8);
  1495. if (st_fifo->tail >= MAX_RX_WINDOW) {
  1496. IRDA_DEBUG(0, "%s(), window is full!\n", __func__);
  1497. continue;
  1498. }
  1499. st_fifo->entries[st_fifo->tail].status = status;
  1500. st_fifo->entries[st_fifo->tail].len = len;
  1501. st_fifo->pending_bytes += len;
  1502. st_fifo->tail++;
  1503. st_fifo->len++;
  1504. }
  1505. /* Try to process all entries in status FIFO */
  1506. while (st_fifo->len > 0) {
  1507. /* Get first entry */
  1508. status = st_fifo->entries[st_fifo->head].status;
  1509. len = st_fifo->entries[st_fifo->head].len;
  1510. st_fifo->pending_bytes -= len;
  1511. st_fifo->head++;
  1512. st_fifo->len--;
  1513. /* Check for errors */
  1514. if (status & FRM_ST_ERR_MSK) {
  1515. if (status & FRM_ST_LOST_FR) {
  1516. /* Add number of lost frames to stats */
  1517. self->netdev->stats.rx_errors += len;
  1518. } else {
  1519. /* Skip frame */
  1520. self->netdev->stats.rx_errors++;
  1521. self->rx_buff.data += len;
  1522. if (status & FRM_ST_MAX_LEN)
  1523. self->netdev->stats.rx_length_errors++;
  1524. if (status & FRM_ST_PHY_ERR)
  1525. self->netdev->stats.rx_frame_errors++;
  1526. if (status & FRM_ST_BAD_CRC)
  1527. self->netdev->stats.rx_crc_errors++;
  1528. }
  1529. /* The errors below can be reported in both cases */
  1530. if (status & FRM_ST_OVR1)
  1531. self->netdev->stats.rx_fifo_errors++;
  1532. if (status & FRM_ST_OVR2)
  1533. self->netdev->stats.rx_fifo_errors++;
  1534. } else {
  1535. /*
  1536. * First we must make sure that the frame we
  1537. * want to deliver is all in main memory. If we
  1538. * cannot tell, then we check if the Rx FIFO is
  1539. * empty. If not then we will have to take a nap
  1540. * and try again later.
  1541. */
  1542. if (st_fifo->pending_bytes < self->io.fifo_size) {
  1543. switch_bank(iobase, BANK0);
  1544. if (inb(iobase+LSR) & LSR_RXDA) {
  1545. /* Put this entry back in fifo */
  1546. st_fifo->head--;
  1547. st_fifo->len++;
  1548. st_fifo->pending_bytes += len;
  1549. st_fifo->entries[st_fifo->head].status = status;
  1550. st_fifo->entries[st_fifo->head].len = len;
  1551. /*
  1552. * DMA not finished yet, so try again
  1553. * later, set timer value, resolution
  1554. * 125 us
  1555. */
  1556. switch_bank(iobase, BANK4);
  1557. outb(0x02, iobase+TMRL); /* x 125 us */
  1558. outb(0x00, iobase+TMRH);
  1559. /* Start timer */
  1560. outb(IRCR1_TMR_EN, iobase+IRCR1);
  1561. /* Restore bank register */
  1562. outb(bank, iobase+BSR);
  1563. return FALSE; /* I'll be back! */
  1564. }
  1565. }
  1566. /*
  1567. * Remember the time we received this frame, so we can
  1568. * reduce the min turn time a bit since we will know
  1569. * how much time we have used for protocol processing
  1570. */
  1571. do_gettimeofday(&self->stamp);
  1572. skb = dev_alloc_skb(len+1);
  1573. if (skb == NULL) {
  1574. IRDA_WARNING("%s(), memory squeeze, "
  1575. "dropping frame.\n",
  1576. __func__);
  1577. self->netdev->stats.rx_dropped++;
  1578. /* Restore bank register */
  1579. outb(bank, iobase+BSR);
  1580. return FALSE;
  1581. }
  1582. /* Make sure IP header gets aligned */
  1583. skb_reserve(skb, 1);
  1584. /* Copy frame without CRC */
  1585. if (self->io.speed < 4000000) {
  1586. skb_put(skb, len-2);
  1587. skb_copy_to_linear_data(skb,
  1588. self->rx_buff.data,
  1589. len - 2);
  1590. } else {
  1591. skb_put(skb, len-4);
  1592. skb_copy_to_linear_data(skb,
  1593. self->rx_buff.data,
  1594. len - 4);
  1595. }
  1596. /* Move to next frame */
  1597. self->rx_buff.data += len;
  1598. self->netdev->stats.rx_bytes += len;
  1599. self->netdev->stats.rx_packets++;
  1600. skb->dev = self->netdev;
  1601. skb_reset_mac_header(skb);
  1602. skb->protocol = htons(ETH_P_IRDA);
  1603. netif_rx(skb);
  1604. }
  1605. }
  1606. /* Restore bank register */
  1607. outb(bank, iobase+BSR);
  1608. return TRUE;
  1609. }
  1610. /*
  1611. * Function nsc_ircc_pio_receive (self)
  1612. *
  1613. * Receive all data in receiver FIFO
  1614. *
  1615. */
  1616. static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self)
  1617. {
  1618. __u8 byte;
  1619. int iobase;
  1620. iobase = self->io.fir_base;
  1621. /* Receive all characters in Rx FIFO */
  1622. do {
  1623. byte = inb(iobase+RXD);
  1624. async_unwrap_char(self->netdev, &self->netdev->stats,
  1625. &self->rx_buff, byte);
  1626. } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */
  1627. }
  1628. /*
  1629. * Function nsc_ircc_sir_interrupt (self, eir)
  1630. *
  1631. * Handle SIR interrupt
  1632. *
  1633. */
  1634. static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir)
  1635. {
  1636. int actual;
  1637. /* Check if transmit FIFO is low on data */
  1638. if (eir & EIR_TXLDL_EV) {
  1639. /* Write data left in transmit buffer */
  1640. actual = nsc_ircc_pio_write(self->io.fir_base,
  1641. self->tx_buff.data,
  1642. self->tx_buff.len,
  1643. self->io.fifo_size);
  1644. self->tx_buff.data += actual;
  1645. self->tx_buff.len -= actual;
  1646. self->io.direction = IO_XMIT;
  1647. /* Check if finished */
  1648. if (self->tx_buff.len > 0)
  1649. self->ier = IER_TXLDL_IE;
  1650. else {
  1651. self->netdev->stats.tx_packets++;
  1652. netif_wake_queue(self->netdev);
  1653. self->ier = IER_TXEMP_IE;
  1654. }
  1655. }
  1656. /* Check if transmission has completed */
  1657. if (eir & EIR_TXEMP_EV) {
  1658. /* Turn around and get ready to receive some data */
  1659. self->io.direction = IO_RECV;
  1660. self->ier = IER_RXHDL_IE;
  1661. /* Check if we need to change the speed?
  1662. * Need to be after self->io.direction to avoid race with
  1663. * nsc_ircc_hard_xmit_sir() - Jean II */
  1664. if (self->new_speed) {
  1665. IRDA_DEBUG(2, "%s(), Changing speed!\n", __func__);
  1666. self->ier = nsc_ircc_change_speed(self,
  1667. self->new_speed);
  1668. self->new_speed = 0;
  1669. netif_wake_queue(self->netdev);
  1670. /* Check if we are going to FIR */
  1671. if (self->io.speed > 115200) {
  1672. /* No need to do anymore SIR stuff */
  1673. return;
  1674. }
  1675. }
  1676. }
  1677. /* Rx FIFO threshold or timeout */
  1678. if (eir & EIR_RXHDL_EV) {
  1679. nsc_ircc_pio_receive(self);
  1680. /* Keep receiving */
  1681. self->ier = IER_RXHDL_IE;
  1682. }
  1683. }
  1684. /*
  1685. * Function nsc_ircc_fir_interrupt (self, eir)
  1686. *
  1687. * Handle MIR/FIR interrupt
  1688. *
  1689. */
  1690. static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase,
  1691. int eir)
  1692. {
  1693. __u8 bank;
  1694. bank = inb(iobase+BSR);
  1695. /* Status FIFO event*/
  1696. if (eir & EIR_SFIF_EV) {
  1697. /* Check if DMA has finished */
  1698. if (nsc_ircc_dma_receive_complete(self, iobase)) {
  1699. /* Wait for next status FIFO interrupt */
  1700. self->ier = IER_SFIF_IE;
  1701. } else {
  1702. self->ier = IER_SFIF_IE | IER_TMR_IE;
  1703. }
  1704. } else if (eir & EIR_TMR_EV) { /* Timer finished */
  1705. /* Disable timer */
  1706. switch_bank(iobase, BANK4);
  1707. outb(0, iobase+IRCR1);
  1708. /* Clear timer event */
  1709. switch_bank(iobase, BANK0);
  1710. outb(ASCR_CTE, iobase+ASCR);
  1711. /* Check if this is a Tx timer interrupt */
  1712. if (self->io.direction == IO_XMIT) {
  1713. nsc_ircc_dma_xmit(self, iobase);
  1714. /* Interrupt on DMA */
  1715. self->ier = IER_DMA_IE;
  1716. } else {
  1717. /* Check (again) if DMA has finished */
  1718. if (nsc_ircc_dma_receive_complete(self, iobase)) {
  1719. self->ier = IER_SFIF_IE;
  1720. } else {
  1721. self->ier = IER_SFIF_IE | IER_TMR_IE;
  1722. }
  1723. }
  1724. } else if (eir & EIR_DMA_EV) {
  1725. /* Finished with all transmissions? */
  1726. if (nsc_ircc_dma_xmit_complete(self)) {
  1727. if(self->new_speed != 0) {
  1728. /* As we stop the Tx queue, the speed change
  1729. * need to be done when the Tx fifo is
  1730. * empty. Ask for a Tx done interrupt */
  1731. self->ier = IER_TXEMP_IE;
  1732. } else {
  1733. /* Check if there are more frames to be
  1734. * transmitted */
  1735. if (irda_device_txqueue_empty(self->netdev)) {
  1736. /* Prepare for receive */
  1737. nsc_ircc_dma_receive(self);
  1738. self->ier = IER_SFIF_IE;
  1739. } else
  1740. IRDA_WARNING("%s(), potential "
  1741. "Tx queue lockup !\n",
  1742. __func__);
  1743. }
  1744. } else {
  1745. /* Not finished yet, so interrupt on DMA again */
  1746. self->ier = IER_DMA_IE;
  1747. }
  1748. } else if (eir & EIR_TXEMP_EV) {
  1749. /* The Tx FIFO has totally drained out, so now we can change
  1750. * the speed... - Jean II */
  1751. self->ier = nsc_ircc_change_speed(self, self->new_speed);
  1752. self->new_speed = 0;
  1753. netif_wake_queue(self->netdev);
  1754. /* Note : nsc_ircc_change_speed() restarted Rx fifo */
  1755. }
  1756. outb(bank, iobase+BSR);
  1757. }
  1758. /*
  1759. * Function nsc_ircc_interrupt (irq, dev_id, regs)
  1760. *
  1761. * An interrupt from the chip has arrived. Time to do some work
  1762. *
  1763. */
  1764. static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id)
  1765. {
  1766. struct net_device *dev = dev_id;
  1767. struct nsc_ircc_cb *self;
  1768. __u8 bsr, eir;
  1769. int iobase;
  1770. self = netdev_priv(dev);
  1771. spin_lock(&self->lock);
  1772. iobase = self->io.fir_base;
  1773. bsr = inb(iobase+BSR); /* Save current bank */
  1774. switch_bank(iobase, BANK0);
  1775. self->ier = inb(iobase+IER);
  1776. eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */
  1777. outb(0, iobase+IER); /* Disable interrupts */
  1778. if (eir) {
  1779. /* Dispatch interrupt handler for the current speed */
  1780. if (self->io.speed > 115200)
  1781. nsc_ircc_fir_interrupt(self, iobase, eir);
  1782. else
  1783. nsc_ircc_sir_interrupt(self, eir);
  1784. }
  1785. outb(self->ier, iobase+IER); /* Restore interrupts */
  1786. outb(bsr, iobase+BSR); /* Restore bank register */
  1787. spin_unlock(&self->lock);
  1788. return IRQ_RETVAL(eir);
  1789. }
  1790. /*
  1791. * Function nsc_ircc_is_receiving (self)
  1792. *
  1793. * Return TRUE is we are currently receiving a frame
  1794. *
  1795. */
  1796. static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self)
  1797. {
  1798. unsigned long flags;
  1799. int status = FALSE;
  1800. int iobase;
  1801. __u8 bank;
  1802. IRDA_ASSERT(self != NULL, return FALSE;);
  1803. spin_lock_irqsave(&self->lock, flags);
  1804. if (self->io.speed > 115200) {
  1805. iobase = self->io.fir_base;
  1806. /* Check if rx FIFO is not empty */
  1807. bank = inb(iobase+BSR);
  1808. switch_bank(iobase, BANK2);
  1809. if ((inb(iobase+RXFLV) & 0x3f) != 0) {
  1810. /* We are receiving something */
  1811. status = TRUE;
  1812. }
  1813. outb(bank, iobase+BSR);
  1814. } else
  1815. status = (self->rx_buff.state != OUTSIDE_FRAME);
  1816. spin_unlock_irqrestore(&self->lock, flags);
  1817. return status;
  1818. }
  1819. /*
  1820. * Function nsc_ircc_net_open (dev)
  1821. *
  1822. * Start the device
  1823. *
  1824. */
  1825. static int nsc_ircc_net_open(struct net_device *dev)
  1826. {
  1827. struct nsc_ircc_cb *self;
  1828. int iobase;
  1829. char hwname[32];
  1830. __u8 bank;
  1831. IRDA_DEBUG(4, "%s()\n", __func__);
  1832. IRDA_ASSERT(dev != NULL, return -1;);
  1833. self = netdev_priv(dev);
  1834. IRDA_ASSERT(self != NULL, return 0;);
  1835. iobase = self->io.fir_base;
  1836. if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) {
  1837. IRDA_WARNING("%s, unable to allocate irq=%d\n",
  1838. driver_name, self->io.irq);
  1839. return -EAGAIN;
  1840. }
  1841. /*
  1842. * Always allocate the DMA channel after the IRQ, and clean up on
  1843. * failure.
  1844. */
  1845. if (request_dma(self->io.dma, dev->name)) {
  1846. IRDA_WARNING("%s, unable to allocate dma=%d\n",
  1847. driver_name, self->io.dma);
  1848. free_irq(self->io.irq, dev);
  1849. return -EAGAIN;
  1850. }
  1851. /* Save current bank */
  1852. bank = inb(iobase+BSR);
  1853. /* turn on interrupts */
  1854. switch_bank(iobase, BANK0);
  1855. outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER);
  1856. /* Restore bank register */
  1857. outb(bank, iobase+BSR);
  1858. /* Ready to play! */
  1859. netif_start_queue(dev);
  1860. /* Give self a hardware name */
  1861. sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base);
  1862. /*
  1863. * Open new IrLAP layer instance, now that everything should be
  1864. * initialized properly
  1865. */
  1866. self->irlap = irlap_open(dev, &self->qos, hwname);
  1867. return 0;
  1868. }
  1869. /*
  1870. * Function nsc_ircc_net_close (dev)
  1871. *
  1872. * Stop the device
  1873. *
  1874. */
  1875. static int nsc_ircc_net_close(struct net_device *dev)
  1876. {
  1877. struct nsc_ircc_cb *self;
  1878. int iobase;
  1879. __u8 bank;
  1880. IRDA_DEBUG(4, "%s()\n", __func__);
  1881. IRDA_ASSERT(dev != NULL, return -1;);
  1882. self = netdev_priv(dev);
  1883. IRDA_ASSERT(self != NULL, return 0;);
  1884. /* Stop device */
  1885. netif_stop_queue(dev);
  1886. /* Stop and remove instance of IrLAP */
  1887. if (self->irlap)
  1888. irlap_close(self->irlap);
  1889. self->irlap = NULL;
  1890. iobase = self->io.fir_base;
  1891. disable_dma(self->io.dma);
  1892. /* Save current bank */
  1893. bank = inb(iobase+BSR);
  1894. /* Disable interrupts */
  1895. switch_bank(iobase, BANK0);
  1896. outb(0, iobase+IER);
  1897. free_irq(self->io.irq, dev);
  1898. free_dma(self->io.dma);
  1899. /* Restore bank register */
  1900. outb(bank, iobase+BSR);
  1901. return 0;
  1902. }
  1903. /*
  1904. * Function nsc_ircc_net_ioctl (dev, rq, cmd)
  1905. *
  1906. * Process IOCTL commands for this device
  1907. *
  1908. */
  1909. static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1910. {
  1911. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1912. struct nsc_ircc_cb *self;
  1913. unsigned long flags;
  1914. int ret = 0;
  1915. IRDA_ASSERT(dev != NULL, return -1;);
  1916. self = netdev_priv(dev);
  1917. IRDA_ASSERT(self != NULL, return -1;);
  1918. IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
  1919. switch (cmd) {
  1920. case SIOCSBANDWIDTH: /* Set bandwidth */
  1921. if (!capable(CAP_NET_ADMIN)) {
  1922. ret = -EPERM;
  1923. break;
  1924. }
  1925. spin_lock_irqsave(&self->lock, flags);
  1926. nsc_ircc_change_speed(self, irq->ifr_baudrate);
  1927. spin_unlock_irqrestore(&self->lock, flags);
  1928. break;
  1929. case SIOCSMEDIABUSY: /* Set media busy */
  1930. if (!capable(CAP_NET_ADMIN)) {
  1931. ret = -EPERM;
  1932. break;
  1933. }
  1934. irda_device_set_media_busy(self->netdev, TRUE);
  1935. break;
  1936. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1937. /* This is already protected */
  1938. irq->ifr_receiving = nsc_ircc_is_receiving(self);
  1939. break;
  1940. default:
  1941. ret = -EOPNOTSUPP;
  1942. }
  1943. return ret;
  1944. }
  1945. static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
  1946. {
  1947. struct nsc_ircc_cb *self = platform_get_drvdata(dev);
  1948. int bank;
  1949. unsigned long flags;
  1950. int iobase = self->io.fir_base;
  1951. if (self->io.suspended)
  1952. return 0;
  1953. IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
  1954. rtnl_lock();
  1955. if (netif_running(self->netdev)) {
  1956. netif_device_detach(self->netdev);
  1957. spin_lock_irqsave(&self->lock, flags);
  1958. /* Save current bank */
  1959. bank = inb(iobase+BSR);
  1960. /* Disable interrupts */
  1961. switch_bank(iobase, BANK0);
  1962. outb(0, iobase+IER);
  1963. /* Restore bank register */
  1964. outb(bank, iobase+BSR);
  1965. spin_unlock_irqrestore(&self->lock, flags);
  1966. free_irq(self->io.irq, self->netdev);
  1967. disable_dma(self->io.dma);
  1968. }
  1969. self->io.suspended = 1;
  1970. rtnl_unlock();
  1971. return 0;
  1972. }
  1973. static int nsc_ircc_resume(struct platform_device *dev)
  1974. {
  1975. struct nsc_ircc_cb *self = platform_get_drvdata(dev);
  1976. unsigned long flags;
  1977. if (!self->io.suspended)
  1978. return 0;
  1979. IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
  1980. rtnl_lock();
  1981. nsc_ircc_setup(&self->io);
  1982. nsc_ircc_init_dongle_interface(self->io.fir_base, self->io.dongle_id);
  1983. if (netif_running(self->netdev)) {
  1984. if (request_irq(self->io.irq, nsc_ircc_interrupt, 0,
  1985. self->netdev->name, self->netdev)) {
  1986. IRDA_WARNING("%s, unable to allocate irq=%d\n",
  1987. driver_name, self->io.irq);
  1988. /*
  1989. * Don't fail resume process, just kill this
  1990. * network interface
  1991. */
  1992. unregister_netdevice(self->netdev);
  1993. } else {
  1994. spin_lock_irqsave(&self->lock, flags);
  1995. nsc_ircc_change_speed(self, self->io.speed);
  1996. spin_unlock_irqrestore(&self->lock, flags);
  1997. netif_device_attach(self->netdev);
  1998. }
  1999. } else {
  2000. spin_lock_irqsave(&self->lock, flags);
  2001. nsc_ircc_change_speed(self, 9600);
  2002. spin_unlock_irqrestore(&self->lock, flags);
  2003. }
  2004. self->io.suspended = 0;
  2005. rtnl_unlock();
  2006. return 0;
  2007. }
  2008. MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
  2009. MODULE_DESCRIPTION("NSC IrDA Device Driver");
  2010. MODULE_LICENSE("GPL");
  2011. module_param(qos_mtt_bits, int, 0);
  2012. MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time");
  2013. module_param_array(io, int, NULL, 0);
  2014. MODULE_PARM_DESC(io, "Base I/O addresses");
  2015. module_param_array(irq, int, NULL, 0);
  2016. MODULE_PARM_DESC(irq, "IRQ lines");
  2017. module_param_array(dma, int, NULL, 0);
  2018. MODULE_PARM_DESC(dma, "DMA channels");
  2019. module_param(dongle_id, int, 0);
  2020. MODULE_PARM_DESC(dongle_id, "Type-id of used dongle");
  2021. module_init(nsc_ircc_init);
  2022. module_exit(nsc_ircc_cleanup);