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/drivers/net/bna/bna_ctrl.c

https://bitbucket.org/ndreys/linux-sunxi
C | 3077 lines | 2328 code | 519 blank | 230 comment | 222 complexity | 76a1af13028ca3238daa335a5fd91915 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfa_sm.h"
  20. #include "bfa_wc.h"
  21. static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
  22. static void
  23. bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
  24. int status)
  25. {
  26. int i;
  27. u8 prio_map;
  28. port->llport.link_status = BNA_LINK_UP;
  29. if (aen->cee_linkup)
  30. port->llport.link_status = BNA_CEE_UP;
  31. /* Compute the priority */
  32. prio_map = aen->prio_map;
  33. if (prio_map) {
  34. for (i = 0; i < 8; i++) {
  35. if ((prio_map >> i) & 0x1)
  36. break;
  37. }
  38. port->priority = i;
  39. } else
  40. port->priority = 0;
  41. /* Dispatch events */
  42. bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
  43. bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
  44. port->link_cbfn(port->bna->bnad, port->llport.link_status);
  45. }
  46. static void
  47. bna_port_cb_link_down(struct bna_port *port, int status)
  48. {
  49. port->llport.link_status = BNA_LINK_DOWN;
  50. /* Dispatch events */
  51. bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
  52. port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
  53. }
  54. static inline int
  55. llport_can_be_up(struct bna_llport *llport)
  56. {
  57. int ready = 0;
  58. if (llport->type == BNA_PORT_T_REGULAR)
  59. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  60. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  61. (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  62. else
  63. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  64. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  65. !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  66. return ready;
  67. }
  68. #define llport_is_up llport_can_be_up
  69. enum bna_llport_event {
  70. LLPORT_E_START = 1,
  71. LLPORT_E_STOP = 2,
  72. LLPORT_E_FAIL = 3,
  73. LLPORT_E_UP = 4,
  74. LLPORT_E_DOWN = 5,
  75. LLPORT_E_FWRESP_UP_OK = 6,
  76. LLPORT_E_FWRESP_UP_FAIL = 7,
  77. LLPORT_E_FWRESP_DOWN = 8
  78. };
  79. static void
  80. bna_llport_cb_port_enabled(struct bna_llport *llport)
  81. {
  82. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  83. if (llport_can_be_up(llport))
  84. bfa_fsm_send_event(llport, LLPORT_E_UP);
  85. }
  86. static void
  87. bna_llport_cb_port_disabled(struct bna_llport *llport)
  88. {
  89. int llport_up = llport_is_up(llport);
  90. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  91. if (llport_up)
  92. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  93. }
  94. /**
  95. * MBOX
  96. */
  97. static int
  98. bna_is_aen(u8 msg_id)
  99. {
  100. switch (msg_id) {
  101. case BFI_LL_I2H_LINK_DOWN_AEN:
  102. case BFI_LL_I2H_LINK_UP_AEN:
  103. case BFI_LL_I2H_PORT_ENABLE_AEN:
  104. case BFI_LL_I2H_PORT_DISABLE_AEN:
  105. return 1;
  106. default:
  107. return 0;
  108. }
  109. }
  110. static void
  111. bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
  112. {
  113. struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
  114. switch (aen->mh.msg_id) {
  115. case BFI_LL_I2H_LINK_UP_AEN:
  116. bna_port_cb_link_up(&bna->port, aen, aen->reason);
  117. break;
  118. case BFI_LL_I2H_LINK_DOWN_AEN:
  119. bna_port_cb_link_down(&bna->port, aen->reason);
  120. break;
  121. case BFI_LL_I2H_PORT_ENABLE_AEN:
  122. bna_llport_cb_port_enabled(&bna->port.llport);
  123. break;
  124. case BFI_LL_I2H_PORT_DISABLE_AEN:
  125. bna_llport_cb_port_disabled(&bna->port.llport);
  126. break;
  127. default:
  128. break;
  129. }
  130. }
  131. static void
  132. bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
  133. {
  134. struct bna *bna = (struct bna *)(llarg);
  135. struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
  136. struct bfi_mhdr *cmd_h, *rsp_h;
  137. struct bna_mbox_qe *mb_qe = NULL;
  138. int to_post = 0;
  139. u8 aen = 0;
  140. char message[BNA_MESSAGE_SIZE];
  141. aen = bna_is_aen(mb_rsp->mh.msg_id);
  142. if (!aen) {
  143. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  144. cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
  145. rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
  146. if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
  147. (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
  148. /* Remove the request from posted_q, update state */
  149. list_del(&mb_qe->qe);
  150. bna->mbox_mod.msg_pending--;
  151. if (list_empty(&bna->mbox_mod.posted_q))
  152. bna->mbox_mod.state = BNA_MBOX_FREE;
  153. else
  154. to_post = 1;
  155. /* Dispatch the cbfn */
  156. if (mb_qe->cbfn)
  157. mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
  158. /* Post the next entry, if needed */
  159. if (to_post) {
  160. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  161. bfa_nw_ioc_mbox_queue(&bna->device.ioc,
  162. &mb_qe->cmd);
  163. }
  164. } else {
  165. snprintf(message, BNA_MESSAGE_SIZE,
  166. "No matching rsp for [%d:%d:%d]\n",
  167. mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
  168. mb_rsp->mh.mtag.i2htok);
  169. pr_info("%s", message);
  170. }
  171. } else
  172. bna_mbox_aen_callback(bna, msg);
  173. }
  174. static void
  175. bna_err_handler(struct bna *bna, u32 intr_status)
  176. {
  177. u32 init_halt;
  178. if (intr_status & __HALT_STATUS_BITS) {
  179. init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
  180. init_halt &= ~__FW_INIT_HALT_P;
  181. writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
  182. }
  183. bfa_nw_ioc_error_isr(&bna->device.ioc);
  184. }
  185. void
  186. bna_mbox_handler(struct bna *bna, u32 intr_status)
  187. {
  188. if (BNA_IS_ERR_INTR(intr_status)) {
  189. bna_err_handler(bna, intr_status);
  190. return;
  191. }
  192. if (BNA_IS_MBOX_INTR(intr_status))
  193. bfa_nw_ioc_mbox_isr(&bna->device.ioc);
  194. }
  195. void
  196. bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
  197. {
  198. struct bfi_mhdr *mh;
  199. mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
  200. mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
  201. bna->mbox_mod.msg_ctr++;
  202. bna->mbox_mod.msg_pending++;
  203. if (bna->mbox_mod.state == BNA_MBOX_FREE) {
  204. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  205. bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
  206. bna->mbox_mod.state = BNA_MBOX_POSTED;
  207. } else {
  208. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  209. }
  210. }
  211. static void
  212. bna_mbox_flush_q(struct bna *bna, struct list_head *q)
  213. {
  214. struct bna_mbox_qe *mb_qe = NULL;
  215. struct list_head *mb_q;
  216. void (*cbfn)(void *arg, int status);
  217. void *cbarg;
  218. mb_q = &bna->mbox_mod.posted_q;
  219. while (!list_empty(mb_q)) {
  220. bfa_q_deq(mb_q, &mb_qe);
  221. cbfn = mb_qe->cbfn;
  222. cbarg = mb_qe->cbarg;
  223. bfa_q_qe_init(mb_qe);
  224. bna->mbox_mod.msg_pending--;
  225. if (cbfn)
  226. cbfn(cbarg, BNA_CB_NOT_EXEC);
  227. }
  228. bna->mbox_mod.state = BNA_MBOX_FREE;
  229. }
  230. static void
  231. bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
  232. {
  233. }
  234. static void
  235. bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
  236. {
  237. bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
  238. }
  239. static void
  240. bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
  241. {
  242. bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
  243. mbox_mod->state = BNA_MBOX_FREE;
  244. mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
  245. INIT_LIST_HEAD(&mbox_mod->posted_q);
  246. mbox_mod->bna = bna;
  247. }
  248. static void
  249. bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
  250. {
  251. mbox_mod->bna = NULL;
  252. }
  253. /**
  254. * LLPORT
  255. */
  256. #define call_llport_stop_cbfn(llport, status)\
  257. do {\
  258. if ((llport)->stop_cbfn)\
  259. (llport)->stop_cbfn(&(llport)->bna->port, status);\
  260. (llport)->stop_cbfn = NULL;\
  261. } while (0)
  262. static void bna_fw_llport_up(struct bna_llport *llport);
  263. static void bna_fw_cb_llport_up(void *arg, int status);
  264. static void bna_fw_llport_down(struct bna_llport *llport);
  265. static void bna_fw_cb_llport_down(void *arg, int status);
  266. static void bna_llport_start(struct bna_llport *llport);
  267. static void bna_llport_stop(struct bna_llport *llport);
  268. static void bna_llport_fail(struct bna_llport *llport);
  269. enum bna_llport_state {
  270. BNA_LLPORT_STOPPED = 1,
  271. BNA_LLPORT_DOWN = 2,
  272. BNA_LLPORT_UP_RESP_WAIT = 3,
  273. BNA_LLPORT_DOWN_RESP_WAIT = 4,
  274. BNA_LLPORT_UP = 5,
  275. BNA_LLPORT_LAST_RESP_WAIT = 6
  276. };
  277. bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
  278. enum bna_llport_event);
  279. bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
  280. enum bna_llport_event);
  281. bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
  282. enum bna_llport_event);
  283. bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
  284. enum bna_llport_event);
  285. bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
  286. enum bna_llport_event);
  287. bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
  288. enum bna_llport_event);
  289. static struct bfa_sm_table llport_sm_table[] = {
  290. {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
  291. {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
  292. {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
  293. {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
  294. {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
  295. {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
  296. };
  297. static void
  298. bna_llport_sm_stopped_entry(struct bna_llport *llport)
  299. {
  300. llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
  301. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  302. }
  303. static void
  304. bna_llport_sm_stopped(struct bna_llport *llport,
  305. enum bna_llport_event event)
  306. {
  307. switch (event) {
  308. case LLPORT_E_START:
  309. bfa_fsm_set_state(llport, bna_llport_sm_down);
  310. break;
  311. case LLPORT_E_STOP:
  312. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  313. break;
  314. case LLPORT_E_FAIL:
  315. break;
  316. case LLPORT_E_DOWN:
  317. /* This event is received due to Rx objects failing */
  318. /* No-op */
  319. break;
  320. case LLPORT_E_FWRESP_UP_OK:
  321. case LLPORT_E_FWRESP_DOWN:
  322. /**
  323. * These events are received due to flushing of mbox when
  324. * device fails
  325. */
  326. /* No-op */
  327. break;
  328. default:
  329. bfa_sm_fault(llport->bna, event);
  330. }
  331. }
  332. static void
  333. bna_llport_sm_down_entry(struct bna_llport *llport)
  334. {
  335. bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
  336. }
  337. static void
  338. bna_llport_sm_down(struct bna_llport *llport,
  339. enum bna_llport_event event)
  340. {
  341. switch (event) {
  342. case LLPORT_E_STOP:
  343. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  344. break;
  345. case LLPORT_E_FAIL:
  346. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  347. break;
  348. case LLPORT_E_UP:
  349. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  350. bna_fw_llport_up(llport);
  351. break;
  352. default:
  353. bfa_sm_fault(llport->bna, event);
  354. }
  355. }
  356. static void
  357. bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
  358. {
  359. BUG_ON(!llport_can_be_up(llport));
  360. /**
  361. * NOTE: Do not call bna_fw_llport_up() here. That will over step
  362. * mbox due to down_resp_wait -> up_resp_wait transition on event
  363. * LLPORT_E_UP
  364. */
  365. }
  366. static void
  367. bna_llport_sm_up_resp_wait(struct bna_llport *llport,
  368. enum bna_llport_event event)
  369. {
  370. switch (event) {
  371. case LLPORT_E_STOP:
  372. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  373. break;
  374. case LLPORT_E_FAIL:
  375. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  376. break;
  377. case LLPORT_E_DOWN:
  378. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  379. break;
  380. case LLPORT_E_FWRESP_UP_OK:
  381. bfa_fsm_set_state(llport, bna_llport_sm_up);
  382. break;
  383. case LLPORT_E_FWRESP_UP_FAIL:
  384. bfa_fsm_set_state(llport, bna_llport_sm_down);
  385. break;
  386. case LLPORT_E_FWRESP_DOWN:
  387. /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
  388. bna_fw_llport_up(llport);
  389. break;
  390. default:
  391. bfa_sm_fault(llport->bna, event);
  392. }
  393. }
  394. static void
  395. bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
  396. {
  397. /**
  398. * NOTE: Do not call bna_fw_llport_down() here. That will over step
  399. * mbox due to up_resp_wait -> down_resp_wait transition on event
  400. * LLPORT_E_DOWN
  401. */
  402. }
  403. static void
  404. bna_llport_sm_down_resp_wait(struct bna_llport *llport,
  405. enum bna_llport_event event)
  406. {
  407. switch (event) {
  408. case LLPORT_E_STOP:
  409. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  410. break;
  411. case LLPORT_E_FAIL:
  412. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  413. break;
  414. case LLPORT_E_UP:
  415. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  416. break;
  417. case LLPORT_E_FWRESP_UP_OK:
  418. /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
  419. bna_fw_llport_down(llport);
  420. break;
  421. case LLPORT_E_FWRESP_UP_FAIL:
  422. case LLPORT_E_FWRESP_DOWN:
  423. bfa_fsm_set_state(llport, bna_llport_sm_down);
  424. break;
  425. default:
  426. bfa_sm_fault(llport->bna, event);
  427. }
  428. }
  429. static void
  430. bna_llport_sm_up_entry(struct bna_llport *llport)
  431. {
  432. }
  433. static void
  434. bna_llport_sm_up(struct bna_llport *llport,
  435. enum bna_llport_event event)
  436. {
  437. switch (event) {
  438. case LLPORT_E_STOP:
  439. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  440. bna_fw_llport_down(llport);
  441. break;
  442. case LLPORT_E_FAIL:
  443. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  444. break;
  445. case LLPORT_E_DOWN:
  446. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  447. bna_fw_llport_down(llport);
  448. break;
  449. default:
  450. bfa_sm_fault(llport->bna, event);
  451. }
  452. }
  453. static void
  454. bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
  455. {
  456. }
  457. static void
  458. bna_llport_sm_last_resp_wait(struct bna_llport *llport,
  459. enum bna_llport_event event)
  460. {
  461. switch (event) {
  462. case LLPORT_E_FAIL:
  463. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  464. break;
  465. case LLPORT_E_DOWN:
  466. /**
  467. * This event is received due to Rx objects stopping in
  468. * parallel to llport
  469. */
  470. /* No-op */
  471. break;
  472. case LLPORT_E_FWRESP_UP_OK:
  473. /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
  474. bna_fw_llport_down(llport);
  475. break;
  476. case LLPORT_E_FWRESP_UP_FAIL:
  477. case LLPORT_E_FWRESP_DOWN:
  478. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  479. break;
  480. default:
  481. bfa_sm_fault(llport->bna, event);
  482. }
  483. }
  484. static void
  485. bna_fw_llport_admin_up(struct bna_llport *llport)
  486. {
  487. struct bfi_ll_port_admin_req ll_req;
  488. memset(&ll_req, 0, sizeof(ll_req));
  489. ll_req.mh.msg_class = BFI_MC_LL;
  490. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  491. ll_req.mh.mtag.h2i.lpu_id = 0;
  492. ll_req.up = BNA_STATUS_T_ENABLED;
  493. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  494. bna_fw_cb_llport_up, llport);
  495. bna_mbox_send(llport->bna, &llport->mbox_qe);
  496. }
  497. static void
  498. bna_fw_llport_up(struct bna_llport *llport)
  499. {
  500. if (llport->type == BNA_PORT_T_REGULAR)
  501. bna_fw_llport_admin_up(llport);
  502. }
  503. static void
  504. bna_fw_cb_llport_up(void *arg, int status)
  505. {
  506. struct bna_llport *llport = (struct bna_llport *)arg;
  507. bfa_q_qe_init(&llport->mbox_qe.qe);
  508. if (status == BFI_LL_CMD_FAIL) {
  509. if (llport->type == BNA_PORT_T_REGULAR)
  510. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  511. else
  512. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  513. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
  514. } else
  515. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
  516. }
  517. static void
  518. bna_fw_llport_admin_down(struct bna_llport *llport)
  519. {
  520. struct bfi_ll_port_admin_req ll_req;
  521. memset(&ll_req, 0, sizeof(ll_req));
  522. ll_req.mh.msg_class = BFI_MC_LL;
  523. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  524. ll_req.mh.mtag.h2i.lpu_id = 0;
  525. ll_req.up = BNA_STATUS_T_DISABLED;
  526. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  527. bna_fw_cb_llport_down, llport);
  528. bna_mbox_send(llport->bna, &llport->mbox_qe);
  529. }
  530. static void
  531. bna_fw_llport_down(struct bna_llport *llport)
  532. {
  533. if (llport->type == BNA_PORT_T_REGULAR)
  534. bna_fw_llport_admin_down(llport);
  535. }
  536. static void
  537. bna_fw_cb_llport_down(void *arg, int status)
  538. {
  539. struct bna_llport *llport = (struct bna_llport *)arg;
  540. bfa_q_qe_init(&llport->mbox_qe.qe);
  541. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
  542. }
  543. static void
  544. bna_port_cb_llport_stopped(struct bna_port *port,
  545. enum bna_cb_status status)
  546. {
  547. bfa_wc_down(&port->chld_stop_wc);
  548. }
  549. static void
  550. bna_llport_init(struct bna_llport *llport, struct bna *bna)
  551. {
  552. llport->flags |= BNA_LLPORT_F_ADMIN_UP;
  553. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  554. llport->type = BNA_PORT_T_REGULAR;
  555. llport->bna = bna;
  556. llport->link_status = BNA_LINK_DOWN;
  557. llport->rx_started_count = 0;
  558. llport->stop_cbfn = NULL;
  559. bfa_q_qe_init(&llport->mbox_qe.qe);
  560. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  561. }
  562. static void
  563. bna_llport_uninit(struct bna_llport *llport)
  564. {
  565. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  566. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  567. llport->bna = NULL;
  568. }
  569. static void
  570. bna_llport_start(struct bna_llport *llport)
  571. {
  572. bfa_fsm_send_event(llport, LLPORT_E_START);
  573. }
  574. static void
  575. bna_llport_stop(struct bna_llport *llport)
  576. {
  577. llport->stop_cbfn = bna_port_cb_llport_stopped;
  578. bfa_fsm_send_event(llport, LLPORT_E_STOP);
  579. }
  580. static void
  581. bna_llport_fail(struct bna_llport *llport)
  582. {
  583. /* Reset the physical port status to enabled */
  584. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  585. bfa_fsm_send_event(llport, LLPORT_E_FAIL);
  586. }
  587. static int
  588. bna_llport_state_get(struct bna_llport *llport)
  589. {
  590. return bfa_sm_to_state(llport_sm_table, llport->fsm);
  591. }
  592. void
  593. bna_llport_rx_started(struct bna_llport *llport)
  594. {
  595. llport->rx_started_count++;
  596. if (llport->rx_started_count == 1) {
  597. llport->flags |= BNA_LLPORT_F_RX_STARTED;
  598. if (llport_can_be_up(llport))
  599. bfa_fsm_send_event(llport, LLPORT_E_UP);
  600. }
  601. }
  602. void
  603. bna_llport_rx_stopped(struct bna_llport *llport)
  604. {
  605. int llport_up = llport_is_up(llport);
  606. llport->rx_started_count--;
  607. if (llport->rx_started_count == 0) {
  608. llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
  609. if (llport_up)
  610. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  611. }
  612. }
  613. /**
  614. * PORT
  615. */
  616. #define bna_port_chld_start(port)\
  617. do {\
  618. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  619. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  620. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  621. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  622. bna_llport_start(&(port)->llport);\
  623. bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
  624. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  625. } while (0)
  626. #define bna_port_chld_stop(port)\
  627. do {\
  628. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  629. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  630. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  631. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  632. bfa_wc_up(&(port)->chld_stop_wc);\
  633. bfa_wc_up(&(port)->chld_stop_wc);\
  634. bfa_wc_up(&(port)->chld_stop_wc);\
  635. bna_llport_stop(&(port)->llport);\
  636. bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
  637. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  638. } while (0)
  639. #define bna_port_chld_fail(port)\
  640. do {\
  641. bna_llport_fail(&(port)->llport);\
  642. bna_tx_mod_fail(&(port)->bna->tx_mod);\
  643. bna_rx_mod_fail(&(port)->bna->rx_mod);\
  644. } while (0)
  645. #define bna_port_rx_start(port)\
  646. do {\
  647. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  648. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  649. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  650. } while (0)
  651. #define bna_port_rx_stop(port)\
  652. do {\
  653. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  654. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  655. bfa_wc_up(&(port)->chld_stop_wc);\
  656. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  657. } while (0)
  658. #define call_port_stop_cbfn(port, status)\
  659. do {\
  660. if ((port)->stop_cbfn)\
  661. (port)->stop_cbfn((port)->stop_cbarg, status);\
  662. (port)->stop_cbfn = NULL;\
  663. (port)->stop_cbarg = NULL;\
  664. } while (0)
  665. #define call_port_pause_cbfn(port, status)\
  666. do {\
  667. if ((port)->pause_cbfn)\
  668. (port)->pause_cbfn((port)->bna->bnad, status);\
  669. (port)->pause_cbfn = NULL;\
  670. } while (0)
  671. #define call_port_mtu_cbfn(port, status)\
  672. do {\
  673. if ((port)->mtu_cbfn)\
  674. (port)->mtu_cbfn((port)->bna->bnad, status);\
  675. (port)->mtu_cbfn = NULL;\
  676. } while (0)
  677. static void bna_fw_pause_set(struct bna_port *port);
  678. static void bna_fw_cb_pause_set(void *arg, int status);
  679. static void bna_fw_mtu_set(struct bna_port *port);
  680. static void bna_fw_cb_mtu_set(void *arg, int status);
  681. enum bna_port_event {
  682. PORT_E_START = 1,
  683. PORT_E_STOP = 2,
  684. PORT_E_FAIL = 3,
  685. PORT_E_PAUSE_CFG = 4,
  686. PORT_E_MTU_CFG = 5,
  687. PORT_E_CHLD_STOPPED = 6,
  688. PORT_E_FWRESP_PAUSE = 7,
  689. PORT_E_FWRESP_MTU = 8
  690. };
  691. enum bna_port_state {
  692. BNA_PORT_STOPPED = 1,
  693. BNA_PORT_MTU_INIT_WAIT = 2,
  694. BNA_PORT_PAUSE_INIT_WAIT = 3,
  695. BNA_PORT_LAST_RESP_WAIT = 4,
  696. BNA_PORT_STARTED = 5,
  697. BNA_PORT_PAUSE_CFG_WAIT = 6,
  698. BNA_PORT_RX_STOP_WAIT = 7,
  699. BNA_PORT_MTU_CFG_WAIT = 8,
  700. BNA_PORT_CHLD_STOP_WAIT = 9
  701. };
  702. bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
  703. enum bna_port_event);
  704. bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
  705. enum bna_port_event);
  706. bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
  707. enum bna_port_event);
  708. bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
  709. enum bna_port_event);
  710. bfa_fsm_state_decl(bna_port, started, struct bna_port,
  711. enum bna_port_event);
  712. bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
  713. enum bna_port_event);
  714. bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
  715. enum bna_port_event);
  716. bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
  717. enum bna_port_event);
  718. bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
  719. enum bna_port_event);
  720. static struct bfa_sm_table port_sm_table[] = {
  721. {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
  722. {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
  723. {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
  724. {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
  725. {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
  726. {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
  727. {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
  728. {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
  729. {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
  730. };
  731. static void
  732. bna_port_sm_stopped_entry(struct bna_port *port)
  733. {
  734. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  735. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  736. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  737. }
  738. static void
  739. bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
  740. {
  741. switch (event) {
  742. case PORT_E_START:
  743. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  744. break;
  745. case PORT_E_STOP:
  746. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  747. break;
  748. case PORT_E_FAIL:
  749. /* No-op */
  750. break;
  751. case PORT_E_PAUSE_CFG:
  752. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  753. break;
  754. case PORT_E_MTU_CFG:
  755. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  756. break;
  757. case PORT_E_CHLD_STOPPED:
  758. /**
  759. * This event is received due to LLPort, Tx and Rx objects
  760. * failing
  761. */
  762. /* No-op */
  763. break;
  764. case PORT_E_FWRESP_PAUSE:
  765. case PORT_E_FWRESP_MTU:
  766. /**
  767. * These events are received due to flushing of mbox when
  768. * device fails
  769. */
  770. /* No-op */
  771. break;
  772. default:
  773. bfa_sm_fault(port->bna, event);
  774. }
  775. }
  776. static void
  777. bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
  778. {
  779. bna_fw_mtu_set(port);
  780. }
  781. static void
  782. bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
  783. {
  784. switch (event) {
  785. case PORT_E_STOP:
  786. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  787. break;
  788. case PORT_E_FAIL:
  789. bfa_fsm_set_state(port, bna_port_sm_stopped);
  790. break;
  791. case PORT_E_PAUSE_CFG:
  792. /* No-op */
  793. break;
  794. case PORT_E_MTU_CFG:
  795. port->flags |= BNA_PORT_F_MTU_CHANGED;
  796. break;
  797. case PORT_E_FWRESP_MTU:
  798. if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  799. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  800. bna_fw_mtu_set(port);
  801. } else {
  802. bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
  803. }
  804. break;
  805. default:
  806. bfa_sm_fault(port->bna, event);
  807. }
  808. }
  809. static void
  810. bna_port_sm_pause_init_wait_entry(struct bna_port *port)
  811. {
  812. bna_fw_pause_set(port);
  813. }
  814. static void
  815. bna_port_sm_pause_init_wait(struct bna_port *port,
  816. enum bna_port_event event)
  817. {
  818. switch (event) {
  819. case PORT_E_STOP:
  820. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  821. break;
  822. case PORT_E_FAIL:
  823. bfa_fsm_set_state(port, bna_port_sm_stopped);
  824. break;
  825. case PORT_E_PAUSE_CFG:
  826. port->flags |= BNA_PORT_F_PAUSE_CHANGED;
  827. break;
  828. case PORT_E_MTU_CFG:
  829. port->flags |= BNA_PORT_F_MTU_CHANGED;
  830. break;
  831. case PORT_E_FWRESP_PAUSE:
  832. if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
  833. port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
  834. bna_fw_pause_set(port);
  835. } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  836. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  837. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  838. } else {
  839. bfa_fsm_set_state(port, bna_port_sm_started);
  840. bna_port_chld_start(port);
  841. }
  842. break;
  843. default:
  844. bfa_sm_fault(port->bna, event);
  845. }
  846. }
  847. static void
  848. bna_port_sm_last_resp_wait_entry(struct bna_port *port)
  849. {
  850. }
  851. static void
  852. bna_port_sm_last_resp_wait(struct bna_port *port,
  853. enum bna_port_event event)
  854. {
  855. switch (event) {
  856. case PORT_E_FAIL:
  857. case PORT_E_FWRESP_PAUSE:
  858. case PORT_E_FWRESP_MTU:
  859. bfa_fsm_set_state(port, bna_port_sm_stopped);
  860. break;
  861. default:
  862. bfa_sm_fault(port->bna, event);
  863. }
  864. }
  865. static void
  866. bna_port_sm_started_entry(struct bna_port *port)
  867. {
  868. /**
  869. * NOTE: Do not call bna_port_chld_start() here, since it will be
  870. * inadvertently called during pause_cfg_wait->started transition
  871. * as well
  872. */
  873. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  874. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  875. }
  876. static void
  877. bna_port_sm_started(struct bna_port *port,
  878. enum bna_port_event event)
  879. {
  880. switch (event) {
  881. case PORT_E_STOP:
  882. bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
  883. break;
  884. case PORT_E_FAIL:
  885. bfa_fsm_set_state(port, bna_port_sm_stopped);
  886. bna_port_chld_fail(port);
  887. break;
  888. case PORT_E_PAUSE_CFG:
  889. bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
  890. break;
  891. case PORT_E_MTU_CFG:
  892. bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
  893. break;
  894. default:
  895. bfa_sm_fault(port->bna, event);
  896. }
  897. }
  898. static void
  899. bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
  900. {
  901. bna_fw_pause_set(port);
  902. }
  903. static void
  904. bna_port_sm_pause_cfg_wait(struct bna_port *port,
  905. enum bna_port_event event)
  906. {
  907. switch (event) {
  908. case PORT_E_FAIL:
  909. bfa_fsm_set_state(port, bna_port_sm_stopped);
  910. bna_port_chld_fail(port);
  911. break;
  912. case PORT_E_FWRESP_PAUSE:
  913. bfa_fsm_set_state(port, bna_port_sm_started);
  914. break;
  915. default:
  916. bfa_sm_fault(port->bna, event);
  917. }
  918. }
  919. static void
  920. bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
  921. {
  922. bna_port_rx_stop(port);
  923. }
  924. static void
  925. bna_port_sm_rx_stop_wait(struct bna_port *port,
  926. enum bna_port_event event)
  927. {
  928. switch (event) {
  929. case PORT_E_FAIL:
  930. bfa_fsm_set_state(port, bna_port_sm_stopped);
  931. bna_port_chld_fail(port);
  932. break;
  933. case PORT_E_CHLD_STOPPED:
  934. bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
  935. break;
  936. default:
  937. bfa_sm_fault(port->bna, event);
  938. }
  939. }
  940. static void
  941. bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
  942. {
  943. bna_fw_mtu_set(port);
  944. }
  945. static void
  946. bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
  947. {
  948. switch (event) {
  949. case PORT_E_FAIL:
  950. bfa_fsm_set_state(port, bna_port_sm_stopped);
  951. bna_port_chld_fail(port);
  952. break;
  953. case PORT_E_FWRESP_MTU:
  954. bfa_fsm_set_state(port, bna_port_sm_started);
  955. bna_port_rx_start(port);
  956. break;
  957. default:
  958. bfa_sm_fault(port->bna, event);
  959. }
  960. }
  961. static void
  962. bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
  963. {
  964. bna_port_chld_stop(port);
  965. }
  966. static void
  967. bna_port_sm_chld_stop_wait(struct bna_port *port,
  968. enum bna_port_event event)
  969. {
  970. switch (event) {
  971. case PORT_E_FAIL:
  972. bfa_fsm_set_state(port, bna_port_sm_stopped);
  973. bna_port_chld_fail(port);
  974. break;
  975. case PORT_E_CHLD_STOPPED:
  976. bfa_fsm_set_state(port, bna_port_sm_stopped);
  977. break;
  978. default:
  979. bfa_sm_fault(port->bna, event);
  980. }
  981. }
  982. static void
  983. bna_fw_pause_set(struct bna_port *port)
  984. {
  985. struct bfi_ll_set_pause_req ll_req;
  986. memset(&ll_req, 0, sizeof(ll_req));
  987. ll_req.mh.msg_class = BFI_MC_LL;
  988. ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
  989. ll_req.mh.mtag.h2i.lpu_id = 0;
  990. ll_req.tx_pause = port->pause_config.tx_pause;
  991. ll_req.rx_pause = port->pause_config.rx_pause;
  992. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  993. bna_fw_cb_pause_set, port);
  994. bna_mbox_send(port->bna, &port->mbox_qe);
  995. }
  996. static void
  997. bna_fw_cb_pause_set(void *arg, int status)
  998. {
  999. struct bna_port *port = (struct bna_port *)arg;
  1000. bfa_q_qe_init(&port->mbox_qe.qe);
  1001. bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
  1002. }
  1003. void
  1004. bna_fw_mtu_set(struct bna_port *port)
  1005. {
  1006. struct bfi_ll_mtu_info_req ll_req;
  1007. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
  1008. ll_req.mtu = htons((u16)port->mtu);
  1009. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  1010. bna_fw_cb_mtu_set, port);
  1011. bna_mbox_send(port->bna, &port->mbox_qe);
  1012. }
  1013. void
  1014. bna_fw_cb_mtu_set(void *arg, int status)
  1015. {
  1016. struct bna_port *port = (struct bna_port *)arg;
  1017. bfa_q_qe_init(&port->mbox_qe.qe);
  1018. bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
  1019. }
  1020. static void
  1021. bna_port_cb_chld_stopped(void *arg)
  1022. {
  1023. struct bna_port *port = (struct bna_port *)arg;
  1024. bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
  1025. }
  1026. static void
  1027. bna_port_init(struct bna_port *port, struct bna *bna)
  1028. {
  1029. port->bna = bna;
  1030. port->flags = 0;
  1031. port->mtu = 0;
  1032. port->type = BNA_PORT_T_REGULAR;
  1033. port->link_cbfn = bnad_cb_port_link_status;
  1034. port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
  1035. port->chld_stop_wc.wc_cbarg = port;
  1036. port->chld_stop_wc.wc_count = 0;
  1037. port->stop_cbfn = NULL;
  1038. port->stop_cbarg = NULL;
  1039. port->pause_cbfn = NULL;
  1040. port->mtu_cbfn = NULL;
  1041. bfa_q_qe_init(&port->mbox_qe.qe);
  1042. bfa_fsm_set_state(port, bna_port_sm_stopped);
  1043. bna_llport_init(&port->llport, bna);
  1044. }
  1045. static void
  1046. bna_port_uninit(struct bna_port *port)
  1047. {
  1048. bna_llport_uninit(&port->llport);
  1049. port->flags = 0;
  1050. port->bna = NULL;
  1051. }
  1052. static int
  1053. bna_port_state_get(struct bna_port *port)
  1054. {
  1055. return bfa_sm_to_state(port_sm_table, port->fsm);
  1056. }
  1057. static void
  1058. bna_port_start(struct bna_port *port)
  1059. {
  1060. port->flags |= BNA_PORT_F_DEVICE_READY;
  1061. if (port->flags & BNA_PORT_F_ENABLED)
  1062. bfa_fsm_send_event(port, PORT_E_START);
  1063. }
  1064. static void
  1065. bna_port_stop(struct bna_port *port)
  1066. {
  1067. port->stop_cbfn = bna_device_cb_port_stopped;
  1068. port->stop_cbarg = &port->bna->device;
  1069. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1070. bfa_fsm_send_event(port, PORT_E_STOP);
  1071. }
  1072. static void
  1073. bna_port_fail(struct bna_port *port)
  1074. {
  1075. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1076. bfa_fsm_send_event(port, PORT_E_FAIL);
  1077. }
  1078. void
  1079. bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
  1080. {
  1081. bfa_wc_down(&port->chld_stop_wc);
  1082. }
  1083. void
  1084. bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
  1085. {
  1086. bfa_wc_down(&port->chld_stop_wc);
  1087. }
  1088. int
  1089. bna_port_mtu_get(struct bna_port *port)
  1090. {
  1091. return port->mtu;
  1092. }
  1093. void
  1094. bna_port_enable(struct bna_port *port)
  1095. {
  1096. if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
  1097. return;
  1098. port->flags |= BNA_PORT_F_ENABLED;
  1099. if (port->flags & BNA_PORT_F_DEVICE_READY)
  1100. bfa_fsm_send_event(port, PORT_E_START);
  1101. }
  1102. void
  1103. bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
  1104. void (*cbfn)(void *, enum bna_cb_status))
  1105. {
  1106. if (type == BNA_SOFT_CLEANUP) {
  1107. (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
  1108. return;
  1109. }
  1110. port->stop_cbfn = cbfn;
  1111. port->stop_cbarg = port->bna->bnad;
  1112. port->flags &= ~BNA_PORT_F_ENABLED;
  1113. bfa_fsm_send_event(port, PORT_E_STOP);
  1114. }
  1115. void
  1116. bna_port_pause_config(struct bna_port *port,
  1117. struct bna_pause_config *pause_config,
  1118. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1119. {
  1120. port->pause_config = *pause_config;
  1121. port->pause_cbfn = cbfn;
  1122. bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
  1123. }
  1124. void
  1125. bna_port_mtu_set(struct bna_port *port, int mtu,
  1126. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1127. {
  1128. port->mtu = mtu;
  1129. port->mtu_cbfn = cbfn;
  1130. bfa_fsm_send_event(port, PORT_E_MTU_CFG);
  1131. }
  1132. void
  1133. bna_port_mac_get(struct bna_port *port, mac_t *mac)
  1134. {
  1135. *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
  1136. }
  1137. /**
  1138. * DEVICE
  1139. */
  1140. #define enable_mbox_intr(_device)\
  1141. do {\
  1142. u32 intr_status;\
  1143. bna_intr_status_get((_device)->bna, intr_status);\
  1144. bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
  1145. bna_mbox_intr_enable((_device)->bna);\
  1146. } while (0)
  1147. #define disable_mbox_intr(_device)\
  1148. do {\
  1149. bna_mbox_intr_disable((_device)->bna);\
  1150. bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
  1151. } while (0)
  1152. static const struct bna_chip_regs_offset reg_offset[] =
  1153. {{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
  1154. HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
  1155. {HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
  1156. HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
  1157. {HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
  1158. HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
  1159. {HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
  1160. HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
  1161. };
  1162. enum bna_device_event {
  1163. DEVICE_E_ENABLE = 1,
  1164. DEVICE_E_DISABLE = 2,
  1165. DEVICE_E_IOC_READY = 3,
  1166. DEVICE_E_IOC_FAILED = 4,
  1167. DEVICE_E_IOC_DISABLED = 5,
  1168. DEVICE_E_IOC_RESET = 6,
  1169. DEVICE_E_PORT_STOPPED = 7,
  1170. };
  1171. enum bna_device_state {
  1172. BNA_DEVICE_STOPPED = 1,
  1173. BNA_DEVICE_IOC_READY_WAIT = 2,
  1174. BNA_DEVICE_READY = 3,
  1175. BNA_DEVICE_PORT_STOP_WAIT = 4,
  1176. BNA_DEVICE_IOC_DISABLE_WAIT = 5,
  1177. BNA_DEVICE_FAILED = 6
  1178. };
  1179. bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
  1180. enum bna_device_event);
  1181. bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
  1182. enum bna_device_event);
  1183. bfa_fsm_state_decl(bna_device, ready, struct bna_device,
  1184. enum bna_device_event);
  1185. bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
  1186. enum bna_device_event);
  1187. bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
  1188. enum bna_device_event);
  1189. bfa_fsm_state_decl(bna_device, failed, struct bna_device,
  1190. enum bna_device_event);
  1191. static struct bfa_sm_table device_sm_table[] = {
  1192. {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
  1193. {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
  1194. {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
  1195. {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
  1196. {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
  1197. {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
  1198. };
  1199. static void
  1200. bna_device_sm_stopped_entry(struct bna_device *device)
  1201. {
  1202. if (device->stop_cbfn)
  1203. device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
  1204. device->stop_cbfn = NULL;
  1205. device->stop_cbarg = NULL;
  1206. }
  1207. static void
  1208. bna_device_sm_stopped(struct bna_device *device,
  1209. enum bna_device_event event)
  1210. {
  1211. switch (event) {
  1212. case DEVICE_E_ENABLE:
  1213. if (device->intr_type == BNA_INTR_T_MSIX)
  1214. bna_mbox_msix_idx_set(device);
  1215. bfa_nw_ioc_enable(&device->ioc);
  1216. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1217. break;
  1218. case DEVICE_E_DISABLE:
  1219. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1220. break;
  1221. case DEVICE_E_IOC_RESET:
  1222. enable_mbox_intr(device);
  1223. break;
  1224. case DEVICE_E_IOC_FAILED:
  1225. bfa_fsm_set_state(device, bna_device_sm_failed);
  1226. break;
  1227. default:
  1228. bfa_sm_fault(device->bna, event);
  1229. }
  1230. }
  1231. static void
  1232. bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
  1233. {
  1234. /**
  1235. * Do not call bfa_ioc_enable() here. It must be called in the
  1236. * previous state due to failed -> ioc_ready_wait transition.
  1237. */
  1238. }
  1239. static void
  1240. bna_device_sm_ioc_ready_wait(struct bna_device *device,
  1241. enum bna_device_event event)
  1242. {
  1243. switch (event) {
  1244. case DEVICE_E_DISABLE:
  1245. if (device->ready_cbfn)
  1246. device->ready_cbfn(device->ready_cbarg,
  1247. BNA_CB_INTERRUPT);
  1248. device->ready_cbfn = NULL;
  1249. device->ready_cbarg = NULL;
  1250. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1251. break;
  1252. case DEVICE_E_IOC_READY:
  1253. bfa_fsm_set_state(device, bna_device_sm_ready);
  1254. break;
  1255. case DEVICE_E_IOC_FAILED:
  1256. bfa_fsm_set_state(device, bna_device_sm_failed);
  1257. break;
  1258. case DEVICE_E_IOC_RESET:
  1259. enable_mbox_intr(device);
  1260. break;
  1261. default:
  1262. bfa_sm_fault(device->bna, event);
  1263. }
  1264. }
  1265. static void
  1266. bna_device_sm_ready_entry(struct bna_device *device)
  1267. {
  1268. bna_mbox_mod_start(&device->bna->mbox_mod);
  1269. bna_port_start(&device->bna->port);
  1270. if (device->ready_cbfn)
  1271. device->ready_cbfn(device->ready_cbarg,
  1272. BNA_CB_SUCCESS);
  1273. device->ready_cbfn = NULL;
  1274. device->ready_cbarg = NULL;
  1275. }
  1276. static void
  1277. bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
  1278. {
  1279. switch (event) {
  1280. case DEVICE_E_DISABLE:
  1281. bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
  1282. break;
  1283. case DEVICE_E_IOC_FAILED:
  1284. bfa_fsm_set_state(device, bna_device_sm_failed);
  1285. break;
  1286. default:
  1287. bfa_sm_fault(device->bna, event);
  1288. }
  1289. }
  1290. static void
  1291. bna_device_sm_port_stop_wait_entry(struct bna_device *device)
  1292. {
  1293. bna_port_stop(&device->bna->port);
  1294. }
  1295. static void
  1296. bna_device_sm_port_stop_wait(struct bna_device *device,
  1297. enum bna_device_event event)
  1298. {
  1299. switch (event) {
  1300. case DEVICE_E_PORT_STOPPED:
  1301. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1302. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1303. break;
  1304. case DEVICE_E_IOC_FAILED:
  1305. disable_mbox_intr(device);
  1306. bna_port_fail(&device->bna->port);
  1307. break;
  1308. default:
  1309. bfa_sm_fault(device->bna, event);
  1310. }
  1311. }
  1312. static void
  1313. bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
  1314. {
  1315. bfa_nw_ioc_disable(&device->ioc);
  1316. }
  1317. static void
  1318. bna_device_sm_ioc_disable_wait(struct bna_device *device,
  1319. enum bna_device_event event)
  1320. {
  1321. switch (event) {
  1322. case DEVICE_E_IOC_DISABLED:
  1323. disable_mbox_intr(device);
  1324. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1325. break;
  1326. default:
  1327. bfa_sm_fault(device->bna, event);
  1328. }
  1329. }
  1330. static void
  1331. bna_device_sm_failed_entry(struct bna_device *device)
  1332. {
  1333. disable_mbox_intr(device);
  1334. bna_port_fail(&device->bna->port);
  1335. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1336. if (device->ready_cbfn)
  1337. device->ready_cbfn(device->ready_cbarg,
  1338. BNA_CB_FAIL);
  1339. device->ready_cbfn = NULL;
  1340. device->ready_cbarg = NULL;
  1341. }
  1342. static void
  1343. bna_device_sm_failed(struct bna_device *device,
  1344. enum bna_device_event event)
  1345. {
  1346. switch (event) {
  1347. case DEVICE_E_DISABLE:
  1348. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1349. break;
  1350. case DEVICE_E_IOC_RESET:
  1351. enable_mbox_intr(device);
  1352. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1353. break;
  1354. default:
  1355. bfa_sm_fault(device->bna, event);
  1356. }
  1357. }
  1358. /* IOC callback functions */
  1359. static void
  1360. bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
  1361. {
  1362. struct bna_device *device = (struct bna_device *)dev;
  1363. if (error)
  1364. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1365. else
  1366. bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
  1367. }
  1368. static void
  1369. bna_device_cb_iocll_disabled(void *dev)
  1370. {
  1371. struct bna_device *device = (struct bna_device *)dev;
  1372. bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
  1373. }
  1374. static void
  1375. bna_device_cb_iocll_failed(void *dev)
  1376. {
  1377. struct bna_device *device = (struct bna_device *)dev;
  1378. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1379. }
  1380. static void
  1381. bna_device_cb_iocll_reset(void *dev)
  1382. {
  1383. struct bna_device *device = (struct bna_device *)dev;
  1384. bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
  1385. }
  1386. static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
  1387. bna_device_cb_iocll_ready,
  1388. bna_device_cb_iocll_disabled,
  1389. bna_device_cb_iocll_failed,
  1390. bna_device_cb_iocll_reset
  1391. };
  1392. /* device */
  1393. static void
  1394. bna_adv_device_init(struct bna_device *device, struct bna *bna,
  1395. struct bna_res_info *res_info)
  1396. {
  1397. u8 *kva;
  1398. u64 dma;
  1399. device->bna = bna;
  1400. kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
  1401. /**
  1402. * Attach common modules (Diag, SFP, CEE, Port) and claim respective
  1403. * DMA memory.
  1404. */
  1405. BNA_GET_DMA_ADDR(
  1406. &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
  1407. kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
  1408. bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
  1409. bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
  1410. kva += bfa_nw_cee_meminfo();
  1411. dma += bfa_nw_cee_meminfo();
  1412. }
  1413. static void
  1414. bna_device_init(struct bna_device *device, struct bna *bna,
  1415. struct bna_res_info *res_info)
  1416. {
  1417. u64 dma;
  1418. device->bna = bna;
  1419. /**
  1420. * Attach IOC and claim:
  1421. * 1. DMA memory for IOC attributes
  1422. * 2. Kernel memory for FW trace
  1423. */
  1424. bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
  1425. bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
  1426. BNA_GET_DMA_ADDR(
  1427. &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
  1428. bfa_nw_ioc_mem_claim(&device->ioc,
  1429. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
  1430. dma);
  1431. bna_adv_device_init(device, bna, res_info);
  1432. /*
  1433. * Initialize mbox_mod only after IOC, so that mbox handler
  1434. * registration goes through
  1435. */
  1436. device->intr_type =
  1437. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
  1438. device->vector =
  1439. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
  1440. bna_mbox_mod_init(&bna->mbox_mod, bna);
  1441. device->ready_cbfn = device->stop_cbfn = NULL;
  1442. device->ready_cbarg = device->stop_cbarg = NULL;
  1443. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1444. }
  1445. static void
  1446. bna_device_uninit(struct bna_device *device)
  1447. {
  1448. bna_mbox_mod_uninit(&device->bna->mbox_mod);
  1449. bfa_nw_ioc_detach(&device->ioc);
  1450. device->bna = NULL;
  1451. }
  1452. static void
  1453. bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
  1454. {
  1455. struct bna_device *device = (struct bna_device *)arg;
  1456. bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
  1457. }
  1458. static int
  1459. bna_device_status_get(struct bna_device *device)
  1460. {
  1461. return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
  1462. }
  1463. void
  1464. bna_device_enable(struct bna_device *device)
  1465. {
  1466. if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
  1467. bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
  1468. return;
  1469. }
  1470. device->ready_cbfn = bnad_cb_device_enabled;
  1471. device->ready_cbarg = device->bna->bnad;
  1472. bfa_fsm_send_event(device, DEVICE_E_ENABLE);
  1473. }
  1474. void
  1475. bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
  1476. {
  1477. if (type == BNA_SOFT_CLEANUP) {
  1478. bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
  1479. return;
  1480. }
  1481. device->stop_cbfn = bnad_cb_device_disabled;
  1482. device->stop_cbarg = device->bna->bnad;
  1483. bfa_fsm_send_event(device, DEVICE_E_DISABLE);
  1484. }
  1485. static int
  1486. bna_device_state_get(struct bna_device *device)
  1487. {
  1488. return bfa_sm_to_state(device_sm_table, device->fsm);
  1489. }
  1490. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  1491. {12, 12},
  1492. {6, 10},
  1493. {5, 10},
  1494. {4, 8},
  1495. {3, 6},
  1496. {3, 6},
  1497. {2, 4},
  1498. {1, 2},
  1499. };
  1500. /* utils */
  1501. static void
  1502. bna_adv_res_req(struct bna_res_info *res_info)
  1503. {
  1504. /* DMA memory for COMMON_MODULE */
  1505. res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
  1506. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1507. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
  1508. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
  1509. bfa_nw_cee_meminfo(), PAGE_SIZE);
  1510. /* Virtual memory for retreiving fw_trc */
  1511. res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
  1512. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1513. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
  1514. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
  1515. /* DMA memory for retreiving stats */
  1516. res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
  1517. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1518. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
  1519. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
  1520. ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
  1521. /* Virtual memory for soft stats */
  1522. res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
  1523. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1524. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
  1525. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
  1526. sizeof(struct bna_sw_stats);
  1527. }
  1528. static void
  1529. bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
  1530. {
  1531. struct bna_tx *tx;
  1532. struct bna_txq *txq;
  1533. struct bna_rx *rx;
  1534. struct bna_rxp *rxp;
  1535. struct list_head *qe;
  1536. struct list_head *txq_qe;
  1537. struct list_head *rxp_qe;
  1538. struct list_head *mac_qe;
  1539. int i;
  1540. sw_stats->device_state = bna_device_state_get(&bna->device);
  1541. sw_stats->port_state = bna_port_state_get(&bna->port);
  1542. sw_stats->port_flags = bna->port.flags;
  1543. sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
  1544. sw_stats->priority = bna->port.priority;
  1545. i = 0;
  1546. list_for_each(qe, &bna->tx_mod.tx_active_q) {
  1547. tx = (struct bna_tx *)qe;
  1548. sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
  1549. sw_stats->tx_stats[i].tx_flags = tx->flags;
  1550. sw_stats->tx_stats[i].num_txqs = 0;
  1551. sw_stats->tx_stats[i].txq_bmap[0] = 0;
  1552. sw_stats->tx_stats[i].txq_bmap[1] = 0;
  1553. list_for_each(txq_qe, &tx->txq_q) {
  1554. txq = (struct bna_txq *)txq_qe;
  1555. if (txq->txq_id < 32)
  1556. sw_stats->tx_stats[i].txq_bmap[0] |=
  1557. ((u32)1 << txq->txq_id);
  1558. else
  1559. sw_stats->tx_stats[i].txq_bmap[1] |=
  1560. ((u32)
  1561. 1 << (txq->txq_id - 32));
  1562. sw_stats->tx_stats[i].num_txqs++;
  1563. }
  1564. sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
  1565. i++;
  1566. }
  1567. sw_stats->num_active_tx = i;
  1568. i = 0;
  1569. list_for_each(qe, &bna->rx_mod.rx_active_q) {
  1570. rx = (struct bna_rx *)qe;
  1571. sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
  1572. sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
  1573. sw_stats->rx_stats[i].num_rxps = 0;
  1574. sw_stats->rx_stats[i].num_rxqs = 0;
  1575. sw_stats->rx_stats[i].rxq_bmap[0] = 0;
  1576. sw_stats->rx_stats[i].rxq_bmap[1] = 0;
  1577. sw_stats->rx_stats[i].cq_bmap[0] = 0;
  1578. sw_stats->rx_stats[i].cq_bmap[1] = 0;
  1579. list_for_each(rxp_qe, &rx->rxp_q) {
  1580. rxp = (struct bna_rxp *)rxp_qe;
  1581. sw_stats->rx_stats[i].num_rxqs += 1;
  1582. if (rxp->type == BNA_RXP_SINGLE) {
  1583. if (rxp->rxq.single.only->rxq_id < 32) {
  1584. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1585. ((u32)1 <<
  1586. rxp->rxq.single.only->rxq_id);
  1587. } else {
  1588. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1589. ((u32)1 <<
  1590. (rxp->rxq.single.only->rxq_id - 32));
  1591. }
  1592. } else {
  1593. if (rxp->rxq.slr.large->rxq_id < 32) {
  1594. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1595. ((u32)1 <<
  1596. rxp->rxq.slr.large->rxq_id);
  1597. } else {
  1598. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1599. ((u32)1 <<
  1600. (rxp->rxq.slr.large->rxq_id - 32));
  1601. }
  1602. if (rxp->rxq.slr.small->rxq_id < 32) {
  1603. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1604. ((u32)1 <<
  1605. rxp->rxq.slr.small->rxq_id);
  1606. } else {
  1607. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1608. ((u32)1 <<
  1609. (rxp->rxq.slr.small->rxq_id - 32));
  1610. }
  1611. sw_stats->rx_stats[i].num_rxqs += 1;
  1612. }
  1613. if (rxp->cq.cq_id < 32)
  1614. sw_stats->rx_stats[i].cq_bmap[0] |=
  1615. (1 << rxp->cq.cq_id);
  1616. else
  1617. sw_stats->rx_stats[i].cq_bmap[1] |=
  1618. (1 << (rxp->cq.cq_id - 32));
  1619. sw_stats->rx_stats[i].num_rxps++;
  1620. }
  1621. sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
  1622. sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
  1623. sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
  1624. sw_stats->rx_stats[i].num_active_ucast = 0;
  1625. if (rx->rxf.ucast_active_mac)
  1626. sw_stats->rx_stats[i].num_active_ucast++;
  1627. list_for_each(mac_qe, &rx->rxf.ucast_active_q)
  1628. sw_stats->rx_stats[i].num_active_ucast++;
  1629. sw_stats->rx_stats[i].num_active_mcast = 0;
  1630. list_for_each(mac_qe, &rx->rxf.mcast_active_q)
  1631. sw_stats->rx_stats[i].num_active_mcast++;
  1632. sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
  1633. sw_stats->rx_stats[i].vlan_filter_status =
  1634. rx->rxf.vlan_filter_status;
  1635. memcpy(sw_stats->rx_stats[i].vlan_filter_table,
  1636. rx->rxf.vlan_filter_table,
  1637. sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
  1638. sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
  1639. sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
  1640. i++;
  1641. }
  1642. sw_stats->num_active_rx = i;
  1643. }
  1644. static void
  1645. bna_fw_cb_stats_get(void *arg, int status)
  1646. {
  1647. struct bna *bna = (struct bna *)arg;
  1648. u64 *p_stats;
  1649. int i, count;
  1650. int rxf_count, txf_count;
  1651. u64 rxf_bmap, txf_bmap;
  1652. bfa_q_qe_init(&bna->mbox_qe.qe);
  1653. if (status == 0) {
  1654. p_stats = (u64 *)bna->stats.hw_stats;
  1655. count = sizeof(struct bfi_ll_stats) / sizeof(u64);
  1656. for (i = 0; i < count; i++)
  1657. p_stats[i] = cpu_to_be64(p_stats[i]);
  1658. rxf_count = 0;
  1659. rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
  1660. ((u64)bna->stats.rxf_bmap[1] << 32);
  1661. for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
  1662. if (rxf_bmap & ((u64)1 << i))
  1663. rxf_count++;
  1664. txf_count = 0;
  1665. txf_bmap = (u64)bna->stats.txf_bmap[0] |
  1666. ((u64)bna->stats.txf_bmap[1] << 32);
  1667. for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
  1668. if (txf_bmap & ((u64)1 << i))
  1669. txf_count++;
  1670. p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
  1671. ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
  1672. txf_count * sizeof(struct bfi_ll_stats_txf))/
  1673. sizeof(u64));
  1674. /* Populate the TXF stats from the firmware DMAed copy */
  1675. for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
  1676. if (txf_bmap & ((u64)1 << i)) {
  1677. p_stats -= sizeof(struct bfi_ll_stats_txf)/
  1678. sizeof(u64);
  1679. memcpy(&bna->stats.hw_stats->txf_stats[i],
  1680. p_stats,
  1681. sizeof(struct bfi_ll_stats_txf));
  1682. }
  1683. /* Populate the RXF stats from the firmware DMAed copy */
  1684. for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
  1685. if (rxf_bmap & ((u64)1 << i)) {
  1686. p_stats -= sizeof(struct bfi_ll_stats_rxf)/
  1687. sizeof(u64);
  1688. memcpy(&bna->stats.hw_stats->rxf_stats[i],
  1689. p_stats,
  1690. sizeof(struct bfi_ll_stats_rxf));
  1691. }
  1692. bna_sw_stats_get(bna, bna->stats.sw_stats);
  1693. bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
  1694. } else
  1695. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1696. }
  1697. static void
  1698. bna_fw_stats_get(struct bna *bna)
  1699. {
  1700. struct bfi_ll_stats_req ll_req;
  1701. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
  1702. ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
  1703. ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
  1704. ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
  1705. ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
  1706. ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
  1707. ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
  1708. ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
  1709. bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
  1710. bna_fw_cb_stats_get, bna);
  1711. bna_mbox_send(bna, &bna->mbox_qe);
  1712. bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
  1713. bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
  1714. bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
  1715. bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
  1716. }
  1717. void
  1718. bna_stats_get(struct bna *bna)
  1719. {
  1720. if (bna_device_status_get(&bna->device))
  1721. bna_fw_stats_get(bna);
  1722. else
  1723. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1724. }
  1725. /* IB */
  1726. static void
  1727. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  1728. {
  1729. ib->ib_config.coalescing_timeo = coalescing_timeo;
  1730. if (ib->start_count)
  1731. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  1732. (u32)ib->ib_config.coalescing_timeo, 0);
  1733. }
  1734. /* RxF */
  1735. void
  1736. bna_rxf_adv_init(struct bna_rxf *rxf,
  1737. struct bna_rx *rx,
  1738. struct bna_rx_config *q_config)
  1739. {
  1740. switch (q_config->rxp_type) {
  1741. case BNA_RXP_SINGLE:
  1742. /* No-op */
  1743. break;
  1744. case BNA_RXP_SLR:
  1745. rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
  1746. break;
  1747. case BNA_RXP_HDS:
  1748. rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
  1749. rxf->hds_cfg.header_size =
  1750. q_config->hds_config.header_size;
  1751. rxf->forced_offset = 0;
  1752. break;
  1753. default:
  1754. break;
  1755. }
  1756. if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
  1757. rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
  1758. rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
  1759. rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
  1760. memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
  1761. &q_config->rss_config.toeplitz_hash_key[0],
  1762. sizeof(rxf->rss_cfg.toeplitz_hash_key));
  1763. }
  1764. }
  1765. static void
  1766. rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
  1767. {
  1768. struct bfi_ll_rxf_req req;
  1769. bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
  1770. req.rxf_id = rxf->rxf_id;
  1771. req.enable = status;
  1772. bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
  1773. rxf_cb_cam_fltr_mbox_cmd, rxf);
  1774. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  1775. }
  1776. int
  1777. rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
  1778. {
  1779. struct bna_mac *mac = NULL;
  1780. struct list_head *qe;
  1781. /* Add additional MAC entries */
  1782. if (!list_empty(&rxf->ucast_pending_add_q)) {
  1783. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  1784. bfa_q_qe_init(qe);
  1785. mac = (struct bna_mac *)qe;
  1786. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
  1787. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  1788. return 1;
  1789. }
  1790. /* Delete MAC addresses previousely added */
  1791. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1792. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1793. bfa_q_qe_init(qe);
  1794. mac = (struct bna_mac *)qe;
  1795. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1796. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1797. return 1;
  1798. }
  1799. return 0;
  1800. }
  1801. int
  1802. rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
  1803. {
  1804. struct bna *bna = rxf->rx->bna;
  1805. /* Enable/disable promiscuous mode */
  1806. if (is_promisc_enable(rxf->rxmode_pending,
  1807. rxf->rxmode_pending_bitmask)) {
  1808. /* move promisc configuration from pending -> active */
  1809. promisc_inactive(rxf->rxmode_pending,
  1810. rxf->rxmode_pending_bitmask);
  1811. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  1812. /* Disable VLAN filter to allow all VLANs */
  1813. __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
  1814. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1815. BNA_STATUS_T_ENABLED);
  1816. return 1;
  1817. } else if (is_promisc_disable(rxf->rxmode_pending,
  1818. rxf->rxmode_pending_bitmask)) {
  1819. /* move promisc configuration from pending -> active */
  1820. promisc_inactive(rxf->rxmode_pending,
  1821. rxf->rxmode_pending_bitmask);
  1822. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1823. bna->rxf_promisc_id = BFI_MAX_RXF;
  1824. /* Revert VLAN filter */
  1825. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1826. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1827. BNA_STATUS_T_DISABLED);
  1828. return 1;
  1829. }
  1830. return 0;
  1831. }
  1832. int
  1833. rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
  1834. {
  1835. /* Enable/disable allmulti mode */
  1836. if (is_allmulti_enable(rxf->rxmode_pending,
  1837. rxf->rxmode_pending_bitmask)) {
  1838. /* move allmulti configuration from pending -> active */
  1839. allmulti_inactive(rxf->rxmode_pending,
  1840. rxf->rxmode_pending_bitmask);
  1841. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  1842. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1843. BNA_STATUS_T_ENABLED);
  1844. return 1;
  1845. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1846. rxf->rxmode_pending_bitmask)) {
  1847. /* move allmulti configuration from pending -> active */
  1848. allmulti_inactive(rxf->rxmode_pending,
  1849. rxf->rxmode_pending_bitmask);
  1850. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1851. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1852. BNA_STATUS_T_DISABLED);
  1853. return 1;
  1854. }
  1855. return 0;
  1856. }
  1857. int
  1858. rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
  1859. {
  1860. struct bna_mac *mac = NULL;
  1861. struct list_head *qe;
  1862. /* 1. delete pending ucast entries */
  1863. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1864. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1865. bfa_q_qe_init(qe);
  1866. mac = (struct bna_mac *)qe;
  1867. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1868. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1869. return 1;
  1870. }
  1871. /* 2. clear active ucast entries; move them to pending_add_q */
  1872. if (!list_empty(&rxf->ucast_active_q)) {
  1873. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1874. bfa_q_qe_init(qe);
  1875. mac = (struct bna_mac *)qe;
  1876. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1877. list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
  1878. return 1;
  1879. }
  1880. return 0;
  1881. }
  1882. int
  1883. rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
  1884. {
  1885. struct bna *bna = rxf->rx->bna;
  1886. /* 6. Execute pending promisc mode disable command */
  1887. if (is_promisc_disable(rxf->rxmode_pending,
  1888. rxf->rxmode_pending_bitmask)) {
  1889. /* move promisc configuration from pending -> active */
  1890. promisc_inactive(rxf->rxmode_pending,
  1891. rxf->rxmode_pending_bitmask);
  1892. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1893. bna->rxf_promisc_id = BFI_MAX_RXF;
  1894. /* Revert VLAN filter */
  1895. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1896. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1897. BNA_STATUS_T_DISABLED);
  1898. return 1;
  1899. }
  1900. /* 7. Clear active promisc mode; move it to pending enable */
  1901. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1902. /* move promisc configuration from active -> pending */
  1903. promisc_enable(rxf->rxmode_pending,
  1904. rxf->rxmode_pending_bitmask);
  1905. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1906. /* Revert VLAN filter */
  1907. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1908. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1909. BNA_STATUS_T_DISABLED);
  1910. return 1;
  1911. }
  1912. return 0;
  1913. }
  1914. int
  1915. rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
  1916. {
  1917. /* 10. Execute pending allmulti mode disable command */
  1918. if (is_allmulti_disable(rxf->rxmode_pending,
  1919. rxf->rxmode_pending_bitmask)) {
  1920. /* move allmulti configuration from pending -> active */
  1921. allmulti_inactive(rxf->rxmode_pending,
  1922. rxf->rxmode_pending_bitmask);
  1923. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1924. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1925. BNA_STATUS_T_DISABLED);
  1926. return 1;
  1927. }
  1928. /* 11. Clear active allmulti mode; move it to pending enable */
  1929. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1930. /* move allmulti configuration from active -> pending */
  1931. allmulti_enable(rxf->rxmode_pending,
  1932. rxf->rxmode_pending_bitmask);
  1933. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1934. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1935. BNA_STATUS_T_DISABLED);
  1936. return 1;
  1937. }
  1938. return 0;
  1939. }
  1940. void
  1941. rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
  1942. {
  1943. struct list_head *qe;
  1944. struct bna_mac *mac;
  1945. /* 1. Move active ucast entries to pending_add_q */
  1946. while (!list_empty(&rxf->ucast_active_q)) {
  1947. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1948. bfa_q_qe_init(qe);
  1949. list_add_tail(qe, &rxf->ucast_pending_add_q);
  1950. }
  1951. /* 2. Throw away delete pending ucast entries */
  1952. while (!list_empty(&rxf->ucast_pending_del_q)) {
  1953. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1954. bfa_q_qe_init(qe);
  1955. mac = (struct bna_mac *)qe;
  1956. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1957. }
  1958. }
  1959. void
  1960. rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
  1961. {
  1962. struct bna *bna = rxf->rx->bna;
  1963. /* 6. Clear pending promisc mode disable */
  1964. if (is_promisc_disable(rxf->rxmode_pending,
  1965. rxf->rxmode_pending_bitmask)) {
  1966. promisc_inactive(rxf->rxmode_pending,
  1967. rxf->rxmode_pending_bitmask);
  1968. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1969. bna->rxf_promisc_id = BFI_MAX_RXF;
  1970. }
  1971. /* 7. Move promisc mode config from active -> pending */
  1972. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1973. promisc_enable(rxf->rxmode_pending,
  1974. rxf->rxmode_pending_bitmask);
  1975. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1976. }
  1977. }
  1978. void
  1979. rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
  1980. {
  1981. /* 10. Clear pending allmulti mode disable */
  1982. if (is_allmulti_disable(rxf->rxmode_pending,
  1983. rxf->rxmode_pending_bitmask)) {
  1984. allmulti_inactive(rxf->rxmode_pending,
  1985. rxf->rxmode_pending_bitmask);
  1986. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1987. }
  1988. /* 11. Move allmulti mode config from active -> pending */
  1989. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1990. allmulti_enable(rxf->rxmode_pending,
  1991. rxf->rxmode_pending_bitmask);
  1992. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1993. }
  1994. }
  1995. /**
  1996. * Should only be called by bna_rxf_mode_set.
  1997. * Helps deciding if h/w configuration is needed or not.
  1998. * Returns:
  1999. * 0 = no h/w change
  2000. * 1 = need h/w change
  2001. */
  2002. static int
  2003. rxf_promisc_enable(struct bna_rxf *rxf)
  2004. {
  2005. struct bna *bna = rxf->rx->bna;
  2006. int ret = 0;
  2007. /* There can not be any pending disable command */
  2008. /* Do nothing if pending enable or already enabled */
  2009. if (is_promisc_enable(rxf->rxmode_pending,
  2010. rxf->rxmode_pending_bitmask) ||
  2011. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  2012. /* Schedule enable */
  2013. } else {
  2014. /* Promisc mode should not be active in the system */
  2015. promisc_enable(rxf->rxmode_pending,
  2016. rxf->rxmode_pending_bitmask);
  2017. bna->rxf_promisc_id = rxf->rxf_id;
  2018. ret = 1;
  2019. }
  2020. return ret;
  2021. }
  2022. /**
  2023. * Should only be called by bna_rxf_mode_set.
  2024. * Helps deciding if h/w configuration is needed or not.
  2025. * Returns:
  2026. * 0 = no h/w change
  2027. * 1 = need h/w change
  2028. */
  2029. static int
  2030. rxf_promisc_disable(struct bna_rxf *rxf)
  2031. {
  2032. struct bna *bna = rxf->rx->bna;
  2033. int ret = 0;
  2034. /* There can not be any pending disable */
  2035. /* Turn off pending enable command , if any */
  2036. if (is_promisc_enable(rxf->rxmode_pending,
  2037. rxf->rxmode_pending_bitmask)) {
  2038. /* Promisc mode should not be active */
  2039. /* system promisc state should be pending */
  2040. promisc_inactive(rxf->rxmode_pending,
  2041. rxf->rxmode_pending_bitmask);
  2042. /* Remove the promisc state from the system */
  2043. bna->rxf_promisc_id = BFI_MAX_RXF;
  2044. /* Schedule disable */
  2045. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  2046. /* Promisc mode should be active in the system */
  2047. promisc_disable(rxf->rxmode_pending,
  2048. rxf->rxmode_pending_bitmask);
  2049. ret = 1;
  2050. /* Do nothing if already disabled */
  2051. } else {
  2052. }
  2053. return ret;
  2054. }
  2055. /**
  2056. * Should only be called by bna_rxf_mode_set.
  2057. * Helps deciding if h/w configuration is needed or not.
  2058. * Returns:
  2059. * 0 = no h/w change
  2060. * 1 = need h/w change
  2061. */
  2062. static int
  2063. rxf_allmulti_enable(struct bna_rxf *rxf)
  2064. {
  2065. int ret = 0;
  2066. /* There can not be any pending disable command */
  2067. /* Do nothing if pending enable or already enabled */
  2068. if (is_allmulti_enable(rxf->rxmode_pending,
  2069. rxf->rxmode_pending_bitmask) ||
  2070. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  2071. /* Schedule enable */
  2072. } else {
  2073. allmulti_enable(rxf->rxmode_pending,
  2074. rxf->rxmode_pending_bitmask);
  2075. ret = 1;
  2076. }
  2077. return ret;
  2078. }
  2079. /**
  2080. * Should only be called by bna_rxf_mode_set.
  2081. * Helps deciding if h/w configuration is needed or not.
  2082. * Returns:
  2083. * 0 = no h/w change
  2084. * 1 = need h/w change
  2085. */
  2086. static int
  2087. rxf_allmulti_disable(struct bna_rxf *rxf)
  2088. {
  2089. int ret = 0;
  2090. /* There can not be any pending disable */
  2091. /* Turn off pending enable command , if any */
  2092. if (is_allmulti_enable(rxf->rxmode_pending,
  2093. rxf->rxmode_pending_bitmask)) {
  2094. /* Allmulti mode should not be active */
  2095. allmulti_inactive(rxf->rxmode_pending,
  2096. rxf->rxmode_pending_bitmask);
  2097. /* Schedule disable */
  2098. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  2099. allmulti_disable(rxf->rxmode_pending,
  2100. rxf->rxmode_pending_bitmask);
  2101. ret = 1;
  2102. }
  2103. return ret;
  2104. }
  2105. /* RxF <- bnad */
  2106. enum bna_cb_status
  2107. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2108. enum bna_rxmode bitmask,
  2109. void (*cbfn)(struct bnad *, struct bna_rx *,
  2110. enum bna_cb_status))
  2111. {
  2112. struct bna_rxf *rxf = &rx->rxf;
  2113. int need_hw_config = 0;
  2114. /* Process the commands */
  2115. if (is_promisc_enable(new_mode, bitmask)) {
  2116. /* If promisc mode is already enabled elsewhere in the system */
  2117. if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
  2118. (rx->bna->rxf_promisc_id != rxf->rxf_id))
  2119. goto err_return;
  2120. if (rxf_promisc_enable(rxf))
  2121. need_hw_config = 1;
  2122. } else if (is_promisc_disable(new_mode, bitmask)) {
  2123. if (rxf_promisc_disable(rxf))
  2124. need_hw_config = 1;
  2125. }
  2126. if (is_allmulti_enable(new_mode, bitmask)) {
  2127. if (rxf_allmulti_enable(rxf))
  2128. need_hw_config = 1;
  2129. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2130. if (rxf_allmulti_disable(rxf))
  2131. need_hw_config = 1;
  2132. }
  2133. /* Trigger h/w if needed */
  2134. if (need_hw_config) {
  2135. rxf->cam_fltr_cbfn = cbfn;
  2136. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2137. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2138. } else if (cbfn)
  2139. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  2140. return BNA_CB_SUCCESS;
  2141. err_return:
  2142. return BNA_CB_FAIL;
  2143. }
  2144. void
  2145. /* RxF <- bnad */
  2146. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2147. {
  2148. struct bna_rxf *rxf = &rx->rxf;
  2149. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2150. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  2151. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2152. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2153. }
  2154. }
  2155. /* Rx */
  2156. /* Rx <- bnad */
  2157. void
  2158. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2159. {
  2160. struct bna_rxp *rxp;
  2161. struct list_head *qe;
  2162. list_for_each(qe, &rx->rxp_q) {
  2163. rxp = (struct bna_rxp *)qe;
  2164. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2165. bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
  2166. }
  2167. }
  2168. /* Rx <- bnad */
  2169. void
  2170. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2171. {
  2172. int i, j;
  2173. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2174. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2175. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2176. }
  2177. /* Rx <- bnad */
  2178. void
  2179. bna_rx_dim_update(struct bna_ccb *ccb)
  2180. {
  2181. struct bna *bna = ccb->cq->rx->bna;
  2182. u32 load, bias;
  2183. u32 pkt_rt, small_rt, large_rt;
  2184. u8 coalescing_timeo;
  2185. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2186. (ccb->pkt_rate.large_pkt_cnt == 0))
  2187. return;
  2188. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2189. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2190. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2191. pkt_rt = small_rt + large_rt;
  2192. if (pkt_rt < BNA_PKT_RATE_10K)
  2193. load = BNA_LOAD_T_LOW_4;
  2194. else if (pkt_rt < BNA_PKT_RATE_20K)
  2195. load = BNA_LOAD_T_LOW_3;
  2196. else if (pkt_rt < BNA_PKT_RATE_30K)
  2197. load = BNA_LOAD_T_LOW_2;
  2198. else if (pkt_rt < BNA_PKT_RATE_40K)
  2199. load = BNA_LOAD_T_LOW_1;
  2200. else if (pkt_rt < BNA_PKT_RATE_50K)
  2201. load = BNA_LOAD_T_HIGH_1;
  2202. else if (pkt_rt < BNA_PKT_RATE_60K)
  2203. load = BNA_LOAD_T_HIGH_2;
  2204. else if (pkt_rt < BNA_PKT_RATE_80K)
  2205. load = BNA_LOAD_T_HIGH_3;
  2206. else
  2207. load = BNA_LOAD_T_HIGH_4;
  2208. if (small_rt > (large_rt << 1))
  2209. bias = 0;
  2210. else
  2211. bias = 1;
  2212. ccb->pkt_rate.small_pkt_cnt = 0;
  2213. ccb->pkt_rate.large_pkt_cnt = 0;
  2214. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2215. ccb->rx_coalescing_timeo = coalescing_timeo;
  2216. /* Set it to IB */
  2217. bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
  2218. }
  2219. /* Tx */
  2220. /* TX <- bnad */
  2221. void
  2222. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  2223. {
  2224. struct bna_txq *txq;
  2225. struct list_head *qe;
  2226. list_for_each(qe, &tx->txq_q) {
  2227. txq = (struct bna_txq *)qe;
  2228. bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
  2229. }
  2230. }
  2231. /*
  2232. * Private data
  2233. */
  2234. struct bna_ritseg_pool_cfg {
  2235. u32 pool_size;
  2236. u32 pool_entry_size;
  2237. };
  2238. init_ritseg_pool(ritseg_pool_cfg);
  2239. /*
  2240. * Private functions
  2241. */
  2242. static void
  2243. bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
  2244. struct bna_res_info *res_info)
  2245. {
  2246. int i;
  2247. ucam_mod->ucmac = (struct bna_mac *)
  2248. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2249. INIT_LIST_HEAD(&ucam_mod->free_q);
  2250. for (i = 0; i < BFI_MAX_UCMAC; i++) {
  2251. bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
  2252. list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
  2253. }
  2254. ucam_mod->bna = bna;
  2255. }
  2256. static void
  2257. bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
  2258. {
  2259. struct list_head *qe;
  2260. int i = 0;
  2261. list_for_each(qe, &ucam_mod->free_q)
  2262. i++;
  2263. ucam_mod->bna = NULL;
  2264. }
  2265. static void
  2266. bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
  2267. struct bna_res_info *res_info)
  2268. {
  2269. int i;
  2270. mcam_mod->mcmac = (struct bna_mac *)
  2271. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2272. INIT_LIST_HEAD(&mcam_mod->free_q);
  2273. for (i = 0; i < BFI_MAX_MCMAC; i++) {
  2274. bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
  2275. list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
  2276. }
  2277. mcam_mod->bna = bna;
  2278. }
  2279. static void
  2280. bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
  2281. {
  2282. struct list_head *qe;
  2283. int i = 0;
  2284. list_for_each(qe, &mcam_mod->free_q)
  2285. i++;
  2286. mcam_mod->bna = NULL;
  2287. }
  2288. static void
  2289. bna_rit_mod_init(struct bna_rit_mod *rit_mod,
  2290. struct bna_res_info *res_info)
  2291. {
  2292. int i;
  2293. int j;
  2294. int count;
  2295. int offset;
  2296. rit_mod->rit = (struct bna_rit_entry *)
  2297. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
  2298. rit_mod->rit_segment = (struct bna_rit_segment *)
  2299. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
  2300. count = 0;
  2301. offset = 0;
  2302. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2303. INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
  2304. for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
  2305. bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
  2306. rit_mod->rit_segment[count].max_rit_size =
  2307. ritseg_pool_cfg[i].pool_entry_size;
  2308. rit_mod->rit_segment[count].rit_offset = offset;
  2309. rit_mod->rit_segment[count].rit =
  2310. &rit_mod->rit[offset];
  2311. list_add_tail(&rit_mod->rit_segment[count].qe,
  2312. &rit_mod->rit_seg_pool[i]);
  2313. count++;
  2314. offset += ritseg_pool_cfg[i].pool_entry_size;
  2315. }
  2316. }
  2317. }
  2318. /*
  2319. * Public functions
  2320. */
  2321. /* Called during probe(), before calling bna_init() */
  2322. void
  2323. bna_res_req(struct bna_res_info *res_info)
  2324. {
  2325. bna_adv_res_req(res_info);
  2326. /* DMA memory for retrieving IOC attributes */
  2327. res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
  2328. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2329. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
  2330. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
  2331. ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
  2332. /* DMA memory for index segment of an IB */
  2333. res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2334. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2335. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
  2336. BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
  2337. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
  2338. /* Virtual memory for IB objects - stored by IB module */
  2339. res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
  2340. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
  2341. BNA_MEM_T_KVA;
  2342. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
  2343. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
  2344. BFI_MAX_IB * sizeof(struct bna_ib);
  2345. /* Virtual memory for intr objects - stored by IB module */
  2346. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
  2347. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
  2348. BNA_MEM_T_KVA;
  2349. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
  2350. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
  2351. BFI_MAX_IB * sizeof(struct bna_intr);
  2352. /* Virtual memory for idx_seg objects - stored by IB module */
  2353. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
  2354. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
  2355. BNA_MEM_T_KVA;
  2356. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
  2357. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
  2358. BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
  2359. /* Virtual memory for Tx objects - stored by Tx module */
  2360. res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
  2361. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
  2362. BNA_MEM_T_KVA;
  2363. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
  2364. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
  2365. BFI_MAX_TXQ * sizeof(struct bna_tx);
  2366. /* Virtual memory for TxQ - stored by Tx module */
  2367. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2368. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
  2369. BNA_MEM_T_KVA;
  2370. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
  2371. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
  2372. BFI_MAX_TXQ * sizeof(struct bna_txq);
  2373. /* Virtual memory for Rx objects - stored by Rx module */
  2374. res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
  2375. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
  2376. BNA_MEM_T_KVA;
  2377. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
  2378. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
  2379. BFI_MAX_RXQ * sizeof(struct bna_rx);
  2380. /* Virtual memory for RxPath - stored by Rx module */
  2381. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
  2382. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
  2383. BNA_MEM_T_KVA;
  2384. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
  2385. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
  2386. BFI_MAX_RXQ * sizeof(struct bna_rxp);
  2387. /* Virtual memory for RxQ - stored by Rx module */
  2388. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2389. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
  2390. BNA_MEM_T_KVA;
  2391. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
  2392. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
  2393. BFI_MAX_RXQ * sizeof(struct bna_rxq);
  2394. /* Virtual memory for Unicast MAC address - stored by ucam module */
  2395. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2396. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
  2397. BNA_MEM_T_KVA;
  2398. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
  2399. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
  2400. BFI_MAX_UCMAC * sizeof(struct bna_mac);
  2401. /* Virtual memory for Multicast MAC address - stored by mcam module */
  2402. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2403. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
  2404. BNA_MEM_T_KVA;
  2405. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
  2406. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
  2407. BFI_MAX_MCMAC * sizeof(struct bna_mac);
  2408. /* Virtual memory for RIT entries */
  2409. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
  2410. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
  2411. BNA_MEM_T_KVA;
  2412. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
  2413. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
  2414. BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
  2415. /* Virtual memory for RIT segment table */
  2416. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
  2417. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
  2418. BNA_MEM_T_KVA;
  2419. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
  2420. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
  2421. BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
  2422. /* Interrupt resource for mailbox interrupt */
  2423. res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
  2424. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
  2425. BNA_INTR_T_MSIX;
  2426. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
  2427. }
  2428. /* Called during probe() */
  2429. void
  2430. bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
  2431. struct bna_res_info *res_info)
  2432. {
  2433. bna->bnad = bnad;
  2434. bna->pcidev = *pcidev;
  2435. bna->stats.hw_stats = (struct bfi_ll_stats *)
  2436. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
  2437. bna->hw_stats_dma.msb =
  2438. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
  2439. bna->hw_stats_dma.lsb =
  2440. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
  2441. bna->stats.sw_stats = (struct bna_sw_stats *)
  2442. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
  2443. bna->regs.page_addr = bna->pcidev.pci_bar_kva +
  2444. reg_offset[bna->pcidev.pci_func].page_addr;
  2445. bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
  2446. reg_offset[bna->pcidev.pci_func].fn_int_status;
  2447. bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
  2448. reg_offset[bna->pcidev.pci_func].fn_int_mask;
  2449. if (bna->pcidev.pci_func < 3)
  2450. bna->port_num = 0;
  2451. else
  2452. bna->port_num = 1;
  2453. /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
  2454. bna_device_init(&bna->device, bna, res_info);
  2455. bna_port_init(&bna->port, bna);
  2456. bna_tx_mod_init(&bna->tx_mod, bna, res_info);
  2457. bna_rx_mod_init(&bna->rx_mod, bna, res_info);
  2458. bna_ib_mod_init(&bna->ib_mod, bna, res_info);
  2459. bna_rit_mod_init(&bna->rit_mod, res_info);
  2460. bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
  2461. bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
  2462. bna->rxf_promisc_id = BFI_MAX_RXF;
  2463. /* Mbox q element for posting stat request to f/w */
  2464. bfa_q_qe_init(&bna->mbox_qe.qe);
  2465. }
  2466. void
  2467. bna_uninit(struct bna *bna)
  2468. {
  2469. bna_mcam_mod_uninit(&bna->mcam_mod);
  2470. bna_ucam_mod_uninit(&bna->ucam_mod);
  2471. bna_ib_mod_uninit(&bna->ib_mod);
  2472. bna_rx_mod_uninit(&bna->rx_mod);
  2473. bna_tx_mod_uninit(&bna->tx_mod);
  2474. bna_port_uninit(&bna->port);
  2475. bna_device_uninit(&bna->device);
  2476. bna->bnad = NULL;
  2477. }
  2478. struct bna_mac *
  2479. bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
  2480. {
  2481. struct list_head *qe;
  2482. if (list_empty(&ucam_mod->free_q))
  2483. return NULL;
  2484. bfa_q_deq(&ucam_mod->free_q, &qe);
  2485. return (struct bna_mac *)qe;
  2486. }
  2487. void
  2488. bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
  2489. {
  2490. list_add_tail(&mac->qe, &ucam_mod->free_q);
  2491. }
  2492. struct bna_mac *
  2493. bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
  2494. {
  2495. struct list_head *qe;
  2496. if (list_empty(&mcam_mod->free_q))
  2497. return NULL;
  2498. bfa_q_deq(&mcam_mod->free_q, &qe);
  2499. return (struct bna_mac *)qe;
  2500. }
  2501. void
  2502. bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
  2503. {
  2504. list_add_tail(&mac->qe, &mcam_mod->free_q);
  2505. }
  2506. /**
  2507. * Note: This should be called in the same locking context as the call to
  2508. * bna_rit_mod_seg_get()
  2509. */
  2510. int
  2511. bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
  2512. {
  2513. int i;
  2514. /* Select the pool for seg_size */
  2515. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2516. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2517. break;
  2518. }
  2519. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2520. return 0;
  2521. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2522. return 0;
  2523. return 1;
  2524. }
  2525. struct bna_rit_segment *
  2526. bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
  2527. {
  2528. struct bna_rit_segment *seg;
  2529. struct list_head *qe;
  2530. int i;
  2531. /* Select the pool for seg_size */
  2532. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2533. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2534. break;
  2535. }
  2536. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2537. return NULL;
  2538. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2539. return NULL;
  2540. bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
  2541. seg = (struct bna_rit_segment *)qe;
  2542. bfa_q_qe_init(&seg->qe);
  2543. seg->rit_size = seg_size;
  2544. return seg;
  2545. }
  2546. void
  2547. bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
  2548. struct bna_rit_segment *seg)
  2549. {
  2550. int i;
  2551. /* Select the pool for seg->max_rit_size */
  2552. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2553. if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
  2554. break;
  2555. }
  2556. seg->rit_size = 0;
  2557. list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
  2558. }