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/drivers/media/video/cx231xx/cx231xx-avcore.c

https://bitbucket.org/ndreys/linux-sunxi
C | 3119 lines | 2267 code | 459 blank | 393 comment | 238 complexity | 22a07687d37e45e6dbe4313587beed1e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0 
    

  1. /*
    2. 

  2.    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
    3. 

  3. 		      USB video capture devices
    4. 

    5. 

  5.    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
    6. 

    7. 

  7.    This program contains the specific code to control the avdecoder chip and
    8. 

  8.    other related usb control functions for cx231xx based chipset.
    9. 

    10. 

  10.    This program is free software; you can redistribute it and/or modify
    11. 

  11.    it under the terms of the GNU General Public License as published by
    12. 

  12.    the Free Software Foundation; either version 2 of the License, or
    13. 

  13.    (at your option) any later version.
    14. 

    15. 

  15.    This program is distributed in the hope that it will be useful,
    16. 

  16.    but WITHOUT ANY WARRANTY; without even the implied warranty of
    17. 

  17.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18. 

  18.    GNU General Public License for more details.
    19. 

    20. 

  20.    You should have received a copy of the GNU General Public License
    21. 

  21.    along with this program; if not, write to the Free Software
    22. 

  22.    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
    23. 

  23.  */
    24. 

  24. 

  25. #include <linux/init.h>
    26. 

  26. #include <linux/list.h>
    27. 

  27. #include <linux/module.h>
    28. 

  28. #include <linux/kernel.h>
    29. 

  29. #include <linux/bitmap.h>
    30. 

  30. #include <linux/usb.h>
    31. 

  31. #include <linux/i2c.h>
    32. 

  32. #include <linux/mm.h>
    33. 

  33. #include <linux/mutex.h>
    34. 

  34. #include <media/tuner.h>
    35. 

  35. 

  36. #include <media/v4l2-common.h>
    37. 

  37. #include <media/v4l2-ioctl.h>
    38. 

  38. #include <media/v4l2-chip-ident.h>
    39. 

  39. 

  40. #include "cx231xx.h"
    41. 

  41. #include "cx231xx-dif.h"
    42. 

  42. 

  43. #define TUNER_MODE_FM_RADIO 0
    44. 

  44. /******************************************************************************
    45. 

  45. 			-: BLOCK ARRANGEMENT :-
    46. 

  46. 	I2S block ----------------------|
    47. 

  47. 	[I2S audio]			|
    48. 

  48. 					|
    49. 

  49. 	Analog Front End --> Direct IF -|-> Cx25840 --> Audio
    50. 

  50. 	[video & audio]			|   [Audio]
    51. 

  51. 					|
    52. 

  52. 					|-> Cx25840 --> Video
    53. 

  53. 					    [Video]
    54. 

    55. 

  55. *******************************************************************************/
    56. 

  56. /******************************************************************************
    57. 

  57.  *                    VERVE REGISTER                                          *
    58. 

  58.  *									      *
    59. 

  59.  ******************************************************************************/
    60. 

  60. static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
    61. 

  61. {
    62. 

  62. 	return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
    63. 

  63. 					saddr, 1, data, 1);
    64. 

  64. }
    65. 

  65. 

  66. static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
    67. 

  67. {
    68. 

  68. 	int status;
    69. 

  69. 	u32 temp = 0;
    70. 

  70. 

  71. 	status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
    72. 

  72. 					saddr, 1, &temp, 1);
    73. 

  73. 	*data = (u8) temp;
    74. 

  74. 	return status;
    75. 

  75. }
    76. 

  76. void initGPIO(struct cx231xx *dev)
    77. 

  77. {
    78. 

  78. 	u32 _gpio_direction = 0;
    79. 

  79. 	u32 value = 0;
    80. 

  80. 	u8 val = 0;
    81. 

  81. 

  82. 	_gpio_direction = _gpio_direction & 0xFC0003FF;
    83. 

  83. 	_gpio_direction = _gpio_direction | 0x03FDFC00;
    84. 

  84. 	cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
    85. 

  85. 

  86. 	verve_read_byte(dev, 0x07, &val);
    87. 

  87. 	cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
    88. 

  88. 	verve_write_byte(dev, 0x07, 0xF4);
    89. 

  89. 	verve_read_byte(dev, 0x07, &val);
    90. 

  90. 	cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
    91. 

  91. 

  92. 	cx231xx_capture_start(dev, 1, 2);
    93. 

  93. 

  94. 	cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
    95. 

  95. 	cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
    96. 

  96. 

  97. }
    98. 

  98. void uninitGPIO(struct cx231xx *dev)
    99. 

  99. {
    100. 

  100. 	u8 value[4] = { 0, 0, 0, 0 };
    101. 

  101. 

  102. 	cx231xx_capture_start(dev, 0, 2);
    103. 

  103. 	verve_write_byte(dev, 0x07, 0x14);
    104. 

  104. 	cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    105. 

  105. 			0x68, value, 4);
    106. 

  106. }
    107. 

  107. 

  108. /******************************************************************************
    109. 

  109.  *                    A F E - B L O C K    C O N T R O L   functions          *
    110. 

  110.  * 				[ANALOG FRONT END]			      *
    111. 

  111.  ******************************************************************************/
    112. 

  112. static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
    113. 

  113. {
    114. 

  114. 	return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
    115. 

  115. 					saddr, 2, data, 1);
    116. 

  116. }
    117. 

  117. 

  118. static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
    119. 

  119. {
    120. 

  120. 	int status;
    121. 

  121. 	u32 temp = 0;
    122. 

  122. 

  123. 	status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
    124. 

  124. 					saddr, 2, &temp, 1);
    125. 

  125. 	*data = (u8) temp;
    126. 

  126. 	return status;
    127. 

  127. }
    128. 

  128. 

  129. int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
    130. 

  130. {
    131. 

  131. 	int status = 0;
    132. 

  132. 	u8 temp = 0;
    133. 

  133. 	u8 afe_power_status = 0;
    134. 

  134. 	int i = 0;
    135. 

  135. 

  136. 	/* super block initialize */
    137. 

  137. 	temp = (u8) (ref_count & 0xff);
    138. 

  138. 	status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
    139. 

  139. 	if (status < 0)
    140. 

  140. 		return status;
    141. 

  141. 

  142. 	status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
    143. 

  143. 	if (status < 0)
    144. 

  144. 		return status;
    145. 

  145. 

  146. 	temp = (u8) ((ref_count & 0x300) >> 8);
    147. 

  147. 	temp |= 0x40;
    148. 

  148. 	status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
    149. 

  149. 	if (status < 0)
    150. 

  150. 		return status;
    151. 

  151. 

  152. 	status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
    153. 

  153. 	if (status < 0)
    154. 

  154. 		return status;
    155. 

  155. 

  156. 	/* enable pll     */
    157. 

  157. 	while (afe_power_status != 0x18) {
    158. 

  158. 		status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
    159. 

  159. 		if (status < 0) {
    160. 

  160. 			cx231xx_info(
    161. 

  161. 			": Init Super Block failed in send cmd\n");
    162. 

  162. 			break;
    163. 

  163. 		}
    164. 

  164. 

  165. 		status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
    166. 

  166. 		afe_power_status &= 0xff;
    167. 

  167. 		if (status < 0) {
    168. 

  168. 			cx231xx_info(
    169. 

  169. 			": Init Super Block failed in receive cmd\n");
    170. 

  170. 			break;
    171. 

  171. 		}
    172. 

  172. 		i++;
    173. 

  173. 		if (i == 10) {
    174. 

  174. 			cx231xx_info(
    175. 

  175. 			": Init Super Block force break in loop !!!!\n");
    176. 

  176. 			status = -1;
    177. 

  177. 			break;
    178. 

  178. 		}
    179. 

  179. 	}
    180. 

  180. 

  181. 	if (status < 0)
    182. 

  182. 		return status;
    183. 

  183. 

  184. 	/* start tuning filter */
    185. 

  185. 	status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
    186. 

  186. 	if (status < 0)
    187. 

  187. 		return status;
    188. 

  188. 

  189. 	msleep(5);
    190. 

  190. 

  191. 	/* exit tuning */
    192. 

  192. 	status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
    193. 

  193. 

  194. 	return status;
    195. 

  195. }
    196. 

  196. 

  197. int cx231xx_afe_init_channels(struct cx231xx *dev)
    198. 

  198. {
    199. 

  199. 	int status = 0;
    200. 

  200. 

  201. 	/* power up all 3 channels, clear pd_buffer */
    202. 

  202. 	status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
    203. 

  203. 	status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
    204. 

  204. 	status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
    205. 

  205. 

  206. 	/* Enable quantizer calibration */
    207. 

  207. 	status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
    208. 

  208. 

  209. 	/* channel initialize, force modulator (fb) reset */
    210. 

  210. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
    211. 

  211. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
    212. 

  212. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
    213. 

  213. 

  214. 	/* start quantilizer calibration  */
    215. 

  215. 	status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
    216. 

  216. 	status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
    217. 

  217. 	status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
    218. 

  218. 	msleep(5);
    219. 

  219. 

  220. 	/* exit modulator (fb) reset */
    221. 

  221. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
    222. 

  222. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
    223. 

  223. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
    224. 

  224. 

  225. 	/* enable the pre_clamp in each channel for single-ended input */
    226. 

  226. 	status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
    227. 

  227. 	status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
    228. 

  228. 	status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
    229. 

  229. 

  230. 	/* use diode instead of resistor, so set term_en to 0, res_en to 0  */
    231. 

  231. 	status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
    232. 

  232. 				   ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
    233. 

  233. 	status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
    234. 

  234. 				   ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
    235. 

  235. 	status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
    236. 

  236. 				   ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
    237. 

  237. 

  238. 	/* dynamic element matching off */
    239. 

  239. 	status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
    240. 

  240. 	status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
    241. 

  241. 	status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
    242. 

  242. 

  243. 	return status;
    244. 

  244. }
    245. 

  245. 

  246. int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
    247. 

  247. {
    248. 

  248. 	u8 c_value = 0;
    249. 

  249. 	int status = 0;
    250. 

  250. 

  251. 	status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
    252. 

  252. 	c_value &= (~(0x50));
    253. 

  253. 	status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
    254. 

  254. 

  255. 	return status;
    256. 

  256. }
    257. 

  257. 

  258. /*
    259. 

  259. 	The Analog Front End in Cx231xx has 3 channels. These
    260. 

  260. 	channels are used to share between different inputs
    261. 

  261. 	like tuner, s-video and composite inputs.
    262. 

    263. 

  263. 	channel 1 ----- pin 1  to pin4(in reg is 1-4)
    264. 

  264. 	channel 2 ----- pin 5  to pin8(in reg is 5-8)
    265. 

  265. 	channel 3 ----- pin 9 to pin 12(in reg is 9-11)
    266. 

  266. */
    267. 

  267. int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
    268. 

  268. {
    269. 

  269. 	u8 ch1_setting = (u8) input_mux;
    270. 

  270. 	u8 ch2_setting = (u8) (input_mux >> 8);
    271. 

  271. 	u8 ch3_setting = (u8) (input_mux >> 16);
    272. 

  272. 	int status = 0;
    273. 

  273. 	u8 value = 0;
    274. 

  274. 

  275. 	if (ch1_setting != 0) {
    276. 

  276. 		status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
    277. 

  277. 		value &= ~INPUT_SEL_MASK;
    278. 

  278. 		value |= (ch1_setting - 1) << 4;
    279. 

  279. 		value &= 0xff;
    280. 

  280. 		status = afe_write_byte(dev, ADC_INPUT_CH1, value);
    281. 

  281. 	}
    282. 

  282. 

  283. 	if (ch2_setting != 0) {
    284. 

  284. 		status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
    285. 

  285. 		value &= ~INPUT_SEL_MASK;
    286. 

  286. 		value |= (ch2_setting - 1) << 4;
    287. 

  287. 		value &= 0xff;
    288. 

  288. 		status = afe_write_byte(dev, ADC_INPUT_CH2, value);
    289. 

  289. 	}
    290. 

  290. 

  291. 	/* For ch3_setting, the value to put in the register is
    292. 

  292. 	   7 less than the input number */
    293. 

  293. 	if (ch3_setting != 0) {
    294. 

  294. 		status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
    295. 

  295. 		value &= ~INPUT_SEL_MASK;
    296. 

  296. 		value |= (ch3_setting - 1) << 4;
    297. 

  297. 		value &= 0xff;
    298. 

  298. 		status = afe_write_byte(dev, ADC_INPUT_CH3, value);
    299. 

  299. 	}
    300. 

  300. 

  301. 	return status;
    302. 

  302. }
    303. 

  303. 

  304. int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
    305. 

  305. {
    306. 

  306. 	int status = 0;
    307. 

  307. 

  308. 	/*
    309. 

  309. 	* FIXME: We need to implement the AFE code for LOW IF and for HI IF.
    310. 

  310. 	* Currently, only baseband works.
    311. 

  311. 	*/
    312. 

  312. 

  313. 	switch (mode) {
    314. 

  314. 	case AFE_MODE_LOW_IF:
    315. 

  315. 		cx231xx_Setup_AFE_for_LowIF(dev);
    316. 

  316. 		break;
    317. 

  317. 	case AFE_MODE_BASEBAND:
    318. 

  318. 		status = cx231xx_afe_setup_AFE_for_baseband(dev);
    319. 

  319. 		break;
    320. 

  320. 	case AFE_MODE_EU_HI_IF:
    321. 

  321. 		/* SetupAFEforEuHiIF(); */
    322. 

  322. 		break;
    323. 

  323. 	case AFE_MODE_US_HI_IF:
    324. 

  324. 		/* SetupAFEforUsHiIF(); */
    325. 

  325. 		break;
    326. 

  326. 	case AFE_MODE_JAPAN_HI_IF:
    327. 

  327. 		/* SetupAFEforJapanHiIF(); */
    328. 

  328. 		break;
    329. 

  329. 	}
    330. 

  330. 

  331. 	if ((mode != dev->afe_mode) &&
    332. 

  332. 		(dev->video_input == CX231XX_VMUX_TELEVISION))
    333. 

  333. 		status = cx231xx_afe_adjust_ref_count(dev,
    334. 

  334. 						     CX231XX_VMUX_TELEVISION);
    335. 

  335. 

  336. 	dev->afe_mode = mode;
    337. 

  337. 

  338. 	return status;
    339. 

  339. }
    340. 

  340. 

  341. int cx231xx_afe_update_power_control(struct cx231xx *dev,
    342. 

  342. 					enum AV_MODE avmode)
    343. 

  343. {
    344. 

  344. 	u8 afe_power_status = 0;
    345. 

  345. 	int status = 0;
    346. 

  346. 

  347. 	switch (dev->model) {
    348. 

  348. 	case CX231XX_BOARD_CNXT_CARRAERA:
    349. 

  349. 	case CX231XX_BOARD_CNXT_RDE_250:
    350. 

  350. 	case CX231XX_BOARD_CNXT_SHELBY:
    351. 

  351. 	case CX231XX_BOARD_CNXT_RDU_250:
    352. 

  352. 	case CX231XX_BOARD_CNXT_RDE_253S:
    353. 

  353. 	case CX231XX_BOARD_CNXT_RDU_253S:
    354. 

  354. 	case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
    355. 

  355. 	case CX231XX_BOARD_HAUPPAUGE_EXETER:
    356. 

  356. 	case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
    357. 

  357. 	case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
    358. 

  358. 		if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
    359. 

  359. 			while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
    360. 

  360. 						FLD_PWRDN_ENABLE_PLL)) {
    361. 

  361. 				status = afe_write_byte(dev, SUP_BLK_PWRDN,
    362. 

  362. 							FLD_PWRDN_TUNING_BIAS |
    363. 

  363. 							FLD_PWRDN_ENABLE_PLL);
    364. 

  364. 				status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    365. 

  365. 							&afe_power_status);
    366. 

  366. 				if (status < 0)
    367. 

  367. 					break;
    368. 

  368. 			}
    369. 

  369. 

  370. 			status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    371. 

  371. 							0x00);
    372. 

  372. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    373. 

  373. 							0x00);
    374. 

  374. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    375. 

  375. 							0x00);
    376. 

  376. 		} else if (avmode == POLARIS_AVMODE_DIGITAL) {
    377. 

  377. 			status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    378. 

  378. 							0x70);
    379. 

  379. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    380. 

  380. 							0x70);
    381. 

  381. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    382. 

  382. 							0x70);
    383. 

  383. 

  384. 			status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    385. 

  385. 						  &afe_power_status);
    386. 

  386. 			afe_power_status |= FLD_PWRDN_PD_BANDGAP |
    387. 

  387. 						FLD_PWRDN_PD_BIAS |
    388. 

  388. 						FLD_PWRDN_PD_TUNECK;
    389. 

  389. 			status |= afe_write_byte(dev, SUP_BLK_PWRDN,
    390. 

  390. 						   afe_power_status);
    391. 

  391. 		} else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
    392. 

  392. 			while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
    393. 

  393. 						FLD_PWRDN_ENABLE_PLL)) {
    394. 

  394. 				status = afe_write_byte(dev, SUP_BLK_PWRDN,
    395. 

  395. 							FLD_PWRDN_TUNING_BIAS |
    396. 

  396. 							FLD_PWRDN_ENABLE_PLL);
    397. 

  397. 				status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    398. 

  398. 							&afe_power_status);
    399. 

  399. 				if (status < 0)
    400. 

  400. 					break;
    401. 

  401. 			}
    402. 

  402. 

  403. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    404. 

  404. 						0x00);
    405. 

  405. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    406. 

  406. 						0x00);
    407. 

  407. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    408. 

  408. 						0x00);
    409. 

  409. 		} else {
    410. 

  410. 			cx231xx_info("Invalid AV mode input\n");
    411. 

  411. 			status = -1;
    412. 

  412. 		}
    413. 

  413. 		break;
    414. 

  414. 	default:
    415. 

  415. 		if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
    416. 

  416. 			while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
    417. 

  417. 						FLD_PWRDN_ENABLE_PLL)) {
    418. 

  418. 				status = afe_write_byte(dev, SUP_BLK_PWRDN,
    419. 

  419. 							FLD_PWRDN_TUNING_BIAS |
    420. 

  420. 							FLD_PWRDN_ENABLE_PLL);
    421. 

  421. 				status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    422. 

  422. 							&afe_power_status);
    423. 

  423. 				if (status < 0)
    424. 

  424. 					break;
    425. 

  425. 			}
    426. 

  426. 

  427. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    428. 

  428. 							0x40);
    429. 

  429. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    430. 

  430. 							0x40);
    431. 

  431. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    432. 

  432. 							0x00);
    433. 

  433. 		} else if (avmode == POLARIS_AVMODE_DIGITAL) {
    434. 

  434. 			status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    435. 

  435. 							0x70);
    436. 

  436. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    437. 

  437. 							0x70);
    438. 

  438. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    439. 

  439. 							0x70);
    440. 

  440. 

  441. 			status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    442. 

  442. 						       &afe_power_status);
    443. 

  443. 			afe_power_status |= FLD_PWRDN_PD_BANDGAP |
    444. 

  444. 						FLD_PWRDN_PD_BIAS |
    445. 

  445. 						FLD_PWRDN_PD_TUNECK;
    446. 

  446. 			status |= afe_write_byte(dev, SUP_BLK_PWRDN,
    447. 

  447. 							afe_power_status);
    448. 

  448. 		} else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
    449. 

  449. 			while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
    450. 

  450. 						FLD_PWRDN_ENABLE_PLL)) {
    451. 

  451. 				status = afe_write_byte(dev, SUP_BLK_PWRDN,
    452. 

  452. 							FLD_PWRDN_TUNING_BIAS |
    453. 

  453. 							FLD_PWRDN_ENABLE_PLL);
    454. 

  454. 				status |= afe_read_byte(dev, SUP_BLK_PWRDN,
    455. 

  455. 							&afe_power_status);
    456. 

  456. 				if (status < 0)
    457. 

  457. 					break;
    458. 

  458. 			}
    459. 

  459. 

  460. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
    461. 

  461. 							0x00);
    462. 

  462. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
    463. 

  463. 							0x00);
    464. 

  464. 			status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
    465. 

  465. 							0x40);
    466. 

  466. 		} else {
    467. 

  467. 			cx231xx_info("Invalid AV mode input\n");
    468. 

  468. 			status = -1;
    469. 

  469. 		}
    470. 

  470. 	}			/* switch  */
    471. 

  471. 

  472. 	return status;
    473. 

  473. }
    474. 

  474. 

  475. int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
    476. 

  476. {
    477. 

  477. 	u8 input_mode = 0;
    478. 

  478. 	u8 ntf_mode = 0;
    479. 

  479. 	int status = 0;
    480. 

  480. 

  481. 	dev->video_input = video_input;
    482. 

  482. 

  483. 	if (video_input == CX231XX_VMUX_TELEVISION) {
    484. 

  484. 		status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
    485. 

  485. 		status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
    486. 

  486. 					&ntf_mode);
    487. 

  487. 	} else {
    488. 

  488. 		status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
    489. 

  489. 		status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
    490. 

  490. 					&ntf_mode);
    491. 

  491. 	}
    492. 

  492. 

  493. 	input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
    494. 

  494. 

  495. 	switch (input_mode) {
    496. 

  496. 	case SINGLE_ENDED:
    497. 

  497. 		dev->afe_ref_count = 0x23C;
    498. 

  498. 		break;
    499. 

  499. 	case LOW_IF:
    500. 

  500. 		dev->afe_ref_count = 0x24C;
    501. 

  501. 		break;
    502. 

  502. 	case EU_IF:
    503. 

  503. 		dev->afe_ref_count = 0x258;
    504. 

  504. 		break;
    505. 

  505. 	case US_IF:
    506. 

  506. 		dev->afe_ref_count = 0x260;
    507. 

  507. 		break;
    508. 

  508. 	default:
    509. 

  509. 		break;
    510. 

  510. 	}
    511. 

  511. 

  512. 	status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
    513. 

  513. 

  514. 	return status;
    515. 

  515. }
    516. 

  516. 

  517. /******************************************************************************
    518. 

  518.  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
    519. 

  519.  ******************************************************************************/
    520. 

  520. static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
    521. 

  521. {
    522. 

  522. 	return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
    523. 

  523. 					saddr, 2, data, 1);
    524. 

  524. }
    525. 

  525. 

  526. static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
    527. 

  527. {
    528. 

  528. 	int status;
    529. 

  529. 	u32 temp = 0;
    530. 

  530. 

  531. 	status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
    532. 

  532. 					saddr, 2, &temp, 1);
    533. 

  533. 	*data = (u8) temp;
    534. 

  534. 	return status;
    535. 

  535. }
    536. 

  536. 

  537. static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
    538. 

  538. {
    539. 

  539. 	return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
    540. 

  540. 					saddr, 2, data, 4);
    541. 

  541. }
    542. 

  542. 

  543. static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
    544. 

  544. {
    545. 

  545. 	return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
    546. 

  546. 					saddr, 2, data, 4);
    547. 

  547. }
    548. 

  548. int cx231xx_check_fw(struct cx231xx *dev)
    549. 

  549. {
    550. 

  550. 	u8 temp = 0;
    551. 

  551. 	int status = 0;
    552. 

  552. 	status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
    553. 

  553. 	if (status < 0)
    554. 

  554. 		return status;
    555. 

  555. 	else
    556. 

  556. 		return temp;
    557. 

  557. 

  558. }
    559. 

  559. 

  560. int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
    561. 

  561. {
    562. 

  562. 	int status = 0;
    563. 

  563. 

  564. 	switch (INPUT(input)->type) {
    565. 

  565. 	case CX231XX_VMUX_COMPOSITE1:
    566. 

  566. 	case CX231XX_VMUX_SVIDEO:
    567. 

  567. 		if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
    568. 

  568. 		    (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
    569. 

  569. 			/* External AV */
    570. 

  570. 			status = cx231xx_set_power_mode(dev,
    571. 

  571. 					POLARIS_AVMODE_ENXTERNAL_AV);
    572. 

  572. 			if (status < 0) {
    573. 

  573. 				cx231xx_errdev("%s: set_power_mode : Failed to"
    574. 

  574. 						" set Power - errCode [%d]!\n",
    575. 

  575. 						__func__, status);
    576. 

  576. 				return status;
    577. 

  577. 			}
    578. 

  578. 		}
    579. 

  579. 		status = cx231xx_set_decoder_video_input(dev,
    580. 

  580. 							 INPUT(input)->type,
    581. 

  581. 							 INPUT(input)->vmux);
    582. 

  582. 		break;
    583. 

  583. 	case CX231XX_VMUX_TELEVISION:
    584. 

  584. 	case CX231XX_VMUX_CABLE:
    585. 

  585. 		if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
    586. 

  586. 		    (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
    587. 

  587. 			/* Tuner */
    588. 

  588. 			status = cx231xx_set_power_mode(dev,
    589. 

  589. 						POLARIS_AVMODE_ANALOGT_TV);
    590. 

  590. 			if (status < 0) {
    591. 

  591. 				cx231xx_errdev("%s: set_power_mode:Failed"
    592. 

  592. 					" to set Power - errCode [%d]!\n",
    593. 

  593. 					__func__, status);
    594. 

  594. 				return status;
    595. 

  595. 			}
    596. 

  596. 		}
    597. 

  597. 		if (dev->tuner_type == TUNER_NXP_TDA18271)
    598. 

  598. 			status = cx231xx_set_decoder_video_input(dev,
    599. 

  599. 							CX231XX_VMUX_TELEVISION,
    600. 

  600. 							INPUT(input)->vmux);
    601. 

  601. 		else
    602. 

  602. 			status = cx231xx_set_decoder_video_input(dev,
    603. 

  603. 							CX231XX_VMUX_COMPOSITE1,
    604. 

  604. 							INPUT(input)->vmux);
    605. 

  605. 

  606. 		break;
    607. 

  607. 	default:
    608. 

  608. 		cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
    609. 

  609. 		     __func__, INPUT(input)->type);
    610. 

  610. 		break;
    611. 

  611. 	}
    612. 

  612. 

  613. 	/* save the selection */
    614. 

  614. 	dev->video_input = input;
    615. 

  615. 

  616. 	return status;
    617. 

  617. }
    618. 

  618. 

  619. int cx231xx_set_decoder_video_input(struct cx231xx *dev,
    620. 

  620. 				u8 pin_type, u8 input)
    621. 

  621. {
    622. 

  622. 	int status = 0;
    623. 

  623. 	u32 value = 0;
    624. 

  624. 

  625. 	if (pin_type != dev->video_input) {
    626. 

  626. 		status = cx231xx_afe_adjust_ref_count(dev, pin_type);
    627. 

  627. 		if (status < 0) {
    628. 

  628. 			cx231xx_errdev("%s: adjust_ref_count :Failed to set"
    629. 

  629. 				"AFE input mux - errCode [%d]!\n",
    630. 

  630. 				__func__, status);
    631. 

  631. 			return status;
    632. 

  632. 		}
    633. 

  633. 	}
    634. 

  634. 

  635. 	/* call afe block to set video inputs */
    636. 

  636. 	status = cx231xx_afe_set_input_mux(dev, input);
    637. 

  637. 	if (status < 0) {
    638. 

  638. 		cx231xx_errdev("%s: set_input_mux :Failed to set"
    639. 

  639. 				" AFE input mux - errCode [%d]!\n",
    640. 

  640. 				__func__, status);
    641. 

  641. 		return status;
    642. 

  642. 	}
    643. 

  643. 

  644. 	switch (pin_type) {
    645. 

  645. 	case CX231XX_VMUX_COMPOSITE1:
    646. 

  646. 		status = vid_blk_read_word(dev, AFE_CTRL, &value);
    647. 

  647. 		value |= (0 << 13) | (1 << 4);
    648. 

  648. 		value &= ~(1 << 5);
    649. 

  649. 

  650. 		/* set [24:23] [22:15] to 0  */
    651. 

  651. 		value &= (~(0x1ff8000));
    652. 

  652. 		/* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
    653. 

  653. 		value |= 0x1000000;
    654. 

  654. 		status = vid_blk_write_word(dev, AFE_CTRL, value);
    655. 

  655. 

  656. 		status = vid_blk_read_word(dev, OUT_CTRL1, &value);
    657. 

  657. 		value |= (1 << 7);
    658. 

  658. 		status = vid_blk_write_word(dev, OUT_CTRL1, value);
    659. 

  659. 

  660. 		/* Set output mode */
    661. 

  661. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    662. 

  662. 							VID_BLK_I2C_ADDRESS,
    663. 

  663. 							OUT_CTRL1,
    664. 

  664. 							FLD_OUT_MODE,
    665. 

  665. 							dev->board.output_mode);
    666. 

  666. 

  667. 		/* Tell DIF object to go to baseband mode  */
    668. 

  668. 		status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
    669. 

  669. 		if (status < 0) {
    670. 

  670. 			cx231xx_errdev("%s: cx231xx_dif set to By pass"
    671. 

  671. 						   " mode- errCode [%d]!\n",
    672. 

  672. 				__func__, status);
    673. 

  673. 			return status;
    674. 

  674. 		}
    675. 

  675. 

  676. 		/* Read the DFE_CTRL1 register */
    677. 

  677. 		status = vid_blk_read_word(dev, DFE_CTRL1, &value);
    678. 

  678. 

  679. 		/* enable the VBI_GATE_EN */
    680. 

  680. 		value |= FLD_VBI_GATE_EN;
    681. 

  681. 

  682. 		/* Enable the auto-VGA enable */
    683. 

  683. 		value |= FLD_VGA_AUTO_EN;
    684. 

  684. 

  685. 		/* Write it back */
    686. 

  686. 		status = vid_blk_write_word(dev, DFE_CTRL1, value);
    687. 

  687. 

  688. 		/* Disable auto config of registers */
    689. 

  689. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    690. 

  690. 					VID_BLK_I2C_ADDRESS,
    691. 

  691. 					MODE_CTRL, FLD_ACFG_DIS,
    692. 

  692. 					cx231xx_set_field(FLD_ACFG_DIS, 1));
    693. 

  693. 

  694. 		/* Set CVBS input mode */
    695. 

  695. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    696. 

  696. 			VID_BLK_I2C_ADDRESS,
    697. 

  697. 			MODE_CTRL, FLD_INPUT_MODE,
    698. 

  698. 			cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
    699. 

  699. 		break;
    700. 

  700. 	case CX231XX_VMUX_SVIDEO:
    701. 

  701. 		/* Disable the use of  DIF */
    702. 

  702. 

  703. 		status = vid_blk_read_word(dev, AFE_CTRL, &value);
    704. 

  704. 

  705. 		/* set [24:23] [22:15] to 0 */
    706. 

  706. 		value &= (~(0x1ff8000));
    707. 

  707. 		/* set FUNC_MODE[24:23] = 2
    708. 

  708. 		IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
    709. 

  709. 		value |= 0x1000010;
    710. 

  710. 		status = vid_blk_write_word(dev, AFE_CTRL, value);
    711. 

  711. 

  712. 		/* Tell DIF object to go to baseband mode */
    713. 

  713. 		status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
    714. 

  714. 		if (status < 0) {
    715. 

  715. 			cx231xx_errdev("%s: cx231xx_dif set to By pass"
    716. 

  716. 						   " mode- errCode [%d]!\n",
    717. 

  717. 				__func__, status);
    718. 

  718. 			return status;
    719. 

  719. 		}
    720. 

  720. 

  721. 		/* Read the DFE_CTRL1 register */
    722. 

  722. 		status = vid_blk_read_word(dev, DFE_CTRL1, &value);
    723. 

  723. 

  724. 		/* enable the VBI_GATE_EN */
    725. 

  725. 		value |= FLD_VBI_GATE_EN;
    726. 

  726. 

  727. 		/* Enable the auto-VGA enable */
    728. 

  728. 		value |= FLD_VGA_AUTO_EN;
    729. 

  729. 

  730. 		/* Write it back */
    731. 

  731. 		status = vid_blk_write_word(dev, DFE_CTRL1, value);
    732. 

  732. 

  733. 		/* Disable auto config of registers  */
    734. 

  734. 		status =  cx231xx_read_modify_write_i2c_dword(dev,
    735. 

  735. 					VID_BLK_I2C_ADDRESS,
    736. 

  736. 					MODE_CTRL, FLD_ACFG_DIS,
    737. 

  737. 					cx231xx_set_field(FLD_ACFG_DIS, 1));
    738. 

  738. 

  739. 		/* Set YC input mode */
    740. 

  740. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    741. 

  741. 			VID_BLK_I2C_ADDRESS,
    742. 

  742. 			MODE_CTRL,
    743. 

  743. 			FLD_INPUT_MODE,
    744. 

  744. 			cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
    745. 

  745. 

  746. 		/* Chroma to ADC2 */
    747. 

  747. 		status = vid_blk_read_word(dev, AFE_CTRL, &value);
    748. 

  748. 		value |= FLD_CHROMA_IN_SEL;	/* set the chroma in select */
    749. 

  749. 

  750. 		/* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
    751. 

  751. 		   This sets them to use video
    752. 

  752. 		   rather than audio.  Only one of the two will be in use. */
    753. 

  753. 		value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
    754. 

  754. 

  755. 		status = vid_blk_write_word(dev, AFE_CTRL, value);
    756. 

  756. 

  757. 		status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
    758. 

  758. 		break;
    759. 

  759. 	case CX231XX_VMUX_TELEVISION:
    760. 

  760. 	case CX231XX_VMUX_CABLE:
    761. 

  761. 	default:
    762. 

  762. 		/* TODO: Test if this is also needed for xc2028/xc3028 */
    763. 

  763. 		if (dev->board.tuner_type == TUNER_XC5000) {
    764. 

  764. 			/* Disable the use of  DIF   */
    765. 

  765. 

  766. 			status = vid_blk_read_word(dev, AFE_CTRL, &value);
    767. 

  767. 			value |= (0 << 13) | (1 << 4);
    768. 

  768. 			value &= ~(1 << 5);
    769. 

  769. 

  770. 			/* set [24:23] [22:15] to 0 */
    771. 

  771. 			value &= (~(0x1FF8000));
    772. 

  772. 			/* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
    773. 

  773. 			value |= 0x1000000;
    774. 

  774. 			status = vid_blk_write_word(dev, AFE_CTRL, value);
    775. 

  775. 

  776. 			status = vid_blk_read_word(dev, OUT_CTRL1, &value);
    777. 

  777. 			value |= (1 << 7);
    778. 

  778. 			status = vid_blk_write_word(dev, OUT_CTRL1, value);
    779. 

  779. 

  780. 			/* Set output mode */
    781. 

  781. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    782. 

  782. 							VID_BLK_I2C_ADDRESS,
    783. 

  783. 							OUT_CTRL1, FLD_OUT_MODE,
    784. 

  784. 							dev->board.output_mode);
    785. 

  785. 

  786. 			/* Tell DIF object to go to baseband mode */
    787. 

  787. 			status = cx231xx_dif_set_standard(dev,
    788. 

  788. 							  DIF_USE_BASEBAND);
    789. 

  789. 			if (status < 0) {
    790. 

  790. 				cx231xx_errdev("%s: cx231xx_dif set to By pass"
    791. 

  791. 						" mode- errCode [%d]!\n",
    792. 

  792. 						__func__, status);
    793. 

  793. 				return status;
    794. 

  794. 			}
    795. 

  795. 

  796. 			/* Read the DFE_CTRL1 register */
    797. 

  797. 			status = vid_blk_read_word(dev, DFE_CTRL1, &value);
    798. 

  798. 

  799. 			/* enable the VBI_GATE_EN */
    800. 

  800. 			value |= FLD_VBI_GATE_EN;
    801. 

  801. 

  802. 			/* Enable the auto-VGA enable */
    803. 

  803. 			value |= FLD_VGA_AUTO_EN;
    804. 

  804. 

  805. 			/* Write it back */
    806. 

  806. 			status = vid_blk_write_word(dev, DFE_CTRL1, value);
    807. 

  807. 

  808. 			/* Disable auto config of registers */
    809. 

  809. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    810. 

  810. 					VID_BLK_I2C_ADDRESS,
    811. 

  811. 					MODE_CTRL, FLD_ACFG_DIS,
    812. 

  812. 					cx231xx_set_field(FLD_ACFG_DIS, 1));
    813. 

  813. 

  814. 			/* Set CVBS input mode */
    815. 

  815. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    816. 

  816. 				VID_BLK_I2C_ADDRESS,
    817. 

  817. 				MODE_CTRL, FLD_INPUT_MODE,
    818. 

  818. 				cx231xx_set_field(FLD_INPUT_MODE,
    819. 

  819. 						INPUT_MODE_CVBS_0));
    820. 

  820. 		} else {
    821. 

  821. 			/* Enable the DIF for the tuner */
    822. 

  822. 

  823. 			/* Reinitialize the DIF */
    824. 

  824. 			status = cx231xx_dif_set_standard(dev, dev->norm);
    825. 

  825. 			if (status < 0) {
    826. 

  826. 				cx231xx_errdev("%s: cx231xx_dif set to By pass"
    827. 

  827. 						" mode- errCode [%d]!\n",
    828. 

  828. 						__func__, status);
    829. 

  829. 				return status;
    830. 

  830. 			}
    831. 

  831. 

  832. 			/* Make sure bypass is cleared */
    833. 

  833. 			status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
    834. 

  834. 

  835. 			/* Clear the bypass bit */
    836. 

  836. 			value &= ~FLD_DIF_DIF_BYPASS;
    837. 

  837. 

  838. 			/* Enable the use of the DIF block */
    839. 

  839. 			status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
    840. 

  840. 

  841. 			/* Read the DFE_CTRL1 register */
    842. 

  842. 			status = vid_blk_read_word(dev, DFE_CTRL1, &value);
    843. 

  843. 

  844. 			/* Disable the VBI_GATE_EN */
    845. 

  845. 			value &= ~FLD_VBI_GATE_EN;
    846. 

  846. 

  847. 			/* Enable the auto-VGA enable, AGC, and
    848. 

  848. 			   set the skip count to 2 */
    849. 

  849. 			value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
    850. 

  850. 

  851. 			/* Write it back */
    852. 

  852. 			status = vid_blk_write_word(dev, DFE_CTRL1, value);
    853. 

  853. 

  854. 			/* Wait until AGC locks up */
    855. 

  855. 			msleep(1);
    856. 

  856. 

  857. 			/* Disable the auto-VGA enable AGC */
    858. 

  858. 			value &= ~(FLD_VGA_AUTO_EN);
    859. 

  859. 

  860. 			/* Write it back */
    861. 

  861. 			status = vid_blk_write_word(dev, DFE_CTRL1, value);
    862. 

  862. 

  863. 			/* Enable Polaris B0 AGC output */
    864. 

  864. 			status = vid_blk_read_word(dev, PIN_CTRL, &value);
    865. 

  865. 			value |= (FLD_OEF_AGC_RF) |
    866. 

  866. 				 (FLD_OEF_AGC_IFVGA) |
    867. 

  867. 				 (FLD_OEF_AGC_IF);
    868. 

  868. 			status = vid_blk_write_word(dev, PIN_CTRL, value);
    869. 

  869. 

  870. 			/* Set output mode */
    871. 

  871. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    872. 

  872. 						VID_BLK_I2C_ADDRESS,
    873. 

  873. 						OUT_CTRL1, FLD_OUT_MODE,
    874. 

  874. 						dev->board.output_mode);
    875. 

  875. 

  876. 			/* Disable auto config of registers */
    877. 

  877. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    878. 

  878. 					VID_BLK_I2C_ADDRESS,
    879. 

  879. 					MODE_CTRL, FLD_ACFG_DIS,
    880. 

  880. 					cx231xx_set_field(FLD_ACFG_DIS, 1));
    881. 

  881. 

  882. 			/* Set CVBS input mode */
    883. 

  883. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    884. 

  884. 				VID_BLK_I2C_ADDRESS,
    885. 

  885. 				MODE_CTRL, FLD_INPUT_MODE,
    886. 

  886. 				cx231xx_set_field(FLD_INPUT_MODE,
    887. 

  887. 						INPUT_MODE_CVBS_0));
    888. 

  888. 

  889. 			/* Set some bits in AFE_CTRL so that channel 2 or 3
    890. 

  890. 			 * is ready to receive audio */
    891. 

  891. 			/* Clear clamp for channels 2 and 3      (bit 16-17) */
    892. 

  892. 			/* Clear droop comp                      (bit 19-20) */
    893. 

  893. 			/* Set VGA_SEL (for audio control)       (bit 7-8) */
    894. 

  894. 			status = vid_blk_read_word(dev, AFE_CTRL, &value);
    895. 

  895. 

  896. 			/*Set Func mode:01-DIF 10-baseband 11-YUV*/
    897. 

  897. 			value &= (~(FLD_FUNC_MODE));
    898. 

  898. 			value |= 0x800000;
    899. 

  899. 

  900. 			value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
    901. 

  901. 

  902. 			status = vid_blk_write_word(dev, AFE_CTRL, value);
    903. 

  903. 

  904. 			if (dev->tuner_type == TUNER_NXP_TDA18271) {
    905. 

  905. 				status = vid_blk_read_word(dev, PIN_CTRL,
    906. 

  906. 				 &value);
    907. 

  907. 				status = vid_blk_write_word(dev, PIN_CTRL,
    908. 

  908. 				 (value & 0xFFFFFFEF));
    909. 

  909. 			}
    910. 

  910. 

  911. 			break;
    912. 

  912. 

  913. 		}
    914. 

  914. 		break;
    915. 

  915. 	}
    916. 

  916. 

  917. 	/* Set raw VBI mode */
    918. 

  918. 	status = cx231xx_read_modify_write_i2c_dword(dev,
    919. 

  919. 				VID_BLK_I2C_ADDRESS,
    920. 

  920. 				OUT_CTRL1, FLD_VBIHACTRAW_EN,
    921. 

  921. 				cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
    922. 

  922. 

  923. 	status = vid_blk_read_word(dev, OUT_CTRL1, &value);
    924. 

  924. 	if (value & 0x02) {
    925. 

  925. 		value |= (1 << 19);
    926. 

  926. 		status = vid_blk_write_word(dev, OUT_CTRL1, value);
    927. 

  927. 	}
    928. 

  928. 

  929. 	return status;
    930. 

  930. }
    931. 

  931. 

  932. void cx231xx_enable656(struct cx231xx *dev)
    933. 

  933. {
    934. 

  934. 	u8 temp = 0;
    935. 

  935. 	int status;
    936. 

  936. 	/*enable TS1 data[0:7] as output to export 656*/
    937. 

  937. 

  938. 	status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
    939. 

  939. 

  940. 	/*enable TS1 clock as output to export 656*/
    941. 

  941. 

  942. 	status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
    943. 

  943. 	temp = temp|0x04;
    944. 

  944. 

  945. 	status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
    946. 

  946. 

  947. }
    948. 

  948. EXPORT_SYMBOL_GPL(cx231xx_enable656);
    949. 

  949. 

  950. void cx231xx_disable656(struct cx231xx *dev)
    951. 

  951. {
    952. 

  952. 	u8 temp = 0;
    953. 

  953. 	int status;
    954. 

  954. 

  955. 

  956. 	status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
    957. 

  957. 

  958. 	status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
    959. 

  959. 	temp = temp&0xFB;
    960. 

  960. 

  961. 	status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
    962. 

  962. }
    963. 

  963. EXPORT_SYMBOL_GPL(cx231xx_disable656);
    964. 

  964. 

  965. /*
    966. 

  966.  * Handle any video-mode specific overrides that are different
    967. 

  967.  * on a per video standards basis after touching the MODE_CTRL
    968. 

  968.  * register which resets many values for autodetect
    969. 

  969.  */
    970. 

  970. int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
    971. 

  971. {
    972. 

  972. 	int status = 0;
    973. 

  973. 

  974. 	cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
    975. 

  975. 		     (unsigned int)dev->norm);
    976. 

  976. 

  977. 	/* Change the DFE_CTRL3 bp_percent to fix flagging */
    978. 

  978. 	status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
    979. 

  979. 

  980. 	if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
    981. 

  981. 		cx231xx_info("do_mode_ctrl_overrides NTSC\n");
    982. 

  982. 

  983. 		/* Move the close caption lines out of active video,
    984. 

  984. 		   adjust the active video start point */
    985. 

  985. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    986. 

  986. 							VID_BLK_I2C_ADDRESS,
    987. 

  987. 							VERT_TIM_CTRL,
    988. 

  988. 							FLD_VBLANK_CNT, 0x18);
    989. 

  989. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    990. 

  990. 							VID_BLK_I2C_ADDRESS,
    991. 

  991. 							VERT_TIM_CTRL,
    992. 

  992. 							FLD_VACTIVE_CNT,
    993. 

  993. 							0x1E7000);
    994. 

  994. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    995. 

  995. 							VID_BLK_I2C_ADDRESS,
    996. 

  996. 							VERT_TIM_CTRL,
    997. 

  997. 							FLD_V656BLANK_CNT,
    998. 

  998. 							0x1C000000);
    999. 

  999. 

  1000. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1001. 

  1001. 							VID_BLK_I2C_ADDRESS,
    1002. 

  1002. 							HORIZ_TIM_CTRL,
    1003. 

  1003. 							FLD_HBLANK_CNT,
    1004. 

  1004. 							cx231xx_set_field
    1005. 

  1005. 							(FLD_HBLANK_CNT, 0x79));
    1006. 

  1006. 

  1007. 	} else if (dev->norm & V4L2_STD_SECAM) {
    1008. 

  1008. 		cx231xx_info("do_mode_ctrl_overrides SECAM\n");
    1009. 

  1009. 		status =  cx231xx_read_modify_write_i2c_dword(dev,
    1010. 

  1010. 							VID_BLK_I2C_ADDRESS,
    1011. 

  1011. 							VERT_TIM_CTRL,
    1012. 

  1012. 							FLD_VBLANK_CNT, 0x20);
    1013. 

  1013. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1014. 

  1014. 							VID_BLK_I2C_ADDRESS,
    1015. 

  1015. 							VERT_TIM_CTRL,
    1016. 

  1016. 							FLD_VACTIVE_CNT,
    1017. 

  1017. 							cx231xx_set_field
    1018. 

  1018. 							(FLD_VACTIVE_CNT,
    1019. 

  1019. 							 0x244));
    1020. 

  1020. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1021. 

  1021. 							VID_BLK_I2C_ADDRESS,
    1022. 

  1022. 							VERT_TIM_CTRL,
    1023. 

  1023. 							FLD_V656BLANK_CNT,
    1024. 

  1024. 							cx231xx_set_field
    1025. 

  1025. 							(FLD_V656BLANK_CNT,
    1026. 

  1026. 							0x24));
    1027. 

  1027. 		/* Adjust the active video horizontal start point */
    1028. 

  1028. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1029. 

  1029. 							VID_BLK_I2C_ADDRESS,
    1030. 

  1030. 							HORIZ_TIM_CTRL,
    1031. 

  1031. 							FLD_HBLANK_CNT,
    1032. 

  1032. 							cx231xx_set_field
    1033. 

  1033. 							(FLD_HBLANK_CNT, 0x85));
    1034. 

  1034. 	} else {
    1035. 

  1035. 		cx231xx_info("do_mode_ctrl_overrides PAL\n");
    1036. 

  1036. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1037. 

  1037. 							VID_BLK_I2C_ADDRESS,
    1038. 

  1038. 							VERT_TIM_CTRL,
    1039. 

  1039. 							FLD_VBLANK_CNT, 0x20);
    1040. 

  1040. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1041. 

  1041. 							VID_BLK_I2C_ADDRESS,
    1042. 

  1042. 							VERT_TIM_CTRL,
    1043. 

  1043. 							FLD_VACTIVE_CNT,
    1044. 

  1044. 							cx231xx_set_field
    1045. 

  1045. 							(FLD_VACTIVE_CNT,
    1046. 

  1046. 							 0x244));
    1047. 

  1047. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1048. 

  1048. 							VID_BLK_I2C_ADDRESS,
    1049. 

  1049. 							VERT_TIM_CTRL,
    1050. 

  1050. 							FLD_V656BLANK_CNT,
    1051. 

  1051. 							cx231xx_set_field
    1052. 

  1052. 							(FLD_V656BLANK_CNT,
    1053. 

  1053. 							0x24));
    1054. 

  1054. 		/* Adjust the active video horizontal start point */
    1055. 

  1055. 		status = cx231xx_read_modify_write_i2c_dword(dev,
    1056. 

  1056. 							VID_BLK_I2C_ADDRESS,
    1057. 

  1057. 							HORIZ_TIM_CTRL,
    1058. 

  1058. 							FLD_HBLANK_CNT,
    1059. 

  1059. 							cx231xx_set_field
    1060. 

  1060. 							(FLD_HBLANK_CNT, 0x85));
    1061. 

  1061. 

  1062. 	}
    1063. 

  1063. 

  1064. 	return status;
    1065. 

  1065. }
    1066. 

  1066. 

  1067. int cx231xx_unmute_audio(struct cx231xx *dev)
    1068. 

  1068. {
    1069. 

  1069. 	return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
    1070. 

  1070. }
    1071. 

  1071. EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
    1072. 

  1072. 

  1073. int stopAudioFirmware(struct cx231xx *dev)
    1074. 

  1074. {
    1075. 

  1075. 	return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
    1076. 

  1076. }
    1077. 

  1077. 

  1078. int restartAudioFirmware(struct cx231xx *dev)
    1079. 

  1079. {
    1080. 

  1080. 	return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
    1081. 

  1081. }
    1082. 

  1082. 

  1083. int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
    1084. 

  1084. {
    1085. 

  1085. 	int status = 0;
    1086. 

  1086. 	enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
    1087. 

  1087. 

  1088. 	switch (INPUT(input)->amux) {
    1089. 

  1089. 	case CX231XX_AMUX_VIDEO:
    1090. 

  1090. 		ainput = AUDIO_INPUT_TUNER_TV;
    1091. 

  1091. 		break;
    1092. 

  1092. 	case CX231XX_AMUX_LINE_IN:
    1093. 

  1093. 		status = cx231xx_i2s_blk_set_audio_input(dev, input);
    1094. 

  1094. 		ainput = AUDIO_INPUT_LINE;
    1095. 

  1095. 		break;
    1096. 

  1096. 	default:
    1097. 

  1097. 		break;
    1098. 

  1098. 	}
    1099. 

  1099. 

  1100. 	status = cx231xx_set_audio_decoder_input(dev, ainput);
    1101. 

  1101. 

  1102. 	return status;
    1103. 

  1103. }
    1104. 

  1104. 

  1105. int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
    1106. 

  1106. 				    enum AUDIO_INPUT audio_input)
    1107. 

  1107. {
    1108. 

  1108. 	u32 dwval;
    1109. 

  1109. 	int status;
    1110. 

  1110. 	u8 gen_ctrl;
    1111. 

  1111. 	u32 value = 0;
    1112. 

  1112. 

  1113. 	/* Put it in soft reset   */
    1114. 

  1114. 	status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
    1115. 

  1115. 	gen_ctrl |= 1;
    1116. 

  1116. 	status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
    1117. 

  1117. 

  1118. 	switch (audio_input) {
    1119. 

  1119. 	case AUDIO_INPUT_LINE:
    1120. 

  1120. 		/* setup AUD_IO control from Merlin paralle output */
    1121. 

  1121. 		value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
    1122. 

  1122. 					  AUD_CHAN_SRC_PARALLEL);
    1123. 

  1123. 		status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
    1124. 

  1124. 

  1125. 		/* setup input to Merlin, SRC2 connect to AC97
    1126. 

  1126. 		   bypass upsample-by-2, slave mode, sony mode, left justify
    1127. 

  1127. 		   adr 091c, dat 01000000 */
    1128. 

  1128. 		status = vid_blk_read_word(dev, AC97_CTL, &dwval);
    1129. 

  1129. 

  1130. 		status = vid_blk_write_word(dev, AC97_CTL,
    1131. 

  1131. 					   (dwval | FLD_AC97_UP2X_BYPASS));
    1132. 

  1132. 

  1133. 		/* select the parallel1 and SRC3 */
    1134. 

  1134. 		status = vid_blk_write_word(dev, BAND_OUT_SEL,
    1135. 

  1135. 				cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
    1136. 

  1136. 				cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
    1137. 

  1137. 				cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
    1138. 

  1138. 

  1139. 		/* unmute all, AC97 in, independence mode
    1140. 

  1140. 		   adr 08d0, data 0x00063073 */
    1141. 

  1141. 		status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
    1142. 

  1142. 		status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
    1143. 

  1143. 

  1144. 		/* set AVC maximum threshold, adr 08d4, dat ffff0024 */
    1145. 

  1145. 		status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
    1146. 

  1146. 		status = vid_blk_write_word(dev, PATH1_VOL_CTL,
    1147. 

  1147. 					   (dwval | FLD_PATH1_AVC_THRESHOLD));
    1148. 

  1148. 

  1149. 		/* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
    1150. 

  1150. 		status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
    1151. 

  1151. 		status = vid_blk_write_word(dev, PATH1_SC_CTL,
    1152. 

  1152. 					   (dwval | FLD_PATH1_SC_THRESHOLD));
    1153. 

  1153. 		break;
    1154. 

  1154. 

  1155. 	case AUDIO_INPUT_TUNER_TV:
    1156. 

  1156. 	default:
    1157. 

  1157. 		status = stopAudioFirmware(dev);
    1158. 

  1158. 		/* Setup SRC sources and clocks */
    1159. 

  1159. 		status = vid_blk_write_word(dev, BAND_OUT_SEL,
    1160. 

  1160. 			cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
    1161. 

  1161. 			cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
    1162. 

  1162. 			cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
    1163. 

  1163. 			cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
    1164. 

  1164. 			cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
    1165. 

  1165. 			cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
    1166. 

  1166. 			cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
    1167. 

  1167. 			cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
    1168. 

  1168. 			cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
    1169. 

  1169. 			cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
    1170. 

  1170. 			cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
    1171. 

  1171. 			cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
    1172. 

  1172. 			cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
    1173. 

  1173. 

  1174. 		/* Setup the AUD_IO control */
    1175. 

  1175. 		status = vid_blk_write_word(dev, AUD_IO_CTRL,
    1176. 

  1176. 			cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
    1177. 

  1177. 			cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
    1178. 

  1178. 			cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
    1179. 

  1179. 			cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
    1180. 

  1180. 			cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
    1181. 

  1181. 

  1182. 		status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
    1183. 

  1183. 

  1184. 		/* setAudioStandard(_audio_standard); */
    1185. 

  1185. 		status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
    1186. 

  1186. 

  1187. 		status = restartAudioFirmware(dev);
    1188. 

  1188. 

  1189. 		switch (dev->board.tuner_type) {
    1190. 

  1190. 		case TUNER_XC5000:
    1191. 

  1191. 			/* SIF passthrough at 28.6363 MHz sample rate */
    1192. 

  1192. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    1193. 

  1193. 					VID_BLK_I2C_ADDRESS,
    1194. 

  1194. 					CHIP_CTRL,
    1195. 

  1195. 					FLD_SIF_EN,
    1196. 

  1196. 					cx231xx_set_field(FLD_SIF_EN, 1));
    1197. 

  1197. 			break;
    1198. 

  1198. 		case TUNER_NXP_TDA18271:
    1199. 

  1199. 			/* Normal mode: SIF passthrough at 14.32 MHz */
    1200. 

  1200. 			status = cx231xx_read_modify_write_i2c_dword(dev,
    1201. 

  1201. 					VID_BLK_I2C_ADDRESS,
    1202. 

  1202. 					CHIP_CTRL,
    1203. 

  1203. 					FLD_SIF_EN,
    1204. 

  1204. 					cx231xx_set_field(FLD_SIF_EN, 0));
    1205. 

  1205. 			break;
    1206. 

  1206. 		default:
    1207. 

  1207. 			/* This is just a casual suggestion to people adding
    1208. 

  1208. 			   new boards in case they use a tuner type we don't
    1209. 

  1209. 			   currently know about */
    1210. 

  1210. 			printk(KERN_INFO "Unknown tuner type configuring SIF");
    1211. 

  1211. 			break;
    1212. 

  1212. 		}
    1213. 

  1213. 		break;
    1214. 

  1214. 

  1215. 	case AUDIO_INPUT_TUNER_FM:
    1216. 

  1216. 		/*  use SIF for FM radio
    1217. 

  1217. 		   setupFM();
    1218. 

  1218. 		   setAudioStandard(_audio_standard);
    1219. 

  1219. 		 */
    1220. 

  1220. 		break;
    1221. 

  1221. 

  1222. 	case AUDIO_INPUT_MUTE:
    1223. 

  1223. 		status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
    1224. 

  1224. 		break;
    1225. 

  1225. 	}
    1226. 

  1226. 

  1227. 	/* Take it out of soft reset */
    1228. 

  1228. 	status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
    1229. 

  1229. 	gen_ctrl &= ~1;
    1230. 

  1230. 	status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
    1231. 

  1231. 

  1232. 	return status;
    1233. 

  1233. }
    1234. 

  1234. 

  1235. /******************************************************************************
    1236. 

  1236.  *                    C H I P Specific  C O N T R O L   functions             *
    1237. 

  1237.  ******************************************************************************/
    1238. 

  1238. int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
    1239. 

  1239. {
    1240. 

  1240. 	u32 value;
    1241. 

  1241. 	int status = 0;
    1242. 

  1242. 

  1243. 	status = vid_blk_read_word(dev, PIN_CTRL, &value);
    1244. 

  1244. 	value |= (~dev->board.ctl_pin_status_mask);
    1245. 

  1245. 	status = vid_blk_write_word(dev, PIN_CTRL, value);
    1246. 

  1246. 

  1247. 	return status;
    1248. 

  1248. }
    1249. 

  1249. 

  1250. int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
    1251. 

  1251. 					      u8 analog_or_digital)
    1252. 

  1252. {
    1253. 

  1253. 	int status = 0;
    1254. 

  1254. 

  1255. 	/* first set the direction to output */
    1256. 

  1256. 	status = cx231xx_set_gpio_direction(dev,
    1257. 

  1257. 					    dev->board.
    1258. 

  1258. 					    agc_analog_digital_select_gpio, 1);
    1259. 

  1259. 

  1260. 	/* 0 - demod ; 1 - Analog mode */
    1261. 

  1261. 	status = cx231xx_set_gpio_value(dev,
    1262. 

  1262. 				   dev->board.agc_analog_digital_select_gpio,
    1263. 

  1263. 				   analog_or_digital);
    1264. 

  1264. 

  1265. 	return status;
    1266. 

  1266. }
    1267. 

  1267. 

  1268. int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
    1269. 

  1269. {
    1270. 

  1270. 	u8 value[4] = { 0, 0, 0, 0 };
    1271. 

  1271. 	int status = 0;
    1272. 

  1272. 	bool current_is_port_3;
    1273. 

  1273. 

  1274. 	if (dev->board.dont_use_port_3)
    1275. 

  1275. 		is_port_3 = false;
    1276. 

  1276. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
    1277. 

  1277. 				       PWR_CTL_EN, value, 4);
    1278. 

  1278. 	if (status < 0)
    1279. 

  1279. 		return status;
    1280. 

  1280. 

  1281. 	current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
    1282. 

  1282. 

  1283. 	/* Just return, if already using the right port */
    1284. 

  1284. 	if (current_is_port_3 == is_port_3)
    1285. 

  1285. 		return 0;
    1286. 

  1286. 

  1287. 	if (is_port_3)
    1288. 

  1288. 		value[0] |= I2C_DEMOD_EN;
    1289. 

  1289. 	else
    1290. 

  1290. 		value[0] &= ~I2C_DEMOD_EN;
    1291. 

  1291. 

  1292. 	cx231xx_info("Changing the i2c master port to %d\n",
    1293. 

  1293. 		     is_port_3 ?  3 : 1);
    1294. 

  1294. 

  1295. 	status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    1296. 

  1296. 					PWR_CTL_EN, value, 4);
    1297. 

  1297. 

  1298. 	return status;
    1299. 

  1299. 

  1300. }
    1301. 

  1301. EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
    1302. 

  1302. 

  1303. void update_HH_register_after_set_DIF(struct cx231xx *dev)
    1304. 

  1304. {
    1305. 

  1305. /*
    1306. 

  1306. 	u8 status = 0;
    1307. 

  1307. 	u32 value = 0;
    1308. 

    1309. 

  1309. 	vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
    1310. 

  1310. 	vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
    1311. 

  1311. 	vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
    1312. 

    1313. 

  1313. 	status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
    1314. 

  1314. 	vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
    1315. 

  1315. 	status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL,  &value);
    1316. 

  1316. */
    1317. 

  1317. }
    1318. 

  1318. 

  1319. void cx231xx_dump_HH_reg(struct cx231xx *dev)
    1320. 

  1320. {
    1321. 

  1321. 	u8 status = 0;
    1322. 

  1322. 	u32 value = 0;
    1323. 

  1323. 	u16  i = 0;
    1324. 

  1324. 

  1325. 	value = 0x45005390;
    1326. 

  1326. 	status = vid_blk_write_word(dev, 0x104, value);
    1327. 

  1327. 

  1328. 	for (i = 0x100; i < 0x140; i++) {
    1329. 

  1329. 		status = vid_blk_read_word(dev, i, &value);
    1330. 

  1330. 		cx231xx_info("reg0x%x=0x%x\n", i, value);
    1331. 

  1331. 		i = i+3;
    1332. 

  1332. 	}
    1333. 

  1333. 

  1334. 	for (i = 0x300; i < 0x400; i++) {
    1335. 

  1335. 		status = vid_blk_read_word(dev, i, &value);
    1336. 

  1336. 		cx231xx_info("reg0x%x=0x%x\n", i, value);
    1337. 

  1337. 		i = i+3;
    1338. 

  1338. 	}
    1339. 

  1339. 

  1340. 	for (i = 0x400; i < 0x440; i++) {
    1341. 

  1341. 		status = vid_blk_read_word(dev, i,  &value);
    1342. 

  1342. 		cx231xx_info("reg0x%x=0x%x\n", i, value);
    1343. 

  1343. 		i = i+3;
    1344. 

  1344. 	}
    1345. 

  1345. 

  1346. 	status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
    1347. 

  1347. 	cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
    1348. 

  1348. 	vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
    1349. 

  1349. 	status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
    1350. 

  1350. 	cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
    1351. 

  1351. }
    1352. 

  1352. 

  1353. void cx231xx_dump_SC_reg(struct cx231xx *dev)
    1354. 

  1354. {
    1355. 

  1355. 	u8 value[4] = { 0, 0, 0, 0 };
    1356. 

  1356. 	int status = 0;
    1357. 

  1357. 	cx231xx_info("cx231xx_dump_SC_reg!\n");
    1358. 

  1358. 

  1359. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
    1360. 

  1360. 				 value, 4);
    1361. 

  1361. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
    1362. 

  1362. 				 value[1], value[2], value[3]);
    1363. 

  1363. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
    1364. 

  1364. 				 value, 4);
    1365. 

  1365. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
    1366. 

  1366. 				 value[1], value[2], value[3]);
    1367. 

  1367. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
    1368. 

  1368. 				 value, 4);
    1369. 

  1369. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
    1370. 

  1370. 				 value[1], value[2], value[3]);
    1371. 

  1371. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
    1372. 

  1372. 				 value, 4);
    1373. 

  1373. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
    1374. 

  1374. 				 value[1], value[2], value[3]);
    1375. 

  1375. 

  1376. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
    1377. 

  1377. 				 value, 4);
    1378. 

  1378. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
    1379. 

  1379. 				 value[1], value[2], value[3]);
    1380. 

  1380. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
    1381. 

  1381. 				 value, 4);
    1382. 

  1382. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
    1383. 

  1383. 				 value[1], value[2], value[3]);
    1384. 

  1384. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
    1385. 

  1385. 				 value, 4);
    1386. 

  1386. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
    1387. 

  1387. 				 value[1], value[2], value[3]);
    1388. 

  1388. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
    1389. 

  1389. 				 value, 4);
    1390. 

  1390. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
    1391. 

  1391. 				 value[1], value[2], value[3]);
    1392. 

  1392. 

  1393. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
    1394. 

  1394. 				 value, 4);
    1395. 

  1395. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
    1396. 

  1396. 				 value[1], value[2], value[3]);
    1397. 

  1397. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
    1398. 

  1398. 				 value, 4);
    1399. 

  1399. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
    1400. 

  1400. 				 value[1], value[2], value[3]);
    1401. 

  1401. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
    1402. 

  1402. 				 value, 4);
    1403. 

  1403. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
    1404. 

  1404. 				 value[1], value[2], value[3]);
    1405. 

  1405. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
    1406. 

  1406. 				 value, 4);
    1407. 

  1407. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
    1408. 

  1408. 				 value[1], value[2], value[3]);
    1409. 

  1409. 

  1410. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
    1411. 

  1411. 				 value, 4);
    1412. 

  1412. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
    1413. 

  1413. 				 value[1], value[2], value[3]);
    1414. 

  1414. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
    1415. 

  1415. 				 value, 4);
    1416. 

  1416. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
    1417. 

  1417. 				 value[1], value[2], value[3]);
    1418. 

  1418. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
    1419. 

  1419. 				 value, 4);
    1420. 

  1420. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
    1421. 

  1421. 				 value[1], value[2], value[3]);
    1422. 

  1422. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
    1423. 

  1423. 				 value, 4);
    1424. 

  1424. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
    1425. 

  1425. 				 value[1], value[2], value[3]);
    1426. 

  1426. 

  1427. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
    1428. 

  1428. 				 value, 4);
    1429. 

  1429. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
    1430. 

  1430. 				 value[1], value[2], value[3]);
    1431. 

  1431. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
    1432. 

  1432. 				 value, 4);
    1433. 

  1433. 	cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
    1434. 

  1434. 				 value[1], value[2], value[3]);
    1435. 

  1435. 

  1436. 

  1437. }
    1438. 

  1438. 

  1439. void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
    1440. 

  1440. 

  1441. {
    1442. 

  1442. 	u8 status = 0;
    1443. 

  1443. 	u8 value = 0;
    1444. 

  1444. 

  1445. 

  1446. 

  1447. 	status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
    1448. 

  1448. 	value = (value & 0xFE)|0x01;
    1449. 

  1449. 	status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
    1450. 

  1450. 

  1451. 	status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
    1452. 

  1452. 	value = (value & 0xFE)|0x00;
    1453. 

  1453. 	status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
    1454. 

  1454. 

  1455. 

  1456. /*
    1457. 

  1457. 	config colibri to lo-if mode
    1458. 

    1459. 

  1459. 	FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
    1460. 

  1460. 		the diff IF input by half,
    1461. 

    1462. 

  1462. 		for low-if agc defect
    1463. 

  1463. */
    1464. 

  1464. 

  1465. 	status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
    1466. 

  1466. 	value = (value & 0xFC)|0x00;
    1467. 

  1467. 	status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
    1468. 

  1468. 

  1469. 	status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
    1470. 

  1470. 	value = (value & 0xF9)|0x02;
    1471. 

  1471. 	status = afe_write_byte(dev, ADC_INPUT_CH3, value);
    1472. 

  1472. 

  1473. 	status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
    1474. 

  1474. 	value = (value & 0xFB)|0x04;
    1475. 

  1475. 	status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
    1476. 

  1476. 

  1477. 	status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
    1478. 

  1478. 	value = (value & 0xFC)|0x03;
    1479. 

  1479. 	status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
    1480. 

  1480. 

  1481. 	status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
    1482. 

  1482. 	value = (value & 0xFB)|0x04;
    1483. 

  1483. 	status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
    1484. 

  1484. 

  1485. 	status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
    1486. 

  1486. 	value = (value & 0xF8)|0x06;
    1487. 

  1487. 	status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
    1488. 

  1488. 

  1489. 	status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
    1490. 

  1490. 	value = (value & 0x8F)|0x40;
    1491. 

  1491. 	status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
    1492. 

  1492. 

  1493. 	status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
    1494. 

  1494. 	value = (value & 0xDF)|0x20;
    1495. 

  1495. 	status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
    1496. 

  1496. }
    1497. 

  1497. 

  1498. void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
    1499. 

  1499. 		 u8 spectral_invert, u32 mode)
    1500. 

  1500. {
    1501. 

  1501. 	u32 colibri_carrier_offset = 0;
    1502. 

  1502. 	u8 status = 0;
    1503. 

  1503. 	u32 func_mode = 0x01; /* Device has a DIF if this function is called */
    1504. 

  1504. 	u32 standard = 0;
    1505. 

  1505. 	u8 value[4] = { 0, 0, 0, 0 };
    1506. 

  1506. 

  1507. 	cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
    1508. 

  1508. 	value[0] = (u8) 0x6F;
    1509. 

  1509. 	value[1] = (u8) 0x6F;
    1510. 

  1510. 	value[2] = (u8) 0x6F;
    1511. 

  1511. 	value[3] = (u8) 0x6F;
    1512. 

  1512. 	status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    1513. 

  1513. 					PWR_CTL_EN, value, 4);
    1514. 

  1514. 

  1515. 	/*Set colibri for low IF*/
    1516. 

  1516. 	status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
    1517. 

  1517. 

  1518. 	/* Set C2HH for low IF operation.*/
    1519. 

  1519. 	standard = dev->norm;
    1520. 

  1520. 	status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
    1521. 

  1521. 						       func_mode, standard);
    1522. 

  1522. 

  1523. 	/* Get colibri offsets.*/
    1524. 

  1524. 	colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
    1525. 

  1525. 								   standard);
    1526. 

  1526. 

  1527. 	cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
    1528. 

  1528. 		     colibri_carrier_offset, standard);
    1529. 

  1529. 

  1530. 	/* Set the band Pass filter for DIF*/
    1531. 

  1531. 	cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
    1532. 

  1532. 				 spectral_invert, mode);
    1533. 

  1533. }
    1534. 

  1534. 

  1535. u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
    1536. 

  1536. {
    1537. 

  1537. 	u32 colibri_carrier_offset = 0;
    1538. 

  1538. 

  1539. 	if (mode == TUNER_MODE_FM_RADIO) {
    1540. 

  1540. 		colibri_carrier_offset = 1100000;
    1541. 

  1541. 	} else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
    1542. 

  1542. 		colibri_carrier_offset = 4832000;  /*4.83MHz	*/
    1543. 

  1543. 	} else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
    1544. 

  1544. 		colibri_carrier_offset = 2700000;  /*2.70MHz       */
    1545. 

  1545. 	} else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
    1546. 

  1546. 			| V4L2_STD_SECAM)) {
    1547. 

  1547. 		colibri_carrier_offset = 2100000;  /*2.10MHz	*/
    1548. 

  1548. 	}
    1549. 

  1549. 

  1550. 	return colibri_carrier_offset;
    1551. 

  1551. }
    1552. 

  1552. 

  1553. void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
    1554. 

  1554. 		 u8 spectral_invert, u32 mode)
    1555. 

  1555. {
    1556. 

  1556. 	unsigned long pll_freq_word;
    1557. 

  1557. 	int status = 0;
    1558. 

  1558. 	u32 dif_misc_ctrl_value = 0;
    1559. 

  1559. 	u64 pll_freq_u64 = 0;
    1560. 

  1560. 	u32 i = 0;
    1561. 

  1561. 

  1562. 	cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
    1563. 

  1563. 			 if_freq, spectral_invert, mode);
    1564. 

  1564. 

  1565. 

  1566. 	if (mode == TUNER_MODE_FM_RADIO) {
    1567. 

  1567. 		pll_freq_word = 0x905A1CAC;
    1568. 

  1568. 		status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
    1569. 

  1569. 

  1570. 	} else /*KSPROPERTY_TUNER_MODE_TV*/{
    1571. 

  1571. 		/* Calculate the PLL frequency word based on the adjusted if_freq*/
    1572. 

  1572. 		pll_freq_word = if_freq;
    1573. 

  1573. 		pll_freq_u64 = (u64)pll_freq_word << 28L;
    1574. 

  1574. 		do_div(pll_freq_u64, 50000000);
    1575. 

  1575. 		pll_freq_word = (u32)pll_freq_u64;
    1576. 

  1576. 		/*pll_freq_word = 0x3463497;*/
    1577. 

  1577. 		status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD,  pll_freq_word);
    1578. 

  1578. 

  1579. 	if (spectral_invert) {
    1580. 

  1580. 		if_freq -= 400000;
    1581. 

  1581. 		/* Enable Spectral Invert*/
    1582. 

  1582. 		status = vid_blk_read_word(dev, DIF_MISC_CTRL,
    1583. 

  1583. 					&dif_misc_ctrl_value);
    1584. 

  1584. 		dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
    1585. 

  1585. 		status = vid_blk_write_word(dev, DIF_MISC_CTRL,
    1586. 

  1586. 					dif_misc_ctrl_value);
    1587. 

  1587. 	} else {
    1588. 

  1588. 		if_freq += 400000;
    1589. 

  1589. 		/* Disable Spectral Invert*/
    1590. 

  1590. 		status = vid_blk_read_word(dev, DIF_MISC_CTRL,
    1591. 

  1591. 					&dif_misc_ctrl_value);
    1592. 

  1592. 		dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
    1593. 

  1593. 		status = vid_blk_write_word(dev, DIF_MISC_CTRL,
    1594. 

  1594. 					dif_misc_ctrl_value);
    1595. 

  1595. 	}
    1596. 

  1596. 

  1597. 	if_freq = (if_freq/100000)*100000;
    1598. 

  1598. 

  1599. 	if (if_freq < 3000000)
    1600. 

  1600. 		if_freq = 3000000;
    1601. 

  1601. 

  1602. 	if (if_freq > 16000000)
    1603. 

  1603. 		if_freq = 16000000;
    1604. 

  1604. 	}
    1605. 

  1605. 

  1606. 	cx231xx_info("Enter IF=%zd\n",
    1607. 

  1607. 			sizeof(Dif_set_array)/sizeof(struct dif_settings));
    1608. 

  1608. 	for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
    1609. 

  1609. 		if (Dif_set_array[i].if_freq == if_freq) {
    1610. 

  1610. 			status = vid_blk_write_word(dev,
    1611. 

  1611. 			Dif_set_array[i].register_address, Dif_set_array[i].value);
    1612. 

  1612. 		}
    1613. 

  1613. 	}
    1614. 

  1614. }
    1615. 

  1615. 

  1616. /******************************************************************************
    1617. 

  1617.  *                 D I F - B L O C K    C O N T R O L   functions             *
    1618. 

  1618.  ******************************************************************************/
    1619. 

  1619. int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
    1620. 

  1620. 					  u32 function_mode, u32 standard)
    1621. 

  1621. {
    1622. 

  1622. 	int status = 0;
    1623. 

  1623. 

  1624. 

  1625. 	if (mode == V4L2_TUNER_RADIO) {
    1626. 

  1626. 		/* C2HH */
    1627. 

  1627. 		/* lo if big signal */
    1628. 

  1628. 		status = cx231xx_reg_mask_write(dev,
    1629. 

  1629. 				VID_BLK_I2C_ADDRESS, 32,
    1630. 

  1630. 				AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
    1631. 

  1631. 		/* FUNC_MODE = DIF */
    1632. 

  1632. 		status = cx231xx_reg_mask_write(dev,
    1633. 

  1633. 				VID_BLK_I2C_ADDRESS, 32,
    1634. 

  1634. 				AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
    1635. 

  1635. 		/* IF_MODE */
    1636. 

  1636. 		status = cx231xx_reg_mask_write(dev,
    1637. 

  1637. 				VID_BLK_I2C_ADDRESS, 32,
    1638. 

  1638. 				AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
    1639. 

  1639. 		/* no inv */
    1640. 

  1640. 		status = cx231xx_reg_mask_write(dev,
    1641. 

  1641. 				VID_BLK_I2C_ADDRESS, 32,
    1642. 

  1642. 				AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
    1643. 

  1643. 	} else if (standard != DIF_USE_BASEBAND) {
    1644. 

  1644. 		if (standard & V4L2_STD_MN) {
    1645. 

  1645. 			/* lo if big signal */
    1646. 

  1646. 			status = cx231xx_reg_mask_write(dev,
    1647. 

  1647. 					VID_BLK_I2C_ADDRESS, 32,
    1648. 

  1648. 					AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
    1649. 

  1649. 			/* FUNC_MODE = DIF */
    1650. 

  1650. 			status = cx231xx_reg_mask_write(dev,
    1651. 

  1651. 					VID_BLK_I2C_ADDRESS, 32,
    1652. 

  1652. 					AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
    1653. 

  1653. 					function_mode);
    1654. 

  1654. 			/* IF_MODE */
    1655. 

  1655. 			status = cx231xx_reg_mask_write(dev,
    1656. 

  1656. 					VID_BLK_I2C_ADDRESS, 32,
    1657. 

  1657. 					AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
    1658. 

  1658. 			/* no inv */
    1659. 

  1659. 			status = cx231xx_reg_mask_write(dev,
    1660. 

  1660. 					VID_BLK_I2C_ADDRESS, 32,
    1661. 

  1661. 					AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
    1662. 

  1662. 			/* 0x124, AUD_CHAN1_SRC = 0x3 */
    1663. 

  1663. 			status = cx231xx_reg_mask_write(dev,
    1664. 

  1664. 					VID_BLK_I2C_ADDRESS, 32,
    1665. 

  1665. 					AUD_IO_CTRL, 0, 31, 0x00000003);
    1666. 

  1666. 		} else if ((standard == V4L2_STD_PAL_I) |
    1667. 

  1667. 			(standard & V4L2_STD_PAL_D) |
    1668. 

  1668. 			(standard & V4L2_STD_SECAM)) {
    1669. 

  1669. 			/* C2HH setup */
    1670. 

  1670. 			/* lo if big signal */
    1671. 

  1671. 			status = cx231xx_reg_mask_write(dev,
    1672. 

  1672. 					VID_BLK_I2C_ADDRESS, 32,
    1673. 

  1673. 					AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
    1674. 

  1674. 			/* FUNC_MODE = DIF */
    1675. 

  1675. 			status = cx231xx_reg_mask_write(dev,
    1676. 

  1676. 					VID_BLK_I2C_ADDRESS, 32,
    1677. 

  1677. 					AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
    1678. 

  1678. 					function_mode);
    1679. 

  1679. 			/* IF_MODE */
    1680. 

  1680. 			status = cx231xx_reg_mask_write(dev,
    1681. 

  1681. 					VID_BLK_I2C_ADDRESS, 32,
    1682. 

  1682. 					AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
    1683. 

  1683. 			/* no inv */
    1684. 

  1684. 			status = cx231xx_reg_mask_write(dev,
    1685. 

  1685. 					VID_BLK_I2C_ADDRESS, 32,
    1686. 

  1686. 					AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
    1687. 

  1687. 		} else {
    1688. 

  1688. 			/* default PAL BG */
    1689. 

  1689. 			/* C2HH setup */
    1690. 

  1690. 			/* lo if big signal */
    1691. 

  1691. 			status = cx231xx_reg_mask_write(dev,
    1692. 

  1692. 					VID_BLK_I2C_ADDRESS, 32,
    1693. 

  1693. 					AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
    1694. 

  1694. 			/* FUNC_MODE = DIF */
    1695. 

  1695. 			status = cx231xx_reg_mask_write(dev,
    1696. 

  1696. 					VID_BLK_I2C_ADDRESS, 32,
    1697. 

  1697. 					AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
    1698. 

  1698. 					function_mode);
    1699. 

  1699. 			/* IF_MODE */
    1700. 

  1700. 			status = cx231xx_reg_mask_write(dev,
    1701. 

  1701. 					VID_BLK_I2C_ADDRESS, 32,
    1702. 

  1702. 					AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
    1703. 

  1703. 			/* no inv */
    1704. 

  1704. 			status = cx231xx_reg_mask_write(dev,
    1705. 

  1705. 					VID_BLK_I2C_ADDRESS, 32,
    1706. 

  1706. 					AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
    1707. 

  1707. 		}
    1708. 

  1708. 	}
    1709. 

  1709. 

  1710. 	return status;
    1711. 

  1711. }
    1712. 

  1712. 

  1713. int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
    1714. 

  1714. {
    1715. 

  1715. 	int status = 0;
    1716. 

  1716. 	u32 dif_misc_ctrl_value = 0;
    1717. 

  1717. 	u32 func_mode = 0;
    1718. 

  1718. 

  1719. 	cx231xx_info("%s: setStandard to %x\n", __func__, standard);
    1720. 

  1720. 

  1721. 	status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
    1722. 

  1722. 	if (standard != DIF_USE_BASEBAND)
    1723. 

  1723. 		dev->norm = standard;
    1724. 

  1724. 

  1725. 	switch (dev->model) {
    1726. 

  1726. 	case CX231XX_BOARD_CNXT_CARRAERA:
    1727. 

  1727. 	case CX231XX_BOARD_CNXT_RDE_250:
    1728. 

  1728. 	case CX231XX_BOARD_CNXT_SHELBY:
    1729. 

  1729. 	case CX231XX_BOARD_CNXT_RDU_250:
    1730. 

  1730. 	case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
    1731. 

  1731. 	case CX231XX_BOARD_HAUPPAUGE_EXETER:
    1732. 

  1732. 		func_mode = 0x03;
    1733. 

  1733. 		break;
    1734. 

  1734. 	case CX231XX_BOARD_CNXT_RDE_253S:
    1735. 

  1735. 	case CX231XX_BOARD_CNXT_RDU_253S:
    1736. 

  1736. 		func_mode = 0x01;
    1737. 

  1737. 		break;
    1738. 

  1738. 	default:
    1739. 

  1739. 		func_mode = 0x01;
    1740. 

  1740. 	}
    1741. 

  1741. 

  1742. 	status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
    1743. 

  1743. 						  func_mode, standard);
    1744. 

  1744. 

  1745. 	if (standard == DIF_USE_BASEBAND) {	/* base band */
    1746. 

  1746. 		/* There is a different SRC_PHASE_INC value
    1747. 

  1747. 		   for baseband vs. DIF */
    1748. 

  1748. 		status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
    1749. 

  1749. 		status = vid_blk_read_word(dev, DIF_MISC_CTRL,
    1750. 

  1750. 						&dif_misc_ctrl_value);
    1751. 

  1751. 		dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
    1752. 

  1752. 		status = vid_blk_write_word(dev, DIF_MISC_CTRL,
    1753. 

  1753. 						dif_misc_ctrl_value);
    1754. 

  1754. 	} else if (standard & V4L2_STD_PAL_D) {
    1755. 

  1755. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1756. 

  1756. 					   DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
    1757. 

  1757. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1758. 

  1758. 					   DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
    1759. 

  1759. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1760. 

  1760. 					   DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
    1761. 

  1761. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1762. 

  1762. 					   DIF_PLL_CTRL3, 0, 31, 0x00008800);
    1763. 

  1763. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1764. 

  1764. 					   DIF_AGC_IF_REF, 0, 31, 0x444C1380);
    1765. 

  1765. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1766. 

  1766. 					   DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
    1767. 

  1767. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1768. 

  1768. 					   DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
    1769. 

  1769. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1770. 

  1770. 					   DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
    1771. 

  1771. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1772. 

  1772. 					   DIF_AGC_IF_INT_CURRENT, 0, 31,
    1773. 

  1773. 					   0x26001700);
    1774. 

  1774. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1775. 

  1775. 					   DIF_AGC_RF_CURRENT, 0, 31,
    1776. 

  1776. 					   0x00002660);
    1777. 

  1777. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1778. 

  1778. 					   DIF_VIDEO_AGC_CTRL, 0, 31,
    1779. 

  1779. 					   0x72500800);
    1780. 

  1780. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1781. 

  1781. 					   DIF_VID_AUD_OVERRIDE, 0, 31,
    1782. 

  1782. 					   0x27000100);
    1783. 

  1783. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1784. 

  1784. 					   DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
    1785. 

  1785. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1786. 

  1786. 					   DIF_COMP_FLT_CTRL, 0, 31,
    1787. 

  1787. 					   0x00000000);
    1788. 

  1788. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1789. 

  1789. 					   DIF_SRC_PHASE_INC, 0, 31,
    1790. 

  1790. 					   0x1befbf06);
    1791. 

  1791. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1792. 

  1792. 					   DIF_SRC_GAIN_CONTROL, 0, 31,
    1793. 

  1793. 					   0x000035e8);
    1794. 

  1794. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1795. 

  1795. 					   DIF_RPT_VARIANCE, 0, 31, 0x00000000);
    1796. 

  1796. 		/* Save the Spec Inversion value */
    1797. 

  1797. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1798. 

  1798. 		dif_misc_ctrl_value |= 0x3a023F11;
    1799. 

  1799. 	} else if (standard & V4L2_STD_PAL_I) {
    1800. 

  1800. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1801. 

  1801. 					   DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
    1802. 

  1802. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1803. 

  1803. 					   DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
    1804. 

  1804. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1805. 

  1805. 					   DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
    1806. 

  1806. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1807. 

  1807. 					   DIF_PLL_CTRL3, 0, 31, 0x00008800);
    1808. 

  1808. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1809. 

  1809. 					   DIF_AGC_IF_REF, 0, 31, 0x444C1380);
    1810. 

  1810. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1811. 

  1811. 					   DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
    1812. 

  1812. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1813. 

  1813. 					   DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
    1814. 

  1814. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1815. 

  1815. 					   DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
    1816. 

  1816. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1817. 

  1817. 					   DIF_AGC_IF_INT_CURRENT, 0, 31,
    1818. 

  1818. 					   0x26001700);
    1819. 

  1819. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1820. 

  1820. 					   DIF_AGC_RF_CURRENT, 0, 31,
    1821. 

  1821. 					   0x00002660);
    1822. 

  1822. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1823. 

  1823. 					   DIF_VIDEO_AGC_CTRL, 0, 31,
    1824. 

  1824. 					   0x72500800);
    1825. 

  1825. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1826. 

  1826. 					   DIF_VID_AUD_OVERRIDE, 0, 31,
    1827. 

  1827. 					   0x27000100);
    1828. 

  1828. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1829. 

  1829. 					   DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
    1830. 

  1830. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1831. 

  1831. 					   DIF_COMP_FLT_CTRL, 0, 31,
    1832. 

  1832. 					   0x00000000);
    1833. 

  1833. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1834. 

  1834. 					   DIF_SRC_PHASE_INC, 0, 31,
    1835. 

  1835. 					   0x1befbf06);
    1836. 

  1836. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1837. 

  1837. 					   DIF_SRC_GAIN_CONTROL, 0, 31,
    1838. 

  1838. 					   0x000035e8);
    1839. 

  1839. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1840. 

  1840. 					   DIF_RPT_VARIANCE, 0, 31, 0x00000000);
    1841. 

  1841. 		/* Save the Spec Inversion value */
    1842. 

  1842. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1843. 

  1843. 		dif_misc_ctrl_value |= 0x3a033F11;
    1844. 

  1844. 	} else if (standard & V4L2_STD_PAL_M) {
    1845. 

  1845. 		/* improved Low Frequency Phase Noise */
    1846. 

  1846. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
    1847. 

  1847. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
    1848. 

  1848. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
    1849. 

  1849. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
    1850. 

  1850. 		status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
    1851. 

  1851. 		status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
    1852. 

  1852. 						0x26001700);
    1853. 

  1853. 		status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
    1854. 

  1854. 						0x00002660);
    1855. 

  1855. 		status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
    1856. 

  1856. 						0x72500800);
    1857. 

  1857. 		status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
    1858. 

  1858. 						0x27000100);
    1859. 

  1859. 		status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
    1860. 

  1860. 		status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
    1861. 

  1861. 						0x009f50c1);
    1862. 

  1862. 		status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
    1863. 

  1863. 						0x1befbf06);
    1864. 

  1864. 		status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
    1865. 

  1865. 						0x000035e8);
    1866. 

  1866. 		status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
    1867. 

  1867. 						0x00000000);
    1868. 

  1868. 		/* Save the Spec Inversion value */
    1869. 

  1869. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1870. 

  1870. 		dif_misc_ctrl_value |= 0x3A0A3F10;
    1871. 

  1871. 	} else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
    1872. 

  1872. 		/* improved Low Frequency Phase Noise */
    1873. 

  1873. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
    1874. 

  1874. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
    1875. 

  1875. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
    1876. 

  1876. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
    1877. 

  1877. 		status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
    1878. 

  1878. 		status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
    1879. 

  1879. 						0x26001700);
    1880. 

  1880. 		status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
    1881. 

  1881. 						0x00002660);
    1882. 

  1882. 		status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
    1883. 

  1883. 						0x72500800);
    1884. 

  1884. 		status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
    1885. 

  1885. 						0x27000100);
    1886. 

  1886. 		status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
    1887. 

  1887. 						0x012c405d);
    1888. 

  1888. 		status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
    1889. 

  1889. 						0x009f50c1);
    1890. 

  1890. 		status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
    1891. 

  1891. 						0x1befbf06);
    1892. 

  1892. 		status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
    1893. 

  1893. 						0x000035e8);
    1894. 

  1894. 		status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
    1895. 

  1895. 						0x00000000);
    1896. 

  1896. 		/* Save the Spec Inversion value */
    1897. 

  1897. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1898. 

  1898. 		dif_misc_ctrl_value = 0x3A093F10;
    1899. 

  1899. 	} else if (standard &
    1900. 

  1900. 		  (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
    1901. 

  1901. 		   V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
    1902. 

  1902. 

  1903. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1904. 

  1904. 					   DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
    1905. 

  1905. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1906. 

  1906. 					   DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
    1907. 

  1907. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1908. 

  1908. 					   DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
    1909. 

  1909. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1910. 

  1910. 					   DIF_PLL_CTRL3, 0, 31, 0x00008800);
    1911. 

  1911. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1912. 

  1912. 					   DIF_AGC_IF_REF, 0, 31, 0x888C0380);
    1913. 

  1913. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1914. 

  1914. 					   DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
    1915. 

  1915. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1916. 

  1916. 					   DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
    1917. 

  1917. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1918. 

  1918. 					   DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
    1919. 

  1919. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1920. 

  1920. 					   DIF_AGC_IF_INT_CURRENT, 0, 31,
    1921. 

  1921. 					   0x26001700);
    1922. 

  1922. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1923. 

  1923. 					   DIF_AGC_RF_CURRENT, 0, 31,
    1924. 

  1924. 					   0x00002660);
    1925. 

  1925. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1926. 

  1926. 					   DIF_VID_AUD_OVERRIDE, 0, 31,
    1927. 

  1927. 					   0x27000100);
    1928. 

  1928. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1929. 

  1929. 					   DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
    1930. 

  1930. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1931. 

  1931. 					   DIF_COMP_FLT_CTRL, 0, 31,
    1932. 

  1932. 					   0x00000000);
    1933. 

  1933. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1934. 

  1934. 					   DIF_SRC_PHASE_INC, 0, 31,
    1935. 

  1935. 					   0x1befbf06);
    1936. 

  1936. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1937. 

  1937. 					   DIF_SRC_GAIN_CONTROL, 0, 31,
    1938. 

  1938. 					   0x000035e8);
    1939. 

  1939. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1940. 

  1940. 					   DIF_RPT_VARIANCE, 0, 31, 0x00000000);
    1941. 

  1941. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1942. 

  1942. 					   DIF_VIDEO_AGC_CTRL, 0, 31,
    1943. 

  1943. 					   0xf4000000);
    1944. 

  1944. 

  1945. 		/* Save the Spec Inversion value */
    1946. 

  1946. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1947. 

  1947. 		dif_misc_ctrl_value |= 0x3a023F11;
    1948. 

  1948. 	} else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
    1949. 

  1949. 		/* Is it SECAM_L1? */
    1950. 

  1950. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1951. 

  1951. 					   DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
    1952. 

  1952. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1953. 

  1953. 					   DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
    1954. 

  1954. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1955. 

  1955. 					   DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
    1956. 

  1956. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1957. 

  1957. 					   DIF_PLL_CTRL3, 0, 31, 0x00008800);
    1958. 

  1958. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1959. 

  1959. 					   DIF_AGC_IF_REF, 0, 31, 0x888C0380);
    1960. 

  1960. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1961. 

  1961. 					   DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
    1962. 

  1962. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1963. 

  1963. 					   DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
    1964. 

  1964. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1965. 

  1965. 					   DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
    1966. 

  1966. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1967. 

  1967. 					   DIF_AGC_IF_INT_CURRENT, 0, 31,
    1968. 

  1968. 					   0x26001700);
    1969. 

  1969. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1970. 

  1970. 					   DIF_AGC_RF_CURRENT, 0, 31,
    1971. 

  1971. 					   0x00002660);
    1972. 

  1972. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1973. 

  1973. 					   DIF_VID_AUD_OVERRIDE, 0, 31,
    1974. 

  1974. 					   0x27000100);
    1975. 

  1975. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1976. 

  1976. 					   DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
    1977. 

  1977. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1978. 

  1978. 					   DIF_COMP_FLT_CTRL, 0, 31,
    1979. 

  1979. 					   0x00000000);
    1980. 

  1980. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1981. 

  1981. 					   DIF_SRC_PHASE_INC, 0, 31,
    1982. 

  1982. 					   0x1befbf06);
    1983. 

  1983. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1984. 

  1984. 					   DIF_SRC_GAIN_CONTROL, 0, 31,
    1985. 

  1985. 					   0x000035e8);
    1986. 

  1986. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1987. 

  1987. 					   DIF_RPT_VARIANCE, 0, 31, 0x00000000);
    1988. 

  1988. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    1989. 

  1989. 					   DIF_VIDEO_AGC_CTRL, 0, 31,
    1990. 

  1990. 					   0xf2560000);
    1991. 

  1991. 

  1992. 		/* Save the Spec Inversion value */
    1993. 

  1993. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    1994. 

  1994. 		dif_misc_ctrl_value |= 0x3a023F11;
    1995. 

  1995. 

  1996. 	} else if (standard & V4L2_STD_NTSC_M) {
    1997. 

  1997. 		/* V4L2_STD_NTSC_M (75 IRE Setup) Or
    1998. 

  1998. 		   V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
    1999. 

  1999. 

  2000. 		/* For NTSC the centre frequency of video coming out of
    2001. 

  2001. 		   sidewinder is around 7.1MHz or 3.6MHz depending on the
    2002. 

  2002. 		   spectral inversion. so for a non spectrally inverted channel
    2003. 

  2003. 		   the pll freq word is 0x03420c49
    2004. 

  2004. 		 */
    2005. 

  2005. 

  2006. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
    2007. 

  2007. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
    2008. 

  2008. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
    2009. 

  2009. 		status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
    2010. 

  2010. 		status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
    2011. 

  2011. 		status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
    2012. 

  2012. 						0x26001700);
    2013. 

  2013. 		status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
    2014. 

  2014. 						0x00002660);
    2015. 

  2015. 		status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
    2016. 

  2016. 						0x04000800);
    2017. 

  2017. 		status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
    2018. 

  2018. 						0x27000100);
    2019. 

  2019. 		status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
    2020. 

  2020. 

  2021. 		status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
    2022. 

  2022. 						0x009f50c1);
    2023. 

  2023. 		status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
    2024. 

  2024. 						0x1befbf06);
    2025. 

  2025. 		status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
    2026. 

  2026. 						0x000035e8);
    2027. 

  2027. 

  2028. 		status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
    2029. 

  2029. 		status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
    2030. 

  2030. 						0xC2262600);
    2031. 

  2031. 		status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
    2032. 

  2032. 

  2033. 		/* Save the Spec Inversion value */
    2034. 

  2034. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    2035. 

  2035. 		dif_misc_ctrl_value |= 0x3a003F10;
    2036. 

  2036. 	} else {
    2037. 

  2037. 		/* default PAL BG */
    2038. 

  2038. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2039. 

  2039. 					   DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
    2040. 

  2040. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2041. 

  2041. 					   DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
    2042. 

  2042. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2043. 

  2043. 					   DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
    2044. 

  2044. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2045. 

  2045. 					   DIF_PLL_CTRL3, 0, 31, 0x00008800);
    2046. 

  2046. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2047. 

  2047. 					   DIF_AGC_IF_REF, 0, 31, 0x444C1380);
    2048. 

  2048. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2049. 

  2049. 					   DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
    2050. 

  2050. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2051. 

  2051. 					   DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
    2052. 

  2052. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2053. 

  2053. 					   DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
    2054. 

  2054. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2055. 

  2055. 					   DIF_AGC_IF_INT_CURRENT, 0, 31,
    2056. 

  2056. 					   0x26001700);
    2057. 

  2057. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2058. 

  2058. 					   DIF_AGC_RF_CURRENT, 0, 31,
    2059. 

  2059. 					   0x00002660);
    2060. 

  2060. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2061. 

  2061. 					   DIF_VIDEO_AGC_CTRL, 0, 31,
    2062. 

  2062. 					   0x72500800);
    2063. 

  2063. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2064. 

  2064. 					   DIF_VID_AUD_OVERRIDE, 0, 31,
    2065. 

  2065. 					   0x27000100);
    2066. 

  2066. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2067. 

  2067. 					   DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
    2068. 

  2068. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2069. 

  2069. 					   DIF_COMP_FLT_CTRL, 0, 31,
    2070. 

  2070. 					   0x00A653A8);
    2071. 

  2071. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2072. 

  2072. 					   DIF_SRC_PHASE_INC, 0, 31,
    2073. 

  2073. 					   0x1befbf06);
    2074. 

  2074. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2075. 

  2075. 					   DIF_SRC_GAIN_CONTROL, 0, 31,
    2076. 

  2076. 					   0x000035e8);
    2077. 

  2077. 		status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
    2078. 

  2078. 					   DIF_RPT_VARIANCE, 0, 31, 0x00000000);
    2079. 

  2079. 		/* Save the Spec Inversion value */
    2080. 

  2080. 		dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
    2081. 

  2081. 		dif_misc_ctrl_value |= 0x3a013F11;
    2082. 

  2082. 	}
    2083. 

  2083. 

  2084. 	/* The AGC values should be the same for all standards,
    2085. 

  2085. 	   AUD_SRC_SEL[19] should always be disabled    */
    2086. 

  2086. 	dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
    2087. 

  2087. 

  2088. 	/* It is still possible to get Set Standard calls even when we
    2089. 

  2089. 	   are in FM mode.
    2090. 

  2090. 	   This is done to override the value for FM. */
    2091. 

  2091. 	if (dev->active_mode == V4L2_TUNER_RADIO)
    2092. 

  2092. 		dif_misc_ctrl_value = 0x7a080000;
    2093. 

  2093. 

  2094. 	/* Write the calculated value for misc ontrol register      */
    2095. 

  2095. 	status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
    2096. 

  2096. 

  2097. 	return status;
    2098. 

  2098. }
    2099. 

  2099. 

  2100. int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
    2101. 

  2101. {
    2102. 

  2102. 	int status = 0;
    2103. 

  2103. 	u32 dwval;
    2104. 

  2104. 

  2105. 	/* Set the RF and IF k_agc values to 3 */
    2106. 

  2106. 	status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
    2107. 

  2107. 	dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
    2108. 

  2108. 	dwval |= 0x33000000;
    2109. 

  2109. 

  2110. 	status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
    2111. 

  2111. 

  2112. 	return status;
    2113. 

  2113. }
    2114. 

  2114. 

  2115. int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
    2116. 

  2116. {
    2117. 

  2117. 	int status = 0;
    2118. 

  2118. 	u32 dwval;
    2119. 

  2119. 	cx231xx_info("cx231xx_tuner_post_channel_change  dev->tuner_type =0%d\n",
    2120. 

  2120. 		     dev->tuner_type);
    2121. 

  2121. 	/* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
    2122. 

  2122. 	 * SECAM L/B/D standards */
    2123. 

  2123. 	status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
    2124. 

  2124. 	dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
    2125. 

  2125. 

  2126. 	if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
    2127. 

  2127. 			 V4L2_STD_SECAM_D)) {
    2128. 

  2128. 			if (dev->tuner_type == TUNER_NXP_TDA18271) {
    2129. 

  2129. 				dwval &= ~FLD_DIF_IF_REF;
    2130. 

  2130. 				dwval |= 0x88000300;
    2131. 

  2131. 			} else
    2132. 

  2132. 				dwval |= 0x88000000;
    2133. 

  2133. 		} else {
    2134. 

  2134. 			if (dev->tuner_type == TUNER_NXP_TDA18271) {
    2135. 

  2135. 				dwval &= ~FLD_DIF_IF_REF;
    2136. 

  2136. 				dwval |= 0xCC000300;
    2137. 

  2137. 			} else
    2138. 

  2138. 				dwval |= 0x44000000;
    2139. 

  2139. 		}
    2140. 

  2140. 

  2141. 	status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
    2142. 

  2142. 

  2143. 	return status;
    2144. 

  2144. }
    2145. 

  2145. 

  2146. /******************************************************************************
    2147. 

  2147.  *        	    I 2 S - B L O C K    C O N T R O L   functions            *
    2148. 

  2148.  ******************************************************************************/
    2149. 

  2149. int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
    2150. 

  2150. {
    2151. 

  2151. 	int status = 0;
    2152. 

  2152. 	u32 value;
    2153. 

  2153. 

  2154. 	status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2155. 

  2155. 				       CH_PWR_CTRL1, 1, &value, 1);
    2156. 

  2156. 	/* enables clock to delta-sigma and decimation filter */
    2157. 

  2157. 	value |= 0x80;
    2158. 

  2158. 	status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2159. 

  2159. 					CH_PWR_CTRL1, 1, value, 1);
    2160. 

  2160. 	/* power up all channel */
    2161. 

  2161. 	status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2162. 

  2162. 					CH_PWR_CTRL2, 1, 0x00, 1);
    2163. 

  2163. 

  2164. 	return status;
    2165. 

  2165. }
    2166. 

  2166. 

  2167. int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
    2168. 

  2168. 					enum AV_MODE avmode)
    2169. 

  2169. {
    2170. 

  2170. 	int status = 0;
    2171. 

  2171. 	u32 value = 0;
    2172. 

  2172. 

  2173. 	if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
    2174. 

  2174. 		status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2175. 

  2175. 					  CH_PWR_CTRL2, 1, &value, 1);
    2176. 

  2176. 		value |= 0xfe;
    2177. 

  2177. 		status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2178. 

  2178. 						CH_PWR_CTRL2, 1, value, 1);
    2179. 

  2179. 	} else {
    2180. 

  2180. 		status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2181. 

  2181. 						CH_PWR_CTRL2, 1, 0x00, 1);
    2182. 

  2182. 	}
    2183. 

  2183. 

  2184. 	return status;
    2185. 

  2185. }
    2186. 

  2186. 

  2187. /* set i2s_blk for audio input types */
    2188. 

  2188. int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
    2189. 

  2189. {
    2190. 

  2190. 	int status = 0;
    2191. 

  2191. 

  2192. 	switch (audio_input) {
    2193. 

  2193. 	case CX231XX_AMUX_LINE_IN:
    2194. 

  2194. 		status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2195. 

  2195. 						CH_PWR_CTRL2, 1, 0x00, 1);
    2196. 

  2196. 		status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
    2197. 

  2197. 						CH_PWR_CTRL1, 1, 0x80, 1);
    2198. 

  2198. 		break;
    2199. 

  2199. 	case CX231XX_AMUX_VIDEO:
    2200. 

  2200. 	default:
    2201. 

  2201. 		break;
    2202. 

  2202. 	}
    2203. 

  2203. 

  2204. 	dev->ctl_ainput = audio_input;
    2205. 

  2205. 

  2206. 	return status;
    2207. 

  2207. }
    2208. 

  2208. 

  2209. /******************************************************************************
    2210. 

  2210.  *                  P O W E R      C O N T R O L   functions                  *
    2211. 

  2211.  ******************************************************************************/
    2212. 

  2212. int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
    2213. 

  2213. {
    2214. 

  2214. 	u8 value[4] = { 0, 0, 0, 0 };
    2215. 

  2215. 	u32 tmp = 0;
    2216. 

  2216. 	int status = 0;
    2217. 

  2217. 

  2218. 	if (dev->power_mode != mode)
    2219. 

  2219. 		dev->power_mode = mode;
    2220. 

  2220. 	else {
    2221. 

  2221. 		cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
    2222. 

  2222. 			     mode);
    2223. 

  2223. 		return 0;
    2224. 

  2224. 	}
    2225. 

  2225. 

  2226. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
    2227. 

  2227. 				       4);
    2228. 

  2228. 	if (status < 0)
    2229. 

  2229. 		return status;
    2230. 

  2230. 

  2231. 	tmp = *((u32 *) value);
    2232. 

  2232. 

  2233. 	switch (mode) {
    2234. 

  2234. 	case POLARIS_AVMODE_ENXTERNAL_AV:
    2235. 

  2235. 

  2236. 		tmp &= (~PWR_MODE_MASK);
    2237. 

  2237. 

  2238. 		tmp |= PWR_AV_EN;
    2239. 

  2239. 		value[0] = (u8) tmp;
    2240. 

  2240. 		value[1] = (u8) (tmp >> 8);
    2241. 

  2241. 		value[2] = (u8) (tmp >> 16);
    2242. 

  2242. 		value[3] = (u8) (tmp >> 24);
    2243. 

  2243. 		status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2244. 

  2244. 						PWR_CTL_EN, value, 4);
    2245. 

  2245. 		msleep(PWR_SLEEP_INTERVAL);
    2246. 

  2246. 

  2247. 		tmp |= PWR_ISO_EN;
    2248. 

  2248. 		value[0] = (u8) tmp;
    2249. 

  2249. 		value[1] = (u8) (tmp >> 8);
    2250. 

  2250. 		value[2] = (u8) (tmp >> 16);
    2251. 

  2251. 		value[3] = (u8) (tmp >> 24);
    2252. 

  2252. 		status =
    2253. 

  2253. 		    cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
    2254. 

  2254. 					   value, 4);
    2255. 

  2255. 		msleep(PWR_SLEEP_INTERVAL);
    2256. 

  2256. 

  2257. 		tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
    2258. 

  2258. 		value[0] = (u8) tmp;
    2259. 

  2259. 		value[1] = (u8) (tmp >> 8);
    2260. 

  2260. 		value[2] = (u8) (tmp >> 16);
    2261. 

  2261. 		value[3] = (u8) (tmp >> 24);
    2262. 

  2262. 		status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2263. 

  2263. 						PWR_CTL_EN, value, 4);
    2264. 

  2264. 

  2265. 		/* reset state of xceive tuner */
    2266. 

  2266. 		dev->xc_fw_load_done = 0;
    2267. 

  2267. 		break;
    2268. 

  2268. 

  2269. 	case POLARIS_AVMODE_ANALOGT_TV:
    2270. 

  2270. 

  2271. 		tmp |= PWR_DEMOD_EN;
    2272. 

  2272. 		tmp |= (I2C_DEMOD_EN);
    2273. 

  2273. 		value[0] = (u8) tmp;
    2274. 

  2274. 		value[1] = (u8) (tmp >> 8);
    2275. 

  2275. 		value[2] = (u8) (tmp >> 16);
    2276. 

  2276. 		value[3] = (u8) (tmp >> 24);
    2277. 

  2277. 		status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2278. 

  2278. 						PWR_CTL_EN, value, 4);
    2279. 

  2279. 		msleep(PWR_SLEEP_INTERVAL);
    2280. 

  2280. 

  2281. 		if (!(tmp & PWR_TUNER_EN)) {
    2282. 

  2282. 			tmp |= (PWR_TUNER_EN);
    2283. 

  2283. 			value[0] = (u8) tmp;
    2284. 

  2284. 			value[1] = (u8) (tmp >> 8);
    2285. 

  2285. 			value[2] = (u8) (tmp >> 16);
    2286. 

  2286. 			value[3] = (u8) (tmp >> 24);
    2287. 

  2287. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2288. 

  2288. 							PWR_CTL_EN, value, 4);
    2289. 

  2289. 			msleep(PWR_SLEEP_INTERVAL);
    2290. 

  2290. 		}
    2291. 

  2291. 

  2292. 		if (!(tmp & PWR_AV_EN)) {
    2293. 

  2293. 			tmp |= PWR_AV_EN;
    2294. 

  2294. 			value[0] = (u8) tmp;
    2295. 

  2295. 			value[1] = (u8) (tmp >> 8);
    2296. 

  2296. 			value[2] = (u8) (tmp >> 16);
    2297. 

  2297. 			value[3] = (u8) (tmp >> 24);
    2298. 

  2298. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2299. 

  2299. 							PWR_CTL_EN, value, 4);
    2300. 

  2300. 			msleep(PWR_SLEEP_INTERVAL);
    2301. 

  2301. 		}
    2302. 

  2302. 		if (!(tmp & PWR_ISO_EN)) {
    2303. 

  2303. 			tmp |= PWR_ISO_EN;
    2304. 

  2304. 			value[0] = (u8) tmp;
    2305. 

  2305. 			value[1] = (u8) (tmp >> 8);
    2306. 

  2306. 			value[2] = (u8) (tmp >> 16);
    2307. 

  2307. 			value[3] = (u8) (tmp >> 24);
    2308. 

  2308. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2309. 

  2309. 							PWR_CTL_EN, value, 4);
    2310. 

  2310. 			msleep(PWR_SLEEP_INTERVAL);
    2311. 

  2311. 		}
    2312. 

  2312. 

  2313. 		if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
    2314. 

  2314. 			tmp |= POLARIS_AVMODE_ANALOGT_TV;
    2315. 

  2315. 			value[0] = (u8) tmp;
    2316. 

  2316. 			value[1] = (u8) (tmp >> 8);
    2317. 

  2317. 			value[2] = (u8) (tmp >> 16);
    2318. 

  2318. 			value[3] = (u8) (tmp >> 24);
    2319. 

  2319. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2320. 

  2320. 							PWR_CTL_EN, value, 4);
    2321. 

  2321. 			msleep(PWR_SLEEP_INTERVAL);
    2322. 

  2322. 		}
    2323. 

  2323. 

  2324. 		if (dev->board.tuner_type != TUNER_ABSENT) {
    2325. 

  2325. 			/* Enable tuner */
    2326. 

  2326. 			cx231xx_enable_i2c_port_3(dev, true);
    2327. 

  2327. 

  2328. 			/* reset the Tuner */
    2329. 

  2329. 			if (dev->board.tuner_gpio)
    2330. 

  2330. 				cx231xx_gpio_set(dev, dev->board.tuner_gpio);
    2331. 

  2331. 

  2332. 			if (dev->cx231xx_reset_analog_tuner)
    2333. 

  2333. 				dev->cx231xx_reset_analog_tuner(dev);
    2334. 

  2334. 		}
    2335. 

  2335. 

  2336. 		break;
    2337. 

  2337. 

  2338. 	case POLARIS_AVMODE_DIGITAL:
    2339. 

  2339. 		if (!(tmp & PWR_TUNER_EN)) {
    2340. 

  2340. 			tmp |= (PWR_TUNER_EN);
    2341. 

  2341. 			value[0] = (u8) tmp;
    2342. 

  2342. 			value[1] = (u8) (tmp >> 8);
    2343. 

  2343. 			value[2] = (u8) (tmp >> 16);
    2344. 

  2344. 			value[3] = (u8) (tmp >> 24);
    2345. 

  2345. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2346. 

  2346. 							PWR_CTL_EN, value, 4);
    2347. 

  2347. 			msleep(PWR_SLEEP_INTERVAL);
    2348. 

  2348. 		}
    2349. 

  2349. 		if (!(tmp & PWR_AV_EN)) {
    2350. 

  2350. 			tmp |= PWR_AV_EN;
    2351. 

  2351. 			value[0] = (u8) tmp;
    2352. 

  2352. 			value[1] = (u8) (tmp >> 8);
    2353. 

  2353. 			value[2] = (u8) (tmp >> 16);
    2354. 

  2354. 			value[3] = (u8) (tmp >> 24);
    2355. 

  2355. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2356. 

  2356. 							PWR_CTL_EN, value, 4);
    2357. 

  2357. 			msleep(PWR_SLEEP_INTERVAL);
    2358. 

  2358. 		}
    2359. 

  2359. 		if (!(tmp & PWR_ISO_EN)) {
    2360. 

  2360. 			tmp |= PWR_ISO_EN;
    2361. 

  2361. 			value[0] = (u8) tmp;
    2362. 

  2362. 			value[1] = (u8) (tmp >> 8);
    2363. 

  2363. 			value[2] = (u8) (tmp >> 16);
    2364. 

  2364. 			value[3] = (u8) (tmp >> 24);
    2365. 

  2365. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2366. 

  2366. 							PWR_CTL_EN, value, 4);
    2367. 

  2367. 			msleep(PWR_SLEEP_INTERVAL);
    2368. 

  2368. 		}
    2369. 

  2369. 

  2370. 		tmp &= (~PWR_AV_MODE);
    2371. 

  2371. 		tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
    2372. 

  2372. 		value[0] = (u8) tmp;
    2373. 

  2373. 		value[1] = (u8) (tmp >> 8);
    2374. 

  2374. 		value[2] = (u8) (tmp >> 16);
    2375. 

  2375. 		value[3] = (u8) (tmp >> 24);
    2376. 

  2376. 		status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2377. 

  2377. 						PWR_CTL_EN, value, 4);
    2378. 

  2378. 		msleep(PWR_SLEEP_INTERVAL);
    2379. 

  2379. 

  2380. 		if (!(tmp & PWR_DEMOD_EN)) {
    2381. 

  2381. 			tmp |= PWR_DEMOD_EN;
    2382. 

  2382. 			value[0] = (u8) tmp;
    2383. 

  2383. 			value[1] = (u8) (tmp >> 8);
    2384. 

  2384. 			value[2] = (u8) (tmp >> 16);
    2385. 

  2385. 			value[3] = (u8) (tmp >> 24);
    2386. 

  2386. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2387. 

  2387. 							PWR_CTL_EN, value, 4);
    2388. 

  2388. 			msleep(PWR_SLEEP_INTERVAL);
    2389. 

  2389. 		}
    2390. 

  2390. 

  2391. 		if (dev->board.tuner_type != TUNER_ABSENT) {
    2392. 

  2392. 			/*
    2393. 

  2393. 			 * Enable tuner
    2394. 

  2394. 			 *	Hauppauge Exeter seems to need to do something different!
    2395. 

  2395. 			 */
    2396. 

  2396. 			if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)
    2397. 

  2397. 				cx231xx_enable_i2c_port_3(dev, false);
    2398. 

  2398. 			else
    2399. 

  2399. 				cx231xx_enable_i2c_port_3(dev, true);
    2400. 

  2400. 

  2401. 			/* reset the Tuner */
    2402. 

  2402. 			if (dev->board.tuner_gpio)
    2403. 

  2403. 				cx231xx_gpio_set(dev, dev->board.tuner_gpio);
    2404. 

  2404. 

  2405. 			if (dev->cx231xx_reset_analog_tuner)
    2406. 

  2406. 				dev->cx231xx_reset_analog_tuner(dev);
    2407. 

  2407. 		}
    2408. 

  2408. 		break;
    2409. 

  2409. 

  2410. 	default:
    2411. 

  2411. 		break;
    2412. 

  2412. 	}
    2413. 

  2413. 

  2414. 	msleep(PWR_SLEEP_INTERVAL);
    2415. 

  2415. 

  2416. 	/* For power saving, only enable Pwr_resetout_n
    2417. 

  2417. 	   when digital TV is selected. */
    2418. 

  2418. 	if (mode == POLARIS_AVMODE_DIGITAL) {
    2419. 

  2419. 		tmp |= PWR_RESETOUT_EN;
    2420. 

  2420. 		value[0] = (u8) tmp;
    2421. 

  2421. 		value[1] = (u8) (tmp >> 8);
    2422. 

  2422. 		value[2] = (u8) (tmp >> 16);
    2423. 

  2423. 		value[3] = (u8) (tmp >> 24);
    2424. 

  2424. 		status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2425. 

  2425. 						PWR_CTL_EN, value, 4);
    2426. 

  2426. 		msleep(PWR_SLEEP_INTERVAL);
    2427. 

  2427. 	}
    2428. 

  2428. 

  2429. 	/* update power control for afe */
    2430. 

  2430. 	status = cx231xx_afe_update_power_control(dev, mode);
    2431. 

  2431. 

  2432. 	/* update power control for i2s_blk */
    2433. 

  2433. 	status = cx231xx_i2s_blk_update_power_control(dev, mode);
    2434. 

  2434. 

  2435. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
    2436. 

  2436. 				       4);
    2437. 

  2437. 

  2438. 	return status;
    2439. 

  2439. }
    2440. 

  2440. 

  2441. int cx231xx_power_suspend(struct cx231xx *dev)
    2442. 

  2442. {
    2443. 

  2443. 	u8 value[4] = { 0, 0, 0, 0 };
    2444. 

  2444. 	u32 tmp = 0;
    2445. 

  2445. 	int status = 0;
    2446. 

  2446. 

  2447. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
    2448. 

  2448. 				       value, 4);
    2449. 

  2449. 	if (status > 0)
    2450. 

  2450. 		return status;
    2451. 

  2451. 

  2452. 	tmp = *((u32 *) value);
    2453. 

  2453. 	tmp &= (~PWR_MODE_MASK);
    2454. 

  2454. 

  2455. 	value[0] = (u8) tmp;
    2456. 

  2456. 	value[1] = (u8) (tmp >> 8);
    2457. 

  2457. 	value[2] = (u8) (tmp >> 16);
    2458. 

  2458. 	value[3] = (u8) (tmp >> 24);
    2459. 

  2459. 	status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
    2460. 

  2460. 					value, 4);
    2461. 

  2461. 

  2462. 	return status;
    2463. 

  2463. }
    2464. 

  2464. 

  2465. /******************************************************************************
    2466. 

  2466.  *                  S T R E A M    C O N T R O L   functions                  *
    2467. 

  2467.  ******************************************************************************/
    2468. 

  2468. int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
    2469. 

  2469. {
    2470. 

  2470. 	u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
    2471. 

  2471. 	u32 tmp = 0;
    2472. 

  2472. 	int status = 0;
    2473. 

  2473. 

  2474. 	cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
    2475. 

  2475. 	status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
    2476. 

  2476. 				       value, 4);
    2477. 

  2477. 	if (status < 0)
    2478. 

  2478. 		return status;
    2479. 

  2479. 

  2480. 	tmp = *((u32 *) value);
    2481. 

  2481. 	tmp |= ep_mask;
    2482. 

  2482. 	value[0] = (u8) tmp;
    2483. 

  2483. 	value[1] = (u8) (tmp >> 8);
    2484. 

  2484. 	value[2] = (u8) (tmp >> 16);
    2485. 

  2485. 	value[3] = (u8) (tmp >> 24);
    2486. 

  2486. 

  2487. 	status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
    2488. 

  2488. 					value, 4);
    2489. 

  2489. 

  2490. 	return status;
    2491. 

  2491. }
    2492. 

  2492. 

  2493. int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
    2494. 

  2494. {
    2495. 

  2495. 	u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
    2496. 

  2496. 	u32 tmp = 0;
    2497. 

  2497. 	int status = 0;
    2498. 

  2498. 

  2499. 	cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
    2500. 

  2500. 	status =
    2501. 

  2501. 	    cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
    2502. 

  2502. 	if (status < 0)
    2503. 

  2503. 		return status;
    2504. 

  2504. 

  2505. 	tmp = *((u32 *) value);
    2506. 

  2506. 	tmp &= (~ep_mask);
    2507. 

  2507. 	value[0] = (u8) tmp;
    2508. 

  2508. 	value[1] = (u8) (tmp >> 8);
    2509. 

  2509. 	value[2] = (u8) (tmp >> 16);
    2510. 

  2510. 	value[3] = (u8) (tmp >> 24);
    2511. 

  2511. 

  2512. 	status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
    2513. 

  2513. 					value, 4);
    2514. 

  2514. 

  2515. 	return status;
    2516. 

  2516. }
    2517. 

  2517. 

  2518. int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
    2519. 

  2519. {
    2520. 

  2520. 	int status = 0;
    2521. 

  2521. 	u32 value = 0;
    2522. 

  2522. 	u8 val[4] = { 0, 0, 0, 0 };
    2523. 

  2523. 

  2524. 	if (dev->udev->speed == USB_SPEED_HIGH) {
    2525. 

  2525. 		switch (media_type) {
    2526. 

  2526. 		case 81: /* audio */
    2527. 

  2527. 			cx231xx_info("%s: Audio enter HANC\n", __func__);
    2528. 

  2528. 			status =
    2529. 

  2529. 			    cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
    2530. 

  2530. 			break;
    2531. 

  2531. 

  2532. 		case 2:	/* vbi */
    2533. 

  2533. 			cx231xx_info("%s: set vanc registers\n", __func__);
    2534. 

  2534. 			status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
    2535. 

  2535. 			break;
    2536. 

  2536. 

  2537. 		case 3:	/* sliced cc */
    2538. 

  2538. 			cx231xx_info("%s: set hanc registers\n", __func__);
    2539. 

  2539. 			status =
    2540. 

  2540. 			    cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
    2541. 

  2541. 			break;
    2542. 

  2542. 

  2543. 		case 0:	/* video */
    2544. 

  2544. 			cx231xx_info("%s: set video registers\n", __func__);
    2545. 

  2545. 			status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
    2546. 

  2546. 			break;
    2547. 

  2547. 

  2548. 		case 4:	/* ts1 */
    2549. 

  2549. 			cx231xx_info("%s: set ts1 registers", __func__);
    2550. 

  2550. 

  2551. 		if (dev->board.has_417) {
    2552. 

  2552. 			cx231xx_info(" MPEG\n");
    2553. 

  2553. 			value &= 0xFFFFFFFC;
    2554. 

  2554. 			value |= 0x3;
    2555. 

  2555. 

  2556. 			status = cx231xx_mode_register(dev, TS_MODE_REG, value);
    2557. 

  2557. 

  2558. 			val[0] = 0x04;
    2559. 

  2559. 			val[1] = 0xA3;
    2560. 

  2560. 			val[2] = 0x3B;
    2561. 

  2561. 			val[3] = 0x00;
    2562. 

  2562. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2563. 

  2563. 				 TS1_CFG_REG, val, 4);
    2564. 

  2564. 

  2565. 			val[0] = 0x00;
    2566. 

  2566. 			val[1] = 0x08;
    2567. 

  2567. 			val[2] = 0x00;
    2568. 

  2568. 			val[3] = 0x08;
    2569. 

  2569. 			status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
    2570. 

  2570. 				 TS1_LENGTH_REG, val, 4);
    2571. 

  2571. 

  2572. 		} else {
    2573. 

  2573. 			cx231xx_info(" BDA\n");
    2574. 

  2574. 			status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
    2575. 

  2575. 			status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
    2576. 

  2576. 		}
    2577. 

  2577. 			break;
    2578. 

  2578. 

  2579. 		case 6:	/* ts1 parallel mode */
    2580. 

  2580. 			cx231xx_info("%s: set ts1 parallel mode registers\n",
    2581. 

  2581. 				     __func__);
    2582. 

  2582. 			status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
    2583. 

  2583. 			status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
    2584. 

  2584. 			break;
    2585. 

  2585. 		}
    2586. 

  2586. 	} else {
    2587. 

  2587. 		status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
    2588. 

  2588. 	}
    2589. 

  2589. 

  2590. 	return status;
    2591. 

  2591. }
    2592. 

  2592. 

  2593. int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
    2594. 

  2594. {
    2595. 

  2595. 	int rc = -1;
    2596. 

  2596. 	u32 ep_mask = -1;
    2597. 

  2597. 	struct pcb_config *pcb_config;
    2598. 

  2598. 

  2599. 	/* get EP for media type */
    2600. 

  2600. 	pcb_config = (struct pcb_config *)&dev->current_pcb_config;
    2601. 

  2601. 

  2602. 	if (pcb_config->config_num == 1) {
    2603. 

  2603. 		switch (media_type) {
    2604. 

  2604. 		case 0:	/* Video */
    2605. 

  2605. 			ep_mask = ENABLE_EP4;	/* ep4  [00:1000] */
    2606. 

  2606. 			break;
    2607. 

  2607. 		case 1:	/* Audio */
    2608. 

  2608. 			ep_mask = ENABLE_EP3;	/* ep3  [00:0100] */
    2609. 

  2609. 			break;
    2610. 

  2610. 		case 2:	/* Vbi */
    2611. 

  2611. 			ep_mask = ENABLE_EP5;	/* ep5 [01:0000] */
    2612. 

  2612. 			break;
    2613. 

  2613. 		case 3:	/* Sliced_cc */
    2614. 

  2614. 			ep_mask = ENABLE_EP6;	/* ep6 [10:0000] */
    2615. 

  2615. 			break;
    2616. 

  2616. 		case 4:	/* ts1 */
    2617. 

  2617. 		case 6:	/* ts1 parallel mode */
    2618. 

  2618. 			ep_mask = ENABLE_EP1;	/* ep1 [00:0001] */
    2619. 

  2619. 			break;
    2620. 

  2620. 		case 5:	/* ts2 */
    2621. 

  2621. 			ep_mask = ENABLE_EP2;	/* ep2 [00:0010] */
    2622. 

  2622. 			break;
    2623. 

  2623. 		}
    2624. 

  2624. 

  2625. 	} else if (pcb_config->config_num > 1) {
    2626. 

  2626. 		switch (media_type) {
    2627. 

  2627. 		case 0:	/* Video */
    2628. 

  2628. 			ep_mask = ENABLE_EP4;	/* ep4  [00:1000] */
    2629. 

  2629. 			break;
    2630. 

  2630. 		case 1:	/* Audio */
    2631. 

  2631. 			ep_mask = ENABLE_EP3;	/* ep3  [00:0100] */
    2632. 

  2632. 			break;
    2633. 

  2633. 		case 2:	/* Vbi */
    2634. 

  2634. 			ep_mask = ENABLE_EP5;	/* ep5 [01:0000] */
    2635. 

  2635. 			break;
    2636. 

  2636. 		case 3:	/* Sliced_cc */
    2637. 

  2637. 			ep_mask = ENABLE_EP6;	/* ep6 [10:0000] */
    2638. 

  2638. 			break;
    2639. 

  2639. 		case 4:	/* ts1 */
    2640. 

  2640. 		case 6:	/* ts1 parallel mode */
    2641. 

  2641. 			ep_mask = ENABLE_EP1;	/* ep1 [00:0001] */
    2642. 

  2642. 			break;
    2643. 

  2643. 		case 5:	/* ts2 */
    2644. 

  2644. 			ep_mask = ENABLE_EP2;	/* ep2 [00:0010] */
    2645. 

  2645. 			break;
    2646. 

  2646. 		}
    2647. 

  2647. 

  2648. 	}
    2649. 

  2649. 

  2650. 	if (start) {
    2651. 

  2651. 		rc = cx231xx_initialize_stream_xfer(dev, media_type);
    2652. 

  2652. 

  2653. 		if (rc < 0)
    2654. 

  2654. 			return rc;
    2655. 

  2655. 

  2656. 		/* enable video capture */
    2657. 

  2657. 		if (ep_mask > 0)
    2658. 

  2658. 			rc = cx231xx_start_stream(dev, ep_mask);
    2659. 

  2659. 	} else {
    2660. 

  2660. 		/* disable video capture */
    2661. 

  2661. 		if (ep_mask > 0)
    2662. 

  2662. 			rc = cx231xx_stop_stream(dev, ep_mask);
    2663. 

  2663. 	}
    2664. 

  2664. 

  2665. 	if (dev->mode == CX231XX_ANALOG_MODE)
    2666. 

  2666. 		;/* do any in Analog mode */
    2667. 

  2667. 	else
    2668. 

  2668. 		;/* do any in digital mode */
    2669. 

  2669. 

  2670. 	return rc;
    2671. 

  2671. }
    2672. 

  2672. EXPORT_SYMBOL_GPL(cx231xx_capture_start);
    2673. 

  2673. 

  2674. /*****************************************************************************
    2675. 

  2675. *                   G P I O   B I T control functions                        *
    2676. 

  2676. ******************************************************************************/
    2677. 

  2677. int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
    2678. 

  2678. {
    2679. 

  2679. 	int status = 0;
    2680. 

  2680. 

  2681. 	status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
    2682. 

  2682. 

  2683. 	return status;
    2684. 

  2684. }
    2685. 

  2685. 

  2686. int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
    2687. 

  2687. {
    2688. 

  2688. 	int status = 0;
    2689. 

  2689. 

  2690. 	status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
    2691. 

  2691. 

  2692. 	return status;
    2693. 

  2693. }
    2694. 

  2694. 

  2695. /*
    2696. 

  2696. * cx231xx_set_gpio_direction
    2697. 

  2697. *      Sets the direction of the GPIO pin to input or output
    2698. 

  2698. *
    2699. 

  2699. * Parameters :
    2700. 

  2700. *      pin_number : The GPIO Pin number to program the direction for
    2701. 

  2701. *                   from 0 to 31
    2702. 

  2702. *      pin_value : The Direction of the GPIO Pin under reference.
    2703. 

  2703. *                      0 = Input direction
    2704. 

  2704. *                      1 = Output direction
    2705. 

  2705. */
    2706. 

  2706. int cx231xx_set_gpio_direction(struct cx231xx *dev,
    2707. 

  2707. 			       int pin_number, int pin_value)
    2708. 

  2708. {
    2709. 

  2709. 	int status = 0;
    2710. 

  2710. 	u32 value = 0;
    2711. 

  2711. 

  2712. 	/* Check for valid pin_number - if 32 , bail out */
    2713. 

  2713. 	if (pin_number >= 32)
    2714. 

  2714. 		return -EINVAL;
    2715. 

  2715. 

  2716. 	/* input */
    2717. 

  2717. 	if (pin_value == 0)
    2718. 

  2718. 		value = dev->gpio_dir & (~(1 << pin_number));	/* clear */
    2719. 

  2719. 	else
    2720. 

  2720. 		value = dev->gpio_dir | (1 << pin_number);
    2721. 

  2721. 

  2722. 	status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
    2723. 

  2723. 

  2724. 	/* cache the value for future */
    2725. 

  2725. 	dev->gpio_dir = value;
    2726. 

  2726. 

  2727. 	return status;
    2728. 

  2728. }
    2729. 

  2729. 

  2730. /*
    2731. 

  2731. * cx231xx_set_gpio_value
    2732. 

  2732. *      Sets the value of the GPIO pin to Logic high or low. The Pin under
    2733. 

  2733. *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
    2734. 

  2734. *
    2735. 

  2735. * Parameters :
    2736. 

  2736. *      pin_number : The GPIO Pin number to program the direction for
    2737. 

  2737. *      pin_value : The value of the GPIO Pin under reference.
    2738. 

  2738. *                      0 = set it to 0
    2739. 

  2739. *                      1 = set it to 1
    2740. 

  2740. */
    2741. 

  2741. int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
    2742. 

  2742. {
    2743. 

  2743. 	int status = 0;
    2744. 

  2744. 	u32 value = 0;
    2745. 

  2745. 

  2746. 	/* Check for valid pin_number - if 0xFF , bail out */
    2747. 

  2747. 	if (pin_number >= 32)
    2748. 

  2748. 		return -EINVAL;
    2749. 

  2749. 

  2750. 	/* first do a sanity check - if the Pin is not output, make it output */
    2751. 

  2751. 	if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
    2752. 

  2752. 		/* It was in input mode */
    2753. 

  2753. 		value = dev->gpio_dir | (1 << pin_number);
    2754. 

  2754. 		dev->gpio_dir = value;
    2755. 

  2755. 		status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2756. 

  2756. 					      (u8 *) &dev->gpio_val);
    2757. 

  2757. 		value = 0;
    2758. 

  2758. 	}
    2759. 

  2759. 

  2760. 	if (pin_value == 0)
    2761. 

  2761. 		value = dev->gpio_val & (~(1 << pin_number));
    2762. 

  2762. 	else
    2763. 

  2763. 		value = dev->gpio_val | (1 << pin_number);
    2764. 

  2764. 

  2765. 	/* store the value */
    2766. 

  2766. 	dev->gpio_val = value;
    2767. 

  2767. 

  2768. 	/* toggle bit0 of GP_IO */
    2769. 

  2769. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2770. 

  2770. 

  2771. 	return status;
    2772. 

  2772. }
    2773. 

  2773. 

  2774. /*****************************************************************************
    2775. 

  2775. *                      G P I O I2C related functions                         *
    2776. 

  2776. ******************************************************************************/
    2777. 

  2777. int cx231xx_gpio_i2c_start(struct cx231xx *dev)
    2778. 

  2778. {
    2779. 

  2779. 	int status = 0;
    2780. 

  2780. 

  2781. 	/* set SCL to output 1 ; set SDA to output 1 */
    2782. 

  2782. 	dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
    2783. 

  2783. 	dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
    2784. 

  2784. 	dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2785. 

  2785. 	dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
    2786. 

  2786. 

  2787. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2788. 

  2788. 	if (status < 0)
    2789. 

  2789. 		return -EINVAL;
    2790. 

  2790. 

  2791. 	/* set SCL to output 1; set SDA to output 0 */
    2792. 

  2792. 	dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2793. 

  2793. 	dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2794. 

  2794. 

  2795. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2796. 

  2796. 	if (status < 0)
    2797. 

  2797. 		return -EINVAL;
    2798. 

  2798. 

  2799. 	/* set SCL to output 0; set SDA to output 0      */
    2800. 

  2800. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2801. 

  2801. 	dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2802. 

  2802. 

  2803. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2804. 

  2804. 	if (status < 0)
    2805. 

  2805. 		return -EINVAL;
    2806. 

  2806. 

  2807. 	return status;
    2808. 

  2808. }
    2809. 

  2809. 

  2810. int cx231xx_gpio_i2c_end(struct cx231xx *dev)
    2811. 

  2811. {
    2812. 

  2812. 	int status = 0;
    2813. 

  2813. 

  2814. 	/* set SCL to output 0; set SDA to output 0      */
    2815. 

  2815. 	dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
    2816. 

  2816. 	dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
    2817. 

  2817. 

  2818. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2819. 

  2819. 	dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2820. 

  2820. 

  2821. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2822. 

  2822. 	if (status < 0)
    2823. 

  2823. 		return -EINVAL;
    2824. 

  2824. 

  2825. 	/* set SCL to output 1; set SDA to output 0      */
    2826. 

  2826. 	dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2827. 

  2827. 	dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2828. 

  2828. 

  2829. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2830. 

  2830. 	if (status < 0)
    2831. 

  2831. 		return -EINVAL;
    2832. 

  2832. 

  2833. 	/* set SCL to input ,release SCL cable control
    2834. 

  2834. 	   set SDA to input ,release SDA cable control */
    2835. 

  2835. 	dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
    2836. 

  2836. 	dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
    2837. 

  2837. 

  2838. 	status =
    2839. 

  2839. 	    cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2840. 

  2840. 	if (status < 0)
    2841. 

  2841. 		return -EINVAL;
    2842. 

  2842. 

  2843. 	return status;
    2844. 

  2844. }
    2845. 

  2845. 

  2846. int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
    2847. 

  2847. {
    2848. 

  2848. 	int status = 0;
    2849. 

  2849. 	u8 i;
    2850. 

  2850. 

  2851. 	/* set SCL to output ; set SDA to output */
    2852. 

  2852. 	dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
    2853. 

  2853. 	dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
    2854. 

  2854. 

  2855. 	for (i = 0; i < 8; i++) {
    2856. 

  2856. 		if (((data << i) & 0x80) == 0) {
    2857. 

  2857. 			/* set SCL to output 0; set SDA to output 0     */
    2858. 

  2858. 			dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2859. 

  2859. 			dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2860. 

  2860. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2861. 

  2861. 						      (u8 *)&dev->gpio_val);
    2862. 

  2862. 

  2863. 			/* set SCL to output 1; set SDA to output 0     */
    2864. 

  2864. 			dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2865. 

  2865. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2866. 

  2866. 						      (u8 *)&dev->gpio_val);
    2867. 

  2867. 

  2868. 			/* set SCL to output 0; set SDA to output 0     */
    2869. 

  2869. 			dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2870. 

  2870. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2871. 

  2871. 						      (u8 *)&dev->gpio_val);
    2872. 

  2872. 		} else {
    2873. 

  2873. 			/* set SCL to output 0; set SDA to output 1     */
    2874. 

  2874. 			dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2875. 

  2875. 			dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
    2876. 

  2876. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2877. 

  2877. 						      (u8 *)&dev->gpio_val);
    2878. 

  2878. 

  2879. 			/* set SCL to output 1; set SDA to output 1     */
    2880. 

  2880. 			dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2881. 

  2881. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2882. 

  2882. 						      (u8 *)&dev->gpio_val);
    2883. 

  2883. 

  2884. 			/* set SCL to output 0; set SDA to output 1     */
    2885. 

  2885. 			dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2886. 

  2886. 			status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2887. 

  2887. 						      (u8 *)&dev->gpio_val);
    2888. 

  2888. 		}
    2889. 

  2889. 	}
    2890. 

  2890. 	return status;
    2891. 

  2891. }
    2892. 

  2892. 

  2893. int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
    2894. 

  2894. {
    2895. 

  2895. 	u8 value = 0;
    2896. 

  2896. 	int status = 0;
    2897. 

  2897. 	u32 gpio_logic_value = 0;
    2898. 

  2898. 	u8 i;
    2899. 

  2899. 

  2900. 	/* read byte */
    2901. 

  2901. 	for (i = 0; i < 8; i++) {	/* send write I2c addr */
    2902. 

  2902. 

  2903. 		/* set SCL to output 0; set SDA to input */
    2904. 

  2904. 		dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2905. 

  2905. 		status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2906. 

  2906. 					      (u8 *)&dev->gpio_val);
    2907. 

  2907. 

  2908. 		/* set SCL to output 1; set SDA to input */
    2909. 

  2909. 		dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    2910. 

  2910. 		status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
    2911. 

  2911. 					      (u8 *)&dev->gpio_val);
    2912. 

  2912. 

  2913. 		/* get SDA data bit */
    2914. 

  2914. 		gpio_logic_value = dev->gpio_val;
    2915. 

  2915. 		status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
    2916. 

  2916. 					      (u8 *)&dev->gpio_val);
    2917. 

  2917. 		if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
    2918. 

  2918. 			value |= (1 << (8 - i - 1));
    2919. 

  2919. 

  2920. 		dev->gpio_val = gpio_logic_value;
    2921. 

  2921. 	}
    2922. 

  2922. 

  2923. 	/* set SCL to output 0,finish the read latest SCL signal.
    2924. 

  2924. 	   !!!set SDA to input, never to modify SDA direction at
    2925. 

  2925. 	   the same times */
    2926. 

  2926. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2927. 

  2927. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2928. 

  2928. 

  2929. 	/* store the value */
    2930. 

  2930. 	*buf = value & 0xff;
    2931. 

  2931. 

  2932. 	return status;
    2933. 

  2933. }
    2934. 

  2934. 

  2935. int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
    2936. 

  2936. {
    2937. 

  2937. 	int status = 0;
    2938. 

  2938. 	u32 gpio_logic_value = 0;
    2939. 

  2939. 	int nCnt = 10;
    2940. 

  2940. 	int nInit = nCnt;
    2941. 

  2941. 

  2942. 	/* clock stretch; set SCL to input; set SDA to input;
    2943. 

  2943. 	   get SCL value till SCL = 1 */
    2944. 

  2944. 	dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
    2945. 

  2945. 	dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
    2946. 

  2946. 

  2947. 	gpio_logic_value = dev->gpio_val;
    2948. 

  2948. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2949. 

  2949. 

  2950. 	do {
    2951. 

  2951. 		msleep(2);
    2952. 

  2952. 		status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
    2953. 

  2953. 					      (u8 *)&dev->gpio_val);
    2954. 

  2954. 		nCnt--;
    2955. 

  2955. 	} while (((dev->gpio_val &
    2956. 

  2956. 			  (1 << dev->board.tuner_scl_gpio)) == 0) &&
    2957. 

  2957. 			 (nCnt > 0));
    2958. 

  2958. 

  2959. 	if (nCnt == 0)
    2960. 

  2960. 		cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
    2961. 

  2961. 			     nInit * 10);
    2962. 

  2962. 

  2963. 	/*
    2964. 

  2964. 	 * readAck
    2965. 

  2965. 	 * through clock stretch, slave has given a SCL signal,
    2966. 

  2966. 	 * so the SDA data can be directly read.
    2967. 

  2967. 	 */
    2968. 

  2968. 	status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2969. 

  2969. 

  2970. 	if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
    2971. 

  2971. 		dev->gpio_val = gpio_logic_value;
    2972. 

  2972. 		dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2973. 

  2973. 		status = 0;
    2974. 

  2974. 	} else {
    2975. 

  2975. 		dev->gpio_val = gpio_logic_value;
    2976. 

  2976. 		dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
    2977. 

  2977. 	}
    2978. 

  2978. 

  2979. 	/* read SDA end, set the SCL to output 0, after this operation,
    2980. 

  2980. 	   SDA direction can be changed. */
    2981. 

  2981. 	dev->gpio_val = gpio_logic_value;
    2982. 

  2982. 	dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
    2983. 

  2983. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    2984. 

  2984. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2985. 

  2985. 

  2986. 	return status;
    2987. 

  2987. }
    2988. 

  2988. 

  2989. int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
    2990. 

  2990. {
    2991. 

  2991. 	int status = 0;
    2992. 

  2992. 

  2993. 	/* set SDA to ouput */
    2994. 

  2994. 	dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
    2995. 

  2995. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    2996. 

  2996. 

  2997. 	/* set SCL = 0 (output); set SDA = 0 (output) */
    2998. 

  2998. 	dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
    2999. 

  2999. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    3000. 

  3000. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3001. 

  3001. 

  3002. 	/* set SCL = 1 (output); set SDA = 0 (output) */
    3003. 

  3003. 	dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    3004. 

  3004. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3005. 

  3005. 

  3006. 	/* set SCL = 0 (output); set SDA = 0 (output) */
    3007. 

  3007. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    3008. 

  3008. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3009. 

  3009. 

  3010. 	/* set SDA to input,and then the slave will read data from SDA. */
    3011. 

  3011. 	dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
    3012. 

  3012. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3013. 

  3013. 

  3014. 	return status;
    3015. 

  3015. }
    3016. 

  3016. 

  3017. int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
    3018. 

  3018. {
    3019. 

  3019. 	int status = 0;
    3020. 

  3020. 

  3021. 	/* set scl to output ; set sda to input */
    3022. 

  3022. 	dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
    3023. 

  3023. 	dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
    3024. 

  3024. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3025. 

  3025. 

  3026. 	/* set scl to output 0; set sda to input */
    3027. 

  3027. 	dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
    3028. 

  3028. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3029. 

  3029. 

  3030. 	/* set scl to output 1; set sda to input */
    3031. 

  3031. 	dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
    3032. 

  3032. 	status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
    3033. 

  3033. 

  3034. 	return status;
    3035. 

  3035. }
    3036. 

  3036. 

  3037. /*****************************************************************************
    3038. 

  3038. *                      G P I O I2C related functions                         *
    3039. 

  3039. ******************************************************************************/
    3040. 

  3040. /* cx231xx_gpio_i2c_read
    3041. 

  3041.  * Function to read data from gpio based I2C interface
    3042. 

  3042.  */
    3043. 

  3043. int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
    3044. 

  3044. {
    3045. 

  3045. 	int status = 0;
    3046. 

  3046. 	int i = 0;
    3047. 

  3047. 

  3048. 	/* get the lock */
    3049. 

  3049. 	mutex_lock(&dev->gpio_i2c_lock);
    3050. 

  3050. 

  3051. 	/* start */
    3052. 

  3052. 	status = cx231xx_gpio_i2c_start(dev);
    3053. 

  3053. 

  3054. 	/* write dev_addr */
    3055. 

  3055. 	status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
    3056. 

  3056. 

  3057. 	/* readAck */
    3058. 

  3058. 	status = cx231xx_gpio_i2c_read_ack(dev);
    3059. 

  3059. 

  3060. 	/* read data */
    3061. 

  3061. 	for (i = 0; i < len; i++) {
    3062. 

  3062. 		/* read data */
    3063. 

  3063. 		buf[i] = 0;
    3064. 

  3064. 		status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
    3065. 

  3065. 

  3066. 		if ((i + 1) != len) {
    3067. 

  3067. 			/* only do write ack if we more length */
    3068. 

  3068. 			status = cx231xx_gpio_i2c_write_ack(dev);
    3069. 

  3069. 		}
    3070. 

  3070. 	}
    3071. 

  3071. 

  3072. 	/* write NAK - inform reads are complete */
    3073. 

  3073. 	status = cx231xx_gpio_i2c_write_nak(dev);
    3074. 

  3074. 

  3075. 	/* write end */
    3076. 

  3076. 	status = cx231xx_gpio_i2c_end(dev);
    3077. 

  3077. 

  3078. 	/* release the lock */
    3079. 

  3079. 	mutex_unlock(&dev->gpio_i2c_lock);
    3080. 

  3080. 

  3081. 	return status;
    3082. 

  3082. }
    3083. 

  3083. 

  3084. /* cx231xx_gpio_i2c_write
    3085. 

  3085.  * Function to write data to gpio based I2C interface
    3086. 

  3086.  */
    3087. 

  3087. int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
    3088. 

  3088. {
    3089. 

  3089. 	int status = 0;
    3090. 

  3090. 	int i = 0;
    3091. 

  3091. 

  3092. 	/* get the lock */
    3093. 

  3093. 	mutex_lock(&dev->gpio_i2c_lock);
    3094. 

  3094. 

  3095. 	/* start */
    3096. 

  3096. 	status = cx231xx_gpio_i2c_start(dev);
    3097. 

  3097. 

  3098. 	/* write dev_addr */
    3099. 

  3099. 	status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
    3100. 

  3100. 

  3101. 	/* read Ack */
    3102. 

  3102. 	status = cx231xx_gpio_i2c_read_ack(dev);
    3103. 

  3103. 

  3104. 	for (i = 0; i < len; i++) {
    3105. 

  3105. 		/* Write data */
    3106. 

  3106. 		status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
    3107. 

  3107. 

  3108. 		/* read Ack */
    3109. 

  3109. 		status = cx231xx_gpio_i2c_read_ack(dev);
    3110. 

  3110. 	}
    3111. 

  3111. 

  3112. 	/* write End */
    3113. 

  3113. 	status = cx231xx_gpio_i2c_end(dev);
    3114. 

  3114. 

  3115. 	/* release the lock */
    3116. 

  3116. 	mutex_unlock(&dev->gpio_i2c_lock);
    3117. 

  3117. 

  3118. 	return 0;
    3119. 

  3119. }
    3120. 

  3120.