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/arch/sparc64/kernel/traps.c

https://bitbucket.org/evzijst/gittest
C | 2118 lines | 1662 code | 256 blank | 200 comment | 255 complexity | 429fcf8b37c9667e80ab350d1cfc84cc MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0
  1. /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
  2. * arch/sparc64/kernel/traps.c
  3. *
  4. * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
  5. * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
  6. */
  7. /*
  8. * I like traps on v9, :))))
  9. */
  10. #include <linux/config.h>
  11. #include <linux/module.h>
  12. #include <linux/sched.h> /* for jiffies */
  13. #include <linux/kernel.h>
  14. #include <linux/kallsyms.h>
  15. #include <linux/signal.h>
  16. #include <linux/smp.h>
  17. #include <linux/smp_lock.h>
  18. #include <linux/mm.h>
  19. #include <linux/init.h>
  20. #include <asm/delay.h>
  21. #include <asm/system.h>
  22. #include <asm/ptrace.h>
  23. #include <asm/oplib.h>
  24. #include <asm/page.h>
  25. #include <asm/pgtable.h>
  26. #include <asm/unistd.h>
  27. #include <asm/uaccess.h>
  28. #include <asm/fpumacro.h>
  29. #include <asm/lsu.h>
  30. #include <asm/dcu.h>
  31. #include <asm/estate.h>
  32. #include <asm/chafsr.h>
  33. #include <asm/psrcompat.h>
  34. #include <asm/processor.h>
  35. #include <asm/timer.h>
  36. #include <asm/kdebug.h>
  37. #ifdef CONFIG_KMOD
  38. #include <linux/kmod.h>
  39. #endif
  40. struct notifier_block *sparc64die_chain;
  41. static DEFINE_SPINLOCK(die_notifier_lock);
  42. int register_die_notifier(struct notifier_block *nb)
  43. {
  44. int err = 0;
  45. unsigned long flags;
  46. spin_lock_irqsave(&die_notifier_lock, flags);
  47. err = notifier_chain_register(&sparc64die_chain, nb);
  48. spin_unlock_irqrestore(&die_notifier_lock, flags);
  49. return err;
  50. }
  51. /* When an irrecoverable trap occurs at tl > 0, the trap entry
  52. * code logs the trap state registers at every level in the trap
  53. * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
  54. * is as follows:
  55. */
  56. struct tl1_traplog {
  57. struct {
  58. unsigned long tstate;
  59. unsigned long tpc;
  60. unsigned long tnpc;
  61. unsigned long tt;
  62. } trapstack[4];
  63. unsigned long tl;
  64. };
  65. static void dump_tl1_traplog(struct tl1_traplog *p)
  66. {
  67. int i;
  68. printk("TRAPLOG: Error at trap level 0x%lx, dumping track stack.\n",
  69. p->tl);
  70. for (i = 0; i < 4; i++) {
  71. printk(KERN_CRIT
  72. "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
  73. "TNPC[%016lx] TT[%lx]\n",
  74. i + 1,
  75. p->trapstack[i].tstate, p->trapstack[i].tpc,
  76. p->trapstack[i].tnpc, p->trapstack[i].tt);
  77. }
  78. }
  79. void do_call_debug(struct pt_regs *regs)
  80. {
  81. notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
  82. }
  83. void bad_trap(struct pt_regs *regs, long lvl)
  84. {
  85. char buffer[32];
  86. siginfo_t info;
  87. if (notify_die(DIE_TRAP, "bad trap", regs,
  88. 0, lvl, SIGTRAP) == NOTIFY_STOP)
  89. return;
  90. if (lvl < 0x100) {
  91. sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
  92. die_if_kernel(buffer, regs);
  93. }
  94. lvl -= 0x100;
  95. if (regs->tstate & TSTATE_PRIV) {
  96. sprintf(buffer, "Kernel bad sw trap %lx", lvl);
  97. die_if_kernel(buffer, regs);
  98. }
  99. if (test_thread_flag(TIF_32BIT)) {
  100. regs->tpc &= 0xffffffff;
  101. regs->tnpc &= 0xffffffff;
  102. }
  103. info.si_signo = SIGILL;
  104. info.si_errno = 0;
  105. info.si_code = ILL_ILLTRP;
  106. info.si_addr = (void __user *)regs->tpc;
  107. info.si_trapno = lvl;
  108. force_sig_info(SIGILL, &info, current);
  109. }
  110. void bad_trap_tl1(struct pt_regs *regs, long lvl)
  111. {
  112. char buffer[32];
  113. if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
  114. 0, lvl, SIGTRAP) == NOTIFY_STOP)
  115. return;
  116. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  117. sprintf (buffer, "Bad trap %lx at tl>0", lvl);
  118. die_if_kernel (buffer, regs);
  119. }
  120. #ifdef CONFIG_DEBUG_BUGVERBOSE
  121. void do_BUG(const char *file, int line)
  122. {
  123. bust_spinlocks(1);
  124. printk("kernel BUG at %s:%d!\n", file, line);
  125. }
  126. #endif
  127. void instruction_access_exception(struct pt_regs *regs,
  128. unsigned long sfsr, unsigned long sfar)
  129. {
  130. siginfo_t info;
  131. if (notify_die(DIE_TRAP, "instruction access exception", regs,
  132. 0, 0x8, SIGTRAP) == NOTIFY_STOP)
  133. return;
  134. if (regs->tstate & TSTATE_PRIV) {
  135. printk("instruction_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
  136. sfsr, sfar);
  137. die_if_kernel("Iax", regs);
  138. }
  139. if (test_thread_flag(TIF_32BIT)) {
  140. regs->tpc &= 0xffffffff;
  141. regs->tnpc &= 0xffffffff;
  142. }
  143. info.si_signo = SIGSEGV;
  144. info.si_errno = 0;
  145. info.si_code = SEGV_MAPERR;
  146. info.si_addr = (void __user *)regs->tpc;
  147. info.si_trapno = 0;
  148. force_sig_info(SIGSEGV, &info, current);
  149. }
  150. void instruction_access_exception_tl1(struct pt_regs *regs,
  151. unsigned long sfsr, unsigned long sfar)
  152. {
  153. if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
  154. 0, 0x8, SIGTRAP) == NOTIFY_STOP)
  155. return;
  156. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  157. instruction_access_exception(regs, sfsr, sfar);
  158. }
  159. void data_access_exception(struct pt_regs *regs,
  160. unsigned long sfsr, unsigned long sfar)
  161. {
  162. siginfo_t info;
  163. if (notify_die(DIE_TRAP, "data access exception", regs,
  164. 0, 0x30, SIGTRAP) == NOTIFY_STOP)
  165. return;
  166. if (regs->tstate & TSTATE_PRIV) {
  167. /* Test if this comes from uaccess places. */
  168. unsigned long fixup;
  169. unsigned long g2 = regs->u_regs[UREG_G2];
  170. if ((fixup = search_extables_range(regs->tpc, &g2))) {
  171. /* Ouch, somebody is trying ugly VM hole tricks on us... */
  172. #ifdef DEBUG_EXCEPTIONS
  173. printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
  174. printk("EX_TABLE: insn<%016lx> fixup<%016lx> "
  175. "g2<%016lx>\n", regs->tpc, fixup, g2);
  176. #endif
  177. regs->tpc = fixup;
  178. regs->tnpc = regs->tpc + 4;
  179. regs->u_regs[UREG_G2] = g2;
  180. return;
  181. }
  182. /* Shit... */
  183. printk("data_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
  184. sfsr, sfar);
  185. die_if_kernel("Dax", regs);
  186. }
  187. info.si_signo = SIGSEGV;
  188. info.si_errno = 0;
  189. info.si_code = SEGV_MAPERR;
  190. info.si_addr = (void __user *)sfar;
  191. info.si_trapno = 0;
  192. force_sig_info(SIGSEGV, &info, current);
  193. }
  194. #ifdef CONFIG_PCI
  195. /* This is really pathetic... */
  196. extern volatile int pci_poke_in_progress;
  197. extern volatile int pci_poke_cpu;
  198. extern volatile int pci_poke_faulted;
  199. #endif
  200. /* When access exceptions happen, we must do this. */
  201. static void spitfire_clean_and_reenable_l1_caches(void)
  202. {
  203. unsigned long va;
  204. if (tlb_type != spitfire)
  205. BUG();
  206. /* Clean 'em. */
  207. for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
  208. spitfire_put_icache_tag(va, 0x0);
  209. spitfire_put_dcache_tag(va, 0x0);
  210. }
  211. /* Re-enable in LSU. */
  212. __asm__ __volatile__("flush %%g6\n\t"
  213. "membar #Sync\n\t"
  214. "stxa %0, [%%g0] %1\n\t"
  215. "membar #Sync"
  216. : /* no outputs */
  217. : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
  218. LSU_CONTROL_IM | LSU_CONTROL_DM),
  219. "i" (ASI_LSU_CONTROL)
  220. : "memory");
  221. }
  222. void do_iae(struct pt_regs *regs)
  223. {
  224. siginfo_t info;
  225. spitfire_clean_and_reenable_l1_caches();
  226. if (notify_die(DIE_TRAP, "instruction access exception", regs,
  227. 0, 0x8, SIGTRAP) == NOTIFY_STOP)
  228. return;
  229. info.si_signo = SIGBUS;
  230. info.si_errno = 0;
  231. info.si_code = BUS_OBJERR;
  232. info.si_addr = (void *)0;
  233. info.si_trapno = 0;
  234. force_sig_info(SIGBUS, &info, current);
  235. }
  236. void do_dae(struct pt_regs *regs)
  237. {
  238. siginfo_t info;
  239. #ifdef CONFIG_PCI
  240. if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
  241. spitfire_clean_and_reenable_l1_caches();
  242. pci_poke_faulted = 1;
  243. /* Why the fuck did they have to change this? */
  244. if (tlb_type == cheetah || tlb_type == cheetah_plus)
  245. regs->tpc += 4;
  246. regs->tnpc = regs->tpc + 4;
  247. return;
  248. }
  249. #endif
  250. spitfire_clean_and_reenable_l1_caches();
  251. if (notify_die(DIE_TRAP, "data access exception", regs,
  252. 0, 0x30, SIGTRAP) == NOTIFY_STOP)
  253. return;
  254. info.si_signo = SIGBUS;
  255. info.si_errno = 0;
  256. info.si_code = BUS_OBJERR;
  257. info.si_addr = (void *)0;
  258. info.si_trapno = 0;
  259. force_sig_info(SIGBUS, &info, current);
  260. }
  261. static char ecc_syndrome_table[] = {
  262. 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
  263. 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
  264. 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
  265. 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
  266. 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
  267. 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
  268. 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
  269. 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
  270. 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
  271. 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
  272. 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
  273. 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
  274. 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
  275. 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
  276. 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
  277. 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
  278. 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
  279. 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
  280. 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
  281. 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
  282. 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
  283. 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
  284. 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
  285. 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
  286. 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
  287. 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
  288. 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
  289. 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
  290. 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
  291. 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
  292. 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
  293. 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
  294. };
  295. /* cee_trap in entry.S encodes AFSR/UDBH/UDBL error status
  296. * in the following format. The AFAR is left as is, with
  297. * reserved bits cleared, and is a raw 40-bit physical
  298. * address.
  299. */
  300. #define CE_STATUS_UDBH_UE (1UL << (43 + 9))
  301. #define CE_STATUS_UDBH_CE (1UL << (43 + 8))
  302. #define CE_STATUS_UDBH_ESYNDR (0xffUL << 43)
  303. #define CE_STATUS_UDBH_SHIFT 43
  304. #define CE_STATUS_UDBL_UE (1UL << (33 + 9))
  305. #define CE_STATUS_UDBL_CE (1UL << (33 + 8))
  306. #define CE_STATUS_UDBL_ESYNDR (0xffUL << 33)
  307. #define CE_STATUS_UDBL_SHIFT 33
  308. #define CE_STATUS_AFSR_MASK (0x1ffffffffUL)
  309. #define CE_STATUS_AFSR_ME (1UL << 32)
  310. #define CE_STATUS_AFSR_PRIV (1UL << 31)
  311. #define CE_STATUS_AFSR_ISAP (1UL << 30)
  312. #define CE_STATUS_AFSR_ETP (1UL << 29)
  313. #define CE_STATUS_AFSR_IVUE (1UL << 28)
  314. #define CE_STATUS_AFSR_TO (1UL << 27)
  315. #define CE_STATUS_AFSR_BERR (1UL << 26)
  316. #define CE_STATUS_AFSR_LDP (1UL << 25)
  317. #define CE_STATUS_AFSR_CP (1UL << 24)
  318. #define CE_STATUS_AFSR_WP (1UL << 23)
  319. #define CE_STATUS_AFSR_EDP (1UL << 22)
  320. #define CE_STATUS_AFSR_UE (1UL << 21)
  321. #define CE_STATUS_AFSR_CE (1UL << 20)
  322. #define CE_STATUS_AFSR_ETS (0xfUL << 16)
  323. #define CE_STATUS_AFSR_ETS_SHIFT 16
  324. #define CE_STATUS_AFSR_PSYND (0xffffUL << 0)
  325. #define CE_STATUS_AFSR_PSYND_SHIFT 0
  326. /* Layout of Ecache TAG Parity Syndrome of AFSR */
  327. #define AFSR_ETSYNDROME_7_0 0x1UL /* E$-tag bus bits <7:0> */
  328. #define AFSR_ETSYNDROME_15_8 0x2UL /* E$-tag bus bits <15:8> */
  329. #define AFSR_ETSYNDROME_21_16 0x4UL /* E$-tag bus bits <21:16> */
  330. #define AFSR_ETSYNDROME_24_22 0x8UL /* E$-tag bus bits <24:22> */
  331. static char *syndrome_unknown = "<Unknown>";
  332. asmlinkage void cee_log(unsigned long ce_status,
  333. unsigned long afar,
  334. struct pt_regs *regs)
  335. {
  336. char memmod_str[64];
  337. char *p;
  338. unsigned short scode, udb_reg;
  339. printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
  340. "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx]\n",
  341. smp_processor_id(),
  342. (ce_status & CE_STATUS_AFSR_MASK),
  343. afar,
  344. ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL),
  345. ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL));
  346. udb_reg = ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL);
  347. if (udb_reg & (1 << 8)) {
  348. scode = ecc_syndrome_table[udb_reg & 0xff];
  349. if (prom_getunumber(scode, afar,
  350. memmod_str, sizeof(memmod_str)) == -1)
  351. p = syndrome_unknown;
  352. else
  353. p = memmod_str;
  354. printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
  355. "Memory Module \"%s\"\n",
  356. smp_processor_id(), scode, p);
  357. }
  358. udb_reg = ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL);
  359. if (udb_reg & (1 << 8)) {
  360. scode = ecc_syndrome_table[udb_reg & 0xff];
  361. if (prom_getunumber(scode, afar,
  362. memmod_str, sizeof(memmod_str)) == -1)
  363. p = syndrome_unknown;
  364. else
  365. p = memmod_str;
  366. printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
  367. "Memory Module \"%s\"\n",
  368. smp_processor_id(), scode, p);
  369. }
  370. }
  371. /* Cheetah error trap handling. */
  372. static unsigned long ecache_flush_physbase;
  373. static unsigned long ecache_flush_linesize;
  374. static unsigned long ecache_flush_size;
  375. /* WARNING: The error trap handlers in assembly know the precise
  376. * layout of the following structure.
  377. *
  378. * C-level handlers below use this information to log the error
  379. * and then determine how to recover (if possible).
  380. */
  381. struct cheetah_err_info {
  382. /*0x00*/u64 afsr;
  383. /*0x08*/u64 afar;
  384. /* D-cache state */
  385. /*0x10*/u64 dcache_data[4]; /* The actual data */
  386. /*0x30*/u64 dcache_index; /* D-cache index */
  387. /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
  388. /*0x40*/u64 dcache_utag; /* D-cache microtag */
  389. /*0x48*/u64 dcache_stag; /* D-cache snooptag */
  390. /* I-cache state */
  391. /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
  392. /*0x90*/u64 icache_index; /* I-cache index */
  393. /*0x98*/u64 icache_tag; /* I-cache phys tag */
  394. /*0xa0*/u64 icache_utag; /* I-cache microtag */
  395. /*0xa8*/u64 icache_stag; /* I-cache snooptag */
  396. /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
  397. /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
  398. /* E-cache state */
  399. /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
  400. /*0xe0*/u64 ecache_index; /* E-cache index */
  401. /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
  402. /*0xf0*/u64 __pad[32 - 30];
  403. };
  404. #define CHAFSR_INVALID ((u64)-1L)
  405. /* This table is ordered in priority of errors and matches the
  406. * AFAR overwrite policy as well.
  407. */
  408. struct afsr_error_table {
  409. unsigned long mask;
  410. const char *name;
  411. };
  412. static const char CHAFSR_PERR_msg[] =
  413. "System interface protocol error";
  414. static const char CHAFSR_IERR_msg[] =
  415. "Internal processor error";
  416. static const char CHAFSR_ISAP_msg[] =
  417. "System request parity error on incoming addresss";
  418. static const char CHAFSR_UCU_msg[] =
  419. "Uncorrectable E-cache ECC error for ifetch/data";
  420. static const char CHAFSR_UCC_msg[] =
  421. "SW Correctable E-cache ECC error for ifetch/data";
  422. static const char CHAFSR_UE_msg[] =
  423. "Uncorrectable system bus data ECC error for read";
  424. static const char CHAFSR_EDU_msg[] =
  425. "Uncorrectable E-cache ECC error for stmerge/blkld";
  426. static const char CHAFSR_EMU_msg[] =
  427. "Uncorrectable system bus MTAG error";
  428. static const char CHAFSR_WDU_msg[] =
  429. "Uncorrectable E-cache ECC error for writeback";
  430. static const char CHAFSR_CPU_msg[] =
  431. "Uncorrectable ECC error for copyout";
  432. static const char CHAFSR_CE_msg[] =
  433. "HW corrected system bus data ECC error for read";
  434. static const char CHAFSR_EDC_msg[] =
  435. "HW corrected E-cache ECC error for stmerge/blkld";
  436. static const char CHAFSR_EMC_msg[] =
  437. "HW corrected system bus MTAG ECC error";
  438. static const char CHAFSR_WDC_msg[] =
  439. "HW corrected E-cache ECC error for writeback";
  440. static const char CHAFSR_CPC_msg[] =
  441. "HW corrected ECC error for copyout";
  442. static const char CHAFSR_TO_msg[] =
  443. "Unmapped error from system bus";
  444. static const char CHAFSR_BERR_msg[] =
  445. "Bus error response from system bus";
  446. static const char CHAFSR_IVC_msg[] =
  447. "HW corrected system bus data ECC error for ivec read";
  448. static const char CHAFSR_IVU_msg[] =
  449. "Uncorrectable system bus data ECC error for ivec read";
  450. static struct afsr_error_table __cheetah_error_table[] = {
  451. { CHAFSR_PERR, CHAFSR_PERR_msg },
  452. { CHAFSR_IERR, CHAFSR_IERR_msg },
  453. { CHAFSR_ISAP, CHAFSR_ISAP_msg },
  454. { CHAFSR_UCU, CHAFSR_UCU_msg },
  455. { CHAFSR_UCC, CHAFSR_UCC_msg },
  456. { CHAFSR_UE, CHAFSR_UE_msg },
  457. { CHAFSR_EDU, CHAFSR_EDU_msg },
  458. { CHAFSR_EMU, CHAFSR_EMU_msg },
  459. { CHAFSR_WDU, CHAFSR_WDU_msg },
  460. { CHAFSR_CPU, CHAFSR_CPU_msg },
  461. { CHAFSR_CE, CHAFSR_CE_msg },
  462. { CHAFSR_EDC, CHAFSR_EDC_msg },
  463. { CHAFSR_EMC, CHAFSR_EMC_msg },
  464. { CHAFSR_WDC, CHAFSR_WDC_msg },
  465. { CHAFSR_CPC, CHAFSR_CPC_msg },
  466. { CHAFSR_TO, CHAFSR_TO_msg },
  467. { CHAFSR_BERR, CHAFSR_BERR_msg },
  468. /* These two do not update the AFAR. */
  469. { CHAFSR_IVC, CHAFSR_IVC_msg },
  470. { CHAFSR_IVU, CHAFSR_IVU_msg },
  471. { 0, NULL },
  472. };
  473. static const char CHPAFSR_DTO_msg[] =
  474. "System bus unmapped error for prefetch/storequeue-read";
  475. static const char CHPAFSR_DBERR_msg[] =
  476. "System bus error for prefetch/storequeue-read";
  477. static const char CHPAFSR_THCE_msg[] =
  478. "Hardware corrected E-cache Tag ECC error";
  479. static const char CHPAFSR_TSCE_msg[] =
  480. "SW handled correctable E-cache Tag ECC error";
  481. static const char CHPAFSR_TUE_msg[] =
  482. "Uncorrectable E-cache Tag ECC error";
  483. static const char CHPAFSR_DUE_msg[] =
  484. "System bus uncorrectable data ECC error due to prefetch/store-fill";
  485. static struct afsr_error_table __cheetah_plus_error_table[] = {
  486. { CHAFSR_PERR, CHAFSR_PERR_msg },
  487. { CHAFSR_IERR, CHAFSR_IERR_msg },
  488. { CHAFSR_ISAP, CHAFSR_ISAP_msg },
  489. { CHAFSR_UCU, CHAFSR_UCU_msg },
  490. { CHAFSR_UCC, CHAFSR_UCC_msg },
  491. { CHAFSR_UE, CHAFSR_UE_msg },
  492. { CHAFSR_EDU, CHAFSR_EDU_msg },
  493. { CHAFSR_EMU, CHAFSR_EMU_msg },
  494. { CHAFSR_WDU, CHAFSR_WDU_msg },
  495. { CHAFSR_CPU, CHAFSR_CPU_msg },
  496. { CHAFSR_CE, CHAFSR_CE_msg },
  497. { CHAFSR_EDC, CHAFSR_EDC_msg },
  498. { CHAFSR_EMC, CHAFSR_EMC_msg },
  499. { CHAFSR_WDC, CHAFSR_WDC_msg },
  500. { CHAFSR_CPC, CHAFSR_CPC_msg },
  501. { CHAFSR_TO, CHAFSR_TO_msg },
  502. { CHAFSR_BERR, CHAFSR_BERR_msg },
  503. { CHPAFSR_DTO, CHPAFSR_DTO_msg },
  504. { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
  505. { CHPAFSR_THCE, CHPAFSR_THCE_msg },
  506. { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
  507. { CHPAFSR_TUE, CHPAFSR_TUE_msg },
  508. { CHPAFSR_DUE, CHPAFSR_DUE_msg },
  509. /* These two do not update the AFAR. */
  510. { CHAFSR_IVC, CHAFSR_IVC_msg },
  511. { CHAFSR_IVU, CHAFSR_IVU_msg },
  512. { 0, NULL },
  513. };
  514. static const char JPAFSR_JETO_msg[] =
  515. "System interface protocol error, hw timeout caused";
  516. static const char JPAFSR_SCE_msg[] =
  517. "Parity error on system snoop results";
  518. static const char JPAFSR_JEIC_msg[] =
  519. "System interface protocol error, illegal command detected";
  520. static const char JPAFSR_JEIT_msg[] =
  521. "System interface protocol error, illegal ADTYPE detected";
  522. static const char JPAFSR_OM_msg[] =
  523. "Out of range memory error has occurred";
  524. static const char JPAFSR_ETP_msg[] =
  525. "Parity error on L2 cache tag SRAM";
  526. static const char JPAFSR_UMS_msg[] =
  527. "Error due to unsupported store";
  528. static const char JPAFSR_RUE_msg[] =
  529. "Uncorrectable ECC error from remote cache/memory";
  530. static const char JPAFSR_RCE_msg[] =
  531. "Correctable ECC error from remote cache/memory";
  532. static const char JPAFSR_BP_msg[] =
  533. "JBUS parity error on returned read data";
  534. static const char JPAFSR_WBP_msg[] =
  535. "JBUS parity error on data for writeback or block store";
  536. static const char JPAFSR_FRC_msg[] =
  537. "Foreign read to DRAM incurring correctable ECC error";
  538. static const char JPAFSR_FRU_msg[] =
  539. "Foreign read to DRAM incurring uncorrectable ECC error";
  540. static struct afsr_error_table __jalapeno_error_table[] = {
  541. { JPAFSR_JETO, JPAFSR_JETO_msg },
  542. { JPAFSR_SCE, JPAFSR_SCE_msg },
  543. { JPAFSR_JEIC, JPAFSR_JEIC_msg },
  544. { JPAFSR_JEIT, JPAFSR_JEIT_msg },
  545. { CHAFSR_PERR, CHAFSR_PERR_msg },
  546. { CHAFSR_IERR, CHAFSR_IERR_msg },
  547. { CHAFSR_ISAP, CHAFSR_ISAP_msg },
  548. { CHAFSR_UCU, CHAFSR_UCU_msg },
  549. { CHAFSR_UCC, CHAFSR_UCC_msg },
  550. { CHAFSR_UE, CHAFSR_UE_msg },
  551. { CHAFSR_EDU, CHAFSR_EDU_msg },
  552. { JPAFSR_OM, JPAFSR_OM_msg },
  553. { CHAFSR_WDU, CHAFSR_WDU_msg },
  554. { CHAFSR_CPU, CHAFSR_CPU_msg },
  555. { CHAFSR_CE, CHAFSR_CE_msg },
  556. { CHAFSR_EDC, CHAFSR_EDC_msg },
  557. { JPAFSR_ETP, JPAFSR_ETP_msg },
  558. { CHAFSR_WDC, CHAFSR_WDC_msg },
  559. { CHAFSR_CPC, CHAFSR_CPC_msg },
  560. { CHAFSR_TO, CHAFSR_TO_msg },
  561. { CHAFSR_BERR, CHAFSR_BERR_msg },
  562. { JPAFSR_UMS, JPAFSR_UMS_msg },
  563. { JPAFSR_RUE, JPAFSR_RUE_msg },
  564. { JPAFSR_RCE, JPAFSR_RCE_msg },
  565. { JPAFSR_BP, JPAFSR_BP_msg },
  566. { JPAFSR_WBP, JPAFSR_WBP_msg },
  567. { JPAFSR_FRC, JPAFSR_FRC_msg },
  568. { JPAFSR_FRU, JPAFSR_FRU_msg },
  569. /* These two do not update the AFAR. */
  570. { CHAFSR_IVU, CHAFSR_IVU_msg },
  571. { 0, NULL },
  572. };
  573. static struct afsr_error_table *cheetah_error_table;
  574. static unsigned long cheetah_afsr_errors;
  575. /* This is allocated at boot time based upon the largest hardware
  576. * cpu ID in the system. We allocate two entries per cpu, one for
  577. * TL==0 logging and one for TL >= 1 logging.
  578. */
  579. struct cheetah_err_info *cheetah_error_log;
  580. static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
  581. {
  582. struct cheetah_err_info *p;
  583. int cpu = smp_processor_id();
  584. if (!cheetah_error_log)
  585. return NULL;
  586. p = cheetah_error_log + (cpu * 2);
  587. if ((afsr & CHAFSR_TL1) != 0UL)
  588. p++;
  589. return p;
  590. }
  591. extern unsigned int tl0_icpe[], tl1_icpe[];
  592. extern unsigned int tl0_dcpe[], tl1_dcpe[];
  593. extern unsigned int tl0_fecc[], tl1_fecc[];
  594. extern unsigned int tl0_cee[], tl1_cee[];
  595. extern unsigned int tl0_iae[], tl1_iae[];
  596. extern unsigned int tl0_dae[], tl1_dae[];
  597. extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
  598. extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
  599. extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
  600. extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
  601. extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
  602. void __init cheetah_ecache_flush_init(void)
  603. {
  604. unsigned long largest_size, smallest_linesize, order, ver;
  605. int node, i, instance;
  606. /* Scan all cpu device tree nodes, note two values:
  607. * 1) largest E-cache size
  608. * 2) smallest E-cache line size
  609. */
  610. largest_size = 0UL;
  611. smallest_linesize = ~0UL;
  612. instance = 0;
  613. while (!cpu_find_by_instance(instance, &node, NULL)) {
  614. unsigned long val;
  615. val = prom_getintdefault(node, "ecache-size",
  616. (2 * 1024 * 1024));
  617. if (val > largest_size)
  618. largest_size = val;
  619. val = prom_getintdefault(node, "ecache-line-size", 64);
  620. if (val < smallest_linesize)
  621. smallest_linesize = val;
  622. instance++;
  623. }
  624. if (largest_size == 0UL || smallest_linesize == ~0UL) {
  625. prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
  626. "parameters.\n");
  627. prom_halt();
  628. }
  629. ecache_flush_size = (2 * largest_size);
  630. ecache_flush_linesize = smallest_linesize;
  631. /* Discover a physically contiguous chunk of physical
  632. * memory in 'sp_banks' of size ecache_flush_size calculated
  633. * above. Store the physical base of this area at
  634. * ecache_flush_physbase.
  635. */
  636. for (node = 0; ; node++) {
  637. if (sp_banks[node].num_bytes == 0)
  638. break;
  639. if (sp_banks[node].num_bytes >= ecache_flush_size) {
  640. ecache_flush_physbase = sp_banks[node].base_addr;
  641. break;
  642. }
  643. }
  644. /* Note: Zero would be a valid value of ecache_flush_physbase so
  645. * don't use that as the success test. :-)
  646. */
  647. if (sp_banks[node].num_bytes == 0) {
  648. prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
  649. "contiguous physical memory.\n", ecache_flush_size);
  650. prom_halt();
  651. }
  652. /* Now allocate error trap reporting scoreboard. */
  653. node = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
  654. for (order = 0; order < MAX_ORDER; order++) {
  655. if ((PAGE_SIZE << order) >= node)
  656. break;
  657. }
  658. cheetah_error_log = (struct cheetah_err_info *)
  659. __get_free_pages(GFP_KERNEL, order);
  660. if (!cheetah_error_log) {
  661. prom_printf("cheetah_ecache_flush_init: Failed to allocate "
  662. "error logging scoreboard (%d bytes).\n", node);
  663. prom_halt();
  664. }
  665. memset(cheetah_error_log, 0, PAGE_SIZE << order);
  666. /* Mark all AFSRs as invalid so that the trap handler will
  667. * log new new information there.
  668. */
  669. for (i = 0; i < 2 * NR_CPUS; i++)
  670. cheetah_error_log[i].afsr = CHAFSR_INVALID;
  671. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  672. if ((ver >> 32) == 0x003e0016) {
  673. cheetah_error_table = &__jalapeno_error_table[0];
  674. cheetah_afsr_errors = JPAFSR_ERRORS;
  675. } else if ((ver >> 32) == 0x003e0015) {
  676. cheetah_error_table = &__cheetah_plus_error_table[0];
  677. cheetah_afsr_errors = CHPAFSR_ERRORS;
  678. } else {
  679. cheetah_error_table = &__cheetah_error_table[0];
  680. cheetah_afsr_errors = CHAFSR_ERRORS;
  681. }
  682. /* Now patch trap tables. */
  683. memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
  684. memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
  685. memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
  686. memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
  687. memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
  688. memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
  689. memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
  690. memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
  691. if (tlb_type == cheetah_plus) {
  692. memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
  693. memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
  694. memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
  695. memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
  696. }
  697. flushi(PAGE_OFFSET);
  698. }
  699. static void cheetah_flush_ecache(void)
  700. {
  701. unsigned long flush_base = ecache_flush_physbase;
  702. unsigned long flush_linesize = ecache_flush_linesize;
  703. unsigned long flush_size = ecache_flush_size;
  704. __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
  705. " bne,pt %%xcc, 1b\n\t"
  706. " ldxa [%2 + %0] %3, %%g0\n\t"
  707. : "=&r" (flush_size)
  708. : "0" (flush_size), "r" (flush_base),
  709. "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
  710. }
  711. static void cheetah_flush_ecache_line(unsigned long physaddr)
  712. {
  713. unsigned long alias;
  714. physaddr &= ~(8UL - 1UL);
  715. physaddr = (ecache_flush_physbase +
  716. (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
  717. alias = physaddr + (ecache_flush_size >> 1UL);
  718. __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
  719. "ldxa [%1] %2, %%g0\n\t"
  720. "membar #Sync"
  721. : /* no outputs */
  722. : "r" (physaddr), "r" (alias),
  723. "i" (ASI_PHYS_USE_EC));
  724. }
  725. /* Unfortunately, the diagnostic access to the I-cache tags we need to
  726. * use to clear the thing interferes with I-cache coherency transactions.
  727. *
  728. * So we must only flush the I-cache when it is disabled.
  729. */
  730. static void __cheetah_flush_icache(void)
  731. {
  732. unsigned long i;
  733. /* Clear the valid bits in all the tags. */
  734. for (i = 0; i < (1 << 15); i += (1 << 5)) {
  735. __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
  736. "membar #Sync"
  737. : /* no outputs */
  738. : "r" (i | (2 << 3)), "i" (ASI_IC_TAG));
  739. }
  740. }
  741. static void cheetah_flush_icache(void)
  742. {
  743. unsigned long dcu_save;
  744. /* Save current DCU, disable I-cache. */
  745. __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
  746. "or %0, %2, %%g1\n\t"
  747. "stxa %%g1, [%%g0] %1\n\t"
  748. "membar #Sync"
  749. : "=r" (dcu_save)
  750. : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
  751. : "g1");
  752. __cheetah_flush_icache();
  753. /* Restore DCU register */
  754. __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
  755. "membar #Sync"
  756. : /* no outputs */
  757. : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
  758. }
  759. static void cheetah_flush_dcache(void)
  760. {
  761. unsigned long i;
  762. for (i = 0; i < (1 << 16); i += (1 << 5)) {
  763. __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
  764. "membar #Sync"
  765. : /* no outputs */
  766. : "r" (i), "i" (ASI_DCACHE_TAG));
  767. }
  768. }
  769. /* In order to make the even parity correct we must do two things.
  770. * First, we clear DC_data_parity and set DC_utag to an appropriate value.
  771. * Next, we clear out all 32-bytes of data for that line. Data of
  772. * all-zero + tag parity value of zero == correct parity.
  773. */
  774. static void cheetah_plus_zap_dcache_parity(void)
  775. {
  776. unsigned long i;
  777. for (i = 0; i < (1 << 16); i += (1 << 5)) {
  778. unsigned long tag = (i >> 14);
  779. unsigned long j;
  780. __asm__ __volatile__("membar #Sync\n\t"
  781. "stxa %0, [%1] %2\n\t"
  782. "membar #Sync"
  783. : /* no outputs */
  784. : "r" (tag), "r" (i),
  785. "i" (ASI_DCACHE_UTAG));
  786. for (j = i; j < i + (1 << 5); j += (1 << 3))
  787. __asm__ __volatile__("membar #Sync\n\t"
  788. "stxa %%g0, [%0] %1\n\t"
  789. "membar #Sync"
  790. : /* no outputs */
  791. : "r" (j), "i" (ASI_DCACHE_DATA));
  792. }
  793. }
  794. /* Conversion tables used to frob Cheetah AFSR syndrome values into
  795. * something palatable to the memory controller driver get_unumber
  796. * routine.
  797. */
  798. #define MT0 137
  799. #define MT1 138
  800. #define MT2 139
  801. #define NONE 254
  802. #define MTC0 140
  803. #define MTC1 141
  804. #define MTC2 142
  805. #define MTC3 143
  806. #define C0 128
  807. #define C1 129
  808. #define C2 130
  809. #define C3 131
  810. #define C4 132
  811. #define C5 133
  812. #define C6 134
  813. #define C7 135
  814. #define C8 136
  815. #define M2 144
  816. #define M3 145
  817. #define M4 146
  818. #define M 147
  819. static unsigned char cheetah_ecc_syntab[] = {
  820. /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
  821. /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
  822. /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
  823. /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
  824. /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
  825. /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
  826. /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
  827. /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
  828. /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
  829. /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
  830. /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
  831. /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
  832. /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
  833. /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
  834. /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
  835. /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
  836. /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
  837. /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
  838. /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
  839. /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
  840. /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
  841. /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
  842. /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
  843. /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
  844. /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
  845. /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
  846. /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
  847. /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
  848. /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
  849. /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
  850. /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
  851. /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
  852. };
  853. static unsigned char cheetah_mtag_syntab[] = {
  854. NONE, MTC0,
  855. MTC1, NONE,
  856. MTC2, NONE,
  857. NONE, MT0,
  858. MTC3, NONE,
  859. NONE, MT1,
  860. NONE, MT2,
  861. NONE, NONE
  862. };
  863. /* Return the highest priority error conditon mentioned. */
  864. static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
  865. {
  866. unsigned long tmp = 0;
  867. int i;
  868. for (i = 0; cheetah_error_table[i].mask; i++) {
  869. if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
  870. return tmp;
  871. }
  872. return tmp;
  873. }
  874. static const char *cheetah_get_string(unsigned long bit)
  875. {
  876. int i;
  877. for (i = 0; cheetah_error_table[i].mask; i++) {
  878. if ((bit & cheetah_error_table[i].mask) != 0UL)
  879. return cheetah_error_table[i].name;
  880. }
  881. return "???";
  882. }
  883. extern int chmc_getunumber(int, unsigned long, char *, int);
  884. static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
  885. unsigned long afsr, unsigned long afar, int recoverable)
  886. {
  887. unsigned long hipri;
  888. char unum[256];
  889. printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
  890. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  891. afsr, afar,
  892. (afsr & CHAFSR_TL1) ? 1 : 0);
  893. printk("%s" "ERROR(%d): TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
  894. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  895. regs->tpc, regs->tnpc, regs->tstate);
  896. printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
  897. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  898. (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
  899. (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
  900. (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
  901. (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
  902. hipri = cheetah_get_hipri(afsr);
  903. printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
  904. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  905. hipri, cheetah_get_string(hipri));
  906. /* Try to get unumber if relevant. */
  907. #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
  908. CHAFSR_CPC | CHAFSR_CPU | \
  909. CHAFSR_UE | CHAFSR_CE | \
  910. CHAFSR_EDC | CHAFSR_EDU | \
  911. CHAFSR_UCC | CHAFSR_UCU | \
  912. CHAFSR_WDU | CHAFSR_WDC)
  913. #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
  914. if (afsr & ESYND_ERRORS) {
  915. int syndrome;
  916. int ret;
  917. syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
  918. syndrome = cheetah_ecc_syntab[syndrome];
  919. ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
  920. if (ret != -1)
  921. printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
  922. (recoverable ? KERN_WARNING : KERN_CRIT),
  923. smp_processor_id(), unum);
  924. } else if (afsr & MSYND_ERRORS) {
  925. int syndrome;
  926. int ret;
  927. syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
  928. syndrome = cheetah_mtag_syntab[syndrome];
  929. ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
  930. if (ret != -1)
  931. printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
  932. (recoverable ? KERN_WARNING : KERN_CRIT),
  933. smp_processor_id(), unum);
  934. }
  935. /* Now dump the cache snapshots. */
  936. printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
  937. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  938. (int) info->dcache_index,
  939. info->dcache_tag,
  940. info->dcache_utag,
  941. info->dcache_stag);
  942. printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
  943. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  944. info->dcache_data[0],
  945. info->dcache_data[1],
  946. info->dcache_data[2],
  947. info->dcache_data[3]);
  948. printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
  949. "u[%016lx] l[%016lx]\n",
  950. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  951. (int) info->icache_index,
  952. info->icache_tag,
  953. info->icache_utag,
  954. info->icache_stag,
  955. info->icache_upper,
  956. info->icache_lower);
  957. printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
  958. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  959. info->icache_data[0],
  960. info->icache_data[1],
  961. info->icache_data[2],
  962. info->icache_data[3]);
  963. printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
  964. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  965. info->icache_data[4],
  966. info->icache_data[5],
  967. info->icache_data[6],
  968. info->icache_data[7]);
  969. printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
  970. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  971. (int) info->ecache_index, info->ecache_tag);
  972. printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
  973. (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
  974. info->ecache_data[0],
  975. info->ecache_data[1],
  976. info->ecache_data[2],
  977. info->ecache_data[3]);
  978. afsr = (afsr & ~hipri) & cheetah_afsr_errors;
  979. while (afsr != 0UL) {
  980. unsigned long bit = cheetah_get_hipri(afsr);
  981. printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
  982. (recoverable ? KERN_WARNING : KERN_CRIT),
  983. bit, cheetah_get_string(bit));
  984. afsr &= ~bit;
  985. }
  986. if (!recoverable)
  987. printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
  988. }
  989. static int cheetah_recheck_errors(struct cheetah_err_info *logp)
  990. {
  991. unsigned long afsr, afar;
  992. int ret = 0;
  993. __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
  994. : "=r" (afsr)
  995. : "i" (ASI_AFSR));
  996. if ((afsr & cheetah_afsr_errors) != 0) {
  997. if (logp != NULL) {
  998. __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
  999. : "=r" (afar)
  1000. : "i" (ASI_AFAR));
  1001. logp->afsr = afsr;
  1002. logp->afar = afar;
  1003. }
  1004. ret = 1;
  1005. }
  1006. __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
  1007. "membar #Sync\n\t"
  1008. : : "r" (afsr), "i" (ASI_AFSR));
  1009. return ret;
  1010. }
  1011. void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
  1012. {
  1013. struct cheetah_err_info local_snapshot, *p;
  1014. int recoverable;
  1015. /* Flush E-cache */
  1016. cheetah_flush_ecache();
  1017. p = cheetah_get_error_log(afsr);
  1018. if (!p) {
  1019. prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
  1020. afsr, afar);
  1021. prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
  1022. smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
  1023. prom_halt();
  1024. }
  1025. /* Grab snapshot of logged error. */
  1026. memcpy(&local_snapshot, p, sizeof(local_snapshot));
  1027. /* If the current trap snapshot does not match what the
  1028. * trap handler passed along into our args, big trouble.
  1029. * In such a case, mark the local copy as invalid.
  1030. *
  1031. * Else, it matches and we mark the afsr in the non-local
  1032. * copy as invalid so we may log new error traps there.
  1033. */
  1034. if (p->afsr != afsr || p->afar != afar)
  1035. local_snapshot.afsr = CHAFSR_INVALID;
  1036. else
  1037. p->afsr = CHAFSR_INVALID;
  1038. cheetah_flush_icache();
  1039. cheetah_flush_dcache();
  1040. /* Re-enable I-cache/D-cache */
  1041. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1042. "or %%g1, %1, %%g1\n\t"
  1043. "stxa %%g1, [%%g0] %0\n\t"
  1044. "membar #Sync"
  1045. : /* no outputs */
  1046. : "i" (ASI_DCU_CONTROL_REG),
  1047. "i" (DCU_DC | DCU_IC)
  1048. : "g1");
  1049. /* Re-enable error reporting */
  1050. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1051. "or %%g1, %1, %%g1\n\t"
  1052. "stxa %%g1, [%%g0] %0\n\t"
  1053. "membar #Sync"
  1054. : /* no outputs */
  1055. : "i" (ASI_ESTATE_ERROR_EN),
  1056. "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
  1057. : "g1");
  1058. /* Decide if we can continue after handling this trap and
  1059. * logging the error.
  1060. */
  1061. recoverable = 1;
  1062. if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
  1063. recoverable = 0;
  1064. /* Re-check AFSR/AFAR. What we are looking for here is whether a new
  1065. * error was logged while we had error reporting traps disabled.
  1066. */
  1067. if (cheetah_recheck_errors(&local_snapshot)) {
  1068. unsigned long new_afsr = local_snapshot.afsr;
  1069. /* If we got a new asynchronous error, die... */
  1070. if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
  1071. CHAFSR_WDU | CHAFSR_CPU |
  1072. CHAFSR_IVU | CHAFSR_UE |
  1073. CHAFSR_BERR | CHAFSR_TO))
  1074. recoverable = 0;
  1075. }
  1076. /* Log errors. */
  1077. cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
  1078. if (!recoverable)
  1079. panic("Irrecoverable Fast-ECC error trap.\n");
  1080. /* Flush E-cache to kick the error trap handlers out. */
  1081. cheetah_flush_ecache();
  1082. }
  1083. /* Try to fix a correctable error by pushing the line out from
  1084. * the E-cache. Recheck error reporting registers to see if the
  1085. * problem is intermittent.
  1086. */
  1087. static int cheetah_fix_ce(unsigned long physaddr)
  1088. {
  1089. unsigned long orig_estate;
  1090. unsigned long alias1, alias2;
  1091. int ret;
  1092. /* Make sure correctable error traps are disabled. */
  1093. __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
  1094. "andn %0, %1, %%g1\n\t"
  1095. "stxa %%g1, [%%g0] %2\n\t"
  1096. "membar #Sync"
  1097. : "=&r" (orig_estate)
  1098. : "i" (ESTATE_ERROR_CEEN),
  1099. "i" (ASI_ESTATE_ERROR_EN)
  1100. : "g1");
  1101. /* We calculate alias addresses that will force the
  1102. * cache line in question out of the E-cache. Then
  1103. * we bring it back in with an atomic instruction so
  1104. * that we get it in some modified/exclusive state,
  1105. * then we displace it again to try and get proper ECC
  1106. * pushed back into the system.
  1107. */
  1108. physaddr &= ~(8UL - 1UL);
  1109. alias1 = (ecache_flush_physbase +
  1110. (physaddr & ((ecache_flush_size >> 1) - 1)));
  1111. alias2 = alias1 + (ecache_flush_size >> 1);
  1112. __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
  1113. "ldxa [%1] %3, %%g0\n\t"
  1114. "casxa [%2] %3, %%g0, %%g0\n\t"
  1115. "membar #StoreLoad | #StoreStore\n\t"
  1116. "ldxa [%0] %3, %%g0\n\t"
  1117. "ldxa [%1] %3, %%g0\n\t"
  1118. "membar #Sync"
  1119. : /* no outputs */
  1120. : "r" (alias1), "r" (alias2),
  1121. "r" (physaddr), "i" (ASI_PHYS_USE_EC));
  1122. /* Did that trigger another error? */
  1123. if (cheetah_recheck_errors(NULL)) {
  1124. /* Try one more time. */
  1125. __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
  1126. "membar #Sync"
  1127. : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
  1128. if (cheetah_recheck_errors(NULL))
  1129. ret = 2;
  1130. else
  1131. ret = 1;
  1132. } else {
  1133. /* No new error, intermittent problem. */
  1134. ret = 0;
  1135. }
  1136. /* Restore error enables. */
  1137. __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
  1138. "membar #Sync"
  1139. : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
  1140. return ret;
  1141. }
  1142. /* Return non-zero if PADDR is a valid physical memory address. */
  1143. static int cheetah_check_main_memory(unsigned long paddr)
  1144. {
  1145. int i;
  1146. for (i = 0; ; i++) {
  1147. if (sp_banks[i].num_bytes == 0)
  1148. break;
  1149. if (paddr >= sp_banks[i].base_addr &&
  1150. paddr < (sp_banks[i].base_addr + sp_banks[i].num_bytes))
  1151. return 1;
  1152. }
  1153. return 0;
  1154. }
  1155. void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
  1156. {
  1157. struct cheetah_err_info local_snapshot, *p;
  1158. int recoverable, is_memory;
  1159. p = cheetah_get_error_log(afsr);
  1160. if (!p) {
  1161. prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
  1162. afsr, afar);
  1163. prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
  1164. smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
  1165. prom_halt();
  1166. }
  1167. /* Grab snapshot of logged error. */
  1168. memcpy(&local_snapshot, p, sizeof(local_snapshot));
  1169. /* If the current trap snapshot does not match what the
  1170. * trap handler passed along into our args, big trouble.
  1171. * In such a case, mark the local copy as invalid.
  1172. *
  1173. * Else, it matches and we mark the afsr in the non-local
  1174. * copy as invalid so we may log new error traps there.
  1175. */
  1176. if (p->afsr != afsr || p->afar != afar)
  1177. local_snapshot.afsr = CHAFSR_INVALID;
  1178. else
  1179. p->afsr = CHAFSR_INVALID;
  1180. is_memory = cheetah_check_main_memory(afar);
  1181. if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
  1182. /* XXX Might want to log the results of this operation
  1183. * XXX somewhere... -DaveM
  1184. */
  1185. cheetah_fix_ce(afar);
  1186. }
  1187. {
  1188. int flush_all, flush_line;
  1189. flush_all = flush_line = 0;
  1190. if ((afsr & CHAFSR_EDC) != 0UL) {
  1191. if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
  1192. flush_line = 1;
  1193. else
  1194. flush_all = 1;
  1195. } else if ((afsr & CHAFSR_CPC) != 0UL) {
  1196. if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
  1197. flush_line = 1;
  1198. else
  1199. flush_all = 1;
  1200. }
  1201. /* Trap handler only disabled I-cache, flush it. */
  1202. cheetah_flush_icache();
  1203. /* Re-enable I-cache */
  1204. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1205. "or %%g1, %1, %%g1\n\t"
  1206. "stxa %%g1, [%%g0] %0\n\t"
  1207. "membar #Sync"
  1208. : /* no outputs */
  1209. : "i" (ASI_DCU_CONTROL_REG),
  1210. "i" (DCU_IC)
  1211. : "g1");
  1212. if (flush_all)
  1213. cheetah_flush_ecache();
  1214. else if (flush_line)
  1215. cheetah_flush_ecache_line(afar);
  1216. }
  1217. /* Re-enable error reporting */
  1218. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1219. "or %%g1, %1, %%g1\n\t"
  1220. "stxa %%g1, [%%g0] %0\n\t"
  1221. "membar #Sync"
  1222. : /* no outputs */
  1223. : "i" (ASI_ESTATE_ERROR_EN),
  1224. "i" (ESTATE_ERROR_CEEN)
  1225. : "g1");
  1226. /* Decide if we can continue after handling this trap and
  1227. * logging the error.
  1228. */
  1229. recoverable = 1;
  1230. if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
  1231. recoverable = 0;
  1232. /* Re-check AFSR/AFAR */
  1233. (void) cheetah_recheck_errors(&local_snapshot);
  1234. /* Log errors. */
  1235. cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
  1236. if (!recoverable)
  1237. panic("Irrecoverable Correctable-ECC error trap.\n");
  1238. }
  1239. void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
  1240. {
  1241. struct cheetah_err_info local_snapshot, *p;
  1242. int recoverable, is_memory;
  1243. #ifdef CONFIG_PCI
  1244. /* Check for the special PCI poke sequence. */
  1245. if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
  1246. cheetah_flush_icache();
  1247. cheetah_flush_dcache();
  1248. /* Re-enable I-cache/D-cache */
  1249. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1250. "or %%g1, %1, %%g1\n\t"
  1251. "stxa %%g1, [%%g0] %0\n\t"
  1252. "membar #Sync"
  1253. : /* no outputs */
  1254. : "i" (ASI_DCU_CONTROL_REG),
  1255. "i" (DCU_DC | DCU_IC)
  1256. : "g1");
  1257. /* Re-enable error reporting */
  1258. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1259. "or %%g1, %1, %%g1\n\t"
  1260. "stxa %%g1, [%%g0] %0\n\t"
  1261. "membar #Sync"
  1262. : /* no outputs */
  1263. : "i" (ASI_ESTATE_ERROR_EN),
  1264. "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
  1265. : "g1");
  1266. (void) cheetah_recheck_errors(NULL);
  1267. pci_poke_faulted = 1;
  1268. regs->tpc += 4;
  1269. regs->tnpc = regs->tpc + 4;
  1270. return;
  1271. }
  1272. #endif
  1273. p = cheetah_get_error_log(afsr);
  1274. if (!p) {
  1275. prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
  1276. afsr, afar);
  1277. prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
  1278. smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
  1279. prom_halt();
  1280. }
  1281. /* Grab snapshot of logged error. */
  1282. memcpy(&local_snapshot, p, sizeof(local_snapshot));
  1283. /* If the current trap snapshot does not match what the
  1284. * trap handler passed along into our args, big trouble.
  1285. * In such a case, mark the local copy as invalid.
  1286. *
  1287. * Else, it matches and we mark the afsr in the non-local
  1288. * copy as invalid so we may log new error traps there.
  1289. */
  1290. if (p->afsr != afsr || p->afar != afar)
  1291. local_snapshot.afsr = CHAFSR_INVALID;
  1292. else
  1293. p->afsr = CHAFSR_INVALID;
  1294. is_memory = cheetah_check_main_memory(afar);
  1295. {
  1296. int flush_all, flush_line;
  1297. flush_all = flush_line = 0;
  1298. if ((afsr & CHAFSR_EDU) != 0UL) {
  1299. if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
  1300. flush_line = 1;
  1301. else
  1302. flush_all = 1;
  1303. } else if ((afsr & CHAFSR_BERR) != 0UL) {
  1304. if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
  1305. flush_line = 1;
  1306. else
  1307. flush_all = 1;
  1308. }
  1309. cheetah_flush_icache();
  1310. cheetah_flush_dcache();
  1311. /* Re-enable I/D caches */
  1312. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1313. "or %%g1, %1, %%g1\n\t"
  1314. "stxa %%g1, [%%g0] %0\n\t"
  1315. "membar #Sync"
  1316. : /* no outputs */
  1317. : "i" (ASI_DCU_CONTROL_REG),
  1318. "i" (DCU_IC | DCU_DC)
  1319. : "g1");
  1320. if (flush_all)
  1321. cheetah_flush_ecache();
  1322. else if (flush_line)
  1323. cheetah_flush_ecache_line(afar);
  1324. }
  1325. /* Re-enable error reporting */
  1326. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1327. "or %%g1, %1, %%g1\n\t"
  1328. "stxa %%g1, [%%g0] %0\n\t"
  1329. "membar #Sync"
  1330. : /* no outputs */
  1331. : "i" (ASI_ESTATE_ERROR_EN),
  1332. "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
  1333. : "g1");
  1334. /* Decide if we can continue after handling this trap and
  1335. * logging the error.
  1336. */
  1337. recoverable = 1;
  1338. if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
  1339. recoverable = 0;
  1340. /* Re-check AFSR/AFAR. What we are looking for here is whether a new
  1341. * error was logged while we had error reporting traps disabled.
  1342. */
  1343. if (cheetah_recheck_errors(&local_snapshot)) {
  1344. unsigned long new_afsr = local_snapshot.afsr;
  1345. /* If we got a new asynchronous error, die... */
  1346. if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
  1347. CHAFSR_WDU | CHAFSR_CPU |
  1348. CHAFSR_IVU | CHAFSR_UE |
  1349. CHAFSR_BERR | CHAFSR_TO))
  1350. recoverable = 0;
  1351. }
  1352. /* Log errors. */
  1353. cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
  1354. /* "Recoverable" here means we try to yank the page from ever
  1355. * being newly used again. This depends upon a few things:
  1356. * 1) Must be main memory, and AFAR must be valid.
  1357. * 2) If we trapped from user, OK.
  1358. * 3) Else, if we trapped from kernel we must find exception
  1359. * table entry (ie. we have to have been accessing user
  1360. * space).
  1361. *
  1362. * If AFAR is not in main memory, or we trapped from kernel
  1363. * and cannot find an exception table entry, it is unacceptable
  1364. * to try and continue.
  1365. */
  1366. if (recoverable && is_memory) {
  1367. if ((regs->tstate & TSTATE_PRIV) == 0UL) {
  1368. /* OK, usermode access. */
  1369. recoverable = 1;
  1370. } else {
  1371. unsigned long g2 = regs->u_regs[UREG_G2];
  1372. unsigned long fixup = search_extables_range(regs->tpc, &g2);
  1373. if (fixup != 0UL) {
  1374. /* OK, kernel access to userspace. */
  1375. recoverable = 1;
  1376. } else {
  1377. /* BAD, privileged state is corrupted. */
  1378. recoverable = 0;
  1379. }
  1380. if (recoverable) {
  1381. if (pfn_valid(afar >> PAGE_SHIFT))
  1382. get_page(pfn_to_page(afar >> PAGE_SHIFT));
  1383. else
  1384. recoverable = 0;
  1385. /* Only perform fixup if we still have a
  1386. * recoverable condition.
  1387. */
  1388. if (recoverable) {
  1389. regs->tpc = fixup;
  1390. regs->tnpc = regs->tpc + 4;
  1391. regs->u_regs[UREG_G2] = g2;
  1392. }
  1393. }
  1394. }
  1395. } else {
  1396. recoverable = 0;
  1397. }
  1398. if (!recoverable)
  1399. panic("Irrecoverable deferred error trap.\n");
  1400. }
  1401. /* Handle a D/I cache parity error trap. TYPE is encoded as:
  1402. *
  1403. * Bit0: 0=dcache,1=icache
  1404. * Bit1: 0=recoverable,1=unrecoverable
  1405. *
  1406. * The hardware has disabled both the I-cache and D-cache in
  1407. * the %dcr register.
  1408. */
  1409. void cheetah_plus_parity_error(int type, struct pt_regs *regs)
  1410. {
  1411. if (type & 0x1)
  1412. __cheetah_flush_icache();
  1413. else
  1414. cheetah_plus_zap_dcache_parity();
  1415. cheetah_flush_dcache();
  1416. /* Re-enable I-cache/D-cache */
  1417. __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
  1418. "or %%g1, %1, %%g1\n\t"
  1419. "stxa %%g1, [%%g0] %0\n\t"
  1420. "membar #Sync"
  1421. : /* no outputs */
  1422. : "i" (ASI_DCU_CONTROL_REG),
  1423. "i" (DCU_DC | DCU_IC)
  1424. : "g1");
  1425. if (type & 0x2) {
  1426. printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
  1427. smp_processor_id(),
  1428. (type & 0x1) ? 'I' : 'D',
  1429. regs->tpc);
  1430. panic("Irrecoverable Cheetah+ parity error.");
  1431. }
  1432. printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
  1433. smp_processor_id(),
  1434. (type & 0x1) ? 'I' : 'D',
  1435. regs->tpc);
  1436. }
  1437. void do_fpe_common(struct pt_regs *regs)
  1438. {
  1439. if (regs->tstate & TSTATE_PRIV) {
  1440. regs->tpc = regs->tnpc;
  1441. regs->tnpc += 4;
  1442. } else {
  1443. unsigned long fsr = current_thread_info()->xfsr[0];
  1444. siginfo_t info;
  1445. if (test_thread_flag(TIF_32BIT)) {
  1446. regs->tpc &= 0xffffffff;
  1447. regs->tnpc &= 0xffffffff;
  1448. }
  1449. info.si_signo = SIGFPE;
  1450. info.si_errno = 0;
  1451. info.si_addr = (void __user *)regs->tpc;
  1452. info.si_trapno = 0;
  1453. info.si_code = __SI_FAULT;
  1454. if ((fsr & 0x1c000) == (1 << 14)) {
  1455. if (fsr & 0x10)
  1456. info.si_code = FPE_FLTINV;
  1457. else if (fsr & 0x08)
  1458. info.si_code = FPE_FLTOVF;
  1459. else if (fsr & 0x04)
  1460. info.si_code = FPE_FLTUND;
  1461. else if (fsr & 0x02)
  1462. info.si_code = FPE_FLTDIV;
  1463. else if (fsr & 0x01)
  1464. info.si_code = FPE_FLTRES;
  1465. }
  1466. force_sig_info(SIGFPE, &info, current);
  1467. }
  1468. }
  1469. void do_fpieee(struct pt_regs *regs)
  1470. {
  1471. if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
  1472. 0, 0x24, SIGFPE) == NOTIFY_STOP)
  1473. return;
  1474. do_fpe_common(regs);
  1475. }
  1476. extern int do_mathemu(struct pt_regs *, struct fpustate *);
  1477. void do_fpother(struct pt_regs *regs)
  1478. {
  1479. struct fpustate *f = FPUSTATE;
  1480. int ret = 0;
  1481. if (notify_die(DIE_TRAP, "fpu exception other", regs,
  1482. 0, 0x25, SIGFPE) == NOTIFY_STOP)
  1483. return;
  1484. switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
  1485. case (2 << 14): /* unfinished_FPop */
  1486. case (3 << 14): /* unimplemented_FPop */
  1487. ret = do_mathemu(regs, f);
  1488. break;
  1489. }
  1490. if (ret)
  1491. return;
  1492. do_fpe_common(regs);
  1493. }
  1494. void do_tof(struct pt_regs *regs)
  1495. {
  1496. siginfo_t info;
  1497. if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
  1498. 0, 0x26, SIGEMT) == NOTIFY_STOP)
  1499. return;
  1500. if (regs->tstate & TSTATE_PRIV)
  1501. die_if_kernel("Penguin overflow trap from kernel mode", regs);
  1502. if (test_thread_flag(TIF_32BIT)) {
  1503. regs->tpc &= 0xffffffff;
  1504. regs->tnpc &= 0xffffffff;
  1505. }
  1506. info.si_signo = SIGEMT;
  1507. info.si_errno = 0;
  1508. info.si_code = EMT_TAGOVF;
  1509. info.si_addr = (void __user *)regs->tpc;
  1510. info.si_trapno = 0;
  1511. force_sig_info(SIGEMT, &info, current);
  1512. }
  1513. void do_div0(struct pt_regs *regs)
  1514. {
  1515. siginfo_t info;
  1516. if (notify_die(DIE_TRAP, "integer division by zero", regs,
  1517. 0, 0x28, SIGFPE) == NOTIFY_STOP)
  1518. return;
  1519. if (regs->tstate & TSTATE_PRIV)
  1520. die_if_kernel("TL0: Kernel divide by zero.", regs);
  1521. if (test_thread_flag(TIF_32BIT)) {
  1522. regs->tpc &= 0xffffffff;
  1523. regs->tnpc &= 0xffffffff;
  1524. }
  1525. info.si_signo = SIGFPE;
  1526. info.si_errno = 0;
  1527. info.si_code = FPE_INTDIV;
  1528. info.si_addr = (void __user *)regs->tpc;
  1529. info.si_trapno = 0;
  1530. force_sig_info(SIGFPE, &info, current);
  1531. }
  1532. void instruction_dump (unsigned int *pc)
  1533. {
  1534. int i;
  1535. if ((((unsigned long) pc) & 3))
  1536. return;
  1537. printk("Instruction DUMP:");
  1538. for (i = -3; i < 6; i++)
  1539. printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
  1540. printk("\n");
  1541. }
  1542. static void user_instruction_dump (unsigned int __user *pc)
  1543. {
  1544. int i;
  1545. unsigned int buf[9];
  1546. if ((((unsigned long) pc) & 3))
  1547. return;
  1548. if (copy_from_user(buf, pc - 3, sizeof(buf)))
  1549. return;
  1550. printk("Instruction DUMP:");
  1551. for (i = 0; i < 9; i++)
  1552. printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
  1553. printk("\n");
  1554. }
  1555. void show_stack(struct task_struct *tsk, unsigned long *_ksp)
  1556. {
  1557. unsigned long pc, fp, thread_base, ksp;
  1558. struct thread_info *tp = tsk->thread_info;
  1559. struct reg_window *rw;
  1560. int count = 0;
  1561. ksp = (unsigned long) _ksp;
  1562. if (tp == current_thread_info())
  1563. flushw_all();
  1564. fp = ksp + STACK_BIAS;
  1565. thread_base = (unsigned long) tp;
  1566. printk("Call Trace:");
  1567. #ifdef CONFIG_KALLSYMS
  1568. printk("\n");
  1569. #endif
  1570. do {
  1571. /* Bogus frame pointer? */
  1572. if (fp < (thread_base + sizeof(struct thread_info)) ||
  1573. fp >= (thread_base + THREAD_SIZE))
  1574. break;
  1575. rw = (struct reg_window *)fp;
  1576. pc = rw->ins[7];
  1577. printk(" [%016lx] ", pc);
  1578. print_symbol("%s\n", pc);
  1579. fp = rw->ins[6] + STACK_BIAS;
  1580. } while (++count < 16);
  1581. #ifndef CONFIG_KALLSYMS
  1582. printk("\n");
  1583. #endif
  1584. }
  1585. void dump_stack(void)
  1586. {
  1587. unsigned long *ksp;
  1588. __asm__ __volatile__("mov %%fp, %0"
  1589. : "=r" (ksp));
  1590. show_stack(current, ksp);
  1591. }
  1592. EXPORT_SYMBOL(dump_stack);
  1593. static inline int is_kernel_stack(struct task_struct *task,
  1594. struct reg_window *rw)
  1595. {
  1596. unsigned long rw_addr = (unsigned long) rw;
  1597. unsigned long thread_base, thread_end;
  1598. if (rw_addr < PAGE_OFFSET) {
  1599. if (task != &init_task)
  1600. return 0;
  1601. }
  1602. thread_base = (unsigned long) task->thread_info;
  1603. thread_end = thread_base + sizeof(union thread_union);
  1604. if (rw_addr >= thread_base &&
  1605. rw_addr < thread_end &&
  1606. !(rw_addr & 0x7UL))
  1607. return 1;
  1608. return 0;
  1609. }
  1610. static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
  1611. {
  1612. unsigned long fp = rw->ins[6];
  1613. if (!fp)
  1614. return NULL;
  1615. return (struct reg_window *) (fp + STACK_BIAS);
  1616. }
  1617. void die_if_kernel(char *str, struct pt_regs *regs)
  1618. {
  1619. static int die_counter;
  1620. extern void __show_regs(struct pt_regs * regs);
  1621. extern void smp_report_regs(void);
  1622. int count = 0;
  1623. /* Amuse the user. */
  1624. printk(
  1625. " \\|/ ____ \\|/\n"
  1626. " \"@'/ .. \\`@\"\n"
  1627. " /_| \\__/ |_\\\n"
  1628. " \\__U_/\n");
  1629. printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
  1630. notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
  1631. __asm__ __volatile__("flushw");
  1632. __show_regs(regs);
  1633. if (regs->tstate & TSTATE_PRIV) {
  1634. struct reg_window *rw = (struct reg_window *)
  1635. (regs->u_regs[UREG_FP] + STACK_BIAS);
  1636. /* Stop the back trace when we hit userland or we
  1637. * find some badly aligned kernel stack.
  1638. */
  1639. while (rw &&
  1640. count++ < 30&&
  1641. is_kernel_stack(current, rw)) {
  1642. printk("Caller[%016lx]", rw->ins[7]);
  1643. print_symbol(": %s", rw->ins[7]);
  1644. printk("\n");
  1645. rw = kernel_stack_up(rw);
  1646. }
  1647. instruction_dump ((unsigned int *) regs->tpc);
  1648. } else {
  1649. if (test_thread_flag(TIF_32BIT)) {
  1650. regs->tpc &= 0xffffffff;
  1651. regs->tnpc &= 0xffffffff;
  1652. }
  1653. user_instruction_dump ((unsigned int __user *) regs->tpc);
  1654. }
  1655. #ifdef CONFIG_SMP
  1656. smp_report_regs();
  1657. #endif
  1658. if (regs->tstate & TSTATE_PRIV)
  1659. do_exit(SIGKILL);
  1660. do_exit(SIGSEGV);
  1661. }
  1662. extern int handle_popc(u32 insn, struct pt_regs *regs);
  1663. extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
  1664. void do_illegal_instruction(struct pt_regs *regs)
  1665. {
  1666. unsigned long pc = regs->tpc;
  1667. unsigned long tstate = regs->tstate;
  1668. u32 insn;
  1669. siginfo_t info;
  1670. if (notify_die(DIE_TRAP, "illegal instruction", regs,
  1671. 0, 0x10, SIGILL) == NOTIFY_STOP)
  1672. return;
  1673. if (tstate & TSTATE_PRIV)
  1674. die_if_kernel("Kernel illegal instruction", regs);
  1675. if (test_thread_flag(TIF_32BIT))
  1676. pc = (u32)pc;
  1677. if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
  1678. if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
  1679. if (handle_popc(insn, regs))
  1680. return;
  1681. } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
  1682. if (handle_ldf_stq(insn, regs))
  1683. return;
  1684. }
  1685. }
  1686. info.si_signo = SIGILL;
  1687. info.si_errno = 0;
  1688. info.si_code = ILL_ILLOPC;
  1689. info.si_addr = (void __user *)pc;
  1690. info.si_trapno = 0;
  1691. force_sig_info(SIGILL, &info, current);
  1692. }
  1693. void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
  1694. {
  1695. siginfo_t info;
  1696. if (notify_die(DIE_TRAP, "memory address unaligned", regs,
  1697. 0, 0x34, SIGSEGV) == NOTIFY_STOP)
  1698. return;
  1699. if (regs->tstate & TSTATE_PRIV) {
  1700. extern void kernel_unaligned_trap(struct pt_regs *regs,
  1701. unsigned int insn,
  1702. unsigned long sfar,
  1703. unsigned long sfsr);
  1704. kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc),
  1705. sfar, sfsr);
  1706. return;
  1707. }
  1708. info.si_signo = SIGBUS;
  1709. info.si_errno = 0;
  1710. info.si_code = BUS_ADRALN;
  1711. info.si_addr = (void __user *)sfar;
  1712. info.si_trapno = 0;
  1713. force_sig_info(SIGBUS, &info, current);
  1714. }
  1715. void do_privop(struct pt_regs *regs)
  1716. {
  1717. siginfo_t info;
  1718. if (notify_die(DIE_TRAP, "privileged operation", regs,
  1719. 0, 0x11, SIGILL) == NOTIFY_STOP)
  1720. return;
  1721. if (test_thread_flag(TIF_32BIT)) {
  1722. regs->tpc &= 0xffffffff;
  1723. regs->tnpc &= 0xffffffff;
  1724. }
  1725. info.si_signo = SIGILL;
  1726. info.si_errno = 0;
  1727. info.si_code = ILL_PRVOPC;
  1728. info.si_addr = (void __user *)regs->tpc;
  1729. info.si_trapno = 0;
  1730. force_sig_info(SIGILL, &info, current);
  1731. }
  1732. void do_privact(struct pt_regs *regs)
  1733. {
  1734. do_privop(regs);
  1735. }
  1736. /* Trap level 1 stuff or other traps we should never see... */
  1737. void do_cee(struct pt_regs *regs)
  1738. {
  1739. die_if_kernel("TL0: Cache Error Exception", regs);
  1740. }
  1741. void do_cee_tl1(struct pt_regs *regs)
  1742. {
  1743. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1744. die_if_kernel("TL1: Cache Error Exception", regs);
  1745. }
  1746. void do_dae_tl1(struct pt_regs *regs)
  1747. {
  1748. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1749. die_if_kernel("TL1: Data Access Exception", regs);
  1750. }
  1751. void do_iae_tl1(struct pt_regs *regs)
  1752. {
  1753. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1754. die_if_kernel("TL1: Instruction Access Exception", regs);
  1755. }
  1756. void do_div0_tl1(struct pt_regs *regs)
  1757. {
  1758. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1759. die_if_kernel("TL1: DIV0 Exception", regs);
  1760. }
  1761. void do_fpdis_tl1(struct pt_regs *regs)
  1762. {
  1763. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1764. die_if_kernel("TL1: FPU Disabled", regs);
  1765. }
  1766. void do_fpieee_tl1(struct pt_regs *regs)
  1767. {
  1768. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1769. die_if_kernel("TL1: FPU IEEE Exception", regs);
  1770. }
  1771. void do_fpother_tl1(struct pt_regs *regs)
  1772. {
  1773. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1774. die_if_kernel("TL1: FPU Other Exception", regs);
  1775. }
  1776. void do_ill_tl1(struct pt_regs *regs)
  1777. {
  1778. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1779. die_if_kernel("TL1: Illegal Instruction Exception", regs);
  1780. }
  1781. void do_irq_tl1(struct pt_regs *regs)
  1782. {
  1783. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1784. die_if_kernel("TL1: IRQ Exception", regs);
  1785. }
  1786. void do_lddfmna_tl1(struct pt_regs *regs)
  1787. {
  1788. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1789. die_if_kernel("TL1: LDDF Exception", regs);
  1790. }
  1791. void do_stdfmna_tl1(struct pt_regs *regs)
  1792. {
  1793. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1794. die_if_kernel("TL1: STDF Exception", regs);
  1795. }
  1796. void do_paw(struct pt_regs *regs)
  1797. {
  1798. die_if_kernel("TL0: Phys Watchpoint Exception", regs);
  1799. }
  1800. void do_paw_tl1(struct pt_regs *regs)
  1801. {
  1802. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1803. die_if_kernel("TL1: Phys Watchpoint Exception", regs);
  1804. }
  1805. void do_vaw(struct pt_regs *regs)
  1806. {
  1807. die_if_kernel("TL0: Virt Watchpoint Exception", regs);
  1808. }
  1809. void do_vaw_tl1(struct pt_regs *regs)
  1810. {
  1811. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1812. die_if_kernel("TL1: Virt Watchpoint Exception", regs);
  1813. }
  1814. void do_tof_tl1(struct pt_regs *regs)
  1815. {
  1816. dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
  1817. die_if_kernel("TL1: Tag Overflow Exception", regs);
  1818. }
  1819. void do_getpsr(struct pt_regs *regs)
  1820. {
  1821. regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
  1822. regs->tpc = regs->tnpc;
  1823. regs->tnpc += 4;
  1824. if (test_thread_flag(TIF_32BIT)) {
  1825. regs->tpc &= 0xffffffff;
  1826. regs->tnpc &= 0xffffffff;
  1827. }
  1828. }
  1829. extern void thread_info_offsets_are_bolixed_dave(void);
  1830. /* Only invoked on boot processor. */
  1831. void __init trap_init(void)
  1832. {
  1833. /* Compile time sanity check. */
  1834. if (TI_TASK != offsetof(struct thread_info, task) ||
  1835. TI_FLAGS != offsetof(struct thread_info, flags) ||
  1836. TI_CPU != offsetof(struct thread_info, cpu) ||
  1837. TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
  1838. TI_KSP != offsetof(struct thread_info, ksp) ||
  1839. TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
  1840. TI_KREGS != offsetof(struct thread_info, kregs) ||
  1841. TI_UTRAPS != offsetof(struct thread_info, utraps) ||
  1842. TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
  1843. TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
  1844. TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
  1845. TI_GSR != offsetof(struct thread_info, gsr) ||
  1846. TI_XFSR != offsetof(struct thread_info, xfsr) ||
  1847. TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
  1848. TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
  1849. TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
  1850. TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
  1851. TI_PCR != offsetof(struct thread_info, pcr_reg) ||
  1852. TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) ||
  1853. TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
  1854. TI_FPREGS != offsetof(struct thread_info, fpregs) ||
  1855. (TI_FPREGS & (64 - 1)))
  1856. thread_info_offsets_are_bolixed_dave();
  1857. /* Attach to the address space of init_task. On SMP we
  1858. * do this in smp.c:smp_callin for other cpus.
  1859. */
  1860. atomic_inc(&init_mm.mm_count);
  1861. current->active_mm = &init_mm;
  1862. }