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/grlib-gpl-1.1.0-b4113/lib/micron/ddr/ddr3.v

https://github.com/shmele/leon3
Verilog | 4136 lines | 3641 code | 172 blank | 323 comment | 846 complexity | 45b3fdda80adcde112979602458017ef MD5 | raw file
   1/****************************************************************************************
   2*
   3*    File Name:  ddr3.v
   4*      Version:  1.60
   5*        Model:  BUS Functional
   6*
   7* Dependencies:  ddr3_model_parameters.vh
   8*
   9*  Description:  Micron SDRAM DDR3 (Double Data Rate 3)
  10*
  11*   Limitation:  - doesn't check for average refresh timings
  12*                - positive ck and ck_n edges are used to form internal clock
  13*                - positive dqs and dqs_n edges are used to latch data
  14*                - test mode is not modeled
  15*                - Duty Cycle Corrector is not modeled
  16*                - Temperature Compensated Self Refresh is not modeled
  17*                - DLL off mode is not modeled.
  18*
  19*         Note:  - Set simulator resolution to "ps" accuracy
  20*                - Set DEBUG = 0 to disable $display messages
  21*
  22*   Disclaimer   This software code and all associated documentation, comments or other 
  23*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
  24*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
  25*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
  26*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
  27*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
  28*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
  29*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
  30*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
  31*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
  32*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
  33*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
  34*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
  35*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
  36*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
  37*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
  38*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
  39*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
  40*                limitation of liability for consequential or incidental damages, the 
  41*                above limitation may not apply to you.
  42*
  43*                Copyright 2003 Micron Technology, Inc. All rights reserved.
  44*
  45* Rev   Author   Date        Changes
  46* ---------------------------------------------------------------------------------------
  47* 0.41  JMK      05/12/06    Removed auto-precharge to power down error check.
  48* 0.42  JMK      08/25/06    Created internal clock using ck and ck_n.
  49*                            TDQS can only be enabled in EMR for x8 configurations.
  50*                            CAS latency is checked vs frequency when DLL locks.
  51*                            Improved checking of DQS during writes.
  52*                            Added true BL4 operation.
  53* 0.43  JMK      08/14/06    Added checking for setting reserved bits in Mode Registers.
  54*                            Added ODTS Readout.
  55*                            Replaced tZQCL with tZQinit and tZQoper
  56*                            Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
  57*                            Added tRFC checking for Refresh to Power-Down Re-Entry.
  58*                            Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
  59*                            Added Clock Frequency Change during Precharge Power-Down.
  60*                            Added -125x speed grades.
  61*                            Fixed tRCD checking during Write.
  62* 1.00  JMK      05/11/07    Initial release
  63* 1.10  JMK      06/26/07    Fixed ODTH8 check during BLOTF
  64*                            Removed temp sensor readout from MPR
  65*                            Updated initialization sequence
  66*                            Updated timing parameters
  67* 1.20  JMK      09/05/07    Updated clock frequency change
  68*                            Added ddr3_dimm module
  69* 1.30  JMK      01/23/08    Updated timing parameters
  70* 1.40  JMK      12/02/08    Added support for DDR3-1866 and DDR3-2133
  71*                            renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
  72*                            Added multi-chip package model support in ddr3_mcp.v
  73* 1.50  JMK      05/04/08    Added 1866 and 2133 speed grades.
  74* 1.60  MYY      07/10/09    Merging of 1.50 version and pre-1.0 version changes
  75*****************************************************************************************/
  76// DO NOT CHANGE THE TIMESCALE
  77// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
  78`timescale 1ps / 1ps
  79
  80// model flags
  81// `define MODEL_PASR
  82
  83module ddr3 (
  84    rst_n,
  85    ck,
  86    ck_n,
  87    cke,
  88    cs_n,
  89    ras_n,
  90    cas_n,
  91    we_n,
  92    dm_tdqs,
  93    ba,
  94    addr,
  95    dq,
  96    dqs,
  97    dqs_n,
  98    tdqs_n,
  99    odt
 100);
 101
 102`define x1Gb
 103`define sg187E
 104`define x16
 105
 106/*    `include "ddr3_model_parameters.vh" */
 107
 108
 109/****************************************************************************************
 110*
 111*   Disclaimer   This software code and all associated documentation, comments or other
 112*  of Warranty:  information (collectively "Software") is provided "AS IS" without
 113*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
 114*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
 115*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
 116*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
 117*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
 118*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
 119*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
 120*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
 121*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
 122*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
 123*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
 124*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
 125*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
 126*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
 127*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
 128*                DAMAGES. Because some jurisdictions prohibit the exclusion or
 129*                limitation of liability for consequential or incidental damages, the
 130*                above limitation may not apply to you.
 131*
 132*                Copyright 2003 Micron Technology, Inc. All rights reserved.
 133*
 134****************************************************************************************/
 135
 136    // Parameters current with 1Gb and 2Gb datasheet rev D
 137
 138    // Timing parameters based on Speed Grade
 139
 140                                            // SYMBOL     UNITS DESCRIPTION
 141                                            // ------     ----- -----------
 142`ifdef x1Gb  // 1Gb parameters
 143
 144  `ifdef sg094E                             // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin
 145      parameter TCK_MIN          =   937.5; // tCK        ps    Minimum Clock Cycle Time
 146      parameter TJIT_PER         =      50; // tJIT(per)  ps    Period JItter
 147      parameter TJIT_CC          =     100; // tJIT(cc)   ps    Cycle to Cycle jitter
 148      parameter TERR_2PER        =      73; // tERR(2per) ps    Accumulated Error (2-cycle)
 149      parameter TERR_3PER        =      85; // tERR(3per) ps    Accumulated Error (3-cycle)
 150      parameter TERR_4PER        =      98; // tERR(4per) ps    Accumulated Error (4-cycle)
 151      parameter TERR_5PER        =     105; // tERR(5per) ps    Accumulated Error (5-cycle)
 152      parameter TERR_6PER        =     111; // tERR(6per) ps    Accumulated Error (6-cycle)
 153      parameter TERR_7PER        =     117; // tERR(7per) ps    Accumulated Error (7-cycle)
 154      parameter TERR_8PER        =     121; // tERR(8per) ps    Accumulated Error (8-cycle)
 155      parameter TERR_9PER        =     125; // tERR(9per) ps    Accumulated Error (9-cycle)
 156      parameter TERR_10PER       =     128; // tERR(10per)ps    Accumulated Error (10-cycle)
 157      parameter TERR_11PER       =     132; // tERR(11per)ps    Accumulated Error (11-cycle)
 158      parameter TERR_12PER       =     134; // tERR(12per)ps    Accumulated Error (12-cycle)
 159      parameter TDS              =       5; // tDS        ps    DQ and DM input setup time relative to DQS
 160      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
 161      parameter TDQSQ            =      70; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 162      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 163      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 164      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 165      parameter TDQSCK           =     175; // tDQSCK     ps    DQS output access time from CK/CK#
 166      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 167      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 168      parameter TDIPW            =     275; // tDIPW      ps    DQ and DM input Pulse Width
 169      parameter TIPW             =     455; // tIPW       ps    Control and Address input Pulse Width
 170      parameter TIS              =      35; // tIS        ps    Input Setup Time
 171      parameter TIH              =      75; // tIH        ps    Input Hold Time
 172      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 173      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 174      parameter TRCD             =   12187; // tRCD       ps    Active to Read/Write command time
 175      parameter TRP              =   12187; // tRP        ps    Precharge command period
 176      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 177      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 178      parameter TAON             =     180; // tAON       ps    RTT turn-on from ODTLon reference
 179      parameter TWLS             =     122; // tWLS       ps    Setup time for tDQS flop
 180      parameter TWLH             =     122; // tWLH       ps    Hold time of tDQS flop
 181      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 182      parameter TAA_MIN          =   12187; // TAA        ps    Internal READ command to first data
 183      parameter CL_TIME          =   12187; // CL         ps    Minimum CAS Latency
 184  `else `ifdef sg094                        // sg094  is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
 185      parameter TCK_MIN          =   937.5; // tCK        ps    Minimum Clock Cycle Time
 186      parameter TJIT_PER         =      50; // tJIT(per)  ps    Period JItter
 187      parameter TJIT_CC          =     100; // tJIT(cc)   ps    Cycle to Cycle jitter
 188      parameter TERR_2PER        =      73; // tERR(2per) ps    Accumulated Error (2-cycle)
 189      parameter TERR_3PER        =      85; // tERR(3per) ps    Accumulated Error (3-cycle)
 190      parameter TERR_4PER        =      98; // tERR(4per) ps    Accumulated Error (4-cycle)
 191      parameter TERR_5PER        =     105; // tERR(5per) ps    Accumulated Error (5-cycle)
 192      parameter TERR_6PER        =     111; // tERR(6per) ps    Accumulated Error (6-cycle)
 193      parameter TERR_7PER        =     117; // tERR(7per) ps    Accumulated Error (7-cycle)
 194      parameter TERR_8PER        =     121; // tERR(8per) ps    Accumulated Error (8-cycle)
 195      parameter TERR_9PER        =     125; // tERR(9per) ps    Accumulated Error (9-cycle)
 196      parameter TERR_10PER       =     128; // tERR(10per)ps    Accumulated Error (10-cycle)
 197      parameter TERR_11PER       =     132; // tERR(11per)ps    Accumulated Error (11-cycle)
 198      parameter TERR_12PER       =     134; // tERR(12per)ps    Accumulated Error (12-cycle)
 199      parameter TDS              =       5; // tDS        ps    DQ and DM input setup time relative to DQS
 200      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
 201      parameter TDQSQ            =      70; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 202      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 203      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 204      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 205      parameter TDQSCK           =     175; // tDQSCK     ps    DQS output access time from CK/CK#
 206      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 207      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 208      parameter TDIPW            =     275; // tDIPW      ps    DQ and DM input Pulse Width
 209      parameter TIPW             =     455; // tIPW       ps    Control and Address input Pulse Width
 210      parameter TIS              =      35; // tIS        ps    Input Setup Time
 211      parameter TIH              =      75; // tIH        ps    Input Hold Time
 212      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 213      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 214      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
 215      parameter TRP              =   13125; // tRP        ps    Precharge command period
 216      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 217      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 218      parameter TAON             =     180; // tAON       ps    RTT turn-on from ODTLon reference
 219      parameter TWLS             =     122; // tWLS       ps    Setup time for tDQS flop
 220      parameter TWLH             =     122; // tWLH       ps    Hold time of tDQS flop
 221      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 222      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
 223      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
 224  `else `ifdef sg107F                       // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin
 225      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
 226      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
 227      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
 228      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
 229      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
 230      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
 231      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
 232      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
 233      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
 234      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
 235      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
 236      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
 237      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
 238      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
 239      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 240      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
 241      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 242      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 243      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 244      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 245      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
 246      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 247      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 248      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
 249      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
 250      parameter TIS              =      50; // tIS        ps    Input Setup Time
 251      parameter TIH              =     100; // tIH        ps    Input Hold Time
 252      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 253      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 254      parameter TRCD             =   12857; // tRCD       ps    Active to Read/Write command time
 255      parameter TRP              =   12857; // tRP        ps    Precharge command period
 256      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 257      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 258      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
 259      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
 260      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
 261      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 262      parameter TAA_MIN          =   12857; // TAA        ps    Internal READ command to first data
 263      parameter CL_TIME          =   12857; // CL         ps    Minimum CAS Latency
 264  `else `ifdef sg107E                       // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
 265      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
 266      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
 267      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
 268      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
 269      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
 270      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
 271      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
 272      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
 273      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
 274      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
 275      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
 276      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
 277      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
 278      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
 279      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 280      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
 281      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 282      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 283      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 284      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 285      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
 286      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 287      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 288      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
 289      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
 290      parameter TIS              =      50; // tIS        ps    Input Setup Time
 291      parameter TIH              =     100; // tIH        ps    Input Hold Time
 292      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 293      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 294      parameter TRCD             =   13928; // tRCD       ps    Active to Read/Write command time
 295      parameter TRP              =   13928; // tRP        ps    Precharge command period
 296      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 297      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 298      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
 299      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
 300      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
 301      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 302      parameter TAA_MIN          =   13928; // TAA        ps    Internal READ command to first data
 303      parameter CL_TIME          =   13928; // CL         ps    Minimum CAS Latency
 304  `else `ifdef sg107                        // sg107  is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin
 305      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
 306      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
 307      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
 308      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
 309      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
 310      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
 311      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
 312      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
 313      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
 314      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
 315      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
 316      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
 317      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
 318      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
 319      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 320      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
 321      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 322      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 323      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 324      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 325      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
 326      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 327      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 328      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
 329      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
 330      parameter TIS              =      50; // tIS        ps    Input Setup Time
 331      parameter TIH              =     100; // tIH        ps    Input Hold Time
 332      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 333      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 334      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
 335      parameter TRP              =   15000; // tRP        ps    Precharge command period
 336      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 337      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 338      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
 339      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
 340      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
 341      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 342      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
 343      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
 344  `else `ifdef sg125F                       // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin
 345      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
 346      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
 347      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
 348      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
 349      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
 350      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
 351      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
 352      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
 353      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
 354      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
 355      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
 356      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
 357      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
 358      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
 359      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 360      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
 361      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 362      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 363      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 364      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 365      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
 366      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 367      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 368      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
 369      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
 370      parameter TIS              =     170; // tIS        ps    Input Setup Time
 371      parameter TIH              =     120; // tIH        ps    Input Hold Time
 372      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 373      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
 374      parameter TRCD             =   11250; // tRCD       ps    Active to Read/Write command time
 375      parameter TRP              =   11250; // tRP        ps    Precharge command period
 376      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 377      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 378      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
 379      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
 380      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
 381      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 382      parameter TAA_MIN          =   11250; // TAA        ps    Internal READ command to first data
 383      parameter CL_TIME          =   11250; // CL         ps    Minimum CAS Latency
 384  `else `ifdef sg125E                       // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin
 385      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
 386      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
 387      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
 388      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
 389      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
 390      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
 391      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
 392      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
 393      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
 394      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
 395      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
 396      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
 397      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
 398      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
 399      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 400      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
 401      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 402      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 403      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 404      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 405      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
 406      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 407      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 408      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
 409      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
 410      parameter TIS              =     170; // tIS        ps    Input Setup Time
 411      parameter TIH              =     120; // tIH        ps    Input Hold Time
 412      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 413      parameter TRC              =   47500; // tRC        ps    Active to Active/Auto Refresh command time
 414      parameter TRCD             =   12500; // tRCD       ps    Active to Read/Write command time
 415      parameter TRP              =   12500; // tRP        ps    Precharge command period
 416      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 417      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 418      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
 419      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
 420      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
 421      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 422      parameter TAA_MIN          =   12500; // TAA        ps    Internal READ command to first data
 423      parameter CL_TIME          =   12500; // CL         ps    Minimum CAS Latency
 424  `else `ifdef sg125                        // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
 425      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
 426      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
 427      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
 428      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
 429      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
 430      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
 431      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
 432      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
 433      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
 434      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
 435      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
 436      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
 437      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
 438      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
 439      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
 440      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
 441      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 442      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 443      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 444      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 445      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
 446      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 447      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 448      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
 449      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
 450      parameter TIS              =     170; // tIS        ps    Input Setup Time
 451      parameter TIH              =     120; // tIH        ps    Input Hold Time
 452      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
 453      parameter TRC              =   48750; // tRC        ps    Active to Active/Auto Refresh command time
 454      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
 455      parameter TRP              =   13125; // tRP        ps    Precharge command period
 456      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 457      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
 458      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
 459      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
 460      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
 461      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
 462      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
 463      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
 464  `else `ifdef sg15E                        // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
 465      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
 466      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
 467      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
 468      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
 469      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
 470      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
 471      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
 472      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
 473      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
 474      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
 475      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
 476      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
 477      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
 478      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
 479      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
 480      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
 481      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 482      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 483      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 484      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 485      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
 486      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 487      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 488      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
 489      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
 490      parameter TIS              =     190; // tIS        ps    Input Setup Time
 491      parameter TIH              =     140; // tIH        ps    Input Hold Time
 492      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
 493      parameter TRC              =   49500; // tRC        ps    Active to Active/Auto Refresh command time
 494      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
 495      parameter TRP              =   13125; // tRP        ps    Precharge command period
 496      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 497      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
 498      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
 499      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
 500      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
 501      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 502      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
 503      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
 504  `else `ifdef sg15                         // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
 505      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
 506      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
 507      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
 508      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
 509      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
 510      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
 511      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
 512      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
 513      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
 514      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
 515      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
 516      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
 517      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
 518      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
 519      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
 520      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
 521      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 522      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 523      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 524      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 525      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
 526      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
 527      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
 528      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
 529      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
 530      parameter TIS              =     190; // tIS        ps    Input Setup Time
 531      parameter TIH              =     140; // tIH        ps    Input Hold Time
 532      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
 533      parameter TRC              =   51000; // tRC        ps    Active to Active/Auto Refresh command time
 534      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
 535      parameter TRP              =   15000; // tRP        ps    Precharge command period
 536      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
 537      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
 538      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
 539      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
 540      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
 541      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 542      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
 543      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
 544  `else `ifdef sg187E                       // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
 545      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
 546      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
 547      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
 548      parameter TERR_2PER        =     132; // tERR(2per) ps    Accumulated Error (2-cycle)
 549      parameter TERR_3PER        =     157; // tERR(3per) ps    Accumulated Error (3-cycle)
 550      parameter TERR_4PER        =     175; // tERR(4per) ps    Accumulated Error (4-cycle)
 551      parameter TERR_5PER        =     188; // tERR(5per) ps    Accumulated Error (5-cycle)
 552      parameter TERR_6PER        =     200; // tERR(6per) ps    Accumulated Error (6-cycle)
 553      parameter TERR_7PER        =     209; // tERR(7per) ps    Accumulated Error (7-cycle)
 554      parameter TERR_8PER        =     217; // tERR(8per) ps    Accumulated Error (8-cycle)
 555      parameter TERR_9PER        =     224; // tERR(9per) ps    Accumulated Error (9-cycle)
 556      parameter TERR_10PER       =     231; // tERR(10per)ps    Accumulated Error (10-cycle)
 557      parameter TERR_11PER       =     237; // tERR(11per)ps    Accumulated Error (11-cycle)
 558      parameter TERR_12PER       =     242; // tERR(12per)ps    Accumulated Error (12-cycle)
 559      parameter TDS              =      75; // tDS        ps    DQ and DM input setup time relative to DQS
 560      parameter TDH              =     100; // tDH        ps    DQ and DM input hold time relative to DQS
 561      parameter TDQSQ            =     150; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 562      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 563      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 564      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 565      parameter TDQSCK           =     300; // tDQSCK     ps    DQS output access time from CK/CK#
 566      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
 567      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
 568      parameter TDIPW            =     490; // tDIPW      ps    DQ and DM input Pulse Width
 569      parameter TIPW             =     780; // tIPW       ps    Control and Address input Pulse Width
 570      parameter TIS              =     275; // tIS        ps    Input Setup Time
 571      parameter TIH              =     200; // tIH        ps    Input Hold Time
 572      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
 573      parameter TRC              =   50625; // tRC        ps    Active to Active/Auto Refresh command time
 574      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
 575      parameter TRP              =   13125; // tRP        ps    Precharge command period
 576      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
 577      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
 578      parameter TAON             =     300; // tAON       ps    RTT turn-on from ODTLon reference
 579      parameter TWLS             =     245; // tWLS       ps    Setup time for tDQS flop
 580      parameter TWLH             =     245; // tWLH       ps    Hold time of tDQS flop
 581      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 582      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
 583      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
 584  `else `ifdef sg187                        // sg187  is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
 585      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
 586      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
 587      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
 588      parameter TERR_2PER        =     132; // tERR(2per) ps    Accumulated Error (2-cycle)
 589      parameter TERR_3PER        =     157; // tERR(3per) ps    Accumulated Error (3-cycle)
 590      parameter TERR_4PER        =     175; // tERR(4per) ps    Accumulated Error (4-cycle)
 591      parameter TERR_5PER        =     188; // tERR(5per) ps    Accumulated Error (5-cycle)
 592      parameter TERR_6PER        =     200; // tERR(6per) ps    Accumulated Error (6-cycle)
 593      parameter TERR_7PER        =     209; // tERR(7per) ps    Accumulated Error (7-cycle)
 594      parameter TERR_8PER        =     217; // tERR(8per) ps    Accumulated Error (8-cycle)
 595      parameter TERR_9PER        =     224; // tERR(9per) ps    Accumulated Error (9-cycle)
 596      parameter TERR_10PER       =     231; // tERR(10per)ps    Accumulated Error (10-cycle)
 597      parameter TERR_11PER       =     237; // tERR(11per)ps    Accumulated Error (11-cycle)
 598      parameter TERR_12PER       =     242; // tERR(12per)ps    Accumulated Error (12-cycle)
 599      parameter TDS              =      75; // tDS        ps    DQ and DM input setup time relative to DQS
 600      parameter TDH              =     100; // tDH        ps    DQ and DM input hold time relative to DQS
 601      parameter TDQSQ            =     150; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 602      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 603      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 604      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 605      parameter TDQSCK           =     300; // tDQSCK     ps    DQS output access time from CK/CK#
 606      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
 607      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
 608      parameter TDIPW            =     490; // tDIPW      ps    DQ and DM input Pulse Width
 609      parameter TIPW             =     780; // tIPW       ps    Control and Address input Pulse Width
 610      parameter TIS              =     275; // tIS        ps    Input Setup Time
 611      parameter TIH              =     200; // tIH        ps    Input Hold Time
 612      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
 613      parameter TRC              =   52500; // tRC        ps    Active to Active/Auto Refresh command time
 614      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
 615      parameter TRP              =   15000; // tRP        ps    Precharge command period
 616      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
 617      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
 618      parameter TAON             =     300; // tAON       ps    RTT turn-on from ODTLon reference
 619      parameter TWLS             =     245; // tWLS       ps    Setup time for tDQS flop
 620      parameter TWLH             =     245; // tWLH       ps    Hold time of tDQS flop
 621      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 622      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
 623      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
 624  `else `ifdef sg25E                        // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin
 625      parameter TCK_MIN          =    2500; // tCK        ps    Minimum Clock Cycle Time
 626      parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter
 627      parameter TJIT_CC          =     200; // tJIT(cc)   ps    Cycle to Cycle jitter
 628      parameter TERR_2PER        =     147; // tERR(2per) ps    Accumulated Error (2-cycle)
 629      parameter TERR_3PER        =     175; // tERR(3per) ps    Accumulated Error (3-cycle)
 630      parameter TERR_4PER        =     194; // tERR(4per) ps    Accumulated Error (4-cycle)
 631      parameter TERR_5PER        =     209; // tERR(5per) ps    Accumulated Error (5-cycle)
 632      parameter TERR_6PER        =     222; // tERR(6per) ps    Accumulated Error (6-cycle)
 633      parameter TERR_7PER        =     232; // tERR(7per) ps    Accumulated Error (7-cycle)
 634      parameter TERR_8PER        =     241; // tERR(8per) ps    Accumulated Error (8-cycle)
 635      parameter TERR_9PER        =     249; // tERR(9per) ps    Accumulated Error (9-cycle)
 636      parameter TERR_10PER       =     257; // tERR(10per)ps    Accumulated Error (10-cycle)
 637      parameter TERR_11PER       =     263; // tERR(11per)ps    Accumulated Error (11-cycle)
 638      parameter TERR_12PER       =     269; // tERR(12per)ps    Accumulated Error (12-cycle)
 639      parameter TDS              =     125; // tDS        ps    DQ and DM input setup time relative to DQS
 640      parameter TDH              =     150; // tDH        ps    DQ and DM input hold time relative to DQS
 641      parameter TDQSQ            =     200; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 642      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 643      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 644      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 645      parameter TDQSCK           =     400; // tDQSCK     ps    DQS output access time from CK/CK#
 646      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
 647      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
 648      parameter TDIPW            =     600; // tDIPW      ps    DQ and DM input Pulse Width
 649      parameter TIPW             =     900; // tIPW       ps    Control and Address input Pulse Width
 650      parameter TIS              =     350; // tIS        ps    Input Setup Time
 651      parameter TIH              =     275; // tIH        ps    Input Hold Time
 652      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
 653      parameter TRC              =   50000; // tRC        ps    Active to Active/Auto Refresh command time
 654      parameter TRCD             =   12500; // tRCD       ps    Active to Read/Write command time
 655      parameter TRP              =   12500; // tRP        ps    Precharge command period
 656      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
 657      parameter TCKE             =    7500; // tCKE       ps    CKE minimum high or low pulse width
 658      parameter TAON             =     400; // tAON       ps    RTT turn-on from ODTLon reference
 659      parameter TWLS             =     325; // tWLS       ps    Setup time for tDQS flop
 660      parameter TWLH             =     325; // tWLH       ps    Hold time of tDQS flop
 661      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 662      parameter TAA_MIN          =   12500; // TAA        ps    Internal READ command to first data
 663      parameter CL_TIME          =   12500; // CL         ps    Minimum CAS Latency
 664  `else `define sg25                        // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
 665      parameter TCK_MIN          =    2500; // tCK        ps    Minimum Clock Cycle Time
 666      parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter
 667      parameter TJIT_CC          =     200; // tJIT(cc)   ps    Cycle to Cycle jitter
 668      parameter TERR_2PER        =     147; // tERR(2per) ps    Accumulated Error (2-cycle)
 669      parameter TERR_3PER        =     175; // tERR(3per) ps    Accumulated Error (3-cycle)
 670      parameter TERR_4PER        =     194; // tERR(4per) ps    Accumulated Error (4-cycle)
 671      parameter TERR_5PER        =     209; // tERR(5per) ps    Accumulated Error (5-cycle)
 672      parameter TERR_6PER        =     222; // tERR(6per) ps    Accumulated Error (6-cycle)
 673      parameter TERR_7PER        =     232; // tERR(7per) ps    Accumulated Error (7-cycle)
 674      parameter TERR_8PER        =     241; // tERR(8per) ps    Accumulated Error (8-cycle)
 675      parameter TERR_9PER        =     249; // tERR(9per) ps    Accumulated Error (9-cycle)
 676      parameter TERR_10PER       =     257; // tERR(10per)ps    Accumulated Error (10-cycle)
 677      parameter TERR_11PER       =     263; // tERR(11per)ps    Accumulated Error (11-cycle)
 678      parameter TERR_12PER       =     269; // tERR(12per)ps    Accumulated Error (12-cycle)
 679      parameter TDS              =     125; // tDS        ps    DQ and DM input setup time relative to DQS
 680      parameter TDH              =     150; // tDH        ps    DQ and DM input hold time relative to DQS
 681      parameter TDQSQ            =     200; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
 682      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
 683      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
 684      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
 685      parameter TDQSCK           =     400; // tDQSCK     ps    DQS output access time from CK/CK#
 686      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
 687      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
 688      parameter TDIPW            =     600; // tDIPW      ps    DQ and DM input Pulse Width
 689      parameter TIPW             =     900; // tIPW       ps    Control and Address input Pulse Width
 690      parameter TIS              =     350; // tIS        ps    Input Setup Time
 691      parameter TIH              =     275; // tIH        ps    Input Hold Time
 692      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
 693      parameter TRC              =   52500; // tRC        ps    Active to Active/Auto Refresh command time
 694      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
 695      parameter TRP              =   15000; // tRP        ps    Precharge command period
 696      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
 697      parameter TCKE             =    7500; // tCKE       ps    CKE minimum high or low pulse width
 698      parameter TAON             =     400; // tAON       ps    RTT turn-on from ODTLon reference
 699      parameter TWLS             =     325; // tWLS       ps    Setup time for tDQS flop
 700      parameter TWLH             =     325; // tWLH       ps    Hold time of tDQS flop
 701      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
 702      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
 703      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
 704  `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
 705
 706  `ifdef x16
 707    `ifdef sg094E
 708      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 709      parameter TFAW             =   30000; // tFAW       ps     (2KB page size) Four Bank Activate window
 710    `else `ifdef sg094
 711      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 712      parameter TFAW             =   30000; // tFAW       ps     (2KB page size) Four Bank Activate window
 713    `else `ifdef sg107F
 714      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 715      parameter TFAW             =   35000; // tFAW       ps     (2KB page size) Four Bank Activate window
 716    `else `ifdef sg107E
 717      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 718      parameter TFAW             =   35000; // tFAW       ps     (2KB page size) Four Bank Activate window
 719    `else `ifdef sg107
 720      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 721      parameter TFAW             =   35000; // tFAW       ps     (2KB page size) Four Bank Activate window
 722    `else `ifdef sg125F
 723      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 724      parameter TFAW             =   40000; // tFAW       ps     (2KB page size) Four Bank Activate window
 725    `else `ifdef sg125E
 726      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 727      parameter TFAW             =   40000; // tFAW       ps     (2KB page size) Four Bank Activate window
 728    `else `ifdef sg125
 729      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 730      parameter TFAW             =   40000; // tFAW       ps     (2KB page size) Four Bank Activate window
 731    `else `ifdef sg15E
 732      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 733      parameter TFAW             =   45000; // tFAW       ps     (2KB page size) Four Bank Activate window
 734    `else `ifdef sg15
 735      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 736      parameter TFAW             =   45000; // tFAW       ps     (2KB page size) Four Bank Activate window
 737    `else // sg187E, sg187, sg25, sg25E
 738      parameter TRRD             =   10000; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
 739      parameter TFAW             =   50000; // tFAW       ps     (2KB page size) Four Bank Activate window
 740    `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
 741  `else // x4, x8
 742    `ifdef sg094E
 743      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 744      parameter TFAW             =   25000; // tFAW       ps     (1KB page size) Four Bank Activate window
 745    `else `ifdef sg094
 746      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 747      parameter TFAW             =   25000; // tFAW       ps     (1KB page size) Four Bank Activate window
 748    `else `ifdef sg107F
 749      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 750      parameter TFAW             =   25000; // tFAW       ps     (1KB page size) Four Bank Activate window
 751    `else `ifdef sg107E
 752      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 753      parameter TFAW             =   25000; // tFAW       ps     (1KB page size) Four Bank Activate window
 754    `else `ifdef sg107
 755      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 756      parameter TFAW             =   25000; // tFAW       ps     (1KB page size) Four Bank Activate window
 757    `else `ifdef sg125F
 758      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 759      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
 760    `else `ifdef sg125E
 761      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 762      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
 763    `else `ifdef sg125
 764      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 765      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
 766    `else `ifdef sg15E
 767      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 768      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
 769    `else `ifdef sg15
 770      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 771      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
 772    `else `ifdef sg187E
 773      parameter TRRD             =    7500; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 774      parameter TFAW             =   37500; // tFAW       ps     (1KB page size) Four Bank Activate window
 775    `else `ifdef sg187
 776      parameter TRRD             =    7500; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 777      parameter TFAW             =   37500; // tFAW       ps     (1KB page size) Four Bank Activate window
 778    `else // sg25, sg25E
 779      parameter TRRD             =   10000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
 780      parameter TFAW             =   40000; // tFAW       ps     (1KB page size) Four Bank Activate window
 781    `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
 782`endif
 783
 784      // Timing Parameters
 785
 786      // Mode Register
 787      parameter CL_MIN           =       5; // CL         tCK   Minimum CAS Latency
 788      parameter CL_MAX           =      14; // CL         tCK   Maximum CAS Latency
 789      parameter AL_MIN           =       0; // AL         tCK   Minimum Additive Latency
 790      parameter AL_MAX           =       2; // AL         tCK   Maximum Additive Latency
 791      parameter WR_MIN           =       5; // WR         tCK   Minimum Write Recovery
 792      parameter WR_MAX           =      16; // WR         tCK   Maximum Write Recovery
 793      parameter BL_MIN           =       4; // BL         tCK   Minimum Burst Length
 794      parameter BL_MAX           =       8; // BL         tCK   Minimum Burst Length
 795      parameter CWL_MIN          =       5; // CWL        tCK   Minimum CAS Write Latency
 796      parameter CWL_MAX          =      10; // CWL        tCK   Maximum CAS Write Latency
 797
 798      // Clock
 799      parameter TCK_MAX          =    3300; // tCK        ps    Maximum Clock Cycle Time
 800      parameter TCH_AVG_MIN      =    0.47; // tCH        tCK   Minimum Clock High-Level Pulse Width
 801      parameter TCL_AVG_MIN      =    0.47; // tCL        tCK   Minimum Clock Low-Level Pulse Width
 802      parameter TCH_AVG_MAX      =    0.53; // tCH        tCK   Maximum Clock High-Level Pulse Width
 803      parameter TCL_AVG_MAX      =    0.53; // tCL        tCK   Maximum Clock Low-Level Pulse Width
 804      parameter TCH_ABS_MIN      =    0.43; // tCH        tCK   Minimum Clock High-Level Pulse Width
 805      parameter TCL_ABS_MIN      =    0.43; // tCL        tCK   Maximum Clock Low-Level Pulse Width
 806      parameter TCKE_TCK         =       3; // tCKE       tCK   CKE minimum high or low pulse width
 807      parameter TAA_MAX          =   20000; // TAA        ps    Internal READ command to first data
 808
 809      // Data OUT
 810      parameter TQH              =    0.38; // tQH        ps    DQ output hold time from DQS, DQS#
 811      // Data Strobe OUT
 812      parameter TRPRE            =    0.90; // tRPRE      tCK   DQS Read Preamble
 813      parameter TRPST            =    0.30; // tRPST      tCK   DQS Read Postamble
 814      // Data Strobe IN
 815      parameter TDQSH            =    0.45; // tDQSH      tCK   DQS input High Pulse Width
 816      parameter TDQSL            =    0.45; // tDQSL      tCK   DQS input Low Pulse Width
 817      parameter TWPRE            =    0.90; // tWPRE      tCK   DQS Write Preamble
 818      parameter TWPST            =    0.30; // tWPST      tCK   DQS Write Postamble
 819      // Command and Address
 820      parameter TZQCS            =      64; // tZQCS      tCK   ZQ Cal (Short) time
 821      parameter TZQINIT          =     512; // tZQinit    tCK   ZQ Cal (Long) time
 822      parameter TZQOPER          =     256; // tZQoper    tCK   ZQ Cal (Long) time
 823      parameter TCCD             =       4; // tCCD       tCK   Cas to Cas command delay
 824      parameter TCCD_DG          =       2; // tCCD_DG    tCK   Cas to Cas command delay to different group
 825      parameter TRAS_MAX         =    60e9; // tRAS       ps    Maximum Active to Precharge command time
 826      parameter TWR              =   15000; // tWR        ps    Write recovery time
 827      parameter TMRD             =       4; // tMRD       tCK   Load Mode Register command cycle time
 828      parameter TMOD             =   15000; // tMOD       ps    LOAD MODE to non-LOAD MODE command cycle time
 829      parameter TMOD_TCK         =      12; // tMOD       tCK   LOAD MODE to non-LOAD MODE command cycle time
 830      parameter TRRD_TCK         =       4; // tRRD       tCK   Active bank a to Active bank b command time
 831      parameter TRRD_DG          =    3000; // tRRD_DG    ps     Active bank a to Active bank b command time to different group
 832      parameter TRRD_DG_TCK      =       2; // tRRD_DG    tCK   Active bank a to Active bank b command time to different group
 833      parameter TRTP             =    7500; // tRTP       ps    Read to Precharge command delay
 834      parameter TRTP_TCK         =       4; // tRTP       tCK   Read to Precharge command delay
 835      parameter TWTR             =    7500; // tWTR       ps    Write to Read command delay
 836      parameter TWTR_DG          =    3750; // tWTR_DG    ps    Write to Read command delay to different group
 837      parameter TWTR_TCK         =       4; // tWTR       tCK   Write to Read command delay
 838      parameter TWTR_DG_TCK      =       2; // tWTR_DG    tCK   Write to Read command delay to different group
 839      parameter TDLLK            =     512; // tDLLK      tCK   DLL locking time
 840      // Refresh - 1Gb
 841      parameter TRFC_MIN         =  110000; // tRFC       ps    Refresh to Refresh Command interval minimum value
 842      parameter TRFC_MAX         =70312500; // tRFC       ps    Refresh to Refresh Command Interval maximum value
 843      // Power Down
 844      parameter TXP_TCK          =       3; // tXP        tCK   Exit power down to a valid command
 845      parameter TXPDLL           =   24000; // tXPDLL     ps    Exit precharge power down to READ or WRITE command (DLL-off mode)
 846      parameter TXPDLL_TCK       =      10; // tXPDLL     tCK   Exit precharge power down to READ or WRITE command (DLL-off mode)
 847      parameter TACTPDEN         =       1; // tACTPDEN   tCK   Timing of last ACT command to power down entry
 848      parameter TPRPDEN          =       1; // tPREPDEN   tCK   Timing of last PRE command to power down entry
 849      parameter TREFPDEN         =       1; // tARPDEN    tCK   Timing of last REFRESH command to power down entry
 850      parameter TCPDED           =       1; // tCPDED     tCK   Command pass disable/enable delay
 851      parameter TPD_MAX          =TRFC_MAX; // tPD        ps    Power-down entry-to-exit timing
 852      parameter TXPR             =  120000; // tXPR       ps    Exit Reset from CKE assertion to a valid command
 853      parameter TXPR_TCK         =       5; // tXPR       tCK   Exit Reset from CKE assertion to a valid command
 854      // Self Refresh
 855      parameter TXS              =  120000; // tXS        ps    Exit self refesh to a non-read or write command
 856      parameter TXS_TCK          =       5; // tXS        tCK   Exit self refesh to a non-read or write command
 857      parameter TXSDLL           =   TDLLK; // tXSRD      tCK   Exit self refresh to a read or write command
 858      parameter TISXR            =     TIS; // tISXR      ps    CKE setup time during self refresh exit.
 859      parameter TCKSRE           =   10000; // tCKSRE     ps    Valid Clock requirement after self refresh entry (SRE)
 860      parameter TCKSRE_TCK       =       5; // tCKSRE     tCK   Valid Clock requirement after self refresh entry (SRE)
 861      parameter TCKSRX           =   10000; // tCKSRX     ps    Valid Clock requirement prior to self refresh exit (SRX)
 862      parameter TCKSRX_TCK       =       5; // tCKSRX     tCK   Valid Clock requirement prior to self refresh exit (SRX)
 863      parameter TCKESR_TCK       =       4; // tCKESR     tCK   Minimum CKE low width for Self Refresh entry to exit timing
 864      // ODT
 865      parameter TAOF             =     0.7; // tAOF       tCK   RTT turn-off from ODTLoff reference
 866      parameter TAONPD           =    8500; // tAONPD     ps    Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
 867      parameter TAOFPD           =    8500; // tAONPD     ps    Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
 868      parameter ODTH4            =       4; // ODTH4      tCK   ODT minimum HIGH time after ODT assertion or write (BL4)
 869      parameter ODTH8            =       6; // ODTH8      tCK   ODT minimum HIGH time after write (BL8)
 870      parameter TADC             =     0.7; // tADC       tCK   RTT dynamic change skew
 871      // Write Levelization
 872      parameter TWLMRD           =      40; // tWLMRD     tCK   First DQS pulse rising edge after tDQSS margining mode is programmed
 873      parameter TWLDQSEN         =      25; // tWLDQSEN   tCK   DQS/DQS delay after tDQSS margining mode is programmed
 874      parameter TWLOE            =    2000; // tWLOE      ps    Write levelization output error
 875
 876      // Size Parameters based on Part Width
 877
 878  `ifdef x4
 879      parameter DM_BITS          =       1; // Set this parameter to control how many Data Mask bits are used
 880      parameter ADDR_BITS        =      14; // MAX Address Bits
 881      parameter ROW_BITS         =      14; // Set this parameter to control how many Address bits are used
 882      parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
 883      parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used       **Same as part bit width**
 884      parameter DQS_BITS         =       1; // Set this parameter to control how many Dqs bits are used
 885  `else `ifdef x8
 886      parameter DM_BITS          =       1; // Set this parameter to control how many Data Mask bits are used
 887      parameter ADDR_BITS        =      14; // MAX Address Bits
 888      parameter ROW_BITS         =      14; // Set this parameter to control how many Address bits are used
 889      parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
 890      parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used       **Same as part bit width**
 891      parameter DQS_BITS         =       1; // Set this parameter to control how many Dqs bits are used
 892  `else `define x16
 893      parameter DM_BITS          =       2; // Set this parameter to control how many Data Mask bits are used
 894      parameter ADDR_BITS        =      13; // MAX Address Bits
 895      parameter ROW_BITS         =      13; // Set this parameter to control how many Address bits are used
 896      parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
 897      parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used       **Same as part bit width**
 898      parameter DQS_BITS         =       2; // Set this parameter to control how many Dqs bits are used
 899  `endif `endif
 900
 901      // Size Parameters
 902      parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits are used
 903      parameter MEM_BITS         =      15; // Set this parameter to control how many write data bursts can be stored in memory.  The default is 2^10=1024.
 904      parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
 905      parameter BC               =      12; // the address bit that controls burst chop
 906      parameter BL_BITS          =       3; // the number of bits required to count to BL_MAX
 907      parameter BO_BITS          =       2; // the number of Burst Order Bits
 908
 909  `ifdef QUAD_RANK
 910      `define DUAL_RANK // also define DUAL_RANK
 911      parameter CS_BITS          =       4; // Number of Chip Select Bits
 912      parameter RANKS            =       4; // Number of Chip Selects
 913  `else `ifdef DUAL_RANK
 914      parameter CS_BITS          =       2; // Number of Chip Select Bits
 915      parameter RANKS            =       2; // Number of Chip Selects
 916  `else
 917      parameter CS_BITS          =       2; // Number of Chip Select Bits
 918      parameter RANKS            =       1; // Number of Chip Selects
 919  `endif `endif
 920
 921      // Simulation parameters
 922      parameter RZQ              =     240; // termination resistance
 923      parameter PRE_DEF_PAT      =   8'hAA; // value returned during mpr pre-defined pattern readout
 924      parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
 925      parameter DEBUG            =       0; // Turn on Debug messages
 926      parameter BUS_DELAY        =       0; // delay in nanoseconds
 927      parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
 928      parameter RANDOM_SEED    = 711689044; //seed value for random generator.
 929
 930      parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
 931      parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
 932      parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
 933      parameter RDQS_PST         =       1; // DQS low time after last read strobe
 934      parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
 935      parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
 936      parameter WDQS_PRE         =       2; // DQS half clock periods prior to first write strobe
 937      parameter WDQS_PST         =       1; // DQS half clock periods after last write strobe
 938
 939  // check for legal cas latency based on the cas write latency
 940  function valid_cl;
 941      input [3:0] cl;
 942      input [3:0] cwl;
 943
 944      case ({cwl, cl})
 945  `ifdef sg094E
 946          {4'd5, 4'd5 },
 947          {4'd5, 4'd6 },
 948          {4'd6, 4'd7 },
 949          {4'd6, 4'd8 },
 950          {4'd7, 4'd9 },
 951          {4'd7, 4'd10},
 952          {4'd8, 4'd10},
 953          {4'd8, 4'd11},
 954          {4'd8, 4'd12},
 955          {4'd9, 4'd12},
 956          {4'd9, 4'd13},
 957          {4'd9, 4'd14},
 958          {4'd10, 4'd13},
 959          {4'd10, 4'd14}: valid_cl = 1;
 960  `else `ifdef sg094
 961          {4'd5, 4'd6 },
 962          {4'd6, 4'd7 },
 963          {4'd6, 4'd8 },
 964          {4'd7, 4'd10},
 965          {4'd8, 4'd11},
 966          {4'd8, 4'd12},
 967          {4'd9, 4'd13},
 968          {4'd9, 4'd14},
 969          {4'd10, 4'd14}: valid_cl = 1;
 970  `else `ifdef sg107F
 971          {4'd5, 4'd6 },
 972          {4'd6, 4'd7 },
 973          {4'd6, 4'd8 },
 974          {4'd7, 4'd9 },
 975          {4'd7, 4'd10},
 976          {4'd8, 4'd11},
 977          {4'd8, 4'd12},
 978          {4'd9, 4'd12},
 979          {4'd9, 4'd13},
 980          {4'd9, 4'd14}: valid_cl = 1;
 981  `else `ifdef sg107E
 982          {4'd5, 4'd6 },
 983          {4'd6, 4'd8 },
 984          {4'd7, 4'd10},
 985          {4'd8, 4'd12},
 986          {4'd9, 4'd13},
 987          {4'd9, 4'd14}: valid_cl = 1;
 988  `else `ifdef sg107
 989          {4'd5, 4'd6 },
 990          {4'd6, 4'd8 },
 991          {4'd7, 4'd10},
 992          {4'd8, 4'd12},
 993          {4'd9, 4'd14}: valid_cl = 1;
 994  `else `ifdef sg125F
 995          {4'd5, 4'd5 },
 996          {4'd5, 4'd6 },
 997          {4'd6, 4'd7 },
 998          {4'd6, 4'd8 },
 999          {4'd7, 4'd8 },
1000          {4'd7, 4'd9 },
1001          {4'd7, 4'd10},
1002          {4'd8, 4'd9 },
1003          {4'd8, 4'd10},
1004          {4'd8, 4'd11}: valid_cl = 1;
1005  `else `ifdef sg125E
1006          {4'd5, 4'd5 },
1007          {4'd5, 4'd6 },
1008          {4'd6, 4'd7 },
1009          {4'd6, 4'd8 },
1010          {4'd7, 4'd9 },
1011          {4'd7, 4'd10},
1012          {4'd8, 4'd10},
1013          {4'd8, 4'd11}: valid_cl = 1;
1014  `else `ifdef sg125
1015          {4'd5, 4'd6 },
1016          {4'd6, 4'd7 },
1017          {4'd6, 4'd8 },
1018          {4'd7, 4'd9 },
1019          {4'd7, 4'd10},
1020          {4'd8, 4'd11}: valid_cl = 1;
1021  `else `ifdef sg15E
1022          {4'd5, 4'd6 },
1023          {4'd6, 4'd7 },
1024          {4'd6, 4'd8 },
1025          {4'd7, 4'd9 },
1026          {4'd7, 4'd10}: valid_cl = 1;
1027  `else `ifdef sg15
1028          {4'd5, 4'd6 },
1029          {4'd6, 4'd8 },
1030          {4'd7, 4'd10}: valid_cl = 1;
1031  `else `ifdef sg187E
1032          {4'd5, 4'd6 },
1033          {4'd6, 4'd7 },
1034          {4'd6, 4'd8 }: valid_cl = 1;
1035  `else `ifdef sg187
1036          {4'd5, 4'd6 },
1037          {4'd6, 4'd8 }: valid_cl = 1;
1038  `else `ifdef sg25E
1039          {4'd5, 4'd5 },
1040          {4'd5, 4'd6 }: valid_cl = 1;
1041  `else `ifdef sg25
1042          {4'd5, 4'd6 }: valid_cl = 1;
1043  `endif `endif `endif `endif `endif `endif `endif `endif `endif  `endif `endif `endif `endif `endif
1044          default : valid_cl = 0;
1045      endcase
1046  endfunction
1047
1048  // find the minimum valid cas write latency
1049  function [3:0] min_cwl;
1050      input period;
1051      real period;
1052      min_cwl = (period >= 2500.0) ? 5:
1053                (period >= 1875.0) ? 6:
1054                (period >= 1500.0) ? 7:
1055                (period >= 1250.0) ? 8:
1056                (period >= 15e3/14) ? 9:
1057                10; // (period >= 937.5)
1058  endfunction
1059
1060  // find the minimum valid cas latency
1061  function [3:0] min_cl;
1062      input period;
1063      real period;
1064      reg [3:0] cwl;
1065      reg [3:0] cl;
1066      begin
1067          cwl = min_cwl(period);
1068          for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
1069              if (valid_cl(cl, cwl)) begin
1070                  min_cl = cl;
1071              end
1072          end
1073      end
1074  endfunction
1075
1076`elsif x2Gb // 2Gb parts
1077                                            // SYMBOL     UNITS DESCRIPTION
1078                                            // ------     ----- -----------
1079  `ifdef sg15E                              // sg15E is equivelant to the JEDEC DDR3-1333H (9-9-9) speed bin
1080      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
1081      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
1082      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
1083      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
1084      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
1085      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
1086      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
1087      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
1088      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
1089      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
1090      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
1091      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
1092      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
1093      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
1094      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
1095      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
1096      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1097      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1098      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1099      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1100      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
1101      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
1102      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
1103      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
1104      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
1105      parameter TIS              =     190; // tIS        ps    Input Setup Time
1106      parameter TIH              =     140; // tIH        ps    Input Hold Time
1107      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
1108      parameter TRC              =   49500; // tRC        ps    Active to Active/Auto Refresh command time
1109      parameter TRCD             =   13500; // tRCD       ps    Active to Read/Write command time
1110      parameter TRP              =   13500; // tRP        ps    Precharge command period
1111      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
1112      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
1113      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
1114      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
1115      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
1116      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1117      parameter TAA_MIN          =   13500; // TAA        ps    Internal READ command to first data
1118      parameter CL_TIME          =   13500; // CL         ps    Minimum CAS Latency
1119  `else `ifdef sg15                         // sg15 is equivelant to the JEDEC DDR3-1333J (10-10-10) speed bin
1120      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
1121      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
1122      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
1123      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
1124      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
1125      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
1126      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
1127      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
1128      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
1129      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
1130      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
1131      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
1132      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
1133      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
1134      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
1135      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
1136      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1137      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1138      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1139      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1140      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
1141      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
1142      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
1143      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
1144      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
1145      parameter TIS              =     190; // tIS        ps    Input Setup Time
1146      parameter TIH              =     140; // tIH        ps    Input Hold Time
1147      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
1148      parameter TRC              =   51000; // tRC        ps    Active to Active/Auto Refresh command time
1149      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
1150      parameter TRP              =   15000; // tRP        ps    Precharge command period
1151      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
1152      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
1153      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
1154      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
1155      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
1156      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1157      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
1158      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
1159  `else `ifdef sg187E                       // sg187E is equivelant to the JEDEC DDR3-1066F (7-7-7) speed bin
1160      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
1161      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
1162      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
1163      parameter TERR_2PER        =     132; // tERR(2per) ps    Accumulated Error (2-cycle)
1164      parameter TERR_3PER        =     157; // tERR(3per) ps    Accumulated Error (3-cycle)
1165      parameter TERR_4PER        =     175; // tERR(4per) ps    Accumulated Error (4-cycle)
1166      parameter TERR_5PER        =     188; // tERR(5per) ps    Accumulated Error (5-cycle)
1167      parameter TERR_6PER        =     200; // tERR(6per) ps    Accumulated Error (6-cycle)
1168      parameter TERR_7PER        =     209; // tERR(7per) ps    Accumulated Error (7-cycle)
1169      parameter TERR_8PER        =     217; // tERR(8per) ps    Accumulated Error (8-cycle)
1170      parameter TERR_9PER        =     224; // tERR(9per) ps    Accumulated Error (9-cycle)
1171      parameter TERR_10PER       =     231; // tERR(10per)ps    Accumulated Error (10-cycle)
1172      parameter TERR_11PER       =     237; // tERR(11per)ps    Accumulated Error (11-cycle)
1173      parameter TERR_12PER       =     242; // tERR(12per)ps    Accumulated Error (12-cycle)
1174      parameter TDS              =      25; // tDS        ps    DQ and DM input setup time relative to DQS
1175      parameter TDH              =     100; // tDH        ps    DQ and DM input hold time relative to DQS
1176      parameter TDQSQ            =     150; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1177      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1178      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1179      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1180      parameter TDQSCK           =     300; // tDQSCK     ps    DQS output access time from CK/CK#
1181      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
1182      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
1183      parameter TDIPW            =     490; // tDIPW      ps    DQ and DM input Pulse Width
1184      parameter TIPW             =     780; // tIPW       ps    Control and Address input Pulse Width
1185      parameter TIS              =     125; // tIS        ps    Input Setup Time
1186      parameter TIH              =     200; // tIH        ps    Input Hold Time
1187      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
1188      parameter TRC              =   50625; // tRC        ps    Active to Active/Auto Refresh command time
1189      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
1190      parameter TRP              =   13125; // tRP        ps    Precharge command period
1191      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
1192      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
1193      parameter TAON             =     300; // tAON       ps    RTT turn-on from ODTLon reference
1194      parameter TWLS             =     245; // tWLS       ps    Setup time for tDQS flop
1195      parameter TWLH             =     245; // tWLH       ps    Hold time of tDQS flop
1196      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1197      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
1198      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
1199  `else `ifdef sg187                        // sg187  is equivelant to the JEDEC DDR3-1066G (8-8-8) speed bin
1200      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
1201      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
1202      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
1203      parameter TERR_2PER        =     132; // tERR(2per) ps    Accumulated Error (2-cycle)
1204      parameter TERR_3PER        =     157; // tERR(3per) ps    Accumulated Error (3-cycle)
1205      parameter TERR_4PER        =     175; // tERR(4per) ps    Accumulated Error (4-cycle)
1206      parameter TERR_5PER        =     188; // tERR(5per) ps    Accumulated Error (5-cycle)
1207      parameter TERR_6PER        =     200; // tERR(6per) ps    Accumulated Error (6-cycle)
1208      parameter TERR_7PER        =     209; // tERR(7per) ps    Accumulated Error (7-cycle)
1209      parameter TERR_8PER        =     217; // tERR(8per) ps    Accumulated Error (8-cycle)
1210      parameter TERR_9PER        =     224; // tERR(9per) ps    Accumulated Error (9-cycle)
1211      parameter TERR_10PER       =     231; // tERR(10per)ps    Accumulated Error (10-cycle)
1212      parameter TERR_11PER       =     237; // tERR(11per)ps    Accumulated Error (11-cycle)
1213      parameter TERR_12PER       =     242; // tERR(12per)ps    Accumulated Error (12-cycle)
1214      parameter TDS              =      25; // tDS        ps    DQ and DM input setup time relative to DQS
1215      parameter TDH              =     100; // tDH        ps    DQ and DM input hold time relative to DQS
1216      parameter TDQSQ            =     150; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1217      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1218      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1219      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1220      parameter TDQSCK           =     300; // tDQSCK     ps    DQS output access time from CK/CK#
1221      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
1222      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
1223      parameter TDIPW            =     490; // tDIPW      ps    DQ and DM input Pulse Width
1224      parameter TIPW             =     780; // tIPW       ps    Control and Address input Pulse Width
1225      parameter TIS              =     125; // tIS        ps    Input Setup Time
1226      parameter TIH              =     200; // tIH        ps    Input Hold Time
1227      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
1228      parameter TRC              =   52500; // tRC        ps    Active to Active/Auto Refresh command time
1229      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
1230      parameter TRP              =   15000; // tRP        ps    Precharge command period
1231      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
1232      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
1233      parameter TAON             =     300; // tAON       ps    RTT turn-on from ODTLon reference
1234      parameter TWLS             =     245; // tWLS       ps    Setup time for tDQS flop
1235      parameter TWLH             =     245; // tWLH       ps    Hold time of tDQS flop
1236      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1237      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
1238      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
1239  `else `ifdef sg25E                        // sg25E is equivelant to the JEDEC DDR3-800D (5-5-5) speed bin
1240      parameter TCK_MIN          =    2500; // tCK        ps    Minimum Clock Cycle Time
1241      parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter
1242      parameter TJIT_CC          =     200; // tJIT(cc)   ps    Cycle to Cycle jitter
1243      parameter TERR_2PER        =     147; // tERR(2per) ps    Accumulated Error (2-cycle)
1244      parameter TERR_3PER        =     175; // tERR(3per) ps    Accumulated Error (3-cycle)
1245      parameter TERR_4PER        =     194; // tERR(4per) ps    Accumulated Error (4-cycle)
1246      parameter TERR_5PER        =     209; // tERR(5per) ps    Accumulated Error (5-cycle)
1247      parameter TERR_6PER        =     222; // tERR(6per) ps    Accumulated Error (6-cycle)
1248      parameter TERR_7PER        =     232; // tERR(7per) ps    Accumulated Error (7-cycle)
1249      parameter TERR_8PER        =     241; // tERR(8per) ps    Accumulated Error (8-cycle)
1250      parameter TERR_9PER        =     249; // tERR(9per) ps    Accumulated Error (9-cycle)
1251      parameter TERR_10PER       =     257; // tERR(10per)ps    Accumulated Error (10-cycle)
1252      parameter TERR_11PER       =     263; // tERR(11per)ps    Accumulated Error (11-cycle)
1253      parameter TERR_12PER       =     269; // tERR(12per)ps    Accumulated Error (12-cycle)
1254      parameter TDS              =      75; // tDS        ps    DQ and DM input setup time relative to DQS
1255      parameter TDH              =     150; // tDH        ps    DQ and DM input hold time relative to DQS
1256      parameter TDQSQ            =     200; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1257      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1258      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1259      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1260      parameter TDQSCK           =     400; // tDQSCK     ps    DQS output access time from CK/CK#
1261      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
1262      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
1263      parameter TDIPW            =     600; // tDIPW      ps    DQ and DM input Pulse Width
1264      parameter TIPW             =     900; // tIPW       ps    Control and Address input Pulse Width
1265      parameter TIS              =     200; // tIS        ps    Input Setup Time
1266      parameter TIH              =     275; // tIH        ps    Input Hold Time
1267      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
1268      parameter TRC              =   50000; // tRC        ps    Active to Active/Auto Refresh command time
1269      parameter TRCD             =   12500; // tRCD       ps    Active to Read/Write command time
1270      parameter TRP              =   12500; // tRP        ps    Precharge command period
1271      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
1272      parameter TCKE             =    7500; // tCKE       ps    CKE minimum high or low pulse width
1273      parameter TAON             =     400; // tAON       ps    RTT turn-on from ODTLon reference
1274      parameter TWLS             =     325; // tWLS       ps    Setup time for tDQS flop
1275      parameter TWLH             =     325; // tWLH       ps    Hold time of tDQS flop
1276      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1277      parameter TAA_MIN          =   12500; // TAA        ps    Internal READ command to first data
1278      parameter CL_TIME          =   12500; // CL         ps    Minimum CAS Latency
1279  `else `define sg25                        // sg25 is equivelant to the JEDEC DDR3-800E (6-6-6) speed bin
1280      parameter TCK_MIN          =    2500; // tCK        ps    Minimum Clock Cycle Time
1281      parameter TJIT_PER         =     100; // tJIT(per)  ps    Period JItter
1282      parameter TJIT_CC          =     200; // tJIT(cc)   ps    Cycle to Cycle jitter
1283      parameter TERR_2PER        =     147; // tERR(2per) ps    Accumulated Error (2-cycle)
1284      parameter TERR_3PER        =     175; // tERR(3per) ps    Accumulated Error (3-cycle)
1285      parameter TERR_4PER        =     194; // tERR(4per) ps    Accumulated Error (4-cycle)
1286      parameter TERR_5PER        =     209; // tERR(5per) ps    Accumulated Error (5-cycle)
1287      parameter TERR_6PER        =     222; // tERR(6per) ps    Accumulated Error (6-cycle)
1288      parameter TERR_7PER        =     232; // tERR(7per) ps    Accumulated Error (7-cycle)
1289      parameter TERR_8PER        =     241; // tERR(8per) ps    Accumulated Error (8-cycle)
1290      parameter TERR_9PER        =     249; // tERR(9per) ps    Accumulated Error (9-cycle)
1291      parameter TERR_10PER       =     257; // tERR(10per)ps    Accumulated Error (10-cycle)
1292      parameter TERR_11PER       =     263; // tERR(11per)ps    Accumulated Error (11-cycle)
1293      parameter TERR_12PER       =     269; // tERR(12per)ps    Accumulated Error (12-cycle)
1294      parameter TDS              =      75; // tDS        ps    DQ and DM input setup time relative to DQS
1295      parameter TDH              =     150; // tDH        ps    DQ and DM input hold time relative to DQS
1296      parameter TDQSQ            =     200; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
1297      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
1298      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
1299      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
1300      parameter TDQSCK           =     400; // tDQSCK     ps    DQS output access time from CK/CK#
1301      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
1302      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
1303      parameter TDIPW            =     600; // tDIPW      ps    DQ and DM input Pulse Width
1304      parameter TIPW             =     900; // tIPW       ps    Control and Address input Pulse Width
1305      parameter TIS              =     200; // tIS        ps    Input Setup Time
1306      parameter TIH              =     275; // tIH        ps    Input Hold Time
1307      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
1308      parameter TRC              =   52500; // tRC        ps    Active to Active/Auto Refresh command time
1309      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
1310      parameter TRP              =   15000; // tRP        ps    Precharge command period
1311      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
1312      parameter TCKE             =    7500; // tCKE       ps    CKE minimum high or low pulse width
1313      parameter TAON             =     400; // tAON       ps    RTT turn-on from ODTLon reference
1314      parameter TWLS             =     325; // tWLS       ps    Setup time for tDQS flop
1315      parameter TWLH             =     325; // tWLH       ps    Hold time of tDQS flop
1316      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
1317      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
1318      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
1319  `endif `endif `endif `endif `endif
1320
1321  `ifdef x16
1322    `ifdef sg15E
1323      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
1324      parameter TFAW             =   45000; // tFAW       ps     (2KB page size) Four Bank Activate window
1325    `else `ifdef sg15
1326      parameter TRRD             =    7500; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
1327      parameter TFAW             =   45000; // tFAW       ps     (2KB page size) Four Bank Activate window
1328    `else // sg187E, sg187, sg25, sg25E
1329      parameter TRRD             =   10000; // tRRD       ps     (2KB page size) Active bank a to Active bank b command time
1330      parameter TFAW             =   50000; // tFAW       ps     (2KB page size) Four Bank Activate window
1331    `endif `endif
1332  `else // x4, x8
1333    `ifdef sg15E
1334      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
1335      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
1336    `else `ifdef sg15
1337      parameter TRRD             =    6000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
1338      parameter TFAW             =   30000; // tFAW       ps     (1KB page size) Four Bank Activate window
1339    `else `ifdef sg187E
1340      parameter TRRD             =    7500; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
1341      parameter TFAW             =   37500; // tFAW       ps     (1KB page size) Four Bank Activate window
1342    `else `ifdef sg187
1343      parameter TRRD             =    7500; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
1344      parameter TFAW             =   37500; // tFAW       ps     (1KB page size) Four Bank Activate window
1345    `else // sg25, sg25E
1346      parameter TRRD             =   10000; // tRRD       ps     (1KB page size) Active bank a to Active bank b command time
1347      parameter TFAW             =   40000; // tFAW       ps     (1KB page size) Four Bank Activate window
1348    `endif `endif `endif `endif
1349  `endif
1350
1351      // Timing Parameters
1352
1353      // Mode Register
1354      parameter CL_MIN           =       5; // CL         tCK   Minimum CAS Latency
1355      parameter CL_MAX           =      11; // CL         tCK   Maximum CAS Latency
1356      parameter AL_MIN           =       0; // AL         tCK   Minimum Additive Latency
1357      parameter AL_MAX           =       2; // AL         tCK   Maximum Additive Latency
1358      parameter WR_MIN           =       5; // WR         tCK   Minimum Write Recovery
1359      parameter WR_MAX           =      12; // WR         tCK   Maximum Write Recovery
1360      parameter BL_MIN           =       4; // BL         tCK   Minimum Burst Length
1361      parameter BL_MAX           =       8; // BL         tCK   Minimum Burst Length
1362      parameter CWL_MIN          =       5; // CWL        tCK   Minimum CAS Write Latency
1363      parameter CWL_MAX          =       8; // CWL        tCK   Maximum CAS Write Latency
1364
1365      // Clock
1366      parameter TCK_MAX          =    3300; // tCK        ps    Maximum Clock Cycle Time
1367      parameter TCH_AVG_MIN      =    0.47; // tCH        tCK   Minimum Clock High-Level Pulse Width
1368      parameter TCL_AVG_MIN      =    0.47; // tCL        tCK   Minimum Clock Low-Level Pulse Width
1369      parameter TCH_AVG_MAX      =    0.53; // tCH        tCK   Maximum Clock High-Level Pulse Width
1370      parameter TCL_AVG_MAX      =    0.53; // tCL        tCK   Maximum Clock Low-Level Pulse Width
1371      parameter TCH_ABS_MIN      =    0.43; // tCH        tCK   Minimum Clock High-Level Pulse Width
1372      parameter TCL_ABS_MIN      =    0.43; // tCL        tCK   Maximum Clock Low-Level Pulse Width
1373      parameter TCKE_TCK         =       3; // tCKE       tCK   CKE minimum high or low pulse width
1374      parameter TAA_MAX          =   20000; // TAA        ps    Internal READ command to first data
1375
1376      // Data OUT
1377      parameter TQH              =    0.38; // tQH        ps    DQ output hold time from DQS, DQS#
1378      // Data Strobe OUT
1379      parameter TRPRE            =    0.90; // tRPRE      tCK   DQS Read Preamble
1380      parameter TRPST            =    0.30; // tRPST      tCK   DQS Read Postamble
1381      // Data Strobe IN
1382      parameter TDQSH            =    0.45; // tDQSH      tCK   DQS input High Pulse Width
1383      parameter TDQSL            =    0.45; // tDQSL      tCK   DQS input Low Pulse Width
1384      parameter TWPRE            =    0.90; // tWPRE      tCK   DQS Write Preamble
1385      parameter TWPST            =    0.30; // tWPST      tCK   DQS Write Postamble
1386      // Command and Address
1387      parameter TZQCS            =      64; // tZQCS      tCK   ZQ Cal (Short) time
1388      parameter TZQINIT          =     512; // tZQinit    tCK   ZQ Cal (Long) time
1389      parameter TZQOPER          =     256; // tZQoper    tCK   ZQ Cal (Long) time
1390      parameter TCCD             =       4; // tCCD       tCK   Cas to Cas command delay
1391      parameter TCCD_DG          =       2; // tCCD_DG    tCK   Cas to Cas command delay to different group
1392      parameter TRAS_MAX         =70312500; // tRAS       ps    Maximum Active to Precharge command time
1393      parameter TWR              =   15000; // tWR        ps    Write recovery time
1394      parameter TMRD             =       4; // tMRD       tCK   Load Mode Register command cycle time
1395      parameter TMOD             =   15000; // tMOD       ps    LOAD MODE to non-LOAD MODE command cycle time
1396      parameter TMOD_TCK         =      12; // tMOD       tCK   LOAD MODE to non-LOAD MODE command cycle time
1397      parameter TRRD_TCK         =       4; // tRRD       tCK   Active bank a to Active bank b command time
1398      parameter TRRD_DG          =    3000; // tRRD_DG    ps     Active bank a to Active bank b command time to different group
1399      parameter TRRD_DG_TCK      =       2; // tRRD_DG    tCK   Active bank a to Active bank b command time to different group
1400      parameter TRTP             =    7500; // tRTP       ps    Read to Precharge command delay
1401      parameter TRTP_TCK         =       4; // tRTP       tCK   Read to Precharge command delay
1402      parameter TWTR             =    7500; // tWTR       ps    Write to Read command delay
1403      parameter TWTR_DG          =    3750; // tWTR_DG    ps    Write to Read command delay to different group
1404      parameter TWTR_TCK         =       4; // tWTR       tCK   Write to Read command delay
1405      parameter TWTR_DG_TCK      =       2; // tWTR_DG    tCK   Write to Read command delay to different group
1406      parameter TDLLK            =     512; // tDLLK      tCK   DLL locking time
1407      // Refresh - 2Gb
1408      parameter TRFC_MIN         =  160000; // tRFC       ps    Refresh to Refresh Command interval minimum value
1409      parameter TRFC_MAX         =70312500; // tRFC       ps    Refresh to Refresh Command Interval maximum value
1410      // Power Down
1411      parameter TXP_TCK          =       3; // tXP        tCK   Exit power down to a valid command
1412      parameter TXPDLL           =   24000; // tXPDLL     ps    Exit precharge power down to READ or WRITE command (DLL-off mode)
1413      parameter TXPDLL_TCK       =      10; // tXPDLL     tCK   Exit precharge power down to READ or WRITE command (DLL-off mode)
1414      parameter TACTPDEN         =       1; // tACTPDEN   tCK   Timing of last ACT command to power down entry
1415      parameter TPRPDEN          =       1; // tPREPDEN   tCK   Timing of last PRE command to power down entry
1416      parameter TREFPDEN         =       1; // tARPDEN    tCK   Timing of last REFRESH command to power down entry
1417      parameter TCPDED           =       1; // tCPDED     tCK   Command pass disable/enable delay
1418      parameter TPD_MAX          =TRFC_MAX; // tPD        ps    Power-down entry-to-exit timing
1419      parameter TXPR             =  170000; // tXPR       ps    Exit Reset from CKE assertion to a valid command
1420      parameter TXPR_TCK         =       5; // tXPR       tCK   Exit Reset from CKE assertion to a valid command
1421      // Self Refresh
1422      parameter TXS              =  170000; // tXS        ps    Exit self refesh to a non-read or write command
1423      parameter TXS_TCK          =       5; // tXS        tCK   Exit self refesh to a non-read or write command
1424      parameter TXSDLL           =   TDLLK; // tXSRD      tCK   Exit self refresh to a read or write command
1425      parameter TISXR            =     TIS; // tISXR      ps    CKE setup time during self refresh exit.
1426      parameter TCKSRE           =   10000; // tCKSRE     ps    Valid Clock requirement after self refresh entry (SRE)
1427      parameter TCKSRE_TCK       =       5; // tCKSRE     tCK   Valid Clock requirement after self refresh entry (SRE)
1428      parameter TCKSRX           =   10000; // tCKSRX     ps    Valid Clock requirement prior to self refresh exit (SRX)
1429      parameter TCKSRX_TCK       =       5; // tCKSRX     tCK   Valid Clock requirement prior to self refresh exit (SRX)
1430      parameter TCKESR_TCK       =       4; // tCKESR     tCK   Minimum CKE low width for Self Refresh entry to exit timing
1431      // ODT
1432      parameter TAOF             =     0.7; // tAOF       tCK   RTT turn-off from ODTLoff reference
1433      parameter TAONPD           =    9000; // tAONPD     ps    Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
1434      parameter TAOFPD           =    9000; // tAONPD     ps    Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
1435      parameter ODTH4            =       4; // ODTH4      tCK   ODT minimum HIGH time after ODT assertion or write (BL4)
1436      parameter ODTH8            =       6; // ODTH8      tCK   ODT minimum HIGH time after write (BL8)
1437      parameter TADC             =     0.7; // tADC       tCK   RTT dynamic change skew
1438      // Write Levelization
1439      parameter TWLMRD           =      40; // tWLMRD     tCK   First DQS pulse rising edge after tDQSS margining mode is programmed
1440      parameter TWLDQSEN         =      25; // tWLDQSEN   tCK   DQS/DQS delay after tDQSS margining mode is programmed
1441      parameter TWLOE            =    2000; // tWLOE      ps    Write levelization output error
1442
1443      // Size Parameters based on Part Width
1444
1445  `ifdef x4
1446      parameter DM_BITS          =       1; // Set this parameter to control how many Data Mask bits are used
1447      parameter ADDR_BITS        =      15; // MAX Address Bits
1448      parameter ROW_BITS         =      15; // Set this parameter to control how many Address bits are used
1449      parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
1450      parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used       **Same as part bit width**
1451      parameter DQS_BITS         =       1; // Set this parameter to control how many Dqs bits are used
1452  `else `ifdef x8
1453      parameter DM_BITS          =       1; // Set this parameter to control how many Data Mask bits are used
1454      parameter ADDR_BITS        =      15; // MAX Address Bits
1455      parameter ROW_BITS         =      15; // Set this parameter to control how many Address bits are used
1456      parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
1457      parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used       **Same as part bit width**
1458      parameter DQS_BITS         =       1; // Set this parameter to control how many Dqs bits are used
1459  `else `define x16
1460      parameter DM_BITS          =       2; // Set this parameter to control how many Data Mask bits are used
1461      parameter ADDR_BITS        =      14; // MAX Address Bits
1462      parameter ROW_BITS         =      14; // Set this parameter to control how many Address bits are used
1463      parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
1464      parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used       **Same as part bit width**
1465      parameter DQS_BITS         =       2; // Set this parameter to control how many Dqs bits are used
1466  `endif `endif
1467
1468      // Size Parameters
1469      parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits are used
1470      parameter MEM_BITS         =      15; // Set this parameter to control how many write data bursts can be stored in memory.  The default is 2^10=1024.
1471      parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
1472      parameter BC               =      12; // the address bit that controls burst chop
1473      parameter BL_BITS          =       3; // the number of bits required to count to BL_MAX
1474      parameter BO_BITS          =       2; // the number of Burst Order Bits
1475
1476  `ifdef QUAD_RANK
1477      `define DUAL_RANK // also define DUAL_RANK
1478      parameter CS_BITS          =       4; // Number of Chip Select Bits
1479      parameter RANKS            =       4; // Number of Chip Selects
1480  `else `ifdef DUAL_RANK
1481      parameter CS_BITS          =       2; // Number of Chip Select Bits
1482      parameter RANKS            =       2; // Number of Chip Selects
1483  `else
1484      parameter CS_BITS          =       2; // Number of Chip Select Bits
1485      parameter RANKS            =       1; // Number of Chip Selects
1486  `endif `endif
1487
1488      // Simulation parameters
1489      parameter RZQ              =     240; // termination resistance
1490      parameter PRE_DEF_PAT      =   8'hAA; // value returned during mpr pre-defined pattern readout
1491      parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
1492      parameter DEBUG            =       0; // Turn on Debug messages
1493      parameter BUS_DELAY        =       0; // delay in nanoseconds
1494      parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
1495      parameter RANDOM_SEED    = 711689044; //seed value for random generator.
1496
1497      parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
1498      parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
1499      parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
1500      parameter RDQS_PST         =       1; // DQS low time after last read strobe
1501      parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
1502      parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
1503      parameter WDQS_PRE         =       2; // DQS half clock periods prior to first write strobe
1504      parameter WDQS_PST         =       1; // DQS half clock periods after last write strobe
1505
1506  // check for legal cas latency based on the cas write latency
1507  function valid_cl;
1508      input [3:0] cl;
1509      input [3:0] cwl;
1510
1511      case ({cwl, cl})
1512  `ifdef sg15E
1513          {4'd5, 4'd6 },
1514          {4'd6, 4'd8 },
1515          {4'd7, 4'd9 },
1516          {4'd7, 4'd10}: valid_cl = 1;
1517  `else `ifdef sg15
1518          {4'd5, 4'd6 },
1519          {4'd6, 4'd8 },
1520          {4'd7, 4'd10}: valid_cl = 1;
1521  `else `ifdef sg187E
1522          {4'd5, 4'd6 },
1523          {4'd6, 4'd7 },
1524          {4'd6, 4'd8 }: valid_cl = 1;
1525  `else `ifdef sg187
1526          {4'd5, 4'd6 },
1527          {4'd6, 4'd8 }: valid_cl = 1;
1528  `else `ifdef sg25E
1529          {4'd5, 4'd5 },
1530          {4'd5, 4'd6 }: valid_cl = 1;
1531  `else `ifdef sg25
1532          {4'd5, 4'd6 }: valid_cl = 1;
1533  `endif `endif `endif `endif `endif `endif
1534          default : valid_cl = 0;
1535      endcase
1536  endfunction
1537
1538  // find the minimum valid cas write latency
1539  function [3:0] min_cwl;
1540      input period;
1541      real period;
1542      min_cwl = (period >= 2500.0) ? 5:
1543                (period >= 1875.0) ? 6:
1544                (period >= 1500.0) ? 7:
1545                8; //(period >= 1250.0)
1546  endfunction
1547
1548  // find the minimum valid cas latency
1549  function [3:0] min_cl;
1550      input period;
1551      real period;
1552      reg [3:0] cwl;
1553      reg [3:0] cl;
1554      begin
1555          cwl = min_cwl(period);
1556          for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
1557              if (valid_cl(cl, cwl)) begin
1558                  min_cl = cl;
1559              end
1560          end
1561      end
1562  endfunction
1563
1564`endif
1565    parameter check_strict_mrbits = 1;
1566    parameter check_strict_timing = 1;
1567    parameter feature_pasr = 1;
1568    parameter feature_truebl4 = 0;
1569   
1570    // text macros
1571    `define DQ_PER_DQS DQ_BITS/DQS_BITS
1572    `define BANKS      (1<<BA_BITS)
1573    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
1574    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
1575    `define MEM_SIZE   (1<<MEM_BITS)
1576    `define MAX_PIPE   4*CL_MAX
1577
1578    // Declare Ports
1579    input   rst_n;
1580    input   ck;
1581    input   ck_n;
1582    input   cke;
1583    input   cs_n;
1584    input   ras_n;
1585    input   cas_n;
1586    input   we_n;
1587    inout   [DM_BITS-1:0]   dm_tdqs;
1588    input   [BA_BITS-1:0]   ba;
1589    input   [ADDR_BITS-1:0] addr;
1590    inout   [DQ_BITS-1:0]   dq;
1591    inout   [DQS_BITS-1:0]  dqs;
1592    inout   [DQS_BITS-1:0]  dqs_n;
1593    output  [DQS_BITS-1:0]  tdqs_n;
1594    input   odt;
1595
1596    // clock jitter
1597    real    tck_avg;
1598    time    tck_sample [TDLLK-1:0];
1599    time    tch_sample [TDLLK-1:0];
1600    time    tcl_sample [TDLLK-1:0];
1601    time    tck_i;
1602    time    tch_i;
1603    time    tcl_i;
1604    real    tch_avg;
1605    real    tcl_avg;
1606    time    tm_ck_pos;
1607    time    tm_ck_neg;
1608    real    tjit_per_rtime;
1609    integer tjit_cc_time;
1610    real    terr_nper_rtime;
1611    //DDR3 clock jitter variables
1612    real    tjit_ch_rtime;
1613    real    duty_cycle;
1614
1615    // clock skew
1616    real    out_delay;
1617    integer dqsck [DQS_BITS-1:0];
1618    integer dqsck_min;
1619    integer dqsck_max;
1620    integer dqsq_min;
1621    integer dqsq_max;
1622    integer seed;
1623
1624    // Mode Registers
1625    reg     [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
1626    reg     burst_order;
1627    reg     [BL_BITS:0] burst_length;
1628    reg     blotf;
1629    reg     truebl4;
1630    integer cas_latency;
1631    reg     dll_reset;
1632    reg     dll_locked;
1633    integer write_recovery;
1634    reg     low_power;
1635    reg     dll_en;
1636    reg     [2:0] odt_rtt_nom;
1637    reg     [1:0] odt_rtt_wr;
1638    reg     odt_en;
1639    reg     dyn_odt_en;
1640    reg     [1:0] al;
1641    integer additive_latency;
1642    reg     write_levelization;
1643    reg     duty_cycle_corrector;
1644    reg     tdqs_en;
1645    reg     out_en;
1646    reg     [2:0] pasr;
1647    integer cas_write_latency;
1648    reg     asr; // auto self refresh
1649    reg     srt; // self refresh temperature range
1650    reg     [1:0] mpr_select;
1651    reg     mpr_en;
1652    reg     odts_readout;
1653    integer read_latency;
1654    integer write_latency;
1655
1656    // cmd encoding
1657    parameter     // {cs, ras, cas, we}
1658        LOAD_MODE = 4'b0000,
1659        REFRESH   = 4'b0001,
1660        PRECHARGE = 4'b0010,
1661        ACTIVATE  = 4'b0011,
1662        WRITE     = 4'b0100,
1663        READ      = 4'b0101,
1664        ZQ        = 4'b0110,
1665        NOP       = 4'b0111,
1666        // DESEL  = 4'b1xxx,
1667        PWR_DOWN  = 4'b1000,
1668        SELF_REF  = 4'b1001
1669    ;
1670
1671    reg [8*9-1:0] cmd_string [9:0];
1672    initial begin
1673        cmd_string[LOAD_MODE] = "Load Mode";
1674        cmd_string[REFRESH  ] = "Refresh  ";
1675        cmd_string[PRECHARGE] = "Precharge";
1676        cmd_string[ACTIVATE ] = "Activate ";
1677        cmd_string[WRITE    ] = "Write    ";
1678        cmd_string[READ     ] = "Read     ";
1679        cmd_string[ZQ       ] = "ZQ       ";
1680        cmd_string[NOP      ] = "No Op    ";
1681        cmd_string[PWR_DOWN ] = "Pwr Down ";
1682        cmd_string[SELF_REF ] = "Self Ref ";
1683    end
1684
1685    // command state
1686    reg     [`BANKS-1:0] active_bank;
1687    reg     [`BANKS-1:0] auto_precharge_bank;
1688    reg     [`BANKS-1:0] write_precharge_bank;
1689    reg     [`BANKS-1:0] read_precharge_bank;
1690    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];
1691    reg     in_power_down;
1692    reg     in_self_refresh;
1693    reg     [3:0] init_mode_reg;
1694    reg     init_dll_reset;
1695    reg     init_done;
1696    integer init_step;
1697    reg     zq_set;
1698    reg     er_trfc_max;
1699    reg     odt_state;
1700    reg     odt_state_dly;
1701    reg     dyn_odt_state;
1702    reg     dyn_odt_state_dly;
1703    reg     prev_odt;
1704    wire    [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
1705    wire    [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
1706    reg     [1:0] mr_chk;
1707    reg     rd_bc;
1708    integer banki;
1709
1710
1711
1712    // cmd timers/counters
1713    integer ref_cntr;
1714    integer odt_cntr;
1715    integer ck_cntr;
1716    integer ck_txpr;
1717    integer ck_load_mode;
1718    integer ck_refresh;
1719    integer ck_precharge;
1720    integer ck_activate;
1721    integer ck_write;
1722    integer ck_read;
1723    integer ck_zqinit;
1724    integer ck_zqoper;
1725    integer ck_zqcs;
1726    integer ck_power_down;
1727    integer ck_slow_exit_pd;
1728    integer ck_self_refresh;
1729    integer ck_freq_change;
1730    integer ck_odt;
1731    integer ck_odth8;
1732    integer ck_dll_reset;
1733    integer ck_cke_cmd;
1734    integer ck_bank_write     [`BANKS-1:0];
1735    integer ck_bank_read      [`BANKS-1:0];
1736    integer ck_group_activate [1:0];
1737    integer ck_group_write    [1:0];
1738    integer ck_group_read     [1:0];
1739    time    tm_txpr;
1740    time    tm_load_mode;
1741    time    tm_refresh;
1742    time    tm_precharge;
1743    time    tm_activate;
1744    time    tm_write_end;
1745    time    tm_power_down;
1746    time    tm_slow_exit_pd;
1747    time    tm_self_refresh;
1748    time    tm_freq_change;
1749    time    tm_cke_cmd;
1750    time    tm_ttsinit;
1751    time    tm_bank_precharge [`BANKS-1:0];
1752    time    tm_bank_activate  [`BANKS-1:0];
1753    time    tm_bank_write_end [`BANKS-1:0];
1754    time    tm_bank_read_end  [`BANKS-1:0];
1755    time    tm_group_activate  [1:0];
1756    time    tm_group_write_end [1:0];
1757
1758    // pipelines
1759    reg     [`MAX_PIPE:0]  al_pipeline;
1760    reg     [`MAX_PIPE:0]  wr_pipeline;
1761    reg     [`MAX_PIPE:0]  rd_pipeline;
1762    reg     [`MAX_PIPE:0]  odt_pipeline;
1763    reg     [`MAX_PIPE:0]  dyn_odt_pipeline;
1764    reg     [BL_BITS:0]    bl_pipeline  [`MAX_PIPE:0];
1765    reg     [BA_BITS-1:0]  ba_pipeline  [`MAX_PIPE:0];
1766    reg     [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
1767    reg     [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
1768    reg     prev_cke;
1769
1770    // data state
1771    reg     [BL_MAX*DQ_BITS-1:0] memory_data;
1772    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;
1773    reg     [BL_BITS-1:0]        burst_position;
1774    reg     [BL_BITS:0]          burst_cntr;
1775    reg     [DQ_BITS-1:0]        dq_temp;
1776    reg     [31:0] check_write_postamble;
1777    reg     [31:0] check_write_preamble;
1778    reg     [31:0] check_write_dqs_high;
1779    reg     [31:0] check_write_dqs_low;
1780    reg     [15:0] check_dm_tdipw;
1781    reg     [63:0] check_dq_tdipw;
1782
1783    // data timers/counters
1784    time    tm_rst_n;
1785    time    tm_cke;
1786    time    tm_odt;
1787    time    tm_tdqss;
1788    time    tm_dm       [15:0];
1789    time    tm_dqs      [15:0];
1790    time    tm_dqs_pos  [31:0];
1791    time    tm_dqss_pos [31:0];
1792    time    tm_dqs_neg  [31:0];
1793    time    tm_dq       [63:0];
1794    time    tm_cmd_addr [22:0];
1795    reg [8*7-1:0] cmd_addr_string [22:0];
1796    initial begin
1797        cmd_addr_string[ 0] = "CS_N   ";
1798        cmd_addr_string[ 1] = "RAS_N  ";
1799        cmd_addr_string[ 2] = "CAS_N  ";
1800        cmd_addr_string[ 3] = "WE_N   ";
1801        cmd_addr_string[ 4] = "BA 0   ";
1802        cmd_addr_string[ 5] = "BA 1   ";
1803        cmd_addr_string[ 6] = "BA 2   ";
1804        cmd_addr_string[ 7] = "ADDR  0";
1805        cmd_addr_string[ 8] = "ADDR  1";
1806        cmd_addr_string[ 9] = "ADDR  2";
1807        cmd_addr_string[10] = "ADDR  3";
1808        cmd_addr_string[11] = "ADDR  4";
1809        cmd_addr_string[12] = "ADDR  5";
1810        cmd_addr_string[13] = "ADDR  6";
1811        cmd_addr_string[14] = "ADDR  7";
1812        cmd_addr_string[15] = "ADDR  8";
1813        cmd_addr_string[16] = "ADDR  9";
1814        cmd_addr_string[17] = "ADDR 10";
1815        cmd_addr_string[18] = "ADDR 11";
1816        cmd_addr_string[19] = "ADDR 12";
1817        cmd_addr_string[20] = "ADDR 13";
1818        cmd_addr_string[21] = "ADDR 14";
1819        cmd_addr_string[22] = "ADDR 15";
1820    end
1821
1822    reg [8*5-1:0] dqs_string [1:0];
1823    initial begin
1824        dqs_string[0] = "DQS  ";
1825        dqs_string[1] = "DQS_N";
1826    end
1827
1828    // Memory Storage
1829`ifdef MAX_MEM
1830    parameter RFF_BITS = DQ_BITS*BL_MAX;
1831     // %z format uses 8 bytes for every 32 bits or less.
1832    parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
1833    reg [1024:1] tmp_model_dir;
1834    integer memfd[`BANKS-1:0];
1835
1836    initial
1837    begin : file_io_open
1838        integer bank;
1839
1840        if (!$value$plusargs("model_data+%s", tmp_model_dir))
1841        begin
1842            tmp_model_dir = "/tmp";
1843            $display(
1844                "%m: at time %t WARNING: no +model_data option specified, using /tmp.",
1845                $time
1846            );
1847        end
1848
1849        for (bank = 0; bank < `BANKS; bank = bank + 1)
1850            memfd[bank] = open_bank_file(bank);
1851    end
1852`else
1853    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];
1854    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];
1855    reg     [MEM_BITS:0]         memory_index;
1856    reg     [MEM_BITS:0]         memory_used = 0;
1857`endif
1858
1859    // receive
1860    reg            rst_n_in;
1861    reg            ck_in;
1862    reg            ck_n_in;
1863    reg            cke_in;
1864    reg            cs_n_in;
1865    reg            ras_n_in;
1866    reg            cas_n_in;
1867    reg            we_n_in;
1868    reg     [15:0] dm_in;
1869    reg     [2:0]  ba_in;
1870    reg     [15:0] addr_in;
1871    reg     [63:0] dq_in;
1872    reg     [31:0] dqs_in;
1873    reg            odt_in;
1874
1875    reg     [15:0] dm_in_pos;
1876    reg     [15:0] dm_in_neg;
1877    reg     [63:0] dq_in_pos;
1878    reg     [63:0] dq_in_neg;
1879    reg            dq_in_valid;
1880    reg            dqs_in_valid;
1881    integer        wdqs_cntr;
1882    integer        wdq_cntr;
1883    integer        wdqs_pos_cntr [31:0];
1884    reg            b2b_write;
1885    reg [BL_BITS:0] wr_burst_length;
1886    reg     [31:0] prev_dqs_in;
1887    reg            diff_ck;
1888
1889    always @(rst_n  ) rst_n_in   <= #BUS_DELAY rst_n;
1890    always @(ck     ) ck_in      <= #BUS_DELAY ck;
1891    always @(ck_n   ) ck_n_in    <= #BUS_DELAY ck_n;
1892    always @(cke    ) cke_in     <= #BUS_DELAY cke;
1893    always @(cs_n   ) cs_n_in    <= #BUS_DELAY cs_n;
1894    always @(ras_n  ) ras_n_in   <= #BUS_DELAY ras_n;
1895    always @(cas_n  ) cas_n_in   <= #BUS_DELAY cas_n;
1896    always @(we_n   ) we_n_in    <= #BUS_DELAY we_n;
1897    always @(dm_tdqs) dm_in      <= #BUS_DELAY dm_tdqs;
1898    always @(ba     ) ba_in      <= #BUS_DELAY ba;
1899    always @(addr   ) addr_in    <= #BUS_DELAY addr;
1900    always @(dq     ) dq_in      <= #BUS_DELAY dq;
1901    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
1902    always @(odt    ) odt_in     <= #BUS_DELAY odt;
1903    // create internal clock
1904    always @(posedge ck_in) diff_ck <= ck_in;
1905    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
1906    
1907    wire    [15:0] dqs_even = dqs_in[15:0];
1908    wire    [15:0] dqs_odd  = dqs_in[31:16];
1909    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 
1910
1911    // transmit
1912    reg                    dqs_out_en;
1913    reg     [DQS_BITS-1:0] dqs_out_en_dly;
1914    reg                    dqs_out;
1915    reg     [DQS_BITS-1:0] dqs_out_dly;
1916    reg                    dq_out_en;
1917    reg     [DQ_BITS-1:0]  dq_out_en_dly;
1918    reg     [DQ_BITS-1:0]  dq_out;
1919    reg     [DQ_BITS-1:0]  dq_out_dly;
1920    integer                rdqsen_cntr;
1921    integer                rdqs_cntr;
1922    integer                rdqen_cntr;
1923    integer                rdq_cntr;
1924
1925    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
1926    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
1927    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
1928    assign tdqs_n = {DQS_BITS{1'bz}};
1929
1930    initial begin
1931        if (BL_MAX < 2) 
1932            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
1933        if ((1<<BO_BITS) > BL_MAX) 
1934            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
1935
1936        $timeformat (-12, 1, " ps", 1);
1937        seed = RANDOM_SEED;
1938
1939        ck_cntr = 0;
1940    end
1941
1942    function integer get_rtt_wr;
1943    input [1:0] rtt;
1944    begin
1945        get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
1946    end
1947    endfunction
1948
1949    function integer get_rtt_nom;
1950    input [2:0] rtt;
1951    begin
1952        case (rtt)
1953            1: get_rtt_nom = RZQ/4;
1954            2: get_rtt_nom = RZQ/2;
1955            3: get_rtt_nom = RZQ/6;
1956            4: get_rtt_nom = RZQ/12;
1957            5: get_rtt_nom = RZQ/8;
1958            default : get_rtt_nom = 0;
1959        endcase
1960    end
1961    endfunction
1962
1963    // calculate the absolute value of a real number
1964    function real abs_value;
1965    input arg;
1966    real arg;
1967    begin
1968        if (arg < 0.0)
1969            abs_value = -1.0 * arg;
1970        else
1971            abs_value = arg;
1972    end
1973    endfunction
1974
1975    function integer ceil;
1976        input number;
1977        real number;
1978
1979        // LMR 4.1.7
1980        // When either operand of a relational expression is a real operand then the other operand shall be converted
1981        // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
1982        if (number > $rtoi(number))
1983            ceil = $rtoi(number) + 1;
1984        else
1985            ceil = number;
1986    endfunction
1987
1988    function integer floor;
1989        input number;
1990        real number;
1991
1992        // LMR 4.1.7
1993        // When either operand of a relational expression is a real operand then the other operand shall be converted
1994        // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
1995        if (number < $rtoi(number))
1996            floor = $rtoi(number) - 1;
1997        else
1998            floor = number;
1999    endfunction
2000
2001`ifdef MAX_MEM
2002
2003    function integer open_bank_file( input integer bank );
2004        integer fd;
2005        reg [2048:1] filename;
2006        begin 
2007            $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
2008
2009            fd = $fopen(filename, "w+");
2010            if (fd == 0)
2011            begin
2012                $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
2013                $finish;
2014            end
2015            else
2016            begin
2017                if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
2018                open_bank_file = fd;
2019            end
2020
2021        end
2022    endfunction
2023
2024    function [RFF_BITS:1] read_from_file( 
2025        input integer fd, 
2026        input integer index 
2027    );
2028        integer code;
2029        integer offset;
2030        reg [1024:1] msg;
2031        reg [RFF_BITS:1] read_value;
2032    
2033        begin
2034            offset = index * RFF_CHUNK;
2035            code = $fseek( fd, offset, 0 );
2036            // $fseek returns 0 on success, -1 on failure
2037            if (code != 0)
2038            begin
2039                $display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
2040                $finish;
2041            end
2042        
2043            code = $fscanf(fd, "%z", read_value);
2044            // $fscanf returns number of items read
2045            if (code != 1)
2046            begin
2047                if ($ferror(fd,msg) != 0)
2048                begin
2049                    $display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
2050                    $display(msg);
2051                    $finish;
2052                end
2053                else
2054                    read_value = 'hx;
2055            end
2056    
2057            /* when reading from unwritten portions of the file, 0 will be returned.
2058            * Use 0 in bit 1 as indicator that invalid data has been read.
2059            * A true 0 is encoded as Z.
2060            */
2061            if (read_value[1] === 1'bz)
2062                // true 0 encoded as Z, data is valid
2063                read_value[1] = 1'b0;
2064            else if (read_value[1] === 1'b0)
2065                // read from file section that has not been written
2066                read_value = 'hx;
2067
2068            read_from_file = read_value;
2069        end
2070    endfunction
2071    
2072    task write_to_file( 
2073        input integer fd, 
2074        input integer index, 
2075        input [RFF_BITS:1] data 
2076    );
2077        integer code;
2078        integer offset;
2079    
2080        begin
2081            offset = index * RFF_CHUNK;
2082            code = $fseek( fd, offset, 0 );
2083            if (code != 0)
2084            begin
2085                $display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
2086                $finish;
2087            end
2088        
2089            // encode a valid data 
2090            if (data[1] === 1'bz)
2091                data[1] = 1'bx;
2092            else if (data[1] === 1'b0)
2093                data[1] = 1'bz;
2094
2095            $fwrite( fd, "%z", data );
2096        end
2097    endtask
2098`else
2099    function get_index;
2100        input [`MAX_BITS-1:0] addr;
2101        begin : index
2102            get_index = 0;
2103            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
2104                if (address[memory_index] == addr) begin
2105                    get_index = 1;
2106                    disable index;
2107                end
2108            end
2109        end
2110    endfunction
2111`endif
2112
2113    task memory_write;
2114        input  [BA_BITS-1:0]  bank;
2115        input  [ROW_BITS-1:0] row;
2116        input  [COL_BITS-1:0] col;
2117        input  [BL_MAX*DQ_BITS-1:0] data;
2118        reg    [`MAX_BITS-1:0] addr;
2119        begin
2120`ifdef MAX_MEM
2121            addr = {row, col}/BL_MAX;
2122            write_to_file( memfd[bank], addr, data );
2123`else
2124            // chop off the lowest address bits
2125            addr = {bank, row, col}/BL_MAX;
2126            if (get_index(addr)) begin
2127                address[memory_index] = addr;
2128                memory[memory_index] = data;
2129            end else if (memory_used == `MEM_SIZE) begin
2130                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
2131                if (STOP_ON_ERROR) $stop(0);
2132            end else begin
2133                address[memory_used] = addr;
2134                memory[memory_used] = data;
2135                memory_used = memory_used + 1;
2136            end
2137`endif
2138        end
2139    endtask
2140
2141    task memory_read;
2142        input  [BA_BITS-1:0]  bank;
2143        input  [ROW_BITS-1:0] row;
2144        input  [COL_BITS-1:0] col;
2145        output [BL_MAX*DQ_BITS-1:0] data;
2146        reg    [`MAX_BITS-1:0] addr;
2147        begin
2148`ifdef MAX_MEM
2149            addr = {row, col}/BL_MAX;
2150            data = read_from_file( memfd[bank], addr );
2151`else
2152            // chop off the lowest address bits
2153            addr = {bank, row, col}/BL_MAX;
2154            if (get_index(addr)) begin
2155                data = memory[memory_index];
2156            end else begin
2157                data = {BL_MAX*DQ_BITS{1'bx}};
2158            end
2159`endif
2160        end
2161    endtask
2162
2163    task set_latency;
2164        begin
2165            if (al == 0) begin
2166                additive_latency = 0;
2167            end else begin
2168                additive_latency = cas_latency - al;
2169            end
2170            read_latency = cas_latency + additive_latency;
2171            write_latency = cas_write_latency + additive_latency;
2172        end
2173    endtask
2174
2175    // this task will erase the contents of 0 or more banks
2176    task erase_banks;
2177        input  [`BANKS-1:0] banks; //one select bit per bank
2178        reg [BA_BITS-1:0] ba;
2179        reg [`MAX_BITS-1:0] i;
2180        integer bank;
2181
2182        begin
2183
2184`ifdef MAX_MEM
2185        for (bank = 0; bank < `BANKS; bank = bank + 1)
2186            if (banks[bank] === 1'b1) begin
2187	        $fclose(memfd[bank]);
2188                memfd[bank] = open_bank_file(bank);
2189	    end
2190`else
2191        memory_index = 0;
2192        i = 0;
2193        // remove the selected banks
2194        for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
2195            ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
2196            if (!banks[ba]) begin //bank is selected to keep
2197                address[i] = address[memory_index];
2198                memory[i] = memory[memory_index];
2199                i = i + 1;
2200            end
2201        end
2202        // clean up the unused banks
2203        for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
2204            address[memory_index] = 'bx;
2205            memory[memory_index] = {8*DQ_BITS{1'bx}};
2206        end
2207        memory_used = i;
2208`endif
2209        end
2210    endtask
2211
2212    // Before this task runs, the model must be in a valid state for precharge power down and out of reset.
2213    // After this task runs, NOP commands must be issued until TZQINIT has been met
2214    task initialize;
2215        input [ADDR_BITS-1:0] mode_reg0;
2216        input [ADDR_BITS-1:0] mode_reg1;
2217        input [ADDR_BITS-1:0] mode_reg2;
2218        input [ADDR_BITS-1:0] mode_reg3;
2219        begin
2220            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
2221            cmd_task(1,       NOP, 'bx, 'bx);
2222            cmd_task(1,        ZQ, 'bx, 'h400); //ZQCL
2223            cmd_task(1, LOAD_MODE, 3, mode_reg3);
2224            cmd_task(1, LOAD_MODE, 2, mode_reg2);
2225            cmd_task(1, LOAD_MODE, 1, mode_reg1);
2226            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
2227            cmd_task(0,       NOP, 'bx, 'bx);
2228        end
2229    endtask
2230    
2231    task reset_task;
2232        integer i;
2233        begin
2234            // disable inputs
2235            dq_in_valid         = 0;
2236            dqs_in_valid       <= 0;
2237            wdqs_cntr           = 0;
2238            wdq_cntr            = 0;
2239            for (i=0; i<31; i=i+1) begin
2240                wdqs_pos_cntr[i]    <= 0;
2241            end
2242            b2b_write           <= 0;
2243            // disable outputs
2244            out_en              = 0;
2245            dq_out_en           = 0;
2246            rdq_cntr            = 0;
2247            dqs_out_en          = 0;
2248            rdqs_cntr           = 0;
2249            // disable ODT
2250            odt_en              = 0;
2251            dyn_odt_en          = 0;
2252            odt_state           = 0;
2253            dyn_odt_state       = 0;
2254            // reset bank state
2255            active_bank         = 0;
2256            auto_precharge_bank = 0;
2257            read_precharge_bank  = 0;
2258	        write_precharge_bank = 0;
2259            // require initialization sequence
2260
2261            init_done            = 0;
2262		    mpr_en              = 0;
2263            init_step           = 0;
2264            init_mode_reg       = 0;
2265            init_dll_reset      = 0;
2266            zq_set              = 0;
2267            // reset DLL
2268            dll_en              = 0;
2269            dll_reset           = 0;
2270            dll_locked          = 0;
2271            // exit power down and self refresh
2272            prev_cke            = 1'bx;
2273            in_power_down       = 0;
2274            in_self_refresh     = 0;
2275            // clear pipelines
2276            al_pipeline         = 0;
2277            wr_pipeline         = 0;
2278            rd_pipeline         = 0;
2279            odt_pipeline        = 0;
2280            dyn_odt_pipeline    = 0;
2281        end
2282    endtask
2283
2284    parameter SAME_BANK  = 2'd0; // same bank, same group
2285    parameter DIFF_BANK  = 2'd1; // different bank, same group
2286    parameter DIFF_GROUP = 2'd2; // different bank, different group
2287
2288    task chk_err;
2289        input [1:0] relationship;
2290        input [BA_BITS-1:0] bank;
2291        input [3:0] fromcmd;
2292        input [3:0] cmd;
2293        reg err;
2294    begin
2295//        $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
2296        casex ({truebl4, relationship, fromcmd, cmd})
2297            // load mode
2298            {1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end
2299            {1'bx, DIFF_BANK , LOAD_MODE, READ     } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))                                         $display ("%m: at time %t ERROR:  tMOD violation during %s", $time, cmd_string[cmd]);                         end
2300            {1'bx, DIFF_BANK , LOAD_MODE, REFRESH  } ,
2301            {1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
2302            {1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
2303            {1'bx, DIFF_BANK , LOAD_MODE, ZQ       } ,
2304            {1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
2305            {1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))                                         $display ("%m: at time %t ERROR:  tMOD violation during %s", $time, cmd_string[cmd]);                         end
2306
2307            // refresh
2308            {1'bx, DIFF_BANK , REFRESH  , LOAD_MODE} ,
2309            {1'bx, DIFF_BANK , REFRESH  , REFRESH  } ,
2310            {1'bx, DIFF_BANK , REFRESH  , PRECHARGE} ,
2311            {1'bx, DIFF_BANK , REFRESH  , ACTIVATE } ,
2312            {1'bx, DIFF_BANK , REFRESH  , ZQ       } ,
2313            {1'bx, DIFF_BANK , REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end
2314            {1'bx, DIFF_BANK , REFRESH  , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN)                                                                              $display ("%m: at time %t ERROR:  tREFPDEN violation during %s", $time, cmd_string[cmd]);                     end
2315
2316            // precharge
2317            {1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP)                                                                        $display ("%m: at time %t ERROR:   tRP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end 
2318            {1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
2319            {1'bx, DIFF_BANK , PRECHARGE, REFRESH  } ,
2320            {1'bx, DIFF_BANK , PRECHARGE, ZQ       } ,
2321            {1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP)                                                                                   $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end
2322            {1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
2323
2324            // activate
2325            {1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX)                                                                    $display ("%m: at time %t ERROR:  tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
2326                                                             if ($time - tm_bank_activate[bank] < TRAS_MIN)                                                                    $display ("%m: at time %t ERROR:  tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
2327            {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC)                                                                         $display ("%m: at time %t ERROR:   tRC violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2328            {1'bx, SAME_BANK , ACTIVATE , WRITE    } ,
2329            {1'bx, SAME_BANK , ACTIVATE , READ     } : ; // tRCD is checked outside this task
2330            {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK))                                           $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2331            {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK))             $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2332            {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK))                                     $display ("%m: at time %t ERROR:  tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);     end
2333            {1'bx, DIFF_BANK , ACTIVATE , REFRESH  } : begin if ($time - tm_activate < TRC)                                                                                    $display ("%m: at time %t ERROR:   tRC violation during %s", $time, cmd_string[cmd]);                         end
2334            {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN)                                                                             $display ("%m: at time %t ERROR:  tACTPDEN violation during %s", $time, cmd_string[cmd]);                     end
2335
2336            // write
2337            {1'bx, SAME_BANK , WRITE    , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR:   tWR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2338            {1'b0, DIFF_BANK , WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD)                                                                                    $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2339            {1'b1, DIFF_BANK , WRITE    , WRITE    } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD)                                                                     $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2340            {1'b0, DIFF_BANK , WRITE    , READ     } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency)                            $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2341            {1'b1, DIFF_BANK , WRITE    , READ     } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency)             $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2342            {1'b1, DIFF_GROUP, WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD_DG)                                                                                 $display ("%m: at time %t ERROR:  tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);     end
2343            {1'b1, DIFF_GROUP, WRITE    , READ     } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency)                         $display ("%m: at time %t ERROR:  tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);     end
2344            {1'bx, DIFF_BANK , WRITE    , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2))                        $display ("%m: at time %t ERROR:  tWRPDEN violation during %s", $time, cmd_string[cmd]);                      end
2345
2346            // read
2347            {1'bx, SAME_BANK , READ     , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK))      $display ("%m: at time %t ERROR:  tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2348            {1'b0, DIFF_BANK , READ     , WRITE    } : ; // tRTW is checked outside this task
2349            {1'b1, DIFF_BANK , READ     , WRITE    } : ; // tRTW is checked outside this task
2350            {1'b0, DIFF_BANK , READ     , READ     } : begin if (ck_cntr - ck_read < TCCD)                                                                                     $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2351            {1'b1, DIFF_BANK , READ     , READ     } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD)                                                                      $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
2352            {1'b1, DIFF_GROUP, READ     , WRITE    } : ; // tRTW is checked outside this task
2353            {1'b1, DIFF_GROUP, READ     , READ     } : begin if (ck_cntr - ck_read < TCCD_DG)                                                                                  $display ("%m: at time %t ERROR:  tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);     end
2354            {1'bx, DIFF_BANK , READ     , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5)                                                                         $display ("%m: at time %t ERROR:  tRDPDEN violation during %s", $time, cmd_string[cmd]);                      end
2355
2356            // zq
2357            {1'bx, DIFF_BANK , ZQ       , LOAD_MODE} : ; // 1 tCK
2358            {1'bx, DIFF_BANK , ZQ       , REFRESH  } ,
2359            {1'bx, DIFF_BANK , ZQ       , PRECHARGE} ,
2360            {1'bx, DIFF_BANK , ZQ       , ACTIVATE } ,
2361            {1'bx, DIFF_BANK , ZQ       , ZQ       } ,
2362            {1'bx, DIFF_BANK , ZQ       , PWR_DOWN } ,
2363            {1'bx, DIFF_BANK , ZQ       , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT)                                                                                $display ("%m: at time %t ERROR:  tZQinit violation during %s", $time, cmd_string[cmd]);
2364                                                             if (ck_cntr - ck_zqoper < TZQOPER)                                                                                $display ("%m: at time %t ERROR:  tZQoper violation during %s", $time, cmd_string[cmd]);
2365                                                             if (ck_cntr - ck_zqcs < TZQCS)                                                                                    $display ("%m: at time %t ERROR:  tZQCS violation during %s", $time, cmd_string[cmd]);                        end
2366
2367            // power down
2368            {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
2369            {1'bx, DIFF_BANK , PWR_DOWN , REFRESH  } ,
2370            {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
2371            {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
2372            {1'bx, DIFF_BANK , PWR_DOWN , WRITE    } ,
2373            {1'bx, DIFF_BANK , PWR_DOWN , ZQ       } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK))                                         $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
2374            {1'bx, DIFF_BANK , PWR_DOWN , READ     } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK))                                         $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                            
2375                                                        else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))                               $display ("%m: at time %t ERROR:  tXPDLL violation during %s", $time, cmd_string[cmd]);                       end
2376            {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
2377            {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK))                                         $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);
2378                                                             if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN))                                              $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);
2379                                                             if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR:  tXPDLL violation during %s", $time, cmd_string[cmd]);
2380                                                             if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK))                                             $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                                             end
2381
2382            // self refresh
2383            {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
2384            {1'bx, DIFF_BANK , SELF_REF , REFRESH  } ,
2385            {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
2386            {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
2387            {1'bx, DIFF_BANK , SELF_REF , WRITE    } ,
2388            {1'bx, DIFF_BANK , SELF_REF , ZQ       } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK))                                     $display ("%m: at time %t ERROR:   tXS violation during %s", $time, cmd_string[cmd]);                         end
2389            {1'bx, DIFF_BANK , SELF_REF , READ     } : begin if (ck_cntr - ck_self_refresh < TXSDLL)                                                                           $display ("%m: at time %t ERROR:  tXSDLL violation during %s", $time, cmd_string[cmd]);                       end
2390            {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
2391            {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK))                                     $display ("%m: at time %t ERROR:   tXS violation during %s", $time, cmd_string[cmd]);
2392                                                             if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK))                                             $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                                             end
2393        endcase
2394    end
2395    endtask
2396
2397    task cmd_task;
2398        input cke;
2399        input [2:0] cmd;
2400        input [BA_BITS-1:0] bank;
2401        input [ADDR_BITS-1:0] addr;
2402        reg [`BANKS:0] i;
2403        integer j;
2404        reg [`BANKS:0] tfaw_cntr;
2405        reg [COL_BITS-1:0] col;
2406        reg group;
2407        begin
2408            // tRFC max check
2409            if (!er_trfc_max && !in_self_refresh) begin
2410                if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
2411                    $display ("%m: at time %t ERROR:  tRFC maximum violation during %s", $time, cmd_string[cmd]);
2412                    er_trfc_max = 1;
2413                end
2414            end
2415            if (cke) begin
2416                if ((cmd < NOP) && (cmd != PRECHARGE)) begin
2417                    if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
2418                        $display ("%m: at time %t ERROR:  tXPR violation during %s", $time, cmd_string[cmd]);
2419                    for (j=0; j<=SELF_REF; j=j+1) begin
2420                        chk_err(SAME_BANK , bank, j, cmd);
2421                        chk_err(DIFF_BANK , bank, j, cmd);
2422                        chk_err(DIFF_GROUP, bank, j, cmd);
2423                    end
2424                end
2425                case (cmd)
2426                    LOAD_MODE : begin
2427                        if (|odt_pipeline)
2428                            $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
2429                        if (odt_state)
2430                            $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
2431
2432                        if (|active_bank) begin
2433                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
2434                            if (STOP_ON_ERROR) $stop(0);
2435                        end else begin
2436                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
2437                            if (bank>>2) begin
2438                                $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
2439                            end
2440                            case (bank)
2441                                0 : begin
2442                                    // Burst Length
2443                                    if (addr[1:0] == 2'b00) begin
2444                                        burst_length = 8;
2445                                        blotf = 0;
2446                                        truebl4 = 0;
2447                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
2448                                    end else if (addr[1:0] == 2'b01) begin
2449                                        burst_length = 8;
2450                                        blotf = 1;
2451                                        truebl4 = 0;
2452                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
2453                                    end else if (addr[1:0] == 2'b10) begin
2454                                        burst_length = 4;
2455                                        blotf = 0;
2456                                        truebl4 = 0;
2457                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
2458                                    end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
2459                                        burst_length = 4;
2460                                        blotf = 0;
2461                                        truebl4 = 1;
2462                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
2463                                    end else begin
2464                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
2465                                    end
2466                                    // Burst Order
2467                                    burst_order = addr[3];
2468                                    if (!burst_order) begin
2469                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
2470                                    end else if (burst_order) begin
2471                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
2472                                    end else begin
2473                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
2474                                    end
2475                                    // CAS Latency
2476                                    cas_latency = {addr[2],addr[6:4]} + 4;
2477                                    set_latency;
2478                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
2479                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
2480                                    end else begin
2481                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
2482                                    end
2483                                    // Reserved
2484                                    if (addr[7] !== 0 && check_strict_mrbits) begin
2485                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2486                                    end
2487                                    // DLL Reset
2488                                    dll_reset = addr[8];
2489                                    if (!dll_reset) begin
2490                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
2491                                    end else if (dll_reset) begin
2492                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
2493                                        dll_locked = 0;
2494                                        init_dll_reset = 1;
2495                                        ck_dll_reset <= ck_cntr;
2496                                    end else begin
2497                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
2498                                    end
2499
2500								   // Write Recovery
2501								   if (addr[11:9] == 0) begin
2502									  write_recovery  = 16;
2503								   end else if (addr[11:9] < 4) begin
2504									  write_recovery  = addr[11:9] + 4;
2505								   end else begin
2506									  write_recovery  = 2*addr[11:9];
2507								   end
2508
2509                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
2510                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
2511                                    end else begin
2512                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
2513                                    end
2514                                    // Power Down Mode
2515                                    low_power = !addr[12];
2516                                    if (!low_power) begin
2517                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
2518                                    end else if (low_power) begin
2519                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
2520                                    end else begin
2521                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
2522                                    end
2523                                    // Reserved
2524                                    if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
2525                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2526                                    end
2527                                end
2528                                1 : begin
2529                                    // DLL Enable
2530                                    dll_en = !addr[0];
2531                                    if (!dll_en) begin
2532                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
2533                                        if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
2534                                    end else if (dll_en) begin
2535                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
2536                                    end else begin
2537                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
2538                                    end
2539                                    // Output Drive Strength
2540                                    if ({addr[5], addr[1]} == 2'b00) begin
2541                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
2542                                    end else if ({addr[5], addr[1]} == 2'b01) begin
2543                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
2544                                    end else if ({addr[5], addr[1]} == 2'b11) begin
2545                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
2546                                    end else begin
2547                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
2548                                    end
2549                                    // ODT Rtt (Rtt_NOM)
2550                                    odt_rtt_nom = {addr[9], addr[6], addr[2]};
2551                                    if (odt_rtt_nom == 3'b000) begin
2552                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
2553                                        odt_en = 0;
2554                                    end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
2555                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
2556                                        odt_en = 1;
2557                                    end else begin
2558                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
2559                                        odt_en = 0;
2560                                    end
2561                                    // Report the additive latency value
2562                                    al = addr[4:3];
2563                                    set_latency;
2564                                    if (al == 0) begin
2565                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
2566                                    end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
2567                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
2568                                    end else begin
2569                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
2570                                    end
2571                                    // Write Levelization
2572                                    write_levelization = addr[7];
2573                                    if (!write_levelization) begin
2574                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
2575                                    end else if (write_levelization) begin
2576                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
2577                                    end else begin
2578                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
2579                                    end
2580                                    // Reserved
2581                                    if (addr[8] !== 0 && check_strict_mrbits) begin
2582                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2583                                    end
2584                                    // Reserved
2585                                    if (addr[10] !== 0 && check_strict_mrbits) begin
2586                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2587                                    end
2588                                    // TDQS Enable
2589                                    tdqs_en = addr[11];
2590                                    if (!tdqs_en) begin
2591                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
2592                                    end else if (tdqs_en) begin
2593                                        if (8 == DQ_BITS) begin
2594										    if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
2595                                        end
2596									    else begin
2597                                            $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable.  TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
2598                                            tdqs_en = 0;
2599										end   
2600                                    end else begin
2601                                        $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
2602                                    end 
2603                                    // Output Enable
2604                                    out_en = !addr[12];
2605                                    if (!out_en) begin
2606                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
2607                                    end else if (out_en) begin
2608                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
2609                                    end else begin
2610                                        $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
2611                                    end 
2612                                    // Reserved
2613                                    if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
2614                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2615                                    end
2616                                end
2617                                2 : begin
2618								    if (feature_pasr) begin
2619                                        // Partial Array Self Refresh
2620                                        pasr = addr[2:0];
2621                                        case (pasr)
2622                                            3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
2623                                            3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
2624                                            3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
2625                                            3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
2626                                            3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
2627                                            3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
2628                                            3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
2629                                            3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
2630                                            default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
2631                                        endcase 
2632									end 
2633								    else
2634                                    if (addr[2:0] !== 0 && check_strict_mrbits) begin
2635                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2636                                    end
2637                                    // CAS Write Latency
2638                                    cas_write_latency = addr[5:3]+5;
2639                                    set_latency;
2640                                    if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
2641                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
2642                                    end else begin
2643                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
2644                                    end
2645                                    // Auto Self Refresh Method
2646                                    asr = addr[6];
2647                                    if (!asr) begin
2648                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
2649                                    end else if (asr) begin
2650                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
2651                                        if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
2652                                    end else begin
2653                                        $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
2654                                    end 
2655                                    // Self Refresh Temperature
2656                                    srt = addr[7];
2657                                    if (!srt) begin
2658                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
2659                                    end else if (srt) begin
2660                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
2661                                        if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
2662                                    end else begin
2663                                        $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
2664                                    end 
2665                                    if (asr && srt)
2666                                        $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
2667                                    // Reserved
2668                                    if (addr[8] !== 0 && check_strict_mrbits) begin
2669                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2670                                    end
2671                                    // Dynamic ODT (Rtt_WR)
2672                                    odt_rtt_wr = addr[10:9];
2673                                    if (odt_rtt_wr == 2'b00) begin
2674                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
2675                                        dyn_odt_en = 0;
2676                                    end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
2677                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
2678                                        dyn_odt_en = 1;
2679                                    end else begin
2680                                        $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
2681                                        dyn_odt_en = 0;
2682                                    end
2683                                    // Reserved
2684                                    if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
2685                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2686                                    end
2687                                end
2688                                3 : begin
2689                                    mpr_select = addr[1:0];
2690                                    // MultiPurpose Register Select
2691                                    if (mpr_select == 2'b00) begin
2692                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
2693                                    end else begin
2694                                        if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
2695                                    end
2696                                    // MultiPurpose Register Enable
2697                                    mpr_en = addr[2];
2698                                    if (!mpr_en) begin
2699                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
2700                                    end else if (mpr_en) begin
2701                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
2702                                    end else begin
2703                                        $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
2704                                    end 
2705                                    // Reserved
2706                                    if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
2707                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
2708                                    end
2709                                end
2710                            endcase
2711                            if (dyn_odt_en && write_levelization)
2712                                $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
2713                            init_mode_reg[bank] = 1;
2714                            mode_reg[bank] = addr;
2715                            tm_load_mode <= $time;
2716                            ck_load_mode <= ck_cntr;
2717                        end
2718                    end
2719                    REFRESH : begin
2720                        if (mpr_en) begin
2721                            $display ("%m: at time %t ERROR: %s Failure.  Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
2722                            if (STOP_ON_ERROR) $stop(0);
2723                        end else if (|active_bank) begin
2724                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
2725                            if (STOP_ON_ERROR) $stop(0);
2726                        end else begin
2727                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
2728                            er_trfc_max = 0;
2729                            ref_cntr = ref_cntr + 1;
2730                            tm_refresh <= $time;
2731                            ck_refresh <= ck_cntr;
2732                        end
2733                    end
2734                    PRECHARGE : begin
2735                        if (addr[AP]) begin
2736                            if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
2737                        end
2738                        // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), 
2739                        // or if the previously open row is already in the process of precharging
2740                        if (|active_bank) begin
2741                            if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
2742                                $display ("%m: at time %t ERROR:  tXPR violation during %s", $time, cmd_string[cmd]);
2743                            if (mpr_en) begin
2744                                $display ("%m: at time %t ERROR: %s Failure.  Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
2745                                if (STOP_ON_ERROR) $stop(0);
2746                            end else begin
2747                                for (i=0; i<`BANKS; i=i+1) begin
2748                                    if (active_bank[i]) begin
2749                                        if (addr[AP] || (i == bank)) begin
2750
2751                                            for (j=0; j<=SELF_REF; j=j+1) begin
2752                                                chk_err(SAME_BANK, i, j, cmd);
2753                                                chk_err(DIFF_BANK, i, j, cmd);
2754                                            end
2755
2756                                            if (auto_precharge_bank[i]) begin
2757                                                $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
2758                                                if (STOP_ON_ERROR) $stop(0);
2759                                            end else begin
2760                                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
2761                                                active_bank[i] = 1'b0;
2762                                                tm_bank_precharge[i] <= $time;
2763                                                tm_precharge <= $time;
2764                                                ck_precharge <= ck_cntr;
2765                                            end
2766                                        end
2767                                    end
2768                                end
2769                            end
2770                        end
2771                    end
2772                    ACTIVATE : begin
2773                        tfaw_cntr = 0;
2774                        for (i=0; i<`BANKS; i=i+1) begin
2775                            if ($time - tm_bank_activate[i] < TFAW) begin
2776                                tfaw_cntr = tfaw_cntr + 1;
2777                            end
2778                        end
2779                        if (tfaw_cntr > 3) begin
2780                            $display ("%m: at time %t ERROR:  tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
2781                        end
2782
2783                        if (mpr_en) begin
2784                            $display ("%m: at time %t ERROR: %s Failure.  Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
2785                            if (STOP_ON_ERROR) $stop(0);
2786                        end else if (!init_done) begin
2787                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
2788                            if (STOP_ON_ERROR) $stop(0);
2789                        end else if (active_bank[bank]) begin
2790                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
2791                            if (STOP_ON_ERROR) $stop(0);
2792                        end else begin
2793                            if (addr >= 1<<ROW_BITS) begin
2794                                $display ("%m: at time %t WARNING: row = %h does not exist.  Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
2795                            end
2796                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
2797                            active_bank[bank] = 1'b1;
2798                            active_row[bank] = addr;
2799                            tm_group_activate[bank[1]] <= $time;
2800                            tm_activate <= $time;
2801                            tm_bank_activate[bank] <= $time;
2802                            ck_group_activate[bank[1]] <= ck_cntr;
2803                            ck_activate <= ck_cntr;
2804                        end
2805                    end
2806                    WRITE : begin
2807                        if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
2808                            if (truebl4) begin
2809                                if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
2810                                    $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
2811                                if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
2812                                    $display ("%m: at time %t ERROR:  tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
2813                            end else begin
2814                                if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
2815                                    $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
2816                            end
2817                        end else begin // BL=8
2818                            if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
2819                                $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
2820                        end
2821
2822                        if (mpr_en) begin
2823                            $display ("%m: at time %t ERROR: %s Failure.  Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
2824                            if (STOP_ON_ERROR) $stop(0);
2825                        end else if (!init_done) begin
2826                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
2827                            if (STOP_ON_ERROR) $stop(0);
2828                        end else if (!active_bank[bank])  begin
2829                            if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
2830                            if (STOP_ON_ERROR) $stop(0);
2831                        end else if (auto_precharge_bank[bank]) begin
2832                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
2833                            if (STOP_ON_ERROR) $stop(0);
2834                        end else if (ck_cntr - ck_write < burst_length/2) begin
2835                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
2836                            if (STOP_ON_ERROR) $stop(0);
2837                        end else begin
2838                            if (addr[AP]) begin
2839                                auto_precharge_bank[bank] = 1'b1;
2840                                write_precharge_bank[bank] = 1'b1;
2841                            end
2842                            col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
2843                            if (col >= 1<<COL_BITS) begin
2844                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
2845                            end
2846                            if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
2847                                col = col & -4;
2848                            end else begin // BL=8
2849                                col = col & -8;
2850                            end
2851                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
2852                            wr_pipeline[2*write_latency + 1]  = 1;
2853                            ba_pipeline[2*write_latency + 1]  = bank;
2854                            row_pipeline[2*write_latency + 1] = active_row[bank];
2855                            col_pipeline[2*write_latency + 1] = col;
2856                            if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
2857                                bl_pipeline[2*write_latency + 1] = 4;
2858                                if (mpr_en && col%4) begin
2859                                    $display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
2860                                end
2861                            end else begin // BL=8
2862                                bl_pipeline[2*write_latency + 1] = 8;
2863                                if (odt_in) begin
2864                                    ck_odth8 <= ck_cntr;
2865                                end
2866                            end
2867                            for (j=0; j<(burst_length + 4); j=j+1) begin
2868                                dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
2869                            end
2870                            ck_bank_write[bank] <= ck_cntr;
2871                            ck_group_write[bank[1]] <= ck_cntr;
2872                            ck_write <= ck_cntr;
2873                        end
2874                    end
2875                    READ : begin
2876                        if (!dll_locked)
2877                            $display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
2878                        if (mpr_en && (addr[1:0] != 2'b00)) begin
2879                            $display ("%m: at time %t ERROR: %s Failure.  addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
2880                            if (STOP_ON_ERROR) $stop(0);
2881                        end else if (!init_done) begin
2882                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
2883                            if (STOP_ON_ERROR) $stop(0);
2884                        end else if (!active_bank[bank] && !mpr_en) begin
2885                            if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
2886                            if (STOP_ON_ERROR) $stop(0);
2887                        end else if (auto_precharge_bank[bank]) begin
2888                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
2889                            if (STOP_ON_ERROR) $stop(0);
2890                        end else if (ck_cntr - ck_read < burst_length/2) begin
2891                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
2892                            if (STOP_ON_ERROR) $stop(0);
2893                        end else begin
2894                            if (addr[AP] && !mpr_en) begin
2895                                auto_precharge_bank[bank] = 1'b1;
2896                                read_precharge_bank[bank] = 1'b1;
2897                            end
2898                            col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
2899                            if (col >= 1<<COL_BITS) begin
2900                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
2901                            end
2902                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
2903                            rd_pipeline[2*read_latency - 1]  = 1;
2904                            ba_pipeline[2*read_latency - 1]  = bank;
2905                            row_pipeline[2*read_latency - 1] = active_row[bank];
2906                            col_pipeline[2*read_latency - 1] = col;
2907                            if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
2908                                bl_pipeline[2*read_latency - 1] = 4;
2909                                if (mpr_en && col%4) begin
2910                                    $display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
2911                                end
2912                            end else begin // BL=8
2913                                bl_pipeline[2*read_latency - 1] = 8;
2914                                if (mpr_en && col%8) begin
2915                                    $display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
2916                                end
2917                            end
2918                            rd_bc = addr[BC];
2919                            ck_bank_read[bank] <= ck_cntr;
2920                            ck_group_read[bank[1]] <= ck_cntr;
2921                            ck_read <= ck_cntr;
2922                        end
2923                    end
2924                    ZQ : begin
2925                        if (mpr_en) begin
2926                            $display ("%m: at time %t ERROR: %s Failure.  Multipurpose Register must be disabled.", $time, cmd_string[cmd])