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/kernel/linux-source-2.6.32/drivers/scsi/mpt2sas/mpt2sas_base.c

https://bitbucket.org/ChuloChumo/sctp_thesis
C | 3727 lines | 2603 code | 423 blank | 701 comment | 361 complexity | a271c9ae883802b0c9df0c2748816304 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt2sas/mpt2_base.c
  6. * Copyright (C) 2007-2009 LSI Corporation
  7. * (mailto:DL-MPTFusionLinux@lsi.com)
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * NO WARRANTY
  20. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  21. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  22. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  23. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  24. * solely responsible for determining the appropriateness of using and
  25. * distributing the Program and assumes all risks associated with its
  26. * exercise of rights under this Agreement, including but not limited to
  27. * the risks and costs of program errors, damage to or loss of data,
  28. * programs or equipment, and unavailability or interruption of operations.
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. * You should have received a copy of the GNU General Public License
  38. * along with this program; if not, write to the Free Software
  39. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  40. * USA.
  41. */
  42. #include <linux/version.h>
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/sort.h>
  56. #include <linux/io.h>
  57. #include "mpt2sas_base.h"
  58. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  59. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  60. #define MPT2SAS_MAX_REQUEST_QUEUE 600 /* maximum controller queue depth */
  61. static int max_queue_depth = -1;
  62. module_param(max_queue_depth, int, 0);
  63. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  64. static int max_sgl_entries = -1;
  65. module_param(max_sgl_entries, int, 0);
  66. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  67. static int msix_disable = -1;
  68. module_param(msix_disable, int, 0);
  69. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  70. /**
  71. * _base_fault_reset_work - workq handling ioc fault conditions
  72. * @work: input argument, used to derive ioc
  73. * Context: sleep.
  74. *
  75. * Return nothing.
  76. */
  77. static void
  78. _base_fault_reset_work(struct work_struct *work)
  79. {
  80. struct MPT2SAS_ADAPTER *ioc =
  81. container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
  82. unsigned long flags;
  83. u32 doorbell;
  84. int rc;
  85. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  86. if (ioc->shost_recovery)
  87. goto rearm_timer;
  88. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  89. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  90. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  91. rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  92. FORCE_BIG_HAMMER);
  93. printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
  94. __func__, (rc == 0) ? "success" : "failed");
  95. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  96. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  97. mpt2sas_base_fault_info(ioc, doorbell &
  98. MPI2_DOORBELL_DATA_MASK);
  99. }
  100. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  101. rearm_timer:
  102. if (ioc->fault_reset_work_q)
  103. queue_delayed_work(ioc->fault_reset_work_q,
  104. &ioc->fault_reset_work,
  105. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  106. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  107. }
  108. /**
  109. * mpt2sas_base_start_watchdog - start the fault_reset_work_q
  110. * @ioc: pointer to scsi command object
  111. * Context: sleep.
  112. *
  113. * Return nothing.
  114. */
  115. void
  116. mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
  117. {
  118. unsigned long flags;
  119. if (ioc->fault_reset_work_q)
  120. return;
  121. /* initialize fault polling */
  122. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  123. snprintf(ioc->fault_reset_work_q_name,
  124. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  125. ioc->fault_reset_work_q =
  126. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  127. if (!ioc->fault_reset_work_q) {
  128. printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
  129. ioc->name, __func__, __LINE__);
  130. return;
  131. }
  132. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  133. if (ioc->fault_reset_work_q)
  134. queue_delayed_work(ioc->fault_reset_work_q,
  135. &ioc->fault_reset_work,
  136. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  137. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  138. }
  139. /**
  140. * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q
  141. * @ioc: pointer to scsi command object
  142. * Context: sleep.
  143. *
  144. * Return nothing.
  145. */
  146. void
  147. mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
  148. {
  149. unsigned long flags;
  150. struct workqueue_struct *wq;
  151. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  152. wq = ioc->fault_reset_work_q;
  153. ioc->fault_reset_work_q = NULL;
  154. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  155. if (wq) {
  156. if (!cancel_delayed_work(&ioc->fault_reset_work))
  157. flush_workqueue(wq);
  158. destroy_workqueue(wq);
  159. }
  160. }
  161. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  162. /**
  163. * _base_sas_ioc_info - verbose translation of the ioc status
  164. * @ioc: pointer to scsi command object
  165. * @mpi_reply: reply mf payload returned from firmware
  166. * @request_hdr: request mf
  167. *
  168. * Return nothing.
  169. */
  170. static void
  171. _base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  172. MPI2RequestHeader_t *request_hdr)
  173. {
  174. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  175. MPI2_IOCSTATUS_MASK;
  176. char *desc = NULL;
  177. u16 frame_sz;
  178. char *func_str = NULL;
  179. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  180. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  181. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  182. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  183. return;
  184. switch (ioc_status) {
  185. /****************************************************************************
  186. * Common IOCStatus values for all replies
  187. ****************************************************************************/
  188. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  189. desc = "invalid function";
  190. break;
  191. case MPI2_IOCSTATUS_BUSY:
  192. desc = "busy";
  193. break;
  194. case MPI2_IOCSTATUS_INVALID_SGL:
  195. desc = "invalid sgl";
  196. break;
  197. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  198. desc = "internal error";
  199. break;
  200. case MPI2_IOCSTATUS_INVALID_VPID:
  201. desc = "invalid vpid";
  202. break;
  203. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  204. desc = "insufficient resources";
  205. break;
  206. case MPI2_IOCSTATUS_INVALID_FIELD:
  207. desc = "invalid field";
  208. break;
  209. case MPI2_IOCSTATUS_INVALID_STATE:
  210. desc = "invalid state";
  211. break;
  212. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  213. desc = "op state not supported";
  214. break;
  215. /****************************************************************************
  216. * Config IOCStatus values
  217. ****************************************************************************/
  218. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  219. desc = "config invalid action";
  220. break;
  221. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  222. desc = "config invalid type";
  223. break;
  224. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  225. desc = "config invalid page";
  226. break;
  227. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  228. desc = "config invalid data";
  229. break;
  230. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  231. desc = "config no defaults";
  232. break;
  233. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  234. desc = "config cant commit";
  235. break;
  236. /****************************************************************************
  237. * SCSI IO Reply
  238. ****************************************************************************/
  239. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  240. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  241. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  242. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  243. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  244. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  245. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  246. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  247. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  248. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  249. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  250. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  251. break;
  252. /****************************************************************************
  253. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  254. ****************************************************************************/
  255. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  256. desc = "eedp guard error";
  257. break;
  258. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  259. desc = "eedp ref tag error";
  260. break;
  261. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  262. desc = "eedp app tag error";
  263. break;
  264. /****************************************************************************
  265. * SCSI Target values
  266. ****************************************************************************/
  267. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  268. desc = "target invalid io index";
  269. break;
  270. case MPI2_IOCSTATUS_TARGET_ABORTED:
  271. desc = "target aborted";
  272. break;
  273. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  274. desc = "target no conn retryable";
  275. break;
  276. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  277. desc = "target no connection";
  278. break;
  279. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  280. desc = "target xfer count mismatch";
  281. break;
  282. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  283. desc = "target data offset error";
  284. break;
  285. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  286. desc = "target too much write data";
  287. break;
  288. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  289. desc = "target iu too short";
  290. break;
  291. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  292. desc = "target ack nak timeout";
  293. break;
  294. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  295. desc = "target nak received";
  296. break;
  297. /****************************************************************************
  298. * Serial Attached SCSI values
  299. ****************************************************************************/
  300. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  301. desc = "smp request failed";
  302. break;
  303. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  304. desc = "smp data overrun";
  305. break;
  306. /****************************************************************************
  307. * Diagnostic Buffer Post / Diagnostic Release values
  308. ****************************************************************************/
  309. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  310. desc = "diagnostic released";
  311. break;
  312. default:
  313. break;
  314. }
  315. if (!desc)
  316. return;
  317. switch (request_hdr->Function) {
  318. case MPI2_FUNCTION_CONFIG:
  319. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  320. func_str = "config_page";
  321. break;
  322. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  323. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  324. func_str = "task_mgmt";
  325. break;
  326. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  327. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  328. func_str = "sas_iounit_ctl";
  329. break;
  330. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  331. frame_sz = sizeof(Mpi2SepRequest_t);
  332. func_str = "enclosure";
  333. break;
  334. case MPI2_FUNCTION_IOC_INIT:
  335. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  336. func_str = "ioc_init";
  337. break;
  338. case MPI2_FUNCTION_PORT_ENABLE:
  339. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  340. func_str = "port_enable";
  341. break;
  342. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  343. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  344. func_str = "smp_passthru";
  345. break;
  346. default:
  347. frame_sz = 32;
  348. func_str = "unknown";
  349. break;
  350. }
  351. printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
  352. " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
  353. _debug_dump_mf(request_hdr, frame_sz/4);
  354. }
  355. /**
  356. * _base_display_event_data - verbose translation of firmware asyn events
  357. * @ioc: pointer to scsi command object
  358. * @mpi_reply: reply mf payload returned from firmware
  359. *
  360. * Return nothing.
  361. */
  362. static void
  363. _base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
  364. Mpi2EventNotificationReply_t *mpi_reply)
  365. {
  366. char *desc = NULL;
  367. u16 event;
  368. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  369. return;
  370. event = le16_to_cpu(mpi_reply->Event);
  371. switch (event) {
  372. case MPI2_EVENT_LOG_DATA:
  373. desc = "Log Data";
  374. break;
  375. case MPI2_EVENT_STATE_CHANGE:
  376. desc = "Status Change";
  377. break;
  378. case MPI2_EVENT_HARD_RESET_RECEIVED:
  379. desc = "Hard Reset Received";
  380. break;
  381. case MPI2_EVENT_EVENT_CHANGE:
  382. desc = "Event Change";
  383. break;
  384. case MPI2_EVENT_TASK_SET_FULL:
  385. desc = "Task Set Full";
  386. break;
  387. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  388. desc = "Device Status Change";
  389. break;
  390. case MPI2_EVENT_IR_OPERATION_STATUS:
  391. desc = "IR Operation Status";
  392. break;
  393. case MPI2_EVENT_SAS_DISCOVERY:
  394. desc = "Discovery";
  395. break;
  396. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  397. desc = "SAS Broadcast Primitive";
  398. break;
  399. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  400. desc = "SAS Init Device Status Change";
  401. break;
  402. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  403. desc = "SAS Init Table Overflow";
  404. break;
  405. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  406. desc = "SAS Topology Change List";
  407. break;
  408. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  409. desc = "SAS Enclosure Device Status Change";
  410. break;
  411. case MPI2_EVENT_IR_VOLUME:
  412. desc = "IR Volume";
  413. break;
  414. case MPI2_EVENT_IR_PHYSICAL_DISK:
  415. desc = "IR Physical Disk";
  416. break;
  417. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  418. desc = "IR Configuration Change List";
  419. break;
  420. case MPI2_EVENT_LOG_ENTRY_ADDED:
  421. desc = "Log Entry Added";
  422. break;
  423. }
  424. if (!desc)
  425. return;
  426. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
  427. }
  428. #endif
  429. /**
  430. * _base_sas_log_info - verbose translation of firmware log info
  431. * @ioc: pointer to scsi command object
  432. * @log_info: log info
  433. *
  434. * Return nothing.
  435. */
  436. static void
  437. _base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
  438. {
  439. union loginfo_type {
  440. u32 loginfo;
  441. struct {
  442. u32 subcode:16;
  443. u32 code:8;
  444. u32 originator:4;
  445. u32 bus_type:4;
  446. } dw;
  447. };
  448. union loginfo_type sas_loginfo;
  449. char *originator_str = NULL;
  450. sas_loginfo.loginfo = log_info;
  451. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  452. return;
  453. /* each nexus loss loginfo */
  454. if (log_info == 0x31170000)
  455. return;
  456. /* eat the loginfos associated with task aborts */
  457. if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
  458. 0x31140000 || log_info == 0x31130000))
  459. return;
  460. switch (sas_loginfo.dw.originator) {
  461. case 0:
  462. originator_str = "IOP";
  463. break;
  464. case 1:
  465. originator_str = "PL";
  466. break;
  467. case 2:
  468. originator_str = "IR";
  469. break;
  470. }
  471. printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
  472. "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
  473. originator_str, sas_loginfo.dw.code,
  474. sas_loginfo.dw.subcode);
  475. }
  476. /**
  477. * mpt2sas_base_fault_info - verbose translation of firmware FAULT code
  478. * @ioc: pointer to scsi command object
  479. * @fault_code: fault code
  480. *
  481. * Return nothing.
  482. */
  483. void
  484. mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
  485. {
  486. printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
  487. ioc->name, fault_code);
  488. }
  489. /**
  490. * _base_display_reply_info -
  491. * @ioc: pointer to scsi command object
  492. * @smid: system request message index
  493. * @msix_index: MSIX table index supplied by the OS
  494. * @reply: reply message frame(lower 32bit addr)
  495. *
  496. * Return nothing.
  497. */
  498. static void
  499. _base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  500. u32 reply)
  501. {
  502. MPI2DefaultReply_t *mpi_reply;
  503. u16 ioc_status;
  504. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  505. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  506. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  507. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  508. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  509. _base_sas_ioc_info(ioc , mpi_reply,
  510. mpt2sas_base_get_msg_frame(ioc, smid));
  511. }
  512. #endif
  513. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
  514. _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
  515. }
  516. /**
  517. * mpt2sas_base_done - base internal command completion routine
  518. * @ioc: pointer to scsi command object
  519. * @smid: system request message index
  520. * @msix_index: MSIX table index supplied by the OS
  521. * @reply: reply message frame(lower 32bit addr)
  522. *
  523. * Return 1 meaning mf should be freed from _base_interrupt
  524. * 0 means the mf is freed from this function.
  525. */
  526. u8
  527. mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  528. u32 reply)
  529. {
  530. MPI2DefaultReply_t *mpi_reply;
  531. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  532. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  533. return 1;
  534. if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
  535. return 1;
  536. ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
  537. if (mpi_reply) {
  538. ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
  539. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  540. }
  541. ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
  542. complete(&ioc->base_cmds.done);
  543. return 1;
  544. }
  545. /**
  546. * _base_async_event - main callback handler for firmware asyn events
  547. * @ioc: pointer to scsi command object
  548. * @msix_index: MSIX table index supplied by the OS
  549. * @reply: reply message frame(lower 32bit addr)
  550. *
  551. * Return 1 meaning mf should be freed from _base_interrupt
  552. * 0 means the mf is freed from this function.
  553. */
  554. static u8
  555. _base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  556. {
  557. Mpi2EventNotificationReply_t *mpi_reply;
  558. Mpi2EventAckRequest_t *ack_request;
  559. u16 smid;
  560. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  561. if (!mpi_reply)
  562. return 1;
  563. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  564. return 1;
  565. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  566. _base_display_event_data(ioc, mpi_reply);
  567. #endif
  568. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  569. goto out;
  570. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  571. if (!smid) {
  572. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  573. ioc->name, __func__);
  574. goto out;
  575. }
  576. ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
  577. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  578. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  579. ack_request->Event = mpi_reply->Event;
  580. ack_request->EventContext = mpi_reply->EventContext;
  581. ack_request->VF_ID = 0; /* TODO */
  582. ack_request->VP_ID = 0;
  583. mpt2sas_base_put_smid_default(ioc, smid);
  584. out:
  585. /* scsih callback handler */
  586. mpt2sas_scsih_event_callback(ioc, msix_index, reply);
  587. /* ctl callback handler */
  588. mpt2sas_ctl_event_callback(ioc, msix_index, reply);
  589. return 1;
  590. }
  591. /**
  592. * _base_get_cb_idx - obtain the callback index
  593. * @ioc: per adapter object
  594. * @smid: system request message index
  595. *
  596. * Return callback index.
  597. */
  598. static u8
  599. _base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  600. {
  601. int i;
  602. u8 cb_idx = 0xFF;
  603. if (smid >= ioc->hi_priority_smid) {
  604. if (smid < ioc->internal_smid) {
  605. i = smid - ioc->hi_priority_smid;
  606. cb_idx = ioc->hpr_lookup[i].cb_idx;
  607. } else {
  608. i = smid - ioc->internal_smid;
  609. cb_idx = ioc->internal_lookup[i].cb_idx;
  610. }
  611. } else {
  612. i = smid - 1;
  613. cb_idx = ioc->scsi_lookup[i].cb_idx;
  614. }
  615. return cb_idx;
  616. }
  617. /**
  618. * _base_mask_interrupts - disable interrupts
  619. * @ioc: pointer to scsi command object
  620. *
  621. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  622. *
  623. * Return nothing.
  624. */
  625. static void
  626. _base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  627. {
  628. u32 him_register;
  629. ioc->mask_interrupts = 1;
  630. him_register = readl(&ioc->chip->HostInterruptMask);
  631. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  632. writel(him_register, &ioc->chip->HostInterruptMask);
  633. readl(&ioc->chip->HostInterruptMask);
  634. }
  635. /**
  636. * _base_unmask_interrupts - enable interrupts
  637. * @ioc: pointer to scsi command object
  638. *
  639. * Enabling only Reply Interrupts
  640. *
  641. * Return nothing.
  642. */
  643. static void
  644. _base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  645. {
  646. u32 him_register;
  647. him_register = readl(&ioc->chip->HostInterruptMask);
  648. him_register &= ~MPI2_HIM_RIM;
  649. writel(him_register, &ioc->chip->HostInterruptMask);
  650. ioc->mask_interrupts = 0;
  651. }
  652. union reply_descriptor {
  653. u64 word;
  654. struct {
  655. u32 low;
  656. u32 high;
  657. } u;
  658. };
  659. /**
  660. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  661. * @irq: irq number (not used)
  662. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  663. * @r: pt_regs pointer (not used)
  664. *
  665. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  666. */
  667. static irqreturn_t
  668. _base_interrupt(int irq, void *bus_id)
  669. {
  670. union reply_descriptor rd;
  671. u32 completed_cmds;
  672. u8 request_desript_type;
  673. u16 smid;
  674. u8 cb_idx;
  675. u32 reply;
  676. u8 msix_index;
  677. struct MPT2SAS_ADAPTER *ioc = bus_id;
  678. Mpi2ReplyDescriptorsUnion_t *rpf;
  679. u8 rc;
  680. if (ioc->mask_interrupts)
  681. return IRQ_NONE;
  682. rpf = &ioc->reply_post_free[ioc->reply_post_host_index];
  683. request_desript_type = rpf->Default.ReplyFlags
  684. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  685. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  686. return IRQ_NONE;
  687. completed_cmds = 0;
  688. do {
  689. rd.word = rpf->Words;
  690. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  691. goto out;
  692. reply = 0;
  693. cb_idx = 0xFF;
  694. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  695. msix_index = rpf->Default.MSIxIndex;
  696. if (request_desript_type ==
  697. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  698. reply = le32_to_cpu
  699. (rpf->AddressReply.ReplyFrameAddress);
  700. } else if (request_desript_type ==
  701. MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
  702. goto next;
  703. else if (request_desript_type ==
  704. MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
  705. goto next;
  706. if (smid)
  707. cb_idx = _base_get_cb_idx(ioc, smid);
  708. if (smid && cb_idx != 0xFF) {
  709. rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
  710. reply);
  711. if (reply)
  712. _base_display_reply_info(ioc, smid, msix_index,
  713. reply);
  714. if (rc)
  715. mpt2sas_base_free_smid(ioc, smid);
  716. }
  717. if (!smid)
  718. _base_async_event(ioc, msix_index, reply);
  719. /* reply free queue handling */
  720. if (reply) {
  721. ioc->reply_free_host_index =
  722. (ioc->reply_free_host_index ==
  723. (ioc->reply_free_queue_depth - 1)) ?
  724. 0 : ioc->reply_free_host_index + 1;
  725. ioc->reply_free[ioc->reply_free_host_index] =
  726. cpu_to_le32(reply);
  727. wmb();
  728. writel(ioc->reply_free_host_index,
  729. &ioc->chip->ReplyFreeHostIndex);
  730. }
  731. next:
  732. rpf->Words = ULLONG_MAX;
  733. ioc->reply_post_host_index = (ioc->reply_post_host_index ==
  734. (ioc->reply_post_queue_depth - 1)) ? 0 :
  735. ioc->reply_post_host_index + 1;
  736. request_desript_type =
  737. ioc->reply_post_free[ioc->reply_post_host_index].Default.
  738. ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  739. completed_cmds++;
  740. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  741. goto out;
  742. if (!ioc->reply_post_host_index)
  743. rpf = ioc->reply_post_free;
  744. else
  745. rpf++;
  746. } while (1);
  747. out:
  748. if (!completed_cmds)
  749. return IRQ_NONE;
  750. wmb();
  751. writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex);
  752. return IRQ_HANDLED;
  753. }
  754. /**
  755. * mpt2sas_base_release_callback_handler - clear interupt callback handler
  756. * @cb_idx: callback index
  757. *
  758. * Return nothing.
  759. */
  760. void
  761. mpt2sas_base_release_callback_handler(u8 cb_idx)
  762. {
  763. mpt_callbacks[cb_idx] = NULL;
  764. }
  765. /**
  766. * mpt2sas_base_register_callback_handler - obtain index for the interrupt callback handler
  767. * @cb_func: callback function
  768. *
  769. * Returns cb_func.
  770. */
  771. u8
  772. mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  773. {
  774. u8 cb_idx;
  775. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  776. if (mpt_callbacks[cb_idx] == NULL)
  777. break;
  778. mpt_callbacks[cb_idx] = cb_func;
  779. return cb_idx;
  780. }
  781. /**
  782. * mpt2sas_base_initialize_callback_handler - initialize the interrupt callback handler
  783. *
  784. * Return nothing.
  785. */
  786. void
  787. mpt2sas_base_initialize_callback_handler(void)
  788. {
  789. u8 cb_idx;
  790. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  791. mpt2sas_base_release_callback_handler(cb_idx);
  792. }
  793. /**
  794. * mpt2sas_base_build_zero_len_sge - build zero length sg entry
  795. * @ioc: per adapter object
  796. * @paddr: virtual address for SGE
  797. *
  798. * Create a zero length scatter gather entry to insure the IOCs hardware has
  799. * something to use if the target device goes brain dead and tries
  800. * to send data even when none is asked for.
  801. *
  802. * Return nothing.
  803. */
  804. void
  805. mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
  806. {
  807. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  808. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  809. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  810. MPI2_SGE_FLAGS_SHIFT);
  811. ioc->base_add_sg_single(paddr, flags_length, -1);
  812. }
  813. /**
  814. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  815. * @paddr: virtual address for SGE
  816. * @flags_length: SGE flags and data transfer length
  817. * @dma_addr: Physical address
  818. *
  819. * Return nothing.
  820. */
  821. static void
  822. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  823. {
  824. Mpi2SGESimple32_t *sgel = paddr;
  825. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  826. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  827. sgel->FlagsLength = cpu_to_le32(flags_length);
  828. sgel->Address = cpu_to_le32(dma_addr);
  829. }
  830. /**
  831. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  832. * @paddr: virtual address for SGE
  833. * @flags_length: SGE flags and data transfer length
  834. * @dma_addr: Physical address
  835. *
  836. * Return nothing.
  837. */
  838. static void
  839. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  840. {
  841. Mpi2SGESimple64_t *sgel = paddr;
  842. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  843. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  844. sgel->FlagsLength = cpu_to_le32(flags_length);
  845. sgel->Address = cpu_to_le64(dma_addr);
  846. }
  847. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  848. /**
  849. * _base_config_dma_addressing - set dma addressing
  850. * @ioc: per adapter object
  851. * @pdev: PCI device struct
  852. *
  853. * Returns 0 for success, non-zero for failure.
  854. */
  855. static int
  856. _base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
  857. {
  858. struct sysinfo s;
  859. char *desc = NULL;
  860. if (sizeof(dma_addr_t) > 4) {
  861. const uint64_t required_mask =
  862. dma_get_required_mask(&pdev->dev);
  863. if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
  864. DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
  865. DMA_BIT_MASK(64))) {
  866. ioc->base_add_sg_single = &_base_add_sg_single_64;
  867. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  868. desc = "64";
  869. goto out;
  870. }
  871. }
  872. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  873. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  874. ioc->base_add_sg_single = &_base_add_sg_single_32;
  875. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  876. desc = "32";
  877. } else
  878. return -ENODEV;
  879. out:
  880. si_meminfo(&s);
  881. printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
  882. "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
  883. return 0;
  884. }
  885. /**
  886. * _base_save_msix_table - backup msix vector table
  887. * @ioc: per adapter object
  888. *
  889. * This address an errata where diag reset clears out the table
  890. */
  891. static void
  892. _base_save_msix_table(struct MPT2SAS_ADAPTER *ioc)
  893. {
  894. int i;
  895. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  896. return;
  897. for (i = 0; i < ioc->msix_vector_count; i++)
  898. ioc->msix_table_backup[i] = ioc->msix_table[i];
  899. }
  900. /**
  901. * _base_restore_msix_table - this restores the msix vector table
  902. * @ioc: per adapter object
  903. *
  904. */
  905. static void
  906. _base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc)
  907. {
  908. int i;
  909. if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
  910. return;
  911. for (i = 0; i < ioc->msix_vector_count; i++)
  912. ioc->msix_table[i] = ioc->msix_table_backup[i];
  913. }
  914. /**
  915. * _base_check_enable_msix - checks MSIX capabable.
  916. * @ioc: per adapter object
  917. *
  918. * Check to see if card is capable of MSIX, and set number
  919. * of avaliable msix vectors
  920. */
  921. static int
  922. _base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  923. {
  924. int base;
  925. u16 message_control;
  926. u32 msix_table_offset;
  927. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  928. if (!base) {
  929. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
  930. "supported\n", ioc->name));
  931. return -EINVAL;
  932. }
  933. /* get msix vector count */
  934. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  935. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  936. /* get msix table */
  937. pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset);
  938. msix_table_offset &= 0xFFFFFFF8;
  939. ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset);
  940. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
  941. "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name,
  942. ioc->msix_vector_count, msix_table_offset, ioc->msix_table));
  943. return 0;
  944. }
  945. /**
  946. * _base_disable_msix - disables msix
  947. * @ioc: per adapter object
  948. *
  949. */
  950. static void
  951. _base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
  952. {
  953. if (ioc->msix_enable) {
  954. pci_disable_msix(ioc->pdev);
  955. kfree(ioc->msix_table_backup);
  956. ioc->msix_table_backup = NULL;
  957. ioc->msix_enable = 0;
  958. }
  959. }
  960. /**
  961. * _base_enable_msix - enables msix, failback to io_apic
  962. * @ioc: per adapter object
  963. *
  964. */
  965. static int
  966. _base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  967. {
  968. struct msix_entry entries;
  969. int r;
  970. u8 try_msix = 0;
  971. if (msix_disable == -1 || msix_disable == 0)
  972. try_msix = 1;
  973. if (!try_msix)
  974. goto try_ioapic;
  975. if (_base_check_enable_msix(ioc) != 0)
  976. goto try_ioapic;
  977. ioc->msix_table_backup = kcalloc(ioc->msix_vector_count,
  978. sizeof(u32), GFP_KERNEL);
  979. if (!ioc->msix_table_backup) {
  980. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
  981. "msix_table_backup failed!!!\n", ioc->name));
  982. goto try_ioapic;
  983. }
  984. memset(&entries, 0, sizeof(struct msix_entry));
  985. r = pci_enable_msix(ioc->pdev, &entries, 1);
  986. if (r) {
  987. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
  988. "failed (r=%d) !!!\n", ioc->name, r));
  989. goto try_ioapic;
  990. }
  991. r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED,
  992. ioc->name, ioc);
  993. if (r) {
  994. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate "
  995. "interrupt %d !!!\n", ioc->name, entries.vector));
  996. pci_disable_msix(ioc->pdev);
  997. goto try_ioapic;
  998. }
  999. ioc->pci_irq = entries.vector;
  1000. ioc->msix_enable = 1;
  1001. return 0;
  1002. /* failback to io_apic interrupt routing */
  1003. try_ioapic:
  1004. r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED,
  1005. ioc->name, ioc);
  1006. if (r) {
  1007. printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
  1008. ioc->name, ioc->pdev->irq);
  1009. r = -EBUSY;
  1010. goto out_fail;
  1011. }
  1012. ioc->pci_irq = ioc->pdev->irq;
  1013. return 0;
  1014. out_fail:
  1015. return r;
  1016. }
  1017. /**
  1018. * mpt2sas_base_map_resources - map in controller resources (io/irq/memap)
  1019. * @ioc: per adapter object
  1020. *
  1021. * Returns 0 for success, non-zero for failure.
  1022. */
  1023. int
  1024. mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
  1025. {
  1026. struct pci_dev *pdev = ioc->pdev;
  1027. u32 memap_sz;
  1028. u32 pio_sz;
  1029. int i, r = 0;
  1030. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n",
  1031. ioc->name, __func__));
  1032. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1033. if (pci_enable_device_mem(pdev)) {
  1034. printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
  1035. "failed\n", ioc->name);
  1036. return -ENODEV;
  1037. }
  1038. if (pci_request_selected_regions(pdev, ioc->bars,
  1039. MPT2SAS_DRIVER_NAME)) {
  1040. printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
  1041. "failed\n", ioc->name);
  1042. r = -ENODEV;
  1043. goto out_fail;
  1044. }
  1045. pci_set_master(pdev);
  1046. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1047. printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
  1048. ioc->name, pci_name(pdev));
  1049. r = -ENODEV;
  1050. goto out_fail;
  1051. }
  1052. for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
  1053. if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO) {
  1054. if (pio_sz)
  1055. continue;
  1056. ioc->pio_chip = pci_resource_start(pdev, i);
  1057. pio_sz = pci_resource_len(pdev, i);
  1058. } else {
  1059. if (memap_sz)
  1060. continue;
  1061. ioc->chip_phys = pci_resource_start(pdev, i);
  1062. memap_sz = pci_resource_len(pdev, i);
  1063. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1064. if (ioc->chip == NULL) {
  1065. printk(MPT2SAS_ERR_FMT "unable to map adapter "
  1066. "memory!\n", ioc->name);
  1067. r = -EINVAL;
  1068. goto out_fail;
  1069. }
  1070. }
  1071. }
  1072. _base_mask_interrupts(ioc);
  1073. r = _base_enable_msix(ioc);
  1074. if (r)
  1075. goto out_fail;
  1076. printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
  1077. ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1078. "IO-APIC enabled"), ioc->pci_irq);
  1079. printk(MPT2SAS_INFO_FMT "iomem(0x%lx), mapped(0x%p), size(%d)\n",
  1080. ioc->name, ioc->chip_phys, ioc->chip, memap_sz);
  1081. printk(MPT2SAS_INFO_FMT "ioport(0x%lx), size(%d)\n",
  1082. ioc->name, ioc->pio_chip, pio_sz);
  1083. return 0;
  1084. out_fail:
  1085. if (ioc->chip_phys)
  1086. iounmap(ioc->chip);
  1087. ioc->chip_phys = 0;
  1088. ioc->pci_irq = -1;
  1089. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1090. pci_disable_device(pdev);
  1091. return r;
  1092. }
  1093. /**
  1094. * mpt2sas_base_get_msg_frame - obtain request mf pointer
  1095. * @ioc: per adapter object
  1096. * @smid: system request message index(smid zero is invalid)
  1097. *
  1098. * Returns virt pointer to message frame.
  1099. */
  1100. void *
  1101. mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1102. {
  1103. return (void *)(ioc->request + (smid * ioc->request_sz));
  1104. }
  1105. /**
  1106. * mpt2sas_base_get_sense_buffer - obtain a sense buffer assigned to a mf request
  1107. * @ioc: per adapter object
  1108. * @smid: system request message index
  1109. *
  1110. * Returns virt pointer to sense buffer.
  1111. */
  1112. void *
  1113. mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1114. {
  1115. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1116. }
  1117. /**
  1118. * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer assigned to a mf request
  1119. * @ioc: per adapter object
  1120. * @smid: system request message index
  1121. *
  1122. * Returns phys pointer to sense buffer.
  1123. */
  1124. dma_addr_t
  1125. mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1126. {
  1127. return ioc->sense_dma + ((smid - 1) * SCSI_SENSE_BUFFERSIZE);
  1128. }
  1129. /**
  1130. * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address
  1131. * @ioc: per adapter object
  1132. * @phys_addr: lower 32 physical addr of the reply
  1133. *
  1134. * Converts 32bit lower physical addr into a virt address.
  1135. */
  1136. void *
  1137. mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
  1138. {
  1139. if (!phys_addr)
  1140. return NULL;
  1141. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1142. }
  1143. /**
  1144. * mpt2sas_base_get_smid - obtain a free smid from internal queue
  1145. * @ioc: per adapter object
  1146. * @cb_idx: callback index
  1147. *
  1148. * Returns smid (zero is invalid)
  1149. */
  1150. u16
  1151. mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1152. {
  1153. unsigned long flags;
  1154. struct request_tracker *request;
  1155. u16 smid;
  1156. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1157. if (list_empty(&ioc->internal_free_list)) {
  1158. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1159. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1160. ioc->name, __func__);
  1161. return 0;
  1162. }
  1163. request = list_entry(ioc->internal_free_list.next,
  1164. struct request_tracker, tracker_list);
  1165. request->cb_idx = cb_idx;
  1166. smid = request->smid;
  1167. list_del(&request->tracker_list);
  1168. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1169. return smid;
  1170. }
  1171. /**
  1172. * mpt2sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1173. * @ioc: per adapter object
  1174. * @cb_idx: callback index
  1175. * @scmd: pointer to scsi command object
  1176. *
  1177. * Returns smid (zero is invalid)
  1178. */
  1179. u16
  1180. mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
  1181. struct scsi_cmnd *scmd)
  1182. {
  1183. unsigned long flags;
  1184. struct request_tracker *request;
  1185. u16 smid;
  1186. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1187. if (list_empty(&ioc->free_list)) {
  1188. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1189. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1190. ioc->name, __func__);
  1191. return 0;
  1192. }
  1193. request = list_entry(ioc->free_list.next,
  1194. struct request_tracker, tracker_list);
  1195. request->scmd = scmd;
  1196. request->cb_idx = cb_idx;
  1197. smid = request->smid;
  1198. list_del(&request->tracker_list);
  1199. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1200. return smid;
  1201. }
  1202. /**
  1203. * mpt2sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1204. * @ioc: per adapter object
  1205. * @cb_idx: callback index
  1206. *
  1207. * Returns smid (zero is invalid)
  1208. */
  1209. u16
  1210. mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1211. {
  1212. unsigned long flags;
  1213. struct request_tracker *request;
  1214. u16 smid;
  1215. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1216. if (list_empty(&ioc->hpr_free_list)) {
  1217. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1218. return 0;
  1219. }
  1220. request = list_entry(ioc->hpr_free_list.next,
  1221. struct request_tracker, tracker_list);
  1222. request->cb_idx = cb_idx;
  1223. smid = request->smid;
  1224. list_del(&request->tracker_list);
  1225. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1226. return smid;
  1227. }
  1228. /**
  1229. * mpt2sas_base_free_smid - put smid back on free_list
  1230. * @ioc: per adapter object
  1231. * @smid: system request message index
  1232. *
  1233. * Return nothing.
  1234. */
  1235. void
  1236. mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1237. {
  1238. unsigned long flags;
  1239. int i;
  1240. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1241. if (smid >= ioc->hi_priority_smid) {
  1242. if (smid < ioc->internal_smid) {
  1243. /* hi-priority */
  1244. i = smid - ioc->hi_priority_smid;
  1245. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1246. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  1247. &ioc->hpr_free_list);
  1248. } else {
  1249. /* internal queue */
  1250. i = smid - ioc->internal_smid;
  1251. ioc->internal_lookup[i].cb_idx = 0xFF;
  1252. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  1253. &ioc->internal_free_list);
  1254. }
  1255. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1256. return;
  1257. }
  1258. /* scsiio queue */
  1259. i = smid - 1;
  1260. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1261. ioc->scsi_lookup[i].scmd = NULL;
  1262. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  1263. &ioc->free_list);
  1264. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1265. /*
  1266. * See _wait_for_commands_to_complete() call with regards to this code.
  1267. */
  1268. if (ioc->shost_recovery && ioc->pending_io_count) {
  1269. if (ioc->pending_io_count == 1)
  1270. wake_up(&ioc->reset_wq);
  1271. ioc->pending_io_count--;
  1272. }
  1273. }
  1274. /**
  1275. * _base_writeq - 64 bit write to MMIO
  1276. * @ioc: per adapter object
  1277. * @b: data payload
  1278. * @addr: address in MMIO space
  1279. * @writeq_lock: spin lock
  1280. *
  1281. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1282. * care of 32 bit environment where its not quarenteed to send the entire word
  1283. * in one transfer.
  1284. */
  1285. #ifndef writeq
  1286. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1287. spinlock_t *writeq_lock)
  1288. {
  1289. unsigned long flags;
  1290. __u64 data_out = cpu_to_le64(b);
  1291. spin_lock_irqsave(writeq_lock, flags);
  1292. writel((u32)(data_out), addr);
  1293. writel((u32)(data_out >> 32), (addr + 4));
  1294. spin_unlock_irqrestore(writeq_lock, flags);
  1295. }
  1296. #else
  1297. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1298. spinlock_t *writeq_lock)
  1299. {
  1300. writeq(cpu_to_le64(b), addr);
  1301. }
  1302. #endif
  1303. /**
  1304. * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1305. * @ioc: per adapter object
  1306. * @smid: system request message index
  1307. * @handle: device handle
  1308. *
  1309. * Return nothing.
  1310. */
  1311. void
  1312. mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1313. {
  1314. Mpi2RequestDescriptorUnion_t descriptor;
  1315. u64 *request = (u64 *)&descriptor;
  1316. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1317. descriptor.SCSIIO.MSIxIndex = 0; /* TODO */
  1318. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1319. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1320. descriptor.SCSIIO.LMID = 0;
  1321. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1322. &ioc->scsi_lookup_lock);
  1323. }
  1324. /**
  1325. * mpt2sas_base_put_smid_hi_priority - send Task Managment request to firmware
  1326. * @ioc: per adapter object
  1327. * @smid: system request message index
  1328. *
  1329. * Return nothing.
  1330. */
  1331. void
  1332. mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1333. {
  1334. Mpi2RequestDescriptorUnion_t descriptor;
  1335. u64 *request = (u64 *)&descriptor;
  1336. descriptor.HighPriority.RequestFlags =
  1337. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1338. descriptor.HighPriority.MSIxIndex = 0; /* TODO */
  1339. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1340. descriptor.HighPriority.LMID = 0;
  1341. descriptor.HighPriority.Reserved1 = 0;
  1342. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1343. &ioc->scsi_lookup_lock);
  1344. }
  1345. /**
  1346. * mpt2sas_base_put_smid_default - Default, primarily used for config pages
  1347. * @ioc: per adapter object
  1348. * @smid: system request message index
  1349. *
  1350. * Return nothing.
  1351. */
  1352. void
  1353. mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1354. {
  1355. Mpi2RequestDescriptorUnion_t descriptor;
  1356. u64 *request = (u64 *)&descriptor;
  1357. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1358. descriptor.Default.MSIxIndex = 0; /* TODO */
  1359. descriptor.Default.SMID = cpu_to_le16(smid);
  1360. descriptor.Default.LMID = 0;
  1361. descriptor.Default.DescriptorTypeDependent = 0;
  1362. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1363. &ioc->scsi_lookup_lock);
  1364. }
  1365. /**
  1366. * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware
  1367. * @ioc: per adapter object
  1368. * @smid: system request message index
  1369. * @io_index: value used to track the IO
  1370. *
  1371. * Return nothing.
  1372. */
  1373. void
  1374. mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
  1375. u16 io_index)
  1376. {
  1377. Mpi2RequestDescriptorUnion_t descriptor;
  1378. u64 *request = (u64 *)&descriptor;
  1379. descriptor.SCSITarget.RequestFlags =
  1380. MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
  1381. descriptor.SCSITarget.MSIxIndex = 0; /* TODO */
  1382. descriptor.SCSITarget.SMID = cpu_to_le16(smid);
  1383. descriptor.SCSITarget.LMID = 0;
  1384. descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
  1385. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1386. &ioc->scsi_lookup_lock);
  1387. }
  1388. /**
  1389. * _base_display_dell_branding - Disply branding string
  1390. * @ioc: per adapter object
  1391. *
  1392. * Return nothing.
  1393. */
  1394. static void
  1395. _base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
  1396. {
  1397. char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
  1398. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
  1399. return;
  1400. memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
  1401. switch (ioc->pdev->subsystem_device) {
  1402. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  1403. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
  1404. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1405. break;
  1406. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  1407. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
  1408. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1409. break;
  1410. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  1411. strncpy(dell_branding,
  1412. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
  1413. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1414. break;
  1415. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  1416. strncpy(dell_branding,
  1417. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
  1418. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1419. break;
  1420. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  1421. strncpy(dell_branding,
  1422. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
  1423. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1424. break;
  1425. case MPT2SAS_DELL_PERC_H200_SSDID:
  1426. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
  1427. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1428. break;
  1429. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  1430. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
  1431. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1432. break;
  1433. default:
  1434. sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
  1435. break;
  1436. }
  1437. printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
  1438. " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
  1439. ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
  1440. ioc->pdev->subsystem_device);
  1441. }
  1442. /**
  1443. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1444. * @ioc: per adapter object
  1445. *
  1446. * Return nothing.
  1447. */
  1448. static void
  1449. _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
  1450. {
  1451. int i = 0;
  1452. char desc[16];
  1453. u8 revision;
  1454. u32 iounit_pg1_flags;
  1455. pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
  1456. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1457. printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
  1458. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  1459. ioc->name, desc,
  1460. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  1461. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  1462. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  1463. ioc->facts.FWVersion.Word & 0x000000FF,
  1464. revision,
  1465. (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24,
  1466. (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16,
  1467. (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
  1468. ioc->bios_pg3.BiosVersion & 0x000000FF);
  1469. _base_display_dell_branding(ioc);
  1470. printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
  1471. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  1472. printk("Initiator");
  1473. i++;
  1474. }
  1475. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  1476. printk("%sTarget", i ? "," : "");
  1477. i++;
  1478. }
  1479. i = 0;
  1480. printk("), ");
  1481. printk("Capabilities=(");
  1482. if (ioc->facts.IOCCapabilities &
  1483. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  1484. printk("Raid");
  1485. i++;
  1486. }
  1487. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  1488. printk("%sTLR", i ? "," : "");
  1489. i++;
  1490. }
  1491. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  1492. printk("%sMulticast", i ? "," : "");
  1493. i++;
  1494. }
  1495. if (ioc->facts.IOCCapabilities &
  1496. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  1497. printk("%sBIDI Target", i ? "," : "");
  1498. i++;
  1499. }
  1500. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  1501. printk("%sEEDP", i ? "," : "");
  1502. i++;
  1503. }
  1504. if (ioc->facts.IOCCapabilities &
  1505. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  1506. printk("%sSnapshot Buffer", i ? "," : "");
  1507. i++;
  1508. }
  1509. if (ioc->facts.IOCCapabilities &
  1510. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  1511. printk("%sDiag Trace Buffer", i ? "," : "");
  1512. i++;
  1513. }
  1514. if (ioc->facts.IOCCapabilities &
  1515. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  1516. printk("%sTask Set Full", i ? "," : "");
  1517. i++;
  1518. }
  1519. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1520. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  1521. printk("%sNCQ", i ? "," : "");
  1522. i++;
  1523. }
  1524. printk(")\n");
  1525. }
  1526. /**
  1527. * _base_static_config_pages - static start of day config pages
  1528. * @ioc: per adapter object
  1529. *
  1530. * Return nothing.
  1531. */
  1532. static void
  1533. _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
  1534. {
  1535. Mpi2ConfigReply_t mpi_reply;
  1536. u32 iounit_pg1_flags;
  1537. mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  1538. if (ioc->ir_firmware)
  1539. mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  1540. &ioc->manu_pg10);
  1541. mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  1542. mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  1543. mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  1544. mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  1545. mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1546. _base_display_ioc_capabilities(ioc);
  1547. /*
  1548. * Enable task_set_full handling in iounit_pg1 when the
  1549. * facts capabilities indicate that its supported.
  1550. */
  1551. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  1552. if ((ioc->facts.IOCCapabilities &
  1553. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  1554. iounit_pg1_flags &=
  1555. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1556. else
  1557. iounit_pg1_flags |=
  1558. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  1559. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  1560. mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  1561. }
  1562. /**
  1563. * _base_release_memory_pools - release memory
  1564. * @ioc: per adapter object
  1565. *
  1566. * Free memory allocated from _base_allocate_memory_pools.
  1567. *
  1568. * Return nothing.
  1569. */
  1570. static void
  1571. _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
  1572. {
  1573. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  1574. __func__));
  1575. if (ioc->request) {
  1576. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  1577. ioc->request, ioc->request_dma);
  1578. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
  1579. ": free\n", ioc->name, ioc->request));
  1580. ioc->request = NULL;
  1581. }
  1582. if (ioc->sense) {
  1583. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  1584. if (ioc->sense_dma_pool)
  1585. pci_pool_destroy(ioc->sense_dma_pool);
  1586. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
  1587. ": free\n", ioc->name, ioc->sense));
  1588. ioc->sense = NULL;
  1589. }
  1590. if (ioc->reply) {
  1591. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  1592. if (ioc->reply_dma_pool)
  1593. pci_pool_destroy(ioc->reply_dma_pool);
  1594. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
  1595. ": free\n", ioc->name, ioc->reply));
  1596. ioc->reply = NULL;
  1597. }
  1598. if (ioc->reply_free) {
  1599. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  1600. ioc->reply_free_dma);
  1601. if (ioc->reply_free_dma_pool)
  1602. pci_pool_destroy(ioc->reply_free_dma_pool);
  1603. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
  1604. "(0x%p): free\n", ioc->name, ioc->reply_free));
  1605. ioc->reply_free = NULL;
  1606. }
  1607. if (ioc->reply_post_free) {
  1608. pci_pool_free(ioc->reply_post_free_dma_pool,
  1609. ioc->reply_post_free, ioc->reply_post_free_dma);
  1610. if (ioc->reply_post_free_dma_pool)
  1611. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  1612. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1613. "reply_post_free_pool(0x%p): free\n", ioc->name,
  1614. ioc->reply_post_free));
  1615. ioc->reply_post_free = NULL;
  1616. }
  1617. if (ioc->config_page) {
  1618. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1619. "config_page(0x%p): free\n", ioc->name,
  1620. ioc->config_page));
  1621. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  1622. ioc->config_page, ioc->config_page_dma);
  1623. }
  1624. kfree(ioc->scsi_lookup);
  1625. kfree(ioc->hpr_lookup);
  1626. kfree(ioc->internal_lookup);
  1627. }
  1628. /**
  1629. * _base_allocate_memory_pools - allocate start of day memory pools
  1630. * @ioc: per adapter object
  1631. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  1632. *
  1633. * Returns 0 success, anything else error
  1634. */
  1635. static int
  1636. _base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  1637. {
  1638. Mpi2IOCFactsReply_t *facts;
  1639. u32 queue_size, queue_diff;
  1640. u16 max_sge_elements;
  1641. u16 num_of_reply_frames;
  1642. u16 chains_needed_per_io;
  1643. u32 sz, total_sz;
  1644. u32 retry_sz;
  1645. u16 max_request_credit;
  1646. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  1647. __func__));
  1648. retry_sz = 0;
  1649. facts = &ioc->facts;
  1650. /* command line tunables for max sgl entries */
  1651. if (max_sgl_entries != -1) {
  1652. ioc->shost->sg_tablesize = (max_sgl_entries <
  1653. MPT2SAS_SG_DEPTH) ? max_sgl_entries :
  1654. MPT2SAS_SG_DEPTH;
  1655. } else {
  1656. ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
  1657. }
  1658. /* command line tunables for max controller queue depth */
  1659. if (max_queue_depth != -1) {
  1660. max_request_credit = (max_queue_depth < facts->RequestCredit)
  1661. ? max_queue_depth : facts->RequestCredit;
  1662. } else {
  1663. max_request_credit = (facts->RequestCredit >
  1664. MPT2SAS_MAX_REQUEST_QUEUE) ? MPT2SAS_MAX_REQUEST_QUEUE :
  1665. facts->RequestCredit;
  1666. }
  1667. ioc->hba_queue_depth = max_request_credit;
  1668. ioc->hi_priority_depth = facts->HighPriorityCredit;
  1669. ioc->internal_depth = ioc->hi_priority_depth + 5;
  1670. /* request frame size */
  1671. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  1672. /* reply frame size */
  1673. ioc->reply_sz = facts->ReplyFrameSize * 4;
  1674. retry_allocation:
  1675. total_sz = 0;
  1676. /* calculate number of sg elements left over in the 1st frame */
  1677. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  1678. sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
  1679. ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
  1680. /* now do the same for a chain buffer */
  1681. max_sge_elements = ioc->request_sz - ioc->sge_size;
  1682. ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
  1683. ioc->chain_offset_value_for_main_message =
  1684. ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
  1685. (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
  1686. /*
  1687. * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  1688. */
  1689. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  1690. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  1691. + 1;
  1692. if (chains_needed_per_io > facts->MaxChainDepth) {
  1693. chains_needed_per_io = facts->MaxChainDepth;
  1694. ioc->shost->sg_tablesize = min_t(u16,
  1695. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  1696. * chains_needed_per_io), ioc->shost->sg_tablesize);
  1697. }
  1698. ioc->chains_needed_per_io = chains_needed_per_io;
  1699. /* reply free queue sizing - taking into account for events */
  1700. num_of_reply_frames = ioc->hba_queue_depth + 32;
  1701. /* number of replies frames can't be a multiple of 16 */
  1702. /* decrease number of reply frames by 1 */
  1703. if (!(num_of_reply_frames % 16))
  1704. num_of_reply_frames--;
  1705. /* calculate number of reply free queue entries
  1706. * (must be multiple of 16)
  1707. */
  1708. /* (we know reply_free_queue_depth is not a multiple of 16) */
  1709. queue_size = num_of_reply_frames;
  1710. queue_size += 16 - (queue_size % 16);
  1711. ioc->reply_free_queue_depth = queue_size;
  1712. /* reply descriptor post queue sizing */
  1713. /* this size should be the number of request frames + number of reply
  1714. * frames
  1715. */
  1716. queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
  1717. /* round up to 16 byte boundary */
  1718. if (queue_size % 16)
  1719. queue_size += 16 - (queue_size % 16);
  1720. /* check against IOC maximum reply post queue depth */
  1721. if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
  1722. queue_diff = queue_size -
  1723. facts->MaxReplyDescriptorPostQueueDepth;
  1724. /* round queue_diff up to multiple of 16 */
  1725. if (queue_diff % 16)
  1726. queue_diff += 16 - (queue_diff % 16);
  1727. /* adjust hba_queue_depth, reply_free_queue_depth,
  1728. * and queue_size
  1729. */
  1730. ioc->hba_queue_depth -= (queue_diff / 2);
  1731. ioc->reply_free_queue_depth -= (queue_diff / 2);
  1732. queue_size = facts->MaxReplyDescriptorPostQueueDepth;
  1733. }
  1734. ioc->reply_post_queue_depth = queue_size;
  1735. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
  1736. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  1737. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  1738. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  1739. ioc->chains_needed_per_io));
  1740. ioc->scsiio_depth = ioc->hba_queue_depth -
  1741. ioc->hi_priority_depth - ioc->internal_depth;
  1742. /* set the scsi host can_queue depth
  1743. * with some internal commands that could be outstanding
  1744. */
  1745. ioc->shost->can_queue = ioc->scsiio_depth - (2);
  1746. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
  1747. "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
  1748. /* contiguous pool for request and chains, 16 byte align, one extra "
  1749. * "frame for smid=0
  1750. */
  1751. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  1752. sz = ((ioc->scsiio_depth + 1 + ioc->chain_depth) * ioc->request_sz);
  1753. /* hi-priority queue */
  1754. sz += (ioc->hi_priority_depth * ioc->request_sz);
  1755. /* internal queue */
  1756. sz += (ioc->internal_depth * ioc->request_sz);
  1757. ioc->request_dma_sz = sz;
  1758. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  1759. if (!ioc->request) {
  1760. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1761. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1762. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  1763. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1764. if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
  1765. goto out;
  1766. retry_sz += 64;
  1767. ioc->hba_queue_depth = max_request_credit - retry_sz;
  1768. goto retry_allocation;
  1769. }
  1770. if (retry_sz)
  1771. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  1772. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  1773. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  1774. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  1775. /* hi-priority queue */
  1776. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  1777. ioc->request_sz);
  1778. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  1779. ioc->request_sz);
  1780. /* internal queue */
  1781. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  1782. ioc->request_sz);
  1783. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  1784. ioc->request_sz);
  1785. ioc->chain = ioc->internal + (ioc->internal_depth *
  1786. ioc->request_sz);
  1787. ioc->chain_dma = ioc->internal_dma + (ioc->internal_depth *
  1788. ioc->request_sz);
  1789. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
  1790. "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  1791. ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  1792. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  1793. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool(0x%p): depth"
  1794. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->chain,
  1795. ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
  1796. ioc->request_sz))/1024));
  1797. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
  1798. ioc->name, (unsigned long long) ioc->request_dma));
  1799. total_sz += sz;
  1800. ioc->scsi_lookup = kcalloc(ioc->scsiio_depth,
  1801. sizeof(struct request_tracker), GFP_KERNEL);
  1802. if (!ioc->scsi_lookup) {
  1803. printk(MPT2SAS_ERR_FMT "scsi_lookup: kcalloc failed\n",
  1804. ioc->name);
  1805. goto out;
  1806. }
  1807. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
  1808. "depth(%d)\n", ioc->name, ioc->request,
  1809. ioc->scsiio_depth));
  1810. /* initialize hi-priority queue smid's */
  1811. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  1812. sizeof(struct request_tracker), GFP_KERNEL);
  1813. if (!ioc->hpr_lookup) {
  1814. printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
  1815. ioc->name);
  1816. goto out;
  1817. }
  1818. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  1819. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
  1820. "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
  1821. ioc->hi_priority_depth, ioc->hi_priority_smid));
  1822. /* initialize internal queue smid's */
  1823. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  1824. sizeof(struct request_tracker), GFP_KERNEL);
  1825. if (!ioc->internal_lookup) {
  1826. printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
  1827. ioc->name);
  1828. goto out;
  1829. }
  1830. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  1831. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
  1832. "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
  1833. ioc->internal_depth, ioc->internal_smid));
  1834. /* sense buffers, 4 byte align */
  1835. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  1836. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  1837. 0);
  1838. if (!ioc->sense_dma_pool) {
  1839. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
  1840. ioc->name);
  1841. goto out;
  1842. }
  1843. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  1844. &ioc->sense_dma);
  1845. if (!ioc->sense) {
  1846. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
  1847. ioc->name);
  1848. goto out;
  1849. }
  1850. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  1851. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  1852. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  1853. SCSI_SENSE_BUFFERSIZE, sz/1024));
  1854. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
  1855. ioc->name, (unsigned long long)ioc->sense_dma));
  1856. total_sz += sz;
  1857. /* reply pool, 4 byte align */
  1858. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  1859. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  1860. 0);
  1861. if (!ioc->reply_dma_pool) {
  1862. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
  1863. ioc->name);
  1864. goto out;
  1865. }
  1866. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  1867. &ioc->reply_dma);
  1868. if (!ioc->reply) {
  1869. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
  1870. ioc->name);
  1871. goto out;
  1872. }
  1873. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
  1874. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
  1875. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  1876. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
  1877. ioc->name, (unsigned long long)ioc->reply_dma));
  1878. total_sz += sz;
  1879. /* reply free queue, 16 byte align */
  1880. sz = ioc->reply_free_queue_depth * 4;
  1881. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  1882. ioc->pdev, sz, 16, 0);
  1883. if (!ioc->reply_free_dma_pool) {
  1884. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
  1885. "failed\n", ioc->name);
  1886. goto out;
  1887. }
  1888. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  1889. &ioc->reply_free_dma);
  1890. if (!ioc->reply_free) {
  1891. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
  1892. "failed\n", ioc->name);
  1893. goto out;
  1894. }
  1895. memset(ioc->reply_free, 0, sz);
  1896. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
  1897. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  1898. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  1899. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
  1900. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
  1901. total_sz += sz;
  1902. /* reply post queue, 16 byte align */
  1903. sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t);
  1904. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  1905. ioc->pdev, sz, 16, 0);
  1906. if (!ioc->reply_post_free_dma_pool) {
  1907. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
  1908. "failed\n", ioc->name);
  1909. goto out;
  1910. }
  1911. ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
  1912. GFP_KERNEL, &ioc->reply_post_free_dma);
  1913. if (!ioc->reply_post_free) {
  1914. printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
  1915. "failed\n", ioc->name);
  1916. goto out;
  1917. }
  1918. memset(ioc->reply_post_free, 0, sz);
  1919. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
  1920. "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
  1921. ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
  1922. sz/1024));
  1923. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
  1924. "(0x%llx)\n", ioc->name, (unsigned long long)
  1925. ioc->reply_post_free_dma));
  1926. total_sz += sz;
  1927. ioc->config_page_sz = 512;
  1928. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  1929. ioc->config_page_sz, &ioc->config_page_dma);
  1930. if (!ioc->config_page) {
  1931. printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
  1932. "failed\n", ioc->name);
  1933. goto out;
  1934. }
  1935. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
  1936. "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
  1937. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
  1938. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
  1939. total_sz += ioc->config_page_sz;
  1940. printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
  1941. ioc->name, total_sz/1024);
  1942. printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
  1943. "Max Controller Queue Depth(%d)\n",
  1944. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  1945. printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
  1946. ioc->name, ioc->shost->sg_tablesize);
  1947. return 0;
  1948. out:
  1949. _base_release_memory_pools(ioc);
  1950. return -ENOMEM;
  1951. }
  1952. /**
  1953. * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter.
  1954. * @ioc: Pointer to MPT_ADAPTER structure
  1955. * @cooked: Request raw or cooked IOC state
  1956. *
  1957. * Returns all IOC Doorbell register bits if cooked==0, else just the
  1958. * Doorbell bits in MPI_IOC_STATE_MASK.
  1959. */
  1960. u32
  1961. mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
  1962. {
  1963. u32 s, sc;
  1964. s = readl(&ioc->chip->Doorbell);
  1965. sc = s & MPI2_IOC_STATE_MASK;
  1966. return cooked ? sc : s;
  1967. }
  1968. /**
  1969. * _base_wait_on_iocstate - waiting on a particular ioc state
  1970. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  1971. * @timeout: timeout in second
  1972. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  1973. *
  1974. * Returns 0 for success, non-zero for failure.
  1975. */
  1976. static int
  1977. _base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  1978. int sleep_flag)
  1979. {
  1980. u32 count, cntdn;
  1981. u32 current_state;
  1982. count = 0;
  1983. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  1984. do {
  1985. current_state = mpt2sas_base_get_iocstate(ioc, 1);
  1986. if (current_state == ioc_state)
  1987. return 0;
  1988. if (count && current_state == MPI2_IOC_STATE_FAULT)
  1989. break;
  1990. if (sleep_flag == CAN_SLEEP)
  1991. msleep(1);
  1992. else
  1993. udelay(500);
  1994. count++;
  1995. } while (--cntdn);
  1996. return current_state;
  1997. }
  1998. /**
  1999. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2000. * a write to the doorbell)
  2001. * @ioc: per adapter object
  2002. * @timeout: timeout in second
  2003. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2004. *
  2005. * Returns 0 for success, non-zero for failure.
  2006. *
  2007. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2008. */
  2009. static int
  2010. _base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2011. int sleep_flag)
  2012. {
  2013. u32 cntdn, count;
  2014. u32 int_status;
  2015. count = 0;
  2016. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2017. do {
  2018. int_status = readl(&ioc->chip->HostInterruptStatus);
  2019. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2020. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2021. "successfull count(%d), timeout(%d)\n", ioc->name,
  2022. __func__, count, timeout));
  2023. return 0;
  2024. }
  2025. if (sleep_flag == CAN_SLEEP)
  2026. msleep(1);
  2027. else
  2028. udelay(500);
  2029. count++;
  2030. } while (--cntdn);
  2031. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2032. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2033. return -EFAULT;
  2034. }
  2035. /**
  2036. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2037. * @ioc: per adapter object
  2038. * @timeout: timeout in second
  2039. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2040. *
  2041. * Returns 0 for success, non-zero for failure.
  2042. *
  2043. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2044. * doorbell.
  2045. */
  2046. static int
  2047. _base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2048. int sleep_flag)
  2049. {
  2050. u32 cntdn, count;
  2051. u32 int_status;
  2052. u32 doorbell;
  2053. count = 0;
  2054. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2055. do {
  2056. int_status = readl(&ioc->chip->HostInterruptStatus);
  2057. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2058. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2059. "successfull count(%d), timeout(%d)\n", ioc->name,
  2060. __func__, count, timeout));
  2061. return 0;
  2062. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2063. doorbell = readl(&ioc->chip->Doorbell);
  2064. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2065. MPI2_IOC_STATE_FAULT) {
  2066. mpt2sas_base_fault_info(ioc , doorbell);
  2067. return -EFAULT;
  2068. }
  2069. } else if (int_status == 0xFFFFFFFF)
  2070. goto out;
  2071. if (sleep_flag == CAN_SLEEP)
  2072. msleep(1);
  2073. else
  2074. udelay(500);
  2075. count++;
  2076. } while (--cntdn);
  2077. out:
  2078. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2079. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2080. return -EFAULT;
  2081. }
  2082. /**
  2083. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2084. * @ioc: per adapter object
  2085. * @timeout: timeout in second
  2086. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2087. *
  2088. * Returns 0 for success, non-zero for failure.
  2089. *
  2090. */
  2091. static int
  2092. _base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2093. int sleep_flag)
  2094. {
  2095. u32 cntdn, count;
  2096. u32 doorbell_reg;
  2097. count = 0;
  2098. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2099. do {
  2100. doorbell_reg = readl(&ioc->chip->Doorbell);
  2101. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2102. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  2103. "successfull count(%d), timeout(%d)\n", ioc->name,
  2104. __func__, count, timeout));
  2105. return 0;
  2106. }
  2107. if (sleep_flag == CAN_SLEEP)
  2108. msleep(1);
  2109. else
  2110. udelay(500);
  2111. count++;
  2112. } while (--cntdn);
  2113. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2114. "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
  2115. return -EFAULT;
  2116. }
  2117. /**
  2118. * _base_send_ioc_reset - send doorbell reset
  2119. * @ioc: per adapter object
  2120. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2121. * @timeout: timeout in second
  2122. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2123. *
  2124. * Returns 0 for success, non-zero for failure.
  2125. */
  2126. static int
  2127. _base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2128. int sleep_flag)
  2129. {
  2130. u32 ioc_state;
  2131. int r = 0;
  2132. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2133. printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
  2134. ioc->name, __func__);
  2135. return -EFAULT;
  2136. }
  2137. if (!(ioc->facts.IOCCapabilities &
  2138. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2139. return -EFAULT;
  2140. printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
  2141. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2142. &ioc->chip->Doorbell);
  2143. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2144. r = -EFAULT;
  2145. goto out;
  2146. }
  2147. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2148. timeout, sleep_flag);
  2149. if (ioc_state) {
  2150. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2151. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2152. r = -EFAULT;
  2153. goto out;
  2154. }
  2155. out:
  2156. printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
  2157. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2158. return r;
  2159. }
  2160. /**
  2161. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2162. * @ioc: per adapter object
  2163. * @request_bytes: request length
  2164. * @request: pointer having request payload
  2165. * @reply_bytes: reply length
  2166. * @reply: pointer to reply payload
  2167. * @timeout: timeout in second
  2168. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2169. *
  2170. * Returns 0 for success, non-zero for failure.
  2171. */
  2172. static int
  2173. _base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
  2174. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2175. {
  2176. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2177. int i;
  2178. u8 failed;
  2179. u16 dummy;
  2180. u32 *mfp;
  2181. /* make sure doorbell is not in use */
  2182. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2183. printk(MPT2SAS_ERR_FMT "doorbell is in use "
  2184. " (line=%d)\n", ioc->name, __LINE__);
  2185. return -EFAULT;
  2186. }
  2187. /* clear pending doorbell interrupts from previous state changes */
  2188. if (readl(&ioc->chip->HostInterruptStatus) &
  2189. MPI2_HIS_IOC2SYS_DB_STATUS)
  2190. writel(0, &ioc->chip->HostInterruptStatus);
  2191. /* send message to ioc */
  2192. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2193. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2194. &ioc->chip->Doorbell);
  2195. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2196. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2197. "int failed (line=%d)\n", ioc->name, __LINE__);
  2198. return -EFAULT;
  2199. }
  2200. writel(0, &ioc->chip->HostInterruptStatus);
  2201. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2202. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2203. "ack failed (line=%d)\n", ioc->name, __LINE__);
  2204. return -EFAULT;
  2205. }
  2206. /* send message 32-bits at a time */
  2207. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2208. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2209. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2210. failed = 1;
  2211. }
  2212. if (failed) {
  2213. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2214. "sending request failed (line=%d)\n", ioc->name, __LINE__);
  2215. return -EFAULT;
  2216. }
  2217. /* now wait for the reply */
  2218. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2219. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2220. "int failed (line=%d)\n", ioc->name, __LINE__);
  2221. return -EFAULT;
  2222. }
  2223. /* read the first two 16-bits, it gives the total length of the reply */
  2224. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2225. & MPI2_DOORBELL_DATA_MASK);
  2226. writel(0, &ioc->chip->HostInterruptStatus);
  2227. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2228. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2229. "int failed (line=%d)\n", ioc->name, __LINE__);
  2230. return -EFAULT;
  2231. }
  2232. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2233. & MPI2_DOORBELL_DATA_MASK);
  2234. writel(0, &ioc->chip->HostInterruptStatus);
  2235. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2236. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2237. printk(MPT2SAS_ERR_FMT "doorbell "
  2238. "handshake int failed (line=%d)\n", ioc->name,
  2239. __LINE__);
  2240. return -EFAULT;
  2241. }
  2242. if (i >= reply_bytes/2) /* overflow case */
  2243. dummy = readl(&ioc->chip->Doorbell);
  2244. else
  2245. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2246. & MPI2_DOORBELL_DATA_MASK);
  2247. writel(0, &ioc->chip->HostInterruptStatus);
  2248. }
  2249. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2250. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2251. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
  2252. " (line=%d)\n", ioc->name, __LINE__));
  2253. }
  2254. writel(0, &ioc->chip->HostInterruptStatus);
  2255. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2256. mfp = (u32 *)reply;
  2257. printk(KERN_DEBUG "\toffset:data\n");
  2258. for (i = 0; i < reply_bytes/4; i++)
  2259. printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
  2260. le32_to_cpu(mfp[i]));
  2261. }
  2262. return 0;
  2263. }
  2264. /**
  2265. * mpt2sas_base_sas_iounit_control - send sas iounit control to FW
  2266. * @ioc: per adapter object
  2267. * @mpi_reply: the reply payload from FW
  2268. * @mpi_request: the request payload sent to FW
  2269. *
  2270. * The SAS IO Unit Control Request message allows the host to perform low-level
  2271. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2272. * to obtain the IOC assigned device handles for a device if it has other
  2273. * identifying information about the device, in addition allows the host to
  2274. * remove IOC resources associated with the device.
  2275. *
  2276. * Returns 0 for success, non-zero for failure.
  2277. */
  2278. int
  2279. mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
  2280. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2281. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2282. {
  2283. u16 smid;
  2284. u32 ioc_state;
  2285. unsigned long timeleft;
  2286. u8 issue_reset;
  2287. int rc;
  2288. void *request;
  2289. u16 wait_state_count;
  2290. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2291. __func__));
  2292. mutex_lock(&ioc->base_cmds.mutex);
  2293. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2294. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2295. ioc->name, __func__);
  2296. rc = -EAGAIN;
  2297. goto out;
  2298. }
  2299. wait_state_count = 0;
  2300. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2301. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2302. if (wait_state_count++ == 10) {
  2303. printk(MPT2SAS_ERR_FMT
  2304. "%s: failed due to ioc not operational\n",
  2305. ioc->name, __func__);
  2306. rc = -EFAULT;
  2307. goto out;
  2308. }
  2309. ssleep(1);
  2310. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2311. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2312. "operational state(count=%d)\n", ioc->name,
  2313. __func__, wait_state_count);
  2314. }
  2315. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2316. if (!smid) {
  2317. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2318. ioc->name, __func__);
  2319. rc = -EAGAIN;
  2320. goto out;
  2321. }
  2322. rc = 0;
  2323. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2324. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2325. ioc->base_cmds.smid = smid;
  2326. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  2327. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2328. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  2329. ioc->ioc_link_reset_in_progress = 1;
  2330. mpt2sas_base_put_smid_default(ioc, smid);
  2331. init_completion(&ioc->base_cmds.done);
  2332. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2333. msecs_to_jiffies(10000));
  2334. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2335. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  2336. ioc->ioc_link_reset_in_progress)
  2337. ioc->ioc_link_reset_in_progress = 0;
  2338. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2339. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2340. ioc->name, __func__);
  2341. _debug_dump_mf(mpi_request,
  2342. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  2343. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2344. issue_reset = 1;
  2345. goto issue_host_reset;
  2346. }
  2347. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2348. memcpy(mpi_reply, ioc->base_cmds.reply,
  2349. sizeof(Mpi2SasIoUnitControlReply_t));
  2350. else
  2351. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  2352. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2353. goto out;
  2354. issue_host_reset:
  2355. if (issue_reset)
  2356. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2357. FORCE_BIG_HAMMER);
  2358. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2359. rc = -EFAULT;
  2360. out:
  2361. mutex_unlock(&ioc->base_cmds.mutex);
  2362. return rc;
  2363. }
  2364. /**
  2365. * mpt2sas_base_scsi_enclosure_processor - sending request to sep device
  2366. * @ioc: per adapter object
  2367. * @mpi_reply: the reply payload from FW
  2368. * @mpi_request: the request payload sent to FW
  2369. *
  2370. * The SCSI Enclosure Processor request message causes the IOC to
  2371. * communicate with SES devices to control LED status signals.
  2372. *
  2373. * Returns 0 for success, non-zero for failure.
  2374. */
  2375. int
  2376. mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
  2377. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  2378. {
  2379. u16 smid;
  2380. u32 ioc_state;
  2381. unsigned long timeleft;
  2382. u8 issue_reset;
  2383. int rc;
  2384. void *request;
  2385. u16 wait_state_count;
  2386. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2387. __func__));
  2388. mutex_lock(&ioc->base_cmds.mutex);
  2389. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2390. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2391. ioc->name, __func__);
  2392. rc = -EAGAIN;
  2393. goto out;
  2394. }
  2395. wait_state_count = 0;
  2396. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2397. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2398. if (wait_state_count++ == 10) {
  2399. printk(MPT2SAS_ERR_FMT
  2400. "%s: failed due to ioc not operational\n",
  2401. ioc->name, __func__);
  2402. rc = -EFAULT;
  2403. goto out;
  2404. }
  2405. ssleep(1);
  2406. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2407. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2408. "operational state(count=%d)\n", ioc->name,
  2409. __func__, wait_state_count);
  2410. }
  2411. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2412. if (!smid) {
  2413. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2414. ioc->name, __func__);
  2415. rc = -EAGAIN;
  2416. goto out;
  2417. }
  2418. rc = 0;
  2419. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2420. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2421. ioc->base_cmds.smid = smid;
  2422. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  2423. mpt2sas_base_put_smid_default(ioc, smid);
  2424. init_completion(&ioc->base_cmds.done);
  2425. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2426. msecs_to_jiffies(10000));
  2427. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2428. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2429. ioc->name, __func__);
  2430. _debug_dump_mf(mpi_request,
  2431. sizeof(Mpi2SepRequest_t)/4);
  2432. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2433. issue_reset = 1;
  2434. goto issue_host_reset;
  2435. }
  2436. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2437. memcpy(mpi_reply, ioc->base_cmds.reply,
  2438. sizeof(Mpi2SepReply_t));
  2439. else
  2440. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  2441. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2442. goto out;
  2443. issue_host_reset:
  2444. if (issue_reset)
  2445. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2446. FORCE_BIG_HAMMER);
  2447. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2448. rc = -EFAULT;
  2449. out:
  2450. mutex_unlock(&ioc->base_cmds.mutex);
  2451. return rc;
  2452. }
  2453. /**
  2454. * _base_get_port_facts - obtain port facts reply and save in ioc
  2455. * @ioc: per adapter object
  2456. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2457. *
  2458. * Returns 0 for success, non-zero for failure.
  2459. */
  2460. static int
  2461. _base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
  2462. {
  2463. Mpi2PortFactsRequest_t mpi_request;
  2464. Mpi2PortFactsReply_t mpi_reply, *pfacts;
  2465. int mpi_reply_sz, mpi_request_sz, r;
  2466. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2467. __func__));
  2468. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  2469. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  2470. memset(&mpi_request, 0, mpi_request_sz);
  2471. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  2472. mpi_request.PortNumber = port;
  2473. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2474. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2475. if (r != 0) {
  2476. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2477. ioc->name, __func__, r);
  2478. return r;
  2479. }
  2480. pfacts = &ioc->pfacts[port];
  2481. memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
  2482. pfacts->PortNumber = mpi_reply.PortNumber;
  2483. pfacts->VP_ID = mpi_reply.VP_ID;
  2484. pfacts->VF_ID = mpi_reply.VF_ID;
  2485. pfacts->MaxPostedCmdBuffers =
  2486. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  2487. return 0;
  2488. }
  2489. /**
  2490. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  2491. * @ioc: per adapter object
  2492. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2493. *
  2494. * Returns 0 for success, non-zero for failure.
  2495. */
  2496. static int
  2497. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2498. {
  2499. Mpi2IOCFactsRequest_t mpi_request;
  2500. Mpi2IOCFactsReply_t mpi_reply, *facts;
  2501. int mpi_reply_sz, mpi_request_sz, r;
  2502. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2503. __func__));
  2504. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  2505. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  2506. memset(&mpi_request, 0, mpi_request_sz);
  2507. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  2508. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  2509. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  2510. if (r != 0) {
  2511. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2512. ioc->name, __func__, r);
  2513. return r;
  2514. }
  2515. facts = &ioc->facts;
  2516. memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
  2517. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  2518. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  2519. facts->VP_ID = mpi_reply.VP_ID;
  2520. facts->VF_ID = mpi_reply.VF_ID;
  2521. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  2522. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  2523. facts->WhoInit = mpi_reply.WhoInit;
  2524. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  2525. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  2526. facts->MaxReplyDescriptorPostQueueDepth =
  2527. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  2528. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  2529. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  2530. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  2531. ioc->ir_firmware = 1;
  2532. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  2533. facts->IOCRequestFrameSize =
  2534. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  2535. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  2536. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  2537. ioc->shost->max_id = -1;
  2538. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  2539. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  2540. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  2541. facts->HighPriorityCredit =
  2542. le16_to_cpu(mpi_reply.HighPriorityCredit);
  2543. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  2544. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  2545. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
  2546. "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
  2547. facts->MaxChainDepth));
  2548. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
  2549. "reply frame size(%d)\n", ioc->name,
  2550. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  2551. return 0;
  2552. }
  2553. /**
  2554. * _base_send_ioc_init - send ioc_init to firmware
  2555. * @ioc: per adapter object
  2556. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2557. *
  2558. * Returns 0 for success, non-zero for failure.
  2559. */
  2560. static int
  2561. _base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2562. {
  2563. Mpi2IOCInitRequest_t mpi_request;
  2564. Mpi2IOCInitReply_t mpi_reply;
  2565. int r;
  2566. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2567. __func__));
  2568. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  2569. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  2570. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  2571. mpi_request.VF_ID = 0; /* TODO */
  2572. mpi_request.VP_ID = 0;
  2573. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  2574. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  2575. /* In MPI Revision I (0xA), the SystemReplyFrameSize(offset 0x18) was
  2576. * removed and made reserved. For those with older firmware will need
  2577. * this fix. It was decided that the Reply and Request frame sizes are
  2578. * the same.
  2579. */
  2580. if ((ioc->facts.HeaderVersion >> 8) < 0xA) {
  2581. mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz);
  2582. /* mpi_request.SystemReplyFrameSize =
  2583. * cpu_to_le16(ioc->reply_sz);
  2584. */
  2585. }
  2586. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  2587. mpi_request.ReplyDescriptorPostQueueDepth =
  2588. cpu_to_le16(ioc->reply_post_queue_depth);
  2589. mpi_request.ReplyFreeQueueDepth =
  2590. cpu_to_le16(ioc->reply_free_queue_depth);
  2591. #if BITS_PER_LONG > 32
  2592. mpi_request.SenseBufferAddressHigh =
  2593. cpu_to_le32(ioc->sense_dma >> 32);
  2594. mpi_request.SystemReplyAddressHigh =
  2595. cpu_to_le32(ioc->reply_dma >> 32);
  2596. mpi_request.SystemRequestFrameBaseAddress =
  2597. cpu_to_le64(ioc->request_dma);
  2598. mpi_request.ReplyFreeQueueAddress =
  2599. cpu_to_le64(ioc->reply_free_dma);
  2600. mpi_request.ReplyDescriptorPostQueueAddress =
  2601. cpu_to_le64(ioc->reply_post_free_dma);
  2602. #else
  2603. mpi_request.SystemRequestFrameBaseAddress =
  2604. cpu_to_le32(ioc->request_dma);
  2605. mpi_request.ReplyFreeQueueAddress =
  2606. cpu_to_le32(ioc->reply_free_dma);
  2607. mpi_request.ReplyDescriptorPostQueueAddress =
  2608. cpu_to_le32(ioc->reply_post_free_dma);
  2609. #endif
  2610. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2611. u32 *mfp;
  2612. int i;
  2613. mfp = (u32 *)&mpi_request;
  2614. printk(KERN_DEBUG "\toffset:data\n");
  2615. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  2616. printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
  2617. le32_to_cpu(mfp[i]));
  2618. }
  2619. r = _base_handshake_req_reply_wait(ioc,
  2620. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  2621. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  2622. sleep_flag);
  2623. if (r != 0) {
  2624. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  2625. ioc->name, __func__, r);
  2626. return r;
  2627. }
  2628. if (mpi_reply.IOCStatus != MPI2_IOCSTATUS_SUCCESS ||
  2629. mpi_reply.IOCLogInfo) {
  2630. printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
  2631. r = -EIO;
  2632. }
  2633. return 0;
  2634. }
  2635. /**
  2636. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  2637. * @ioc: per adapter object
  2638. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2639. *
  2640. * Returns 0 for success, non-zero for failure.
  2641. */
  2642. static int
  2643. _base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2644. {
  2645. Mpi2PortEnableRequest_t *mpi_request;
  2646. u32 ioc_state;
  2647. unsigned long timeleft;
  2648. int r = 0;
  2649. u16 smid;
  2650. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  2651. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2652. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2653. ioc->name, __func__);
  2654. return -EAGAIN;
  2655. }
  2656. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2657. if (!smid) {
  2658. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2659. ioc->name, __func__);
  2660. return -EAGAIN;
  2661. }
  2662. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2663. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2664. ioc->base_cmds.smid = smid;
  2665. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  2666. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  2667. mpi_request->VF_ID = 0; /* TODO */
  2668. mpi_request->VP_ID = 0;
  2669. mpt2sas_base_put_smid_default(ioc, smid);
  2670. init_completion(&ioc->base_cmds.done);
  2671. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2672. 300*HZ);
  2673. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2674. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2675. ioc->name, __func__);
  2676. _debug_dump_mf(mpi_request,
  2677. sizeof(Mpi2PortEnableRequest_t)/4);
  2678. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2679. r = -EFAULT;
  2680. else
  2681. r = -ETIME;
  2682. goto out;
  2683. } else
  2684. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
  2685. ioc->name, __func__));
  2686. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL,
  2687. 60, sleep_flag);
  2688. if (ioc_state) {
  2689. printk(MPT2SAS_ERR_FMT "%s: failed going to operational state "
  2690. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2691. r = -EFAULT;
  2692. }
  2693. out:
  2694. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2695. printk(MPT2SAS_INFO_FMT "port enable: %s\n",
  2696. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2697. return r;
  2698. }
  2699. /**
  2700. * _base_unmask_events - turn on notification for this event
  2701. * @ioc: per adapter object
  2702. * @event: firmware event
  2703. *
  2704. * The mask is stored in ioc->event_masks.
  2705. */
  2706. static void
  2707. _base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
  2708. {
  2709. u32 desired_event;
  2710. if (event >= 128)
  2711. return;
  2712. desired_event = (1 << (event % 32));
  2713. if (event < 32)
  2714. ioc->event_masks[0] &= ~desired_event;
  2715. else if (event < 64)
  2716. ioc->event_masks[1] &= ~desired_event;
  2717. else if (event < 96)
  2718. ioc->event_masks[2] &= ~desired_event;
  2719. else if (event < 128)
  2720. ioc->event_masks[3] &= ~desired_event;
  2721. }
  2722. /**
  2723. * _base_event_notification - send event notification
  2724. * @ioc: per adapter object
  2725. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2726. *
  2727. * Returns 0 for success, non-zero for failure.
  2728. */
  2729. static int
  2730. _base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2731. {
  2732. Mpi2EventNotificationRequest_t *mpi_request;
  2733. unsigned long timeleft;
  2734. u16 smid;
  2735. int r = 0;
  2736. int i;
  2737. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2738. __func__));
  2739. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  2740. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  2741. ioc->name, __func__);
  2742. return -EAGAIN;
  2743. }
  2744. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2745. if (!smid) {
  2746. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2747. ioc->name, __func__);
  2748. return -EAGAIN;
  2749. }
  2750. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2751. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  2752. ioc->base_cmds.smid = smid;
  2753. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  2754. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  2755. mpi_request->VF_ID = 0; /* TODO */
  2756. mpi_request->VP_ID = 0;
  2757. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  2758. mpi_request->EventMasks[i] =
  2759. le32_to_cpu(ioc->event_masks[i]);
  2760. mpt2sas_base_put_smid_default(ioc, smid);
  2761. init_completion(&ioc->base_cmds.done);
  2762. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  2763. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2764. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2765. ioc->name, __func__);
  2766. _debug_dump_mf(mpi_request,
  2767. sizeof(Mpi2EventNotificationRequest_t)/4);
  2768. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  2769. r = -EFAULT;
  2770. else
  2771. r = -ETIME;
  2772. } else
  2773. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
  2774. ioc->name, __func__));
  2775. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2776. return r;
  2777. }
  2778. /**
  2779. * mpt2sas_base_validate_event_type - validating event types
  2780. * @ioc: per adapter object
  2781. * @event: firmware event
  2782. *
  2783. * This will turn on firmware event notification when application
  2784. * ask for that event. We don't mask events that are already enabled.
  2785. */
  2786. void
  2787. mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
  2788. {
  2789. int i, j;
  2790. u32 event_mask, desired_event;
  2791. u8 send_update_to_fw;
  2792. for (i = 0, send_update_to_fw = 0; i <
  2793. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  2794. event_mask = ~event_type[i];
  2795. desired_event = 1;
  2796. for (j = 0; j < 32; j++) {
  2797. if (!(event_mask & desired_event) &&
  2798. (ioc->event_masks[i] & desired_event)) {
  2799. ioc->event_masks[i] &= ~desired_event;
  2800. send_update_to_fw = 1;
  2801. }
  2802. desired_event = (desired_event << 1);
  2803. }
  2804. }
  2805. if (!send_update_to_fw)
  2806. return;
  2807. mutex_lock(&ioc->base_cmds.mutex);
  2808. _base_event_notification(ioc, CAN_SLEEP);
  2809. mutex_unlock(&ioc->base_cmds.mutex);
  2810. }
  2811. /**
  2812. * _base_diag_reset - the "big hammer" start of day reset
  2813. * @ioc: per adapter object
  2814. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2815. *
  2816. * Returns 0 for success, non-zero for failure.
  2817. */
  2818. static int
  2819. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2820. {
  2821. u32 host_diagnostic;
  2822. u32 ioc_state;
  2823. u32 count;
  2824. u32 hcb_size;
  2825. printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
  2826. _base_save_msix_table(ioc);
  2827. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "clear interrupts\n",
  2828. ioc->name));
  2829. count = 0;
  2830. do {
  2831. /* Write magic sequence to WriteSequence register
  2832. * Loop until in diagnostic mode
  2833. */
  2834. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "write magic "
  2835. "sequence\n", ioc->name));
  2836. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2837. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  2838. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  2839. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  2840. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2841. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2842. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  2843. /* wait 100 msec */
  2844. if (sleep_flag == CAN_SLEEP)
  2845. msleep(100);
  2846. else
  2847. mdelay(100);
  2848. if (count++ > 20)
  2849. goto out;
  2850. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2851. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "wrote magic "
  2852. "sequence: count(%d), host_diagnostic(0x%08x)\n",
  2853. ioc->name, count, host_diagnostic));
  2854. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  2855. hcb_size = readl(&ioc->chip->HCBSize);
  2856. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "diag reset: issued\n",
  2857. ioc->name));
  2858. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  2859. &ioc->chip->HostDiagnostic);
  2860. /* don't access any registers for 50 milliseconds */
  2861. msleep(50);
  2862. /* 300 second max wait */
  2863. for (count = 0; count < 3000000 ; count++) {
  2864. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  2865. if (host_diagnostic == 0xFFFFFFFF)
  2866. goto out;
  2867. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  2868. break;
  2869. /* wait 100 msec */
  2870. if (sleep_flag == CAN_SLEEP)
  2871. msleep(1);
  2872. else
  2873. mdelay(1);
  2874. }
  2875. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  2876. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter "
  2877. "assuming the HCB Address points to good F/W\n",
  2878. ioc->name));
  2879. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  2880. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  2881. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  2882. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT
  2883. "re-enable the HCDW\n", ioc->name));
  2884. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  2885. &ioc->chip->HCBSize);
  2886. }
  2887. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter\n",
  2888. ioc->name));
  2889. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  2890. &ioc->chip->HostDiagnostic);
  2891. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "disable writes to the "
  2892. "diagnostic register\n", ioc->name));
  2893. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  2894. drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "Wait for FW to go to the "
  2895. "READY state\n", ioc->name));
  2896. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  2897. sleep_flag);
  2898. if (ioc_state) {
  2899. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2900. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2901. goto out;
  2902. }
  2903. _base_restore_msix_table(ioc);
  2904. printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
  2905. return 0;
  2906. out:
  2907. printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
  2908. return -EFAULT;
  2909. }
  2910. /**
  2911. * _base_make_ioc_ready - put controller in READY state
  2912. * @ioc: per adapter object
  2913. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2914. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  2915. *
  2916. * Returns 0 for success, non-zero for failure.
  2917. */
  2918. static int
  2919. _base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  2920. enum reset_type type)
  2921. {
  2922. u32 ioc_state;
  2923. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2924. __func__));
  2925. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  2926. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: ioc_state(0x%08x)\n",
  2927. ioc->name, __func__, ioc_state));
  2928. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  2929. return 0;
  2930. if (ioc_state & MPI2_DOORBELL_USED) {
  2931. dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "unexpected doorbell "
  2932. "active!\n", ioc->name));
  2933. goto issue_diag_reset;
  2934. }
  2935. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  2936. mpt2sas_base_fault_info(ioc, ioc_state &
  2937. MPI2_DOORBELL_DATA_MASK);
  2938. goto issue_diag_reset;
  2939. }
  2940. if (type == FORCE_BIG_HAMMER)
  2941. goto issue_diag_reset;
  2942. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  2943. if (!(_base_send_ioc_reset(ioc,
  2944. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP)))
  2945. return 0;
  2946. issue_diag_reset:
  2947. return _base_diag_reset(ioc, CAN_SLEEP);
  2948. }
  2949. /**
  2950. * _base_make_ioc_operational - put controller in OPERATIONAL state
  2951. * @ioc: per adapter object
  2952. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2953. *
  2954. * Returns 0 for success, non-zero for failure.
  2955. */
  2956. static int
  2957. _base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2958. {
  2959. int r, i;
  2960. unsigned long flags;
  2961. u32 reply_address;
  2962. u16 smid;
  2963. struct _tr_list *delayed_tr, *delayed_tr_next;
  2964. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  2965. __func__));
  2966. /* clean the delayed target reset list */
  2967. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  2968. &ioc->delayed_tr_list, list) {
  2969. list_del(&delayed_tr->list);
  2970. kfree(delayed_tr);
  2971. }
  2972. /* initialize the scsi lookup free list */
  2973. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  2974. INIT_LIST_HEAD(&ioc->free_list);
  2975. smid = 1;
  2976. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  2977. ioc->scsi_lookup[i].cb_idx = 0xFF;
  2978. ioc->scsi_lookup[i].smid = smid;
  2979. ioc->scsi_lookup[i].scmd = NULL;
  2980. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  2981. &ioc->free_list);
  2982. }
  2983. /* hi-priority queue */
  2984. INIT_LIST_HEAD(&ioc->hpr_free_list);
  2985. smid = ioc->hi_priority_smid;
  2986. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  2987. ioc->hpr_lookup[i].cb_idx = 0xFF;
  2988. ioc->hpr_lookup[i].smid = smid;
  2989. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  2990. &ioc->hpr_free_list);
  2991. }
  2992. /* internal queue */
  2993. INIT_LIST_HEAD(&ioc->internal_free_list);
  2994. smid = ioc->internal_smid;
  2995. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  2996. ioc->internal_lookup[i].cb_idx = 0xFF;
  2997. ioc->internal_lookup[i].smid = smid;
  2998. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  2999. &ioc->internal_free_list);
  3000. }
  3001. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3002. /* initialize Reply Free Queue */
  3003. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3004. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3005. ioc->reply_sz)
  3006. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3007. /* initialize Reply Post Free Queue */
  3008. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3009. ioc->reply_post_free[i].Words = ULLONG_MAX;
  3010. r = _base_send_ioc_init(ioc, sleep_flag);
  3011. if (r)
  3012. return r;
  3013. /* initialize the index's */
  3014. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3015. ioc->reply_post_host_index = 0;
  3016. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3017. writel(0, &ioc->chip->ReplyPostHostIndex);
  3018. _base_unmask_interrupts(ioc);
  3019. r = _base_event_notification(ioc, sleep_flag);
  3020. if (r)
  3021. return r;
  3022. if (sleep_flag == CAN_SLEEP)
  3023. _base_static_config_pages(ioc);
  3024. r = _base_send_port_enable(ioc, sleep_flag);
  3025. if (r)
  3026. return r;
  3027. return r;
  3028. }
  3029. /**
  3030. * mpt2sas_base_free_resources - free resources controller resources (io/irq/memap)
  3031. * @ioc: per adapter object
  3032. *
  3033. * Return nothing.
  3034. */
  3035. void
  3036. mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
  3037. {
  3038. struct pci_dev *pdev = ioc->pdev;
  3039. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3040. __func__));
  3041. _base_mask_interrupts(ioc);
  3042. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3043. if (ioc->pci_irq) {
  3044. synchronize_irq(pdev->irq);
  3045. free_irq(ioc->pci_irq, ioc);
  3046. }
  3047. _base_disable_msix(ioc);
  3048. if (ioc->chip_phys)
  3049. iounmap(ioc->chip);
  3050. ioc->pci_irq = -1;
  3051. ioc->chip_phys = 0;
  3052. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3053. pci_disable_device(pdev);
  3054. return;
  3055. }
  3056. /**
  3057. * mpt2sas_base_attach - attach controller instance
  3058. * @ioc: per adapter object
  3059. *
  3060. * Returns 0 for success, non-zero for failure.
  3061. */
  3062. int
  3063. mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
  3064. {
  3065. int r, i;
  3066. dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3067. __func__));
  3068. r = mpt2sas_base_map_resources(ioc);
  3069. if (r)
  3070. return r;
  3071. pci_set_drvdata(ioc->pdev, ioc->shost);
  3072. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3073. if (r)
  3074. goto out_free_resources;
  3075. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  3076. if (r)
  3077. goto out_free_resources;
  3078. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  3079. sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
  3080. if (!ioc->pfacts)
  3081. goto out_free_resources;
  3082. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  3083. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  3084. if (r)
  3085. goto out_free_resources;
  3086. }
  3087. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  3088. if (r)
  3089. goto out_free_resources;
  3090. init_waitqueue_head(&ioc->reset_wq);
  3091. /* base internal command bits */
  3092. mutex_init(&ioc->base_cmds.mutex);
  3093. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3094. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3095. /* transport internal command bits */
  3096. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3097. ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
  3098. mutex_init(&ioc->transport_cmds.mutex);
  3099. /* task management internal command bits */
  3100. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3101. ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
  3102. mutex_init(&ioc->tm_cmds.mutex);
  3103. /* config page internal command bits */
  3104. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3105. ioc->config_cmds.status = MPT2_CMD_NOT_USED;
  3106. mutex_init(&ioc->config_cmds.mutex);
  3107. /* ctl module internal command bits */
  3108. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  3109. ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
  3110. mutex_init(&ioc->ctl_cmds.mutex);
  3111. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3112. ioc->event_masks[i] = -1;
  3113. /* here we enable the events we care about */
  3114. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  3115. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  3116. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  3117. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  3118. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  3119. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  3120. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  3121. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  3122. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  3123. _base_unmask_events(ioc, MPI2_EVENT_TASK_SET_FULL);
  3124. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  3125. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  3126. if (r)
  3127. goto out_free_resources;
  3128. mpt2sas_base_start_watchdog(ioc);
  3129. return 0;
  3130. out_free_resources:
  3131. ioc->remove_host = 1;
  3132. mpt2sas_base_free_resources(ioc);
  3133. _base_release_memory_pools(ioc);
  3134. pci_set_drvdata(ioc->pdev, NULL);
  3135. kfree(ioc->tm_cmds.reply);
  3136. kfree(ioc->transport_cmds.reply);
  3137. kfree(ioc->config_cmds.reply);
  3138. kfree(ioc->base_cmds.reply);
  3139. kfree(ioc->ctl_cmds.reply);
  3140. kfree(ioc->pfacts);
  3141. ioc->ctl_cmds.reply = NULL;
  3142. ioc->base_cmds.reply = NULL;
  3143. ioc->tm_cmds.reply = NULL;
  3144. ioc->transport_cmds.reply = NULL;
  3145. ioc->config_cmds.reply = NULL;
  3146. ioc->pfacts = NULL;
  3147. return r;
  3148. }
  3149. /**
  3150. * mpt2sas_base_detach - remove controller instance
  3151. * @ioc: per adapter object
  3152. *
  3153. * Return nothing.
  3154. */
  3155. void
  3156. mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
  3157. {
  3158. dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
  3159. __func__));
  3160. mpt2sas_base_stop_watchdog(ioc);
  3161. mpt2sas_base_free_resources(ioc);
  3162. _base_release_memory_pools(ioc);
  3163. pci_set_drvdata(ioc->pdev, NULL);
  3164. kfree(ioc->pfacts);
  3165. kfree(ioc->ctl_cmds.reply);
  3166. kfree(ioc->base_cmds.reply);
  3167. kfree(ioc->tm_cmds.reply);
  3168. kfree(ioc->transport_cmds.reply);
  3169. kfree(ioc->config_cmds.reply);
  3170. }
  3171. /**
  3172. * _base_reset_handler - reset callback handler (for base)
  3173. * @ioc: per adapter object
  3174. * @reset_phase: phase
  3175. *
  3176. * The handler for doing any required cleanup or initialization.
  3177. *
  3178. * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
  3179. * MPT2_IOC_DONE_RESET
  3180. *
  3181. * Return nothing.
  3182. */
  3183. static void
  3184. _base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
  3185. {
  3186. mpt2sas_scsih_reset_handler(ioc, reset_phase);
  3187. mpt2sas_ctl_reset_handler(ioc, reset_phase);
  3188. switch (reset_phase) {
  3189. case MPT2_IOC_PRE_RESET:
  3190. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3191. "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
  3192. break;
  3193. case MPT2_IOC_AFTER_RESET:
  3194. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3195. "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
  3196. if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
  3197. ioc->transport_cmds.status |= MPT2_CMD_RESET;
  3198. mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  3199. complete(&ioc->transport_cmds.done);
  3200. }
  3201. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3202. ioc->base_cmds.status |= MPT2_CMD_RESET;
  3203. mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
  3204. complete(&ioc->base_cmds.done);
  3205. }
  3206. if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
  3207. ioc->config_cmds.status |= MPT2_CMD_RESET;
  3208. mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
  3209. ioc->config_cmds.smid = USHORT_MAX;
  3210. complete(&ioc->config_cmds.done);
  3211. }
  3212. break;
  3213. case MPT2_IOC_DONE_RESET:
  3214. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
  3215. "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
  3216. break;
  3217. }
  3218. }
  3219. /**
  3220. * _wait_for_commands_to_complete - reset controller
  3221. * @ioc: Pointer to MPT_ADAPTER structure
  3222. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3223. *
  3224. * This function waiting(3s) for all pending commands to complete
  3225. * prior to putting controller in reset.
  3226. */
  3227. static void
  3228. _wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3229. {
  3230. u32 ioc_state;
  3231. unsigned long flags;
  3232. u16 i;
  3233. ioc->pending_io_count = 0;
  3234. if (sleep_flag != CAN_SLEEP)
  3235. return;
  3236. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3237. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  3238. return;
  3239. /* pending command count */
  3240. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3241. for (i = 0; i < ioc->scsiio_depth; i++)
  3242. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  3243. ioc->pending_io_count++;
  3244. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3245. if (!ioc->pending_io_count)
  3246. return;
  3247. /* wait for pending commands to complete */
  3248. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 3 * HZ);
  3249. }
  3250. /**
  3251. * mpt2sas_base_hard_reset_handler - reset controller
  3252. * @ioc: Pointer to MPT_ADAPTER structure
  3253. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3254. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3255. *
  3256. * Returns 0 for success, non-zero for failure.
  3257. */
  3258. int
  3259. mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3260. enum reset_type type)
  3261. {
  3262. int r;
  3263. unsigned long flags;
  3264. u8 pe_complete = ioc->wait_for_port_enable_to_complete;
  3265. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name,
  3266. __func__));
  3267. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3268. if (ioc->shost_recovery) {
  3269. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3270. printk(MPT2SAS_ERR_FMT "%s: busy\n",
  3271. ioc->name, __func__);
  3272. return -EBUSY;
  3273. }
  3274. ioc->shost_recovery = 1;
  3275. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3276. _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
  3277. _wait_for_commands_to_complete(ioc, sleep_flag);
  3278. _base_mask_interrupts(ioc);
  3279. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  3280. if (r)
  3281. goto out;
  3282. _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
  3283. /* If this hard reset is called while port enable is active, then
  3284. * there is no reason to call make_ioc_operational
  3285. */
  3286. if (pe_complete) {
  3287. r = -EFAULT;
  3288. goto out;
  3289. }
  3290. r = _base_make_ioc_operational(ioc, sleep_flag);
  3291. if (!r)
  3292. _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
  3293. out:
  3294. dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: %s\n",
  3295. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  3296. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  3297. ioc->shost_recovery = 0;
  3298. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  3299. if (!r)
  3300. _base_reset_handler(ioc, MPT2_IOC_RUNNING);
  3301. return r;
  3302. }