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    33. 

  33. <h1>stm32f10x_map.h</h1><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************</span>
    34. 

  34. <a name="l00002"></a>00002 <span class="comment">* File Name          : stm32f10x_map.h</span>
    35. 

  35. <a name="l00003"></a>00003 <span class="comment">* Author             : MCD Application Team</span>
    36. 

  36. <a name="l00004"></a>00004 <span class="comment">* Version            : V2.0.3</span>
    37. 

  37. <a name="l00005"></a>00005 <span class="comment">* Date               : 09/22/2008</span>
    38. 

  38. <a name="l00006"></a>00006 <span class="comment">* Description        : This file contains all the peripheral register&apos;s definitions,</span>
    39. 

  39. <a name="l00007"></a>00007 <span class="comment">*                      bits definitions and memory mapping.</span>
    40. 

  40. <a name="l00008"></a>00008 <span class="comment">********************************************************************************</span>
    41. 

  41. <a name="l00009"></a>00009 <span class="comment">* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS</span>
    42. 

  42. <a name="l00010"></a>00010 <span class="comment">* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.</span>
    43. 

  43. <a name="l00011"></a>00011 <span class="comment">* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,</span>
    44. 

  44. <a name="l00012"></a>00012 <span class="comment">* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE</span>
    45. 

  45. <a name="l00013"></a>00013 <span class="comment">* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING</span>
    46. 

  46. <a name="l00014"></a>00014 <span class="comment">* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.</span>
    47. 

  47. <a name="l00015"></a>00015 <span class="comment">*******************************************************************************/</span>
    48. 

  48. <a name="l00016"></a>00016 
    49. 

  49. <a name="l00017"></a>00017 <span class="comment">/* Define to prevent recursive inclusion -------------------------------------*/</span>
    50. 

  50. <a name="l00018"></a>00018 <span class="preprocessor">#ifndef __STM32F10x_MAP_H</span>
    51. 

  51. <a name="l00019"></a>00019 <span class="preprocessor"></span><span class="preprocessor">#define __STM32F10x_MAP_H</span>
    52. 

  52. <a name="l00020"></a>00020 <span class="preprocessor"></span>
    53. 

  53. <a name="l00021"></a>00021 <span class="preprocessor">#ifndef EXT</span>
    54. 

  54. <a name="l00022"></a>00022 <span class="preprocessor"></span><span class="preprocessor">  #define EXT extern</span>
    55. 

  55. <a name="l00023"></a>00023 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* EXT */</span>
    56. 

  56. <a name="l00024"></a>00024 
    57. 

  57. <a name="l00025"></a>00025 <span class="comment">/* Includes ------------------------------------------------------------------*/</span>
    58. 

  58. <a name="l00026"></a>00026 <span class="preprocessor">#include &quot;stm32f10x_conf.h&quot;</span>
    59. 

  59. <a name="l00027"></a>00027 <span class="preprocessor">#include &quot;stm32f10x_type.h&quot;</span>
    60. 

  60. <a name="l00028"></a>00028 <span class="preprocessor">#include &quot;cortexm3_macro.h&quot;</span>
    61. 

  61. <a name="l00029"></a>00029 
    62. 

  62. <a name="l00030"></a>00030 <span class="comment">/* Exported types ------------------------------------------------------------*/</span>
    63. 

  63. <a name="l00031"></a>00031 <span class="comment">/******************************************************************************/</span>
    64. 

  64. <a name="l00032"></a>00032 <span class="comment">/*                         Peripheral registers structures                    */</span>
    65. 

  65. <a name="l00033"></a>00033 <span class="comment">/******************************************************************************/</span>
    66. 

  66. <a name="l00034"></a>00034 
    67. 

  67. <a name="l00035"></a>00035 <span class="comment">/*------------------------ Analog to Digital Converter -----------------------*/</span>
    68. 

  68. <a name="l00036"></a>00036 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    69. 

  69. <a name="l00037"></a>00037 {
    70. 

  70. <a name="l00038"></a>00038   vu32 SR;
    71. 

  71. <a name="l00039"></a>00039   vu32 CR1;
    72. 

  72. <a name="l00040"></a>00040   vu32 CR2;
    73. 

  73. <a name="l00041"></a>00041   vu32 SMPR1;
    74. 

  74. <a name="l00042"></a>00042   vu32 SMPR2;
    75. 

  75. <a name="l00043"></a>00043   vu32 JOFR1;
    76. 

  76. <a name="l00044"></a>00044   vu32 JOFR2;
    77. 

  77. <a name="l00045"></a>00045   vu32 JOFR3;
    78. 

  78. <a name="l00046"></a>00046   vu32 JOFR4;
    79. 

  79. <a name="l00047"></a>00047   vu32 HTR;
    80. 

  80. <a name="l00048"></a>00048   vu32 LTR;
    81. 

  81. <a name="l00049"></a>00049   vu32 SQR1;
    82. 

  82. <a name="l00050"></a>00050   vu32 SQR2;
    83. 

  83. <a name="l00051"></a>00051   vu32 SQR3;
    84. 

  84. <a name="l00052"></a>00052   vu32 JSQR;
    85. 

  85. <a name="l00053"></a>00053   vu32 JDR1;
    86. 

  86. <a name="l00054"></a>00054   vu32 JDR2;
    87. 

  87. <a name="l00055"></a>00055   vu32 JDR3;
    88. 

  88. <a name="l00056"></a>00056   vu32 JDR4;
    89. 

  89. <a name="l00057"></a>00057   vu32 DR;
    90. 

  90. <a name="l00058"></a>00058 } ADC_TypeDef;
    91. 

  91. <a name="l00059"></a>00059 
    92. 

  92. <a name="l00060"></a>00060 <span class="comment">/*------------------------ Backup Registers ----------------------------------*/</span>
    93. 

  93. <a name="l00061"></a>00061 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    94. 

  94. <a name="l00062"></a>00062 {
    95. 

  95. <a name="l00063"></a>00063   u32  RESERVED0;
    96. 

  96. <a name="l00064"></a>00064   vu16 DR1;
    97. 

  97. <a name="l00065"></a>00065   u16  RESERVED1;
    98. 

  98. <a name="l00066"></a>00066   vu16 DR2;
    99. 

  99. <a name="l00067"></a>00067   u16  RESERVED2;
    100. 

  100. <a name="l00068"></a>00068   vu16 DR3;
    101. 

  101. <a name="l00069"></a>00069   u16  RESERVED3;
    102. 

  102. <a name="l00070"></a>00070   vu16 DR4;
    103. 

  103. <a name="l00071"></a>00071   u16  RESERVED4;
    104. 

  104. <a name="l00072"></a>00072   vu16 DR5;
    105. 

  105. <a name="l00073"></a>00073   u16  RESERVED5;
    106. 

  106. <a name="l00074"></a>00074   vu16 DR6;
    107. 

  107. <a name="l00075"></a>00075   u16  RESERVED6;
    108. 

  108. <a name="l00076"></a>00076   vu16 DR7;
    109. 

  109. <a name="l00077"></a>00077   u16  RESERVED7;
    110. 

  110. <a name="l00078"></a>00078   vu16 DR8;
    111. 

  111. <a name="l00079"></a>00079   u16  RESERVED8;
    112. 

  112. <a name="l00080"></a>00080   vu16 DR9;
    113. 

  113. <a name="l00081"></a>00081   u16  RESERVED9;
    114. 

  114. <a name="l00082"></a>00082   vu16 DR10;
    115. 

  115. <a name="l00083"></a>00083   u16  RESERVED10; 
    116. 

  116. <a name="l00084"></a>00084   vu16 RTCCR;
    117. 

  117. <a name="l00085"></a>00085   u16  RESERVED11;
    118. 

  118. <a name="l00086"></a>00086   vu16 CR;
    119. 

  119. <a name="l00087"></a>00087   u16  RESERVED12;
    120. 

  120. <a name="l00088"></a>00088   vu16 CSR;
    121. 

  121. <a name="l00089"></a>00089   u16  RESERVED13[5];
    122. 

  122. <a name="l00090"></a>00090   vu16 DR11;
    123. 

  123. <a name="l00091"></a>00091   u16  RESERVED14;
    124. 

  124. <a name="l00092"></a>00092   vu16 DR12;
    125. 

  125. <a name="l00093"></a>00093   u16  RESERVED15;
    126. 

  126. <a name="l00094"></a>00094   vu16 DR13;
    127. 

  127. <a name="l00095"></a>00095   u16  RESERVED16;
    128. 

  128. <a name="l00096"></a>00096   vu16 DR14;
    129. 

  129. <a name="l00097"></a>00097   u16  RESERVED17;
    130. 

  130. <a name="l00098"></a>00098   vu16 DR15;
    131. 

  131. <a name="l00099"></a>00099   u16  RESERVED18;
    132. 

  132. <a name="l00100"></a>00100   vu16 DR16;
    133. 

  133. <a name="l00101"></a>00101   u16  RESERVED19;
    134. 

  134. <a name="l00102"></a>00102   vu16 DR17;
    135. 

  135. <a name="l00103"></a>00103   u16  RESERVED20;
    136. 

  136. <a name="l00104"></a>00104   vu16 DR18;
    137. 

  137. <a name="l00105"></a>00105   u16  RESERVED21;
    138. 

  138. <a name="l00106"></a>00106   vu16 DR19;
    139. 

  139. <a name="l00107"></a>00107   u16  RESERVED22;
    140. 

  140. <a name="l00108"></a>00108   vu16 DR20;
    141. 

  141. <a name="l00109"></a>00109   u16  RESERVED23;
    142. 

  142. <a name="l00110"></a>00110   vu16 DR21;
    143. 

  143. <a name="l00111"></a>00111   u16  RESERVED24;
    144. 

  144. <a name="l00112"></a>00112   vu16 DR22;
    145. 

  145. <a name="l00113"></a>00113   u16  RESERVED25;
    146. 

  146. <a name="l00114"></a>00114   vu16 DR23;
    147. 

  147. <a name="l00115"></a>00115   u16  RESERVED26;
    148. 

  148. <a name="l00116"></a>00116   vu16 DR24;
    149. 

  149. <a name="l00117"></a>00117   u16  RESERVED27;
    150. 

  150. <a name="l00118"></a>00118   vu16 DR25;
    151. 

  151. <a name="l00119"></a>00119   u16  RESERVED28;
    152. 

  152. <a name="l00120"></a>00120   vu16 DR26;
    153. 

  153. <a name="l00121"></a>00121   u16  RESERVED29;
    154. 

  154. <a name="l00122"></a>00122   vu16 DR27;
    155. 

  155. <a name="l00123"></a>00123   u16  RESERVED30;
    156. 

  156. <a name="l00124"></a>00124   vu16 DR28;
    157. 

  157. <a name="l00125"></a>00125   u16  RESERVED31;
    158. 

  158. <a name="l00126"></a>00126   vu16 DR29;
    159. 

  159. <a name="l00127"></a>00127   u16  RESERVED32;
    160. 

  160. <a name="l00128"></a>00128   vu16 DR30;
    161. 

  161. <a name="l00129"></a>00129   u16  RESERVED33; 
    162. 

  162. <a name="l00130"></a>00130   vu16 DR31;
    163. 

  163. <a name="l00131"></a>00131   u16  RESERVED34;
    164. 

  164. <a name="l00132"></a>00132   vu16 DR32;
    165. 

  165. <a name="l00133"></a>00133   u16  RESERVED35;
    166. 

  166. <a name="l00134"></a>00134   vu16 DR33;
    167. 

  167. <a name="l00135"></a>00135   u16  RESERVED36;
    168. 

  168. <a name="l00136"></a>00136   vu16 DR34;
    169. 

  169. <a name="l00137"></a>00137   u16  RESERVED37;
    170. 

  170. <a name="l00138"></a>00138   vu16 DR35;
    171. 

  171. <a name="l00139"></a>00139   u16  RESERVED38;
    172. 

  172. <a name="l00140"></a>00140   vu16 DR36;
    173. 

  173. <a name="l00141"></a>00141   u16  RESERVED39;
    174. 

  174. <a name="l00142"></a>00142   vu16 DR37;
    175. 

  175. <a name="l00143"></a>00143   u16  RESERVED40;
    176. 

  176. <a name="l00144"></a>00144   vu16 DR38;
    177. 

  177. <a name="l00145"></a>00145   u16  RESERVED41;
    178. 

  178. <a name="l00146"></a>00146   vu16 DR39;
    179. 

  179. <a name="l00147"></a>00147   u16  RESERVED42;
    180. 

  180. <a name="l00148"></a>00148   vu16 DR40;
    181. 

  181. <a name="l00149"></a>00149   u16  RESERVED43;
    182. 

  182. <a name="l00150"></a>00150   vu16 DR41;
    183. 

  183. <a name="l00151"></a>00151   u16  RESERVED44;
    184. 

  184. <a name="l00152"></a>00152   vu16 DR42;
    185. 

  185. <a name="l00153"></a>00153   u16  RESERVED45;    
    186. 

  186. <a name="l00154"></a>00154 } BKP_TypeDef;
    187. 

  187. <a name="l00155"></a>00155 
    188. 

  188. <a name="l00156"></a>00156 <span class="comment">/*------------------------ Controller Area Network ---------------------------*/</span>
    189. 

  189. <a name="l00157"></a>00157 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    190. 

  190. <a name="l00158"></a>00158 {
    191. 

  191. <a name="l00159"></a>00159   vu32 TIR;
    192. 

  192. <a name="l00160"></a>00160   vu32 TDTR;
    193. 

  193. <a name="l00161"></a>00161   vu32 TDLR;
    194. 

  194. <a name="l00162"></a>00162   vu32 TDHR;
    195. 

  195. <a name="l00163"></a>00163 } CAN_TxMailBox_TypeDef;
    196. 

  196. <a name="l00164"></a>00164 
    197. 

  197. <a name="l00165"></a>00165 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    198. 

  198. <a name="l00166"></a>00166 {
    199. 

  199. <a name="l00167"></a>00167   vu32 RIR;
    200. 

  200. <a name="l00168"></a>00168   vu32 RDTR;
    201. 

  201. <a name="l00169"></a>00169   vu32 RDLR;
    202. 

  202. <a name="l00170"></a>00170   vu32 RDHR;
    203. 

  203. <a name="l00171"></a>00171 } CAN_FIFOMailBox_TypeDef;
    204. 

  204. <a name="l00172"></a>00172 
    205. 

  205. <a name="l00173"></a>00173 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    206. 

  206. <a name="l00174"></a>00174 {
    207. 

  207. <a name="l00175"></a>00175   vu32 FR1;
    208. 

  208. <a name="l00176"></a>00176   vu32 FR2;
    209. 

  209. <a name="l00177"></a>00177 } CAN_FilterRegister_TypeDef;
    210. 

  210. <a name="l00178"></a>00178 
    211. 

  211. <a name="l00179"></a>00179 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    212. 

  212. <a name="l00180"></a>00180 {
    213. 

  213. <a name="l00181"></a>00181   vu32 MCR;
    214. 

  214. <a name="l00182"></a>00182   vu32 MSR;
    215. 

  215. <a name="l00183"></a>00183   vu32 TSR;
    216. 

  216. <a name="l00184"></a>00184   vu32 RF0R;
    217. 

  217. <a name="l00185"></a>00185   vu32 RF1R;
    218. 

  218. <a name="l00186"></a>00186   vu32 IER;
    219. 

  219. <a name="l00187"></a>00187   vu32 ESR;
    220. 

  220. <a name="l00188"></a>00188   vu32 BTR;
    221. 

  221. <a name="l00189"></a>00189   u32  RESERVED0[88];
    222. 

  222. <a name="l00190"></a>00190   CAN_TxMailBox_TypeDef sTxMailBox[3];
    223. 

  223. <a name="l00191"></a>00191   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
    224. 

  224. <a name="l00192"></a>00192   u32  RESERVED1[12];
    225. 

  225. <a name="l00193"></a>00193   vu32 FMR;
    226. 

  226. <a name="l00194"></a>00194   vu32 FM1R;
    227. 

  227. <a name="l00195"></a>00195   u32  RESERVED2;
    228. 

  228. <a name="l00196"></a>00196   vu32 FS1R;
    229. 

  229. <a name="l00197"></a>00197   u32  RESERVED3;
    230. 

  230. <a name="l00198"></a>00198   vu32 FFA1R;
    231. 

  231. <a name="l00199"></a>00199   u32  RESERVED4;
    232. 

  232. <a name="l00200"></a>00200   vu32 FA1R;
    233. 

  233. <a name="l00201"></a>00201   u32  RESERVED5[8];
    234. 

  234. <a name="l00202"></a>00202   CAN_FilterRegister_TypeDef sFilterRegister[14];
    235. 

  235. <a name="l00203"></a>00203 } CAN_TypeDef;
    236. 

  236. <a name="l00204"></a>00204 
    237. 

  237. <a name="l00205"></a>00205 <span class="comment">/*------------------------ CRC calculation unit ------------------------------*/</span>
    238. 

  238. <a name="l00206"></a>00206 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    239. 

  239. <a name="l00207"></a>00207 {
    240. 

  240. <a name="l00208"></a>00208   vu32 DR;
    241. 

  241. <a name="l00209"></a>00209   vu8  IDR;
    242. 

  242. <a name="l00210"></a>00210   u8   RESERVED0;
    243. 

  243. <a name="l00211"></a>00211   u16  RESERVED1;
    244. 

  244. <a name="l00212"></a>00212   vu32 CR;
    245. 

  245. <a name="l00213"></a>00213 } CRC_TypeDef;
    246. 

  246. <a name="l00214"></a>00214 
    247. 

  247. <a name="l00215"></a>00215 
    248. 

  248. <a name="l00216"></a>00216 <span class="comment">/*------------------------ Digital to Analog Converter -----------------------*/</span>
    249. 

  249. <a name="l00217"></a>00217 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    250. 

  250. <a name="l00218"></a>00218 {
    251. 

  251. <a name="l00219"></a>00219   vu32 CR;
    252. 

  252. <a name="l00220"></a>00220   vu32 SWTRIGR;
    253. 

  253. <a name="l00221"></a>00221   vu32 DHR12R1;
    254. 

  254. <a name="l00222"></a>00222   vu32 DHR12L1;
    255. 

  255. <a name="l00223"></a>00223   vu32 DHR8R1;
    256. 

  256. <a name="l00224"></a>00224   vu32 DHR12R2;
    257. 

  257. <a name="l00225"></a>00225   vu32 DHR12L2;
    258. 

  258. <a name="l00226"></a>00226   vu32 DHR8R2;
    259. 

  259. <a name="l00227"></a>00227   vu32 DHR12RD;
    260. 

  260. <a name="l00228"></a>00228   vu32 DHR12LD;
    261. 

  261. <a name="l00229"></a>00229   vu32 DHR8RD;
    262. 

  262. <a name="l00230"></a>00230   vu32 DOR1;
    263. 

  263. <a name="l00231"></a>00231   vu32 DOR2;
    264. 

  264. <a name="l00232"></a>00232 } DAC_TypeDef;
    265. 

  265. <a name="l00233"></a>00233 
    266. 

  266. <a name="l00234"></a>00234 <span class="comment">/*------------------------ Debug MCU -----------------------------------------*/</span>
    267. 

  267. <a name="l00235"></a>00235 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    268. 

  268. <a name="l00236"></a>00236 {
    269. 

  269. <a name="l00237"></a>00237   vu32 IDCODE;
    270. 

  270. <a name="l00238"></a>00238   vu32 CR;      
    271. 

  271. <a name="l00239"></a>00239 }DBGMCU_TypeDef;
    272. 

  272. <a name="l00240"></a>00240 
    273. 

  273. <a name="l00241"></a>00241 <span class="comment">/*------------------------ DMA Controller ------------------------------------*/</span>
    274. 

  274. <a name="l00242"></a>00242 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    275. 

  275. <a name="l00243"></a>00243 {
    276. 

  276. <a name="l00244"></a>00244   vu32 CCR;
    277. 

  277. <a name="l00245"></a>00245   vu32 CNDTR;
    278. 

  278. <a name="l00246"></a>00246   vu32 CPAR;
    279. 

  279. <a name="l00247"></a>00247   vu32 CMAR;
    280. 

  280. <a name="l00248"></a>00248 } DMA_Channel_TypeDef;
    281. 

  281. <a name="l00249"></a>00249 
    282. 

  282. <a name="l00250"></a>00250 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    283. 

  283. <a name="l00251"></a>00251 {
    284. 

  284. <a name="l00252"></a>00252   vu32 <a class="code" href="a01646.html#ga28bf4c54d9527b4a20eb142b6cf3d66a" title="USB general interrupt subroutine.">ISR</a>;
    285. 

  285. <a name="l00253"></a>00253   vu32 IFCR;
    286. 

  286. <a name="l00254"></a>00254 } DMA_TypeDef;
    287. 

  287. <a name="l00255"></a>00255 
    288. 

  288. <a name="l00256"></a>00256 <span class="comment">/*------------------------ External Interrupt/Event Controller ---------------*/</span>
    289. 

  289. <a name="l00257"></a>00257 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    290. 

  290. <a name="l00258"></a>00258 {
    291. 

  291. <a name="l00259"></a>00259   vu32 IMR;
    292. 

  292. <a name="l00260"></a>00260   vu32 EMR;
    293. 

  293. <a name="l00261"></a>00261   vu32 RTSR;
    294. 

  294. <a name="l00262"></a>00262   vu32 FTSR;
    295. 

  295. <a name="l00263"></a>00263   vu32 SWIER;
    296. 

  296. <a name="l00264"></a>00264   vu32 PR;
    297. 

  297. <a name="l00265"></a>00265 } EXTI_TypeDef;
    298. 

  298. <a name="l00266"></a>00266 
    299. 

  299. <a name="l00267"></a>00267 <span class="comment">/*------------------------ FLASH and Option Bytes Registers ------------------*/</span>
    300. 

  300. <a name="l00268"></a>00268 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    301. 

  301. <a name="l00269"></a>00269 {
    302. 

  302. <a name="l00270"></a>00270   vu32 ACR;
    303. 

  303. <a name="l00271"></a>00271   vu32 KEYR;
    304. 

  304. <a name="l00272"></a>00272   vu32 OPTKEYR;
    305. 

  305. <a name="l00273"></a>00273   vu32 SR;
    306. 

  306. <a name="l00274"></a>00274   vu32 CR;
    307. 

  307. <a name="l00275"></a>00275   vu32 AR;
    308. 

  308. <a name="l00276"></a>00276   vu32 RESERVED;
    309. 

  309. <a name="l00277"></a>00277   vu32 OBR;
    310. 

  310. <a name="l00278"></a>00278   vu32 WRPR;
    311. 

  311. <a name="l00279"></a>00279 } FLASH_TypeDef;
    312. 

  312. <a name="l00280"></a>00280 
    313. 

  313. <a name="l00281"></a>00281 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    314. 

  314. <a name="l00282"></a>00282 {
    315. 

  315. <a name="l00283"></a>00283   vu16 RDP;
    316. 

  316. <a name="l00284"></a>00284   vu16 USER;
    317. 

  317. <a name="l00285"></a>00285   vu16 Data0;
    318. 

  318. <a name="l00286"></a>00286   vu16 Data1;
    319. 

  319. <a name="l00287"></a>00287   vu16 WRP0;
    320. 

  320. <a name="l00288"></a>00288   vu16 WRP1;
    321. 

  321. <a name="l00289"></a>00289   vu16 WRP2;
    322. 

  322. <a name="l00290"></a>00290   vu16 WRP3;
    323. 

  323. <a name="l00291"></a>00291 } OB_TypeDef;
    324. 

  324. <a name="l00292"></a>00292 
    325. 

  325. <a name="l00293"></a>00293 <span class="comment">/*------------------------ Flexible Static Memory Controller -----------------*/</span>
    326. 

  326. <a name="l00294"></a>00294 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    327. 

  327. <a name="l00295"></a>00295 {
    328. 

  328. <a name="l00296"></a>00296   vu32 BTCR[8];   
    329. 

  329. <a name="l00297"></a>00297 } FSMC_Bank1_TypeDef; 
    330. 

  330. <a name="l00298"></a>00298 
    331. 

  331. <a name="l00299"></a>00299 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    332. 

  332. <a name="l00300"></a>00300 {
    333. 

  333. <a name="l00301"></a>00301   vu32 BWTR[7];
    334. 

  334. <a name="l00302"></a>00302 } FSMC_Bank1E_TypeDef;
    335. 

  335. <a name="l00303"></a>00303 
    336. 

  336. <a name="l00304"></a>00304 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    337. 

  337. <a name="l00305"></a>00305 {
    338. 

  338. <a name="l00306"></a>00306   vu32 PCR2;
    339. 

  339. <a name="l00307"></a>00307   vu32 SR2;
    340. 

  340. <a name="l00308"></a>00308   vu32 PMEM2;
    341. 

  341. <a name="l00309"></a>00309   vu32 PATT2;
    342. 

  342. <a name="l00310"></a>00310   u32  RESERVED0;   
    343. 

  343. <a name="l00311"></a>00311   vu32 ECCR2; 
    344. 

  344. <a name="l00312"></a>00312 } FSMC_Bank2_TypeDef;  
    345. 

  345. <a name="l00313"></a>00313 
    346. 

  346. <a name="l00314"></a>00314 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    347. 

  347. <a name="l00315"></a>00315 {
    348. 

  348. <a name="l00316"></a>00316   vu32 PCR3;
    349. 

  349. <a name="l00317"></a>00317   vu32 SR3;
    350. 

  350. <a name="l00318"></a>00318   vu32 PMEM3;
    351. 

  351. <a name="l00319"></a>00319   vu32 PATT3;
    352. 

  352. <a name="l00320"></a>00320   u32  RESERVED0;   
    353. 

  353. <a name="l00321"></a>00321   vu32 ECCR3; 
    354. 

  354. <a name="l00322"></a>00322 } FSMC_Bank3_TypeDef; 
    355. 

  355. <a name="l00323"></a>00323 
    356. 

  356. <a name="l00324"></a>00324 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    357. 

  357. <a name="l00325"></a>00325 {
    358. 

  358. <a name="l00326"></a>00326   vu32 PCR4;
    359. 

  359. <a name="l00327"></a>00327   vu32 SR4;
    360. 

  360. <a name="l00328"></a>00328   vu32 PMEM4;
    361. 

  361. <a name="l00329"></a>00329   vu32 PATT4;
    362. 

  362. <a name="l00330"></a>00330   vu32 PIO4; 
    363. 

  363. <a name="l00331"></a>00331 } FSMC_Bank4_TypeDef; 
    364. 

  364. <a name="l00332"></a>00332 
    365. 

  365. <a name="l00333"></a>00333 <span class="comment">/*------------------------ General Purpose and Alternate Function IO ---------*/</span>
    366. 

  366. <a name="l00334"></a>00334 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    367. 

  367. <a name="l00335"></a>00335 {
    368. 

  368. <a name="l00336"></a>00336   vu32 CRL;
    369. 

  369. <a name="l00337"></a>00337   vu32 CRH;
    370. 

  370. <a name="l00338"></a>00338   vu32 IDR;
    371. 

  371. <a name="l00339"></a>00339   vu32 ODR;
    372. 

  372. <a name="l00340"></a>00340   vu32 BSRR;
    373. 

  373. <a name="l00341"></a>00341   vu32 BRR;
    374. 

  374. <a name="l00342"></a>00342   vu32 LCKR;
    375. 

  375. <a name="l00343"></a>00343 } GPIO_TypeDef;
    376. 

  376. <a name="l00344"></a>00344 
    377. 

  377. <a name="l00345"></a>00345 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    378. 

  378. <a name="l00346"></a>00346 {
    379. 

  379. <a name="l00347"></a>00347   vu32 EVCR;
    380. 

  380. <a name="l00348"></a>00348   vu32 MAPR;
    381. 

  381. <a name="l00349"></a>00349   vu32 EXTICR[4];
    382. 

  382. <a name="l00350"></a>00350 } AFIO_TypeDef;
    383. 

  383. <a name="l00351"></a>00351 
    384. 

  384. <a name="l00352"></a>00352 <span class="comment">/*------------------------ Inter-integrated Circuit Interface ----------------*/</span>
    385. 

  385. <a name="l00353"></a>00353 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    386. 

  386. <a name="l00354"></a>00354 {
    387. 

  387. <a name="l00355"></a>00355   vu16 CR1;
    388. 

  388. <a name="l00356"></a>00356   u16  RESERVED0;
    389. 

  389. <a name="l00357"></a>00357   vu16 CR2;
    390. 

  390. <a name="l00358"></a>00358   u16  RESERVED1;
    391. 

  391. <a name="l00359"></a>00359   vu16 OAR1;
    392. 

  392. <a name="l00360"></a>00360   u16  RESERVED2;
    393. 

  393. <a name="l00361"></a>00361   vu16 OAR2;
    394. 

  394. <a name="l00362"></a>00362   u16  RESERVED3;
    395. 

  395. <a name="l00363"></a>00363   vu16 DR;
    396. 

  396. <a name="l00364"></a>00364   u16  RESERVED4;
    397. 

  397. <a name="l00365"></a>00365   vu16 SR1;
    398. 

  398. <a name="l00366"></a>00366   u16  RESERVED5;
    399. 

  399. <a name="l00367"></a>00367   vu16 SR2;
    400. 

  400. <a name="l00368"></a>00368   u16  RESERVED6;
    401. 

  401. <a name="l00369"></a>00369   vu16 CCR;
    402. 

  402. <a name="l00370"></a>00370   u16  RESERVED7;
    403. 

  403. <a name="l00371"></a>00371   vu16 TRISE;
    404. 

  404. <a name="l00372"></a>00372   u16  RESERVED8;
    405. 

  405. <a name="l00373"></a>00373 } I2C_TypeDef;
    406. 

  406. <a name="l00374"></a>00374 
    407. 

  407. <a name="l00375"></a>00375 <span class="comment">/*------------------------ Independent WATCHDOG ------------------------------*/</span>
    408. 

  408. <a name="l00376"></a>00376 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    409. 

  409. <a name="l00377"></a>00377 {
    410. 

  410. <a name="l00378"></a>00378   vu32 KR;
    411. 

  411. <a name="l00379"></a>00379   vu32 PR;
    412. 

  412. <a name="l00380"></a>00380   vu32 RLR;
    413. 

  413. <a name="l00381"></a>00381   vu32 SR;
    414. 

  414. <a name="l00382"></a>00382 } IWDG_TypeDef;
    415. 

  415. <a name="l00383"></a>00383 
    416. 

  416. <a name="l00384"></a>00384 <span class="comment">/*------------------------ Nested Vectored Interrupt Controller --------------*/</span>
    417. 

  417. <a name="l00385"></a>00385 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    418. 

  418. <a name="l00386"></a>00386 {
    419. 

  419. <a name="l00387"></a>00387   vu32 ISER[2];
    420. 

  420. <a name="l00388"></a>00388   u32  RESERVED0[30];
    421. 

  421. <a name="l00389"></a>00389   vu32 ICER[2];
    422. 

  422. <a name="l00390"></a>00390   u32  RSERVED1[30];
    423. 

  423. <a name="l00391"></a>00391   vu32 ISPR[2];
    424. 

  424. <a name="l00392"></a>00392   u32  RESERVED2[30];
    425. 

  425. <a name="l00393"></a>00393   vu32 ICPR[2];
    426. 

  426. <a name="l00394"></a>00394   u32  RESERVED3[30];
    427. 

  427. <a name="l00395"></a>00395   vu32 IABR[2];
    428. 

  428. <a name="l00396"></a>00396   u32  RESERVED4[62];
    429. 

  429. <a name="l00397"></a>00397   vu32 IPR[15];
    430. 

  430. <a name="l00398"></a>00398 } NVIC_TypeDef;
    431. 

  431. <a name="l00399"></a>00399 
    432. 

  432. <a name="l00400"></a>00400 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    433. 

  433. <a name="l00401"></a>00401 {
    434. 

  434. <a name="l00402"></a>00402   vuc32 CPUID;
    435. 

  435. <a name="l00403"></a>00403   vu32 ICSR;
    436. 

  436. <a name="l00404"></a>00404   vu32 VTOR;
    437. 

  437. <a name="l00405"></a>00405   vu32 AIRCR;
    438. 

  438. <a name="l00406"></a>00406   vu32 SCR;
    439. 

  439. <a name="l00407"></a>00407   vu32 CCR;
    440. 

  440. <a name="l00408"></a>00408   vu32 SHPR[3];
    441. 

  441. <a name="l00409"></a>00409   vu32 SHCSR;
    442. 

  442. <a name="l00410"></a>00410   vu32 CFSR;
    443. 

  443. <a name="l00411"></a>00411   vu32 HFSR;
    444. 

  444. <a name="l00412"></a>00412   vu32 DFSR;
    445. 

  445. <a name="l00413"></a>00413   vu32 MMFAR;
    446. 

  446. <a name="l00414"></a>00414   vu32 BFAR;
    447. 

  447. <a name="l00415"></a>00415   vu32 AFSR;
    448. 

  448. <a name="l00416"></a>00416 } SCB_TypeDef;
    449. 

  449. <a name="l00417"></a>00417 
    450. 

  450. <a name="l00418"></a>00418 <span class="comment">/*------------------------ Power Control -------------------------------------*/</span>
    451. 

  451. <a name="l00419"></a>00419 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    452. 

  452. <a name="l00420"></a>00420 {
    453. 

  453. <a name="l00421"></a>00421   vu32 CR;
    454. 

  454. <a name="l00422"></a>00422   vu32 CSR;
    455. 

  455. <a name="l00423"></a>00423 } PWR_TypeDef;
    456. 

  456. <a name="l00424"></a>00424 
    457. 

  457. <a name="l00425"></a>00425 <span class="comment">/*------------------------ Reset and Clock Control ---------------------------*/</span>
    458. 

  458. <a name="l00426"></a>00426 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    459. 

  459. <a name="l00427"></a>00427 {
    460. 

  460. <a name="l00428"></a>00428   vu32 CR;
    461. 

  461. <a name="l00429"></a>00429   vu32 CFGR;
    462. 

  462. <a name="l00430"></a>00430   vu32 CIR;
    463. 

  463. <a name="l00431"></a>00431   vu32 APB2RSTR;
    464. 

  464. <a name="l00432"></a>00432   vu32 APB1RSTR;
    465. 

  465. <a name="l00433"></a>00433   vu32 AHBENR;
    466. 

  466. <a name="l00434"></a>00434   vu32 APB2ENR;
    467. 

  467. <a name="l00435"></a>00435   vu32 APB1ENR;
    468. 

  468. <a name="l00436"></a>00436   vu32 BDCR;
    469. 

  469. <a name="l00437"></a>00437   vu32 CSR;
    470. 

  470. <a name="l00438"></a>00438 } RCC_TypeDef;
    471. 

  471. <a name="l00439"></a>00439 
    472. 

  472. <a name="l00440"></a>00440 <span class="comment">/*------------------------ Real-Time Clock -----------------------------------*/</span>
    473. 

  473. <a name="l00441"></a>00441 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    474. 

  474. <a name="l00442"></a>00442 {
    475. 

  475. <a name="l00443"></a>00443   vu16 CRH;
    476. 

  476. <a name="l00444"></a>00444   u16  RESERVED0;
    477. 

  477. <a name="l00445"></a>00445   vu16 CRL;
    478. 

  478. <a name="l00446"></a>00446   u16  RESERVED1;
    479. 

  479. <a name="l00447"></a>00447   vu16 PRLH;
    480. 

  480. <a name="l00448"></a>00448   u16  RESERVED2;
    481. 

  481. <a name="l00449"></a>00449   vu16 PRLL;
    482. 

  482. <a name="l00450"></a>00450   u16  RESERVED3;
    483. 

  483. <a name="l00451"></a>00451   vu16 DIVH;
    484. 

  484. <a name="l00452"></a>00452   u16  RESERVED4;
    485. 

  485. <a name="l00453"></a>00453   vu16 DIVL;
    486. 

  486. <a name="l00454"></a>00454   u16  RESERVED5;
    487. 

  487. <a name="l00455"></a>00455   vu16 CNTH;
    488. 

  488. <a name="l00456"></a>00456   u16  RESERVED6;
    489. 

  489. <a name="l00457"></a>00457   vu16 CNTL;
    490. 

  490. <a name="l00458"></a>00458   u16  RESERVED7;
    491. 

  491. <a name="l00459"></a>00459   vu16 ALRH;
    492. 

  492. <a name="l00460"></a>00460   u16  RESERVED8;
    493. 

  493. <a name="l00461"></a>00461   vu16 ALRL;
    494. 

  494. <a name="l00462"></a>00462   u16  RESERVED9;
    495. 

  495. <a name="l00463"></a>00463 } RTC_TypeDef;
    496. 

  496. <a name="l00464"></a>00464 
    497. 

  497. <a name="l00465"></a>00465 <span class="comment">/*------------------------ SD host Interface ---------------------------------*/</span>
    498. 

  498. <a name="l00466"></a>00466 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    499. 

  499. <a name="l00467"></a>00467 {
    500. 

  500. <a name="l00468"></a>00468   vu32 POWER;
    501. 

  501. <a name="l00469"></a>00469   vu32 CLKCR;
    502. 

  502. <a name="l00470"></a>00470   vu32 ARG;
    503. 

  503. <a name="l00471"></a>00471   vu32 CMD;
    504. 

  504. <a name="l00472"></a>00472   vuc32 RESPCMD;
    505. 

  505. <a name="l00473"></a>00473   vuc32 RESP1;
    506. 

  506. <a name="l00474"></a>00474   vuc32 RESP2;
    507. 

  507. <a name="l00475"></a>00475   vuc32 RESP3;
    508. 

  508. <a name="l00476"></a>00476   vuc32 RESP4;
    509. 

  509. <a name="l00477"></a>00477   vu32 DTIMER;
    510. 

  510. <a name="l00478"></a>00478   vu32 DLEN;
    511. 

  511. <a name="l00479"></a>00479   vu32 DCTRL;
    512. 

  512. <a name="l00480"></a>00480   vuc32 DCOUNT;
    513. 

  513. <a name="l00481"></a>00481   vuc32 STA;
    514. 

  514. <a name="l00482"></a>00482   vu32 ICR;
    515. 

  515. <a name="l00483"></a>00483   vu32 MASK;
    516. 

  516. <a name="l00484"></a>00484   u32  RESERVED0[2];
    517. 

  517. <a name="l00485"></a>00485   vuc32 FIFOCNT;
    518. 

  518. <a name="l00486"></a>00486   u32  RESERVED1[13];
    519. 

  519. <a name="l00487"></a>00487   vu32 FIFO;
    520. 

  520. <a name="l00488"></a>00488 } SDIO_TypeDef;
    521. 

  521. <a name="l00489"></a>00489 
    522. 

  522. <a name="l00490"></a>00490 <span class="comment">/*------------------------ Serial Peripheral Interface -----------------------*/</span>
    523. 

  523. <a name="l00491"></a>00491 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    524. 

  524. <a name="l00492"></a>00492 {
    525. 

  525. <a name="l00493"></a>00493   vu16 CR1;
    526. 

  526. <a name="l00494"></a>00494   u16  RESERVED0;
    527. 

  527. <a name="l00495"></a>00495   vu16 CR2;
    528. 

  528. <a name="l00496"></a>00496   u16  RESERVED1;
    529. 

  529. <a name="l00497"></a>00497   vu16 SR;
    530. 

  530. <a name="l00498"></a>00498   u16  RESERVED2;
    531. 

  531. <a name="l00499"></a>00499   vu16 DR;
    532. 

  532. <a name="l00500"></a>00500   u16  RESERVED3;
    533. 

  533. <a name="l00501"></a>00501   vu16 CRCPR;
    534. 

  534. <a name="l00502"></a>00502   u16  RESERVED4;
    535. 

  535. <a name="l00503"></a>00503   vu16 RXCRCR;
    536. 

  536. <a name="l00504"></a>00504   u16  RESERVED5;
    537. 

  537. <a name="l00505"></a>00505   vu16 TXCRCR;
    538. 

  538. <a name="l00506"></a>00506   u16  RESERVED6;
    539. 

  539. <a name="l00507"></a>00507   vu16 I2SCFGR;
    540. 

  540. <a name="l00508"></a>00508   u16  RESERVED7;
    541. 

  541. <a name="l00509"></a>00509   vu16 I2SPR;
    542. 

  542. <a name="l00510"></a>00510   u16  RESERVED8;  
    543. 

  543. <a name="l00511"></a>00511 } SPI_TypeDef;
    544. 

  544. <a name="l00512"></a>00512 
    545. 

  545. <a name="l00513"></a>00513 <span class="comment">/*------------------------ SystemTick ----------------------------------------*/</span>
    546. 

  546. <a name="l00514"></a>00514 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    547. 

  547. <a name="l00515"></a>00515 {
    548. 

  548. <a name="l00516"></a>00516   vu32 CTRL;
    549. 

  549. <a name="l00517"></a>00517   vu32 LOAD;
    550. 

  550. <a name="l00518"></a>00518   vu32 VAL;
    551. 

  551. <a name="l00519"></a>00519   vuc32 CALIB;
    552. 

  552. <a name="l00520"></a>00520 } SysTick_TypeDef;
    553. 

  553. <a name="l00521"></a>00521 
    554. 

  554. <a name="l00522"></a>00522 <span class="comment">/*------------------------ TIM -----------------------------------------------*/</span>
    555. 

  555. <a name="l00523"></a>00523 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    556. 

  556. <a name="l00524"></a>00524 {
    557. 

  557. <a name="l00525"></a>00525   vu16 CR1;
    558. 

  558. <a name="l00526"></a>00526   u16  RESERVED0;
    559. 

  559. <a name="l00527"></a>00527   vu16 CR2;
    560. 

  560. <a name="l00528"></a>00528   u16  RESERVED1;
    561. 

  561. <a name="l00529"></a>00529   vu16 SMCR;
    562. 

  562. <a name="l00530"></a>00530   u16  RESERVED2;
    563. 

  563. <a name="l00531"></a>00531   vu16 DIER;
    564. 

  564. <a name="l00532"></a>00532   u16  RESERVED3;
    565. 

  565. <a name="l00533"></a>00533   vu16 SR;
    566. 

  566. <a name="l00534"></a>00534   u16  RESERVED4;
    567. 

  567. <a name="l00535"></a>00535   vu16 EGR;
    568. 

  568. <a name="l00536"></a>00536   u16  RESERVED5;
    569. 

  569. <a name="l00537"></a>00537   vu16 CCMR1;
    570. 

  570. <a name="l00538"></a>00538   u16  RESERVED6;
    571. 

  571. <a name="l00539"></a>00539   vu16 CCMR2;
    572. 

  572. <a name="l00540"></a>00540   u16  RESERVED7;
    573. 

  573. <a name="l00541"></a>00541   vu16 CCER;
    574. 

  574. <a name="l00542"></a>00542   u16  RESERVED8;
    575. 

  575. <a name="l00543"></a>00543   vu16 CNT;
    576. 

  576. <a name="l00544"></a>00544   u16  RESERVED9;
    577. 

  577. <a name="l00545"></a>00545   vu16 PSC;
    578. 

  578. <a name="l00546"></a>00546   u16  RESERVED10;
    579. 

  579. <a name="l00547"></a>00547   vu16 ARR;
    580. 

  580. <a name="l00548"></a>00548   u16  RESERVED11;
    581. 

  581. <a name="l00549"></a>00549   vu16 RCR;
    582. 

  582. <a name="l00550"></a>00550   u16  RESERVED12;
    583. 

  583. <a name="l00551"></a>00551   vu16 CCR1;
    584. 

  584. <a name="l00552"></a>00552   u16  RESERVED13;
    585. 

  585. <a name="l00553"></a>00553   vu16 CCR2;
    586. 

  586. <a name="l00554"></a>00554   u16  RESERVED14;
    587. 

  587. <a name="l00555"></a>00555   vu16 CCR3;
    588. 

  588. <a name="l00556"></a>00556   u16  RESERVED15;
    589. 

  589. <a name="l00557"></a>00557   vu16 CCR4;
    590. 

  590. <a name="l00558"></a>00558   u16  RESERVED16;
    591. 

  591. <a name="l00559"></a>00559   vu16 BDTR;
    592. 

  592. <a name="l00560"></a>00560   u16  RESERVED17;
    593. 

  593. <a name="l00561"></a>00561   vu16 DCR;
    594. 

  594. <a name="l00562"></a>00562   u16  RESERVED18;
    595. 

  595. <a name="l00563"></a>00563   vu16 DMAR;
    596. 

  596. <a name="l00564"></a>00564   u16  RESERVED19;
    597. 

  597. <a name="l00565"></a>00565 } TIM_TypeDef;
    598. 

  598. <a name="l00566"></a>00566 
    599. 

  599. <a name="l00567"></a>00567 <span class="comment">/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/</span>
    600. 

  600. <a name="l00568"></a>00568 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    601. 

  601. <a name="l00569"></a>00569 {
    602. 

  602. <a name="l00570"></a>00570   vu16 SR;
    603. 

  603. <a name="l00571"></a>00571   u16  RESERVED0;
    604. 

  604. <a name="l00572"></a>00572   vu16 DR;
    605. 

  605. <a name="l00573"></a>00573   u16  RESERVED1;
    606. 

  606. <a name="l00574"></a>00574   vu16 BRR;
    607. 

  607. <a name="l00575"></a>00575   u16  RESERVED2;
    608. 

  608. <a name="l00576"></a>00576   vu16 CR1;
    609. 

  609. <a name="l00577"></a>00577   u16  RESERVED3;
    610. 

  610. <a name="l00578"></a>00578   vu16 CR2;
    611. 

  611. <a name="l00579"></a>00579   u16  RESERVED4;
    612. 

  612. <a name="l00580"></a>00580   vu16 CR3;
    613. 

  613. <a name="l00581"></a>00581   u16  RESERVED5;
    614. 

  614. <a name="l00582"></a>00582   vu16 GTPR;
    615. 

  615. <a name="l00583"></a>00583   u16  RESERVED6;
    616. 

  616. <a name="l00584"></a>00584 } USART_TypeDef;
    617. 

  617. <a name="l00585"></a>00585 
    618. 

  618. <a name="l00586"></a>00586 <span class="comment">/*------------------------ Window WATCHDOG -----------------------------------*/</span>
    619. 

  619. <a name="l00587"></a>00587 <span class="keyword">typedef</span> <span class="keyword">struct</span>
    620. 

  620. <a name="l00588"></a>00588 {
    621. 

  621. <a name="l00589"></a>00589   vu32 CR;
    622. 

  622. <a name="l00590"></a>00590   vu32 CFR;
    623. 

  623. <a name="l00591"></a>00591   vu32 SR;
    624. 

  624. <a name="l00592"></a>00592 } WWDG_TypeDef;
    625. 

  625. <a name="l00593"></a>00593 
    626. 

  626. <a name="l00594"></a>00594 <span class="comment">/******************************************************************************/</span>
    627. 

  627. <a name="l00595"></a>00595 <span class="comment">/*                         Peripheral memory map                              */</span>
    628. 

  628. <a name="l00596"></a>00596 <span class="comment">/******************************************************************************/</span>
    629. 

  629. <a name="l00597"></a>00597 <span class="comment">/* Peripheral and SRAM base address in the alias region */</span>
    630. 

  630. <a name="l00598"></a>00598 <span class="preprocessor">#define PERIPH_BB_BASE        ((u32)0x42000000)</span>
    631. 

  631. <a name="l00599"></a>00599 <span class="preprocessor"></span><span class="preprocessor">#define SRAM_BB_BASE          ((u32)0x22000000)</span>
    632. 

  632. <a name="l00600"></a>00600 <span class="preprocessor"></span>
    633. 

  633. <a name="l00601"></a>00601 <span class="comment">/* Peripheral and SRAM base address in the bit-band region */</span>
    634. 

  634. <a name="l00602"></a>00602 <span class="preprocessor">#define SRAM_BASE             ((u32)0x20000000)</span>
    635. 

  635. <a name="l00603"></a>00603 <span class="preprocessor"></span><span class="preprocessor">#define PERIPH_BASE           ((u32)0x40000000)</span>
    636. 

  636. <a name="l00604"></a>00604 <span class="preprocessor"></span>
    637. 

  637. <a name="l00605"></a>00605 <span class="comment">/* FSMC registers base address */</span>
    638. 

  638. <a name="l00606"></a>00606 <span class="preprocessor">#define FSMC_R_BASE           ((u32)0xA0000000)</span>
    639. 

  639. <a name="l00607"></a>00607 <span class="preprocessor"></span>
    640. 

  640. <a name="l00608"></a>00608 <span class="comment">/* Peripheral memory map */</span>
    641. 

  641. <a name="l00609"></a>00609 <span class="preprocessor">#define APB1PERIPH_BASE       PERIPH_BASE</span>
    642. 

  642. <a name="l00610"></a>00610 <span class="preprocessor"></span><span class="preprocessor">#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)</span>
    643. 

  643. <a name="l00611"></a>00611 <span class="preprocessor"></span><span class="preprocessor">#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)</span>
    644. 

  644. <a name="l00612"></a>00612 <span class="preprocessor"></span>
    645. 

  645. <a name="l00613"></a>00613 <span class="preprocessor">#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)</span>
    646. 

  646. <a name="l00614"></a>00614 <span class="preprocessor"></span><span class="preprocessor">#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)</span>
    647. 

  647. <a name="l00615"></a>00615 <span class="preprocessor"></span><span class="preprocessor">#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)</span>
    648. 

  648. <a name="l00616"></a>00616 <span class="preprocessor"></span><span class="preprocessor">#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)</span>
    649. 

  649. <a name="l00617"></a>00617 <span class="preprocessor"></span><span class="preprocessor">#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)</span>
    650. 

  650. <a name="l00618"></a>00618 <span class="preprocessor"></span><span class="preprocessor">#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)</span>
    651. 

  651. <a name="l00619"></a>00619 <span class="preprocessor"></span><span class="preprocessor">#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)</span>
    652. 

  652. <a name="l00620"></a>00620 <span class="preprocessor"></span><span class="preprocessor">#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)</span>
    653. 

  653. <a name="l00621"></a>00621 <span class="preprocessor"></span><span class="preprocessor">#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)</span>
    654. 

  654. <a name="l00622"></a>00622 <span class="preprocessor"></span><span class="preprocessor">#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)</span>
    655. 

  655. <a name="l00623"></a>00623 <span class="preprocessor"></span><span class="preprocessor">#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)</span>
    656. 

  656. <a name="l00624"></a>00624 <span class="preprocessor"></span><span class="preprocessor">#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)</span>
    657. 

  657. <a name="l00625"></a>00625 <span class="preprocessor"></span><span class="preprocessor">#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)</span>
    658. 

  658. <a name="l00626"></a>00626 <span class="preprocessor"></span><span class="preprocessor">#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)</span>
    659. 

  659. <a name="l00627"></a>00627 <span class="preprocessor"></span><span class="preprocessor">#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)</span>
    660. 

  660. <a name="l00628"></a>00628 <span class="preprocessor"></span><span class="preprocessor">#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)</span>
    661. 

  661. <a name="l00629"></a>00629 <span class="preprocessor"></span><span class="preprocessor">#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)</span>
    662. 

  662. <a name="l00630"></a>00630 <span class="preprocessor"></span><span class="preprocessor">#define CAN_BASE              (APB1PERIPH_BASE + 0x6400)</span>
    663. 

  663. <a name="l00631"></a>00631 <span class="preprocessor"></span><span class="preprocessor">#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)</span>
    664. 

  664. <a name="l00632"></a>00632 <span class="preprocessor"></span><span class="preprocessor">#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)</span>
    665. 

  665. <a name="l00633"></a>00633 <span class="preprocessor"></span><span class="preprocessor">#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)</span>
    666. 

  666. <a name="l00634"></a>00634 <span class="preprocessor"></span>
    667. 

  667. <a name="l00635"></a>00635 <span class="preprocessor">#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)</span>
    668. 

  668. <a name="l00636"></a>00636 <span class="preprocessor"></span><span class="preprocessor">#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)</span>
    669. 

  669. <a name="l00637"></a>00637 <span class="preprocessor"></span><span class="preprocessor">#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)</span>
    670. 

  670. <a name="l00638"></a>00638 <span class="preprocessor"></span><span class="preprocessor">#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)</span>
    671. 

  671. <a name="l00639"></a>00639 <span class="preprocessor"></span><span class="preprocessor">#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)</span>
    672. 

  672. <a name="l00640"></a>00640 <span class="preprocessor"></span><span class="preprocessor">#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)</span>
    673. 

  673. <a name="l00641"></a>00641 <span class="preprocessor"></span><span class="preprocessor">#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)</span>
    674. 

  674. <a name="l00642"></a>00642 <span class="preprocessor"></span><span class="preprocessor">#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)</span>
    675. 

  675. <a name="l00643"></a>00643 <span class="preprocessor"></span><span class="preprocessor">#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)</span>
    676. 

  676. <a name="l00644"></a>00644 <span class="preprocessor"></span><span class="preprocessor">#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)</span>
    677. 

  677. <a name="l00645"></a>00645 <span class="preprocessor"></span><span class="preprocessor">#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)</span>
    678. 

  678. <a name="l00646"></a>00646 <span class="preprocessor"></span><span class="preprocessor">#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)</span>
    679. 

  679. <a name="l00647"></a>00647 <span class="preprocessor"></span><span class="preprocessor">#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)</span>
    680. 

  680. <a name="l00648"></a>00648 <span class="preprocessor"></span><span class="preprocessor">#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)</span>
    681. 

  681. <a name="l00649"></a>00649 <span class="preprocessor"></span><span class="preprocessor">#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)</span>
    682. 

  682. <a name="l00650"></a>00650 <span class="preprocessor"></span><span class="preprocessor">#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)</span>
    683. 

  683. <a name="l00651"></a>00651 <span class="preprocessor"></span>
    684. 

  684. <a name="l00652"></a>00652 <span class="preprocessor">#define SDIO_BASE             (PERIPH_BASE + 0x18000)</span>
    685. 

  685. <a name="l00653"></a>00653 <span class="preprocessor"></span>
    686. 

  686. <a name="l00654"></a>00654 <span class="preprocessor">#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)</span>
    687. 

  687. <a name="l00655"></a>00655 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)</span>
    688. 

  688. <a name="l00656"></a>00656 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)</span>
    689. 

  689. <a name="l00657"></a>00657 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)</span>
    690. 

  690. <a name="l00658"></a>00658 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)</span>
    691. 

  691. <a name="l00659"></a>00659 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)</span>
    692. 

  692. <a name="l00660"></a>00660 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)</span>
    693. 

  693. <a name="l00661"></a>00661 <span class="preprocessor"></span><span class="preprocessor">#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)</span>
    694. 

  694. <a name="l00662"></a>00662 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)</span>
    695. 

  695. <a name="l00663"></a>00663 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)</span>
    696. 

  696. <a name="l00664"></a>00664 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)</span>
    697. 

  697. <a name="l00665"></a>00665 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)</span>
    698. 

  698. <a name="l00666"></a>00666 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)</span>
    699. 

  699. <a name="l00667"></a>00667 <span class="preprocessor"></span><span class="preprocessor">#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)</span>
    700. 

  700. <a name="l00668"></a>00668 <span class="preprocessor"></span><span class="preprocessor">#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)</span>
    701. 

  701. <a name="l00669"></a>00669 <span class="preprocessor"></span><span class="preprocessor">#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)</span>
    702. 

  702. <a name="l00670"></a>00670 <span class="preprocessor"></span>
    703. 

  703. <a name="l00671"></a>00671 <span class="comment">/* Flash registers base address */</span>
    704. 

  704. <a name="l00672"></a>00672 <span class="preprocessor">#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000)</span>
    705. 

  705. <a name="l00673"></a>00673 <span class="preprocessor"></span><span class="comment">/* Flash Option Bytes base address */</span>
    706. 

  706. <a name="l00674"></a>00674 <span class="preprocessor">#define OB_BASE               ((u32)0x1FFFF800)</span>
    707. 

  707. <a name="l00675"></a>00675 <span class="preprocessor"></span>
    708. 

  708. <a name="l00676"></a>00676 <span class="comment">/* FSMC Bankx registers base address */</span>
    709. 

  709. <a name="l00677"></a>00677 <span class="preprocessor">#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)</span>
    710. 

  710. <a name="l00678"></a>00678 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)</span>
    711. 

  711. <a name="l00679"></a>00679 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)</span>
    712. 

  712. <a name="l00680"></a>00680 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)</span>
    713. 

  713. <a name="l00681"></a>00681 <span class="preprocessor"></span><span class="preprocessor">#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)</span>
    714. 

  714. <a name="l00682"></a>00682 <span class="preprocessor"></span>
    715. 

  715. <a name="l00683"></a>00683 <span class="comment">/* Debug MCU registers base address */</span>
    716. 

  716. <a name="l00684"></a>00684 <span class="preprocessor">#define DBGMCU_BASE          ((u32)0xE0042000)</span>
    717. 

  717. <a name="l00685"></a>00685 <span class="preprocessor"></span>
    718. 

  718. <a name="l00686"></a>00686 <span class="comment">/* System Control Space memory map */</span>
    719. 

  719. <a name="l00687"></a>00687 <span class="preprocessor">#define SCS_BASE              ((u32)0xE000E000)</span>
    720. 

  720. <a name="l00688"></a>00688 <span class="preprocessor"></span>
    721. 

  721. <a name="l00689"></a>00689 <span class="preprocessor">#define SysTick_BASE          (SCS_BASE + 0x0010)</span>
    722. 

  722. <a name="l00690"></a>00690 <span class="preprocessor"></span><span class="preprocessor">#define NVIC_BASE             (SCS_BASE + 0x0100)</span>
    723. 

  723. <a name="l00691"></a>00691 <span class="preprocessor"></span><span class="preprocessor">#define SCB_BASE              (SCS_BASE + 0x0D00)</span>
    724. 

  724. <a name="l00692"></a>00692 <span class="preprocessor"></span>
    725. 

  725. <a name="l00693"></a>00693 <span class="comment">/******************************************************************************/</span>
    726. 

  726. <a name="l00694"></a>00694 <span class="comment">/*                         Peripheral declaration                             */</span>
    727. 

  727. <a name="l00695"></a>00695 <span class="comment">/******************************************************************************/</span>
    728. 

  728. <a name="l00696"></a>00696 
    729. 

  729. <a name="l00697"></a>00697 <span class="comment">/*------------------------ Non Debug Mode ------------------------------------*/</span>
    730. 

  730. <a name="l00698"></a>00698 <span class="preprocessor">#ifndef DEBUG</span>
    731. 

  731. <a name="l00699"></a>00699 <span class="preprocessor"></span><span class="preprocessor">#ifdef _TIM2</span>
    732. 

  732. <a name="l00700"></a>00700 <span class="preprocessor"></span><span class="preprocessor">  #define TIM2                ((TIM_TypeDef *) TIM2_BASE)</span>
    733. 

  733. <a name="l00701"></a>00701 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM2 */</span>
    734. 

  734. <a name="l00702"></a>00702 
    735. 

  735. <a name="l00703"></a>00703 <span class="preprocessor">#ifdef _TIM3</span>
    736. 

  736. <a name="l00704"></a>00704 <span class="preprocessor"></span><span class="preprocessor">  #define TIM3                ((TIM_TypeDef *) TIM3_BASE)</span>
    737. 

  737. <a name="l00705"></a>00705 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM3 */</span>
    738. 

  738. <a name="l00706"></a>00706 
    739. 

  739. <a name="l00707"></a>00707 <span class="preprocessor">#ifdef _TIM4</span>
    740. 

  740. <a name="l00708"></a>00708 <span class="preprocessor"></span><span class="preprocessor">  #define TIM4                ((TIM_TypeDef *) TIM4_BASE)</span>
    741. 

  741. <a name="l00709"></a>00709 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM4 */</span>
    742. 

  742. <a name="l00710"></a>00710 
    743. 

  743. <a name="l00711"></a>00711 <span class="preprocessor">#ifdef _TIM5</span>
    744. 

  744. <a name="l00712"></a>00712 <span class="preprocessor"></span><span class="preprocessor">  #define TIM5                ((TIM_TypeDef *) TIM5_BASE)</span>
    745. 

  745. <a name="l00713"></a>00713 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM5 */</span>
    746. 

  746. <a name="l00714"></a>00714 
    747. 

  747. <a name="l00715"></a>00715 <span class="preprocessor">#ifdef _TIM6</span>
    748. 

  748. <a name="l00716"></a>00716 <span class="preprocessor"></span><span class="preprocessor">  #define TIM6                ((TIM_TypeDef *) TIM6_BASE)</span>
    749. 

  749. <a name="l00717"></a>00717 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM6 */</span>
    750. 

  750. <a name="l00718"></a>00718 
    751. 

  751. <a name="l00719"></a>00719 <span class="preprocessor">#ifdef _TIM7</span>
    752. 

  752. <a name="l00720"></a>00720 <span class="preprocessor"></span><span class="preprocessor">  #define TIM7                ((TIM_TypeDef *) TIM7_BASE)</span>
    753. 

  753. <a name="l00721"></a>00721 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM7 */</span>
    754. 

  754. <a name="l00722"></a>00722 
    755. 

  755. <a name="l00723"></a>00723 <span class="preprocessor">#ifdef _RTC</span>
    756. 

  756. <a name="l00724"></a>00724 <span class="preprocessor"></span><span class="preprocessor">  #define RTC                 ((RTC_TypeDef *) RTC_BASE)</span>
    757. 

  757. <a name="l00725"></a>00725 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_RTC */</span>
    758. 

  758. <a name="l00726"></a>00726 
    759. 

  759. <a name="l00727"></a>00727 <span class="preprocessor">#ifdef _WWDG</span>
    760. 

  760. <a name="l00728"></a>00728 <span class="preprocessor"></span><span class="preprocessor">  #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)</span>
    761. 

  761. <a name="l00729"></a>00729 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_WWDG */</span>
    762. 

  762. <a name="l00730"></a>00730 
    763. 

  763. <a name="l00731"></a>00731 <span class="preprocessor">#ifdef _IWDG</span>
    764. 

  764. <a name="l00732"></a>00732 <span class="preprocessor"></span><span class="preprocessor">  #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)</span>
    765. 

  765. <a name="l00733"></a>00733 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_IWDG */</span>
    766. 

  766. <a name="l00734"></a>00734 
    767. 

  767. <a name="l00735"></a>00735 <span class="preprocessor">#ifdef _SPI2</span>
    768. 

  768. <a name="l00736"></a>00736 <span class="preprocessor"></span><span class="preprocessor">  #define SPI2                ((SPI_TypeDef *) SPI2_BASE)</span>
    769. 

  769. <a name="l00737"></a>00737 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SPI2 */</span>
    770. 

  770. <a name="l00738"></a>00738 
    771. 

  771. <a name="l00739"></a>00739 <span class="preprocessor">#ifdef _SPI3</span>
    772. 

  772. <a name="l00740"></a>00740 <span class="preprocessor"></span><span class="preprocessor">  #define SPI3                ((SPI_TypeDef *) SPI3_BASE)</span>
    773. 

  773. <a name="l00741"></a>00741 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SPI3 */</span>
    774. 

  774. <a name="l00742"></a>00742 
    775. 

  775. <a name="l00743"></a>00743 <span class="preprocessor">#ifdef _USART2</span>
    776. 

  776. <a name="l00744"></a>00744 <span class="preprocessor"></span><span class="preprocessor">  #define USART2              ((USART_TypeDef *) USART2_BASE)</span>
    777. 

  777. <a name="l00745"></a>00745 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_USART2 */</span>
    778. 

  778. <a name="l00746"></a>00746 
    779. 

  779. <a name="l00747"></a>00747 <span class="preprocessor">#ifdef _USART3</span>
    780. 

  780. <a name="l00748"></a>00748 <span class="preprocessor"></span><span class="preprocessor">  #define USART3              ((USART_TypeDef *) USART3_BASE)</span>
    781. 

  781. <a name="l00749"></a>00749 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_USART3 */</span>
    782. 

  782. <a name="l00750"></a>00750 
    783. 

  783. <a name="l00751"></a>00751 <span class="preprocessor">#ifdef _UART4</span>
    784. 

  784. <a name="l00752"></a>00752 <span class="preprocessor"></span><span class="preprocessor">  #define UART4              ((USART_TypeDef *) UART4_BASE)</span>
    785. 

  785. <a name="l00753"></a>00753 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_UART4 */</span>
    786. 

  786. <a name="l00754"></a>00754 
    787. 

  787. <a name="l00755"></a>00755 <span class="preprocessor">#ifdef _UART5</span>
    788. 

  788. <a name="l00756"></a>00756 <span class="preprocessor"></span><span class="preprocessor">  #define UART5              ((USART_TypeDef *) UART5_BASE)</span>
    789. 

  789. <a name="l00757"></a>00757 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_USART5 */</span>
    790. 

  790. <a name="l00758"></a>00758 
    791. 

  791. <a name="l00759"></a>00759 <span class="preprocessor">#ifdef _I2C1</span>
    792. 

  792. <a name="l00760"></a>00760 <span class="preprocessor"></span><span class="preprocessor">  #define I2C1                ((I2C_TypeDef *) I2C1_BASE)</span>
    793. 

  793. <a name="l00761"></a>00761 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_I2C1 */</span>
    794. 

  794. <a name="l00762"></a>00762 
    795. 

  795. <a name="l00763"></a>00763 <span class="preprocessor">#ifdef _I2C2</span>
    796. 

  796. <a name="l00764"></a>00764 <span class="preprocessor"></span><span class="preprocessor">  #define I2C2                ((I2C_TypeDef *) I2C2_BASE)</span>
    797. 

  797. <a name="l00765"></a>00765 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_I2C2 */</span>
    798. 

  798. <a name="l00766"></a>00766 
    799. 

  799. <a name="l00767"></a>00767 <span class="preprocessor">#ifdef _CAN</span>
    800. 

  800. <a name="l00768"></a>00768 <span class="preprocessor"></span><span class="preprocessor">  #define CAN                 ((CAN_TypeDef *) CAN_BASE)</span>
    801. 

  801. <a name="l00769"></a>00769 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_CAN */</span>
    802. 

  802. <a name="l00770"></a>00770 
    803. 

  803. <a name="l00771"></a>00771 <span class="preprocessor">#ifdef _BKP</span>
    804. 

  804. <a name="l00772"></a>00772 <span class="preprocessor"></span><span class="preprocessor">  #define BKP                 ((BKP_TypeDef *) BKP_BASE)</span>
    805. 

  805. <a name="l00773"></a>00773 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_BKP */</span>
    806. 

  806. <a name="l00774"></a>00774 
    807. 

  807. <a name="l00775"></a>00775 <span class="preprocessor">#ifdef _PWR</span>
    808. 

  808. <a name="l00776"></a>00776 <span class="preprocessor"></span><span class="preprocessor">  #define PWR                 ((PWR_TypeDef *) PWR_BASE)</span>
    809. 

  809. <a name="l00777"></a>00777 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_PWR */</span>
    810. 

  810. <a name="l00778"></a>00778 
    811. 

  811. <a name="l00779"></a>00779 <span class="preprocessor">#ifdef _DAC</span>
    812. 

  812. <a name="l00780"></a>00780 <span class="preprocessor"></span><span class="preprocessor">  #define DAC                 ((DAC_TypeDef *) DAC_BASE)</span>
    813. 

  813. <a name="l00781"></a>00781 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DAC */</span>
    814. 

  814. <a name="l00782"></a>00782 
    815. 

  815. <a name="l00783"></a>00783 <span class="preprocessor">#ifdef _AFIO</span>
    816. 

  816. <a name="l00784"></a>00784 <span class="preprocessor"></span><span class="preprocessor">  #define AFIO                ((AFIO_TypeDef *) AFIO_BASE)</span>
    817. 

  817. <a name="l00785"></a>00785 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_AFIO */</span>
    818. 

  818. <a name="l00786"></a>00786 
    819. 

  819. <a name="l00787"></a>00787 <span class="preprocessor">#ifdef _EXTI</span>
    820. 

  820. <a name="l00788"></a>00788 <span class="preprocessor"></span><span class="preprocessor">  #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)</span>
    821. 

  821. <a name="l00789"></a>00789 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_EXTI */</span>
    822. 

  822. <a name="l00790"></a>00790 
    823. 

  823. <a name="l00791"></a>00791 <span class="preprocessor">#ifdef _GPIOA</span>
    824. 

  824. <a name="l00792"></a>00792 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)</span>
    825. 

  825. <a name="l00793"></a>00793 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOA */</span>
    826. 

  826. <a name="l00794"></a>00794 
    827. 

  827. <a name="l00795"></a>00795 <span class="preprocessor">#ifdef _GPIOB</span>
    828. 

  828. <a name="l00796"></a>00796 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)</span>
    829. 

  829. <a name="l00797"></a>00797 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOB */</span>
    830. 

  830. <a name="l00798"></a>00798 
    831. 

  831. <a name="l00799"></a>00799 <span class="preprocessor">#ifdef _GPIOC</span>
    832. 

  832. <a name="l00800"></a>00800 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)</span>
    833. 

  833. <a name="l00801"></a>00801 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOC */</span>
    834. 

  834. <a name="l00802"></a>00802 
    835. 

  835. <a name="l00803"></a>00803 <span class="preprocessor">#ifdef _GPIOD</span>
    836. 

  836. <a name="l00804"></a>00804 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)</span>
    837. 

  837. <a name="l00805"></a>00805 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOD */</span>
    838. 

  838. <a name="l00806"></a>00806 
    839. 

  839. <a name="l00807"></a>00807 <span class="preprocessor">#ifdef _GPIOE</span>
    840. 

  840. <a name="l00808"></a>00808 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)</span>
    841. 

  841. <a name="l00809"></a>00809 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOE */</span>
    842. 

  842. <a name="l00810"></a>00810 
    843. 

  843. <a name="l00811"></a>00811 <span class="preprocessor">#ifdef _GPIOF</span>
    844. 

  844. <a name="l00812"></a>00812 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)</span>
    845. 

  845. <a name="l00813"></a>00813 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOF */</span>
    846. 

  846. <a name="l00814"></a>00814 
    847. 

  847. <a name="l00815"></a>00815 <span class="preprocessor">#ifdef _GPIOG</span>
    848. 

  848. <a name="l00816"></a>00816 <span class="preprocessor"></span><span class="preprocessor">  #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)</span>
    849. 

  849. <a name="l00817"></a>00817 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_GPIOG */</span>
    850. 

  850. <a name="l00818"></a>00818 
    851. 

  851. <a name="l00819"></a>00819 <span class="preprocessor">#ifdef _ADC1</span>
    852. 

  852. <a name="l00820"></a>00820 <span class="preprocessor"></span><span class="preprocessor">  #define ADC1                ((ADC_TypeDef *) ADC1_BASE)</span>
    853. 

  853. <a name="l00821"></a>00821 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_ADC1 */</span>
    854. 

  854. <a name="l00822"></a>00822 
    855. 

  855. <a name="l00823"></a>00823 <span class="preprocessor">#ifdef _ADC2</span>
    856. 

  856. <a name="l00824"></a>00824 <span class="preprocessor"></span><span class="preprocessor">  #define ADC2                ((ADC_TypeDef *) ADC2_BASE)</span>
    857. 

  857. <a name="l00825"></a>00825 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_ADC2 */</span>
    858. 

  858. <a name="l00826"></a>00826 
    859. 

  859. <a name="l00827"></a>00827 <span class="preprocessor">#ifdef _TIM1</span>
    860. 

  860. <a name="l00828"></a>00828 <span class="preprocessor"></span><span class="preprocessor">  #define TIM1                ((TIM_TypeDef *) TIM1_BASE)</span>
    861. 

  861. <a name="l00829"></a>00829 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM1 */</span>
    862. 

  862. <a name="l00830"></a>00830 
    863. 

  863. <a name="l00831"></a>00831 <span class="preprocessor">#ifdef _SPI1</span>
    864. 

  864. <a name="l00832"></a>00832 <span class="preprocessor"></span><span class="preprocessor">  #define SPI1                ((SPI_TypeDef *) SPI1_BASE)</span>
    865. 

  865. <a name="l00833"></a>00833 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SPI1 */</span>
    866. 

  866. <a name="l00834"></a>00834 
    867. 

  867. <a name="l00835"></a>00835 <span class="preprocessor">#ifdef _TIM8</span>
    868. 

  868. <a name="l00836"></a>00836 <span class="preprocessor"></span><span class="preprocessor">  #define TIM8                ((TIM_TypeDef *) TIM8_BASE)</span>
    869. 

  869. <a name="l00837"></a>00837 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_TIM8 */</span>
    870. 

  870. <a name="l00838"></a>00838 
    871. 

  871. <a name="l00839"></a>00839 <span class="preprocessor">#ifdef _USART1</span>
    872. 

  872. <a name="l00840"></a>00840 <span class="preprocessor"></span><span class="preprocessor">  #define USART1              ((USART_TypeDef *) USART1_BASE)</span>
    873. 

  873. <a name="l00841"></a>00841 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_USART1 */</span>
    874. 

  874. <a name="l00842"></a>00842 
    875. 

  875. <a name="l00843"></a>00843 <span class="preprocessor">#ifdef _ADC3</span>
    876. 

  876. <a name="l00844"></a>00844 <span class="preprocessor"></span><span class="preprocessor">  #define ADC3                ((ADC_TypeDef *) ADC3_BASE)</span>
    877. 

  877. <a name="l00845"></a>00845 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_ADC3 */</span>
    878. 

  878. <a name="l00846"></a>00846 
    879. 

  879. <a name="l00847"></a>00847 <span class="preprocessor">#ifdef _SDIO</span>
    880. 

  880. <a name="l00848"></a>00848 <span class="preprocessor"></span><span class="preprocessor">  #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)</span>
    881. 

  881. <a name="l00849"></a>00849 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SDIO */</span>
    882. 

  882. <a name="l00850"></a>00850 
    883. 

  883. <a name="l00851"></a>00851 <span class="preprocessor">#ifdef _DMA</span>
    884. 

  884. <a name="l00852"></a>00852 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1                ((DMA_TypeDef *) DMA1_BASE)</span>
    885. 

  885. <a name="l00853"></a>00853 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2                ((DMA_TypeDef *) DMA2_BASE)</span>
    886. 

  886. <a name="l00854"></a>00854 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA */</span>
    887. 

  887. <a name="l00855"></a>00855 
    888. 

  888. <a name="l00856"></a>00856 <span class="preprocessor">#ifdef _DMA1_Channel1</span>
    889. 

  889. <a name="l00857"></a>00857 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)</span>
    890. 

  890. <a name="l00858"></a>00858 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel1 */</span>
    891. 

  891. <a name="l00859"></a>00859 
    892. 

  892. <a name="l00860"></a>00860 <span class="preprocessor">#ifdef _DMA1_Channel2</span>
    893. 

  893. <a name="l00861"></a>00861 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)</span>
    894. 

  894. <a name="l00862"></a>00862 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel2 */</span>
    895. 

  895. <a name="l00863"></a>00863 
    896. 

  896. <a name="l00864"></a>00864 <span class="preprocessor">#ifdef _DMA1_Channel3</span>
    897. 

  897. <a name="l00865"></a>00865 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)</span>
    898. 

  898. <a name="l00866"></a>00866 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel3 */</span>
    899. 

  899. <a name="l00867"></a>00867 
    900. 

  900. <a name="l00868"></a>00868 <span class="preprocessor">#ifdef _DMA1_Channel4</span>
    901. 

  901. <a name="l00869"></a>00869 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)</span>
    902. 

  902. <a name="l00870"></a>00870 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel4 */</span>
    903. 

  903. <a name="l00871"></a>00871 
    904. 

  904. <a name="l00872"></a>00872 <span class="preprocessor">#ifdef _DMA1_Channel5</span>
    905. 

  905. <a name="l00873"></a>00873 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)</span>
    906. 

  906. <a name="l00874"></a>00874 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel5 */</span>
    907. 

  907. <a name="l00875"></a>00875 
    908. 

  908. <a name="l00876"></a>00876 <span class="preprocessor">#ifdef _DMA1_Channel6</span>
    909. 

  909. <a name="l00877"></a>00877 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)</span>
    910. 

  910. <a name="l00878"></a>00878 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel6 */</span>
    911. 

  911. <a name="l00879"></a>00879 
    912. 

  912. <a name="l00880"></a>00880 <span class="preprocessor">#ifdef _DMA1_Channel7</span>
    913. 

  913. <a name="l00881"></a>00881 <span class="preprocessor"></span><span class="preprocessor">  #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)</span>
    914. 

  914. <a name="l00882"></a>00882 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel7 */</span>
    915. 

  915. <a name="l00883"></a>00883 
    916. 

  916. <a name="l00884"></a>00884 <span class="preprocessor">#ifdef _DMA2_Channel1</span>
    917. 

  917. <a name="l00885"></a>00885 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)</span>
    918. 

  918. <a name="l00886"></a>00886 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel1 */</span>
    919. 

  919. <a name="l00887"></a>00887 
    920. 

  920. <a name="l00888"></a>00888 <span class="preprocessor">#ifdef _DMA2_Channel2</span>
    921. 

  921. <a name="l00889"></a>00889 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)</span>
    922. 

  922. <a name="l00890"></a>00890 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel2 */</span>
    923. 

  923. <a name="l00891"></a>00891 
    924. 

  924. <a name="l00892"></a>00892 <span class="preprocessor">#ifdef _DMA2_Channel3</span>
    925. 

  925. <a name="l00893"></a>00893 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)</span>
    926. 

  926. <a name="l00894"></a>00894 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel3 */</span>
    927. 

  927. <a name="l00895"></a>00895 
    928. 

  928. <a name="l00896"></a>00896 <span class="preprocessor">#ifdef _DMA2_Channel4</span>
    929. 

  929. <a name="l00897"></a>00897 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)</span>
    930. 

  930. <a name="l00898"></a>00898 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel4 */</span>
    931. 

  931. <a name="l00899"></a>00899 
    932. 

  932. <a name="l00900"></a>00900 <span class="preprocessor">#ifdef _DMA2_Channel5</span>
    933. 

  933. <a name="l00901"></a>00901 <span class="preprocessor"></span><span class="preprocessor">  #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)</span>
    934. 

  934. <a name="l00902"></a>00902 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel5 */</span>
    935. 

  935. <a name="l00903"></a>00903 
    936. 

  936. <a name="l00904"></a>00904 <span class="preprocessor">#ifdef _RCC</span>
    937. 

  937. <a name="l00905"></a>00905 <span class="preprocessor"></span><span class="preprocessor">  #define RCC                 ((RCC_TypeDef *) RCC_BASE)</span>
    938. 

  938. <a name="l00906"></a>00906 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_RCC */</span>
    939. 

  939. <a name="l00907"></a>00907 
    940. 

  940. <a name="l00908"></a>00908 <span class="preprocessor">#ifdef _CRC</span>
    941. 

  941. <a name="l00909"></a>00909 <span class="preprocessor"></span><span class="preprocessor">  #define CRC                 ((CRC_TypeDef *) CRC_BASE)</span>
    942. 

  942. <a name="l00910"></a>00910 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_CRC */</span>
    943. 

  943. <a name="l00911"></a>00911 
    944. 

  944. <a name="l00912"></a>00912 <span class="preprocessor">#ifdef _FLASH</span>
    945. 

  945. <a name="l00913"></a>00913 <span class="preprocessor"></span><span class="preprocessor">  #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)</span>
    946. 

  946. <a name="l00914"></a>00914 <span class="preprocessor"></span><span class="preprocessor">  #define OB                  ((OB_TypeDef *) OB_BASE) </span>
    947. 

  947. <a name="l00915"></a>00915 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_FLASH */</span>
    948. 

  948. <a name="l00916"></a>00916 
    949. 

  949. <a name="l00917"></a>00917 <span class="preprocessor">#ifdef _FSMC</span>
    950. 

  950. <a name="l00918"></a>00918 <span class="preprocessor"></span><span class="preprocessor">  #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)</span>
    951. 

  951. <a name="l00919"></a>00919 <span class="preprocessor"></span><span class="preprocessor">  #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)</span>
    952. 

  952. <a name="l00920"></a>00920 <span class="preprocessor"></span><span class="preprocessor">  #define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)</span>
    953. 

  953. <a name="l00921"></a>00921 <span class="preprocessor"></span><span class="preprocessor">  #define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)</span>
    954. 

  954. <a name="l00922"></a>00922 <span class="preprocessor"></span><span class="preprocessor">  #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)</span>
    955. 

  955. <a name="l00923"></a>00923 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_FSMC */</span>
    956. 

  956. <a name="l00924"></a>00924 
    957. 

  957. <a name="l00925"></a>00925 <span class="preprocessor">#ifdef _DBGMCU</span>
    958. 

  958. <a name="l00926"></a>00926 <span class="preprocessor"></span><span class="preprocessor">  #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)</span>
    959. 

  959. <a name="l00927"></a>00927 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_DBGMCU */</span>
    960. 

  960. <a name="l00928"></a>00928 
    961. 

  961. <a name="l00929"></a>00929 <span class="preprocessor">#ifdef _SysTick</span>
    962. 

  962. <a name="l00930"></a>00930 <span class="preprocessor"></span><span class="preprocessor">  #define SysTick             ((SysTick_TypeDef *) SysTick_BASE)</span>
    963. 

  963. <a name="l00931"></a>00931 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_SysTick */</span>
    964. 

  964. <a name="l00932"></a>00932 
    965. 

  965. <a name="l00933"></a>00933 <span class="preprocessor">#ifdef _NVIC</span>
    966. 

  966. <a name="l00934"></a>00934 <span class="preprocessor"></span><span class="preprocessor">  #define NVIC                ((NVIC_TypeDef *) NVIC_BASE)</span>
    967. 

  967. <a name="l00935"></a>00935 <span class="preprocessor"></span><span class="preprocessor">  #define SCB                 ((SCB_TypeDef *) SCB_BASE)  </span>
    968. 

  968. <a name="l00936"></a>00936 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/*_NVIC */</span>
    969. 

  969. <a name="l00937"></a>00937 
    970. 

  970. <a name="l00938"></a>00938 <span class="comment">/*------------------------ Debug Mode ----------------------------------------*/</span>
    971. 

  971. <a name="l00939"></a>00939 <span class="preprocessor">#else   </span><span class="comment">/* DEBUG */</span>
    972. 

  972. <a name="l00940"></a>00940 <span class="preprocessor">#ifdef _TIM2</span>
    973. 

  973. <a name="l00941"></a>00941 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM2;
    974. 

  974. <a name="l00942"></a>00942 <span class="preprocessor">#endif </span><span class="comment">/*_TIM2 */</span>
    975. 

  975. <a name="l00943"></a>00943 
    976. 

  976. <a name="l00944"></a>00944 <span class="preprocessor">#ifdef _TIM3</span>
    977. 

  977. <a name="l00945"></a>00945 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM3;
    978. 

  978. <a name="l00946"></a>00946 <span class="preprocessor">#endif </span><span class="comment">/*_TIM3 */</span>
    979. 

  979. <a name="l00947"></a>00947 
    980. 

  980. <a name="l00948"></a>00948 <span class="preprocessor">#ifdef _TIM4</span>
    981. 

  981. <a name="l00949"></a>00949 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM4;
    982. 

  982. <a name="l00950"></a>00950 <span class="preprocessor">#endif </span><span class="comment">/*_TIM4 */</span>
    983. 

  983. <a name="l00951"></a>00951 
    984. 

  984. <a name="l00952"></a>00952 <span class="preprocessor">#ifdef _TIM5</span>
    985. 

  985. <a name="l00953"></a>00953 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM5;
    986. 

  986. <a name="l00954"></a>00954 <span class="preprocessor">#endif </span><span class="comment">/*_TIM5 */</span>
    987. 

  987. <a name="l00955"></a>00955 
    988. 

  988. <a name="l00956"></a>00956 <span class="preprocessor">#ifdef _TIM6</span>
    989. 

  989. <a name="l00957"></a>00957 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM6;
    990. 

  990. <a name="l00958"></a>00958 <span class="preprocessor">#endif </span><span class="comment">/*_TIM6 */</span>
    991. 

  991. <a name="l00959"></a>00959 
    992. 

  992. <a name="l00960"></a>00960 <span class="preprocessor">#ifdef _TIM7</span>
    993. 

  993. <a name="l00961"></a>00961 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM7;
    994. 

  994. <a name="l00962"></a>00962 <span class="preprocessor">#endif </span><span class="comment">/*_TIM7 */</span>
    995. 

  995. <a name="l00963"></a>00963 
    996. 

  996. <a name="l00964"></a>00964 <span class="preprocessor">#ifdef _RTC</span>
    997. 

  997. <a name="l00965"></a>00965 <span class="preprocessor"></span>  EXT RTC_TypeDef             *RTC;
    998. 

  998. <a name="l00966"></a>00966 <span class="preprocessor">#endif </span><span class="comment">/*_RTC */</span>
    999. 

  999. <a name="l00967"></a>00967 
    1000. 

  1000. <a name="l00968"></a>00968 <span class="preprocessor">#ifdef _WWDG</span>
    1001. 

  1001. <a name="l00969"></a>00969 <span class="preprocessor"></span>  EXT WWDG_TypeDef            *WWDG;
    1002. 

  1002. <a name="l00970"></a>00970 <span class="preprocessor">#endif </span><span class="comment">/*_WWDG */</span>
    1003. 

  1003. <a name="l00971"></a>00971 
    1004. 

  1004. <a name="l00972"></a>00972 <span class="preprocessor">#ifdef _IWDG</span>
    1005. 

  1005. <a name="l00973"></a>00973 <span class="preprocessor"></span>  EXT IWDG_TypeDef            *IWDG;
    1006. 

  1006. <a name="l00974"></a>00974 <span class="preprocessor">#endif </span><span class="comment">/*_IWDG */</span>
    1007. 

  1007. <a name="l00975"></a>00975 
    1008. 

  1008. <a name="l00976"></a>00976 <span class="preprocessor">#ifdef _SPI2</span>
    1009. 

  1009. <a name="l00977"></a>00977 <span class="preprocessor"></span>  EXT SPI_TypeDef             *SPI2;
    1010. 

  1010. <a name="l00978"></a>00978 <span class="preprocessor">#endif </span><span class="comment">/*_SPI2 */</span>
    1011. 

  1011. <a name="l00979"></a>00979 
    1012. 

  1012. <a name="l00980"></a>00980 <span class="preprocessor">#ifdef _SPI3</span>
    1013. 

  1013. <a name="l00981"></a>00981 <span class="preprocessor"></span>  EXT SPI_TypeDef             *SPI3;
    1014. 

  1014. <a name="l00982"></a>00982 <span class="preprocessor">#endif </span><span class="comment">/*_SPI3 */</span>
    1015. 

  1015. <a name="l00983"></a>00983 
    1016. 

  1016. <a name="l00984"></a>00984 <span class="preprocessor">#ifdef _USART2</span>
    1017. 

  1017. <a name="l00985"></a>00985 <span class="preprocessor"></span>  EXT USART_TypeDef           *USART2;
    1018. 

  1018. <a name="l00986"></a>00986 <span class="preprocessor">#endif </span><span class="comment">/*_USART2 */</span>
    1019. 

  1019. <a name="l00987"></a>00987 
    1020. 

  1020. <a name="l00988"></a>00988 <span class="preprocessor">#ifdef _USART3</span>
    1021. 

  1021. <a name="l00989"></a>00989 <span class="preprocessor"></span>  EXT USART_TypeDef           *USART3;
    1022. 

  1022. <a name="l00990"></a>00990 <span class="preprocessor">#endif </span><span class="comment">/*_USART3 */</span>
    1023. 

  1023. <a name="l00991"></a>00991 
    1024. 

  1024. <a name="l00992"></a>00992 <span class="preprocessor">#ifdef _UART4</span>
    1025. 

  1025. <a name="l00993"></a>00993 <span class="preprocessor"></span>  EXT USART_TypeDef           *UART4;
    1026. 

  1026. <a name="l00994"></a>00994 <span class="preprocessor">#endif </span><span class="comment">/*_UART4 */</span>
    1027. 

  1027. <a name="l00995"></a>00995 
    1028. 

  1028. <a name="l00996"></a>00996 <span class="preprocessor">#ifdef _UART5</span>
    1029. 

  1029. <a name="l00997"></a>00997 <span class="preprocessor"></span>  EXT USART_TypeDef           *UART5;
    1030. 

  1030. <a name="l00998"></a>00998 <span class="preprocessor">#endif </span><span class="comment">/*_UART5 */</span>
    1031. 

  1031. <a name="l00999"></a>00999 
    1032. 

  1032. <a name="l01000"></a>01000 <span class="preprocessor">#ifdef _I2C1</span>
    1033. 

  1033. <a name="l01001"></a>01001 <span class="preprocessor"></span>  EXT I2C_TypeDef             *I2C1;
    1034. 

  1034. <a name="l01002"></a>01002 <span class="preprocessor">#endif </span><span class="comment">/*_I2C1 */</span>
    1035. 

  1035. <a name="l01003"></a>01003 
    1036. 

  1036. <a name="l01004"></a>01004 <span class="preprocessor">#ifdef _I2C2</span>
    1037. 

  1037. <a name="l01005"></a>01005 <span class="preprocessor"></span>  EXT I2C_TypeDef             *I2C2;
    1038. 

  1038. <a name="l01006"></a>01006 <span class="preprocessor">#endif </span><span class="comment">/*_I2C2 */</span>
    1039. 

  1039. <a name="l01007"></a>01007 
    1040. 

  1040. <a name="l01008"></a>01008 <span class="preprocessor">#ifdef _CAN</span>
    1041. 

  1041. <a name="l01009"></a>01009 <span class="preprocessor"></span>  EXT CAN_TypeDef             *CAN;
    1042. 

  1042. <a name="l01010"></a>01010 <span class="preprocessor">#endif </span><span class="comment">/*_CAN */</span>
    1043. 

  1043. <a name="l01011"></a>01011 
    1044. 

  1044. <a name="l01012"></a>01012 <span class="preprocessor">#ifdef _BKP</span>
    1045. 

  1045. <a name="l01013"></a>01013 <span class="preprocessor"></span>  EXT BKP_TypeDef             *BKP;
    1046. 

  1046. <a name="l01014"></a>01014 <span class="preprocessor">#endif </span><span class="comment">/*_BKP */</span>
    1047. 

  1047. <a name="l01015"></a>01015 
    1048. 

  1048. <a name="l01016"></a>01016 <span class="preprocessor">#ifdef _PWR</span>
    1049. 

  1049. <a name="l01017"></a>01017 <span class="preprocessor"></span>  EXT PWR_TypeDef             *PWR;
    1050. 

  1050. <a name="l01018"></a>01018 <span class="preprocessor">#endif </span><span class="comment">/*_PWR */</span>
    1051. 

  1051. <a name="l01019"></a>01019 
    1052. 

  1052. <a name="l01020"></a>01020 <span class="preprocessor">#ifdef _DAC</span>
    1053. 

  1053. <a name="l01021"></a>01021 <span class="preprocessor"></span>  EXT DAC_TypeDef             *DAC;
    1054. 

  1054. <a name="l01022"></a>01022 <span class="preprocessor">#endif </span><span class="comment">/*_DAC */</span>
    1055. 

  1055. <a name="l01023"></a>01023 
    1056. 

  1056. <a name="l01024"></a>01024 <span class="preprocessor">#ifdef _AFIO</span>
    1057. 

  1057. <a name="l01025"></a>01025 <span class="preprocessor"></span>  EXT AFIO_TypeDef            *AFIO;
    1058. 

  1058. <a name="l01026"></a>01026 <span class="preprocessor">#endif </span><span class="comment">/*_AFIO */</span>
    1059. 

  1059. <a name="l01027"></a>01027 
    1060. 

  1060. <a name="l01028"></a>01028 <span class="preprocessor">#ifdef _EXTI</span>
    1061. 

  1061. <a name="l01029"></a>01029 <span class="preprocessor"></span>  EXT EXTI_TypeDef            *EXTI;
    1062. 

  1062. <a name="l01030"></a>01030 <span class="preprocessor">#endif </span><span class="comment">/*_EXTI */</span>
    1063. 

  1063. <a name="l01031"></a>01031 
    1064. 

  1064. <a name="l01032"></a>01032 <span class="preprocessor">#ifdef _GPIOA</span>
    1065. 

  1065. <a name="l01033"></a>01033 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOA;
    1066. 

  1066. <a name="l01034"></a>01034 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOA */</span>
    1067. 

  1067. <a name="l01035"></a>01035 
    1068. 

  1068. <a name="l01036"></a>01036 <span class="preprocessor">#ifdef _GPIOB</span>
    1069. 

  1069. <a name="l01037"></a>01037 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOB;
    1070. 

  1070. <a name="l01038"></a>01038 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOB */</span>
    1071. 

  1071. <a name="l01039"></a>01039 
    1072. 

  1072. <a name="l01040"></a>01040 <span class="preprocessor">#ifdef _GPIOC</span>
    1073. 

  1073. <a name="l01041"></a>01041 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOC;
    1074. 

  1074. <a name="l01042"></a>01042 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOC */</span>
    1075. 

  1075. <a name="l01043"></a>01043 
    1076. 

  1076. <a name="l01044"></a>01044 <span class="preprocessor">#ifdef _GPIOD</span>
    1077. 

  1077. <a name="l01045"></a>01045 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOD;
    1078. 

  1078. <a name="l01046"></a>01046 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOD */</span>
    1079. 

  1079. <a name="l01047"></a>01047 
    1080. 

  1080. <a name="l01048"></a>01048 <span class="preprocessor">#ifdef _GPIOE</span>
    1081. 

  1081. <a name="l01049"></a>01049 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOE;
    1082. 

  1082. <a name="l01050"></a>01050 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOE */</span>
    1083. 

  1083. <a name="l01051"></a>01051 
    1084. 

  1084. <a name="l01052"></a>01052 <span class="preprocessor">#ifdef _GPIOF</span>
    1085. 

  1085. <a name="l01053"></a>01053 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOF;
    1086. 

  1086. <a name="l01054"></a>01054 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOF */</span>
    1087. 

  1087. <a name="l01055"></a>01055 
    1088. 

  1088. <a name="l01056"></a>01056 <span class="preprocessor">#ifdef _GPIOG</span>
    1089. 

  1089. <a name="l01057"></a>01057 <span class="preprocessor"></span>  EXT GPIO_TypeDef            *GPIOG;
    1090. 

  1090. <a name="l01058"></a>01058 <span class="preprocessor">#endif </span><span class="comment">/*_GPIOG */</span>
    1091. 

  1091. <a name="l01059"></a>01059 
    1092. 

  1092. <a name="l01060"></a>01060 <span class="preprocessor">#ifdef _ADC1</span>
    1093. 

  1093. <a name="l01061"></a>01061 <span class="preprocessor"></span>  EXT ADC_TypeDef             *ADC1;
    1094. 

  1094. <a name="l01062"></a>01062 <span class="preprocessor">#endif </span><span class="comment">/*_ADC1 */</span>
    1095. 

  1095. <a name="l01063"></a>01063 
    1096. 

  1096. <a name="l01064"></a>01064 <span class="preprocessor">#ifdef _ADC2</span>
    1097. 

  1097. <a name="l01065"></a>01065 <span class="preprocessor"></span>  EXT ADC_TypeDef             *ADC2;
    1098. 

  1098. <a name="l01066"></a>01066 <span class="preprocessor">#endif </span><span class="comment">/*_ADC2 */</span>
    1099. 

  1099. <a name="l01067"></a>01067 
    1100. 

  1100. <a name="l01068"></a>01068 <span class="preprocessor">#ifdef _TIM1</span>
    1101. 

  1101. <a name="l01069"></a>01069 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM1;
    1102. 

  1102. <a name="l01070"></a>01070 <span class="preprocessor">#endif </span><span class="comment">/*_TIM1 */</span>
    1103. 

  1103. <a name="l01071"></a>01071 
    1104. 

  1104. <a name="l01072"></a>01072 <span class="preprocessor">#ifdef _SPI1</span>
    1105. 

  1105. <a name="l01073"></a>01073 <span class="preprocessor"></span>  EXT SPI_TypeDef             *SPI1;
    1106. 

  1106. <a name="l01074"></a>01074 <span class="preprocessor">#endif </span><span class="comment">/*_SPI1 */</span>
    1107. 

  1107. <a name="l01075"></a>01075 
    1108. 

  1108. <a name="l01076"></a>01076 <span class="preprocessor">#ifdef _TIM8</span>
    1109. 

  1109. <a name="l01077"></a>01077 <span class="preprocessor"></span>  EXT TIM_TypeDef             *TIM8;
    1110. 

  1110. <a name="l01078"></a>01078 <span class="preprocessor">#endif </span><span class="comment">/*_TIM8 */</span>
    1111. 

  1111. <a name="l01079"></a>01079 
    1112. 

  1112. <a name="l01080"></a>01080 <span class="preprocessor">#ifdef _USART1</span>
    1113. 

  1113. <a name="l01081"></a>01081 <span class="preprocessor"></span>  EXT USART_TypeDef           *USART1;
    1114. 

  1114. <a name="l01082"></a>01082 <span class="preprocessor">#endif </span><span class="comment">/*_USART1 */</span>
    1115. 

  1115. <a name="l01083"></a>01083 
    1116. 

  1116. <a name="l01084"></a>01084 <span class="preprocessor">#ifdef _ADC3</span>
    1117. 

  1117. <a name="l01085"></a>01085 <span class="preprocessor"></span>  EXT ADC_TypeDef             *ADC3;
    1118. 

  1118. <a name="l01086"></a>01086 <span class="preprocessor">#endif </span><span class="comment">/*_ADC3 */</span>
    1119. 

  1119. <a name="l01087"></a>01087 
    1120. 

  1120. <a name="l01088"></a>01088 <span class="preprocessor">#ifdef _SDIO</span>
    1121. 

  1121. <a name="l01089"></a>01089 <span class="preprocessor"></span>  EXT SDIO_TypeDef            *SDIO;
    1122. 

  1122. <a name="l01090"></a>01090 <span class="preprocessor">#endif </span><span class="comment">/*_SDIO */</span>
    1123. 

  1123. <a name="l01091"></a>01091 
    1124. 

  1124. <a name="l01092"></a>01092 <span class="preprocessor">#ifdef _DMA</span>
    1125. 

  1125. <a name="l01093"></a>01093 <span class="preprocessor"></span>  EXT DMA_TypeDef             *DMA1;
    1126. 

  1126. <a name="l01094"></a>01094   EXT DMA_TypeDef             *DMA2;
    1127. 

  1127. <a name="l01095"></a>01095 <span class="preprocessor">#endif </span><span class="comment">/*_DMA */</span>
    1128. 

  1128. <a name="l01096"></a>01096 
    1129. 

  1129. <a name="l01097"></a>01097 <span class="preprocessor">#ifdef _DMA1_Channel1</span>
    1130. 

  1130. <a name="l01098"></a>01098 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel1;
    1131. 

  1131. <a name="l01099"></a>01099 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel1 */</span>
    1132. 

  1132. <a name="l01100"></a>01100 
    1133. 

  1133. <a name="l01101"></a>01101 <span class="preprocessor">#ifdef _DMA1_Channel2</span>
    1134. 

  1134. <a name="l01102"></a>01102 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel2;
    1135. 

  1135. <a name="l01103"></a>01103 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel2 */</span>
    1136. 

  1136. <a name="l01104"></a>01104 
    1137. 

  1137. <a name="l01105"></a>01105 <span class="preprocessor">#ifdef _DMA1_Channel3</span>
    1138. 

  1138. <a name="l01106"></a>01106 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel3;
    1139. 

  1139. <a name="l01107"></a>01107 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel3 */</span>
    1140. 

  1140. <a name="l01108"></a>01108 
    1141. 

  1141. <a name="l01109"></a>01109 <span class="preprocessor">#ifdef _DMA1_Channel4</span>
    1142. 

  1142. <a name="l01110"></a>01110 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel4;
    1143. 

  1143. <a name="l01111"></a>01111 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel4 */</span>
    1144. 

  1144. <a name="l01112"></a>01112 
    1145. 

  1145. <a name="l01113"></a>01113 <span class="preprocessor">#ifdef _DMA1_Channel5</span>
    1146. 

  1146. <a name="l01114"></a>01114 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel5;
    1147. 

  1147. <a name="l01115"></a>01115 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel5 */</span>
    1148. 

  1148. <a name="l01116"></a>01116 
    1149. 

  1149. <a name="l01117"></a>01117 <span class="preprocessor">#ifdef _DMA1_Channel6</span>
    1150. 

  1150. <a name="l01118"></a>01118 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel6;
    1151. 

  1151. <a name="l01119"></a>01119 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel6 */</span>
    1152. 

  1152. <a name="l01120"></a>01120 
    1153. 

  1153. <a name="l01121"></a>01121 <span class="preprocessor">#ifdef _DMA1_Channel7</span>
    1154. 

  1154. <a name="l01122"></a>01122 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA1_Channel7;
    1155. 

  1155. <a name="l01123"></a>01123 <span class="preprocessor">#endif </span><span class="comment">/*_DMA1_Channel7 */</span>
    1156. 

  1156. <a name="l01124"></a>01124 
    1157. 

  1157. <a name="l01125"></a>01125 <span class="preprocessor">#ifdef _DMA2_Channel1</span>
    1158. 

  1158. <a name="l01126"></a>01126 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA2_Channel1;
    1159. 

  1159. <a name="l01127"></a>01127 <span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel1 */</span>
    1160. 

  1160. <a name="l01128"></a>01128 
    1161. 

  1161. <a name="l01129"></a>01129 <span class="preprocessor">#ifdef _DMA2_Channel2</span>
    1162. 

  1162. <a name="l01130"></a>01130 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA2_Channel2;
    1163. 

  1163. <a name="l01131"></a>01131 <span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel2 */</span>
    1164. 

  1164. <a name="l01132"></a>01132 
    1165. 

  1165. <a name="l01133"></a>01133 <span class="preprocessor">#ifdef _DMA2_Channel3</span>
    1166. 

  1166. <a name="l01134"></a>01134 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA2_Channel3;
    1167. 

  1167. <a name="l01135"></a>01135 <span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel3 */</span>
    1168. 

  1168. <a name="l01136"></a>01136 
    1169. 

  1169. <a name="l01137"></a>01137 <span class="preprocessor">#ifdef _DMA2_Channel4</span>
    1170. 

  1170. <a name="l01138"></a>01138 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA2_Channel4;
    1171. 

  1171. <a name="l01139"></a>01139 <span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel4 */</span>
    1172. 

  1172. <a name="l01140"></a>01140 
    1173. 

  1173. <a name="l01141"></a>01141 <span class="preprocessor">#ifdef _DMA2_Channel5</span>
    1174. 

  1174. <a name="l01142"></a>01142 <span class="preprocessor"></span>  EXT DMA_Channel_TypeDef     *DMA2_Channel5;
    1175. 

  1175. <a name="l01143"></a>01143 <span class="preprocessor">#endif </span><span class="comment">/*_DMA2_Channel5 */</span>
    1176. 

  1176. <a name="l01144"></a>01144 
    1177. 

  1177. <a name="l01145"></a>01145 <span class="preprocessor">#ifdef _RCC</span>
    1178. 

  1178. <a name="l01146"></a>01146 <span class="preprocessor"></span>  EXT RCC_TypeDef             *RCC;
    1179. 

  1179. <a name="l01147"></a>01147 <span class="preprocessor">#endif </span><span class="comment">/*_RCC */</span>
    1180. 

  1180. <a name="l01148"></a>01148 
    1181. 

  1181. <a name="l01149"></a>01149 <span class="preprocessor">#ifdef _CRC</span>
    1182. 

  1182. <a name="l01150"></a>01150 <span class="preprocessor"></span>  EXT CRC_TypeDef             *CRC;
    1183. 

  1183. <a name="l01151"></a>01151 <span class="preprocessor">#endif </span><span class="comment">/*_CRC */</span>
    1184. 

  1184. <a name="l01152"></a>01152 
    1185. 

  1185. <a name="l01153"></a>01153 <span class="preprocessor">#ifdef _FLASH</span>
    1186. 

  1186. <a name="l01154"></a>01154 <span class="preprocessor"></span>  EXT FLASH_TypeDef            *FLASH;
    1187. 

  1187. <a name="l01155"></a>01155   EXT OB_TypeDef               *OB;  
    1188. 

  1188. <a name="l01156"></a>01156 <span class="preprocessor">#endif </span><span class="comment">/*_FLASH */</span>
    1189. 

  1189. <a name="l01157"></a>01157 
    1190. 

  1190. <a name="l01158"></a>01158 <span class="preprocessor">#ifdef _FSMC</span>
    1191. 

  1191. <a name="l01159"></a>01159 <span class="preprocessor"></span>  EXT FSMC_Bank1_TypeDef      *FSMC_Bank1;
    1192. 

  1192. <a name="l01160"></a>01160   EXT FSMC_Bank1E_TypeDef     *FSMC_Bank1E;
    1193. 

  1193. <a name="l01161"></a>01161   EXT FSMC_Bank2_TypeDef      *FSMC_Bank2;
    1194. 

  1194. <a name="l01162"></a>01162   EXT FSMC_Bank3_TypeDef      *FSMC_Bank3;
    1195. 

  1195. <a name="l01163"></a>01163   EXT FSMC_Bank4_TypeDef      *FSMC_Bank4;
    1196. 

  1196. <a name="l01164"></a>01164 <span class="preprocessor">#endif </span><span class="comment">/*_FSMC */</span>
    1197. 

  1197. <a name="l01165"></a>01165 
    1198. 

  1198. <a name="l01166"></a>01166 <span class="preprocessor">#ifdef _DBGMCU</span>
    1199. 

  1199. <a name="l01167"></a>01167 <span class="preprocessor"></span>  EXT DBGMCU_TypeDef          *DBGMCU;
    1200. 

  1200. <a name="l01168"></a>01168 <span class="preprocessor">#endif </span><span class="comment">/*_DBGMCU */</span>
    1201. 

  1201. <a name="l01169"></a>01169 
    1202. 

  1202. <a name="l01170"></a>01170 <span class="preprocessor">#ifdef _SysTick</span>
    1203. 

  1203. <a name="l01171"></a>01171 <span class="preprocessor"></span>  EXT SysTick_TypeDef         *SysTick;
    1204. 

  1204. <a name="l01172"></a>01172 <span class="preprocessor">#endif </span><span class="comment">/*_SysTick */</span>
    1205. 

  1205. <a name="l01173"></a>01173 
    1206. 

  1206. <a name="l01174"></a>01174 <span class="preprocessor">#ifdef _NVIC</span>
    1207. 

  1207. <a name="l01175"></a>01175 <span class="preprocessor"></span>  EXT NVIC_TypeDef            *NVIC;
    1208. 

  1208. <a name="l01176"></a>01176   EXT SCB_TypeDef             *SCB;
    1209. 

  1209. <a name="l01177"></a>01177 <span class="preprocessor">#endif </span><span class="comment">/*_NVIC */</span>
    1210. 

  1210. <a name="l01178"></a>01178 
    1211. 

  1211. <a name="l01179"></a>01179 <span class="preprocessor">#endif  </span><span class="comment">/* DEBUG */</span>
    1212. 

  1212. <a name="l01180"></a>01180 
    1213. 

  1213. <a name="l01181"></a>01181 <span class="comment">/* Exported constants --------------------------------------------------------*/</span>
    1214. 

  1214. <a name="l01182"></a>01182 <span class="comment">/******************************************************************************/</span>
    1215. 

  1215. <a name="l01183"></a>01183 <span class="comment">/*                                                                            */</span>
    1216. 

  1216. <a name="l01184"></a>01184 <span class="comment">/*                          CRC calculation unit                              */</span>
    1217. 

  1217. <a name="l01185"></a>01185 <span class="comment">/*                                                                            */</span>
    1218. 

  1218. <a name="l01186"></a>01186 <span class="comment">/******************************************************************************/</span>
    1219. 

  1219. <a name="l01187"></a>01187 
    1220. 

  1220. <a name="l01188"></a>01188 <span class="comment">/*******************  Bit definition for CRC_DR register  *********************/</span>
    1221. 

  1221. <a name="l01189"></a>01189 <span class="preprocessor">#define  CRC_DR_DR                           ((u32)0xFFFFFFFF) </span><span class="comment">/* Data register bits */</span>
    1222. 

  1222. <a name="l01190"></a>01190 
    1223. 

  1223. <a name="l01191"></a>01191 
    1224. 

  1224. <a name="l01192"></a>01192 <span class="comment">/*******************  Bit definition for CRC_IDR register  ********************/</span>
    1225. 

  1225. <a name="l01193"></a>01193 <span class="preprocessor">#define  CRC_IDR_IDR                         ((u8)0xFF)        </span><span class="comment">/* General-purpose 8-bit data register bits */</span>
    1226. 

  1226. <a name="l01194"></a>01194 
    1227. 

  1227. <a name="l01195"></a>01195 
    1228. 

  1228. <a name="l01196"></a>01196 <span class="comment">/********************  Bit definition for CRC_CR register  ********************/</span>
    1229. 

  1229. <a name="l01197"></a>01197 <span class="preprocessor">#define  CRC_CR_RESET                        ((u8)0x01)        </span><span class="comment">/* RESET bit */</span>
    1230. 

  1230. <a name="l01198"></a>01198 
    1231. 

  1231. <a name="l01199"></a>01199 
    1232. 

  1232. <a name="l01200"></a>01200 
    1233. 

  1233. <a name="l01201"></a>01201 <span class="comment">/******************************************************************************/</span>
    1234. 

  1234. <a name="l01202"></a>01202 <span class="comment">/*                                                                            */</span>
    1235. 

  1235. <a name="l01203"></a>01203 <span class="comment">/*                             Power Control                                  */</span>
    1236. 

  1236. <a name="l01204"></a>01204 <span class="comment">/*                                                                            */</span>
    1237. 

  1237. <a name="l01205"></a>01205 <span class="comment">/******************************************************************************/</span>
    1238. 

  1238. <a name="l01206"></a>01206 
    1239. 

  1239. <a name="l01207"></a>01207 <span class="comment">/********************  Bit definition for PWR_CR register  ********************/</span>
    1240. 

  1240. <a name="l01208"></a>01208 <span class="preprocessor">#define  PWR_CR_LPDS                         ((u16)0x0001)     </span><span class="comment">/* Low-Power Deepsleep */</span>
    1241. 

  1241. <a name="l01209"></a>01209 <span class="preprocessor">#define  PWR_CR_PDDS                         ((u16)0x0002)     </span><span class="comment">/* Power Down Deepsleep */</span>
    1242. 

  1242. <a name="l01210"></a>01210 <span class="preprocessor">#define  PWR_CR_CWUF                         ((u16)0x0004)     </span><span class="comment">/* Clear Wakeup Flag */</span>
    1243. 

  1243. <a name="l01211"></a>01211 <span class="preprocessor">#define  PWR_CR_CSBF                         ((u16)0x0008)     </span><span class="comment">/* Clear Standby Flag */</span>
    1244. 

  1244. <a name="l01212"></a>01212 <span class="preprocessor">#define  PWR_CR_PVDE                         ((u16)0x0010)     </span><span class="comment">/* Power Voltage Detector Enable */</span>
    1245. 

  1245. <a name="l01213"></a>01213 
    1246. 

  1246. <a name="l01214"></a>01214 <span class="preprocessor">#define  PWR_CR_PLS                          ((u16)0x00E0)     </span><span class="comment">/* PLS[2:0] bits (PVD Level Selection) */</span>
    1247. 

  1247. <a name="l01215"></a>01215 <span class="preprocessor">#define  PWR_CR_PLS_0                        ((u16)0x0020)     </span><span class="comment">/* Bit 0 */</span>
    1248. 

  1248. <a name="l01216"></a>01216 <span class="preprocessor">#define  PWR_CR_PLS_1                        ((u16)0x0040)     </span><span class="comment">/* Bit 1 */</span>
    1249. 

  1249. <a name="l01217"></a>01217 <span class="preprocessor">#define  PWR_CR_PLS_2                        ((u16)0x0080)     </span><span class="comment">/* Bit 2 */</span>
    1250. 

  1250. <a name="l01218"></a>01218 
    1251. 

  1251. <a name="l01219"></a>01219 <span class="comment">/* PVD level configuration */</span>
    1252. 

  1252. <a name="l01220"></a>01220 <span class="preprocessor">#define  PWR_CR_PLS_2V2                      ((u16)0x0000)     </span><span class="comment">/* PVD level 2.2V */</span>
    1253. 

  1253. <a name="l01221"></a>01221 <span class="preprocessor">#define  PWR_CR_PLS_2V3                      ((u16)0x0020)     </span><span class="comment">/* PVD level 2.3V */</span>
    1254. 

  1254. <a name="l01222"></a>01222 <span class="preprocessor">#define  PWR_CR_PLS_2V4                      ((u16)0x0040)     </span><span class="comment">/* PVD level 2.4V */</span>
    1255. 

  1255. <a name="l01223"></a>01223 <span class="preprocessor">#define  PWR_CR_PLS_2V5                      ((u16)0x0060)     </span><span class="comment">/* PVD level 2.5V */</span>
    1256. 

  1256. <a name="l01224"></a>01224 <span class="preprocessor">#define  PWR_CR_PLS_2V6                      ((u16)0x0080)     </span><span class="comment">/* PVD level 2.6V */</span>
    1257. 

  1257. <a name="l01225"></a>01225 <span class="preprocessor">#define  PWR_CR_PLS_2V7                      ((u16)0x00A0)     </span><span class="comment">/* PVD level 2.7V */</span>
    1258. 

  1258. <a name="l01226"></a>01226 <span class="preprocessor">#define  PWR_CR_PLS_2V8                      ((u16)0x00C0)     </span><span class="comment">/* PVD level 2.8V */</span>
    1259. 

  1259. <a name="l01227"></a>01227 <span class="preprocessor">#define  PWR_CR_PLS_2V9                      ((u16)0x00E0)     </span><span class="comment">/* PVD level 2.9V */</span>
    1260. 

  1260. <a name="l01228"></a>01228 
    1261. 

  1261. <a name="l01229"></a>01229 <span class="preprocessor">#define  PWR_CR_DBP                          ((u16)0x0100)     </span><span class="comment">/* Disable Backup Domain write protection */</span>
    1262. 

  1262. <a name="l01230"></a>01230 
    1263. 

  1263. <a name="l01231"></a>01231 
    1264. 

  1264. <a name="l01232"></a>01232 <span class="comment">/*******************  Bit definition for PWR_CSR register  ********************/</span>
    1265. 

  1265. <a name="l01233"></a>01233 <span class="preprocessor">#define  PWR_CSR_WUF                         ((u16)0x0001)     </span><span class="comment">/* Wakeup Flag */</span>
    1266. 

  1266. <a name="l01234"></a>01234 <span class="preprocessor">#define  PWR_CSR_SBF                         ((u16)0x0002)     </span><span class="comment">/* Standby Flag */</span>
    1267. 

  1267. <a name="l01235"></a>01235 <span class="preprocessor">#define  PWR_CSR_PVDO                        ((u16)0x0004)     </span><span class="comment">/* PVD Output */</span>
    1268. 

  1268. <a name="l01236"></a>01236 <span class="preprocessor">#define  PWR_CSR_EWUP                        ((u16)0x0100)     </span><span class="comment">/* Enable WKUP pin */</span>
    1269. 

  1269. <a name="l01237"></a>01237 
    1270. 

  1270. <a name="l01238"></a>01238 
    1271. 

  1271. <a name="l01239"></a>01239 
    1272. 

  1272. <a name="l01240"></a>01240 <span class="comment">/******************************************************************************/</span>
    1273. 

  1273. <a name="l01241"></a>01241 <span class="comment">/*                                                                            */</span>
    1274. 

  1274. <a name="l01242"></a>01242 <span class="comment">/*                            Backup registers                                */</span>
    1275. 

  1275. <a name="l01243"></a>01243 <span class="comment">/*                                                                            */</span>
    1276. 

  1276. <a name="l01244"></a>01244 <span class="comment">/******************************************************************************/</span>
    1277. 

  1277. <a name="l01245"></a>01245 
    1278. 

  1278. <a name="l01246"></a>01246 <span class="comment">/*******************  Bit definition for BKP_DR1 register  ********************/</span>
    1279. 

  1279. <a name="l01247"></a>01247 <span class="preprocessor">#define  BKP_DR1_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1280. 

  1280. <a name="l01248"></a>01248 
    1281. 

  1281. <a name="l01249"></a>01249 
    1282. 

  1282. <a name="l01250"></a>01250 <span class="comment">/*******************  Bit definition for BKP_DR2 register  ********************/</span>
    1283. 

  1283. <a name="l01251"></a>01251 <span class="preprocessor">#define  BKP_DR2_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1284. 

  1284. <a name="l01252"></a>01252 
    1285. 

  1285. <a name="l01253"></a>01253 
    1286. 

  1286. <a name="l01254"></a>01254 <span class="comment">/*******************  Bit definition for BKP_DR3 register  ********************/</span>
    1287. 

  1287. <a name="l01255"></a>01255 <span class="preprocessor">#define  BKP_DR3_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1288. 

  1288. <a name="l01256"></a>01256 
    1289. 

  1289. <a name="l01257"></a>01257 
    1290. 

  1290. <a name="l01258"></a>01258 <span class="comment">/*******************  Bit definition for BKP_DR4 register  ********************/</span>
    1291. 

  1291. <a name="l01259"></a>01259 <span class="preprocessor">#define  BKP_DR4_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1292. 

  1292. <a name="l01260"></a>01260 
    1293. 

  1293. <a name="l01261"></a>01261 
    1294. 

  1294. <a name="l01262"></a>01262 <span class="comment">/*******************  Bit definition for BKP_DR5 register  ********************/</span>
    1295. 

  1295. <a name="l01263"></a>01263 <span class="preprocessor">#define  BKP_DR5_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1296. 

  1296. <a name="l01264"></a>01264 
    1297. 

  1297. <a name="l01265"></a>01265 
    1298. 

  1298. <a name="l01266"></a>01266 <span class="comment">/*******************  Bit definition for BKP_DR6 register  ********************/</span>
    1299. 

  1299. <a name="l01267"></a>01267 <span class="preprocessor">#define  BKP_DR6_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1300. 

  1300. <a name="l01268"></a>01268 
    1301. 

  1301. <a name="l01269"></a>01269 
    1302. 

  1302. <a name="l01270"></a>01270 <span class="comment">/*******************  Bit definition for BKP_DR7 register  ********************/</span>
    1303. 

  1303. <a name="l01271"></a>01271 <span class="preprocessor">#define  BKP_DR7_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1304. 

  1304. <a name="l01272"></a>01272 
    1305. 

  1305. <a name="l01273"></a>01273 
    1306. 

  1306. <a name="l01274"></a>01274 <span class="comment">/*******************  Bit definition for BKP_DR8 register  ********************/</span>
    1307. 

  1307. <a name="l01275"></a>01275 <span class="preprocessor">#define  BKP_DR8_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1308. 

  1308. <a name="l01276"></a>01276 
    1309. 

  1309. <a name="l01277"></a>01277 
    1310. 

  1310. <a name="l01278"></a>01278 <span class="comment">/*******************  Bit definition for BKP_DR9 register  ********************/</span>
    1311. 

  1311. <a name="l01279"></a>01279 <span class="preprocessor">#define  BKP_DR9_D                           ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1312. 

  1312. <a name="l01280"></a>01280 
    1313. 

  1313. <a name="l01281"></a>01281 
    1314. 

  1314. <a name="l01282"></a>01282 <span class="comment">/*******************  Bit definition for BKP_DR10 register  *******************/</span>
    1315. 

  1315. <a name="l01283"></a>01283 <span class="preprocessor">#define  BKP_DR10_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1316. 

  1316. <a name="l01284"></a>01284 
    1317. 

  1317. <a name="l01285"></a>01285 
    1318. 

  1318. <a name="l01286"></a>01286 <span class="comment">/*******************  Bit definition for BKP_DR11 register  *******************/</span>
    1319. 

  1319. <a name="l01287"></a>01287 <span class="preprocessor">#define  BKP_DR11_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1320. 

  1320. <a name="l01288"></a>01288 
    1321. 

  1321. <a name="l01289"></a>01289 
    1322. 

  1322. <a name="l01290"></a>01290 <span class="comment">/*******************  Bit definition for BKP_DR12 register  *******************/</span>
    1323. 

  1323. <a name="l01291"></a>01291 <span class="preprocessor">#define  BKP_DR12_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1324. 

  1324. <a name="l01292"></a>01292 
    1325. 

  1325. <a name="l01293"></a>01293 
    1326. 

  1326. <a name="l01294"></a>01294 <span class="comment">/*******************  Bit definition for BKP_DR13 register  *******************/</span>
    1327. 

  1327. <a name="l01295"></a>01295 <span class="preprocessor">#define  BKP_DR13_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1328. 

  1328. <a name="l01296"></a>01296 
    1329. 

  1329. <a name="l01297"></a>01297 
    1330. 

  1330. <a name="l01298"></a>01298 <span class="comment">/*******************  Bit definition for BKP_DR14 register  *******************/</span>
    1331. 

  1331. <a name="l01299"></a>01299 <span class="preprocessor">#define  BKP_DR14_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1332. 

  1332. <a name="l01300"></a>01300 
    1333. 

  1333. <a name="l01301"></a>01301 
    1334. 

  1334. <a name="l01302"></a>01302 <span class="comment">/*******************  Bit definition for BKP_DR15 register  *******************/</span>
    1335. 

  1335. <a name="l01303"></a>01303 <span class="preprocessor">#define  BKP_DR15_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1336. 

  1336. <a name="l01304"></a>01304 
    1337. 

  1337. <a name="l01305"></a>01305 
    1338. 

  1338. <a name="l01306"></a>01306 <span class="comment">/*******************  Bit definition for BKP_DR16 register  *******************/</span>
    1339. 

  1339. <a name="l01307"></a>01307 <span class="preprocessor">#define  BKP_DR16_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1340. 

  1340. <a name="l01308"></a>01308 
    1341. 

  1341. <a name="l01309"></a>01309 
    1342. 

  1342. <a name="l01310"></a>01310 <span class="comment">/*******************  Bit definition for BKP_DR17 register  *******************/</span>
    1343. 

  1343. <a name="l01311"></a>01311 <span class="preprocessor">#define  BKP_DR17_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1344. 

  1344. <a name="l01312"></a>01312 
    1345. 

  1345. <a name="l01313"></a>01313 
    1346. 

  1346. <a name="l01314"></a>01314 <span class="comment">/******************  Bit definition for BKP_DR18 register  ********************/</span>
    1347. 

  1347. <a name="l01315"></a>01315 <span class="preprocessor">#define  BKP_DR18_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1348. 

  1348. <a name="l01316"></a>01316 
    1349. 

  1349. <a name="l01317"></a>01317 
    1350. 

  1350. <a name="l01318"></a>01318 <span class="comment">/*******************  Bit definition for BKP_DR19 register  *******************/</span>
    1351. 

  1351. <a name="l01319"></a>01319 <span class="preprocessor">#define  BKP_DR19_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1352. 

  1352. <a name="l01320"></a>01320 
    1353. 

  1353. <a name="l01321"></a>01321 
    1354. 

  1354. <a name="l01322"></a>01322 <span class="comment">/*******************  Bit definition for BKP_DR20 register  *******************/</span>
    1355. 

  1355. <a name="l01323"></a>01323 <span class="preprocessor">#define  BKP_DR20_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1356. 

  1356. <a name="l01324"></a>01324 
    1357. 

  1357. <a name="l01325"></a>01325 
    1358. 

  1358. <a name="l01326"></a>01326 <span class="comment">/*******************  Bit definition for BKP_DR21 register  *******************/</span>
    1359. 

  1359. <a name="l01327"></a>01327 <span class="preprocessor">#define  BKP_DR21_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1360. 

  1360. <a name="l01328"></a>01328 
    1361. 

  1361. <a name="l01329"></a>01329 
    1362. 

  1362. <a name="l01330"></a>01330 <span class="comment">/*******************  Bit definition for BKP_DR22 register  *******************/</span>
    1363. 

  1363. <a name="l01331"></a>01331 <span class="preprocessor">#define  BKP_DR22_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1364. 

  1364. <a name="l01332"></a>01332 
    1365. 

  1365. <a name="l01333"></a>01333 
    1366. 

  1366. <a name="l01334"></a>01334 <span class="comment">/*******************  Bit definition for BKP_DR23 register  *******************/</span>
    1367. 

  1367. <a name="l01335"></a>01335 <span class="preprocessor">#define  BKP_DR23_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1368. 

  1368. <a name="l01336"></a>01336 
    1369. 

  1369. <a name="l01337"></a>01337 
    1370. 

  1370. <a name="l01338"></a>01338 <span class="comment">/*******************  Bit definition for BKP_DR24 register  *******************/</span>
    1371. 

  1371. <a name="l01339"></a>01339 <span class="preprocessor">#define  BKP_DR24_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1372. 

  1372. <a name="l01340"></a>01340 
    1373. 

  1373. <a name="l01341"></a>01341 
    1374. 

  1374. <a name="l01342"></a>01342 <span class="comment">/*******************  Bit definition for BKP_DR25 register  *******************/</span>
    1375. 

  1375. <a name="l01343"></a>01343 <span class="preprocessor">#define  BKP_DR25_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1376. 

  1376. <a name="l01344"></a>01344 
    1377. 

  1377. <a name="l01345"></a>01345 
    1378. 

  1378. <a name="l01346"></a>01346 <span class="comment">/*******************  Bit definition for BKP_DR26 register  *******************/</span>
    1379. 

  1379. <a name="l01347"></a>01347 <span class="preprocessor">#define  BKP_DR26_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1380. 

  1380. <a name="l01348"></a>01348 
    1381. 

  1381. <a name="l01349"></a>01349 
    1382. 

  1382. <a name="l01350"></a>01350 <span class="comment">/*******************  Bit definition for BKP_DR27 register  *******************/</span>
    1383. 

  1383. <a name="l01351"></a>01351 <span class="preprocessor">#define  BKP_DR27_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1384. 

  1384. <a name="l01352"></a>01352 
    1385. 

  1385. <a name="l01353"></a>01353 
    1386. 

  1386. <a name="l01354"></a>01354 <span class="comment">/*******************  Bit definition for BKP_DR28 register  *******************/</span>
    1387. 

  1387. <a name="l01355"></a>01355 <span class="preprocessor">#define  BKP_DR28_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1388. 

  1388. <a name="l01356"></a>01356 
    1389. 

  1389. <a name="l01357"></a>01357 
    1390. 

  1390. <a name="l01358"></a>01358 <span class="comment">/*******************  Bit definition for BKP_DR29 register  *******************/</span>
    1391. 

  1391. <a name="l01359"></a>01359 <span class="preprocessor">#define  BKP_DR29_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1392. 

  1392. <a name="l01360"></a>01360 
    1393. 

  1393. <a name="l01361"></a>01361 
    1394. 

  1394. <a name="l01362"></a>01362 <span class="comment">/*******************  Bit definition for BKP_DR30 register  *******************/</span>
    1395. 

  1395. <a name="l01363"></a>01363 <span class="preprocessor">#define  BKP_DR30_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1396. 

  1396. <a name="l01364"></a>01364 
    1397. 

  1397. <a name="l01365"></a>01365 
    1398. 

  1398. <a name="l01366"></a>01366 <span class="comment">/*******************  Bit definition for BKP_DR31 register  *******************/</span>
    1399. 

  1399. <a name="l01367"></a>01367 <span class="preprocessor">#define  BKP_DR31_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1400. 

  1400. <a name="l01368"></a>01368 
    1401. 

  1401. <a name="l01369"></a>01369 
    1402. 

  1402. <a name="l01370"></a>01370 <span class="comment">/*******************  Bit definition for BKP_DR32 register  *******************/</span>
    1403. 

  1403. <a name="l01371"></a>01371 <span class="preprocessor">#define  BKP_DR32_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1404. 

  1404. <a name="l01372"></a>01372 
    1405. 

  1405. <a name="l01373"></a>01373 
    1406. 

  1406. <a name="l01374"></a>01374 <span class="comment">/*******************  Bit definition for BKP_DR33 register  *******************/</span>
    1407. 

  1407. <a name="l01375"></a>01375 <span class="preprocessor">#define  BKP_DR33_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1408. 

  1408. <a name="l01376"></a>01376 
    1409. 

  1409. <a name="l01377"></a>01377 
    1410. 

  1410. <a name="l01378"></a>01378 <span class="comment">/*******************  Bit definition for BKP_DR34 register  *******************/</span>
    1411. 

  1411. <a name="l01379"></a>01379 <span class="preprocessor">#define  BKP_DR34_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1412. 

  1412. <a name="l01380"></a>01380 
    1413. 

  1413. <a name="l01381"></a>01381 
    1414. 

  1414. <a name="l01382"></a>01382 <span class="comment">/*******************  Bit definition for BKP_DR35 register  *******************/</span>
    1415. 

  1415. <a name="l01383"></a>01383 <span class="preprocessor">#define  BKP_DR35_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1416. 

  1416. <a name="l01384"></a>01384 
    1417. 

  1417. <a name="l01385"></a>01385 
    1418. 

  1418. <a name="l01386"></a>01386 <span class="comment">/*******************  Bit definition for BKP_DR36 register  *******************/</span>
    1419. 

  1419. <a name="l01387"></a>01387 <span class="preprocessor">#define  BKP_DR36_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1420. 

  1420. <a name="l01388"></a>01388 
    1421. 

  1421. <a name="l01389"></a>01389 
    1422. 

  1422. <a name="l01390"></a>01390 <span class="comment">/*******************  Bit definition for BKP_DR37 register  *******************/</span>
    1423. 

  1423. <a name="l01391"></a>01391 <span class="preprocessor">#define  BKP_DR37_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1424. 

  1424. <a name="l01392"></a>01392 
    1425. 

  1425. <a name="l01393"></a>01393 
    1426. 

  1426. <a name="l01394"></a>01394 <span class="comment">/*******************  Bit definition for BKP_DR38 register  *******************/</span>
    1427. 

  1427. <a name="l01395"></a>01395 <span class="preprocessor">#define  BKP_DR38_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1428. 

  1428. <a name="l01396"></a>01396 
    1429. 

  1429. <a name="l01397"></a>01397 
    1430. 

  1430. <a name="l01398"></a>01398 <span class="comment">/*******************  Bit definition for BKP_DR39 register  *******************/</span>
    1431. 

  1431. <a name="l01399"></a>01399 <span class="preprocessor">#define  BKP_DR39_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1432. 

  1432. <a name="l01400"></a>01400 
    1433. 

  1433. <a name="l01401"></a>01401 
    1434. 

  1434. <a name="l01402"></a>01402 <span class="comment">/*******************  Bit definition for BKP_DR40 register  *******************/</span>
    1435. 

  1435. <a name="l01403"></a>01403 <span class="preprocessor">#define  BKP_DR40_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1436. 

  1436. <a name="l01404"></a>01404 
    1437. 

  1437. <a name="l01405"></a>01405 
    1438. 

  1438. <a name="l01406"></a>01406 <span class="comment">/*******************  Bit definition for BKP_DR41 register  *******************/</span>
    1439. 

  1439. <a name="l01407"></a>01407 <span class="preprocessor">#define  BKP_DR41_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1440. 

  1440. <a name="l01408"></a>01408 
    1441. 

  1441. <a name="l01409"></a>01409 
    1442. 

  1442. <a name="l01410"></a>01410 <span class="comment">/*******************  Bit definition for BKP_DR42 register  *******************/</span>
    1443. 

  1443. <a name="l01411"></a>01411 <span class="preprocessor">#define  BKP_DR42_D                          ((u16)0xFFFF)     </span><span class="comment">/* Backup data */</span>
    1444. 

  1444. <a name="l01412"></a>01412 
    1445. 

  1445. <a name="l01413"></a>01413 
    1446. 

  1446. <a name="l01414"></a>01414 <span class="comment">/******************  Bit definition for BKP_RTCCR register  *******************/</span>
    1447. 

  1447. <a name="l01415"></a>01415 <span class="preprocessor">#define  BKP_RTCCR_CAL                       ((u16)0x007F)     </span><span class="comment">/* Calibration value */</span>
    1448. 

  1448. <a name="l01416"></a>01416 <span class="preprocessor">#define  BKP_RTCCR_CCO                       ((u16)0x0080)     </span><span class="comment">/* Calibration Clock Output */</span>
    1449. 

  1449. <a name="l01417"></a>01417 <span class="preprocessor">#define  BKP_RTCCR_ASOE                      ((u16)0x0100)     </span><span class="comment">/* Alarm or Second Output Enable */</span>
    1450. 

  1450. <a name="l01418"></a>01418 <span class="preprocessor">#define  BKP_RTCCR_ASOS                      ((u16)0x0200)     </span><span class="comment">/* Alarm or Second Output Selection */</span>
    1451. 

  1451. <a name="l01419"></a>01419 
    1452. 

  1452. <a name="l01420"></a>01420 
    1453. 

  1453. <a name="l01421"></a>01421 <span class="comment">/********************  Bit definition for BKP_CR register  ********************/</span>
    1454. 

  1454. <a name="l01422"></a>01422 <span class="preprocessor">#define  BKP_CR_TPE                          ((u8)0x01)        </span><span class="comment">/* TAMPER pin enable */</span>
    1455. 

  1455. <a name="l01423"></a>01423 <span class="preprocessor">#define  BKP_CR_TPAL                         ((u8)0x02)        </span><span class="comment">/* TAMPER pin active level */</span>
    1456. 

  1456. <a name="l01424"></a>01424 
    1457. 

  1457. <a name="l01425"></a>01425 
    1458. 

  1458. <a name="l01426"></a>01426 <span class="comment">/*******************  Bit definition for BKP_CSR register  ********************/</span>
    1459. 

  1459. <a name="l01427"></a>01427 <span class="preprocessor">#define  BKP_CSR_CTE                         ((u16)0x0001)     </span><span class="comment">/* Clear Tamper event */</span>
    1460. 

  1460. <a name="l01428"></a>01428 <span class="preprocessor">#define  BKP_CSR_CTI                         ((u16)0x0002)     </span><span class="comment">/* Clear Tamper Interrupt */</span>
    1461. 

  1461. <a name="l01429"></a>01429 <span class="preprocessor">#define  BKP_CSR_TPIE                        ((u16)0x0004)     </span><span class="comment">/* TAMPER Pin interrupt enable */</span>
    1462. 

  1462. <a name="l01430"></a>01430 <span class="preprocessor">#define  BKP_CSR_TEF                         ((u16)0x0100)     </span><span class="comment">/* Tamper Event Flag */</span>
    1463. 

  1463. <a name="l01431"></a>01431 <span class="preprocessor">#define  BKP_CSR_TIF                         ((u16)0x0200)     </span><span class="comment">/* Tamper Interrupt Flag */</span>
    1464. 

  1464. <a name="l01432"></a>01432 
    1465. 

  1465. <a name="l01433"></a>01433 
    1466. 

  1466. <a name="l01434"></a>01434 
    1467. 

  1467. <a name="l01435"></a>01435 <span class="comment">/******************************************************************************/</span>
    1468. 

  1468. <a name="l01436"></a>01436 <span class="comment">/*                                                                            */</span>
    1469. 

  1469. <a name="l01437"></a>01437 <span class="comment">/*                         Reset and Clock Control                            */</span>
    1470. 

  1470. <a name="l01438"></a>01438 <span class="comment">/*                                                                            */</span>
    1471. 

  1471. <a name="l01439"></a>01439 <span class="comment">/******************************************************************************/</span>
    1472. 

  1472. <a name="l01440"></a>01440 
    1473. 

  1473. <a name="l01441"></a>01441 
    1474. 

  1474. <a name="l01442"></a>01442 <span class="comment">/********************  Bit definition for RCC_CR register  ********************/</span>
    1475. 

  1475. <a name="l01443"></a>01443 <span class="preprocessor">#define  RCC_CR_HSION                        ((u32)0x00000001)        </span><span class="comment">/* Internal High Speed clock enable */</span>
    1476. 

  1476. <a name="l01444"></a>01444 <span class="preprocessor">#define  RCC_CR_HSIRDY                       ((u32)0x00000002)        </span><span class="comment">/* Internal High Speed clock ready flag */</span>
    1477. 

  1477. <a name="l01445"></a>01445 <span class="preprocessor">#define  RCC_CR_HSITRIM                      ((u32)0x000000F8)        </span><span class="comment">/* Internal High Speed clock trimming */</span>
    1478. 

  1478. <a name="l01446"></a>01446 <span class="preprocessor">#define  RCC_CR_HSICAL                       ((u32)0x0000FF00)        </span><span class="comment">/* Internal High Speed clock Calibration */</span>
    1479. 

  1479. <a name="l01447"></a>01447 <span class="preprocessor">#define  RCC_CR_HSEON                        ((u32)0x00010000)        </span><span class="comment">/* External High Speed clock enable */</span>
    1480. 

  1480. <a name="l01448"></a>01448 <span class="preprocessor">#define  RCC_CR_HSERDY                       ((u32)0x00020000)        </span><span class="comment">/* External High Speed clock ready flag */</span>
    1481. 

  1481. <a name="l01449"></a>01449 <span class="preprocessor">#define  RCC_CR_HSEBYP                       ((u32)0x00040000)        </span><span class="comment">/* External High Speed clock Bypass */</span>
    1482. 

  1482. <a name="l01450"></a>01450 <span class="preprocessor">#define  RCC_CR_CSSON                        ((u32)0x00080000)        </span><span class="comment">/* Clock Security System enable */</span>
    1483. 

  1483. <a name="l01451"></a>01451 <span class="preprocessor">#define  RCC_CR_PLLON                        ((u32)0x01000000)        </span><span class="comment">/* PLL enable */</span>
    1484. 

  1484. <a name="l01452"></a>01452 <span class="preprocessor">#define  RCC_CR_PLLRDY                       ((u32)0x02000000)        </span><span class="comment">/* PLL clock ready flag */</span>
    1485. 

  1485. <a name="l01453"></a>01453 
    1486. 

  1486. <a name="l01454"></a>01454 
    1487. 

  1487. <a name="l01455"></a>01455 <span class="comment">/*******************  Bit definition for RCC_CFGR register  *******************/</span>
    1488. 

  1488. <a name="l01456"></a>01456 <span class="preprocessor">#define  RCC_CFGR_SW                         ((u32)0x00000003)        </span><span class="comment">/* SW[1:0] bits (System clock Switch) */</span>
    1489. 

  1489. <a name="l01457"></a>01457 <span class="preprocessor">#define  RCC_CFGR_SW_0                       ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    1490. 

  1490. <a name="l01458"></a>01458 <span class="preprocessor">#define  RCC_CFGR_SW_1                       ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    1491. 

  1491. <a name="l01459"></a>01459 
    1492. 

  1492. <a name="l01460"></a>01460 <span class="comment">/* SW configuration */</span>
    1493. 

  1493. <a name="l01461"></a>01461 <span class="preprocessor">#define  RCC_CFGR_SW_HSI                     ((u32)0x00000000)        </span><span class="comment">/* HSI selected as system clock */</span>
    1494. 

  1494. <a name="l01462"></a>01462 <span class="preprocessor">#define  RCC_CFGR_SW_HSE                     ((u32)0x00000001)        </span><span class="comment">/* HSE selected as system clock */</span>
    1495. 

  1495. <a name="l01463"></a>01463 <span class="preprocessor">#define  RCC_CFGR_SW_PLL                     ((u32)0x00000002)        </span><span class="comment">/* PLL selected as system clock */</span>
    1496. 

  1496. <a name="l01464"></a>01464 
    1497. 

  1497. <a name="l01465"></a>01465 <span class="preprocessor">#define  RCC_CFGR_SWS                        ((u32)0x0000000C)        </span><span class="comment">/* SWS[1:0] bits (System Clock Switch Status) */</span>
    1498. 

  1498. <a name="l01466"></a>01466 <span class="preprocessor">#define  RCC_CFGR_SWS_0                      ((u32)0x00000004)        </span><span class="comment">/* Bit 0 */</span>
    1499. 

  1499. <a name="l01467"></a>01467 <span class="preprocessor">#define  RCC_CFGR_SWS_1                      ((u32)0x00000008)        </span><span class="comment">/* Bit 1 */</span>
    1500. 

  1500. <a name="l01468"></a>01468 
    1501. 

  1501. <a name="l01469"></a>01469 <span class="comment">/* SWS configuration */</span>
    1502. 

  1502. <a name="l01470"></a>01470 <span class="preprocessor">#define  RCC_CFGR_SWS_HSI                    ((u32)0x00000000)        </span><span class="comment">/* HSI oscillator used as system clock */</span>
    1503. 

  1503. <a name="l01471"></a>01471 <span class="preprocessor">#define  RCC_CFGR_SWS_HSE                    ((u32)0x00000004)        </span><span class="comment">/* HSE oscillator used as system clock */</span>
    1504. 

  1504. <a name="l01472"></a>01472 <span class="preprocessor">#define  RCC_CFGR_SWS_PLL                    ((u32)0x00000008)        </span><span class="comment">/* PLL used as system clock */</span>
    1505. 

  1505. <a name="l01473"></a>01473 
    1506. 

  1506. <a name="l01474"></a>01474 <span class="preprocessor">#define  RCC_CFGR_HPRE                       ((u32)0x000000F0)        </span><span class="comment">/* HPRE[3:0] bits (AHB prescaler) */</span>
    1507. 

  1507. <a name="l01475"></a>01475 <span class="preprocessor">#define  RCC_CFGR_HPRE_0                     ((u32)0x00000010)        </span><span class="comment">/* Bit 0 */</span>
    1508. 

  1508. <a name="l01476"></a>01476 <span class="preprocessor">#define  RCC_CFGR_HPRE_1                     ((u32)0x00000020)        </span><span class="comment">/* Bit 1 */</span>
    1509. 

  1509. <a name="l01477"></a>01477 <span class="preprocessor">#define  RCC_CFGR_HPRE_2                     ((u32)0x00000040)        </span><span class="comment">/* Bit 2 */</span>
    1510. 

  1510. <a name="l01478"></a>01478 <span class="preprocessor">#define  RCC_CFGR_HPRE_3                     ((u32)0x00000080)        </span><span class="comment">/* Bit 3 */</span>
    1511. 

  1511. <a name="l01479"></a>01479 
    1512. 

  1512. <a name="l01480"></a>01480 <span class="comment">/* HPRE configuration */</span>
    1513. 

  1513. <a name="l01481"></a>01481 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV1                  ((u32)0x00000000)        </span><span class="comment">/* SYSCLK not divided */</span>
    1514. 

  1514. <a name="l01482"></a>01482 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV2                  ((u32)0x00000080)        </span><span class="comment">/* SYSCLK divided by 2 */</span>
    1515. 

  1515. <a name="l01483"></a>01483 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV4                  ((u32)0x00000090)        </span><span class="comment">/* SYSCLK divided by 4 */</span>
    1516. 

  1516. <a name="l01484"></a>01484 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV8                  ((u32)0x000000A0)        </span><span class="comment">/* SYSCLK divided by 8 */</span>
    1517. 

  1517. <a name="l01485"></a>01485 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV16                 ((u32)0x000000B0)        </span><span class="comment">/* SYSCLK divided by 16 */</span>
    1518. 

  1518. <a name="l01486"></a>01486 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV64                 ((u32)0x000000C0)        </span><span class="comment">/* SYSCLK divided by 64 */</span>
    1519. 

  1519. <a name="l01487"></a>01487 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV128                ((u32)0x000000D0)        </span><span class="comment">/* SYSCLK divided by 128 */</span>
    1520. 

  1520. <a name="l01488"></a>01488 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV256                ((u32)0x000000E0)        </span><span class="comment">/* SYSCLK divided by 256 */</span>
    1521. 

  1521. <a name="l01489"></a>01489 <span class="preprocessor">#define  RCC_CFGR_HPRE_DIV512                ((u32)0x000000F0)        </span><span class="comment">/* SYSCLK divided by 512 */</span>
    1522. 

  1522. <a name="l01490"></a>01490 
    1523. 

  1523. <a name="l01491"></a>01491 <span class="preprocessor">#define  RCC_CFGR_PPRE1                      ((u32)0x00000700)        </span><span class="comment">/* PRE1[2:0] bits (APB1 prescaler) */</span>
    1524. 

  1524. <a name="l01492"></a>01492 <span class="preprocessor">#define  RCC_CFGR_PPRE1_0                    ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    1525. 

  1525. <a name="l01493"></a>01493 <span class="preprocessor">#define  RCC_CFGR_PPRE1_1                    ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    1526. 

  1526. <a name="l01494"></a>01494 <span class="preprocessor">#define  RCC_CFGR_PPRE1_2                    ((u32)0x00000400)        </span><span class="comment">/* Bit 2 */</span>
    1527. 

  1527. <a name="l01495"></a>01495 
    1528. 

  1528. <a name="l01496"></a>01496 <span class="comment">/* PPRE1 configuration */</span>
    1529. 

  1529. <a name="l01497"></a>01497 <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV1                 ((u32)0x00000000)        </span><span class="comment">/* HCLK not divided */</span>
    1530. 

  1530. <a name="l01498"></a>01498 <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV2                 ((u32)0x00000400)        </span><span class="comment">/* HCLK divided by 2 */</span>
    1531. 

  1531. <a name="l01499"></a>01499 <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV4                 ((u32)0x00000500)        </span><span class="comment">/* HCLK divided by 4 */</span>
    1532. 

  1532. <a name="l01500"></a>01500 <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV8                 ((u32)0x00000600)        </span><span class="comment">/* HCLK divided by 8 */</span>
    1533. 

  1533. <a name="l01501"></a>01501 <span class="preprocessor">#define  RCC_CFGR_PPRE1_DIV16                ((u32)0x00000700)        </span><span class="comment">/* HCLK divided by 16 */</span>
    1534. 

  1534. <a name="l01502"></a>01502 
    1535. 

  1535. <a name="l01503"></a>01503 <span class="preprocessor">#define  RCC_CFGR_PPRE2                      ((u32)0x00003800)        </span><span class="comment">/* PRE2[2:0] bits (APB2 prescaler) */</span>
    1536. 

  1536. <a name="l01504"></a>01504 <span class="preprocessor">#define  RCC_CFGR_PPRE2_0                    ((u32)0x00000800)        </span><span class="comment">/* Bit 0 */</span>
    1537. 

  1537. <a name="l01505"></a>01505 <span class="preprocessor">#define  RCC_CFGR_PPRE2_1                    ((u32)0x00001000)        </span><span class="comment">/* Bit 1 */</span>
    1538. 

  1538. <a name="l01506"></a>01506 <span class="preprocessor">#define  RCC_CFGR_PPRE2_2                    ((u32)0x00002000)        </span><span class="comment">/* Bit 2 */</span>
    1539. 

  1539. <a name="l01507"></a>01507 
    1540. 

  1540. <a name="l01508"></a>01508 <span class="comment">/* PPRE2 configuration */</span>
    1541. 

  1541. <a name="l01509"></a>01509 <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV1                 ((u32)0x00000000)        </span><span class="comment">/* HCLK not divided */</span>
    1542. 

  1542. <a name="l01510"></a>01510 <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV2                 ((u32)0x00002000)        </span><span class="comment">/* HCLK divided by 2 */</span>
    1543. 

  1543. <a name="l01511"></a>01511 <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV4                 ((u32)0x00002800)        </span><span class="comment">/* HCLK divided by 4 */</span>
    1544. 

  1544. <a name="l01512"></a>01512 <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV8                 ((u32)0x00003000)        </span><span class="comment">/* HCLK divided by 8 */</span>
    1545. 

  1545. <a name="l01513"></a>01513 <span class="preprocessor">#define  RCC_CFGR_PPRE2_DIV16                ((u32)0x00003800)        </span><span class="comment">/* HCLK divided by 16 */</span>
    1546. 

  1546. <a name="l01514"></a>01514 
    1547. 

  1547. <a name="l01515"></a>01515 <span class="preprocessor">#define  RCC_CFGR_ADCPRE                     ((u32)0x0000C000)        </span><span class="comment">/* ADCPRE[1:0] bits (ADC prescaler) */</span>
    1548. 

  1548. <a name="l01516"></a>01516 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_0                   ((u32)0x00004000)        </span><span class="comment">/* Bit 0 */</span>
    1549. 

  1549. <a name="l01517"></a>01517 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_1                   ((u32)0x00008000)        </span><span class="comment">/* Bit 1 */</span>
    1550. 

  1550. <a name="l01518"></a>01518 
    1551. 

  1551. <a name="l01519"></a>01519 <span class="comment">/* ADCPPRE configuration */</span>
    1552. 

  1552. <a name="l01520"></a>01520 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_DIV2                ((u32)0x00000000)        </span><span class="comment">/* PCLK2 divided by 2 */</span>
    1553. 

  1553. <a name="l01521"></a>01521 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_DIV4                ((u32)0x00004000)        </span><span class="comment">/* PCLK2 divided by 4 */</span>
    1554. 

  1554. <a name="l01522"></a>01522 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_DIV6                ((u32)0x00008000)        </span><span class="comment">/* PCLK2 divided by 6 */</span>
    1555. 

  1555. <a name="l01523"></a>01523 <span class="preprocessor">#define  RCC_CFGR_ADCPRE_DIV8                ((u32)0x0000C000)        </span><span class="comment">/* PCLK2 divided by 8 */</span>
    1556. 

  1556. <a name="l01524"></a>01524 
    1557. 

  1557. <a name="l01525"></a>01525 <span class="preprocessor">#define  RCC_CFGR_PLLSRC                     ((u32)0x00010000)        </span><span class="comment">/* PLL entry clock source */</span>
    1558. 

  1558. <a name="l01526"></a>01526 <span class="preprocessor">#define  RCC_CFGR_PLLXTPRE                   ((u32)0x00020000)        </span><span class="comment">/* HSE divider for PLL entry */</span>
    1559. 

  1559. <a name="l01527"></a>01527 
    1560. 

  1560. <a name="l01528"></a>01528 <span class="preprocessor">#define  RCC_CFGR_PLLMULL                    ((u32)0x003C0000)        </span><span class="comment">/* PLLMUL[3:0] bits (PLL multiplication factor) */</span>
    1561. 

  1561. <a name="l01529"></a>01529 <span class="preprocessor">#define  RCC_CFGR_PLLMULL_0                  ((u32)0x00040000)        </span><span class="comment">/* Bit 0 */</span>
    1562. 

  1562. <a name="l01530"></a>01530 <span class="preprocessor">#define  RCC_CFGR_PLLMULL_1                  ((u32)0x00080000)        </span><span class="comment">/* Bit 1 */</span>
    1563. 

  1563. <a name="l01531"></a>01531 <span class="preprocessor">#define  RCC_CFGR_PLLMULL_2                  ((u32)0x00100000)        </span><span class="comment">/* Bit 2 */</span>
    1564. 

  1564. <a name="l01532"></a>01532 <span class="preprocessor">#define  RCC_CFGR_PLLMULL_3                  ((u32)0x00200000)        </span><span class="comment">/* Bit 3 */</span>
    1565. 

  1565. <a name="l01533"></a>01533 
    1566. 

  1566. <a name="l01534"></a>01534 <span class="comment">/* PLLMUL configuration */</span>
    1567. 

  1567. <a name="l01535"></a>01535 <span class="preprocessor">#define  RCC_CFGR_PLLMULL2                   ((u32)0x00000000)        </span><span class="comment">/* PLL input clock*2 */</span>
    1568. 

  1568. <a name="l01536"></a>01536 <span class="preprocessor">#define  RCC_CFGR_PLLMULL3                   ((u32)0x00040000)        </span><span class="comment">/* PLL input clock*3 */</span>
    1569. 

  1569. <a name="l01537"></a>01537 <span class="preprocessor">#define  RCC_CFGR_PLLMULL4                   ((u32)0x00080000)        </span><span class="comment">/* PLL input clock*4 */</span>
    1570. 

  1570. <a name="l01538"></a>01538 <span class="preprocessor">#define  RCC_CFGR_PLLMULL5                   ((u32)0x000C0000)        </span><span class="comment">/* PLL input clock*5 */</span>
    1571. 

  1571. <a name="l01539"></a>01539 <span class="preprocessor">#define  RCC_CFGR_PLLMULL6                   ((u32)0x00100000)        </span><span class="comment">/* PLL input clock*6 */</span>
    1572. 

  1572. <a name="l01540"></a>01540 <span class="preprocessor">#define  RCC_CFGR_PLLMULL7                   ((u32)0x00140000)        </span><span class="comment">/* PLL input clock*7 */</span>
    1573. 

  1573. <a name="l01541"></a>01541 <span class="preprocessor">#define  RCC_CFGR_PLLMULL8                   ((u32)0x00180000)        </span><span class="comment">/* PLL input clock*8 */</span>
    1574. 

  1574. <a name="l01542"></a>01542 <span class="preprocessor">#define  RCC_CFGR_PLLMULL9                   ((u32)0x001C0000)        </span><span class="comment">/* PLL input clock*9 */</span>
    1575. 

  1575. <a name="l01543"></a>01543 <span class="preprocessor">#define  RCC_CFGR_PLLMULL10                  ((u32)0x00200000)        </span><span class="comment">/* PLL input clock10 */</span>
    1576. 

  1576. <a name="l01544"></a>01544 <span class="preprocessor">#define  RCC_CFGR_PLLMULL11                  ((u32)0x00240000)        </span><span class="comment">/* PLL input clock*11 */</span>
    1577. 

  1577. <a name="l01545"></a>01545 <span class="preprocessor">#define  RCC_CFGR_PLLMULL12                  ((u32)0x00280000)        </span><span class="comment">/* PLL input clock*12 */</span>
    1578. 

  1578. <a name="l01546"></a>01546 <span class="preprocessor">#define  RCC_CFGR_PLLMULL13                  ((u32)0x002C0000)        </span><span class="comment">/* PLL input clock*13 */</span>
    1579. 

  1579. <a name="l01547"></a>01547 <span class="preprocessor">#define  RCC_CFGR_PLLMULL14                  ((u32)0x00300000)        </span><span class="comment">/* PLL input clock*14 */</span>
    1580. 

  1580. <a name="l01548"></a>01548 <span class="preprocessor">#define  RCC_CFGR_PLLMULL15                  ((u32)0x00340000)        </span><span class="comment">/* PLL input clock*15 */</span>
    1581. 

  1581. <a name="l01549"></a>01549 <span class="preprocessor">#define  RCC_CFGR_PLLMULL16                  ((u32)0x00380000)        </span><span class="comment">/* PLL input clock*16 */</span>
    1582. 

  1582. <a name="l01550"></a>01550 
    1583. 

  1583. <a name="l01551"></a>01551 <span class="preprocessor">#define  RCC_CFGR_USBPRE                     ((u32)0x00400000)        </span><span class="comment">/* USB prescaler */</span>
    1584. 

  1584. <a name="l01552"></a>01552 
    1585. 

  1585. <a name="l01553"></a>01553 <span class="preprocessor">#define  RCC_CFGR_MCO                        ((u32)0x07000000)        </span><span class="comment">/* MCO[2:0] bits (Microcontroller Clock Output) */</span>
    1586. 

  1586. <a name="l01554"></a>01554 <span class="preprocessor">#define  RCC_CFGR_MCO_0                      ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    1587. 

  1587. <a name="l01555"></a>01555 <span class="preprocessor">#define  RCC_CFGR_MCO_1                      ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    1588. 

  1588. <a name="l01556"></a>01556 <span class="preprocessor">#define  RCC_CFGR_MCO_2                      ((u32)0x04000000)        </span><span class="comment">/* Bit 2 */</span>
    1589. 

  1589. <a name="l01557"></a>01557 
    1590. 

  1590. <a name="l01558"></a>01558 <span class="comment">/* MCO configuration */</span>
    1591. 

  1591. <a name="l01559"></a>01559 <span class="preprocessor">#define  RCC_CFGR_MCO_NOCLOCK                ((u32)0x00000000)        </span><span class="comment">/* No clock */</span>
    1592. 

  1592. <a name="l01560"></a>01560 <span class="preprocessor">#define  RCC_CFGR_MCO_SYSCLK                 ((u32)0x04000000)        </span><span class="comment">/* System clock selected */</span>
    1593. 

  1593. <a name="l01561"></a>01561 <span class="preprocessor">#define  RCC_CFGR_MCO_HSI                    ((u32)0x05000000)        </span><span class="comment">/* Internal 8 MHz RC oscillator clock selected */</span>
    1594. 

  1594. <a name="l01562"></a>01562 <span class="preprocessor">#define  RCC_CFGR_MCO_HSE                    ((u32)0x06000000)        </span><span class="comment">/* External 1-25 MHz oscillator clock selected */</span>
    1595. 

  1595. <a name="l01563"></a>01563 <span class="preprocessor">#define  RCC_CFGR_MCO_PLL                    ((u32)0x07000000)        </span><span class="comment">/* PLL clock divided by 2 selected*/</span>
    1596. 

  1596. <a name="l01564"></a>01564 
    1597. 

  1597. <a name="l01565"></a>01565 
    1598. 

  1598. <a name="l01566"></a>01566 <span class="comment">/*******************  Bit definition for RCC_CIR register  ********************/</span>
    1599. 

  1599. <a name="l01567"></a>01567 <span class="preprocessor">#define  RCC_CIR_LSIRDYF                     ((u32)0x00000001)        </span><span class="comment">/* LSI Ready Interrupt flag */</span>
    1600. 

  1600. <a name="l01568"></a>01568 <span class="preprocessor">#define  RCC_CIR_LSERDYF                     ((u32)0x00000002)        </span><span class="comment">/* LSE Ready Interrupt flag */</span>
    1601. 

  1601. <a name="l01569"></a>01569 <span class="preprocessor">#define  RCC_CIR_HSIRDYF                     ((u32)0x00000004)        </span><span class="comment">/* HSI Ready Interrupt flag */</span>
    1602. 

  1602. <a name="l01570"></a>01570 <span class="preprocessor">#define  RCC_CIR_HSERDYF                     ((u32)0x00000008)        </span><span class="comment">/* HSE Ready Interrupt flag */</span>
    1603. 

  1603. <a name="l01571"></a>01571 <span class="preprocessor">#define  RCC_CIR_PLLRDYF                     ((u32)0x00000010)        </span><span class="comment">/* PLL Ready Interrupt flag */</span>
    1604. 

  1604. <a name="l01572"></a>01572 <span class="preprocessor">#define  RCC_CIR_CSSF                        ((u32)0x00000080)        </span><span class="comment">/* Clock Security System Interrupt flag */</span>
    1605. 

  1605. <a name="l01573"></a>01573 <span class="preprocessor">#define  RCC_CIR_LSIRDYIE                    ((u32)0x00000100)        </span><span class="comment">/* LSI Ready Interrupt Enable */</span>
    1606. 

  1606. <a name="l01574"></a>01574 <span class="preprocessor">#define  RCC_CIR_LSERDYIE                    ((u32)0x00000200)        </span><span class="comment">/* LSE Ready Interrupt Enable */</span>
    1607. 

  1607. <a name="l01575"></a>01575 <span class="preprocessor">#define  RCC_CIR_HSIRDYIE                    ((u32)0x00000400)        </span><span class="comment">/* HSI Ready Interrupt Enable */</span>
    1608. 

  1608. <a name="l01576"></a>01576 <span class="preprocessor">#define  RCC_CIR_HSERDYIE                    ((u32)0x00000800)        </span><span class="comment">/* HSE Ready Interrupt Enable */</span>
    1609. 

  1609. <a name="l01577"></a>01577 <span class="preprocessor">#define  RCC_CIR_PLLRDYIE                    ((u32)0x00001000)        </span><span class="comment">/* PLL Ready Interrupt Enable */</span>
    1610. 

  1610. <a name="l01578"></a>01578 <span class="preprocessor">#define  RCC_CIR_LSIRDYC                     ((u32)0x00010000)        </span><span class="comment">/* LSI Ready Interrupt Clear */</span>
    1611. 

  1611. <a name="l01579"></a>01579 <span class="preprocessor">#define  RCC_CIR_LSERDYC                     ((u32)0x00020000)        </span><span class="comment">/* LSE Ready Interrupt Clear */</span>
    1612. 

  1612. <a name="l01580"></a>01580 <span class="preprocessor">#define  RCC_CIR_HSIRDYC                     ((u32)0x00040000)        </span><span class="comment">/* HSI Ready Interrupt Clear */</span>
    1613. 

  1613. <a name="l01581"></a>01581 <span class="preprocessor">#define  RCC_CIR_HSERDYC                     ((u32)0x00080000)        </span><span class="comment">/* HSE Ready Interrupt Clear */</span>
    1614. 

  1614. <a name="l01582"></a>01582 <span class="preprocessor">#define  RCC_CIR_PLLRDYC                     ((u32)0x00100000)        </span><span class="comment">/* PLL Ready Interrupt Clear */</span>
    1615. 

  1615. <a name="l01583"></a>01583 <span class="preprocessor">#define  RCC_CIR_CSSC                        ((u32)0x00800000)        </span><span class="comment">/* Clock Security System Interrupt Clear */</span>
    1616. 

  1616. <a name="l01584"></a>01584 
    1617. 

  1617. <a name="l01585"></a>01585 
    1618. 

  1618. <a name="l01586"></a>01586 <span class="comment">/*****************  Bit definition for RCC_APB2RSTR register  *****************/</span>
    1619. 

  1619. <a name="l01587"></a>01587 <span class="preprocessor">#define  RCC_APB2RSTR_AFIORST                ((u16)0x0001)            </span><span class="comment">/* Alternate Function I/O reset */</span>
    1620. 

  1620. <a name="l01588"></a>01588 <span class="preprocessor">#define  RCC_APB2RSTR_IOPARST                ((u16)0x0004)            </span><span class="comment">/* I/O port A reset */</span>
    1621. 

  1621. <a name="l01589"></a>01589 <span class="preprocessor">#define  RCC_APB2RSTR_IOPBRST                ((u16)0x0008)            </span><span class="comment">/* IO port B reset */</span>
    1622. 

  1622. <a name="l01590"></a>01590 <span class="preprocessor">#define  RCC_APB2RSTR_IOPCRST                ((u16)0x0010)            </span><span class="comment">/* IO port C reset */</span>
    1623. 

  1623. <a name="l01591"></a>01591 <span class="preprocessor">#define  RCC_APB2RSTR_IOPDRST                ((u16)0x0020)            </span><span class="comment">/* IO port D reset */</span>
    1624. 

  1624. <a name="l01592"></a>01592 <span class="preprocessor">#define  RCC_APB2RSTR_IOPERST                ((u16)0x0040)            </span><span class="comment">/* IO port E reset */</span>
    1625. 

  1625. <a name="l01593"></a>01593 <span class="preprocessor">#define  RCC_APB2RSTR_IOPFRST                ((u16)0x0080)            </span><span class="comment">/* IO port F reset */</span>
    1626. 

  1626. <a name="l01594"></a>01594 <span class="preprocessor">#define  RCC_APB2RSTR_IOPGRST                ((u16)0x0100)            </span><span class="comment">/* IO port G reset */</span>
    1627. 

  1627. <a name="l01595"></a>01595 <span class="preprocessor">#define  RCC_APB2RSTR_ADC1RST                ((u16)0x0200)            </span><span class="comment">/* ADC 1 interface reset */</span>
    1628. 

  1628. <a name="l01596"></a>01596 <span class="preprocessor">#define  RCC_APB2RSTR_ADC2RST                ((u16)0x0400)            </span><span class="comment">/* ADC 2 interface reset */</span>
    1629. 

  1629. <a name="l01597"></a>01597 <span class="preprocessor">#define  RCC_APB2RSTR_TIM1RST                ((u16)0x0800)            </span><span class="comment">/* TIM1 Timer reset */</span>
    1630. 

  1630. <a name="l01598"></a>01598 <span class="preprocessor">#define  RCC_APB2RSTR_SPI1RST                ((u16)0x1000)            </span><span class="comment">/* SPI 1 reset */</span>
    1631. 

  1631. <a name="l01599"></a>01599 <span class="preprocessor">#define  RCC_APB2RSTR_TIM8RST                ((u16)0x2000)            </span><span class="comment">/* TIM8 Timer reset */</span>
    1632. 

  1632. <a name="l01600"></a>01600 <span class="preprocessor">#define  RCC_APB2RSTR_USART1RST              ((u16)0x4000)            </span><span class="comment">/* USART1 reset */</span>
    1633. 

  1633. <a name="l01601"></a>01601 <span class="preprocessor">#define  RCC_APB2RSTR_ADC3RST                ((u16)0x8000)            </span><span class="comment">/* ADC3 interface reset */</span>
    1634. 

  1634. <a name="l01602"></a>01602 
    1635. 

  1635. <a name="l01603"></a>01603 
    1636. 

  1636. <a name="l01604"></a>01604 <span class="comment">/*****************  Bit definition for RCC_APB1RSTR register  *****************/</span>
    1637. 

  1637. <a name="l01605"></a>01605 <span class="preprocessor">#define  RCC_APB1RSTR_TIM2RST                ((u32)0x00000001)        </span><span class="comment">/* Timer 2 reset */</span>
    1638. 

  1638. <a name="l01606"></a>01606 <span class="preprocessor">#define  RCC_APB1RSTR_TIM3RST                ((u32)0x00000002)        </span><span class="comment">/* Timer 3 reset */</span>
    1639. 

  1639. <a name="l01607"></a>01607 <span class="preprocessor">#define  RCC_APB1RSTR_TIM4RST                ((u32)0x00000004)        </span><span class="comment">/* Timer 4 reset */</span>
    1640. 

  1640. <a name="l01608"></a>01608 <span class="preprocessor">#define  RCC_APB1RSTR_TIM5RST                ((u32)0x00000008)        </span><span class="comment">/* Timer 5 reset */</span>
    1641. 

  1641. <a name="l01609"></a>01609 <span class="preprocessor">#define  RCC_APB1RSTR_TIM6RST                ((u32)0x00000010)        </span><span class="comment">/* Timer 6 reset */</span>
    1642. 

  1642. <a name="l01610"></a>01610 <span class="preprocessor">#define  RCC_APB1RSTR_TIM7RST                ((u32)0x00000020)        </span><span class="comment">/* Timer 7 reset */</span>
    1643. 

  1643. <a name="l01611"></a>01611 <span class="preprocessor">#define  RCC_APB1RSTR_WWDGRST                ((u32)0x00000800)        </span><span class="comment">/* Window Watchdog reset */</span>
    1644. 

  1644. <a name="l01612"></a>01612 <span class="preprocessor">#define  RCC_APB1RSTR_SPI2RST                ((u32)0x00004000)        </span><span class="comment">/* SPI 2 reset */</span>
    1645. 

  1645. <a name="l01613"></a>01613 <span class="preprocessor">#define  RCC_APB1RSTR_SPI3RST                ((u32)0x00008000)        </span><span class="comment">/* SPI 3 reset */</span>
    1646. 

  1646. <a name="l01614"></a>01614 <span class="preprocessor">#define  RCC_APB1RSTR_USART2RST              ((u32)0x00020000)        </span><span class="comment">/* USART 2 reset */</span>
    1647. 

  1647. <a name="l01615"></a>01615 <span class="preprocessor">#define  RCC_APB1RSTR_USART3RST              ((u32)0x00040000)        </span><span class="comment">/* RUSART 3 reset */</span>
    1648. 

  1648. <a name="l01616"></a>01616 <span class="preprocessor">#define  RCC_APB1RSTR_UART4RST               ((u32)0x00080000)        </span><span class="comment">/* USART 4 reset */</span>
    1649. 

  1649. <a name="l01617"></a>01617 <span class="preprocessor">#define  RCC_APB1RSTR_UART5RST               ((u32)0x00100000)        </span><span class="comment">/* USART 5 reset */</span>
    1650. 

  1650. <a name="l01618"></a>01618 <span class="preprocessor">#define  RCC_APB1RSTR_I2C1RST                ((u32)0x00200000)        </span><span class="comment">/* I2C 1 reset */</span>
    1651. 

  1651. <a name="l01619"></a>01619 <span class="preprocessor">#define  RCC_APB1RSTR_I2C2RST                ((u32)0x00400000)        </span><span class="comment">/* I2C 2 reset */</span>
    1652. 

  1652. <a name="l01620"></a>01620 <span class="preprocessor">#define  RCC_APB1RSTR_USBRST                 ((u32)0x00800000)        </span><span class="comment">/* USB reset */</span>
    1653. 

  1653. <a name="l01621"></a>01621 <span class="preprocessor">#define  RCC_APB1RSTR_CANRST                 ((u32)0x02000000)        </span><span class="comment">/* CAN reset */</span>
    1654. 

  1654. <a name="l01622"></a>01622 <span class="preprocessor">#define  RCC_APB1RSTR_BKPRST                 ((u32)0x08000000)        </span><span class="comment">/* Backup interface reset */</span>
    1655. 

  1655. <a name="l01623"></a>01623 <span class="preprocessor">#define  RCC_APB1RSTR_PWRRST                 ((u32)0x10000000)        </span><span class="comment">/* Power interface reset */</span>
    1656. 

  1656. <a name="l01624"></a>01624 <span class="preprocessor">#define  RCC_APB1RSTR_DACRST                 ((u32)0x20000000)        </span><span class="comment">/* DAC interface reset */</span>
    1657. 

  1657. <a name="l01625"></a>01625 
    1658. 

  1658. <a name="l01626"></a>01626 
    1659. 

  1659. <a name="l01627"></a>01627 <span class="comment">/******************  Bit definition for RCC_AHBENR register  ******************/</span>
    1660. 

  1660. <a name="l01628"></a>01628 <span class="preprocessor">#define  RCC_AHBENR_DMA1EN                   ((u16)0x0001)            </span><span class="comment">/* DMA1 clock enable */</span>
    1661. 

  1661. <a name="l01629"></a>01629 <span class="preprocessor">#define  RCC_AHBENR_DMA2EN                   ((u16)0x0002)            </span><span class="comment">/* DMA2 clock enable */</span>
    1662. 

  1662. <a name="l01630"></a>01630 <span class="preprocessor">#define  RCC_AHBENR_SRAMEN                   ((u16)0x0004)            </span><span class="comment">/* SRAM interface clock enable */</span>
    1663. 

  1663. <a name="l01631"></a>01631 <span class="preprocessor">#define  RCC_AHBENR_FLITFEN                  ((u16)0x0010)            </span><span class="comment">/* FLITF clock enable */</span>
    1664. 

  1664. <a name="l01632"></a>01632 <span class="preprocessor">#define  RCC_AHBENR_CRCEN                    ((u16)0x0040)            </span><span class="comment">/* CRC clock enable */</span>
    1665. 

  1665. <a name="l01633"></a>01633 <span class="preprocessor">#define  RCC_AHBENR_FSMCEN                   ((u16)0x0100)            </span><span class="comment">/* FSMC clock enable */</span>
    1666. 

  1666. <a name="l01634"></a>01634 <span class="preprocessor">#define  RCC_AHBENR_SDIOEN                   ((u16)0x0400)            </span><span class="comment">/* SDIO clock enable */</span>
    1667. 

  1667. <a name="l01635"></a>01635 
    1668. 

  1668. <a name="l01636"></a>01636 
    1669. 

  1669. <a name="l01637"></a>01637 <span class="comment">/******************  Bit definition for RCC_APB2ENR register  *****************/</span>
    1670. 

  1670. <a name="l01638"></a>01638 <span class="preprocessor">#define  RCC_APB2ENR_AFIOEN                  ((u16)0x0001)            </span><span class="comment">/* Alternate Function I/O clock enable */</span>
    1671. 

  1671. <a name="l01639"></a>01639 <span class="preprocessor">#define  RCC_APB2ENR_IOPAEN                  ((u16)0x0004)            </span><span class="comment">/* I/O port A clock enable */</span>
    1672. 

  1672. <a name="l01640"></a>01640 <span class="preprocessor">#define  RCC_APB2ENR_IOPBEN                  ((u16)0x0008)            </span><span class="comment">/* I/O port B clock enable */</span>
    1673. 

  1673. <a name="l01641"></a>01641 <span class="preprocessor">#define  RCC_APB2ENR_IOPCEN                  ((u16)0x0010)            </span><span class="comment">/* I/O port C clock enable */</span>
    1674. 

  1674. <a name="l01642"></a>01642 <span class="preprocessor">#define  RCC_APB2ENR_IOPDEN                  ((u16)0x0020)            </span><span class="comment">/* I/O port D clock enable */</span>
    1675. 

  1675. <a name="l01643"></a>01643 <span class="preprocessor">#define  RCC_APB2ENR_IOPEEN                  ((u16)0x0040)            </span><span class="comment">/* I/O port E clock enable */</span>
    1676. 

  1676. <a name="l01644"></a>01644 <span class="preprocessor">#define  RCC_APB2ENR_IOPFEN                  ((u16)0x0080)            </span><span class="comment">/* I/O port F clock enable */</span>
    1677. 

  1677. <a name="l01645"></a>01645 <span class="preprocessor">#define  RCC_APB2ENR_IOPGEN                  ((u16)0x0100)            </span><span class="comment">/* I/O port G clock enable */</span>
    1678. 

  1678. <a name="l01646"></a>01646 <span class="preprocessor">#define  RCC_APB2ENR_ADC1EN                  ((u16)0x0200)            </span><span class="comment">/* ADC 1 interface clock enable */</span>
    1679. 

  1679. <a name="l01647"></a>01647 <span class="preprocessor">#define  RCC_APB2ENR_ADC2EN                  ((u16)0x0400)            </span><span class="comment">/* ADC 2 interface clock enable */</span>
    1680. 

  1680. <a name="l01648"></a>01648 <span class="preprocessor">#define  RCC_APB2ENR_TIM1EN                  ((u16)0x0800)            </span><span class="comment">/* TIM1 Timer clock enable */</span>
    1681. 

  1681. <a name="l01649"></a>01649 <span class="preprocessor">#define  RCC_APB2ENR_SPI1EN                  ((u16)0x1000)            </span><span class="comment">/* SPI 1 clock enable */</span>
    1682. 

  1682. <a name="l01650"></a>01650 <span class="preprocessor">#define  RCC_APB2ENR_TIM8EN                  ((u16)0x2000)            </span><span class="comment">/* TIM8 Timer clock enable */</span>
    1683. 

  1683. <a name="l01651"></a>01651 <span class="preprocessor">#define  RCC_APB2ENR_USART1EN                ((u16)0x4000)            </span><span class="comment">/* USART1 clock enable */</span>
    1684. 

  1684. <a name="l01652"></a>01652 <span class="preprocessor">#define  RCC_APB2ENR_ADC3EN                  ((u16)0x8000)            </span><span class="comment">/* DMA1 clock enable */</span>
    1685. 

  1685. <a name="l01653"></a>01653 
    1686. 

  1686. <a name="l01654"></a>01654 
    1687. 

  1687. <a name="l01655"></a>01655 <span class="comment">/*****************  Bit definition for RCC_APB1ENR register  ******************/</span>
    1688. 

  1688. <a name="l01656"></a>01656 <span class="preprocessor">#define  RCC_APB1ENR_TIM2EN                  ((u32)0x00000001)        </span><span class="comment">/* Timer 2 clock enabled*/</span>
    1689. 

  1689. <a name="l01657"></a>01657 <span class="preprocessor">#define  RCC_APB1ENR_TIM3EN                  ((u32)0x00000002)        </span><span class="comment">/* Timer 3 clock enable */</span>
    1690. 

  1690. <a name="l01658"></a>01658 <span class="preprocessor">#define  RCC_APB1ENR_TIM4EN                  ((u32)0x00000004)        </span><span class="comment">/* Timer 4 clock enable */</span>
    1691. 

  1691. <a name="l01659"></a>01659 <span class="preprocessor">#define  RCC_APB1ENR_TIM5EN                  ((u32)0x00000008)        </span><span class="comment">/* Timer 5 clock enable */</span>
    1692. 

  1692. <a name="l01660"></a>01660 <span class="preprocessor">#define  RCC_APB1ENR_TIM6EN                  ((u32)0x00000010)        </span><span class="comment">/* Timer 6 clock enable */</span>
    1693. 

  1693. <a name="l01661"></a>01661 <span class="preprocessor">#define  RCC_APB1ENR_TIM7EN                  ((u32)0x00000020)        </span><span class="comment">/* Timer 7 clock enable */</span>
    1694. 

  1694. <a name="l01662"></a>01662 <span class="preprocessor">#define  RCC_APB1ENR_WWDGEN                  ((u32)0x00000800)        </span><span class="comment">/* Window Watchdog clock enable */</span>
    1695. 

  1695. <a name="l01663"></a>01663 <span class="preprocessor">#define  RCC_APB1ENR_SPI2EN                  ((u32)0x00004000)        </span><span class="comment">/* SPI 2 clock enable */</span>
    1696. 

  1696. <a name="l01664"></a>01664 <span class="preprocessor">#define  RCC_APB1ENR_SPI3EN                  ((u32)0x00008000)        </span><span class="comment">/* SPI 3 clock enable */</span>
    1697. 

  1697. <a name="l01665"></a>01665 <span class="preprocessor">#define  RCC_APB1ENR_USART2EN                ((u32)0x00020000)        </span><span class="comment">/* USART 2 clock enable */</span>
    1698. 

  1698. <a name="l01666"></a>01666 <span class="preprocessor">#define  RCC_APB1ENR_USART3EN                ((u32)0x00040000)        </span><span class="comment">/* USART 3 clock enable */</span>
    1699. 

  1699. <a name="l01667"></a>01667 <span class="preprocessor">#define  RCC_APB1ENR_UART4EN                 ((u32)0x00080000)        </span><span class="comment">/* USART 4 clock enable */</span>
    1700. 

  1700. <a name="l01668"></a>01668 <span class="preprocessor">#define  RCC_APB1ENR_UART5EN                 ((u32)0x00100000)        </span><span class="comment">/* USART 5 clock enable */</span>
    1701. 

  1701. <a name="l01669"></a>01669 <span class="preprocessor">#define  RCC_APB1ENR_I2C1EN                  ((u32)0x00200000)        </span><span class="comment">/* I2C 1 clock enable */</span>
    1702. 

  1702. <a name="l01670"></a>01670 <span class="preprocessor">#define  RCC_APB1ENR_I2C2EN                  ((u32)0x00400000)        </span><span class="comment">/* I2C 2 clock enable */</span>
    1703. 

  1703. <a name="l01671"></a>01671 <span class="preprocessor">#define  RCC_APB1ENR_USBEN                   ((u32)0x00800000)        </span><span class="comment">/* USB clock enable */</span>
    1704. 

  1704. <a name="l01672"></a>01672 <span class="preprocessor">#define  RCC_APB1ENR_CANEN                   ((u32)0x02000000)        </span><span class="comment">/* CAN clock enable */</span>
    1705. 

  1705. <a name="l01673"></a>01673 <span class="preprocessor">#define  RCC_APB1ENR_BKPEN                   ((u32)0x08000000)        </span><span class="comment">/* Backup interface clock enable */</span>
    1706. 

  1706. <a name="l01674"></a>01674 <span class="preprocessor">#define  RCC_APB1ENR_PWREN                   ((u32)0x10000000)        </span><span class="comment">/* Power interface clock enable */</span>
    1707. 

  1707. <a name="l01675"></a>01675 <span class="preprocessor">#define  RCC_APB1ENR_DACEN                   ((u32)0x20000000)        </span><span class="comment">/* DAC interface clock enable */</span>
    1708. 

  1708. <a name="l01676"></a>01676 
    1709. 

  1709. <a name="l01677"></a>01677 
    1710. 

  1710. <a name="l01678"></a>01678 <span class="comment">/*******************  Bit definition for RCC_BDCR register  *******************/</span>
    1711. 

  1711. <a name="l01679"></a>01679 <span class="preprocessor">#define  RCC_BDCR_LSEON                      ((u32)0x00000001)        </span><span class="comment">/* External Low Speed oscillator enable */</span>
    1712. 

  1712. <a name="l01680"></a>01680 <span class="preprocessor">#define  RCC_BDCR_LSERDY                     ((u32)0x00000002)        </span><span class="comment">/* External Low Speed oscillator Ready */</span>
    1713. 

  1713. <a name="l01681"></a>01681 <span class="preprocessor">#define  RCC_BDCR_LSEBYP                     ((u32)0x00000004)        </span><span class="comment">/* External Low Speed oscillator Bypass */</span>
    1714. 

  1714. <a name="l01682"></a>01682 
    1715. 

  1715. <a name="l01683"></a>01683 <span class="preprocessor">#define  RCC_BDCR_RTCSEL                     ((u32)0x00000300)        </span><span class="comment">/* RTCSEL[1:0] bits (RTC clock source selection) */</span>
    1716. 

  1716. <a name="l01684"></a>01684 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_0                   ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    1717. 

  1717. <a name="l01685"></a>01685 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_1                   ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    1718. 

  1718. <a name="l01686"></a>01686 <span class="comment">/* RTC congiguration */</span>
    1719. 

  1719. <a name="l01687"></a>01687 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_NOCLOCK             ((u32)0x00000000)        </span><span class="comment">/* No clock */</span>
    1720. 

  1720. <a name="l01688"></a>01688 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_LSE                 ((u32)0x00000100)        </span><span class="comment">/* LSE oscillator clock used as RTC clock */</span>
    1721. 

  1721. <a name="l01689"></a>01689 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_LSI                 ((u32)0x00000200)        </span><span class="comment">/* LSI oscillator clock used as RTC clock */</span>
    1722. 

  1722. <a name="l01690"></a>01690 <span class="preprocessor">#define  RCC_BDCR_RTCSEL_HSE                 ((u32)0x00000300)        </span><span class="comment">/* HSE oscillator clock divided by 128 used as RTC clock */</span>
    1723. 

  1723. <a name="l01691"></a>01691 
    1724. 

  1724. <a name="l01692"></a>01692 <span class="preprocessor">#define  RCC_BDCR_RTCEN                      ((u32)0x00008000)        </span><span class="comment">/* RTC clock enable */</span>
    1725. 

  1725. <a name="l01693"></a>01693 <span class="preprocessor">#define  RCC_BDCR_BDRST                      ((u32)0x00010000)        </span><span class="comment">/* Backup domain software reset  */</span>
    1726. 

  1726. <a name="l01694"></a>01694 
    1727. 

  1727. <a name="l01695"></a>01695 
    1728. 

  1728. <a name="l01696"></a>01696 <span class="comment">/*******************  Bit definition for RCC_CSR register  ********************/</span>  
    1729. 

  1729. <a name="l01697"></a>01697 <span class="preprocessor">#define  RCC_CSR_LSION                       ((u32)0x00000001)        </span><span class="comment">/* Internal Low Speed oscillator enable */</span>
    1730. 

  1730. <a name="l01698"></a>01698 <span class="preprocessor">#define  RCC_CSR_LSIRDY                      ((u32)0x00000002)        </span><span class="comment">/* Internal Low Speed oscillator Ready */</span>
    1731. 

  1731. <a name="l01699"></a>01699 <span class="preprocessor">#define  RCC_CSR_RMVF                        ((u32)0x01000000)        </span><span class="comment">/* Remove reset flag */</span>
    1732. 

  1732. <a name="l01700"></a>01700 <span class="preprocessor">#define  RCC_CSR_PINRSTF                     ((u32)0x04000000)        </span><span class="comment">/* PIN reset flag */</span>
    1733. 

  1733. <a name="l01701"></a>01701 <span class="preprocessor">#define  RCC_CSR_PORRSTF                     ((u32)0x08000000)        </span><span class="comment">/* POR/PDR reset flag */</span>
    1734. 

  1734. <a name="l01702"></a>01702 <span class="preprocessor">#define  RCC_CSR_SFTRSTF                     ((u32)0x10000000)        </span><span class="comment">/* Software Reset flag */</span>
    1735. 

  1735. <a name="l01703"></a>01703 <span class="preprocessor">#define  RCC_CSR_IWDGRSTF                    ((u32)0x20000000)        </span><span class="comment">/* Independent Watchdog reset flag */</span>
    1736. 

  1736. <a name="l01704"></a>01704 <span class="preprocessor">#define  RCC_CSR_WWDGRSTF                    ((u32)0x40000000)        </span><span class="comment">/* Window watchdog reset flag */</span>
    1737. 

  1737. <a name="l01705"></a>01705 <span class="preprocessor">#define  RCC_CSR_LPWRRSTF                    ((u32)0x80000000)        </span><span class="comment">/* Low-Power reset flag */</span>
    1738. 

  1738. <a name="l01706"></a>01706 
    1739. 

  1739. <a name="l01707"></a>01707 
    1740. 

  1740. <a name="l01708"></a>01708 
    1741. 

  1741. <a name="l01709"></a>01709 <span class="comment">/******************************************************************************/</span>
    1742. 

  1742. <a name="l01710"></a>01710 <span class="comment">/*                                                                            */</span>
    1743. 

  1743. <a name="l01711"></a>01711 <span class="comment">/*                General Purpose and Alternate Function IO                   */</span>
    1744. 

  1744. <a name="l01712"></a>01712 <span class="comment">/*                                                                            */</span>
    1745. 

  1745. <a name="l01713"></a>01713 <span class="comment">/******************************************************************************/</span>
    1746. 

  1746. <a name="l01714"></a>01714 
    1747. 

  1747. <a name="l01715"></a>01715 <span class="comment">/*******************  Bit definition for GPIO_CRL register  *******************/</span>
    1748. 

  1748. <a name="l01716"></a>01716 <span class="preprocessor">#define  GPIO_CRL_MODE                       ((u32)0x33333333)        </span><span class="comment">/* Port x mode bits */</span>
    1749. 

  1749. <a name="l01717"></a>01717 
    1750. 

  1750. <a name="l01718"></a>01718 <span class="preprocessor">#define  GPIO_CRL_MODE0                      ((u32)0x00000003)        </span><span class="comment">/* MODE0[1:0] bits (Port x mode bits, pin 0) */</span>
    1751. 

  1751. <a name="l01719"></a>01719 <span class="preprocessor">#define  GPIO_CRL_MODE0_0                    ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    1752. 

  1752. <a name="l01720"></a>01720 <span class="preprocessor">#define  GPIO_CRL_MODE0_1                    ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    1753. 

  1753. <a name="l01721"></a>01721 
    1754. 

  1754. <a name="l01722"></a>01722 <span class="preprocessor">#define  GPIO_CRL_MODE1                      ((u32)0x00000030)        </span><span class="comment">/* MODE1[1:0] bits (Port x mode bits, pin 1) */</span>
    1755. 

  1755. <a name="l01723"></a>01723 <span class="preprocessor">#define  GPIO_CRL_MODE1_0                    ((u32)0x00000010)        </span><span class="comment">/* Bit 0 */</span>
    1756. 

  1756. <a name="l01724"></a>01724 <span class="preprocessor">#define  GPIO_CRL_MODE1_1                    ((u32)0x00000020)        </span><span class="comment">/* Bit 1 */</span>
    1757. 

  1757. <a name="l01725"></a>01725 
    1758. 

  1758. <a name="l01726"></a>01726 <span class="preprocessor">#define  GPIO_CRL_MODE2                      ((u32)0x00000300)        </span><span class="comment">/* MODE2[1:0] bits (Port x mode bits, pin 2) */</span>
    1759. 

  1759. <a name="l01727"></a>01727 <span class="preprocessor">#define  GPIO_CRL_MODE2_0                    ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    1760. 

  1760. <a name="l01728"></a>01728 <span class="preprocessor">#define  GPIO_CRL_MODE2_1                    ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    1761. 

  1761. <a name="l01729"></a>01729 
    1762. 

  1762. <a name="l01730"></a>01730 <span class="preprocessor">#define  GPIO_CRL_MODE3                      ((u32)0x00003000)        </span><span class="comment">/* MODE3[1:0] bits (Port x mode bits, pin 3) */</span>
    1763. 

  1763. <a name="l01731"></a>01731 <span class="preprocessor">#define  GPIO_CRL_MODE3_0                    ((u32)0x00001000)        </span><span class="comment">/* Bit 0 */</span>
    1764. 

  1764. <a name="l01732"></a>01732 <span class="preprocessor">#define  GPIO_CRL_MODE3_1                    ((u32)0x00002000)        </span><span class="comment">/* Bit 1 */</span>
    1765. 

  1765. <a name="l01733"></a>01733 
    1766. 

  1766. <a name="l01734"></a>01734 <span class="preprocessor">#define  GPIO_CRL_MODE4                      ((u32)0x00030000)        </span><span class="comment">/* MODE4[1:0] bits (Port x mode bits, pin 4) */</span>
    1767. 

  1767. <a name="l01735"></a>01735 <span class="preprocessor">#define  GPIO_CRL_MODE4_0                    ((u32)0x00010000)        </span><span class="comment">/* Bit 0 */</span>
    1768. 

  1768. <a name="l01736"></a>01736 <span class="preprocessor">#define  GPIO_CRL_MODE4_1                    ((u32)0x00020000)        </span><span class="comment">/* Bit 1 */</span>
    1769. 

  1769. <a name="l01737"></a>01737 
    1770. 

  1770. <a name="l01738"></a>01738 <span class="preprocessor">#define  GPIO_CRL_MODE5                      ((u32)0x00300000)        </span><span class="comment">/* MODE5[1:0] bits (Port x mode bits, pin 5) */</span>
    1771. 

  1771. <a name="l01739"></a>01739 <span class="preprocessor">#define  GPIO_CRL_MODE5_0                    ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    1772. 

  1772. <a name="l01740"></a>01740 <span class="preprocessor">#define  GPIO_CRL_MODE5_1                    ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    1773. 

  1773. <a name="l01741"></a>01741 
    1774. 

  1774. <a name="l01742"></a>01742 <span class="preprocessor">#define  GPIO_CRL_MODE6                      ((u32)0x03000000)        </span><span class="comment">/* MODE6[1:0] bits (Port x mode bits, pin 6) */</span>
    1775. 

  1775. <a name="l01743"></a>01743 <span class="preprocessor">#define  GPIO_CRL_MODE6_0                    ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    1776. 

  1776. <a name="l01744"></a>01744 <span class="preprocessor">#define  GPIO_CRL_MODE6_1                    ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    1777. 

  1777. <a name="l01745"></a>01745 
    1778. 

  1778. <a name="l01746"></a>01746 <span class="preprocessor">#define  GPIO_CRL_MODE7                      ((u32)0x30000000)        </span><span class="comment">/* MODE7[1:0] bits (Port x mode bits, pin 7) */</span>
    1779. 

  1779. <a name="l01747"></a>01747 <span class="preprocessor">#define  GPIO_CRL_MODE7_0                    ((u32)0x10000000)        </span><span class="comment">/* Bit 0 */</span>
    1780. 

  1780. <a name="l01748"></a>01748 <span class="preprocessor">#define  GPIO_CRL_MODE7_1                    ((u32)0x20000000)        </span><span class="comment">/* Bit 1 */</span>
    1781. 

  1781. <a name="l01749"></a>01749 
    1782. 

  1782. <a name="l01750"></a>01750 
    1783. 

  1783. <a name="l01751"></a>01751 <span class="preprocessor">#define  GPIO_CRL_CNF                        ((u32)0xCCCCCCCC)        </span><span class="comment">/* Port x configuration bits */</span>
    1784. 

  1784. <a name="l01752"></a>01752 
    1785. 

  1785. <a name="l01753"></a>01753 <span class="preprocessor">#define  GPIO_CRL_CNF0                       ((u32)0x0000000C)        </span><span class="comment">/* CNF0[1:0] bits (Port x configuration bits, pin 0) */</span>
    1786. 

  1786. <a name="l01754"></a>01754 <span class="preprocessor">#define  GPIO_CRL_CNF0_0                     ((u32)0x00000004)        </span><span class="comment">/* Bit 0 */</span>
    1787. 

  1787. <a name="l01755"></a>01755 <span class="preprocessor">#define  GPIO_CRL_CNF0_1                     ((u32)0x00000008)        </span><span class="comment">/* Bit 1 */</span>
    1788. 

  1788. <a name="l01756"></a>01756 
    1789. 

  1789. <a name="l01757"></a>01757 <span class="preprocessor">#define  GPIO_CRL_CNF1                       ((u32)0x000000C0)        </span><span class="comment">/* CNF1[1:0] bits (Port x configuration bits, pin 1) */</span>
    1790. 

  1790. <a name="l01758"></a>01758 <span class="preprocessor">#define  GPIO_CRL_CNF1_0                     ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    1791. 

  1791. <a name="l01759"></a>01759 <span class="preprocessor">#define  GPIO_CRL_CNF1_1                     ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    1792. 

  1792. <a name="l01760"></a>01760 
    1793. 

  1793. <a name="l01761"></a>01761 <span class="preprocessor">#define  GPIO_CRL_CNF2                       ((u32)0x00000C00)        </span><span class="comment">/* CNF2[1:0] bits (Port x configuration bits, pin 2) */</span>
    1794. 

  1794. <a name="l01762"></a>01762 <span class="preprocessor">#define  GPIO_CRL_CNF2_0                     ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    1795. 

  1795. <a name="l01763"></a>01763 <span class="preprocessor">#define  GPIO_CRL_CNF2_1                     ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    1796. 

  1796. <a name="l01764"></a>01764 
    1797. 

  1797. <a name="l01765"></a>01765 <span class="preprocessor">#define  GPIO_CRL_CNF3                       ((u32)0x0000C000)        </span><span class="comment">/* CNF3[1:0] bits (Port x configuration bits, pin 3) */</span>
    1798. 

  1798. <a name="l01766"></a>01766 <span class="preprocessor">#define  GPIO_CRL_CNF3_0                     ((u32)0x00004000)        </span><span class="comment">/* Bit 0 */</span>
    1799. 

  1799. <a name="l01767"></a>01767 <span class="preprocessor">#define  GPIO_CRL_CNF3_1                     ((u32)0x00008000)        </span><span class="comment">/* Bit 1 */</span>
    1800. 

  1800. <a name="l01768"></a>01768 
    1801. 

  1801. <a name="l01769"></a>01769 <span class="preprocessor">#define  GPIO_CRL_CNF4                       ((u32)0x000C0000)        </span><span class="comment">/* CNF4[1:0] bits (Port x configuration bits, pin 4) */</span>
    1802. 

  1802. <a name="l01770"></a>01770 <span class="preprocessor">#define  GPIO_CRL_CNF4_0                     ((u32)0x00040000)        </span><span class="comment">/* Bit 0 */</span>
    1803. 

  1803. <a name="l01771"></a>01771 <span class="preprocessor">#define  GPIO_CRL_CNF4_1                     ((u32)0x00080000)        </span><span class="comment">/* Bit 1 */</span>
    1804. 

  1804. <a name="l01772"></a>01772 
    1805. 

  1805. <a name="l01773"></a>01773 <span class="preprocessor">#define  GPIO_CRL_CNF5                       ((u32)0x00C00000)        </span><span class="comment">/* CNF5[1:0] bits (Port x configuration bits, pin 5) */</span>
    1806. 

  1806. <a name="l01774"></a>01774 <span class="preprocessor">#define  GPIO_CRL_CNF5_0                     ((u32)0x00400000)        </span><span class="comment">/* Bit 0 */</span>
    1807. 

  1807. <a name="l01775"></a>01775 <span class="preprocessor">#define  GPIO_CRL_CNF5_1                     ((u32)0x00800000)        </span><span class="comment">/* Bit 1 */</span>
    1808. 

  1808. <a name="l01776"></a>01776 
    1809. 

  1809. <a name="l01777"></a>01777 <span class="preprocessor">#define  GPIO_CRL_CNF6                       ((u32)0x0C000000)        </span><span class="comment">/* CNF6[1:0] bits (Port x configuration bits, pin 6) */</span>
    1810. 

  1810. <a name="l01778"></a>01778 <span class="preprocessor">#define  GPIO_CRL_CNF6_0                     ((u32)0x04000000)        </span><span class="comment">/* Bit 0 */</span>
    1811. 

  1811. <a name="l01779"></a>01779 <span class="preprocessor">#define  GPIO_CRL_CNF6_1                     ((u32)0x08000000)        </span><span class="comment">/* Bit 1 */</span>
    1812. 

  1812. <a name="l01780"></a>01780 
    1813. 

  1813. <a name="l01781"></a>01781 <span class="preprocessor">#define  GPIO_CRL_CNF7                       ((u32)0xC0000000)        </span><span class="comment">/* CNF7[1:0] bits (Port x configuration bits, pin 7) */</span>
    1814. 

  1814. <a name="l01782"></a>01782 <span class="preprocessor">#define  GPIO_CRL_CNF7_0                     ((u32)0x40000000)        </span><span class="comment">/* Bit 0 */</span>
    1815. 

  1815. <a name="l01783"></a>01783 <span class="preprocessor">#define  GPIO_CRL_CNF7_1                     ((u32)0x80000000)        </span><span class="comment">/* Bit 1 */</span>
    1816. 

  1816. <a name="l01784"></a>01784 
    1817. 

  1817. <a name="l01785"></a>01785 
    1818. 

  1818. <a name="l01786"></a>01786 <span class="comment">/*******************  Bit definition for GPIO_CRH register  *******************/</span>
    1819. 

  1819. <a name="l01787"></a>01787 <span class="preprocessor">#define  GPIO_CRH_MODE                       ((u32)0x33333333)        </span><span class="comment">/* Port x mode bits */</span>
    1820. 

  1820. <a name="l01788"></a>01788 
    1821. 

  1821. <a name="l01789"></a>01789 <span class="preprocessor">#define  GPIO_CRH_MODE8                      ((u32)0x00000003)        </span><span class="comment">/* MODE8[1:0] bits (Port x mode bits, pin 8) */</span>
    1822. 

  1822. <a name="l01790"></a>01790 <span class="preprocessor">#define  GPIO_CRH_MODE8_0                    ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    1823. 

  1823. <a name="l01791"></a>01791 <span class="preprocessor">#define  GPIO_CRH_MODE8_1                    ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    1824. 

  1824. <a name="l01792"></a>01792 
    1825. 

  1825. <a name="l01793"></a>01793 <span class="preprocessor">#define  GPIO_CRH_MODE9                      ((u32)0x00000030)        </span><span class="comment">/* MODE9[1:0] bits (Port x mode bits, pin 9) */</span>
    1826. 

  1826. <a name="l01794"></a>01794 <span class="preprocessor">#define  GPIO_CRH_MODE9_0                    ((u32)0x00000010)        </span><span class="comment">/* Bit 0 */</span>
    1827. 

  1827. <a name="l01795"></a>01795 <span class="preprocessor">#define  GPIO_CRH_MODE9_1                    ((u32)0x00000020)        </span><span class="comment">/* Bit 1 */</span>
    1828. 

  1828. <a name="l01796"></a>01796 
    1829. 

  1829. <a name="l01797"></a>01797 <span class="preprocessor">#define  GPIO_CRH_MODE10                     ((u32)0x00000300)        </span><span class="comment">/* MODE10[1:0] bits (Port x mode bits, pin 10) */</span>
    1830. 

  1830. <a name="l01798"></a>01798 <span class="preprocessor">#define  GPIO_CRH_MODE10_0                   ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    1831. 

  1831. <a name="l01799"></a>01799 <span class="preprocessor">#define  GPIO_CRH_MODE10_1                   ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    1832. 

  1832. <a name="l01800"></a>01800 
    1833. 

  1833. <a name="l01801"></a>01801 <span class="preprocessor">#define  GPIO_CRH_MODE11                     ((u32)0x00003000)        </span><span class="comment">/* MODE11[1:0] bits (Port x mode bits, pin 11) */</span>
    1834. 

  1834. <a name="l01802"></a>01802 <span class="preprocessor">#define  GPIO_CRH_MODE11_0                   ((u32)0x00001000)        </span><span class="comment">/* Bit 0 */</span>
    1835. 

  1835. <a name="l01803"></a>01803 <span class="preprocessor">#define  GPIO_CRH_MODE11_1                   ((u32)0x00002000)        </span><span class="comment">/* Bit 1 */</span>
    1836. 

  1836. <a name="l01804"></a>01804 
    1837. 

  1837. <a name="l01805"></a>01805 <span class="preprocessor">#define  GPIO_CRH_MODE12                     ((u32)0x00030000)        </span><span class="comment">/* MODE12[1:0] bits (Port x mode bits, pin 12) */</span>
    1838. 

  1838. <a name="l01806"></a>01806 <span class="preprocessor">#define  GPIO_CRH_MODE12_0                   ((u32)0x00010000)        </span><span class="comment">/* Bit 0 */</span>
    1839. 

  1839. <a name="l01807"></a>01807 <span class="preprocessor">#define  GPIO_CRH_MODE12_1                   ((u32)0x00020000)        </span><span class="comment">/* Bit 1 */</span>
    1840. 

  1840. <a name="l01808"></a>01808 
    1841. 

  1841. <a name="l01809"></a>01809 <span class="preprocessor">#define  GPIO_CRH_MODE13                     ((u32)0x00300000)        </span><span class="comment">/* MODE13[1:0] bits (Port x mode bits, pin 13) */</span>
    1842. 

  1842. <a name="l01810"></a>01810 <span class="preprocessor">#define  GPIO_CRH_MODE13_0                   ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    1843. 

  1843. <a name="l01811"></a>01811 <span class="preprocessor">#define  GPIO_CRH_MODE13_1                   ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    1844. 

  1844. <a name="l01812"></a>01812 
    1845. 

  1845. <a name="l01813"></a>01813 <span class="preprocessor">#define  GPIO_CRH_MODE14                     ((u32)0x03000000)        </span><span class="comment">/* MODE14[1:0] bits (Port x mode bits, pin 14) */</span>
    1846. 

  1846. <a name="l01814"></a>01814 <span class="preprocessor">#define  GPIO_CRH_MODE14_0                   ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    1847. 

  1847. <a name="l01815"></a>01815 <span class="preprocessor">#define  GPIO_CRH_MODE14_1                   ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    1848. 

  1848. <a name="l01816"></a>01816 
    1849. 

  1849. <a name="l01817"></a>01817 <span class="preprocessor">#define  GPIO_CRH_MODE15                     ((u32)0x30000000)        </span><span class="comment">/* MODE15[1:0] bits (Port x mode bits, pin 15) */</span>
    1850. 

  1850. <a name="l01818"></a>01818 <span class="preprocessor">#define  GPIO_CRH_MODE15_0                   ((u32)0x10000000)        </span><span class="comment">/* Bit 0 */</span>
    1851. 

  1851. <a name="l01819"></a>01819 <span class="preprocessor">#define  GPIO_CRH_MODE15_1                   ((u32)0x20000000)        </span><span class="comment">/* Bit 1 */</span>
    1852. 

  1852. <a name="l01820"></a>01820 
    1853. 

  1853. <a name="l01821"></a>01821 
    1854. 

  1854. <a name="l01822"></a>01822 <span class="preprocessor">#define  GPIO_CRH_CNF                        ((u32)0xCCCCCCCC)        </span><span class="comment">/* Port x configuration bits */</span>
    1855. 

  1855. <a name="l01823"></a>01823 
    1856. 

  1856. <a name="l01824"></a>01824 <span class="preprocessor">#define  GPIO_CRH_CNF8                       ((u32)0x0000000C)        </span><span class="comment">/* CNF8[1:0] bits (Port x configuration bits, pin 8) */</span>
    1857. 

  1857. <a name="l01825"></a>01825 <span class="preprocessor">#define  GPIO_CRH_CNF8_0                     ((u32)0x00000004)        </span><span class="comment">/* Bit 0 */</span>
    1858. 

  1858. <a name="l01826"></a>01826 <span class="preprocessor">#define  GPIO_CRH_CNF8_1                     ((u32)0x00000008)        </span><span class="comment">/* Bit 1 */</span>
    1859. 

  1859. <a name="l01827"></a>01827 
    1860. 

  1860. <a name="l01828"></a>01828 <span class="preprocessor">#define  GPIO_CRH_CNF9                       ((u32)0x000000C0)        </span><span class="comment">/* CNF9[1:0] bits (Port x configuration bits, pin 9) */</span>
    1861. 

  1861. <a name="l01829"></a>01829 <span class="preprocessor">#define  GPIO_CRH_CNF9_0                     ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    1862. 

  1862. <a name="l01830"></a>01830 <span class="preprocessor">#define  GPIO_CRH_CNF9_1                     ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    1863. 

  1863. <a name="l01831"></a>01831 
    1864. 

  1864. <a name="l01832"></a>01832 <span class="preprocessor">#define  GPIO_CRH_CNF10                      ((u32)0x00000C00)        </span><span class="comment">/* CNF10[1:0] bits (Port x configuration bits, pin 10) */</span>
    1865. 

  1865. <a name="l01833"></a>01833 <span class="preprocessor">#define  GPIO_CRH_CNF10_0                    ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    1866. 

  1866. <a name="l01834"></a>01834 <span class="preprocessor">#define  GPIO_CRH_CNF10_1                    ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    1867. 

  1867. <a name="l01835"></a>01835 
    1868. 

  1868. <a name="l01836"></a>01836 <span class="preprocessor">#define  GPIO_CRH_CNF11                      ((u32)0x0000C000)        </span><span class="comment">/* CNF11[1:0] bits (Port x configuration bits, pin 11) */</span>
    1869. 

  1869. <a name="l01837"></a>01837 <span class="preprocessor">#define  GPIO_CRH_CNF11_0                    ((u32)0x00004000)        </span><span class="comment">/* Bit 0 */</span>
    1870. 

  1870. <a name="l01838"></a>01838 <span class="preprocessor">#define  GPIO_CRH_CNF11_1                    ((u32)0x00008000)        </span><span class="comment">/* Bit 1 */</span>
    1871. 

  1871. <a name="l01839"></a>01839 
    1872. 

  1872. <a name="l01840"></a>01840 <span class="preprocessor">#define  GPIO_CRH_CNF12                      ((u32)0x000C0000)        </span><span class="comment">/* CNF12[1:0] bits (Port x configuration bits, pin 12) */</span>
    1873. 

  1873. <a name="l01841"></a>01841 <span class="preprocessor">#define  GPIO_CRH_CNF12_0                    ((u32)0x00040000)        </span><span class="comment">/* Bit 0 */</span>
    1874. 

  1874. <a name="l01842"></a>01842 <span class="preprocessor">#define  GPIO_CRH_CNF12_1                    ((u32)0x00080000)        </span><span class="comment">/* Bit 1 */</span>
    1875. 

  1875. <a name="l01843"></a>01843 
    1876. 

  1876. <a name="l01844"></a>01844 <span class="preprocessor">#define  GPIO_CRH_CNF13                      ((u32)0x00C00000)        </span><span class="comment">/* CNF13[1:0] bits (Port x configuration bits, pin 13) */</span>
    1877. 

  1877. <a name="l01845"></a>01845 <span class="preprocessor">#define  GPIO_CRH_CNF13_0                    ((u32)0x00400000)        </span><span class="comment">/* Bit 0 */</span>
    1878. 

  1878. <a name="l01846"></a>01846 <span class="preprocessor">#define  GPIO_CRH_CNF13_1                    ((u32)0x00800000)        </span><span class="comment">/* Bit 1 */</span>
    1879. 

  1879. <a name="l01847"></a>01847 
    1880. 

  1880. <a name="l01848"></a>01848 <span class="preprocessor">#define  GPIO_CRH_CNF14                      ((u32)0x0C000000)        </span><span class="comment">/* CNF14[1:0] bits (Port x configuration bits, pin 14) */</span>
    1881. 

  1881. <a name="l01849"></a>01849 <span class="preprocessor">#define  GPIO_CRH_CNF14_0                    ((u32)0x04000000)        </span><span class="comment">/* Bit 0 */</span>
    1882. 

  1882. <a name="l01850"></a>01850 <span class="preprocessor">#define  GPIO_CRH_CNF14_1                    ((u32)0x08000000)        </span><span class="comment">/* Bit 1 */</span>
    1883. 

  1883. <a name="l01851"></a>01851 
    1884. 

  1884. <a name="l01852"></a>01852 <span class="preprocessor">#define  GPIO_CRH_CNF15                      ((u32)0xC0000000)        </span><span class="comment">/* CNF15[1:0] bits (Port x configuration bits, pin 15) */</span>
    1885. 

  1885. <a name="l01853"></a>01853 <span class="preprocessor">#define  GPIO_CRH_CNF15_0                    ((u32)0x40000000)        </span><span class="comment">/* Bit 0 */</span>
    1886. 

  1886. <a name="l01854"></a>01854 <span class="preprocessor">#define  GPIO_CRH_CNF15_1                    ((u32)0x80000000)        </span><span class="comment">/* Bit 1 */</span>
    1887. 

  1887. <a name="l01855"></a>01855 
    1888. 

  1888. <a name="l01856"></a>01856 
    1889. 

  1889. <a name="l01857"></a>01857 <span class="comment">/*******************  Bit definition for GPIO_IDR register  *******************/</span>
    1890. 

  1890. <a name="l01858"></a>01858 <span class="preprocessor">#define GPIO_IDR_IDR0                        ((u16)0x0001)            </span><span class="comment">/* Port input data, bit 0 */</span>
    1891. 

  1891. <a name="l01859"></a>01859 <span class="preprocessor">#define GPIO_IDR_IDR1                        ((u16)0x0002)            </span><span class="comment">/* Port input data, bit 1 */</span>
    1892. 

  1892. <a name="l01860"></a>01860 <span class="preprocessor">#define GPIO_IDR_IDR2                        ((u16)0x0004)            </span><span class="comment">/* Port input data, bit 2 */</span>
    1893. 

  1893. <a name="l01861"></a>01861 <span class="preprocessor">#define GPIO_IDR_IDR3                        ((u16)0x0008)            </span><span class="comment">/* Port input data, bit 3 */</span>
    1894. 

  1894. <a name="l01862"></a>01862 <span class="preprocessor">#define GPIO_IDR_IDR4                        ((u16)0x0010)            </span><span class="comment">/* Port input data, bit 4 */</span>
    1895. 

  1895. <a name="l01863"></a>01863 <span class="preprocessor">#define GPIO_IDR_IDR5                        ((u16)0x0020)            </span><span class="comment">/* Port input data, bit 5 */</span>
    1896. 

  1896. <a name="l01864"></a>01864 <span class="preprocessor">#define GPIO_IDR_IDR6                        ((u16)0x0040)            </span><span class="comment">/* Port input data, bit 6 */</span>
    1897. 

  1897. <a name="l01865"></a>01865 <span class="preprocessor">#define GPIO_IDR_IDR7                        ((u16)0x0080)            </span><span class="comment">/* Port input data, bit 7 */</span>
    1898. 

  1898. <a name="l01866"></a>01866 <span class="preprocessor">#define GPIO_IDR_IDR8                        ((u16)0x0100)            </span><span class="comment">/* Port input data, bit 8 */</span>
    1899. 

  1899. <a name="l01867"></a>01867 <span class="preprocessor">#define GPIO_IDR_IDR9                        ((u16)0x0200)            </span><span class="comment">/* Port input data, bit 9 */</span>
    1900. 

  1900. <a name="l01868"></a>01868 <span class="preprocessor">#define GPIO_IDR_IDR10                       ((u16)0x0400)            </span><span class="comment">/* Port input data, bit 10 */</span>
    1901. 

  1901. <a name="l01869"></a>01869 <span class="preprocessor">#define GPIO_IDR_IDR11                       ((u16)0x0800)            </span><span class="comment">/* Port input data, bit 11 */</span>
    1902. 

  1902. <a name="l01870"></a>01870 <span class="preprocessor">#define GPIO_IDR_IDR12                       ((u16)0x1000)            </span><span class="comment">/* Port input data, bit 12 */</span>
    1903. 

  1903. <a name="l01871"></a>01871 <span class="preprocessor">#define GPIO_IDR_IDR13                       ((u16)0x2000)            </span><span class="comment">/* Port input data, bit 13 */</span>
    1904. 

  1904. <a name="l01872"></a>01872 <span class="preprocessor">#define GPIO_IDR_IDR14                       ((u16)0x4000)            </span><span class="comment">/* Port input data, bit 14 */</span>
    1905. 

  1905. <a name="l01873"></a>01873 <span class="preprocessor">#define GPIO_IDR_IDR15                       ((u16)0x8000)            </span><span class="comment">/* Port input data, bit 15 */</span>
    1906. 

  1906. <a name="l01874"></a>01874 
    1907. 

  1907. <a name="l01875"></a>01875 
    1908. 

  1908. <a name="l01876"></a>01876 <span class="comment">/*******************  Bit definition for GPIO_ODR register  *******************/</span>
    1909. 

  1909. <a name="l01877"></a>01877 <span class="preprocessor">#define GPIO_ODR_ODR0                        ((u16)0x0001)            </span><span class="comment">/* Port output data, bit 0 */</span>
    1910. 

  1910. <a name="l01878"></a>01878 <span class="preprocessor">#define GPIO_ODR_ODR1                        ((u16)0x0002)            </span><span class="comment">/* Port output data, bit 1 */</span>
    1911. 

  1911. <a name="l01879"></a>01879 <span class="preprocessor">#define GPIO_ODR_ODR2                        ((u16)0x0004)            </span><span class="comment">/* Port output data, bit 2 */</span>
    1912. 

  1912. <a name="l01880"></a>01880 <span class="preprocessor">#define GPIO_ODR_ODR3                        ((u16)0x0008)            </span><span class="comment">/* Port output data, bit 3 */</span>
    1913. 

  1913. <a name="l01881"></a>01881 <span class="preprocessor">#define GPIO_ODR_ODR4                        ((u16)0x0010)            </span><span class="comment">/* Port output data, bit 4 */</span>
    1914. 

  1914. <a name="l01882"></a>01882 <span class="preprocessor">#define GPIO_ODR_ODR5                        ((u16)0x0020)            </span><span class="comment">/* Port output data, bit 5 */</span>
    1915. 

  1915. <a name="l01883"></a>01883 <span class="preprocessor">#define GPIO_ODR_ODR6                        ((u16)0x0040)            </span><span class="comment">/* Port output data, bit 6 */</span>
    1916. 

  1916. <a name="l01884"></a>01884 <span class="preprocessor">#define GPIO_ODR_ODR7                        ((u16)0x0080)            </span><span class="comment">/* Port output data, bit 7 */</span>
    1917. 

  1917. <a name="l01885"></a>01885 <span class="preprocessor">#define GPIO_ODR_ODR8                        ((u16)0x0100)            </span><span class="comment">/* Port output data, bit 8 */</span>
    1918. 

  1918. <a name="l01886"></a>01886 <span class="preprocessor">#define GPIO_ODR_ODR9                        ((u16)0x0200)            </span><span class="comment">/* Port output data, bit 9 */</span>
    1919. 

  1919. <a name="l01887"></a>01887 <span class="preprocessor">#define GPIO_ODR_ODR10                       ((u16)0x0400)            </span><span class="comment">/* Port output data, bit 10 */</span>
    1920. 

  1920. <a name="l01888"></a>01888 <span class="preprocessor">#define GPIO_ODR_ODR11                       ((u16)0x0800)            </span><span class="comment">/* Port output data, bit 11 */</span>
    1921. 

  1921. <a name="l01889"></a>01889 <span class="preprocessor">#define GPIO_ODR_ODR12                       ((u16)0x1000)            </span><span class="comment">/* Port output data, bit 12 */</span>
    1922. 

  1922. <a name="l01890"></a>01890 <span class="preprocessor">#define GPIO_ODR_ODR13                       ((u16)0x2000)            </span><span class="comment">/* Port output data, bit 13 */</span>
    1923. 

  1923. <a name="l01891"></a>01891 <span class="preprocessor">#define GPIO_ODR_ODR14                       ((u16)0x4000)            </span><span class="comment">/* Port output data, bit 14 */</span>
    1924. 

  1924. <a name="l01892"></a>01892 <span class="preprocessor">#define GPIO_ODR_ODR15                       ((u16)0x8000)            </span><span class="comment">/* Port output data, bit 15 */</span>
    1925. 

  1925. <a name="l01893"></a>01893 
    1926. 

  1926. <a name="l01894"></a>01894 
    1927. 

  1927. <a name="l01895"></a>01895 <span class="comment">/******************  Bit definition for GPIO_BSRR register  *******************/</span>
    1928. 

  1928. <a name="l01896"></a>01896 <span class="preprocessor">#define GPIO_BSRR_BS0                        ((u32)0x00000001)        </span><span class="comment">/* Port x Set bit 0 */</span>
    1929. 

  1929. <a name="l01897"></a>01897 <span class="preprocessor">#define GPIO_BSRR_BS1                        ((u32)0x00000002)        </span><span class="comment">/* Port x Set bit 1 */</span>
    1930. 

  1930. <a name="l01898"></a>01898 <span class="preprocessor">#define GPIO_BSRR_BS2                        ((u32)0x00000004)        </span><span class="comment">/* Port x Set bit 2 */</span>
    1931. 

  1931. <a name="l01899"></a>01899 <span class="preprocessor">#define GPIO_BSRR_BS3                        ((u32)0x00000008)        </span><span class="comment">/* Port x Set bit 3 */</span>
    1932. 

  1932. <a name="l01900"></a>01900 <span class="preprocessor">#define GPIO_BSRR_BS4                        ((u32)0x00000010)        </span><span class="comment">/* Port x Set bit 4 */</span>
    1933. 

  1933. <a name="l01901"></a>01901 <span class="preprocessor">#define GPIO_BSRR_BS5                        ((u32)0x00000020)        </span><span class="comment">/* Port x Set bit 5 */</span>
    1934. 

  1934. <a name="l01902"></a>01902 <span class="preprocessor">#define GPIO_BSRR_BS6                        ((u32)0x00000040)        </span><span class="comment">/* Port x Set bit 6 */</span>
    1935. 

  1935. <a name="l01903"></a>01903 <span class="preprocessor">#define GPIO_BSRR_BS7                        ((u32)0x00000080)        </span><span class="comment">/* Port x Set bit 7 */</span>
    1936. 

  1936. <a name="l01904"></a>01904 <span class="preprocessor">#define GPIO_BSRR_BS8                        ((u32)0x00000100)        </span><span class="comment">/* Port x Set bit 8 */</span>
    1937. 

  1937. <a name="l01905"></a>01905 <span class="preprocessor">#define GPIO_BSRR_BS9                        ((u32)0x00000200)        </span><span class="comment">/* Port x Set bit 9 */</span>
    1938. 

  1938. <a name="l01906"></a>01906 <span class="preprocessor">#define GPIO_BSRR_BS10                       ((u32)0x00000400)        </span><span class="comment">/* Port x Set bit 10 */</span>
    1939. 

  1939. <a name="l01907"></a>01907 <span class="preprocessor">#define GPIO_BSRR_BS11                       ((u32)0x00000800)        </span><span class="comment">/* Port x Set bit 11 */</span>
    1940. 

  1940. <a name="l01908"></a>01908 <span class="preprocessor">#define GPIO_BSRR_BS12                       ((u32)0x00001000)        </span><span class="comment">/* Port x Set bit 12 */</span>
    1941. 

  1941. <a name="l01909"></a>01909 <span class="preprocessor">#define GPIO_BSRR_BS13                       ((u32)0x00002000)        </span><span class="comment">/* Port x Set bit 13 */</span>
    1942. 

  1942. <a name="l01910"></a>01910 <span class="preprocessor">#define GPIO_BSRR_BS14                       ((u32)0x00004000)        </span><span class="comment">/* Port x Set bit 14 */</span>
    1943. 

  1943. <a name="l01911"></a>01911 <span class="preprocessor">#define GPIO_BSRR_BS15                       ((u32)0x00008000)        </span><span class="comment">/* Port x Set bit 15 */</span>
    1944. 

  1944. <a name="l01912"></a>01912 
    1945. 

  1945. <a name="l01913"></a>01913 <span class="preprocessor">#define GPIO_BSRR_BR0                        ((u32)0x00010000)        </span><span class="comment">/* Port x Reset bit 0 */</span>
    1946. 

  1946. <a name="l01914"></a>01914 <span class="preprocessor">#define GPIO_BSRR_BR1                        ((u32)0x00020000)        </span><span class="comment">/* Port x Reset bit 1 */</span>
    1947. 

  1947. <a name="l01915"></a>01915 <span class="preprocessor">#define GPIO_BSRR_BR2                        ((u32)0x00040000)        </span><span class="comment">/* Port x Reset bit 2 */</span>
    1948. 

  1948. <a name="l01916"></a>01916 <span class="preprocessor">#define GPIO_BSRR_BR3                        ((u32)0x00080000)        </span><span class="comment">/* Port x Reset bit 3 */</span>
    1949. 

  1949. <a name="l01917"></a>01917 <span class="preprocessor">#define GPIO_BSRR_BR4                        ((u32)0x00100000)        </span><span class="comment">/* Port x Reset bit 4 */</span>
    1950. 

  1950. <a name="l01918"></a>01918 <span class="preprocessor">#define GPIO_BSRR_BR5                        ((u32)0x00200000)        </span><span class="comment">/* Port x Reset bit 5 */</span>
    1951. 

  1951. <a name="l01919"></a>01919 <span class="preprocessor">#define GPIO_BSRR_BR6                        ((u32)0x00400000)        </span><span class="comment">/* Port x Reset bit 6 */</span>
    1952. 

  1952. <a name="l01920"></a>01920 <span class="preprocessor">#define GPIO_BSRR_BR7                        ((u32)0x00800000)        </span><span class="comment">/* Port x Reset bit 7 */</span>
    1953. 

  1953. <a name="l01921"></a>01921 <span class="preprocessor">#define GPIO_BSRR_BR8                        ((u32)0x01000000)        </span><span class="comment">/* Port x Reset bit 8 */</span>
    1954. 

  1954. <a name="l01922"></a>01922 <span class="preprocessor">#define GPIO_BSRR_BR9                        ((u32)0x02000000)        </span><span class="comment">/* Port x Reset bit 9 */</span>
    1955. 

  1955. <a name="l01923"></a>01923 <span class="preprocessor">#define GPIO_BSRR_BR10                       ((u32)0x04000000)        </span><span class="comment">/* Port x Reset bit 10 */</span>
    1956. 

  1956. <a name="l01924"></a>01924 <span class="preprocessor">#define GPIO_BSRR_BR11                       ((u32)0x08000000)        </span><span class="comment">/* Port x Reset bit 11 */</span>
    1957. 

  1957. <a name="l01925"></a>01925 <span class="preprocessor">#define GPIO_BSRR_BR12                       ((u32)0x10000000)        </span><span class="comment">/* Port x Reset bit 12 */</span>
    1958. 

  1958. <a name="l01926"></a>01926 <span class="preprocessor">#define GPIO_BSRR_BR13                       ((u32)0x20000000)        </span><span class="comment">/* Port x Reset bit 13 */</span>
    1959. 

  1959. <a name="l01927"></a>01927 <span class="preprocessor">#define GPIO_BSRR_BR14                       ((u32)0x40000000)        </span><span class="comment">/* Port x Reset bit 14 */</span>
    1960. 

  1960. <a name="l01928"></a>01928 <span class="preprocessor">#define GPIO_BSRR_BR15                       ((u32)0x80000000)        </span><span class="comment">/* Port x Reset bit 15 */</span>
    1961. 

  1961. <a name="l01929"></a>01929 
    1962. 

  1962. <a name="l01930"></a>01930 
    1963. 

  1963. <a name="l01931"></a>01931 <span class="comment">/*******************  Bit definition for GPIO_BRR register  *******************/</span>
    1964. 

  1964. <a name="l01932"></a>01932 <span class="preprocessor">#define GPIO_BRR_BR0                         ((u16)0x0001)            </span><span class="comment">/* Port x Reset bit 0 */</span>
    1965. 

  1965. <a name="l01933"></a>01933 <span class="preprocessor">#define GPIO_BRR_BR1                         ((u16)0x0002)            </span><span class="comment">/* Port x Reset bit 1 */</span>
    1966. 

  1966. <a name="l01934"></a>01934 <span class="preprocessor">#define GPIO_BRR_BR2                         ((u16)0x0004)            </span><span class="comment">/* Port x Reset bit 2 */</span>
    1967. 

  1967. <a name="l01935"></a>01935 <span class="preprocessor">#define GPIO_BRR_BR3                         ((u16)0x0008)            </span><span class="comment">/* Port x Reset bit 3 */</span>
    1968. 

  1968. <a name="l01936"></a>01936 <span class="preprocessor">#define GPIO_BRR_BR4                         ((u16)0x0010)            </span><span class="comment">/* Port x Reset bit 4 */</span>
    1969. 

  1969. <a name="l01937"></a>01937 <span class="preprocessor">#define GPIO_BRR_BR5                         ((u16)0x0020)            </span><span class="comment">/* Port x Reset bit 5 */</span>
    1970. 

  1970. <a name="l01938"></a>01938 <span class="preprocessor">#define GPIO_BRR_BR6                         ((u16)0x0040)            </span><span class="comment">/* Port x Reset bit 6 */</span>
    1971. 

  1971. <a name="l01939"></a>01939 <span class="preprocessor">#define GPIO_BRR_BR7                         ((u16)0x0080)            </span><span class="comment">/* Port x Reset bit 7 */</span>
    1972. 

  1972. <a name="l01940"></a>01940 <span class="preprocessor">#define GPIO_BRR_BR8                         ((u16)0x0100)            </span><span class="comment">/* Port x Reset bit 8 */</span>
    1973. 

  1973. <a name="l01941"></a>01941 <span class="preprocessor">#define GPIO_BRR_BR9                         ((u16)0x0200)            </span><span class="comment">/* Port x Reset bit 9 */</span>
    1974. 

  1974. <a name="l01942"></a>01942 <span class="preprocessor">#define GPIO_BRR_BR10                        ((u16)0x0400)            </span><span class="comment">/* Port x Reset bit 10 */</span>
    1975. 

  1975. <a name="l01943"></a>01943 <span class="preprocessor">#define GPIO_BRR_BR11                        ((u16)0x0800)            </span><span class="comment">/* Port x Reset bit 11 */</span>
    1976. 

  1976. <a name="l01944"></a>01944 <span class="preprocessor">#define GPIO_BRR_BR12                        ((u16)0x1000)            </span><span class="comment">/* Port x Reset bit 12 */</span>
    1977. 

  1977. <a name="l01945"></a>01945 <span class="preprocessor">#define GPIO_BRR_BR13                        ((u16)0x2000)            </span><span class="comment">/* Port x Reset bit 13 */</span>
    1978. 

  1978. <a name="l01946"></a>01946 <span class="preprocessor">#define GPIO_BRR_BR14                        ((u16)0x4000)            </span><span class="comment">/* Port x Reset bit 14 */</span>
    1979. 

  1979. <a name="l01947"></a>01947 <span class="preprocessor">#define GPIO_BRR_BR15                        ((u16)0x8000)            </span><span class="comment">/* Port x Reset bit 15 */</span>
    1980. 

  1980. <a name="l01948"></a>01948 
    1981. 

  1981. <a name="l01949"></a>01949 
    1982. 

  1982. <a name="l01950"></a>01950 <span class="comment">/******************  Bit definition for GPIO_LCKR register  *******************/</span>
    1983. 

  1983. <a name="l01951"></a>01951 <span class="preprocessor">#define GPIO_LCKR_LCK0                       ((u32)0x00000001)        </span><span class="comment">/* Port x Lock bit 0 */</span>
    1984. 

  1984. <a name="l01952"></a>01952 <span class="preprocessor">#define GPIO_LCKR_LCK1                       ((u32)0x00000002)        </span><span class="comment">/* Port x Lock bit 1 */</span>
    1985. 

  1985. <a name="l01953"></a>01953 <span class="preprocessor">#define GPIO_LCKR_LCK2                       ((u32)0x00000004)        </span><span class="comment">/* Port x Lock bit 2 */</span>
    1986. 

  1986. <a name="l01954"></a>01954 <span class="preprocessor">#define GPIO_LCKR_LCK3                       ((u32)0x00000008)        </span><span class="comment">/* Port x Lock bit 3 */</span>
    1987. 

  1987. <a name="l01955"></a>01955 <span class="preprocessor">#define GPIO_LCKR_LCK4                       ((u32)0x00000010)        </span><span class="comment">/* Port x Lock bit 4 */</span>
    1988. 

  1988. <a name="l01956"></a>01956 <span class="preprocessor">#define GPIO_LCKR_LCK5                       ((u32)0x00000020)        </span><span class="comment">/* Port x Lock bit 5 */</span>
    1989. 

  1989. <a name="l01957"></a>01957 <span class="preprocessor">#define GPIO_LCKR_LCK6                       ((u32)0x00000040)        </span><span class="comment">/* Port x Lock bit 6 */</span>
    1990. 

  1990. <a name="l01958"></a>01958 <span class="preprocessor">#define GPIO_LCKR_LCK7                       ((u32)0x00000080)        </span><span class="comment">/* Port x Lock bit 7 */</span>
    1991. 

  1991. <a name="l01959"></a>01959 <span class="preprocessor">#define GPIO_LCKR_LCK8                       ((u32)0x00000100)        </span><span class="comment">/* Port x Lock bit 8 */</span>
    1992. 

  1992. <a name="l01960"></a>01960 <span class="preprocessor">#define GPIO_LCKR_LCK9                       ((u32)0x00000200)        </span><span class="comment">/* Port x Lock bit 9 */</span>
    1993. 

  1993. <a name="l01961"></a>01961 <span class="preprocessor">#define GPIO_LCKR_LCK10                      ((u32)0x00000400)        </span><span class="comment">/* Port x Lock bit 10 */</span>
    1994. 

  1994. <a name="l01962"></a>01962 <span class="preprocessor">#define GPIO_LCKR_LCK11                      ((u32)0x00000800)        </span><span class="comment">/* Port x Lock bit 11 */</span>
    1995. 

  1995. <a name="l01963"></a>01963 <span class="preprocessor">#define GPIO_LCKR_LCK12                      ((u32)0x00001000)        </span><span class="comment">/* Port x Lock bit 12 */</span>
    1996. 

  1996. <a name="l01964"></a>01964 <span class="preprocessor">#define GPIO_LCKR_LCK13                      ((u32)0x00002000)        </span><span class="comment">/* Port x Lock bit 13 */</span>
    1997. 

  1997. <a name="l01965"></a>01965 <span class="preprocessor">#define GPIO_LCKR_LCK14                      ((u32)0x00004000)        </span><span class="comment">/* Port x Lock bit 14 */</span>
    1998. 

  1998. <a name="l01966"></a>01966 <span class="preprocessor">#define GPIO_LCKR_LCK15                      ((u32)0x00008000)        </span><span class="comment">/* Port x Lock bit 15 */</span>
    1999. 

  1999. <a name="l01967"></a>01967 <span class="preprocessor">#define GPIO_LCKR_LCKK                       ((u32)0x00010000)        </span><span class="comment">/* Lock key */</span>
    2000. 

  2000. <a name="l01968"></a>01968 
    2001. 

  2001. <a name="l01969"></a>01969 
    2002. 

  2002. <a name="l01970"></a>01970 <span class="comment">/*----------------------------------------------------------------------------*/</span>
    2003. 

  2003. <a name="l01971"></a>01971 
    2004. 

  2004. <a name="l01972"></a>01972 
    2005. 

  2005. <a name="l01973"></a>01973 <span class="comment">/******************  Bit definition for AFIO_EVCR register  *******************/</span>
    2006. 

  2006. <a name="l01974"></a>01974 <span class="preprocessor">#define AFIO_EVCR_PIN                        ((u8)0x0F)               </span><span class="comment">/* PIN[3:0] bits (Pin selection) */</span>
    2007. 

  2007. <a name="l01975"></a>01975 <span class="preprocessor">#define AFIO_EVCR_PIN_0                      ((u8)0x01)               </span><span class="comment">/* Bit 0 */</span>
    2008. 

  2008. <a name="l01976"></a>01976 <span class="preprocessor">#define AFIO_EVCR_PIN_1                      ((u8)0x02)               </span><span class="comment">/* Bit 1 */</span>
    2009. 

  2009. <a name="l01977"></a>01977 <span class="preprocessor">#define AFIO_EVCR_PIN_2                      ((u8)0x04)               </span><span class="comment">/* Bit 2 */</span>
    2010. 

  2010. <a name="l01978"></a>01978 <span class="preprocessor">#define AFIO_EVCR_PIN_3                      ((u8)0x08)               </span><span class="comment">/* Bit 3 */</span>
    2011. 

  2011. <a name="l01979"></a>01979 
    2012. 

  2012. <a name="l01980"></a>01980 <span class="comment">/* PIN configuration */</span>
    2013. 

  2013. <a name="l01981"></a>01981 <span class="preprocessor">#define AFIO_EVCR_PIN_PX0                    ((u8)0x00)               </span><span class="comment">/* Pin 0 selected */</span>
    2014. 

  2014. <a name="l01982"></a>01982 <span class="preprocessor">#define AFIO_EVCR_PIN_PX1                    ((u8)0x01)               </span><span class="comment">/* Pin 1 selected */</span>
    2015. 

  2015. <a name="l01983"></a>01983 <span class="preprocessor">#define AFIO_EVCR_PIN_PX2                    ((u8)0x02)               </span><span class="comment">/* Pin 2 selected */</span>
    2016. 

  2016. <a name="l01984"></a>01984 <span class="preprocessor">#define AFIO_EVCR_PIN_PX3                    ((u8)0x03)               </span><span class="comment">/* Pin 3 selected */</span>
    2017. 

  2017. <a name="l01985"></a>01985 <span class="preprocessor">#define AFIO_EVCR_PIN_PX4                    ((u8)0x04)               </span><span class="comment">/* Pin 4 selected */</span>
    2018. 

  2018. <a name="l01986"></a>01986 <span class="preprocessor">#define AFIO_EVCR_PIN_PX5                    ((u8)0x05)               </span><span class="comment">/* Pin 5 selected */</span>
    2019. 

  2019. <a name="l01987"></a>01987 <span class="preprocessor">#define AFIO_EVCR_PIN_PX6                    ((u8)0x06)               </span><span class="comment">/* Pin 6 selected */</span>
    2020. 

  2020. <a name="l01988"></a>01988 <span class="preprocessor">#define AFIO_EVCR_PIN_PX7                    ((u8)0x07)               </span><span class="comment">/* Pin 7 selected */</span>
    2021. 

  2021. <a name="l01989"></a>01989 <span class="preprocessor">#define AFIO_EVCR_PIN_PX8                    ((u8)0x08)               </span><span class="comment">/* Pin 8 selected */</span>
    2022. 

  2022. <a name="l01990"></a>01990 <span class="preprocessor">#define AFIO_EVCR_PIN_PX9                    ((u8)0x09)               </span><span class="comment">/* Pin 9 selected */</span>
    2023. 

  2023. <a name="l01991"></a>01991 <span class="preprocessor">#define AFIO_EVCR_PIN_PX10                   ((u8)0x0A)               </span><span class="comment">/* Pin 10 selected */</span>
    2024. 

  2024. <a name="l01992"></a>01992 <span class="preprocessor">#define AFIO_EVCR_PIN_PX11                   ((u8)0x0B)               </span><span class="comment">/* Pin 11 selected */</span>
    2025. 

  2025. <a name="l01993"></a>01993 <span class="preprocessor">#define AFIO_EVCR_PIN_PX12                   ((u8)0x0C)               </span><span class="comment">/* Pin 12 selected */</span>
    2026. 

  2026. <a name="l01994"></a>01994 <span class="preprocessor">#define AFIO_EVCR_PIN_PX13                   ((u8)0x0D)               </span><span class="comment">/* Pin 13 selected */</span>
    2027. 

  2027. <a name="l01995"></a>01995 <span class="preprocessor">#define AFIO_EVCR_PIN_PX14                   ((u8)0x0E)               </span><span class="comment">/* Pin 14 selected */</span>
    2028. 

  2028. <a name="l01996"></a>01996 <span class="preprocessor">#define AFIO_EVCR_PIN_PX15                   ((u8)0x0F)               </span><span class="comment">/* Pin 15 selected */</span>
    2029. 

  2029. <a name="l01997"></a>01997 
    2030. 

  2030. <a name="l01998"></a>01998 <span class="preprocessor">#define AFIO_EVCR_PORT                       ((u8)0x70)               </span><span class="comment">/* PORT[2:0] bits (Port selection) */</span>
    2031. 

  2031. <a name="l01999"></a>01999 <span class="preprocessor">#define AFIO_EVCR_PORT_0                     ((u8)0x10)               </span><span class="comment">/* Bit 0 */</span>
    2032. 

  2032. <a name="l02000"></a>02000 <span class="preprocessor">#define AFIO_EVCR_PORT_1                     ((u8)0x20)               </span><span class="comment">/* Bit 1 */</span>
    2033. 

  2033. <a name="l02001"></a>02001 <span class="preprocessor">#define AFIO_EVCR_PORT_2                     ((u8)0x40)               </span><span class="comment">/* Bit 2 */</span>
    2034. 

  2034. <a name="l02002"></a>02002 
    2035. 

  2035. <a name="l02003"></a>02003 <span class="comment">/* PORT configuration */</span>
    2036. 

  2036. <a name="l02004"></a>02004 <span class="preprocessor">#define AFIO_EVCR_PORT_PA                    ((u8)0x00)               </span><span class="comment">/* Port A selected */</span>
    2037. 

  2037. <a name="l02005"></a>02005 <span class="preprocessor">#define AFIO_EVCR_PORT_PB                    ((u8)0x10)               </span><span class="comment">/* Port B selected */</span>
    2038. 

  2038. <a name="l02006"></a>02006 <span class="preprocessor">#define AFIO_EVCR_PORT_PC                    ((u8)0x20)               </span><span class="comment">/* Port C selected */</span>
    2039. 

  2039. <a name="l02007"></a>02007 <span class="preprocessor">#define AFIO_EVCR_PORT_PD                    ((u8)0x30)               </span><span class="comment">/* Port D selected */</span>
    2040. 

  2040. <a name="l02008"></a>02008 <span class="preprocessor">#define AFIO_EVCR_PORT_PE                    ((u8)0x40)               </span><span class="comment">/* Port E selected */</span>
    2041. 

  2041. <a name="l02009"></a>02009 
    2042. 

  2042. <a name="l02010"></a>02010 <span class="preprocessor">#define AFIO_EVCR_EVOE                       ((u8)0x80)               </span><span class="comment">/* Event Output Enable */</span>
    2043. 

  2043. <a name="l02011"></a>02011 
    2044. 

  2044. <a name="l02012"></a>02012 
    2045. 

  2045. <a name="l02013"></a>02013 <span class="comment">/******************  Bit definition for AFIO_MAPR register  *******************/</span>
    2046. 

  2046. <a name="l02014"></a>02014 <span class="preprocessor">#define AFIO_MAPR_SPI1 _REMAP                ((u32)0x00000001)        </span><span class="comment">/* SPI1 remapping */</span>
    2047. 

  2047. <a name="l02015"></a>02015 <span class="preprocessor">#define AFIO_MAPR_I2C1_REMAP                 ((u32)0x00000002)        </span><span class="comment">/* I2C1 remapping */</span>
    2048. 

  2048. <a name="l02016"></a>02016 <span class="preprocessor">#define AFIO_MAPR_USART1_REMAP               ((u32)0x00000004)        </span><span class="comment">/* USART1 remapping */</span>
    2049. 

  2049. <a name="l02017"></a>02017 <span class="preprocessor">#define AFIO_MAPR_USART2_REMAP               ((u32)0x00000008)        </span><span class="comment">/* USART2 remapping */</span>
    2050. 

  2050. <a name="l02018"></a>02018 
    2051. 

  2051. <a name="l02019"></a>02019 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP               ((u32)0x00000030)        </span><span class="comment">/* USART3_REMAP[1:0] bits (USART3 remapping) */</span>
    2052. 

  2052. <a name="l02020"></a>02020 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP_0             ((u32)0x00000010)        </span><span class="comment">/* Bit 0 */</span>
    2053. 

  2053. <a name="l02021"></a>02021 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP_1             ((u32)0x00000020)        </span><span class="comment">/* Bit 1 */</span>
    2054. 

  2054. <a name="l02022"></a>02022 
    2055. 

  2055. <a name="l02023"></a>02023 <span class="comment">/* USART3_REMAP configuration */</span>
    2056. 

  2056. <a name="l02024"></a>02024 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((u32)0x00000000)        </span><span class="comment">/* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */</span>
    2057. 

  2057. <a name="l02025"></a>02025 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((u32)0x00000010)        </span><span class="comment">/* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */</span>
    2058. 

  2058. <a name="l02026"></a>02026 <span class="preprocessor">#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((u32)0x00000030)        </span><span class="comment">/* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */</span>
    2059. 

  2059. <a name="l02027"></a>02027 
    2060. 

  2060. <a name="l02028"></a>02028 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP                 ((u32)0x000000C0)        </span><span class="comment">/* TIM1_REMAP[1:0] bits (TIM1 remapping) */</span>
    2061. 

  2061. <a name="l02029"></a>02029 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP_0               ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    2062. 

  2062. <a name="l02030"></a>02030 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP_1               ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    2063. 

  2063. <a name="l02031"></a>02031 
    2064. 

  2064. <a name="l02032"></a>02032 <span class="comment">/* TIM1_REMAP configuration */</span>
    2065. 

  2065. <a name="l02033"></a>02033 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((u32)0x00000000)        </span><span class="comment">/* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */</span>
    2066. 

  2066. <a name="l02034"></a>02034 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((u32)0x00000040)        </span><span class="comment">/* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */</span>
    2067. 

  2067. <a name="l02035"></a>02035 <span class="preprocessor">#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((u32)0x000000C0)        </span><span class="comment">/* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */</span>
    2068. 

  2068. <a name="l02036"></a>02036 
    2069. 

  2069. <a name="l02037"></a>02037 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP                 ((u32)0x00000300)        </span><span class="comment">/* TIM2_REMAP[1:0] bits (TIM2 remapping) */</span>
    2070. 

  2070. <a name="l02038"></a>02038 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_0               ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    2071. 

  2071. <a name="l02039"></a>02039 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_1               ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    2072. 

  2072. <a name="l02040"></a>02040 
    2073. 

  2073. <a name="l02041"></a>02041 <span class="comment">/* TIM2_REMAP configuration */</span>
    2074. 

  2074. <a name="l02042"></a>02042 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((u32)0x00000000)        </span><span class="comment">/* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */</span>
    2075. 

  2075. <a name="l02043"></a>02043 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((u32)0x00000100)        </span><span class="comment">/* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */</span>
    2076. 

  2076. <a name="l02044"></a>02044 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((u32)0x00000200)        </span><span class="comment">/* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */</span>
    2077. 

  2077. <a name="l02045"></a>02045 <span class="preprocessor">#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((u32)0x00000300)        </span><span class="comment">/* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */</span>
    2078. 

  2078. <a name="l02046"></a>02046 
    2079. 

  2079. <a name="l02047"></a>02047 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP                 ((u32)0x00000C00)        </span><span class="comment">/* TIM3_REMAP[1:0] bits (TIM3 remapping) */</span>
    2080. 

  2080. <a name="l02048"></a>02048 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP_0               ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    2081. 

  2081. <a name="l02049"></a>02049 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP_1               ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    2082. 

  2082. <a name="l02050"></a>02050 
    2083. 

  2083. <a name="l02051"></a>02051 <span class="comment">/* TIM3_REMAP configuration */</span>
    2084. 

  2084. <a name="l02052"></a>02052 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((u32)0x00000000)        </span><span class="comment">/* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */</span>
    2085. 

  2085. <a name="l02053"></a>02053 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((u32)0x00000800)        </span><span class="comment">/* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */</span>
    2086. 

  2086. <a name="l02054"></a>02054 <span class="preprocessor">#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((u32)0x00000C00)        </span><span class="comment">/* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */</span>
    2087. 

  2087. <a name="l02055"></a>02055 
    2088. 

  2088. <a name="l02056"></a>02056 <span class="preprocessor">#define AFIO_MAPR_TIM4_REMAP                 ((u32)0x00001000)        </span><span class="comment">/* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */</span>
    2089. 

  2089. <a name="l02057"></a>02057 
    2090. 

  2090. <a name="l02058"></a>02058 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP                  ((u32)0x00006000)        </span><span class="comment">/* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */</span>
    2091. 

  2091. <a name="l02059"></a>02059 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP_0                ((u32)0x00002000)        </span><span class="comment">/* Bit 0 */</span>
    2092. 

  2092. <a name="l02060"></a>02060 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP_1                ((u32)0x00004000)        </span><span class="comment">/* Bit 1 */</span>
    2093. 

  2093. <a name="l02061"></a>02061 
    2094. 

  2094. <a name="l02062"></a>02062 <span class="comment">/* CAN_REMAP configuration */</span>
    2095. 

  2095. <a name="l02063"></a>02063 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP_REMAP1           ((u32)0x00000000)        </span><span class="comment">/* CANRX mapped to PA11, CANTX mapped to PA12 */</span>
    2096. 

  2096. <a name="l02064"></a>02064 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP_REMAP2           ((u32)0x00004000)        </span><span class="comment">/* CANRX mapped to PB8, CANTX mapped to PB9 */</span>
    2097. 

  2097. <a name="l02065"></a>02065 <span class="preprocessor">#define AFIO_MAPR_CAN_REMAP_REMAP3           ((u32)0x00006000)        </span><span class="comment">/* CANRX mapped to PD0, CANTX mapped to PD1 */</span>
    2098. 

  2098. <a name="l02066"></a>02066 
    2099. 

  2099. <a name="l02067"></a>02067 <span class="preprocessor">#define AFIO_MAPR_PD01_REMAP                 ((u32)0x00008000)        </span><span class="comment">/* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */</span>
    2100. 

  2100. <a name="l02068"></a>02068 <span class="preprocessor">#define AFIO_MAPR_TIM5CH4_IREMAP             ((u32)0x00010000)        </span><span class="comment">/* TIM5 Channel4 Internal Remap */</span>
    2101. 

  2101. <a name="l02069"></a>02069 <span class="preprocessor">#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((u32)0x00020000)        </span><span class="comment">/* ADC 1 External Trigger Injected Conversion remapping */</span>
    2102. 

  2102. <a name="l02070"></a>02070 <span class="preprocessor">#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((u32)0x00040000)        </span><span class="comment">/* ADC 1 External Trigger Regular Conversion remapping */</span>
    2103. 

  2103. <a name="l02071"></a>02071 <span class="preprocessor">#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((u32)0x00080000)        </span><span class="comment">/* ADC 2 External Trigger Injected Conversion remapping */</span>
    2104. 

  2104. <a name="l02072"></a>02072 <span class="preprocessor">#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((u32)0x00100000)        </span><span class="comment">/* ADC 2 External Trigger Regular Conversion remapping */</span>
    2105. 

  2105. <a name="l02073"></a>02073 
    2106. 

  2106. <a name="l02074"></a>02074 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG                    ((u32)0x07000000)        </span><span class="comment">/* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */</span>
    2107. 

  2107. <a name="l02075"></a>02075 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_0                  ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    2108. 

  2108. <a name="l02076"></a>02076 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_1                  ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    2109. 

  2109. <a name="l02077"></a>02077 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_2                  ((u32)0x04000000)        </span><span class="comment">/* Bit 2 */</span>
    2110. 

  2110. <a name="l02078"></a>02078 
    2111. 

  2111. <a name="l02079"></a>02079 <span class="comment">/* SWJ_CFG configuration */</span>
    2112. 

  2112. <a name="l02080"></a>02080 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_RESET              ((u32)0x00000000)        </span><span class="comment">/* Full SWJ (JTAG-DP + SW-DP) : Reset State */</span>
    2113. 

  2113. <a name="l02081"></a>02081 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((u32)0x01000000)        </span><span class="comment">/* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */</span>
    2114. 

  2114. <a name="l02082"></a>02082 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((u32)0x02000000)        </span><span class="comment">/* JTAG-DP Disabled and SW-DP Enabled */</span>
    2115. 

  2115. <a name="l02083"></a>02083 <span class="preprocessor">#define AFIO_MAPR_SWJ_CFG_DISABLE            ((u32)0x04000000)        </span><span class="comment">/* JTAG-DP Disabled and SW-DP Disabled */</span>
    2116. 

  2116. <a name="l02084"></a>02084 
    2117. 

  2117. <a name="l02085"></a>02085 
    2118. 

  2118. <a name="l02086"></a>02086 <span class="comment">/*****************  Bit definition for AFIO_EXTICR1 register  *****************/</span>
    2119. 

  2119. <a name="l02087"></a>02087 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0                   ((u16)0x000F)            </span><span class="comment">/* EXTI 0 configuration */</span>
    2120. 

  2120. <a name="l02088"></a>02088 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1                   ((u16)0x00F0)            </span><span class="comment">/* EXTI 1 configuration */</span>
    2121. 

  2121. <a name="l02089"></a>02089 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2                   ((u16)0x0F00)            </span><span class="comment">/* EXTI 2 configuration */</span>
    2122. 

  2122. <a name="l02090"></a>02090 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3                   ((u16)0xF000)            </span><span class="comment">/* EXTI 3 configuration */</span>
    2123. 

  2123. <a name="l02091"></a>02091 
    2124. 

  2124. <a name="l02092"></a>02092 <span class="comment">/* EXTI0 configuration */</span>
    2125. 

  2125. <a name="l02093"></a>02093 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PA                ((u16)0x0000)            </span><span class="comment">/* PA[0] pin */</span>
    2126. 

  2126. <a name="l02094"></a>02094 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PB                ((u16)0x0001)            </span><span class="comment">/* PB[0] pin */</span>
    2127. 

  2127. <a name="l02095"></a>02095 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PC                ((u16)0x0002)            </span><span class="comment">/* PC[0] pin */</span>
    2128. 

  2128. <a name="l02096"></a>02096 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PD                ((u16)0x0003)            </span><span class="comment">/* PD[0] pin */</span>
    2129. 

  2129. <a name="l02097"></a>02097 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PE                ((u16)0x0004)            </span><span class="comment">/* PE[0] pin */</span>
    2130. 

  2130. <a name="l02098"></a>02098 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PF                ((u16)0x0005)            </span><span class="comment">/* PF[0] pin */</span>
    2131. 

  2131. <a name="l02099"></a>02099 <span class="preprocessor">#define AFIO_EXTICR1_EXTI0_PG                ((u16)0x0006)            </span><span class="comment">/* PG[0] pin */</span>
    2132. 

  2132. <a name="l02100"></a>02100 
    2133. 

  2133. <a name="l02101"></a>02101 <span class="comment">/* EXTI1 configuration */</span>
    2134. 

  2134. <a name="l02102"></a>02102 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PA                ((u16)0x0000)            </span><span class="comment">/* PA[1] pin */</span>
    2135. 

  2135. <a name="l02103"></a>02103 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PB                ((u16)0x0010)            </span><span class="comment">/* PB[1] pin */</span>
    2136. 

  2136. <a name="l02104"></a>02104 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PC                ((u16)0x0020)            </span><span class="comment">/* PC[1] pin */</span>
    2137. 

  2137. <a name="l02105"></a>02105 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PD                ((u16)0x0030)            </span><span class="comment">/* PD[1] pin */</span>
    2138. 

  2138. <a name="l02106"></a>02106 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PE                ((u16)0x0040)            </span><span class="comment">/* PE[1] pin */</span>
    2139. 

  2139. <a name="l02107"></a>02107 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PF                ((u16)0x0050)            </span><span class="comment">/* PF[1] pin */</span>
    2140. 

  2140. <a name="l02108"></a>02108 <span class="preprocessor">#define AFIO_EXTICR1_EXTI1_PG                ((u16)0x0060)            </span><span class="comment">/* PG[1] pin */</span>
    2141. 

  2141. <a name="l02109"></a>02109 
    2142. 

  2142. <a name="l02110"></a>02110 <span class="comment">/* EXTI2 configuration */</span>  
    2143. 

  2143. <a name="l02111"></a>02111 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PA                ((u16)0x0000)            </span><span class="comment">/* PA[2] pin */</span>
    2144. 

  2144. <a name="l02112"></a>02112 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PB                ((u16)0x0100)            </span><span class="comment">/* PB[2] pin */</span>
    2145. 

  2145. <a name="l02113"></a>02113 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PC                ((u16)0x0200)            </span><span class="comment">/* PC[2] pin */</span>
    2146. 

  2146. <a name="l02114"></a>02114 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PD                ((u16)0x0300)            </span><span class="comment">/* PD[2] pin */</span>
    2147. 

  2147. <a name="l02115"></a>02115 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PE                ((u16)0x0400)            </span><span class="comment">/* PE[2] pin */</span>
    2148. 

  2148. <a name="l02116"></a>02116 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PF                ((u16)0x0500)            </span><span class="comment">/* PF[2] pin */</span>
    2149. 

  2149. <a name="l02117"></a>02117 <span class="preprocessor">#define AFIO_EXTICR1_EXTI2_PG                ((u16)0x0600)            </span><span class="comment">/* PG[2] pin */</span>
    2150. 

  2150. <a name="l02118"></a>02118 
    2151. 

  2151. <a name="l02119"></a>02119 <span class="comment">/* EXTI3 configuration */</span>
    2152. 

  2152. <a name="l02120"></a>02120 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PA                ((u16)0x0000)            </span><span class="comment">/* PA[3] pin */</span>
    2153. 

  2153. <a name="l02121"></a>02121 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PB                ((u16)0x1000)            </span><span class="comment">/* PB[3] pin */</span>
    2154. 

  2154. <a name="l02122"></a>02122 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PC                ((u16)0x2000)            </span><span class="comment">/* PC[3] pin */</span>
    2155. 

  2155. <a name="l02123"></a>02123 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PD                ((u16)0x3000)            </span><span class="comment">/* PD[3] pin */</span>
    2156. 

  2156. <a name="l02124"></a>02124 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PE                ((u16)0x4000)            </span><span class="comment">/* PE[3] pin */</span>
    2157. 

  2157. <a name="l02125"></a>02125 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PF                ((u16)0x5000)            </span><span class="comment">/* PF[3] pin */</span>
    2158. 

  2158. <a name="l02126"></a>02126 <span class="preprocessor">#define AFIO_EXTICR1_EXTI3_PG                ((u16)0x6000)            </span><span class="comment">/* PG[3] pin */</span>
    2159. 

  2159. <a name="l02127"></a>02127 
    2160. 

  2160. <a name="l02128"></a>02128 
    2161. 

  2161. <a name="l02129"></a>02129 <span class="comment">/*****************  Bit definition for AFIO_EXTICR2 register  *****************/</span>
    2162. 

  2162. <a name="l02130"></a>02130 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4                   ((u16)0x000F)            </span><span class="comment">/* EXTI 4 configuration */</span>
    2163. 

  2163. <a name="l02131"></a>02131 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5                   ((u16)0x00F0)            </span><span class="comment">/* EXTI 5 configuration */</span>
    2164. 

  2164. <a name="l02132"></a>02132 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6                   ((u16)0x0F00)            </span><span class="comment">/* EXTI 6 configuration */</span>
    2165. 

  2165. <a name="l02133"></a>02133 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7                   ((u16)0xF000)            </span><span class="comment">/* EXTI 7 configuration */</span>
    2166. 

  2166. <a name="l02134"></a>02134 
    2167. 

  2167. <a name="l02135"></a>02135 <span class="comment">/* EXTI4 configuration */</span>
    2168. 

  2168. <a name="l02136"></a>02136 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PA                ((u16)0x0000)            </span><span class="comment">/* PA[4] pin */</span>
    2169. 

  2169. <a name="l02137"></a>02137 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PB                ((u16)0x0001)            </span><span class="comment">/* PB[4] pin */</span>
    2170. 

  2170. <a name="l02138"></a>02138 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PC                ((u16)0x0002)            </span><span class="comment">/* PC[4] pin */</span>
    2171. 

  2171. <a name="l02139"></a>02139 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PD                ((u16)0x0003)            </span><span class="comment">/* PD[4] pin */</span>
    2172. 

  2172. <a name="l02140"></a>02140 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PE                ((u16)0x0004)            </span><span class="comment">/* PE[4] pin */</span>
    2173. 

  2173. <a name="l02141"></a>02141 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PF                ((u16)0x0005)            </span><span class="comment">/* PF[4] pin */</span>
    2174. 

  2174. <a name="l02142"></a>02142 <span class="preprocessor">#define AFIO_EXTICR2_EXTI4_PG                ((u16)0x0006)            </span><span class="comment">/* PG[4] pin */</span>
    2175. 

  2175. <a name="l02143"></a>02143 
    2176. 

  2176. <a name="l02144"></a>02144 <span class="comment">/* EXTI5 configuration */</span>
    2177. 

  2177. <a name="l02145"></a>02145 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PA                ((u16)0x0000)            </span><span class="comment">/* PA[5] pin */</span>
    2178. 

  2178. <a name="l02146"></a>02146 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PB                ((u16)0x0010)            </span><span class="comment">/* PB[5] pin */</span>
    2179. 

  2179. <a name="l02147"></a>02147 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PC                ((u16)0x0020)            </span><span class="comment">/* PC[5] pin */</span>
    2180. 

  2180. <a name="l02148"></a>02148 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PD                ((u16)0x0030)            </span><span class="comment">/* PD[5] pin */</span>
    2181. 

  2181. <a name="l02149"></a>02149 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PE                ((u16)0x0040)            </span><span class="comment">/* PE[5] pin */</span>
    2182. 

  2182. <a name="l02150"></a>02150 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PF                ((u16)0x0050)            </span><span class="comment">/* PF[5] pin */</span>
    2183. 

  2183. <a name="l02151"></a>02151 <span class="preprocessor">#define AFIO_EXTICR2_EXTI5_PG                ((u16)0x0060)            </span><span class="comment">/* PG[5] pin */</span>
    2184. 

  2184. <a name="l02152"></a>02152 
    2185. 

  2185. <a name="l02153"></a>02153 <span class="comment">/* EXTI6 configuration */</span>  
    2186. 

  2186. <a name="l02154"></a>02154 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PA                ((u16)0x0000)            </span><span class="comment">/* PA[6] pin */</span>
    2187. 

  2187. <a name="l02155"></a>02155 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PB                ((u16)0x0100)            </span><span class="comment">/* PB[6] pin */</span>
    2188. 

  2188. <a name="l02156"></a>02156 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PC                ((u16)0x0200)            </span><span class="comment">/* PC[6] pin */</span>
    2189. 

  2189. <a name="l02157"></a>02157 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PD                ((u16)0x0300)            </span><span class="comment">/* PD[6] pin */</span>
    2190. 

  2190. <a name="l02158"></a>02158 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PE                ((u16)0x0400)            </span><span class="comment">/* PE[6] pin */</span>
    2191. 

  2191. <a name="l02159"></a>02159 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PF                ((u16)0x0500)            </span><span class="comment">/* PF[6] pin */</span>
    2192. 

  2192. <a name="l02160"></a>02160 <span class="preprocessor">#define AFIO_EXTICR2_EXTI6_PG                ((u16)0x0600)            </span><span class="comment">/* PG[6] pin */</span>
    2193. 

  2193. <a name="l02161"></a>02161 
    2194. 

  2194. <a name="l02162"></a>02162 <span class="comment">/* EXTI7 configuration */</span>
    2195. 

  2195. <a name="l02163"></a>02163 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PA                ((u16)0x0000)            </span><span class="comment">/* PA[7] pin */</span>
    2196. 

  2196. <a name="l02164"></a>02164 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PB                ((u16)0x1000)            </span><span class="comment">/* PB[7] pin */</span>
    2197. 

  2197. <a name="l02165"></a>02165 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PC                ((u16)0x2000)            </span><span class="comment">/* PC[7] pin */</span>
    2198. 

  2198. <a name="l02166"></a>02166 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PD                ((u16)0x3000)            </span><span class="comment">/* PD[7] pin */</span>
    2199. 

  2199. <a name="l02167"></a>02167 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PE                ((u16)0x4000)            </span><span class="comment">/* PE[7] pin */</span>
    2200. 

  2200. <a name="l02168"></a>02168 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PF                ((u16)0x5000)            </span><span class="comment">/* PF[7] pin */</span>
    2201. 

  2201. <a name="l02169"></a>02169 <span class="preprocessor">#define AFIO_EXTICR2_EXTI7_PG                ((u16)0x6000)            </span><span class="comment">/* PG[7] pin */</span>
    2202. 

  2202. <a name="l02170"></a>02170 
    2203. 

  2203. <a name="l02171"></a>02171 
    2204. 

  2204. <a name="l02172"></a>02172 <span class="comment">/*****************  Bit definition for AFIO_EXTICR3 register  *****************/</span>
    2205. 

  2205. <a name="l02173"></a>02173 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8                   ((u16)0x000F)            </span><span class="comment">/* EXTI 8 configuration */</span>
    2206. 

  2206. <a name="l02174"></a>02174 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9                   ((u16)0x00F0)            </span><span class="comment">/* EXTI 9 configuration */</span>
    2207. 

  2207. <a name="l02175"></a>02175 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10                  ((u16)0x0F00)            </span><span class="comment">/* EXTI 10 configuration */</span>
    2208. 

  2208. <a name="l02176"></a>02176 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11                  ((u16)0xF000)            </span><span class="comment">/* EXTI 11 configuration */</span>
    2209. 

  2209. <a name="l02177"></a>02177 
    2210. 

  2210. <a name="l02178"></a>02178 <span class="comment">/* EXTI8 configuration */</span>
    2211. 

  2211. <a name="l02179"></a>02179 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PA                ((u16)0x0000)            </span><span class="comment">/* PA[8] pin */</span>
    2212. 

  2212. <a name="l02180"></a>02180 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PB                ((u16)0x0001)            </span><span class="comment">/* PB[8] pin */</span>
    2213. 

  2213. <a name="l02181"></a>02181 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PC                ((u16)0x0002)            </span><span class="comment">/* PC[8] pin */</span>
    2214. 

  2214. <a name="l02182"></a>02182 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PD                ((u16)0x0003)            </span><span class="comment">/* PD[8] pin */</span>
    2215. 

  2215. <a name="l02183"></a>02183 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PE                ((u16)0x0004)            </span><span class="comment">/* PE[8] pin */</span>
    2216. 

  2216. <a name="l02184"></a>02184 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PF                ((u16)0x0005)            </span><span class="comment">/* PF[8] pin */</span>
    2217. 

  2217. <a name="l02185"></a>02185 <span class="preprocessor">#define AFIO_EXTICR3_EXTI8_PG                ((u16)0x0006)            </span><span class="comment">/* PG[8] pin */</span>
    2218. 

  2218. <a name="l02186"></a>02186 
    2219. 

  2219. <a name="l02187"></a>02187 <span class="comment">/* EXTI9 configuration */</span>
    2220. 

  2220. <a name="l02188"></a>02188 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PA                ((u16)0x0000)            </span><span class="comment">/* PA[9] pin */</span>
    2221. 

  2221. <a name="l02189"></a>02189 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PB                ((u16)0x0010)            </span><span class="comment">/* PB[9] pin */</span>
    2222. 

  2222. <a name="l02190"></a>02190 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PC                ((u16)0x0020)            </span><span class="comment">/* PC[9] pin */</span>
    2223. 

  2223. <a name="l02191"></a>02191 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PD                ((u16)0x0030)            </span><span class="comment">/* PD[9] pin */</span>
    2224. 

  2224. <a name="l02192"></a>02192 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PE                ((u16)0x0040)            </span><span class="comment">/* PE[9] pin */</span>
    2225. 

  2225. <a name="l02193"></a>02193 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PF                ((u16)0x0050)            </span><span class="comment">/* PF[9] pin */</span>
    2226. 

  2226. <a name="l02194"></a>02194 <span class="preprocessor">#define AFIO_EXTICR3_EXTI9_PG                ((u16)0x0060)            </span><span class="comment">/* PG[9] pin */</span>
    2227. 

  2227. <a name="l02195"></a>02195 
    2228. 

  2228. <a name="l02196"></a>02196 <span class="comment">/* EXTI10 configuration */</span>  
    2229. 

  2229. <a name="l02197"></a>02197 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PA               ((u16)0x0000)            </span><span class="comment">/* PA[10] pin */</span>
    2230. 

  2230. <a name="l02198"></a>02198 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PB               ((u16)0x0100)            </span><span class="comment">/* PB[10] pin */</span>
    2231. 

  2231. <a name="l02199"></a>02199 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PC               ((u16)0x0200)            </span><span class="comment">/* PC[10] pin */</span>
    2232. 

  2232. <a name="l02200"></a>02200 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PD               ((u16)0x0300)            </span><span class="comment">/* PD[10] pin */</span>
    2233. 

  2233. <a name="l02201"></a>02201 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PE               ((u16)0x0400)            </span><span class="comment">/* PE[10] pin */</span>
    2234. 

  2234. <a name="l02202"></a>02202 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PF               ((u16)0x0500)            </span><span class="comment">/* PF[10] pin */</span>
    2235. 

  2235. <a name="l02203"></a>02203 <span class="preprocessor">#define AFIO_EXTICR3_EXTI10_PG               ((u16)0x0600)            </span><span class="comment">/* PG[10] pin */</span>
    2236. 

  2236. <a name="l02204"></a>02204 
    2237. 

  2237. <a name="l02205"></a>02205 <span class="comment">/* EXTI11 configuration */</span>
    2238. 

  2238. <a name="l02206"></a>02206 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PA               ((u16)0x0000)            </span><span class="comment">/* PA[11] pin */</span>
    2239. 

  2239. <a name="l02207"></a>02207 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PB               ((u16)0x1000)            </span><span class="comment">/* PB[11] pin */</span>
    2240. 

  2240. <a name="l02208"></a>02208 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PC               ((u16)0x2000)            </span><span class="comment">/* PC[11] pin */</span>
    2241. 

  2241. <a name="l02209"></a>02209 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PD               ((u16)0x3000)            </span><span class="comment">/* PD[11] pin */</span>
    2242. 

  2242. <a name="l02210"></a>02210 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PE               ((u16)0x4000)            </span><span class="comment">/* PE[11] pin */</span>
    2243. 

  2243. <a name="l02211"></a>02211 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PF               ((u16)0x5000)            </span><span class="comment">/* PF[11] pin */</span>
    2244. 

  2244. <a name="l02212"></a>02212 <span class="preprocessor">#define AFIO_EXTICR3_EXTI11_PG               ((u16)0x6000)            </span><span class="comment">/* PG[11] pin */</span>
    2245. 

  2245. <a name="l02213"></a>02213 
    2246. 

  2246. <a name="l02214"></a>02214 
    2247. 

  2247. <a name="l02215"></a>02215 <span class="comment">/*****************  Bit definition for AFIO_EXTICR4 register  *****************/</span>
    2248. 

  2248. <a name="l02216"></a>02216 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12                  ((u16)0x000F)            </span><span class="comment">/* EXTI 12 configuration */</span>
    2249. 

  2249. <a name="l02217"></a>02217 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13                  ((u16)0x00F0)            </span><span class="comment">/* EXTI 13 configuration */</span>
    2250. 

  2250. <a name="l02218"></a>02218 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14                  ((u16)0x0F00)            </span><span class="comment">/* EXTI 14 configuration */</span>
    2251. 

  2251. <a name="l02219"></a>02219 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15                  ((u16)0xF000)            </span><span class="comment">/* EXTI 15 configuration */</span>
    2252. 

  2252. <a name="l02220"></a>02220 
    2253. 

  2253. <a name="l02221"></a>02221 <span class="comment">/* EXTI12 configuration */</span>
    2254. 

  2254. <a name="l02222"></a>02222 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PA               ((u16)0x0000)            </span><span class="comment">/* PA[12] pin */</span>
    2255. 

  2255. <a name="l02223"></a>02223 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PB               ((u16)0x0001)            </span><span class="comment">/* PB[12] pin */</span>
    2256. 

  2256. <a name="l02224"></a>02224 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PC               ((u16)0x0002)            </span><span class="comment">/* PC[12] pin */</span>
    2257. 

  2257. <a name="l02225"></a>02225 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PD               ((u16)0x0003)            </span><span class="comment">/* PD[12] pin */</span>
    2258. 

  2258. <a name="l02226"></a>02226 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PE               ((u16)0x0004)            </span><span class="comment">/* PE[12] pin */</span>
    2259. 

  2259. <a name="l02227"></a>02227 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PF               ((u16)0x0005)            </span><span class="comment">/* PF[12] pin */</span>
    2260. 

  2260. <a name="l02228"></a>02228 <span class="preprocessor">#define AFIO_EXTICR4_EXTI12_PG               ((u16)0x0006)            </span><span class="comment">/* PG[12] pin */</span>
    2261. 

  2261. <a name="l02229"></a>02229 
    2262. 

  2262. <a name="l02230"></a>02230 <span class="comment">/* EXTI13 configuration */</span>
    2263. 

  2263. <a name="l02231"></a>02231 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PA               ((u16)0x0000)            </span><span class="comment">/* PA[13] pin */</span>
    2264. 

  2264. <a name="l02232"></a>02232 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PB               ((u16)0x0010)            </span><span class="comment">/* PB[13] pin */</span>
    2265. 

  2265. <a name="l02233"></a>02233 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PC               ((u16)0x0020)            </span><span class="comment">/* PC[13] pin */</span>
    2266. 

  2266. <a name="l02234"></a>02234 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PD               ((u16)0x0030)            </span><span class="comment">/* PD[13] pin */</span>
    2267. 

  2267. <a name="l02235"></a>02235 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PE               ((u16)0x0040)            </span><span class="comment">/* PE[13] pin */</span>
    2268. 

  2268. <a name="l02236"></a>02236 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PF               ((u16)0x0050)            </span><span class="comment">/* PF[13] pin */</span>
    2269. 

  2269. <a name="l02237"></a>02237 <span class="preprocessor">#define AFIO_EXTICR4_EXTI13_PG               ((u16)0x0060)            </span><span class="comment">/* PG[13] pin */</span>
    2270. 

  2270. <a name="l02238"></a>02238 
    2271. 

  2271. <a name="l02239"></a>02239 <span class="comment">/* EXTI14 configuration */</span>  
    2272. 

  2272. <a name="l02240"></a>02240 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PA               ((u16)0x0000)            </span><span class="comment">/* PA[14] pin */</span>
    2273. 

  2273. <a name="l02241"></a>02241 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PB               ((u16)0x0100)            </span><span class="comment">/* PB[14] pin */</span>
    2274. 

  2274. <a name="l02242"></a>02242 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PC               ((u16)0x0200)            </span><span class="comment">/* PC[14] pin */</span>
    2275. 

  2275. <a name="l02243"></a>02243 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PD               ((u16)0x0300)            </span><span class="comment">/* PD[14] pin */</span>
    2276. 

  2276. <a name="l02244"></a>02244 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PE               ((u16)0x0400)            </span><span class="comment">/* PE[14] pin */</span>
    2277. 

  2277. <a name="l02245"></a>02245 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PF               ((u16)0x0500)            </span><span class="comment">/* PF[14] pin */</span>
    2278. 

  2278. <a name="l02246"></a>02246 <span class="preprocessor">#define AFIO_EXTICR4_EXTI14_PG               ((u16)0x0600)            </span><span class="comment">/* PG[14] pin */</span>
    2279. 

  2279. <a name="l02247"></a>02247 
    2280. 

  2280. <a name="l02248"></a>02248 <span class="comment">/* EXTI15 configuration */</span>
    2281. 

  2281. <a name="l02249"></a>02249 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PA               ((u16)0x0000)            </span><span class="comment">/* PA[15] pin */</span>
    2282. 

  2282. <a name="l02250"></a>02250 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PB               ((u16)0x1000)            </span><span class="comment">/* PB[15] pin */</span>
    2283. 

  2283. <a name="l02251"></a>02251 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PC               ((u16)0x2000)            </span><span class="comment">/* PC[15] pin */</span>
    2284. 

  2284. <a name="l02252"></a>02252 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PD               ((u16)0x3000)            </span><span class="comment">/* PD[15] pin */</span>
    2285. 

  2285. <a name="l02253"></a>02253 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PE               ((u16)0x4000)            </span><span class="comment">/* PE[15] pin */</span>
    2286. 

  2286. <a name="l02254"></a>02254 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PF               ((u16)0x5000)            </span><span class="comment">/* PF[15] pin */</span>
    2287. 

  2287. <a name="l02255"></a>02255 <span class="preprocessor">#define AFIO_EXTICR4_EXTI15_PG               ((u16)0x6000)            </span><span class="comment">/* PG[15] pin */</span>
    2288. 

  2288. <a name="l02256"></a>02256 
    2289. 

  2289. <a name="l02257"></a>02257 
    2290. 

  2290. <a name="l02258"></a>02258 
    2291. 

  2291. <a name="l02259"></a>02259 <span class="comment">/******************************************************************************/</span>
    2292. 

  2292. <a name="l02260"></a>02260 <span class="comment">/*                                                                            */</span>
    2293. 

  2293. <a name="l02261"></a>02261 <span class="comment">/*                               SystemTick                                   */</span>
    2294. 

  2294. <a name="l02262"></a>02262 <span class="comment">/*                                                                            */</span>
    2295. 

  2295. <a name="l02263"></a>02263 <span class="comment">/******************************************************************************/</span>
    2296. 

  2296. <a name="l02264"></a>02264 
    2297. 

  2297. <a name="l02265"></a>02265 <span class="comment">/*****************  Bit definition for SysTick_CTRL register  *****************/</span>
    2298. 

  2298. <a name="l02266"></a>02266 <span class="preprocessor">#define  SysTick_CTRL_ENABLE                 ((u32)0x00000001)        </span><span class="comment">/* Counter enable */</span>
    2299. 

  2299. <a name="l02267"></a>02267 <span class="preprocessor">#define  SysTick_CTRL_TICKINT                ((u32)0x00000002)        </span><span class="comment">/* Counting down to 0 pends the SysTick handler */</span>
    2300. 

  2300. <a name="l02268"></a>02268 <span class="preprocessor">#define  SysTick_CTRL_CLKSOURCE              ((u32)0x00000004)        </span><span class="comment">/* Clock source */</span>
    2301. 

  2301. <a name="l02269"></a>02269 <span class="preprocessor">#define  SysTick_CTRL_COUNTFLAG              ((u32)0x00010000)        </span><span class="comment">/* Count Flag */</span>
    2302. 

  2302. <a name="l02270"></a>02270 
    2303. 

  2303. <a name="l02271"></a>02271 
    2304. 

  2304. <a name="l02272"></a>02272 <span class="comment">/*****************  Bit definition for SysTick_LOAD register  *****************/</span>
    2305. 

  2305. <a name="l02273"></a>02273 <span class="preprocessor">#define  SysTick_LOAD_RELOAD                 ((u32)0x00FFFFFF)        </span><span class="comment">/* Value to load into the SysTick Current Value Register when the counter reaches 0 */</span>
    2306. 

  2306. <a name="l02274"></a>02274 
    2307. 

  2307. <a name="l02275"></a>02275 
    2308. 

  2308. <a name="l02276"></a>02276 <span class="comment">/*****************  Bit definition for SysTick_VAL register  ******************/</span>
    2309. 

  2309. <a name="l02277"></a>02277 <span class="preprocessor">#define  SysTick_VAL_CURRENT                 ((u32)0x00FFFFFF)        </span><span class="comment">/* Current value at the time the register is accessed */</span>
    2310. 

  2310. <a name="l02278"></a>02278 
    2311. 

  2311. <a name="l02279"></a>02279 
    2312. 

  2312. <a name="l02280"></a>02280 <span class="comment">/*****************  Bit definition for SysTick_CALIB register  ****************/</span>
    2313. 

  2313. <a name="l02281"></a>02281 <span class="preprocessor">#define  SysTick_CALIB_TENMS                 ((u32)0x00FFFFFF)        </span><span class="comment">/* Reload value to use for 10ms timing */</span>
    2314. 

  2314. <a name="l02282"></a>02282 <span class="preprocessor">#define  SysTick_CALIB_SKEW                  ((u32)0x40000000)        </span><span class="comment">/* Calibration value is not exactly 10 ms */</span>
    2315. 

  2315. <a name="l02283"></a>02283 <span class="preprocessor">#define  SysTick_CALIB_NOREF                 ((u32)0x80000000)        </span><span class="comment">/* The reference clock is not provided */</span>
    2316. 

  2316. <a name="l02284"></a>02284 
    2317. 

  2317. <a name="l02285"></a>02285 
    2318. 

  2318. <a name="l02286"></a>02286 
    2319. 

  2319. <a name="l02287"></a>02287 <span class="comment">/******************************************************************************/</span>
    2320. 

  2320. <a name="l02288"></a>02288 <span class="comment">/*                                                                            */</span>
    2321. 

  2321. <a name="l02289"></a>02289 <span class="comment">/*                  Nested Vectored Interrupt Controller                      */</span>
    2322. 

  2322. <a name="l02290"></a>02290 <span class="comment">/*                                                                            */</span>
    2323. 

  2323. <a name="l02291"></a>02291 <span class="comment">/******************************************************************************/</span>
    2324. 

  2324. <a name="l02292"></a>02292 
    2325. 

  2325. <a name="l02293"></a>02293 <span class="comment">/******************  Bit definition for NVIC_ISER register  *******************/</span>
    2326. 

  2326. <a name="l02294"></a>02294 <span class="preprocessor">#define  NVIC_ISER_SETENA                    ((u32)0xFFFFFFFF)        </span><span class="comment">/* Interrupt set enable bits */</span>
    2327. 

  2327. <a name="l02295"></a>02295 <span class="preprocessor">#define  NVIC_ISER_SETENA_0                  ((u32)0x00000001)        </span><span class="comment">/* bit 0 */</span>
    2328. 

  2328. <a name="l02296"></a>02296 <span class="preprocessor">#define  NVIC_ISER_SETENA_1                  ((u32)0x00000002)        </span><span class="comment">/* bit 1 */</span>
    2329. 

  2329. <a name="l02297"></a>02297 <span class="preprocessor">#define  NVIC_ISER_SETENA_2                  ((u32)0x00000004)        </span><span class="comment">/* bit 2 */</span>
    2330. 

  2330. <a name="l02298"></a>02298 <span class="preprocessor">#define  NVIC_ISER_SETENA_3                  ((u32)0x00000008)        </span><span class="comment">/* bit 3 */</span>
    2331. 

  2331. <a name="l02299"></a>02299 <span class="preprocessor">#define  NVIC_ISER_SETENA_4                  ((u32)0x00000010)        </span><span class="comment">/* bit 4 */</span>
    2332. 

  2332. <a name="l02300"></a>02300 <span class="preprocessor">#define  NVIC_ISER_SETENA_5                  ((u32)0x00000020)        </span><span class="comment">/* bit 5 */</span>
    2333. 

  2333. <a name="l02301"></a>02301 <span class="preprocessor">#define  NVIC_ISER_SETENA_6                  ((u32)0x00000040)        </span><span class="comment">/* bit 6 */</span>
    2334. 

  2334. <a name="l02302"></a>02302 <span class="preprocessor">#define  NVIC_ISER_SETENA_7                  ((u32)0x00000080)        </span><span class="comment">/* bit 7 */</span>
    2335. 

  2335. <a name="l02303"></a>02303 <span class="preprocessor">#define  NVIC_ISER_SETENA_8                  ((u32)0x00000100)        </span><span class="comment">/* bit 8 */</span>
    2336. 

  2336. <a name="l02304"></a>02304 <span class="preprocessor">#define  NVIC_ISER_SETENA_9                  ((u32)0x00000200)        </span><span class="comment">/* bit 9 */</span>
    2337. 

  2337. <a name="l02305"></a>02305 <span class="preprocessor">#define  NVIC_ISER_SETENA_10                 ((u32)0x00000400)        </span><span class="comment">/* bit 10 */</span>
    2338. 

  2338. <a name="l02306"></a>02306 <span class="preprocessor">#define  NVIC_ISER_SETENA_11                 ((u32)0x00000800)        </span><span class="comment">/* bit 11 */</span>
    2339. 

  2339. <a name="l02307"></a>02307 <span class="preprocessor">#define  NVIC_ISER_SETENA_12                 ((u32)0x00001000)        </span><span class="comment">/* bit 12 */</span>
    2340. 

  2340. <a name="l02308"></a>02308 <span class="preprocessor">#define  NVIC_ISER_SETENA_13                 ((u32)0x00002000)        </span><span class="comment">/* bit 13 */</span>
    2341. 

  2341. <a name="l02309"></a>02309 <span class="preprocessor">#define  NVIC_ISER_SETENA_14                 ((u32)0x00004000)        </span><span class="comment">/* bit 14 */</span>
    2342. 

  2342. <a name="l02310"></a>02310 <span class="preprocessor">#define  NVIC_ISER_SETENA_15                 ((u32)0x00008000)        </span><span class="comment">/* bit 15 */</span>
    2343. 

  2343. <a name="l02311"></a>02311 <span class="preprocessor">#define  NVIC_ISER_SETENA_16                 ((u32)0x00010000)        </span><span class="comment">/* bit 16 */</span>
    2344. 

  2344. <a name="l02312"></a>02312 <span class="preprocessor">#define  NVIC_ISER_SETENA_17                 ((u32)0x00020000)        </span><span class="comment">/* bit 17 */</span>
    2345. 

  2345. <a name="l02313"></a>02313 <span class="preprocessor">#define  NVIC_ISER_SETENA_18                 ((u32)0x00040000)        </span><span class="comment">/* bit 18 */</span>
    2346. 

  2346. <a name="l02314"></a>02314 <span class="preprocessor">#define  NVIC_ISER_SETENA_19                 ((u32)0x00080000)        </span><span class="comment">/* bit 19 */</span>
    2347. 

  2347. <a name="l02315"></a>02315 <span class="preprocessor">#define  NVIC_ISER_SETENA_20                 ((u32)0x00100000)        </span><span class="comment">/* bit 20 */</span>
    2348. 

  2348. <a name="l02316"></a>02316 <span class="preprocessor">#define  NVIC_ISER_SETENA_21                 ((u32)0x00200000)        </span><span class="comment">/* bit 21 */</span>
    2349. 

  2349. <a name="l02317"></a>02317 <span class="preprocessor">#define  NVIC_ISER_SETENA_22                 ((u32)0x00400000)        </span><span class="comment">/* bit 22 */</span>
    2350. 

  2350. <a name="l02318"></a>02318 <span class="preprocessor">#define  NVIC_ISER_SETENA_23                 ((u32)0x00800000)        </span><span class="comment">/* bit 23 */</span>
    2351. 

  2351. <a name="l02319"></a>02319 <span class="preprocessor">#define  NVIC_ISER_SETENA_24                 ((u32)0x01000000)        </span><span class="comment">/* bit 24 */</span>
    2352. 

  2352. <a name="l02320"></a>02320 <span class="preprocessor">#define  NVIC_ISER_SETENA_25                 ((u32)0x02000000)        </span><span class="comment">/* bit 25 */</span>
    2353. 

  2353. <a name="l02321"></a>02321 <span class="preprocessor">#define  NVIC_ISER_SETENA_26                 ((u32)0x04000000)        </span><span class="comment">/* bit 26 */</span>
    2354. 

  2354. <a name="l02322"></a>02322 <span class="preprocessor">#define  NVIC_ISER_SETENA_27                 ((u32)0x08000000)        </span><span class="comment">/* bit 27 */</span>
    2355. 

  2355. <a name="l02323"></a>02323 <span class="preprocessor">#define  NVIC_ISER_SETENA_28                 ((u32)0x10000000)        </span><span class="comment">/* bit 28 */</span>
    2356. 

  2356. <a name="l02324"></a>02324 <span class="preprocessor">#define  NVIC_ISER_SETENA_29                 ((u32)0x20000000)        </span><span class="comment">/* bit 29 */</span>
    2357. 

  2357. <a name="l02325"></a>02325 <span class="preprocessor">#define  NVIC_ISER_SETENA_30                 ((u32)0x40000000)        </span><span class="comment">/* bit 30 */</span>
    2358. 

  2358. <a name="l02326"></a>02326 <span class="preprocessor">#define  NVIC_ISER_SETENA_31                 ((u32)0x80000000)        </span><span class="comment">/* bit 31 */</span>
    2359. 

  2359. <a name="l02327"></a>02327 
    2360. 

  2360. <a name="l02328"></a>02328 
    2361. 

  2361. <a name="l02329"></a>02329 
    2362. 

  2362. <a name="l02330"></a>02330 <span class="comment">/******************  Bit definition for NVIC_ICER register  *******************/</span>
    2363. 

  2363. <a name="l02331"></a>02331 <span class="preprocessor">#define  NVIC_ICER_CLRENA                   ((u32)0xFFFFFFFF)        </span><span class="comment">/* Interrupt clear-enable bits */</span>
    2364. 

  2364. <a name="l02332"></a>02332 <span class="preprocessor">#define  NVIC_ICER_CLRENA_0                  ((u32)0x00000001)        </span><span class="comment">/* bit 0 */</span>
    2365. 

  2365. <a name="l02333"></a>02333 <span class="preprocessor">#define  NVIC_ICER_CLRENA_1                  ((u32)0x00000002)        </span><span class="comment">/* bit 1 */</span>
    2366. 

  2366. <a name="l02334"></a>02334 <span class="preprocessor">#define  NVIC_ICER_CLRENA_2                  ((u32)0x00000004)        </span><span class="comment">/* bit 2 */</span>
    2367. 

  2367. <a name="l02335"></a>02335 <span class="preprocessor">#define  NVIC_ICER_CLRENA_3                  ((u32)0x00000008)        </span><span class="comment">/* bit 3 */</span>
    2368. 

  2368. <a name="l02336"></a>02336 <span class="preprocessor">#define  NVIC_ICER_CLRENA_4                  ((u32)0x00000010)        </span><span class="comment">/* bit 4 */</span>
    2369. 

  2369. <a name="l02337"></a>02337 <span class="preprocessor">#define  NVIC_ICER_CLRENA_5                  ((u32)0x00000020)        </span><span class="comment">/* bit 5 */</span>
    2370. 

  2370. <a name="l02338"></a>02338 <span class="preprocessor">#define  NVIC_ICER_CLRENA_6                  ((u32)0x00000040)        </span><span class="comment">/* bit 6 */</span>
    2371. 

  2371. <a name="l02339"></a>02339 <span class="preprocessor">#define  NVIC_ICER_CLRENA_7                  ((u32)0x00000080)        </span><span class="comment">/* bit 7 */</span>
    2372. 

  2372. <a name="l02340"></a>02340 <span class="preprocessor">#define  NVIC_ICER_CLRENA_8                  ((u32)0x00000100)        </span><span class="comment">/* bit 8 */</span>
    2373. 

  2373. <a name="l02341"></a>02341 <span class="preprocessor">#define  NVIC_ICER_CLRENA_9                  ((u32)0x00000200)        </span><span class="comment">/* bit 9 */</span>
    2374. 

  2374. <a name="l02342"></a>02342 <span class="preprocessor">#define  NVIC_ICER_CLRENA_10                 ((u32)0x00000400)        </span><span class="comment">/* bit 10 */</span>
    2375. 

  2375. <a name="l02343"></a>02343 <span class="preprocessor">#define  NVIC_ICER_CLRENA_11                 ((u32)0x00000800)        </span><span class="comment">/* bit 11 */</span>
    2376. 

  2376. <a name="l02344"></a>02344 <span class="preprocessor">#define  NVIC_ICER_CLRENA_12                 ((u32)0x00001000)        </span><span class="comment">/* bit 12 */</span>
    2377. 

  2377. <a name="l02345"></a>02345 <span class="preprocessor">#define  NVIC_ICER_CLRENA_13                 ((u32)0x00002000)        </span><span class="comment">/* bit 13 */</span>
    2378. 

  2378. <a name="l02346"></a>02346 <span class="preprocessor">#define  NVIC_ICER_CLRENA_14                 ((u32)0x00004000)        </span><span class="comment">/* bit 14 */</span>
    2379. 

  2379. <a name="l02347"></a>02347 <span class="preprocessor">#define  NVIC_ICER_CLRENA_15                 ((u32)0x00008000)        </span><span class="comment">/* bit 15 */</span>
    2380. 

  2380. <a name="l02348"></a>02348 <span class="preprocessor">#define  NVIC_ICER_CLRENA_16                 ((u32)0x00010000)        </span><span class="comment">/* bit 16 */</span>
    2381. 

  2381. <a name="l02349"></a>02349 <span class="preprocessor">#define  NVIC_ICER_CLRENA_17                 ((u32)0x00020000)        </span><span class="comment">/* bit 17 */</span>
    2382. 

  2382. <a name="l02350"></a>02350 <span class="preprocessor">#define  NVIC_ICER_CLRENA_18                 ((u32)0x00040000)        </span><span class="comment">/* bit 18 */</span>
    2383. 

  2383. <a name="l02351"></a>02351 <span class="preprocessor">#define  NVIC_ICER_CLRENA_19                 ((u32)0x00080000)        </span><span class="comment">/* bit 19 */</span>
    2384. 

  2384. <a name="l02352"></a>02352 <span class="preprocessor">#define  NVIC_ICER_CLRENA_20                 ((u32)0x00100000)        </span><span class="comment">/* bit 20 */</span>
    2385. 

  2385. <a name="l02353"></a>02353 <span class="preprocessor">#define  NVIC_ICER_CLRENA_21                 ((u32)0x00200000)        </span><span class="comment">/* bit 21 */</span>
    2386. 

  2386. <a name="l02354"></a>02354 <span class="preprocessor">#define  NVIC_ICER_CLRENA_22                 ((u32)0x00400000)        </span><span class="comment">/* bit 22 */</span>
    2387. 

  2387. <a name="l02355"></a>02355 <span class="preprocessor">#define  NVIC_ICER_CLRENA_23                 ((u32)0x00800000)        </span><span class="comment">/* bit 23 */</span>
    2388. 

  2388. <a name="l02356"></a>02356 <span class="preprocessor">#define  NVIC_ICER_CLRENA_24                 ((u32)0x01000000)        </span><span class="comment">/* bit 24 */</span>
    2389. 

  2389. <a name="l02357"></a>02357 <span class="preprocessor">#define  NVIC_ICER_CLRENA_25                 ((u32)0x02000000)        </span><span class="comment">/* bit 25 */</span>
    2390. 

  2390. <a name="l02358"></a>02358 <span class="preprocessor">#define  NVIC_ICER_CLRENA_26                 ((u32)0x04000000)        </span><span class="comment">/* bit 26 */</span>
    2391. 

  2391. <a name="l02359"></a>02359 <span class="preprocessor">#define  NVIC_ICER_CLRENA_27                 ((u32)0x08000000)        </span><span class="comment">/* bit 27 */</span>
    2392. 

  2392. <a name="l02360"></a>02360 <span class="preprocessor">#define  NVIC_ICER_CLRENA_28                 ((u32)0x10000000)        </span><span class="comment">/* bit 28 */</span>
    2393. 

  2393. <a name="l02361"></a>02361 <span class="preprocessor">#define  NVIC_ICER_CLRENA_29                 ((u32)0x20000000)        </span><span class="comment">/* bit 29 */</span>
    2394. 

  2394. <a name="l02362"></a>02362 <span class="preprocessor">#define  NVIC_ICER_CLRENA_30                 ((u32)0x40000000)        </span><span class="comment">/* bit 30 */</span>
    2395. 

  2395. <a name="l02363"></a>02363 <span class="preprocessor">#define  NVIC_ICER_CLRENA_31                 ((u32)0x80000000)        </span><span class="comment">/* bit 31 */</span>
    2396. 

  2396. <a name="l02364"></a>02364 
    2397. 

  2397. <a name="l02365"></a>02365 
    2398. 

  2398. <a name="l02366"></a>02366 <span class="comment">/******************  Bit definition for NVIC_ISPR register  *******************/</span>
    2399. 

  2399. <a name="l02367"></a>02367 <span class="preprocessor">#define  NVIC_ISPR_SETPEND                   ((u32)0xFFFFFFFF)        </span><span class="comment">/* Interrupt set-pending bits */</span>
    2400. 

  2400. <a name="l02368"></a>02368 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_0                 ((u32)0x00000001)        </span><span class="comment">/* bit 0 */</span>
    2401. 

  2401. <a name="l02369"></a>02369 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_1                 ((u32)0x00000002)        </span><span class="comment">/* bit 1 */</span>
    2402. 

  2402. <a name="l02370"></a>02370 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_2                 ((u32)0x00000004)        </span><span class="comment">/* bit 2 */</span>
    2403. 

  2403. <a name="l02371"></a>02371 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_3                 ((u32)0x00000008)        </span><span class="comment">/* bit 3 */</span>
    2404. 

  2404. <a name="l02372"></a>02372 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_4                 ((u32)0x00000010)        </span><span class="comment">/* bit 4 */</span>
    2405. 

  2405. <a name="l02373"></a>02373 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_5                 ((u32)0x00000020)        </span><span class="comment">/* bit 5 */</span>
    2406. 

  2406. <a name="l02374"></a>02374 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_6                 ((u32)0x00000040)        </span><span class="comment">/* bit 6 */</span>
    2407. 

  2407. <a name="l02375"></a>02375 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_7                 ((u32)0x00000080)        </span><span class="comment">/* bit 7 */</span>
    2408. 

  2408. <a name="l02376"></a>02376 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_8                 ((u32)0x00000100)        </span><span class="comment">/* bit 8 */</span>
    2409. 

  2409. <a name="l02377"></a>02377 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_9                 ((u32)0x00000200)        </span><span class="comment">/* bit 9 */</span>
    2410. 

  2410. <a name="l02378"></a>02378 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_10                ((u32)0x00000400)        </span><span class="comment">/* bit 10 */</span>
    2411. 

  2411. <a name="l02379"></a>02379 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_11                ((u32)0x00000800)        </span><span class="comment">/* bit 11 */</span>
    2412. 

  2412. <a name="l02380"></a>02380 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_12                ((u32)0x00001000)        </span><span class="comment">/* bit 12 */</span>
    2413. 

  2413. <a name="l02381"></a>02381 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_13                ((u32)0x00002000)        </span><span class="comment">/* bit 13 */</span>
    2414. 

  2414. <a name="l02382"></a>02382 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_14                ((u32)0x00004000)        </span><span class="comment">/* bit 14 */</span>
    2415. 

  2415. <a name="l02383"></a>02383 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_15                ((u32)0x00008000)        </span><span class="comment">/* bit 15 */</span>
    2416. 

  2416. <a name="l02384"></a>02384 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_16                ((u32)0x00010000)        </span><span class="comment">/* bit 16 */</span>
    2417. 

  2417. <a name="l02385"></a>02385 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_17                ((u32)0x00020000)        </span><span class="comment">/* bit 17 */</span>
    2418. 

  2418. <a name="l02386"></a>02386 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_18                ((u32)0x00040000)        </span><span class="comment">/* bit 18 */</span>
    2419. 

  2419. <a name="l02387"></a>02387 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_19                ((u32)0x00080000)        </span><span class="comment">/* bit 19 */</span>
    2420. 

  2420. <a name="l02388"></a>02388 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_20                ((u32)0x00100000)        </span><span class="comment">/* bit 20 */</span>
    2421. 

  2421. <a name="l02389"></a>02389 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_21                ((u32)0x00200000)        </span><span class="comment">/* bit 21 */</span>
    2422. 

  2422. <a name="l02390"></a>02390 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_22                ((u32)0x00400000)        </span><span class="comment">/* bit 22 */</span>
    2423. 

  2423. <a name="l02391"></a>02391 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_23                ((u32)0x00800000)        </span><span class="comment">/* bit 23 */</span>
    2424. 

  2424. <a name="l02392"></a>02392 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_24                ((u32)0x01000000)        </span><span class="comment">/* bit 24 */</span>
    2425. 

  2425. <a name="l02393"></a>02393 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_25                ((u32)0x02000000)        </span><span class="comment">/* bit 25 */</span>
    2426. 

  2426. <a name="l02394"></a>02394 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_26                ((u32)0x04000000)        </span><span class="comment">/* bit 26 */</span>
    2427. 

  2427. <a name="l02395"></a>02395 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_27                ((u32)0x08000000)        </span><span class="comment">/* bit 27 */</span>
    2428. 

  2428. <a name="l02396"></a>02396 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_28                ((u32)0x10000000)        </span><span class="comment">/* bit 28 */</span>
    2429. 

  2429. <a name="l02397"></a>02397 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_29                ((u32)0x20000000)        </span><span class="comment">/* bit 29 */</span>
    2430. 

  2430. <a name="l02398"></a>02398 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_30                ((u32)0x40000000)        </span><span class="comment">/* bit 30 */</span>
    2431. 

  2431. <a name="l02399"></a>02399 <span class="preprocessor">#define  NVIC_ISPR_SETPEND_31                ((u32)0x80000000)        </span><span class="comment">/* bit 31 */</span>
    2432. 

  2432. <a name="l02400"></a>02400 
    2433. 

  2433. <a name="l02401"></a>02401 
    2434. 

  2434. <a name="l02402"></a>02402 <span class="comment">/******************  Bit definition for NVIC_ICPR register  *******************/</span>
    2435. 

  2435. <a name="l02403"></a>02403 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND                   ((u32)0xFFFFFFFF)        </span><span class="comment">/* Interrupt clear-pending bits */</span>
    2436. 

  2436. <a name="l02404"></a>02404 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_0                 ((u32)0x00000001)        </span><span class="comment">/* bit 0 */</span>
    2437. 

  2437. <a name="l02405"></a>02405 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_1                 ((u32)0x00000002)        </span><span class="comment">/* bit 1 */</span>
    2438. 

  2438. <a name="l02406"></a>02406 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_2                 ((u32)0x00000004)        </span><span class="comment">/* bit 2 */</span>
    2439. 

  2439. <a name="l02407"></a>02407 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_3                 ((u32)0x00000008)        </span><span class="comment">/* bit 3 */</span>
    2440. 

  2440. <a name="l02408"></a>02408 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_4                 ((u32)0x00000010)        </span><span class="comment">/* bit 4 */</span>
    2441. 

  2441. <a name="l02409"></a>02409 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_5                 ((u32)0x00000020)        </span><span class="comment">/* bit 5 */</span>
    2442. 

  2442. <a name="l02410"></a>02410 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_6                 ((u32)0x00000040)        </span><span class="comment">/* bit 6 */</span>
    2443. 

  2443. <a name="l02411"></a>02411 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_7                 ((u32)0x00000080)        </span><span class="comment">/* bit 7 */</span>
    2444. 

  2444. <a name="l02412"></a>02412 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_8                 ((u32)0x00000100)        </span><span class="comment">/* bit 8 */</span>
    2445. 

  2445. <a name="l02413"></a>02413 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_9                 ((u32)0x00000200)        </span><span class="comment">/* bit 9 */</span>
    2446. 

  2446. <a name="l02414"></a>02414 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_10                ((u32)0x00000400)        </span><span class="comment">/* bit 10 */</span>
    2447. 

  2447. <a name="l02415"></a>02415 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_11                ((u32)0x00000800)        </span><span class="comment">/* bit 11 */</span>
    2448. 

  2448. <a name="l02416"></a>02416 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_12                ((u32)0x00001000)        </span><span class="comment">/* bit 12 */</span>
    2449. 

  2449. <a name="l02417"></a>02417 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_13                ((u32)0x00002000)        </span><span class="comment">/* bit 13 */</span>
    2450. 

  2450. <a name="l02418"></a>02418 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_14                ((u32)0x00004000)        </span><span class="comment">/* bit 14 */</span>
    2451. 

  2451. <a name="l02419"></a>02419 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_15                ((u32)0x00008000)        </span><span class="comment">/* bit 15 */</span>
    2452. 

  2452. <a name="l02420"></a>02420 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_16                ((u32)0x00010000)        </span><span class="comment">/* bit 16 */</span>
    2453. 

  2453. <a name="l02421"></a>02421 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_17                ((u32)0x00020000)        </span><span class="comment">/* bit 17 */</span>
    2454. 

  2454. <a name="l02422"></a>02422 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_18                ((u32)0x00040000)        </span><span class="comment">/* bit 18 */</span>
    2455. 

  2455. <a name="l02423"></a>02423 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_19                ((u32)0x00080000)        </span><span class="comment">/* bit 19 */</span>
    2456. 

  2456. <a name="l02424"></a>02424 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_20                ((u32)0x00100000)        </span><span class="comment">/* bit 20 */</span>
    2457. 

  2457. <a name="l02425"></a>02425 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_21                ((u32)0x00200000)        </span><span class="comment">/* bit 21 */</span>
    2458. 

  2458. <a name="l02426"></a>02426 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_22                ((u32)0x00400000)        </span><span class="comment">/* bit 22 */</span>
    2459. 

  2459. <a name="l02427"></a>02427 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_23                ((u32)0x00800000)        </span><span class="comment">/* bit 23 */</span>
    2460. 

  2460. <a name="l02428"></a>02428 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_24                ((u32)0x01000000)        </span><span class="comment">/* bit 24 */</span>
    2461. 

  2461. <a name="l02429"></a>02429 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_25                ((u32)0x02000000)        </span><span class="comment">/* bit 25 */</span>
    2462. 

  2462. <a name="l02430"></a>02430 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_26                ((u32)0x04000000)        </span><span class="comment">/* bit 26 */</span>
    2463. 

  2463. <a name="l02431"></a>02431 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_27                ((u32)0x08000000)        </span><span class="comment">/* bit 27 */</span>
    2464. 

  2464. <a name="l02432"></a>02432 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_28                ((u32)0x10000000)        </span><span class="comment">/* bit 28 */</span>
    2465. 

  2465. <a name="l02433"></a>02433 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_29                ((u32)0x20000000)        </span><span class="comment">/* bit 29 */</span>
    2466. 

  2466. <a name="l02434"></a>02434 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_30                ((u32)0x40000000)        </span><span class="comment">/* bit 30 */</span>
    2467. 

  2467. <a name="l02435"></a>02435 <span class="preprocessor">#define  NVIC_ICPR_CLRPEND_31                ((u32)0x80000000)        </span><span class="comment">/* bit 31 */</span>
    2468. 

  2468. <a name="l02436"></a>02436 
    2469. 

  2469. <a name="l02437"></a>02437 
    2470. 

  2470. <a name="l02438"></a>02438 <span class="comment">/******************  Bit definition for NVIC_IABR register  *******************/</span>
    2471. 

  2471. <a name="l02439"></a>02439 <span class="preprocessor">#define  NVIC_IABR_ACTIVE                    ((u32)0xFFFFFFFF)        </span><span class="comment">/* Interrupt active flags */</span>
    2472. 

  2472. <a name="l02440"></a>02440 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_0                  ((u32)0x00000001)        </span><span class="comment">/* bit 0 */</span>
    2473. 

  2473. <a name="l02441"></a>02441 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_1                  ((u32)0x00000002)        </span><span class="comment">/* bit 1 */</span>
    2474. 

  2474. <a name="l02442"></a>02442 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_2                  ((u32)0x00000004)        </span><span class="comment">/* bit 2 */</span>
    2475. 

  2475. <a name="l02443"></a>02443 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_3                  ((u32)0x00000008)        </span><span class="comment">/* bit 3 */</span>
    2476. 

  2476. <a name="l02444"></a>02444 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_4                  ((u32)0x00000010)        </span><span class="comment">/* bit 4 */</span>
    2477. 

  2477. <a name="l02445"></a>02445 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_5                  ((u32)0x00000020)        </span><span class="comment">/* bit 5 */</span>
    2478. 

  2478. <a name="l02446"></a>02446 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_6                  ((u32)0x00000040)        </span><span class="comment">/* bit 6 */</span>
    2479. 

  2479. <a name="l02447"></a>02447 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_7                  ((u32)0x00000080)        </span><span class="comment">/* bit 7 */</span>
    2480. 

  2480. <a name="l02448"></a>02448 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_8                  ((u32)0x00000100)        </span><span class="comment">/* bit 8 */</span>
    2481. 

  2481. <a name="l02449"></a>02449 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_9                  ((u32)0x00000200)        </span><span class="comment">/* bit 9 */</span>
    2482. 

  2482. <a name="l02450"></a>02450 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_10                 ((u32)0x00000400)        </span><span class="comment">/* bit 10 */</span>
    2483. 

  2483. <a name="l02451"></a>02451 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_11                 ((u32)0x00000800)        </span><span class="comment">/* bit 11 */</span>
    2484. 

  2484. <a name="l02452"></a>02452 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_12                 ((u32)0x00001000)        </span><span class="comment">/* bit 12 */</span>
    2485. 

  2485. <a name="l02453"></a>02453 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_13                 ((u32)0x00002000)        </span><span class="comment">/* bit 13 */</span>
    2486. 

  2486. <a name="l02454"></a>02454 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_14                 ((u32)0x00004000)        </span><span class="comment">/* bit 14 */</span>
    2487. 

  2487. <a name="l02455"></a>02455 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_15                 ((u32)0x00008000)        </span><span class="comment">/* bit 15 */</span>
    2488. 

  2488. <a name="l02456"></a>02456 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_16                 ((u32)0x00010000)        </span><span class="comment">/* bit 16 */</span>
    2489. 

  2489. <a name="l02457"></a>02457 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_17                 ((u32)0x00020000)        </span><span class="comment">/* bit 17 */</span>
    2490. 

  2490. <a name="l02458"></a>02458 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_18                 ((u32)0x00040000)        </span><span class="comment">/* bit 18 */</span>
    2491. 

  2491. <a name="l02459"></a>02459 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_19                 ((u32)0x00080000)        </span><span class="comment">/* bit 19 */</span>
    2492. 

  2492. <a name="l02460"></a>02460 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_20                 ((u32)0x00100000)        </span><span class="comment">/* bit 20 */</span>
    2493. 

  2493. <a name="l02461"></a>02461 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_21                 ((u32)0x00200000)        </span><span class="comment">/* bit 21 */</span>
    2494. 

  2494. <a name="l02462"></a>02462 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_22                 ((u32)0x00400000)        </span><span class="comment">/* bit 22 */</span>
    2495. 

  2495. <a name="l02463"></a>02463 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_23                 ((u32)0x00800000)        </span><span class="comment">/* bit 23 */</span>
    2496. 

  2496. <a name="l02464"></a>02464 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_24                 ((u32)0x01000000)        </span><span class="comment">/* bit 24 */</span>
    2497. 

  2497. <a name="l02465"></a>02465 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_25                 ((u32)0x02000000)        </span><span class="comment">/* bit 25 */</span>
    2498. 

  2498. <a name="l02466"></a>02466 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_26                 ((u32)0x04000000)        </span><span class="comment">/* bit 26 */</span>
    2499. 

  2499. <a name="l02467"></a>02467 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_27                 ((u32)0x08000000)        </span><span class="comment">/* bit 27 */</span>
    2500. 

  2500. <a name="l02468"></a>02468 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_28                 ((u32)0x10000000)        </span><span class="comment">/* bit 28 */</span>
    2501. 

  2501. <a name="l02469"></a>02469 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_29                 ((u32)0x20000000)        </span><span class="comment">/* bit 29 */</span>
    2502. 

  2502. <a name="l02470"></a>02470 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_30                 ((u32)0x40000000)        </span><span class="comment">/* bit 30 */</span>
    2503. 

  2503. <a name="l02471"></a>02471 <span class="preprocessor">#define  NVIC_IABR_ACTIVE_31                 ((u32)0x80000000)        </span><span class="comment">/* bit 31 */</span>
    2504. 

  2504. <a name="l02472"></a>02472 
    2505. 

  2505. <a name="l02473"></a>02473 
    2506. 

  2506. <a name="l02474"></a>02474 <span class="comment">/******************  Bit definition for NVIC_PRI0 register  *******************/</span>
    2507. 

  2507. <a name="l02475"></a>02475 <span class="preprocessor">#define  NVIC_IPR0_PRI_0                     ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 0 */</span>
    2508. 

  2508. <a name="l02476"></a>02476 <span class="preprocessor">#define  NVIC_IPR0_PRI_1                     ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 1 */</span>
    2509. 

  2509. <a name="l02477"></a>02477 <span class="preprocessor">#define  NVIC_IPR0_PRI_2                     ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 2 */</span>
    2510. 

  2510. <a name="l02478"></a>02478 <span class="preprocessor">#define  NVIC_IPR0_PRI_3                     ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 3 */</span>
    2511. 

  2511. <a name="l02479"></a>02479 
    2512. 

  2512. <a name="l02480"></a>02480 
    2513. 

  2513. <a name="l02481"></a>02481 <span class="comment">/******************  Bit definition for NVIC_PRI1 register  *******************/</span>
    2514. 

  2514. <a name="l02482"></a>02482 <span class="preprocessor">#define  NVIC_IPR1_PRI_4                     ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 4 */</span>
    2515. 

  2515. <a name="l02483"></a>02483 <span class="preprocessor">#define  NVIC_IPR1_PRI_5                     ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 5 */</span>
    2516. 

  2516. <a name="l02484"></a>02484 <span class="preprocessor">#define  NVIC_IPR1_PRI_6                     ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 6 */</span>
    2517. 

  2517. <a name="l02485"></a>02485 <span class="preprocessor">#define  NVIC_IPR1_PRI_7                     ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 7 */</span>
    2518. 

  2518. <a name="l02486"></a>02486 
    2519. 

  2519. <a name="l02487"></a>02487 
    2520. 

  2520. <a name="l02488"></a>02488 <span class="comment">/******************  Bit definition for NVIC_PRI2 register  *******************/</span>
    2521. 

  2521. <a name="l02489"></a>02489 <span class="preprocessor">#define  NVIC_IPR2_PRI_8                     ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 8 */</span>
    2522. 

  2522. <a name="l02490"></a>02490 <span class="preprocessor">#define  NVIC_IPR2_PRI_9                     ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 9 */</span>
    2523. 

  2523. <a name="l02491"></a>02491 <span class="preprocessor">#define  NVIC_IPR2_PRI_10                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 10 */</span>
    2524. 

  2524. <a name="l02492"></a>02492 <span class="preprocessor">#define  NVIC_IPR2_PRI_11                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 11 */</span>
    2525. 

  2525. <a name="l02493"></a>02493 
    2526. 

  2526. <a name="l02494"></a>02494 
    2527. 

  2527. <a name="l02495"></a>02495 <span class="comment">/******************  Bit definition for NVIC_PRI3 register  *******************/</span>
    2528. 

  2528. <a name="l02496"></a>02496 <span class="preprocessor">#define  NVIC_IPR3_PRI_12                    ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 12 */</span>
    2529. 

  2529. <a name="l02497"></a>02497 <span class="preprocessor">#define  NVIC_IPR3_PRI_13                    ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 13 */</span>
    2530. 

  2530. <a name="l02498"></a>02498 <span class="preprocessor">#define  NVIC_IPR3_PRI_14                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 14 */</span>
    2531. 

  2531. <a name="l02499"></a>02499 <span class="preprocessor">#define  NVIC_IPR3_PRI_15                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 15 */</span>
    2532. 

  2532. <a name="l02500"></a>02500 
    2533. 

  2533. <a name="l02501"></a>02501 
    2534. 

  2534. <a name="l02502"></a>02502 <span class="comment">/******************  Bit definition for NVIC_PRI4 register  *******************/</span>
    2535. 

  2535. <a name="l02503"></a>02503 <span class="preprocessor">#define  NVIC_IPR4_PRI_16                    ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 16 */</span>
    2536. 

  2536. <a name="l02504"></a>02504 <span class="preprocessor">#define  NVIC_IPR4_PRI_17                    ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 17 */</span>
    2537. 

  2537. <a name="l02505"></a>02505 <span class="preprocessor">#define  NVIC_IPR4_PRI_18                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 18 */</span>
    2538. 

  2538. <a name="l02506"></a>02506 <span class="preprocessor">#define  NVIC_IPR4_PRI_19                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 19 */</span>
    2539. 

  2539. <a name="l02507"></a>02507 
    2540. 

  2540. <a name="l02508"></a>02508 
    2541. 

  2541. <a name="l02509"></a>02509 <span class="comment">/******************  Bit definition for NVIC_PRI5 register  *******************/</span>
    2542. 

  2542. <a name="l02510"></a>02510 <span class="preprocessor">#define  NVIC_IPR5_PRI_20                    ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 20 */</span>
    2543. 

  2543. <a name="l02511"></a>02511 <span class="preprocessor">#define  NVIC_IPR5_PRI_21                    ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 21 */</span>
    2544. 

  2544. <a name="l02512"></a>02512 <span class="preprocessor">#define  NVIC_IPR5_PRI_22                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 22 */</span>
    2545. 

  2545. <a name="l02513"></a>02513 <span class="preprocessor">#define  NVIC_IPR5_PRI_23                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 23 */</span>
    2546. 

  2546. <a name="l02514"></a>02514 
    2547. 

  2547. <a name="l02515"></a>02515 
    2548. 

  2548. <a name="l02516"></a>02516 <span class="comment">/******************  Bit definition for NVIC_PRI6 register  *******************/</span>
    2549. 

  2549. <a name="l02517"></a>02517 <span class="preprocessor">#define  NVIC_IPR6_PRI_24                    ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 24 */</span>
    2550. 

  2550. <a name="l02518"></a>02518 <span class="preprocessor">#define  NVIC_IPR6_PRI_25                    ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 25 */</span>
    2551. 

  2551. <a name="l02519"></a>02519 <span class="preprocessor">#define  NVIC_IPR6_PRI_26                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 26 */</span>
    2552. 

  2552. <a name="l02520"></a>02520 <span class="preprocessor">#define  NVIC_IPR6_PRI_27                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 27 */</span>
    2553. 

  2553. <a name="l02521"></a>02521 
    2554. 

  2554. <a name="l02522"></a>02522 
    2555. 

  2555. <a name="l02523"></a>02523 <span class="comment">/******************  Bit definition for NVIC_PRI7 register  *******************/</span>
    2556. 

  2556. <a name="l02524"></a>02524 <span class="preprocessor">#define  NVIC_IPR7_PRI_28                    ((u32)0x000000FF)        </span><span class="comment">/* Priority of interrupt 28 */</span>
    2557. 

  2557. <a name="l02525"></a>02525 <span class="preprocessor">#define  NVIC_IPR7_PRI_29                    ((u32)0x0000FF00)        </span><span class="comment">/* Priority of interrupt 29 */</span>
    2558. 

  2558. <a name="l02526"></a>02526 <span class="preprocessor">#define  NVIC_IPR7_PRI_30                    ((u32)0x00FF0000)        </span><span class="comment">/* Priority of interrupt 30 */</span>
    2559. 

  2559. <a name="l02527"></a>02527 <span class="preprocessor">#define  NVIC_IPR7_PRI_31                    ((u32)0xFF000000)        </span><span class="comment">/* Priority of interrupt 31 */</span>
    2560. 

  2560. <a name="l02528"></a>02528 
    2561. 

  2561. <a name="l02529"></a>02529 
    2562. 

  2562. <a name="l02530"></a>02530 <span class="comment">/******************  Bit definition for SCB_CPUID register  *******************/</span>
    2563. 

  2563. <a name="l02531"></a>02531 <span class="preprocessor">#define  SCB_CPUID_REVISION                  ((u32)0x0000000F)        </span><span class="comment">/* Implementation defined revision number */</span>
    2564. 

  2564. <a name="l02532"></a>02532 <span class="preprocessor">#define  SCB_CPUID_PARTNO                    ((u32)0x0000FFF0)        </span><span class="comment">/* Number of processor within family */</span>
    2565. 

  2565. <a name="l02533"></a>02533 <span class="preprocessor">#define  SCB_CPUID_Constant                  ((u32)0x000F0000)        </span><span class="comment">/* Reads as 0x0F */</span>
    2566. 

  2566. <a name="l02534"></a>02534 <span class="preprocessor">#define  SCB_CPUID_VARIANT                   ((u32)0x00F00000)        </span><span class="comment">/* Implementation defined variant number */</span>
    2567. 

  2567. <a name="l02535"></a>02535 <span class="preprocessor">#define  SCB_CPUID_IMPLEMENTER               ((u32)0xFF000000)        </span><span class="comment">/* Implementer code. ARM is 0x41 */</span>
    2568. 

  2568. <a name="l02536"></a>02536 
    2569. 

  2569. <a name="l02537"></a>02537 
    2570. 

  2570. <a name="l02538"></a>02538 <span class="comment">/*******************  Bit definition for SCB_ICSR register  *******************/</span>
    2571. 

  2571. <a name="l02539"></a>02539 <span class="preprocessor">#define  SCB_ICSR_VECTACTIVE                 ((u32)0x000001FF)        </span><span class="comment">/* Active ISR number field */</span>
    2572. 

  2572. <a name="l02540"></a>02540 <span class="preprocessor">#define  SCB_ICSR_RETTOBASE                  ((u32)0x00000800)        </span><span class="comment">/* All active exceptions minus the IPSR_current_exception yields the empty set */</span>
    2573. 

  2573. <a name="l02541"></a>02541 <span class="preprocessor">#define  SCB_ICSR_VECTPENDING                ((u32)0x003FF000)        </span><span class="comment">/* Pending ISR number field */</span>
    2574. 

  2574. <a name="l02542"></a>02542 <span class="preprocessor">#define  SCB_ICSR_ISRPENDING                 ((u32)0x00400000)        </span><span class="comment">/* Interrupt pending flag */</span>
    2575. 

  2575. <a name="l02543"></a>02543 <span class="preprocessor">#define  SCB_ICSR_ISRPREEMPT                 ((u32)0x00800000)        </span><span class="comment">/* It indicates that a pending interrupt becomes active in the next running cycle */</span>
    2576. 

  2576. <a name="l02544"></a>02544 <span class="preprocessor">#define  SCB_ICSR_PENDSTCLR                  ((u32)0x02000000)        </span><span class="comment">/* Clear pending SysTick bit */</span>
    2577. 

  2577. <a name="l02545"></a>02545 <span class="preprocessor">#define  SCB_ICSR_PENDSTSET                  ((u32)0x04000000)        </span><span class="comment">/* Set pending SysTick bit */</span>
    2578. 

  2578. <a name="l02546"></a>02546 <span class="preprocessor">#define  SCB_ICSR_PENDSVCLR                  ((u32)0x08000000)        </span><span class="comment">/* Clear pending pendSV bit */</span>
    2579. 

  2579. <a name="l02547"></a>02547 <span class="preprocessor">#define  SCB_ICSR_PENDSVSET                  ((u32)0x10000000)        </span><span class="comment">/* Set pending pendSV bit */</span>
    2580. 

  2580. <a name="l02548"></a>02548 <span class="preprocessor">#define  SCB_ICSR_NMIPENDSET                 ((u32)0x80000000)        </span><span class="comment">/* Set pending NMI bit */</span>
    2581. 

  2581. <a name="l02549"></a>02549 
    2582. 

  2582. <a name="l02550"></a>02550 
    2583. 

  2583. <a name="l02551"></a>02551 <span class="comment">/*******************  Bit definition for SCB_VTOR register  *******************/</span>
    2584. 

  2584. <a name="l02552"></a>02552 <span class="preprocessor">#define  SCB_VTOR_TBLOFF                     ((u32)0x1FFFFF80)        </span><span class="comment">/* Vector table base offset field */</span>
    2585. 

  2585. <a name="l02553"></a>02553 <span class="preprocessor">#define  SCB_VTOR_TBLBASE                    ((u32)0x20000000)        </span><span class="comment">/* Table base in code(0) or RAM(1) */</span>
    2586. 

  2586. <a name="l02554"></a>02554 
    2587. 

  2587. <a name="l02555"></a>02555 
    2588. 

  2588. <a name="l02556"></a>02556 <span class="comment">/******************  Bit definition for SCB_AIRCR register  *******************/</span>
    2589. 

  2589. <a name="l02557"></a>02557 <span class="preprocessor">#define  SCB_AIRCR_VECTRESET                 ((u32)0x00000001)        </span><span class="comment">/* System Reset bit */</span>
    2590. 

  2590. <a name="l02558"></a>02558 <span class="preprocessor">#define  SCB_AIRCR_VECTCLRACTIVE             ((u32)0x00000002)        </span><span class="comment">/* Clear active vector bit */</span>
    2591. 

  2591. <a name="l02559"></a>02559 <span class="preprocessor">#define  SCB_AIRCR_SYSRESETREQ               ((u32)0x00000004)        </span><span class="comment">/* Requests chip control logic to generate a reset */</span>
    2592. 

  2592. <a name="l02560"></a>02560 
    2593. 

  2593. <a name="l02561"></a>02561 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP                  ((u32)0x00000700)        </span><span class="comment">/* PRIGROUP[2:0] bits (Priority group) */</span>
    2594. 

  2594. <a name="l02562"></a>02562 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP_0                ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    2595. 

  2595. <a name="l02563"></a>02563 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP_1                ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    2596. 

  2596. <a name="l02564"></a>02564 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP_2                ((u32)0x00000400)        </span><span class="comment">/* Bit 2  */</span>
    2597. 

  2597. <a name="l02565"></a>02565 
    2598. 

  2598. <a name="l02566"></a>02566 <span class="comment">/* prority group configuration */</span>
    2599. 

  2599. <a name="l02567"></a>02567 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP0                 ((u32)0x00000000)        </span><span class="comment">/* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */</span>
    2600. 

  2600. <a name="l02568"></a>02568 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP1                 ((u32)0x00000100)        </span><span class="comment">/* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */</span>
    2601. 

  2601. <a name="l02569"></a>02569 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP2                 ((u32)0x00000200)        </span><span class="comment">/* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */</span>
    2602. 

  2602. <a name="l02570"></a>02570 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP3                 ((u32)0x00000300)        </span><span class="comment">/* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */</span>
    2603. 

  2603. <a name="l02571"></a>02571 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP4                 ((u32)0x00000400)        </span><span class="comment">/* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */</span>
    2604. 

  2604. <a name="l02572"></a>02572 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP5                 ((u32)0x00000500)        </span><span class="comment">/* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */</span>
    2605. 

  2605. <a name="l02573"></a>02573 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP6                 ((u32)0x00000600)        </span><span class="comment">/* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */</span>
    2606. 

  2606. <a name="l02574"></a>02574 <span class="preprocessor">#define  SCB_AIRCR_PRIGROUP7                 ((u32)0x00000700)        </span><span class="comment">/* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */</span>
    2607. 

  2607. <a name="l02575"></a>02575 
    2608. 

  2608. <a name="l02576"></a>02576 <span class="preprocessor">#define  SCB_AIRCR_ENDIANESS                 ((u32)0x00008000)        </span><span class="comment">/* Data endianness bit */</span>
    2609. 

  2609. <a name="l02577"></a>02577 <span class="preprocessor">#define  SCB_AIRCR_VECTKEY                   ((u32)0xFFFF0000)        </span><span class="comment">/* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */</span>
    2610. 

  2610. <a name="l02578"></a>02578 
    2611. 

  2611. <a name="l02579"></a>02579 
    2612. 

  2612. <a name="l02580"></a>02580 <span class="comment">/*******************  Bit definition for SCB_SCR register  ********************/</span>
    2613. 

  2613. <a name="l02581"></a>02581 <span class="preprocessor">#define  SCB_SCR_SLEEPONEXIT                 ((u8)0x02)               </span><span class="comment">/* Sleep on exit bit */</span>
    2614. 

  2614. <a name="l02582"></a>02582 <span class="preprocessor">#define  SCB_SCR_SLEEPDEEP                   ((u8)0x04)               </span><span class="comment">/* Sleep deep bit */</span>
    2615. 

  2615. <a name="l02583"></a>02583 <span class="preprocessor">#define  SCB_SCR_SEVONPEND                   ((u8)0x10)               </span><span class="comment">/* Wake up from WFE */</span>
    2616. 

  2616. <a name="l02584"></a>02584 
    2617. 

  2617. <a name="l02585"></a>02585 
    2618. 

  2618. <a name="l02586"></a>02586 <span class="comment">/********************  Bit definition for SCB_CCR register  *******************/</span>
    2619. 

  2619. <a name="l02587"></a>02587 <span class="preprocessor">#define  SCB_CCR_NONBASETHRDENA              ((u16)0x0001)            </span><span class="comment">/* Thread mode can be entered from any level in Handler mode by controlled return value */</span>
    2620. 

  2620. <a name="l02588"></a>02588 <span class="preprocessor">#define  SCB_CCR_USERSETMPEND                ((u16)0x0002)            </span><span class="comment">/* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */</span>
    2621. 

  2621. <a name="l02589"></a>02589 <span class="preprocessor">#define  SCB_CCR_UNALIGN_TRP                 ((u16)0x0008)            </span><span class="comment">/* Trap for unaligned access */</span>
    2622. 

  2622. <a name="l02590"></a>02590 <span class="preprocessor">#define  SCB_CCR_DIV_0_TRP                   ((u16)0x0010)            </span><span class="comment">/* Trap on Divide by 0 */</span>
    2623. 

  2623. <a name="l02591"></a>02591 <span class="preprocessor">#define  SCB_CCR_BFHFNMIGN                   ((u16)0x0100)            </span><span class="comment">/* Handlers running at priority -1 and -2 */</span>
    2624. 

  2624. <a name="l02592"></a>02592 <span class="preprocessor">#define  SCB_CCR_STKALIGN                    ((u16)0x0200)            </span><span class="comment">/* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */</span>
    2625. 

  2625. <a name="l02593"></a>02593 
    2626. 

  2626. <a name="l02594"></a>02594 
    2627. 

  2627. <a name="l02595"></a>02595 <span class="comment">/*******************  Bit definition for SCB_SHPR register ********************/</span>
    2628. 

  2628. <a name="l02596"></a>02596 <span class="preprocessor">#define  SCB_SHPR_PRI_N                      ((u32)0x000000FF)        </span><span class="comment">/* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */</span>
    2629. 

  2629. <a name="l02597"></a>02597 <span class="preprocessor">#define  SCB_SHPR_PRI_N1                     ((u32)0x0000FF00)        </span><span class="comment">/* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */</span>
    2630. 

  2630. <a name="l02598"></a>02598 <span class="preprocessor">#define  SCB_SHPR_PRI_N2                     ((u32)0x00FF0000)        </span><span class="comment">/* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */</span>
    2631. 

  2631. <a name="l02599"></a>02599 <span class="preprocessor">#define  SCB_SHPR_PRI_N3                     ((u32)0xFF000000)        </span><span class="comment">/* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */</span>
    2632. 

  2632. <a name="l02600"></a>02600 
    2633. 

  2633. <a name="l02601"></a>02601 
    2634. 

  2634. <a name="l02602"></a>02602 <span class="comment">/******************  Bit definition for SCB_SHCSR register  *******************/</span>
    2635. 

  2635. <a name="l02603"></a>02603 <span class="preprocessor">#define  SCB_SHCSR_MEMFAULTACT               ((u32)0x00000001)        </span><span class="comment">/* MemManage is active */</span>
    2636. 

  2636. <a name="l02604"></a>02604 <span class="preprocessor">#define  SCB_SHCSR_BUSFAULTACT               ((u32)0x00000002)        </span><span class="comment">/* BusFault is active */</span>
    2637. 

  2637. <a name="l02605"></a>02605 <span class="preprocessor">#define  SCB_SHCSR_USGFAULTACT               ((u32)0x00000008)        </span><span class="comment">/* UsageFault is active */</span>
    2638. 

  2638. <a name="l02606"></a>02606 <span class="preprocessor">#define  SCB_SHCSR_SVCALLACT                 ((u32)0x00000080)        </span><span class="comment">/* SVCall is active */</span>
    2639. 

  2639. <a name="l02607"></a>02607 <span class="preprocessor">#define  SCB_SHCSR_MONITORACT                ((u32)0x00000100)        </span><span class="comment">/* Monitor is active */</span>
    2640. 

  2640. <a name="l02608"></a>02608 <span class="preprocessor">#define  SCB_SHCSR_PENDSVACT                 ((u32)0x00000400)        </span><span class="comment">/* PendSV is active */</span>
    2641. 

  2641. <a name="l02609"></a>02609 <span class="preprocessor">#define  SCB_SHCSR_SYSTICKACT                ((u32)0x00000800)        </span><span class="comment">/* SysTick is active */</span>
    2642. 

  2642. <a name="l02610"></a>02610 <span class="preprocessor">#define  SCB_SHCSR_USGFAULTPENDED            ((u32)0x00001000)        </span><span class="comment">/* Usage Fault is pended */</span>
    2643. 

  2643. <a name="l02611"></a>02611 <span class="preprocessor">#define  SCB_SHCSR_MEMFAULTPENDED            ((u32)0x00002000)        </span><span class="comment">/* MemManage is pended */</span>
    2644. 

  2644. <a name="l02612"></a>02612 <span class="preprocessor">#define  SCB_SHCSR_BUSFAULTPENDED            ((u32)0x00004000)        </span><span class="comment">/* Bus Fault is pended */</span>
    2645. 

  2645. <a name="l02613"></a>02613 <span class="preprocessor">#define  SCB_SHCSR_SVCALLPENDED              ((u32)0x00008000)        </span><span class="comment">/* SVCall is pended */</span>
    2646. 

  2646. <a name="l02614"></a>02614 <span class="preprocessor">#define  SCB_SHCSR_MEMFAULTENA               ((u32)0x00010000)        </span><span class="comment">/* MemManage enable */</span>
    2647. 

  2647. <a name="l02615"></a>02615 <span class="preprocessor">#define  SCB_SHCSR_BUSFAULTENA               ((u32)0x00020000)        </span><span class="comment">/* Bus Fault enable */</span>
    2648. 

  2648. <a name="l02616"></a>02616 <span class="preprocessor">#define  SCB_SHCSR_USGFAULTENA               ((u32)0x00040000)        </span><span class="comment">/* UsageFault enable */</span>
    2649. 

  2649. <a name="l02617"></a>02617 
    2650. 

  2650. <a name="l02618"></a>02618 
    2651. 

  2651. <a name="l02619"></a>02619 <span class="comment">/*******************  Bit definition for SCB_CFSR register  *******************/</span>
    2652. 

  2652. <a name="l02620"></a>02620 <span class="comment">/* MFSR */</span>
    2653. 

  2653. <a name="l02621"></a>02621 <span class="preprocessor">#define  SCB_CFSR_IACCVIOL                   ((u32)0x00000001)        </span><span class="comment">/* Instruction access violation */</span>
    2654. 

  2654. <a name="l02622"></a>02622 <span class="preprocessor">#define  SCB_CFSR_DACCVIOL                   ((u32)0x00000002)        </span><span class="comment">/* Data access violation */</span>
    2655. 

  2655. <a name="l02623"></a>02623 <span class="preprocessor">#define  SCB_CFSR_MUNSTKERR                  ((u32)0x00000008)        </span><span class="comment">/* Unstacking error */</span>
    2656. 

  2656. <a name="l02624"></a>02624 <span class="preprocessor">#define  SCB_CFSR_MSTKERR                    ((u32)0x00000010)        </span><span class="comment">/* Stacking error */</span>
    2657. 

  2657. <a name="l02625"></a>02625 <span class="preprocessor">#define  SCB_CFSR_MMARVALID                  ((u32)0x00000080)        </span><span class="comment">/* Memory Manage Address Register address valid flag */</span>
    2658. 

  2658. <a name="l02626"></a>02626 <span class="comment">/* BFSR */</span>
    2659. 

  2659. <a name="l02627"></a>02627 <span class="preprocessor">#define  SCB_CFSR_IBUSERR                    ((u32)0x00000100)        </span><span class="comment">/* Instruction bus error flag */</span>
    2660. 

  2660. <a name="l02628"></a>02628 <span class="preprocessor">#define  SCB_CFSR_PRECISERR                  ((u32)0x00000200)        </span><span class="comment">/* Precise data bus error */</span>
    2661. 

  2661. <a name="l02629"></a>02629 <span class="preprocessor">#define  SCB_CFSR_IMPRECISERR                ((u32)0x00000400)        </span><span class="comment">/* Imprecise data bus error */</span>
    2662. 

  2662. <a name="l02630"></a>02630 <span class="preprocessor">#define  SCB_CFSR_UNSTKERR                   ((u32)0x00000800)        </span><span class="comment">/* Unstacking error */</span>
    2663. 

  2663. <a name="l02631"></a>02631 <span class="preprocessor">#define  SCB_CFSR_STKERR                     ((u32)0x00001000)        </span><span class="comment">/* Stacking error */</span>
    2664. 

  2664. <a name="l02632"></a>02632 <span class="preprocessor">#define  SCB_CFSR_BFARVALID                  ((u32)0x00008000)        </span><span class="comment">/* Bus Fault Address Register address valid flag */</span>
    2665. 

  2665. <a name="l02633"></a>02633 <span class="comment">/* UFSR */</span>
    2666. 

  2666. <a name="l02634"></a>02634 <span class="preprocessor">#define  SCB_CFSR_UNDEFINSTR                 ((u32)0x00010000)        </span><span class="comment">/* The processor attempt to excecute an undefined instruction */</span>
    2667. 

  2667. <a name="l02635"></a>02635 <span class="preprocessor">#define  SCB_CFSR_INVSTATE                   ((u32)0x00020000)        </span><span class="comment">/* Invalid combination of EPSR and instruction */</span>
    2668. 

  2668. <a name="l02636"></a>02636 <span class="preprocessor">#define  SCB_CFSR_INVPC                      ((u32)0x00040000)        </span><span class="comment">/* Attempt to load EXC_RETURN into pc illegally */</span>
    2669. 

  2669. <a name="l02637"></a>02637 <span class="preprocessor">#define  SCB_CFSR_NOCP                       ((u32)0x00080000)        </span><span class="comment">/* Attempt to use a coprocessor instruction */</span>
    2670. 

  2670. <a name="l02638"></a>02638 <span class="preprocessor">#define  SCB_CFSR_UNALIGNED                  ((u32)0x01000000)        </span><span class="comment">/* Fault occurs when there is an attempt to make an unaligned memory access */</span>
    2671. 

  2671. <a name="l02639"></a>02639 <span class="preprocessor">#define  SCB_CFSR_DIVBYZERO                  ((u32)0x02000000)        </span><span class="comment">/* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */</span>
    2672. 

  2672. <a name="l02640"></a>02640 
    2673. 

  2673. <a name="l02641"></a>02641 
    2674. 

  2674. <a name="l02642"></a>02642 <span class="comment">/*******************  Bit definition for SCB_HFSR register  *******************/</span>
    2675. 

  2675. <a name="l02643"></a>02643 <span class="preprocessor">#define  SCB_HFSR_VECTTBL                    ((u32)0x00000002)        </span><span class="comment">/* Fault occures because of vector table read on exception processing */</span>
    2676. 

  2676. <a name="l02644"></a>02644 <span class="preprocessor">#define  SCB_HFSR_FORCED                     ((u32)0x40000000)        </span><span class="comment">/* Hard Fault activated when a configurable Fault was received and cannot activate */</span>
    2677. 

  2677. <a name="l02645"></a>02645 <span class="preprocessor">#define  SCB_HFSR_DEBUGEVT                   ((u32)0x80000000)        </span><span class="comment">/* Fault related to debug */</span>
    2678. 

  2678. <a name="l02646"></a>02646 
    2679. 

  2679. <a name="l02647"></a>02647 
    2680. 

  2680. <a name="l02648"></a>02648 <span class="comment">/*******************  Bit definition for SCB_DFSR register  *******************/</span>
    2681. 

  2681. <a name="l02649"></a>02649 <span class="preprocessor">#define  SCB_DFSR_HALTED                     ((u8)0x01)               </span><span class="comment">/* Halt request flag */</span>
    2682. 

  2682. <a name="l02650"></a>02650 <span class="preprocessor">#define  SCB_DFSR_BKPT                       ((u8)0x02)               </span><span class="comment">/* BKPT flag */</span>
    2683. 

  2683. <a name="l02651"></a>02651 <span class="preprocessor">#define  SCB_DFSR_DWTTRAP                    ((u8)0x04)               </span><span class="comment">/* Data Watchpoint and Trace (DWT) flag */</span>
    2684. 

  2684. <a name="l02652"></a>02652 <span class="preprocessor">#define  SCB_DFSR_VCATCH                     ((u8)0x08)               </span><span class="comment">/* Vector catch flag */</span>
    2685. 

  2685. <a name="l02653"></a>02653 <span class="preprocessor">#define  SCB_DFSR_EXTERNAL                   ((u8)0x10)               </span><span class="comment">/* External debug request flag */</span>
    2686. 

  2686. <a name="l02654"></a>02654 
    2687. 

  2687. <a name="l02655"></a>02655 
    2688. 

  2688. <a name="l02656"></a>02656 <span class="comment">/*******************  Bit definition for SCB_MMFAR register  ******************/</span>
    2689. 

  2689. <a name="l02657"></a>02657 <span class="preprocessor">#define  SCB_MMFAR_ADDRESS                   ((u32)0xFFFFFFFF)        </span><span class="comment">/* Mem Manage fault address field */</span>
    2690. 

  2690. <a name="l02658"></a>02658 
    2691. 

  2691. <a name="l02659"></a>02659 
    2692. 

  2692. <a name="l02660"></a>02660 <span class="comment">/*******************  Bit definition for SCB_BFAR register  *******************/</span>
    2693. 

  2693. <a name="l02661"></a>02661 <span class="preprocessor">#define  SCB_BFAR_ADDRESS                    ((u32)0xFFFFFFFF)        </span><span class="comment">/* Bus fault address field */</span>
    2694. 

  2694. <a name="l02662"></a>02662 
    2695. 

  2695. <a name="l02663"></a>02663 
    2696. 

  2696. <a name="l02664"></a>02664 <span class="comment">/*******************  Bit definition for SCB_afsr register  *******************/</span>
    2697. 

  2697. <a name="l02665"></a>02665 <span class="preprocessor">#define  SCB_AFSR_IMPDEF                     ((u32)0xFFFFFFFF)        </span><span class="comment">/* Implementation defined */</span>
    2698. 

  2698. <a name="l02666"></a>02666 
    2699. 

  2699. <a name="l02667"></a>02667 
    2700. 

  2700. <a name="l02668"></a>02668 
    2701. 

  2701. <a name="l02669"></a>02669 <span class="comment">/******************************************************************************/</span>
    2702. 

  2702. <a name="l02670"></a>02670 <span class="comment">/*                                                                            */</span>
    2703. 

  2703. <a name="l02671"></a>02671 <span class="comment">/*                    External Interrupt/Event Controller                     */</span>
    2704. 

  2704. <a name="l02672"></a>02672 <span class="comment">/*                                                                            */</span>
    2705. 

  2705. <a name="l02673"></a>02673 <span class="comment">/******************************************************************************/</span>
    2706. 

  2706. <a name="l02674"></a>02674 
    2707. 

  2707. <a name="l02675"></a>02675 <span class="comment">/*******************  Bit definition for EXTI_IMR register  *******************/</span>
    2708. 

  2708. <a name="l02676"></a>02676 <span class="preprocessor">#define  EXTI_IMR_MR0                        ((u32)0x00000001)        </span><span class="comment">/* Interrupt Mask on line 0 */</span>
    2709. 

  2709. <a name="l02677"></a>02677 <span class="preprocessor">#define  EXTI_IMR_MR1                        ((u32)0x00000002)        </span><span class="comment">/* Interrupt Mask on line 1 */</span>
    2710. 

  2710. <a name="l02678"></a>02678 <span class="preprocessor">#define  EXTI_IMR_MR2                        ((u32)0x00000004)        </span><span class="comment">/* Interrupt Mask on line 2 */</span>
    2711. 

  2711. <a name="l02679"></a>02679 <span class="preprocessor">#define  EXTI_IMR_MR3                        ((u32)0x00000008)        </span><span class="comment">/* Interrupt Mask on line 3 */</span>
    2712. 

  2712. <a name="l02680"></a>02680 <span class="preprocessor">#define  EXTI_IMR_MR4                        ((u32)0x00000010)        </span><span class="comment">/* Interrupt Mask on line 4 */</span>
    2713. 

  2713. <a name="l02681"></a>02681 <span class="preprocessor">#define  EXTI_IMR_MR5                        ((u32)0x00000020)        </span><span class="comment">/* Interrupt Mask on line 5 */</span>
    2714. 

  2714. <a name="l02682"></a>02682 <span class="preprocessor">#define  EXTI_IMR_MR6                        ((u32)0x00000040)        </span><span class="comment">/* Interrupt Mask on line 6 */</span>
    2715. 

  2715. <a name="l02683"></a>02683 <span class="preprocessor">#define  EXTI_IMR_MR7                        ((u32)0x00000080)        </span><span class="comment">/* Interrupt Mask on line 7 */</span>
    2716. 

  2716. <a name="l02684"></a>02684 <span class="preprocessor">#define  EXTI_IMR_MR8                        ((u32)0x00000100)        </span><span class="comment">/* Interrupt Mask on line 8 */</span>
    2717. 

  2717. <a name="l02685"></a>02685 <span class="preprocessor">#define  EXTI_IMR_MR9                        ((u32)0x00000200)        </span><span class="comment">/* Interrupt Mask on line 9 */</span>
    2718. 

  2718. <a name="l02686"></a>02686 <span class="preprocessor">#define  EXTI_IMR_MR10                       ((u32)0x00000400)        </span><span class="comment">/* Interrupt Mask on line 10 */</span>
    2719. 

  2719. <a name="l02687"></a>02687 <span class="preprocessor">#define  EXTI_IMR_MR11                       ((u32)0x00000800)        </span><span class="comment">/* Interrupt Mask on line 11 */</span>
    2720. 

  2720. <a name="l02688"></a>02688 <span class="preprocessor">#define  EXTI_IMR_MR12                       ((u32)0x00001000)        </span><span class="comment">/* Interrupt Mask on line 12 */</span>
    2721. 

  2721. <a name="l02689"></a>02689 <span class="preprocessor">#define  EXTI_IMR_MR13                       ((u32)0x00002000)        </span><span class="comment">/* Interrupt Mask on line 13 */</span>
    2722. 

  2722. <a name="l02690"></a>02690 <span class="preprocessor">#define  EXTI_IMR_MR14                       ((u32)0x00004000)        </span><span class="comment">/* Interrupt Mask on line 14 */</span>
    2723. 

  2723. <a name="l02691"></a>02691 <span class="preprocessor">#define  EXTI_IMR_MR15                       ((u32)0x00008000)        </span><span class="comment">/* Interrupt Mask on line 15 */</span>
    2724. 

  2724. <a name="l02692"></a>02692 <span class="preprocessor">#define  EXTI_IMR_MR16                       ((u32)0x00010000)        </span><span class="comment">/* Interrupt Mask on line 16 */</span>
    2725. 

  2725. <a name="l02693"></a>02693 <span class="preprocessor">#define  EXTI_IMR_MR17                       ((u32)0x00020000)        </span><span class="comment">/* Interrupt Mask on line 17 */</span>
    2726. 

  2726. <a name="l02694"></a>02694 <span class="preprocessor">#define  EXTI_IMR_MR18                       ((u32)0x00040000)        </span><span class="comment">/* Interrupt Mask on line 18 */</span>
    2727. 

  2727. <a name="l02695"></a>02695 
    2728. 

  2728. <a name="l02696"></a>02696 
    2729. 

  2729. <a name="l02697"></a>02697 <span class="comment">/*******************  Bit definition for EXTI_EMR register  *******************/</span>
    2730. 

  2730. <a name="l02698"></a>02698 <span class="preprocessor">#define  EXTI_EMR_MR0                        ((u32)0x00000001)        </span><span class="comment">/* Event Mask on line 0 */</span>
    2731. 

  2731. <a name="l02699"></a>02699 <span class="preprocessor">#define  EXTI_EMR_MR1                        ((u32)0x00000002)        </span><span class="comment">/* Event Mask on line 1 */</span>
    2732. 

  2732. <a name="l02700"></a>02700 <span class="preprocessor">#define  EXTI_EMR_MR2                        ((u32)0x00000004)        </span><span class="comment">/* Event Mask on line 2 */</span>
    2733. 

  2733. <a name="l02701"></a>02701 <span class="preprocessor">#define  EXTI_EMR_MR3                        ((u32)0x00000008)        </span><span class="comment">/* Event Mask on line 3 */</span>
    2734. 

  2734. <a name="l02702"></a>02702 <span class="preprocessor">#define  EXTI_EMR_MR4                        ((u32)0x00000010)        </span><span class="comment">/* Event Mask on line 4 */</span>
    2735. 

  2735. <a name="l02703"></a>02703 <span class="preprocessor">#define  EXTI_EMR_MR5                        ((u32)0x00000020)        </span><span class="comment">/* Event Mask on line 5 */</span>
    2736. 

  2736. <a name="l02704"></a>02704 <span class="preprocessor">#define  EXTI_EMR_MR6                        ((u32)0x00000040)        </span><span class="comment">/* Event Mask on line 6 */</span>
    2737. 

  2737. <a name="l02705"></a>02705 <span class="preprocessor">#define  EXTI_EMR_MR7                        ((u32)0x00000080)        </span><span class="comment">/* Event Mask on line 7 */</span>
    2738. 

  2738. <a name="l02706"></a>02706 <span class="preprocessor">#define  EXTI_EMR_MR8                        ((u32)0x00000100)        </span><span class="comment">/* Event Mask on line 8 */</span>
    2739. 

  2739. <a name="l02707"></a>02707 <span class="preprocessor">#define  EXTI_EMR_MR9                        ((u32)0x00000200)        </span><span class="comment">/* Event Mask on line 9 */</span>
    2740. 

  2740. <a name="l02708"></a>02708 <span class="preprocessor">#define  EXTI_EMR_MR10                       ((u32)0x00000400)        </span><span class="comment">/* Event Mask on line 10 */</span>
    2741. 

  2741. <a name="l02709"></a>02709 <span class="preprocessor">#define  EXTI_EMR_MR11                       ((u32)0x00000800)        </span><span class="comment">/* Event Mask on line 11 */</span>
    2742. 

  2742. <a name="l02710"></a>02710 <span class="preprocessor">#define  EXTI_EMR_MR12                       ((u32)0x00001000)        </span><span class="comment">/* Event Mask on line 12 */</span>
    2743. 

  2743. <a name="l02711"></a>02711 <span class="preprocessor">#define  EXTI_EMR_MR13                       ((u32)0x00002000)        </span><span class="comment">/* Event Mask on line 13 */</span>
    2744. 

  2744. <a name="l02712"></a>02712 <span class="preprocessor">#define  EXTI_EMR_MR14                       ((u32)0x00004000)        </span><span class="comment">/* Event Mask on line 14 */</span>
    2745. 

  2745. <a name="l02713"></a>02713 <span class="preprocessor">#define  EXTI_EMR_MR15                       ((u32)0x00008000)        </span><span class="comment">/* Event Mask on line 15 */</span>
    2746. 

  2746. <a name="l02714"></a>02714 <span class="preprocessor">#define  EXTI_EMR_MR16                       ((u32)0x00010000)        </span><span class="comment">/* Event Mask on line 16 */</span>
    2747. 

  2747. <a name="l02715"></a>02715 <span class="preprocessor">#define  EXTI_EMR_MR17                       ((u32)0x00020000)        </span><span class="comment">/* Event Mask on line 17 */</span>
    2748. 

  2748. <a name="l02716"></a>02716 <span class="preprocessor">#define  EXTI_EMR_MR18                       ((u32)0x00040000)        </span><span class="comment">/* Event Mask on line 18 */</span>
    2749. 

  2749. <a name="l02717"></a>02717 
    2750. 

  2750. <a name="l02718"></a>02718 
    2751. 

  2751. <a name="l02719"></a>02719 <span class="comment">/******************  Bit definition for EXTI_RTSR register  *******************/</span>
    2752. 

  2752. <a name="l02720"></a>02720 <span class="preprocessor">#define  EXTI_RTSR_TR0                       ((u32)0x00000001)        </span><span class="comment">/* Rising trigger event configuration bit of line 0 */</span>
    2753. 

  2753. <a name="l02721"></a>02721 <span class="preprocessor">#define  EXTI_RTSR_TR1                       ((u32)0x00000002)        </span><span class="comment">/* Rising trigger event configuration bit of line 1 */</span>
    2754. 

  2754. <a name="l02722"></a>02722 <span class="preprocessor">#define  EXTI_RTSR_TR2                       ((u32)0x00000004)        </span><span class="comment">/* Rising trigger event configuration bit of line 2 */</span>
    2755. 

  2755. <a name="l02723"></a>02723 <span class="preprocessor">#define  EXTI_RTSR_TR3                       ((u32)0x00000008)        </span><span class="comment">/* Rising trigger event configuration bit of line 3 */</span>
    2756. 

  2756. <a name="l02724"></a>02724 <span class="preprocessor">#define  EXTI_RTSR_TR4                       ((u32)0x00000010)        </span><span class="comment">/* Rising trigger event configuration bit of line 4 */</span>
    2757. 

  2757. <a name="l02725"></a>02725 <span class="preprocessor">#define  EXTI_RTSR_TR5                       ((u32)0x00000020)        </span><span class="comment">/* Rising trigger event configuration bit of line 5 */</span>
    2758. 

  2758. <a name="l02726"></a>02726 <span class="preprocessor">#define  EXTI_RTSR_TR6                       ((u32)0x00000040)        </span><span class="comment">/* Rising trigger event configuration bit of line 6 */</span>
    2759. 

  2759. <a name="l02727"></a>02727 <span class="preprocessor">#define  EXTI_RTSR_TR7                       ((u32)0x00000080)        </span><span class="comment">/* Rising trigger event configuration bit of line 7 */</span>
    2760. 

  2760. <a name="l02728"></a>02728 <span class="preprocessor">#define  EXTI_RTSR_TR8                       ((u32)0x00000100)        </span><span class="comment">/* Rising trigger event configuration bit of line 8 */</span>
    2761. 

  2761. <a name="l02729"></a>02729 <span class="preprocessor">#define  EXTI_RTSR_TR9                       ((u32)0x00000200)        </span><span class="comment">/* Rising trigger event configuration bit of line 9 */</span>
    2762. 

  2762. <a name="l02730"></a>02730 <span class="preprocessor">#define  EXTI_RTSR_TR10                      ((u32)0x00000400)        </span><span class="comment">/* Rising trigger event configuration bit of line 10 */</span>
    2763. 

  2763. <a name="l02731"></a>02731 <span class="preprocessor">#define  EXTI_RTSR_TR11                      ((u32)0x00000800)        </span><span class="comment">/* Rising trigger event configuration bit of line 11 */</span>
    2764. 

  2764. <a name="l02732"></a>02732 <span class="preprocessor">#define  EXTI_RTSR_TR12                      ((u32)0x00001000)        </span><span class="comment">/* Rising trigger event configuration bit of line 12 */</span>
    2765. 

  2765. <a name="l02733"></a>02733 <span class="preprocessor">#define  EXTI_RTSR_TR13                      ((u32)0x00002000)        </span><span class="comment">/* Rising trigger event configuration bit of line 13 */</span>
    2766. 

  2766. <a name="l02734"></a>02734 <span class="preprocessor">#define  EXTI_RTSR_TR14                      ((u32)0x00004000)        </span><span class="comment">/* Rising trigger event configuration bit of line 14 */</span>
    2767. 

  2767. <a name="l02735"></a>02735 <span class="preprocessor">#define  EXTI_RTSR_TR15                      ((u32)0x00008000)        </span><span class="comment">/* Rising trigger event configuration bit of line 15 */</span>
    2768. 

  2768. <a name="l02736"></a>02736 <span class="preprocessor">#define  EXTI_RTSR_TR16                      ((u32)0x00010000)        </span><span class="comment">/* Rising trigger event configuration bit of line 16 */</span>
    2769. 

  2769. <a name="l02737"></a>02737 <span class="preprocessor">#define  EXTI_RTSR_TR17                      ((u32)0x00020000)        </span><span class="comment">/* Rising trigger event configuration bit of line 17 */</span>
    2770. 

  2770. <a name="l02738"></a>02738 <span class="preprocessor">#define  EXTI_RTSR_TR18                      ((u32)0x00040000)        </span><span class="comment">/* Rising trigger event configuration bit of line 18 */</span>
    2771. 

  2771. <a name="l02739"></a>02739 
    2772. 

  2772. <a name="l02740"></a>02740 
    2773. 

  2773. <a name="l02741"></a>02741 <span class="comment">/******************  Bit definition for EXTI_FTSR register  *******************/</span>
    2774. 

  2774. <a name="l02742"></a>02742 <span class="preprocessor">#define  EXTI_FTSR_TR0                       ((u32)0x00000001)        </span><span class="comment">/* Falling trigger event configuration bit of line 0 */</span>
    2775. 

  2775. <a name="l02743"></a>02743 <span class="preprocessor">#define  EXTI_FTSR_TR1                       ((u32)0x00000002)        </span><span class="comment">/* Falling trigger event configuration bit of line 1 */</span>
    2776. 

  2776. <a name="l02744"></a>02744 <span class="preprocessor">#define  EXTI_FTSR_TR2                       ((u32)0x00000004)        </span><span class="comment">/* Falling trigger event configuration bit of line 2 */</span>
    2777. 

  2777. <a name="l02745"></a>02745 <span class="preprocessor">#define  EXTI_FTSR_TR3                       ((u32)0x00000008)        </span><span class="comment">/* Falling trigger event configuration bit of line 3 */</span>
    2778. 

  2778. <a name="l02746"></a>02746 <span class="preprocessor">#define  EXTI_FTSR_TR4                       ((u32)0x00000010)        </span><span class="comment">/* Falling trigger event configuration bit of line 4 */</span>
    2779. 

  2779. <a name="l02747"></a>02747 <span class="preprocessor">#define  EXTI_FTSR_TR5                       ((u32)0x00000020)        </span><span class="comment">/* Falling trigger event configuration bit of line 5 */</span>
    2780. 

  2780. <a name="l02748"></a>02748 <span class="preprocessor">#define  EXTI_FTSR_TR6                       ((u32)0x00000040)        </span><span class="comment">/* Falling trigger event configuration bit of line 6 */</span>
    2781. 

  2781. <a name="l02749"></a>02749 <span class="preprocessor">#define  EXTI_FTSR_TR7                       ((u32)0x00000080)        </span><span class="comment">/* Falling trigger event configuration bit of line 7 */</span>
    2782. 

  2782. <a name="l02750"></a>02750 <span class="preprocessor">#define  EXTI_FTSR_TR8                       ((u32)0x00000100)        </span><span class="comment">/* Falling trigger event configuration bit of line 8 */</span>
    2783. 

  2783. <a name="l02751"></a>02751 <span class="preprocessor">#define  EXTI_FTSR_TR9                       ((u32)0x00000200)        </span><span class="comment">/* Falling trigger event configuration bit of line 9 */</span>
    2784. 

  2784. <a name="l02752"></a>02752 <span class="preprocessor">#define  EXTI_FTSR_TR10                      ((u32)0x00000400)        </span><span class="comment">/* Falling trigger event configuration bit of line 10 */</span>
    2785. 

  2785. <a name="l02753"></a>02753 <span class="preprocessor">#define  EXTI_FTSR_TR11                      ((u32)0x00000800)        </span><span class="comment">/* Falling trigger event configuration bit of line 11 */</span>
    2786. 

  2786. <a name="l02754"></a>02754 <span class="preprocessor">#define  EXTI_FTSR_TR12                      ((u32)0x00001000)        </span><span class="comment">/* Falling trigger event configuration bit of line 12 */</span>
    2787. 

  2787. <a name="l02755"></a>02755 <span class="preprocessor">#define  EXTI_FTSR_TR13                      ((u32)0x00002000)        </span><span class="comment">/* Falling trigger event configuration bit of line 13 */</span>
    2788. 

  2788. <a name="l02756"></a>02756 <span class="preprocessor">#define  EXTI_FTSR_TR14                      ((u32)0x00004000)        </span><span class="comment">/* Falling trigger event configuration bit of line 14 */</span>
    2789. 

  2789. <a name="l02757"></a>02757 <span class="preprocessor">#define  EXTI_FTSR_TR15                      ((u32)0x00008000)        </span><span class="comment">/* Falling trigger event configuration bit of line 15 */</span>
    2790. 

  2790. <a name="l02758"></a>02758 <span class="preprocessor">#define  EXTI_FTSR_TR16                      ((u32)0x00010000)        </span><span class="comment">/* Falling trigger event configuration bit of line 16 */</span>
    2791. 

  2791. <a name="l02759"></a>02759 <span class="preprocessor">#define  EXTI_FTSR_TR17                      ((u32)0x00020000)        </span><span class="comment">/* Falling trigger event configuration bit of line 17 */</span>
    2792. 

  2792. <a name="l02760"></a>02760 <span class="preprocessor">#define  EXTI_FTSR_TR18                      ((u32)0x00040000)        </span><span class="comment">/* Falling trigger event configuration bit of line 18 */</span>
    2793. 

  2793. <a name="l02761"></a>02761 
    2794. 

  2794. <a name="l02762"></a>02762 
    2795. 

  2795. <a name="l02763"></a>02763 <span class="comment">/******************  Bit definition for EXTI_SWIER register  ******************/</span>
    2796. 

  2796. <a name="l02764"></a>02764 <span class="preprocessor">#define  EXTI_SWIER_SWIER0                   ((u32)0x00000001)        </span><span class="comment">/* Software Interrupt on line 0 */</span>
    2797. 

  2797. <a name="l02765"></a>02765 <span class="preprocessor">#define  EXTI_SWIER_SWIER1                   ((u32)0x00000002)        </span><span class="comment">/* Software Interrupt on line 1 */</span>
    2798. 

  2798. <a name="l02766"></a>02766 <span class="preprocessor">#define  EXTI_SWIER_SWIER2                   ((u32)0x00000004)        </span><span class="comment">/* Software Interrupt on line 2 */</span>
    2799. 

  2799. <a name="l02767"></a>02767 <span class="preprocessor">#define  EXTI_SWIER_SWIER3                   ((u32)0x00000008)        </span><span class="comment">/* Software Interrupt on line 3 */</span>
    2800. 

  2800. <a name="l02768"></a>02768 <span class="preprocessor">#define  EXTI_SWIER_SWIER4                   ((u32)0x00000010)        </span><span class="comment">/* Software Interrupt on line 4 */</span>
    2801. 

  2801. <a name="l02769"></a>02769 <span class="preprocessor">#define  EXTI_SWIER_SWIER5                   ((u32)0x00000020)        </span><span class="comment">/* Software Interrupt on line 5 */</span>
    2802. 

  2802. <a name="l02770"></a>02770 <span class="preprocessor">#define  EXTI_SWIER_SWIER6                   ((u32)0x00000040)        </span><span class="comment">/* Software Interrupt on line 6 */</span>
    2803. 

  2803. <a name="l02771"></a>02771 <span class="preprocessor">#define  EXTI_SWIER_SWIER7                   ((u32)0x00000080)        </span><span class="comment">/* Software Interrupt on line 7 */</span>
    2804. 

  2804. <a name="l02772"></a>02772 <span class="preprocessor">#define  EXTI_SWIER_SWIER8                   ((u32)0x00000100)        </span><span class="comment">/* Software Interrupt on line 8 */</span>
    2805. 

  2805. <a name="l02773"></a>02773 <span class="preprocessor">#define  EXTI_SWIER_SWIER9                   ((u32)0x00000200)        </span><span class="comment">/* Software Interrupt on line 9 */</span>
    2806. 

  2806. <a name="l02774"></a>02774 <span class="preprocessor">#define  EXTI_SWIER_SWIER10                  ((u32)0x00000400)        </span><span class="comment">/* Software Interrupt on line 10 */</span>
    2807. 

  2807. <a name="l02775"></a>02775 <span class="preprocessor">#define  EXTI_SWIER_SWIER11                  ((u32)0x00000800)        </span><span class="comment">/* Software Interrupt on line 11 */</span>
    2808. 

  2808. <a name="l02776"></a>02776 <span class="preprocessor">#define  EXTI_SWIER_SWIER12                  ((u32)0x00001000)        </span><span class="comment">/* Software Interrupt on line 12 */</span>
    2809. 

  2809. <a name="l02777"></a>02777 <span class="preprocessor">#define  EXTI_SWIER_SWIER13                  ((u32)0x00002000)        </span><span class="comment">/* Software Interrupt on line 13 */</span>
    2810. 

  2810. <a name="l02778"></a>02778 <span class="preprocessor">#define  EXTI_SWIER_SWIER14                  ((u32)0x00004000)        </span><span class="comment">/* Software Interrupt on line 14 */</span>
    2811. 

  2811. <a name="l02779"></a>02779 <span class="preprocessor">#define  EXTI_SWIER_SWIER15                  ((u32)0x00008000)        </span><span class="comment">/* Software Interrupt on line 15 */</span>
    2812. 

  2812. <a name="l02780"></a>02780 <span class="preprocessor">#define  EXTI_SWIER_SWIER16                  ((u32)0x00010000)        </span><span class="comment">/* Software Interrupt on line 16 */</span>
    2813. 

  2813. <a name="l02781"></a>02781 <span class="preprocessor">#define  EXTI_SWIER_SWIER17                  ((u32)0x00020000)        </span><span class="comment">/* Software Interrupt on line 17 */</span>
    2814. 

  2814. <a name="l02782"></a>02782 <span class="preprocessor">#define  EXTI_SWIER_SWIER18                  ((u32)0x00040000)        </span><span class="comment">/* Software Interrupt on line 18 */</span>
    2815. 

  2815. <a name="l02783"></a>02783 
    2816. 

  2816. <a name="l02784"></a>02784 
    2817. 

  2817. <a name="l02785"></a>02785 <span class="comment">/*******************  Bit definition for EXTI_PR register  ********************/</span>
    2818. 

  2818. <a name="l02786"></a>02786 <span class="preprocessor">#define  EXTI_PR_PR0                         ((u32)0x00000001)        </span><span class="comment">/* Pending bit 0 */</span>
    2819. 

  2819. <a name="l02787"></a>02787 <span class="preprocessor">#define  EXTI_PR_PR1                         ((u32)0x00000002)        </span><span class="comment">/* Pending bit 1 */</span>
    2820. 

  2820. <a name="l02788"></a>02788 <span class="preprocessor">#define  EXTI_PR_PR2                         ((u32)0x00000004)        </span><span class="comment">/* Pending bit 2 */</span>
    2821. 

  2821. <a name="l02789"></a>02789 <span class="preprocessor">#define  EXTI_PR_PR3                         ((u32)0x00000008)        </span><span class="comment">/* Pending bit 3 */</span>
    2822. 

  2822. <a name="l02790"></a>02790 <span class="preprocessor">#define  EXTI_PR_PR4                         ((u32)0x00000010)        </span><span class="comment">/* Pending bit 4 */</span>
    2823. 

  2823. <a name="l02791"></a>02791 <span class="preprocessor">#define  EXTI_PR_PR5                         ((u32)0x00000020)        </span><span class="comment">/* Pending bit 5 */</span>
    2824. 

  2824. <a name="l02792"></a>02792 <span class="preprocessor">#define  EXTI_PR_PR6                         ((u32)0x00000040)        </span><span class="comment">/* Pending bit 6 */</span>
    2825. 

  2825. <a name="l02793"></a>02793 <span class="preprocessor">#define  EXTI_PR_PR7                         ((u32)0x00000080)        </span><span class="comment">/* Pending bit 7 */</span>
    2826. 

  2826. <a name="l02794"></a>02794 <span class="preprocessor">#define  EXTI_PR_PR8                         ((u32)0x00000100)        </span><span class="comment">/* Pending bit 8 */</span>
    2827. 

  2827. <a name="l02795"></a>02795 <span class="preprocessor">#define  EXTI_PR_PR9                         ((u32)0x00000200)        </span><span class="comment">/* Pending bit 9 */</span>
    2828. 

  2828. <a name="l02796"></a>02796 <span class="preprocessor">#define  EXTI_PR_PR10                        ((u32)0x00000400)        </span><span class="comment">/* Pending bit 10 */</span>
    2829. 

  2829. <a name="l02797"></a>02797 <span class="preprocessor">#define  EXTI_PR_PR11                        ((u32)0x00000800)        </span><span class="comment">/* Pending bit 11 */</span>
    2830. 

  2830. <a name="l02798"></a>02798 <span class="preprocessor">#define  EXTI_PR_PR12                        ((u32)0x00001000)        </span><span class="comment">/* Pending bit 12 */</span>
    2831. 

  2831. <a name="l02799"></a>02799 <span class="preprocessor">#define  EXTI_PR_PR13                        ((u32)0x00002000)        </span><span class="comment">/* Pending bit 13 */</span>
    2832. 

  2832. <a name="l02800"></a>02800 <span class="preprocessor">#define  EXTI_PR_PR14                        ((u32)0x00004000)        </span><span class="comment">/* Pending bit 14 */</span>
    2833. 

  2833. <a name="l02801"></a>02801 <span class="preprocessor">#define  EXTI_PR_PR15                        ((u32)0x00008000)        </span><span class="comment">/* Pending bit 15 */</span>
    2834. 

  2834. <a name="l02802"></a>02802 <span class="preprocessor">#define  EXTI_PR_PR16                        ((u32)0x00010000)        </span><span class="comment">/* Pending bit 16 */</span>
    2835. 

  2835. <a name="l02803"></a>02803 <span class="preprocessor">#define  EXTI_PR_PR17                        ((u32)0x00020000)        </span><span class="comment">/* Pending bit 17 */</span>
    2836. 

  2836. <a name="l02804"></a>02804 <span class="preprocessor">#define  EXTI_PR_PR18                        ((u32)0x00040000)        </span><span class="comment">/* Trigger request occurred on the external interrupt line 18 */</span>
    2837. 

  2837. <a name="l02805"></a>02805 
    2838. 

  2838. <a name="l02806"></a>02806 
    2839. 

  2839. <a name="l02807"></a>02807 
    2840. 

  2840. <a name="l02808"></a>02808 <span class="comment">/******************************************************************************/</span>
    2841. 

  2841. <a name="l02809"></a>02809 <span class="comment">/*                                                                            */</span>
    2842. 

  2842. <a name="l02810"></a>02810 <span class="comment">/*                             DMA Controller                                 */</span>
    2843. 

  2843. <a name="l02811"></a>02811 <span class="comment">/*                                                                            */</span>
    2844. 

  2844. <a name="l02812"></a>02812 <span class="comment">/******************************************************************************/</span>
    2845. 

  2845. <a name="l02813"></a>02813 
    2846. 

  2846. <a name="l02814"></a>02814 <span class="comment">/*******************  Bit definition for DMA_ISR register  ********************/</span>
    2847. 

  2847. <a name="l02815"></a>02815 <span class="preprocessor">#define  DMA_ISR_GIF1                        ((u32)0x00000001)        </span><span class="comment">/* Channel 1 Global interrupt flag */</span>
    2848. 

  2848. <a name="l02816"></a>02816 <span class="preprocessor">#define  DMA_ISR_TCIF1                       ((u32)0x00000002)        </span><span class="comment">/* Channel 1 Transfer Complete flag */</span>
    2849. 

  2849. <a name="l02817"></a>02817 <span class="preprocessor">#define  DMA_ISR_HTIF1                       ((u32)0x00000004)        </span><span class="comment">/* Channel 1 Half Transfer flag */</span>
    2850. 

  2850. <a name="l02818"></a>02818 <span class="preprocessor">#define  DMA_ISR_TEIF1                       ((u32)0x00000008)        </span><span class="comment">/* Channel 1 Transfer Error flag */</span>
    2851. 

  2851. <a name="l02819"></a>02819 <span class="preprocessor">#define  DMA_ISR_GIF2                        ((u32)0x00000010)        </span><span class="comment">/* Channel 2 Global interrupt flag */</span>
    2852. 

  2852. <a name="l02820"></a>02820 <span class="preprocessor">#define  DMA_ISR_TCIF2                       ((u32)0x00000020)        </span><span class="comment">/* Channel 2 Transfer Complete flag */</span>
    2853. 

  2853. <a name="l02821"></a>02821 <span class="preprocessor">#define  DMA_ISR_HTIF2                       ((u32)0x00000040)        </span><span class="comment">/* Channel 2 Half Transfer flag */</span>
    2854. 

  2854. <a name="l02822"></a>02822 <span class="preprocessor">#define  DMA_ISR_TEIF2                       ((u32)0x00000080)        </span><span class="comment">/* Channel 2 Transfer Error flag */</span>
    2855. 

  2855. <a name="l02823"></a>02823 <span class="preprocessor">#define  DMA_ISR_GIF3                        ((u32)0x00000100)        </span><span class="comment">/* Channel 3 Global interrupt flag */</span>
    2856. 

  2856. <a name="l02824"></a>02824 <span class="preprocessor">#define  DMA_ISR_TCIF3                       ((u32)0x00000200)        </span><span class="comment">/* Channel 3 Transfer Complete flag */</span>
    2857. 

  2857. <a name="l02825"></a>02825 <span class="preprocessor">#define  DMA_ISR_HTIF3                       ((u32)0x00000400)        </span><span class="comment">/* Channel 3 Half Transfer flag */</span>
    2858. 

  2858. <a name="l02826"></a>02826 <span class="preprocessor">#define  DMA_ISR_TEIF3                       ((u32)0x00000800)        </span><span class="comment">/* Channel 3 Transfer Error flag */</span>
    2859. 

  2859. <a name="l02827"></a>02827 <span class="preprocessor">#define  DMA_ISR_GIF4                        ((u32)0x00001000)        </span><span class="comment">/* Channel 4 Global interrupt flag */</span>
    2860. 

  2860. <a name="l02828"></a>02828 <span class="preprocessor">#define  DMA_ISR_TCIF4                       ((u32)0x00002000)        </span><span class="comment">/* Channel 4 Transfer Complete flag */</span>
    2861. 

  2861. <a name="l02829"></a>02829 <span class="preprocessor">#define  DMA_ISR_HTIF4                       ((u32)0x00004000)        </span><span class="comment">/* Channel 4 Half Transfer flag */</span>
    2862. 

  2862. <a name="l02830"></a>02830 <span class="preprocessor">#define  DMA_ISR_TEIF4                       ((u32)0x00008000)        </span><span class="comment">/* Channel 4 Transfer Error flag */</span>
    2863. 

  2863. <a name="l02831"></a>02831 <span class="preprocessor">#define  DMA_ISR_GIF5                        ((u32)0x00010000)        </span><span class="comment">/* Channel 5 Global interrupt flag */</span>
    2864. 

  2864. <a name="l02832"></a>02832 <span class="preprocessor">#define  DMA_ISR_TCIF5                       ((u32)0x00020000)        </span><span class="comment">/* Channel 5 Transfer Complete flag */</span>
    2865. 

  2865. <a name="l02833"></a>02833 <span class="preprocessor">#define  DMA_ISR_HTIF5                       ((u32)0x00040000)        </span><span class="comment">/* Channel 5 Half Transfer flag */</span>
    2866. 

  2866. <a name="l02834"></a>02834 <span class="preprocessor">#define  DMA_ISR_TEIF5                       ((u32)0x00080000)        </span><span class="comment">/* Channel 5 Transfer Error flag */</span>
    2867. 

  2867. <a name="l02835"></a>02835 <span class="preprocessor">#define  DMA_ISR_GIF6                        ((u32)0x00100000)        </span><span class="comment">/* Channel 6 Global interrupt flag */</span>
    2868. 

  2868. <a name="l02836"></a>02836 <span class="preprocessor">#define  DMA_ISR_TCIF6                       ((u32)0x00200000)        </span><span class="comment">/* Channel 6 Transfer Complete flag */</span>
    2869. 

  2869. <a name="l02837"></a>02837 <span class="preprocessor">#define  DMA_ISR_HTIF6                       ((u32)0x00400000)        </span><span class="comment">/* Channel 6 Half Transfer flag */</span>
    2870. 

  2870. <a name="l02838"></a>02838 <span class="preprocessor">#define  DMA_ISR_TEIF6                       ((u32)0x00800000)        </span><span class="comment">/* Channel 6 Transfer Error flag */</span>
    2871. 

  2871. <a name="l02839"></a>02839 <span class="preprocessor">#define  DMA_ISR_GIF7                        ((u32)0x01000000)        </span><span class="comment">/* Channel 7 Global interrupt flag */</span>
    2872. 

  2872. <a name="l02840"></a>02840 <span class="preprocessor">#define  DMA_ISR_TCIF7                       ((u32)0x02000000)        </span><span class="comment">/* Channel 7 Transfer Complete flag */</span>
    2873. 

  2873. <a name="l02841"></a>02841 <span class="preprocessor">#define  DMA_ISR_HTIF7                       ((u32)0x04000000)        </span><span class="comment">/* Channel 7 Half Transfer flag */</span>
    2874. 

  2874. <a name="l02842"></a>02842 <span class="preprocessor">#define  DMA_ISR_TEIF7                       ((u32)0x08000000)        </span><span class="comment">/* Channel 7 Transfer Error flag */</span>
    2875. 

  2875. <a name="l02843"></a>02843 
    2876. 

  2876. <a name="l02844"></a>02844 
    2877. 

  2877. <a name="l02845"></a>02845 <span class="comment">/*******************  Bit definition for DMA_IFCR register  *******************/</span>
    2878. 

  2878. <a name="l02846"></a>02846 <span class="preprocessor">#define  DMA_IFCR_CGIF1                      ((u32)0x00000001)        </span><span class="comment">/* Channel 1 Global interrupt clearr */</span>
    2879. 

  2879. <a name="l02847"></a>02847 <span class="preprocessor">#define  DMA_IFCR_CTCIF1                     ((u32)0x00000002)        </span><span class="comment">/* Channel 1 Transfer Complete clear */</span>
    2880. 

  2880. <a name="l02848"></a>02848 <span class="preprocessor">#define  DMA_IFCR_CHTIF1                     ((u32)0x00000004)        </span><span class="comment">/* Channel 1 Half Transfer clear */</span>
    2881. 

  2881. <a name="l02849"></a>02849 <span class="preprocessor">#define  DMA_IFCR_CTEIF1                     ((u32)0x00000008)        </span><span class="comment">/* Channel 1 Transfer Error clear */</span>
    2882. 

  2882. <a name="l02850"></a>02850 <span class="preprocessor">#define  DMA_IFCR_CGIF2                      ((u32)0x00000010)        </span><span class="comment">/* Channel 2 Global interrupt clear */</span>
    2883. 

  2883. <a name="l02851"></a>02851 <span class="preprocessor">#define  DMA_IFCR_CTCIF2                     ((u32)0x00000020)        </span><span class="comment">/* Channel 2 Transfer Complete clear */</span>
    2884. 

  2884. <a name="l02852"></a>02852 <span class="preprocessor">#define  DMA_IFCR_CHTIF2                     ((u32)0x00000040)        </span><span class="comment">/* Channel 2 Half Transfer clear */</span>
    2885. 

  2885. <a name="l02853"></a>02853 <span class="preprocessor">#define  DMA_IFCR_CTEIF2                     ((u32)0x00000080)        </span><span class="comment">/* Channel 2 Transfer Error clear */</span>
    2886. 

  2886. <a name="l02854"></a>02854 <span class="preprocessor">#define  DMA_IFCR_CGIF3                      ((u32)0x00000100)        </span><span class="comment">/* Channel 3 Global interrupt clear */</span>
    2887. 

  2887. <a name="l02855"></a>02855 <span class="preprocessor">#define  DMA_IFCR_CTCIF3                     ((u32)0x00000200)        </span><span class="comment">/* Channel 3 Transfer Complete clear */</span>
    2888. 

  2888. <a name="l02856"></a>02856 <span class="preprocessor">#define  DMA_IFCR_CHTIF3                     ((u32)0x00000400)        </span><span class="comment">/* Channel 3 Half Transfer clear */</span>
    2889. 

  2889. <a name="l02857"></a>02857 <span class="preprocessor">#define  DMA_IFCR_CTEIF3                     ((u32)0x00000800)        </span><span class="comment">/* Channel 3 Transfer Error clear */</span>
    2890. 

  2890. <a name="l02858"></a>02858 <span class="preprocessor">#define  DMA_IFCR_CGIF4                      ((u32)0x00001000)        </span><span class="comment">/* Channel 4 Global interrupt clear */</span>
    2891. 

  2891. <a name="l02859"></a>02859 <span class="preprocessor">#define  DMA_IFCR_CTCIF4                     ((u32)0x00002000)        </span><span class="comment">/* Channel 4 Transfer Complete clear */</span>
    2892. 

  2892. <a name="l02860"></a>02860 <span class="preprocessor">#define  DMA_IFCR_CHTIF4                     ((u32)0x00004000)        </span><span class="comment">/* Channel 4 Half Transfer clear */</span>
    2893. 

  2893. <a name="l02861"></a>02861 <span class="preprocessor">#define  DMA_IFCR_CTEIF4                     ((u32)0x00008000)        </span><span class="comment">/* Channel 4 Transfer Error clear */</span>
    2894. 

  2894. <a name="l02862"></a>02862 <span class="preprocessor">#define  DMA_IFCR_CGIF5                      ((u32)0x00010000)        </span><span class="comment">/* Channel 5 Global interrupt clear */</span>
    2895. 

  2895. <a name="l02863"></a>02863 <span class="preprocessor">#define  DMA_IFCR_CTCIF5                     ((u32)0x00020000)        </span><span class="comment">/* Channel 5 Transfer Complete clear */</span>
    2896. 

  2896. <a name="l02864"></a>02864 <span class="preprocessor">#define  DMA_IFCR_CHTIF5                     ((u32)0x00040000)        </span><span class="comment">/* Channel 5 Half Transfer clear */</span>
    2897. 

  2897. <a name="l02865"></a>02865 <span class="preprocessor">#define  DMA_IFCR_CTEIF5                     ((u32)0x00080000)        </span><span class="comment">/* Channel 5 Transfer Error clear */</span>
    2898. 

  2898. <a name="l02866"></a>02866 <span class="preprocessor">#define  DMA_IFCR_CGIF6                      ((u32)0x00100000)        </span><span class="comment">/* Channel 6 Global interrupt clear */</span>
    2899. 

  2899. <a name="l02867"></a>02867 <span class="preprocessor">#define  DMA_IFCR_CTCIF6                     ((u32)0x00200000)        </span><span class="comment">/* Channel 6 Transfer Complete clear */</span>
    2900. 

  2900. <a name="l02868"></a>02868 <span class="preprocessor">#define  DMA_IFCR_CHTIF6                     ((u32)0x00400000)        </span><span class="comment">/* Channel 6 Half Transfer clear */</span>
    2901. 

  2901. <a name="l02869"></a>02869 <span class="preprocessor">#define  DMA_IFCR_CTEIF6                     ((u32)0x00800000)        </span><span class="comment">/* Channel 6 Transfer Error clear */</span>
    2902. 

  2902. <a name="l02870"></a>02870 <span class="preprocessor">#define  DMA_IFCR_CGIF7                      ((u32)0x01000000)        </span><span class="comment">/* Channel 7 Global interrupt clear */</span>
    2903. 

  2903. <a name="l02871"></a>02871 <span class="preprocessor">#define  DMA_IFCR_CTCIF7                     ((u32)0x02000000)        </span><span class="comment">/* Channel 7 Transfer Complete clear */</span>
    2904. 

  2904. <a name="l02872"></a>02872 <span class="preprocessor">#define  DMA_IFCR_CHTIF7                     ((u32)0x04000000)        </span><span class="comment">/* Channel 7 Half Transfer clear */</span>
    2905. 

  2905. <a name="l02873"></a>02873 <span class="preprocessor">#define  DMA_IFCR_CTEIF7                     ((u32)0x08000000)        </span><span class="comment">/* Channel 7 Transfer Error clear */</span>
    2906. 

  2906. <a name="l02874"></a>02874 
    2907. 

  2907. <a name="l02875"></a>02875 
    2908. 

  2908. <a name="l02876"></a>02876 <span class="comment">/*******************  Bit definition for DMA_CCR1 register  *******************/</span>
    2909. 

  2909. <a name="l02877"></a>02877 <span class="preprocessor">#define  DMA_CCR1_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable*/</span>
    2910. 

  2910. <a name="l02878"></a>02878 <span class="preprocessor">#define  DMA_CCR1_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    2911. 

  2911. <a name="l02879"></a>02879 <span class="preprocessor">#define  DMA_CCR1_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    2912. 

  2912. <a name="l02880"></a>02880 <span class="preprocessor">#define  DMA_CCR1_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    2913. 

  2913. <a name="l02881"></a>02881 <span class="preprocessor">#define  DMA_CCR1_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    2914. 

  2914. <a name="l02882"></a>02882 <span class="preprocessor">#define  DMA_CCR1_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    2915. 

  2915. <a name="l02883"></a>02883 <span class="preprocessor">#define  DMA_CCR1_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    2916. 

  2916. <a name="l02884"></a>02884 <span class="preprocessor">#define  DMA_CCR1_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    2917. 

  2917. <a name="l02885"></a>02885 
    2918. 

  2918. <a name="l02886"></a>02886 <span class="preprocessor">#define  DMA_CCR1_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    2919. 

  2919. <a name="l02887"></a>02887 <span class="preprocessor">#define  DMA_CCR1_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    2920. 

  2920. <a name="l02888"></a>02888 <span class="preprocessor">#define  DMA_CCR1_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    2921. 

  2921. <a name="l02889"></a>02889 
    2922. 

  2922. <a name="l02890"></a>02890 <span class="preprocessor">#define  DMA_CCR1_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    2923. 

  2923. <a name="l02891"></a>02891 <span class="preprocessor">#define  DMA_CCR1_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    2924. 

  2924. <a name="l02892"></a>02892 <span class="preprocessor">#define  DMA_CCR1_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    2925. 

  2925. <a name="l02893"></a>02893 
    2926. 

  2926. <a name="l02894"></a>02894 <span class="preprocessor">#define  DMA_CCR1_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits(Channel Priority level) */</span>
    2927. 

  2927. <a name="l02895"></a>02895 <span class="preprocessor">#define  DMA_CCR1_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    2928. 

  2928. <a name="l02896"></a>02896 <span class="preprocessor">#define  DMA_CCR1_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    2929. 

  2929. <a name="l02897"></a>02897 
    2930. 

  2930. <a name="l02898"></a>02898 <span class="preprocessor">#define  DMA_CCR1_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode */</span>
    2931. 

  2931. <a name="l02899"></a>02899 
    2932. 

  2932. <a name="l02900"></a>02900 
    2933. 

  2933. <a name="l02901"></a>02901 <span class="comment">/*******************  Bit definition for DMA_CCR2 register  *******************/</span>
    2934. 

  2934. <a name="l02902"></a>02902 <span class="preprocessor">#define  DMA_CCR2_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    2935. 

  2935. <a name="l02903"></a>02903 <span class="preprocessor">#define  DMA_CCR2_TCIE                       ((u16)0x0002)            </span><span class="comment">/* ransfer complete interrupt enable */</span>
    2936. 

  2936. <a name="l02904"></a>02904 <span class="preprocessor">#define  DMA_CCR2_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    2937. 

  2937. <a name="l02905"></a>02905 <span class="preprocessor">#define  DMA_CCR2_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    2938. 

  2938. <a name="l02906"></a>02906 <span class="preprocessor">#define  DMA_CCR2_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    2939. 

  2939. <a name="l02907"></a>02907 <span class="preprocessor">#define  DMA_CCR2_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    2940. 

  2940. <a name="l02908"></a>02908 <span class="preprocessor">#define  DMA_CCR2_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    2941. 

  2941. <a name="l02909"></a>02909 <span class="preprocessor">#define  DMA_CCR2_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    2942. 

  2942. <a name="l02910"></a>02910 
    2943. 

  2943. <a name="l02911"></a>02911 <span class="preprocessor">#define  DMA_CCR2_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    2944. 

  2944. <a name="l02912"></a>02912 <span class="preprocessor">#define  DMA_CCR2_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    2945. 

  2945. <a name="l02913"></a>02913 <span class="preprocessor">#define  DMA_CCR2_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    2946. 

  2946. <a name="l02914"></a>02914 
    2947. 

  2947. <a name="l02915"></a>02915 <span class="preprocessor">#define  DMA_CCR2_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    2948. 

  2948. <a name="l02916"></a>02916 <span class="preprocessor">#define  DMA_CCR2_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    2949. 

  2949. <a name="l02917"></a>02917 <span class="preprocessor">#define  DMA_CCR2_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    2950. 

  2950. <a name="l02918"></a>02918 
    2951. 

  2951. <a name="l02919"></a>02919 <span class="preprocessor">#define  DMA_CCR2_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    2952. 

  2952. <a name="l02920"></a>02920 <span class="preprocessor">#define  DMA_CCR2_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    2953. 

  2953. <a name="l02921"></a>02921 <span class="preprocessor">#define  DMA_CCR2_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    2954. 

  2954. <a name="l02922"></a>02922 
    2955. 

  2955. <a name="l02923"></a>02923 <span class="preprocessor">#define  DMA_CCR2_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode */</span>
    2956. 

  2956. <a name="l02924"></a>02924 
    2957. 

  2957. <a name="l02925"></a>02925 
    2958. 

  2958. <a name="l02926"></a>02926 <span class="comment">/*******************  Bit definition for DMA_CCR3 register  *******************/</span>
    2959. 

  2959. <a name="l02927"></a>02927 <span class="preprocessor">#define  DMA_CCR3_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    2960. 

  2960. <a name="l02928"></a>02928 <span class="preprocessor">#define  DMA_CCR3_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    2961. 

  2961. <a name="l02929"></a>02929 <span class="preprocessor">#define  DMA_CCR3_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    2962. 

  2962. <a name="l02930"></a>02930 <span class="preprocessor">#define  DMA_CCR3_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    2963. 

  2963. <a name="l02931"></a>02931 <span class="preprocessor">#define  DMA_CCR3_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    2964. 

  2964. <a name="l02932"></a>02932 <span class="preprocessor">#define  DMA_CCR3_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    2965. 

  2965. <a name="l02933"></a>02933 <span class="preprocessor">#define  DMA_CCR3_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    2966. 

  2966. <a name="l02934"></a>02934 <span class="preprocessor">#define  DMA_CCR3_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    2967. 

  2967. <a name="l02935"></a>02935 
    2968. 

  2968. <a name="l02936"></a>02936 <span class="preprocessor">#define  DMA_CCR3_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    2969. 

  2969. <a name="l02937"></a>02937 <span class="preprocessor">#define  DMA_CCR3_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    2970. 

  2970. <a name="l02938"></a>02938 <span class="preprocessor">#define  DMA_CCR3_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    2971. 

  2971. <a name="l02939"></a>02939 
    2972. 

  2972. <a name="l02940"></a>02940 <span class="preprocessor">#define  DMA_CCR3_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    2973. 

  2973. <a name="l02941"></a>02941 <span class="preprocessor">#define  DMA_CCR3_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    2974. 

  2974. <a name="l02942"></a>02942 <span class="preprocessor">#define  DMA_CCR3_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    2975. 

  2975. <a name="l02943"></a>02943 
    2976. 

  2976. <a name="l02944"></a>02944 <span class="preprocessor">#define  DMA_CCR3_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    2977. 

  2977. <a name="l02945"></a>02945 <span class="preprocessor">#define  DMA_CCR3_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    2978. 

  2978. <a name="l02946"></a>02946 <span class="preprocessor">#define  DMA_CCR3_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    2979. 

  2979. <a name="l02947"></a>02947 
    2980. 

  2980. <a name="l02948"></a>02948 <span class="preprocessor">#define  DMA_CCR3_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode */</span>
    2981. 

  2981. <a name="l02949"></a>02949 
    2982. 

  2982. <a name="l02950"></a>02950 
    2983. 

  2983. <a name="l02951"></a>02951 <span class="comment">/*******************  Bit definition for DMA_CCR4 register  *******************/</span>
    2984. 

  2984. <a name="l02952"></a>02952 <span class="preprocessor">#define  DMA_CCR4_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    2985. 

  2985. <a name="l02953"></a>02953 <span class="preprocessor">#define  DMA_CCR4_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    2986. 

  2986. <a name="l02954"></a>02954 <span class="preprocessor">#define  DMA_CCR4_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    2987. 

  2987. <a name="l02955"></a>02955 <span class="preprocessor">#define  DMA_CCR4_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    2988. 

  2988. <a name="l02956"></a>02956 <span class="preprocessor">#define  DMA_CCR4_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    2989. 

  2989. <a name="l02957"></a>02957 <span class="preprocessor">#define  DMA_CCR4_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    2990. 

  2990. <a name="l02958"></a>02958 <span class="preprocessor">#define  DMA_CCR4_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    2991. 

  2991. <a name="l02959"></a>02959 <span class="preprocessor">#define  DMA_CCR4_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    2992. 

  2992. <a name="l02960"></a>02960 
    2993. 

  2993. <a name="l02961"></a>02961 <span class="preprocessor">#define  DMA_CCR4_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    2994. 

  2994. <a name="l02962"></a>02962 <span class="preprocessor">#define  DMA_CCR4_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    2995. 

  2995. <a name="l02963"></a>02963 <span class="preprocessor">#define  DMA_CCR4_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    2996. 

  2996. <a name="l02964"></a>02964 
    2997. 

  2997. <a name="l02965"></a>02965 <span class="preprocessor">#define  DMA_CCR4_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    2998. 

  2998. <a name="l02966"></a>02966 <span class="preprocessor">#define  DMA_CCR4_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    2999. 

  2999. <a name="l02967"></a>02967 <span class="preprocessor">#define  DMA_CCR4_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3000. 

  3000. <a name="l02968"></a>02968 
    3001. 

  3001. <a name="l02969"></a>02969 <span class="preprocessor">#define  DMA_CCR4_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    3002. 

  3002. <a name="l02970"></a>02970 <span class="preprocessor">#define  DMA_CCR4_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3003. 

  3003. <a name="l02971"></a>02971 <span class="preprocessor">#define  DMA_CCR4_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3004. 

  3004. <a name="l02972"></a>02972 
    3005. 

  3005. <a name="l02973"></a>02973 <span class="preprocessor">#define  DMA_CCR4_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode */</span>
    3006. 

  3006. <a name="l02974"></a>02974 
    3007. 

  3007. <a name="l02975"></a>02975 
    3008. 

  3008. <a name="l02976"></a>02976 <span class="comment">/******************  Bit definition for DMA_CCR5 register  *******************/</span>
    3009. 

  3009. <a name="l02977"></a>02977 <span class="preprocessor">#define  DMA_CCR5_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    3010. 

  3010. <a name="l02978"></a>02978 <span class="preprocessor">#define  DMA_CCR5_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    3011. 

  3011. <a name="l02979"></a>02979 <span class="preprocessor">#define  DMA_CCR5_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    3012. 

  3012. <a name="l02980"></a>02980 <span class="preprocessor">#define  DMA_CCR5_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    3013. 

  3013. <a name="l02981"></a>02981 <span class="preprocessor">#define  DMA_CCR5_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    3014. 

  3014. <a name="l02982"></a>02982 <span class="preprocessor">#define  DMA_CCR5_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    3015. 

  3015. <a name="l02983"></a>02983 <span class="preprocessor">#define  DMA_CCR5_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    3016. 

  3016. <a name="l02984"></a>02984 <span class="preprocessor">#define  DMA_CCR5_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    3017. 

  3017. <a name="l02985"></a>02985 
    3018. 

  3018. <a name="l02986"></a>02986 <span class="preprocessor">#define  DMA_CCR5_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    3019. 

  3019. <a name="l02987"></a>02987 <span class="preprocessor">#define  DMA_CCR5_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3020. 

  3020. <a name="l02988"></a>02988 <span class="preprocessor">#define  DMA_CCR5_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3021. 

  3021. <a name="l02989"></a>02989 
    3022. 

  3022. <a name="l02990"></a>02990 <span class="preprocessor">#define  DMA_CCR5_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    3023. 

  3023. <a name="l02991"></a>02991 <span class="preprocessor">#define  DMA_CCR5_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    3024. 

  3024. <a name="l02992"></a>02992 <span class="preprocessor">#define  DMA_CCR5_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3025. 

  3025. <a name="l02993"></a>02993 
    3026. 

  3026. <a name="l02994"></a>02994 <span class="preprocessor">#define  DMA_CCR5_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    3027. 

  3027. <a name="l02995"></a>02995 <span class="preprocessor">#define  DMA_CCR5_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3028. 

  3028. <a name="l02996"></a>02996 <span class="preprocessor">#define  DMA_CCR5_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3029. 

  3029. <a name="l02997"></a>02997 
    3030. 

  3030. <a name="l02998"></a>02998 <span class="preprocessor">#define  DMA_CCR5_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode enable */</span>
    3031. 

  3031. <a name="l02999"></a>02999 
    3032. 

  3032. <a name="l03000"></a>03000 
    3033. 

  3033. <a name="l03001"></a>03001 <span class="comment">/*******************  Bit definition for DMA_CCR6 register  *******************/</span>
    3034. 

  3034. <a name="l03002"></a>03002 <span class="preprocessor">#define  DMA_CCR6_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    3035. 

  3035. <a name="l03003"></a>03003 <span class="preprocessor">#define  DMA_CCR6_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    3036. 

  3036. <a name="l03004"></a>03004 <span class="preprocessor">#define  DMA_CCR6_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    3037. 

  3037. <a name="l03005"></a>03005 <span class="preprocessor">#define  DMA_CCR6_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    3038. 

  3038. <a name="l03006"></a>03006 <span class="preprocessor">#define  DMA_CCR6_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    3039. 

  3039. <a name="l03007"></a>03007 <span class="preprocessor">#define  DMA_CCR6_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    3040. 

  3040. <a name="l03008"></a>03008 <span class="preprocessor">#define  DMA_CCR6_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    3041. 

  3041. <a name="l03009"></a>03009 <span class="preprocessor">#define  DMA_CCR6_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    3042. 

  3042. <a name="l03010"></a>03010 
    3043. 

  3043. <a name="l03011"></a>03011 <span class="preprocessor">#define  DMA_CCR6_PSIZE                      ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    3044. 

  3044. <a name="l03012"></a>03012 <span class="preprocessor">#define  DMA_CCR6_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3045. 

  3045. <a name="l03013"></a>03013 <span class="preprocessor">#define  DMA_CCR6_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3046. 

  3046. <a name="l03014"></a>03014 
    3047. 

  3047. <a name="l03015"></a>03015 <span class="preprocessor">#define  DMA_CCR6_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    3048. 

  3048. <a name="l03016"></a>03016 <span class="preprocessor">#define  DMA_CCR6_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    3049. 

  3049. <a name="l03017"></a>03017 <span class="preprocessor">#define  DMA_CCR6_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3050. 

  3050. <a name="l03018"></a>03018 
    3051. 

  3051. <a name="l03019"></a>03019 <span class="preprocessor">#define  DMA_CCR6_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    3052. 

  3052. <a name="l03020"></a>03020 <span class="preprocessor">#define  DMA_CCR6_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3053. 

  3053. <a name="l03021"></a>03021 <span class="preprocessor">#define  DMA_CCR6_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3054. 

  3054. <a name="l03022"></a>03022 
    3055. 

  3055. <a name="l03023"></a>03023 <span class="preprocessor">#define  DMA_CCR6_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode */</span>
    3056. 

  3056. <a name="l03024"></a>03024 
    3057. 

  3057. <a name="l03025"></a>03025 
    3058. 

  3058. <a name="l03026"></a>03026 <span class="comment">/*******************  Bit definition for DMA_CCR7 register  *******************/</span>
    3059. 

  3059. <a name="l03027"></a>03027 <span class="preprocessor">#define  DMA_CCR7_EN                         ((u16)0x0001)            </span><span class="comment">/* Channel enable */</span>
    3060. 

  3060. <a name="l03028"></a>03028 <span class="preprocessor">#define  DMA_CCR7_TCIE                       ((u16)0x0002)            </span><span class="comment">/* Transfer complete interrupt enable */</span>
    3061. 

  3061. <a name="l03029"></a>03029 <span class="preprocessor">#define  DMA_CCR7_HTIE                       ((u16)0x0004)            </span><span class="comment">/* Half Transfer interrupt enable */</span>
    3062. 

  3062. <a name="l03030"></a>03030 <span class="preprocessor">#define  DMA_CCR7_TEIE                       ((u16)0x0008)            </span><span class="comment">/* Transfer error interrupt enable */</span>
    3063. 

  3063. <a name="l03031"></a>03031 <span class="preprocessor">#define  DMA_CCR7_DIR                        ((u16)0x0010)            </span><span class="comment">/* Data transfer direction */</span>
    3064. 

  3064. <a name="l03032"></a>03032 <span class="preprocessor">#define  DMA_CCR7_CIRC                       ((u16)0x0020)            </span><span class="comment">/* Circular mode */</span>
    3065. 

  3065. <a name="l03033"></a>03033 <span class="preprocessor">#define  DMA_CCR7_PINC                       ((u16)0x0040)            </span><span class="comment">/* Peripheral increment mode */</span>
    3066. 

  3066. <a name="l03034"></a>03034 <span class="preprocessor">#define  DMA_CCR7_MINC                       ((u16)0x0080)            </span><span class="comment">/* Memory increment mode */</span>
    3067. 

  3067. <a name="l03035"></a>03035 
    3068. 

  3068. <a name="l03036"></a>03036 <span class="preprocessor">#define  DMA_CCR7_PSIZE            ,         ((u16)0x0300)            </span><span class="comment">/* PSIZE[1:0] bits (Peripheral size) */</span>
    3069. 

  3069. <a name="l03037"></a>03037 <span class="preprocessor">#define  DMA_CCR7_PSIZE_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3070. 

  3070. <a name="l03038"></a>03038 <span class="preprocessor">#define  DMA_CCR7_PSIZE_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3071. 

  3071. <a name="l03039"></a>03039 
    3072. 

  3072. <a name="l03040"></a>03040 <span class="preprocessor">#define  DMA_CCR7_MSIZE                      ((u16)0x0C00)            </span><span class="comment">/* MSIZE[1:0] bits (Memory size) */</span>
    3073. 

  3073. <a name="l03041"></a>03041 <span class="preprocessor">#define  DMA_CCR7_MSIZE_0                    ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    3074. 

  3074. <a name="l03042"></a>03042 <span class="preprocessor">#define  DMA_CCR7_MSIZE_1                    ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3075. 

  3075. <a name="l03043"></a>03043 
    3076. 

  3076. <a name="l03044"></a>03044 <span class="preprocessor">#define  DMA_CCR7_PL                         ((u16)0x3000)            </span><span class="comment">/* PL[1:0] bits (Channel Priority level) */</span>
    3077. 

  3077. <a name="l03045"></a>03045 <span class="preprocessor">#define  DMA_CCR7_PL_0                       ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3078. 

  3078. <a name="l03046"></a>03046 <span class="preprocessor">#define  DMA_CCR7_PL_1                       ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3079. 

  3079. <a name="l03047"></a>03047 
    3080. 

  3080. <a name="l03048"></a>03048 <span class="preprocessor">#define  DMA_CCR7_MEM2MEM                    ((u16)0x4000)            </span><span class="comment">/* Memory to memory mode enable */</span>
    3081. 

  3081. <a name="l03049"></a>03049 
    3082. 

  3082. <a name="l03050"></a>03050 
    3083. 

  3083. <a name="l03051"></a>03051 <span class="comment">/******************  Bit definition for DMA_CNDTR1 register  ******************/</span>
    3084. 

  3084. <a name="l03052"></a>03052 <span class="preprocessor">#define  DMA_CNDTR1_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3085. 

  3085. <a name="l03053"></a>03053 
    3086. 

  3086. <a name="l03054"></a>03054 
    3087. 

  3087. <a name="l03055"></a>03055 <span class="comment">/******************  Bit definition for DMA_CNDTR2 register  ******************/</span>
    3088. 

  3088. <a name="l03056"></a>03056 <span class="preprocessor">#define  DMA_CNDTR2_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3089. 

  3089. <a name="l03057"></a>03057 
    3090. 

  3090. <a name="l03058"></a>03058 
    3091. 

  3091. <a name="l03059"></a>03059 <span class="comment">/******************  Bit definition for DMA_CNDTR3 register  ******************/</span>
    3092. 

  3092. <a name="l03060"></a>03060 <span class="preprocessor">#define  DMA_CNDTR3_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3093. 

  3093. <a name="l03061"></a>03061 
    3094. 

  3094. <a name="l03062"></a>03062 
    3095. 

  3095. <a name="l03063"></a>03063 <span class="comment">/******************  Bit definition for DMA_CNDTR4 register  ******************/</span>
    3096. 

  3096. <a name="l03064"></a>03064 <span class="preprocessor">#define  DMA_CNDTR4_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3097. 

  3097. <a name="l03065"></a>03065 
    3098. 

  3098. <a name="l03066"></a>03066 
    3099. 

  3099. <a name="l03067"></a>03067 <span class="comment">/******************  Bit definition for DMA_CNDTR5 register  ******************/</span>
    3100. 

  3100. <a name="l03068"></a>03068 <span class="preprocessor">#define  DMA_CNDTR5_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3101. 

  3101. <a name="l03069"></a>03069 
    3102. 

  3102. <a name="l03070"></a>03070 
    3103. 

  3103. <a name="l03071"></a>03071 <span class="comment">/******************  Bit definition for DMA_CNDTR6 register  ******************/</span>
    3104. 

  3104. <a name="l03072"></a>03072 <span class="preprocessor">#define  DMA_CNDTR6_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3105. 

  3105. <a name="l03073"></a>03073 
    3106. 

  3106. <a name="l03074"></a>03074 
    3107. 

  3107. <a name="l03075"></a>03075 <span class="comment">/******************  Bit definition for DMA_CNDTR7 register  ******************/</span>
    3108. 

  3108. <a name="l03076"></a>03076 <span class="preprocessor">#define  DMA_CNDTR7_NDT                      ((u16)0xFFFF)            </span><span class="comment">/* Number of data to Transfer */</span>
    3109. 

  3109. <a name="l03077"></a>03077 
    3110. 

  3110. <a name="l03078"></a>03078 
    3111. 

  3111. <a name="l03079"></a>03079 <span class="comment">/******************  Bit definition for DMA_CPAR1 register  *******************/</span>
    3112. 

  3112. <a name="l03080"></a>03080 <span class="preprocessor">#define  DMA_CPAR1_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3113. 

  3113. <a name="l03081"></a>03081 
    3114. 

  3114. <a name="l03082"></a>03082 
    3115. 

  3115. <a name="l03083"></a>03083 <span class="comment">/******************  Bit definition for DMA_CPAR2 register  *******************/</span>
    3116. 

  3116. <a name="l03084"></a>03084 <span class="preprocessor">#define  DMA_CPAR2_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3117. 

  3117. <a name="l03085"></a>03085 
    3118. 

  3118. <a name="l03086"></a>03086 
    3119. 

  3119. <a name="l03087"></a>03087 <span class="comment">/******************  Bit definition for DMA_CPAR3 register  *******************/</span>
    3120. 

  3120. <a name="l03088"></a>03088 <span class="preprocessor">#define  DMA_CPAR3_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3121. 

  3121. <a name="l03089"></a>03089 
    3122. 

  3122. <a name="l03090"></a>03090 
    3123. 

  3123. <a name="l03091"></a>03091 <span class="comment">/******************  Bit definition for DMA_CPAR4 register  *******************/</span>
    3124. 

  3124. <a name="l03092"></a>03092 <span class="preprocessor">#define  DMA_CPAR4_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3125. 

  3125. <a name="l03093"></a>03093 
    3126. 

  3126. <a name="l03094"></a>03094 
    3127. 

  3127. <a name="l03095"></a>03095 <span class="comment">/******************  Bit definition for DMA_CPAR5 register  *******************/</span>
    3128. 

  3128. <a name="l03096"></a>03096 <span class="preprocessor">#define  DMA_CPAR5_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3129. 

  3129. <a name="l03097"></a>03097 
    3130. 

  3130. <a name="l03098"></a>03098 
    3131. 

  3131. <a name="l03099"></a>03099 <span class="comment">/******************  Bit definition for DMA_CPAR6 register  *******************/</span>
    3132. 

  3132. <a name="l03100"></a>03100 <span class="preprocessor">#define  DMA_CPAR6_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3133. 

  3133. <a name="l03101"></a>03101 
    3134. 

  3134. <a name="l03102"></a>03102 
    3135. 

  3135. <a name="l03103"></a>03103 <span class="comment">/******************  Bit definition for DMA_CPAR7 register  *******************/</span>
    3136. 

  3136. <a name="l03104"></a>03104 <span class="preprocessor">#define  DMA_CPAR7_PA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Peripheral Address */</span>
    3137. 

  3137. <a name="l03105"></a>03105 
    3138. 

  3138. <a name="l03106"></a>03106 
    3139. 

  3139. <a name="l03107"></a>03107 <span class="comment">/******************  Bit definition for DMA_CMAR1 register  *******************/</span>
    3140. 

  3140. <a name="l03108"></a>03108 <span class="preprocessor">#define  DMA_CMAR1_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3141. 

  3141. <a name="l03109"></a>03109 
    3142. 

  3142. <a name="l03110"></a>03110 
    3143. 

  3143. <a name="l03111"></a>03111 <span class="comment">/******************  Bit definition for DMA_CMAR2 register  *******************/</span>
    3144. 

  3144. <a name="l03112"></a>03112 <span class="preprocessor">#define  DMA_CMAR2_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3145. 

  3145. <a name="l03113"></a>03113 
    3146. 

  3146. <a name="l03114"></a>03114 
    3147. 

  3147. <a name="l03115"></a>03115 <span class="comment">/******************  Bit definition for DMA_CMAR3 register  *******************/</span>
    3148. 

  3148. <a name="l03116"></a>03116 <span class="preprocessor">#define  DMA_CMAR3_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3149. 

  3149. <a name="l03117"></a>03117 
    3150. 

  3150. <a name="l03118"></a>03118 
    3151. 

  3151. <a name="l03119"></a>03119 <span class="comment">/******************  Bit definition for DMA_CMAR4 register  *******************/</span>
    3152. 

  3152. <a name="l03120"></a>03120 <span class="preprocessor">#define  DMA_CMAR4_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3153. 

  3153. <a name="l03121"></a>03121 
    3154. 

  3154. <a name="l03122"></a>03122 
    3155. 

  3155. <a name="l03123"></a>03123 <span class="comment">/******************  Bit definition for DMA_CMAR5 register  *******************/</span>
    3156. 

  3156. <a name="l03124"></a>03124 <span class="preprocessor">#define  DMA_CMAR5_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3157. 

  3157. <a name="l03125"></a>03125 
    3158. 

  3158. <a name="l03126"></a>03126 
    3159. 

  3159. <a name="l03127"></a>03127 <span class="comment">/******************  Bit definition for DMA_CMAR6 register  *******************/</span>
    3160. 

  3160. <a name="l03128"></a>03128 <span class="preprocessor">#define  DMA_CMAR6_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3161. 

  3161. <a name="l03129"></a>03129 
    3162. 

  3162. <a name="l03130"></a>03130 
    3163. 

  3163. <a name="l03131"></a>03131 <span class="comment">/******************  Bit definition for DMA_CMAR7 register  *******************/</span>
    3164. 

  3164. <a name="l03132"></a>03132 <span class="preprocessor">#define  DMA_CMAR7_MA                        ((u32)0xFFFFFFFF)        </span><span class="comment">/* Memory Address */</span>
    3165. 

  3165. <a name="l03133"></a>03133 
    3166. 

  3166. <a name="l03134"></a>03134 
    3167. 

  3167. <a name="l03135"></a>03135 
    3168. 

  3168. <a name="l03136"></a>03136 <span class="comment">/******************************************************************************/</span>
    3169. 

  3169. <a name="l03137"></a>03137 <span class="comment">/*                                                                            */</span>
    3170. 

  3170. <a name="l03138"></a>03138 <span class="comment">/*                        Analog to Digital Converter                         */</span>
    3171. 

  3171. <a name="l03139"></a>03139 <span class="comment">/*                                                                            */</span>
    3172. 

  3172. <a name="l03140"></a>03140 <span class="comment">/******************************************************************************/</span>
    3173. 

  3173. <a name="l03141"></a>03141 
    3174. 

  3174. <a name="l03142"></a>03142 <span class="comment">/********************  Bit definition for ADC_SR register  ********************/</span>
    3175. 

  3175. <a name="l03143"></a>03143 <span class="preprocessor">#define  ADC_SR_AWD                          ((u8)0x01)               </span><span class="comment">/* Analog watchdog flag */</span>
    3176. 

  3176. <a name="l03144"></a>03144 <span class="preprocessor">#define  ADC_SR_EOC                          ((u8)0x02)               </span><span class="comment">/* End of conversion */</span>
    3177. 

  3177. <a name="l03145"></a>03145 <span class="preprocessor">#define  ADC_SR_JEOC                         ((u8)0x04)               </span><span class="comment">/* Injected channel end of conversion */</span>
    3178. 

  3178. <a name="l03146"></a>03146 <span class="preprocessor">#define  ADC_SR_JSTRT                        ((u8)0x08)               </span><span class="comment">/* Injected channel Start flag */</span>
    3179. 

  3179. <a name="l03147"></a>03147 <span class="preprocessor">#define  ADC_SR_STRT                         ((u8)0x10)               </span><span class="comment">/* Regular channel Start flag */</span>
    3180. 

  3180. <a name="l03148"></a>03148 
    3181. 

  3181. <a name="l03149"></a>03149 
    3182. 

  3182. <a name="l03150"></a>03150 <span class="comment">/*******************  Bit definition for ADC_CR1 register  ********************/</span>
    3183. 

  3183. <a name="l03151"></a>03151 <span class="preprocessor">#define  ADC_CR1_AWDCH                       ((u32)0x0000001F)        </span><span class="comment">/* AWDCH[4:0] bits (Analog watchdog channel select bits) */</span>
    3184. 

  3184. <a name="l03152"></a>03152 <span class="preprocessor">#define  ADC_CR1_AWDCH_0                     ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3185. 

  3185. <a name="l03153"></a>03153 <span class="preprocessor">#define  ADC_CR1_AWDCH_1                     ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3186. 

  3186. <a name="l03154"></a>03154 <span class="preprocessor">#define  ADC_CR1_AWDCH_2                     ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3187. 

  3187. <a name="l03155"></a>03155 <span class="preprocessor">#define  ADC_CR1_AWDCH_3                     ((u32)0x00000008)        </span><span class="comment">/* Bit 3 */</span>
    3188. 

  3188. <a name="l03156"></a>03156 <span class="preprocessor">#define  ADC_CR1_AWDCH_4                     ((u32)0x00000010)        </span><span class="comment">/* Bit 4 */</span>
    3189. 

  3189. <a name="l03157"></a>03157 
    3190. 

  3190. <a name="l03158"></a>03158 <span class="preprocessor">#define  ADC_CR1_EOCIE                       ((u32)0x00000020)        </span><span class="comment">/* Interrupt enable for EOC */</span>
    3191. 

  3191. <a name="l03159"></a>03159 <span class="preprocessor">#define  ADC_CR1_AWDIE                       ((u32)0x00000040)        </span><span class="comment">/* AAnalog Watchdog interrupt enable */</span>
    3192. 

  3192. <a name="l03160"></a>03160 <span class="preprocessor">#define  ADC_CR1_JEOCIE                      ((u32)0x00000080)        </span><span class="comment">/* Interrupt enable for injected channels */</span>
    3193. 

  3193. <a name="l03161"></a>03161 <span class="preprocessor">#define  ADC_CR1_SCAN                        ((u32)0x00000100)        </span><span class="comment">/* Scan mode */</span>
    3194. 

  3194. <a name="l03162"></a>03162 <span class="preprocessor">#define  ADC_CR1_AWDSGL                      ((u32)0x00000200)        </span><span class="comment">/* Enable the watchdog on a single channel in scan mode */</span>
    3195. 

  3195. <a name="l03163"></a>03163 <span class="preprocessor">#define  ADC_CR1_JAUTO                       ((u32)0x00000400)        </span><span class="comment">/* Automatic injected group conversion */</span>
    3196. 

  3196. <a name="l03164"></a>03164 <span class="preprocessor">#define  ADC_CR1_DISCEN                      ((u32)0x00000800)        </span><span class="comment">/* Discontinuous mode on regular channels */</span>
    3197. 

  3197. <a name="l03165"></a>03165 <span class="preprocessor">#define  ADC_CR1_JDISCEN                     ((u32)0x00001000)        </span><span class="comment">/* Discontinuous mode on injected channels */</span>
    3198. 

  3198. <a name="l03166"></a>03166 
    3199. 

  3199. <a name="l03167"></a>03167 <span class="preprocessor">#define  ADC_CR1_DISCNUM                     ((u32)0x0000E000)        </span><span class="comment">/* DISCNUM[2:0] bits (Discontinuous mode channel count) */</span>
    3200. 

  3200. <a name="l03168"></a>03168 <span class="preprocessor">#define  ADC_CR1_DISCNUM_0                   ((u32)0x00002000)        </span><span class="comment">/* Bit 0 */</span>
    3201. 

  3201. <a name="l03169"></a>03169 <span class="preprocessor">#define  ADC_CR1_DISCNUM_1                   ((u32)0x00004000)        </span><span class="comment">/* Bit 1 */</span>
    3202. 

  3202. <a name="l03170"></a>03170 <span class="preprocessor">#define  ADC_CR1_DISCNUM_2                   ((u32)0x00008000)        </span><span class="comment">/* Bit 2 */</span>
    3203. 

  3203. <a name="l03171"></a>03171 
    3204. 

  3204. <a name="l03172"></a>03172 <span class="preprocessor">#define  ADC_CR1_DUALMOD                     ((u32)0x000F0000)        </span><span class="comment">/* DUALMOD[3:0] bits (Dual mode selection) */</span>
    3205. 

  3205. <a name="l03173"></a>03173 <span class="preprocessor">#define  ADC_CR1_DUALMOD_0                   ((u32)0x00010000)        </span><span class="comment">/* Bit 0 */</span>
    3206. 

  3206. <a name="l03174"></a>03174 <span class="preprocessor">#define  ADC_CR1_DUALMOD_1                   ((u32)0x00020000)        </span><span class="comment">/* Bit 1 */</span>
    3207. 

  3207. <a name="l03175"></a>03175 <span class="preprocessor">#define  ADC_CR1_DUALMOD_2                   ((u32)0x00040000)        </span><span class="comment">/* Bit 2 */</span>
    3208. 

  3208. <a name="l03176"></a>03176 <span class="preprocessor">#define  ADC_CR1_DUALMOD_3                   ((u32)0x00080000)        </span><span class="comment">/* Bit 3 */</span>
    3209. 

  3209. <a name="l03177"></a>03177 
    3210. 

  3210. <a name="l03178"></a>03178 <span class="preprocessor">#define  ADC_CR1_JAWDEN                      ((u32)0x00400000)        </span><span class="comment">/* Analog watchdog enable on injected channels */</span>
    3211. 

  3211. <a name="l03179"></a>03179 <span class="preprocessor">#define  ADC_CR1_AWDEN                       ((u32)0x00800000)        </span><span class="comment">/* Analog watchdog enable on regular channels */</span>
    3212. 

  3212. <a name="l03180"></a>03180 
    3213. 

  3213. <a name="l03181"></a>03181   
    3214. 

  3214. <a name="l03182"></a>03182 <span class="comment">/*******************  Bit definition for ADC_CR2 register  ********************/</span>
    3215. 

  3215. <a name="l03183"></a>03183 <span class="preprocessor">#define  ADC_CR2_ADON                        ((u32)0x00000001)        </span><span class="comment">/* A/D Converter ON / OFF */</span>
    3216. 

  3216. <a name="l03184"></a>03184 <span class="preprocessor">#define  ADC_CR2_CONT                        ((u32)0x00000002)        </span><span class="comment">/* Continuous Conversion */</span>
    3217. 

  3217. <a name="l03185"></a>03185 <span class="preprocessor">#define  ADC_CR2_CAL                         ((u32)0x00000004)        </span><span class="comment">/* A/D Calibration */</span>
    3218. 

  3218. <a name="l03186"></a>03186 <span class="preprocessor">#define  ADC_CR2_RSTCAL                      ((u32)0x00000008)        </span><span class="comment">/* Reset Calibration */</span>
    3219. 

  3219. <a name="l03187"></a>03187 <span class="preprocessor">#define  ADC_CR2_DMA                         ((u32)0x00000100)        </span><span class="comment">/* Direct Memory access mode */</span>
    3220. 

  3220. <a name="l03188"></a>03188 <span class="preprocessor">#define  ADC_CR2_ALIGN                       ((u32)0x00000800)        </span><span class="comment">/* Data Alignment */</span>
    3221. 

  3221. <a name="l03189"></a>03189 
    3222. 

  3222. <a name="l03190"></a>03190 <span class="preprocessor">#define  ADC_CR2_JEXTSEL                     ((u32)0x00007000)        </span><span class="comment">/* JEXTSEL[2:0] bits (External event select for injected group) */</span>
    3223. 

  3223. <a name="l03191"></a>03191 <span class="preprocessor">#define  ADC_CR2_JEXTSEL_0                   ((u32)0x00001000)        </span><span class="comment">/* Bit 0 */</span>
    3224. 

  3224. <a name="l03192"></a>03192 <span class="preprocessor">#define  ADC_CR2_JEXTSEL_1                   ((u32)0x00002000)        </span><span class="comment">/* Bit 1 */</span>
    3225. 

  3225. <a name="l03193"></a>03193 <span class="preprocessor">#define  ADC_CR2_JEXTSEL_2                   ((u32)0x00004000)        </span><span class="comment">/* Bit 2 */</span>
    3226. 

  3226. <a name="l03194"></a>03194 
    3227. 

  3227. <a name="l03195"></a>03195 <span class="preprocessor">#define  ADC_CR2_JEXTTRIG                    ((u32)0x00008000)        </span><span class="comment">/* External Trigger Conversion mode for injected channels */</span>
    3228. 

  3228. <a name="l03196"></a>03196 
    3229. 

  3229. <a name="l03197"></a>03197 <span class="preprocessor">#define  ADC_CR2_EXTSEL                      ((u32)0x000E0000)        </span><span class="comment">/* EXTSEL[2:0] bits (External Event Select for regular group) */</span>
    3230. 

  3230. <a name="l03198"></a>03198 <span class="preprocessor">#define  ADC_CR2_EXTSEL_0                    ((u32)0x00020000)        </span><span class="comment">/* Bit 0 */</span>
    3231. 

  3231. <a name="l03199"></a>03199 <span class="preprocessor">#define  ADC_CR2_EXTSEL_1                    ((u32)0x00040000)        </span><span class="comment">/* Bit 1 */</span>
    3232. 

  3232. <a name="l03200"></a>03200 <span class="preprocessor">#define  ADC_CR2_EXTSEL_2                    ((u32)0x00080000)        </span><span class="comment">/* Bit 2 */</span>
    3233. 

  3233. <a name="l03201"></a>03201 
    3234. 

  3234. <a name="l03202"></a>03202 <span class="preprocessor">#define  ADC_CR2_EXTTRIG                     ((u32)0x00100000)        </span><span class="comment">/* External Trigger Conversion mode for regular channels */</span>
    3235. 

  3235. <a name="l03203"></a>03203 <span class="preprocessor">#define  ADC_CR2_JSWSTART                    ((u32)0x00200000)        </span><span class="comment">/* Start Conversion of injected channels */</span>
    3236. 

  3236. <a name="l03204"></a>03204 <span class="preprocessor">#define  ADC_CR2_SWSTART                     ((u32)0x00400000)        </span><span class="comment">/* Start Conversion of regular channels */</span>
    3237. 

  3237. <a name="l03205"></a>03205 <span class="preprocessor">#define  ADC_CR2_TSVREFE                     ((u32)0x00800000)        </span><span class="comment">/* Temperature Sensor and VREFINT Enable */</span>
    3238. 

  3238. <a name="l03206"></a>03206 
    3239. 

  3239. <a name="l03207"></a>03207 
    3240. 

  3240. <a name="l03208"></a>03208 <span class="comment">/******************  Bit definition for ADC_SMPR1 register  *******************/</span>
    3241. 

  3241. <a name="l03209"></a>03209 <span class="preprocessor">#define  ADC_SMPR1_SMP10                     ((u32)0x00000007)        </span><span class="comment">/* SMP10[2:0] bits (Channel 10 Sample time selection) */</span>
    3242. 

  3242. <a name="l03210"></a>03210 <span class="preprocessor">#define  ADC_SMPR1_SMP10_0                   ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3243. 

  3243. <a name="l03211"></a>03211 <span class="preprocessor">#define  ADC_SMPR1_SMP10_1                   ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3244. 

  3244. <a name="l03212"></a>03212 <span class="preprocessor">#define  ADC_SMPR1_SMP10_2                   ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3245. 

  3245. <a name="l03213"></a>03213 
    3246. 

  3246. <a name="l03214"></a>03214 <span class="preprocessor">#define  ADC_SMPR1_SMP11                     ((u32)0x00000038)        </span><span class="comment">/* SMP11[2:0] bits (Channel 11 Sample time selection) */</span>
    3247. 

  3247. <a name="l03215"></a>03215 <span class="preprocessor">#define  ADC_SMPR1_SMP11_0                   ((u32)0x00000008)        </span><span class="comment">/* Bit 0 */</span>
    3248. 

  3248. <a name="l03216"></a>03216 <span class="preprocessor">#define  ADC_SMPR1_SMP11_1                   ((u32)0x00000010)        </span><span class="comment">/* Bit 1 */</span>
    3249. 

  3249. <a name="l03217"></a>03217 <span class="preprocessor">#define  ADC_SMPR1_SMP11_2                   ((u32)0x00000020)        </span><span class="comment">/* Bit 2 */</span>
    3250. 

  3250. <a name="l03218"></a>03218 
    3251. 

  3251. <a name="l03219"></a>03219 <span class="preprocessor">#define  ADC_SMPR1_SMP12                     ((u32)0x000001C0)        </span><span class="comment">/* SMP12[2:0] bits (Channel 12 Sample time selection) */</span>
    3252. 

  3252. <a name="l03220"></a>03220 <span class="preprocessor">#define  ADC_SMPR1_SMP12_0                   ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    3253. 

  3253. <a name="l03221"></a>03221 <span class="preprocessor">#define  ADC_SMPR1_SMP12_1                   ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    3254. 

  3254. <a name="l03222"></a>03222 <span class="preprocessor">#define  ADC_SMPR1_SMP12_2                   ((u32)0x00000100)        </span><span class="comment">/* Bit 2 */</span>
    3255. 

  3255. <a name="l03223"></a>03223 
    3256. 

  3256. <a name="l03224"></a>03224 <span class="preprocessor">#define  ADC_SMPR1_SMP13                     ((u32)0x00000E00)        </span><span class="comment">/* SMP13[2:0] bits (Channel 13 Sample time selection) */</span>
    3257. 

  3257. <a name="l03225"></a>03225 <span class="preprocessor">#define  ADC_SMPR1_SMP13_0                   ((u32)0x00000200)        </span><span class="comment">/* Bit 0 */</span>
    3258. 

  3258. <a name="l03226"></a>03226 <span class="preprocessor">#define  ADC_SMPR1_SMP13_1                   ((u32)0x00000400)        </span><span class="comment">/* Bit 1 */</span>
    3259. 

  3259. <a name="l03227"></a>03227 <span class="preprocessor">#define  ADC_SMPR1_SMP13_2                   ((u32)0x00000800)        </span><span class="comment">/* Bit 2 */</span>
    3260. 

  3260. <a name="l03228"></a>03228 
    3261. 

  3261. <a name="l03229"></a>03229 <span class="preprocessor">#define  ADC_SMPR1_SMP14                     ((u32)0x00007000)        </span><span class="comment">/* SMP14[2:0] bits (Channel 14 Sample time selection) */</span>
    3262. 

  3262. <a name="l03230"></a>03230 <span class="preprocessor">#define  ADC_SMPR1_SMP14_0                   ((u32)0x00001000)        </span><span class="comment">/* Bit 0 */</span>
    3263. 

  3263. <a name="l03231"></a>03231 <span class="preprocessor">#define  ADC_SMPR1_SMP14_1                   ((u32)0x00002000)        </span><span class="comment">/* Bit 1 */</span>
    3264. 

  3264. <a name="l03232"></a>03232 <span class="preprocessor">#define  ADC_SMPR1_SMP14_2                   ((u32)0x00004000)        </span><span class="comment">/* Bit 2 */</span>
    3265. 

  3265. <a name="l03233"></a>03233 
    3266. 

  3266. <a name="l03234"></a>03234 <span class="preprocessor">#define  ADC_SMPR1_SMP15                     ((u32)0x00038000)        </span><span class="comment">/* SMP15[2:0] bits (Channel 15 Sample time selection) */</span>
    3267. 

  3267. <a name="l03235"></a>03235 <span class="preprocessor">#define  ADC_SMPR1_SMP15_0                   ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3268. 

  3268. <a name="l03236"></a>03236 <span class="preprocessor">#define  ADC_SMPR1_SMP15_1                   ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3269. 

  3269. <a name="l03237"></a>03237 <span class="preprocessor">#define  ADC_SMPR1_SMP15_2                   ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3270. 

  3270. <a name="l03238"></a>03238 
    3271. 

  3271. <a name="l03239"></a>03239 <span class="preprocessor">#define  ADC_SMPR1_SMP16                     ((u32)0x001C0000)        </span><span class="comment">/* SMP16[2:0] bits (Channel 16 Sample time selection) */</span>
    3272. 

  3272. <a name="l03240"></a>03240 <span class="preprocessor">#define  ADC_SMPR1_SMP16_0                   ((u32)0x00040000)        </span><span class="comment">/* Bit 0 */</span>
    3273. 

  3273. <a name="l03241"></a>03241 <span class="preprocessor">#define  ADC_SMPR1_SMP16_1                   ((u32)0x00080000)        </span><span class="comment">/* Bit 1 */</span>
    3274. 

  3274. <a name="l03242"></a>03242 <span class="preprocessor">#define  ADC_SMPR1_SMP16_2                   ((u32)0x00100000)        </span><span class="comment">/* Bit 2 */</span>
    3275. 

  3275. <a name="l03243"></a>03243 
    3276. 

  3276. <a name="l03244"></a>03244 <span class="preprocessor">#define  ADC_SMPR1_SMP17                     ((u32)0x00E00000)        </span><span class="comment">/* SMP17[2:0] bits (Channel 17 Sample time selection) */</span>
    3277. 

  3277. <a name="l03245"></a>03245 <span class="preprocessor">#define  ADC_SMPR1_SMP17_0                   ((u32)0x00200000)        </span><span class="comment">/* Bit 0 */</span>
    3278. 

  3278. <a name="l03246"></a>03246 <span class="preprocessor">#define  ADC_SMPR1_SMP17_1                   ((u32)0x00400000)        </span><span class="comment">/* Bit 1 */</span>
    3279. 

  3279. <a name="l03247"></a>03247 <span class="preprocessor">#define  ADC_SMPR1_SMP17_2                   ((u32)0x00800000)        </span><span class="comment">/* Bit 2 */</span>
    3280. 

  3280. <a name="l03248"></a>03248 
    3281. 

  3281. <a name="l03249"></a>03249 
    3282. 

  3282. <a name="l03250"></a>03250 <span class="comment">/******************  Bit definition for ADC_SMPR2 register  *******************/</span>
    3283. 

  3283. <a name="l03251"></a>03251 <span class="preprocessor">#define  ADC_SMPR2_SMP0                      ((u32)0x00000007)        </span><span class="comment">/* SMP0[2:0] bits (Channel 0 Sample time selection) */</span>
    3284. 

  3284. <a name="l03252"></a>03252 <span class="preprocessor">#define  ADC_SMPR2_SMP0_0                    ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3285. 

  3285. <a name="l03253"></a>03253 <span class="preprocessor">#define  ADC_SMPR2_SMP0_1                    ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3286. 

  3286. <a name="l03254"></a>03254 <span class="preprocessor">#define  ADC_SMPR2_SMP0_2                    ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3287. 

  3287. <a name="l03255"></a>03255 
    3288. 

  3288. <a name="l03256"></a>03256 <span class="preprocessor">#define  ADC_SMPR2_SMP1                      ((u32)0x00000038)        </span><span class="comment">/* SMP1[2:0] bits (Channel 1 Sample time selection) */</span>
    3289. 

  3289. <a name="l03257"></a>03257 <span class="preprocessor">#define  ADC_SMPR2_SMP1_0                    ((u32)0x00000008)        </span><span class="comment">/* Bit 0 */</span>
    3290. 

  3290. <a name="l03258"></a>03258 <span class="preprocessor">#define  ADC_SMPR2_SMP1_1                    ((u32)0x00000010)        </span><span class="comment">/* Bit 1 */</span>
    3291. 

  3291. <a name="l03259"></a>03259 <span class="preprocessor">#define  ADC_SMPR2_SMP1_2                    ((u32)0x00000020)        </span><span class="comment">/* Bit 2 */</span>
    3292. 

  3292. <a name="l03260"></a>03260 
    3293. 

  3293. <a name="l03261"></a>03261 <span class="preprocessor">#define  ADC_SMPR2_SMP2                      ((u32)0x000001C0)        </span><span class="comment">/* SMP2[2:0] bits (Channel 2 Sample time selection) */</span>
    3294. 

  3294. <a name="l03262"></a>03262 <span class="preprocessor">#define  ADC_SMPR2_SMP2_0                    ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    3295. 

  3295. <a name="l03263"></a>03263 <span class="preprocessor">#define  ADC_SMPR2_SMP2_1                    ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    3296. 

  3296. <a name="l03264"></a>03264 <span class="preprocessor">#define  ADC_SMPR2_SMP2_2                    ((u32)0x00000100)        </span><span class="comment">/* Bit 2 */</span>
    3297. 

  3297. <a name="l03265"></a>03265 
    3298. 

  3298. <a name="l03266"></a>03266 <span class="preprocessor">#define  ADC_SMPR2_SMP3                      ((u32)0x00000E00)        </span><span class="comment">/* SMP3[2:0] bits (Channel 3 Sample time selection) */</span>
    3299. 

  3299. <a name="l03267"></a>03267 <span class="preprocessor">#define  ADC_SMPR2_SMP3_0                    ((u32)0x00000200)        </span><span class="comment">/* Bit 0 */</span>
    3300. 

  3300. <a name="l03268"></a>03268 <span class="preprocessor">#define  ADC_SMPR2_SMP3_1                    ((u32)0x00000400)        </span><span class="comment">/* Bit 1 */</span>
    3301. 

  3301. <a name="l03269"></a>03269 <span class="preprocessor">#define  ADC_SMPR2_SMP3_2                    ((u32)0x00000800)        </span><span class="comment">/* Bit 2 */</span>
    3302. 

  3302. <a name="l03270"></a>03270 
    3303. 

  3303. <a name="l03271"></a>03271 <span class="preprocessor">#define  ADC_SMPR2_SMP4                      ((u32)0x00007000)        </span><span class="comment">/* SMP4[2:0] bits (Channel 4 Sample time selection) */</span>
    3304. 

  3304. <a name="l03272"></a>03272 <span class="preprocessor">#define  ADC_SMPR2_SMP4_0                    ((u32)0x00001000)        </span><span class="comment">/* Bit 0 */</span>
    3305. 

  3305. <a name="l03273"></a>03273 <span class="preprocessor">#define  ADC_SMPR2_SMP4_1                    ((u32)0x00002000)        </span><span class="comment">/* Bit 1 */</span>
    3306. 

  3306. <a name="l03274"></a>03274 <span class="preprocessor">#define  ADC_SMPR2_SMP4_2                    ((u32)0x00004000)        </span><span class="comment">/* Bit 2 */</span>
    3307. 

  3307. <a name="l03275"></a>03275 
    3308. 

  3308. <a name="l03276"></a>03276 <span class="preprocessor">#define  ADC_SMPR2_SMP5                      ((u32)0x00038000)        </span><span class="comment">/* SMP5[2:0] bits (Channel 5 Sample time selection) */</span>
    3309. 

  3309. <a name="l03277"></a>03277 <span class="preprocessor">#define  ADC_SMPR2_SMP5_0                    ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3310. 

  3310. <a name="l03278"></a>03278 <span class="preprocessor">#define  ADC_SMPR2_SMP5_1                    ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3311. 

  3311. <a name="l03279"></a>03279 <span class="preprocessor">#define  ADC_SMPR2_SMP5_2                    ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3312. 

  3312. <a name="l03280"></a>03280 
    3313. 

  3313. <a name="l03281"></a>03281 <span class="preprocessor">#define  ADC_SMPR2_SMP6                      ((u32)0x001C0000)        </span><span class="comment">/* SMP6[2:0] bits (Channel 6 Sample time selection) */</span>
    3314. 

  3314. <a name="l03282"></a>03282 <span class="preprocessor">#define  ADC_SMPR2_SMP6_0                    ((u32)0x00040000)        </span><span class="comment">/* Bit 0 */</span>
    3315. 

  3315. <a name="l03283"></a>03283 <span class="preprocessor">#define  ADC_SMPR2_SMP6_1                    ((u32)0x00080000)        </span><span class="comment">/* Bit 1 */</span>
    3316. 

  3316. <a name="l03284"></a>03284 <span class="preprocessor">#define  ADC_SMPR2_SMP6_2                    ((u32)0x00100000)        </span><span class="comment">/* Bit 2 */</span>
    3317. 

  3317. <a name="l03285"></a>03285 
    3318. 

  3318. <a name="l03286"></a>03286 <span class="preprocessor">#define  ADC_SMPR2_SMP7                      ((u32)0x00E00000)        </span><span class="comment">/* SMP7[2:0] bits (Channel 7 Sample time selection) */</span>
    3319. 

  3319. <a name="l03287"></a>03287 <span class="preprocessor">#define  ADC_SMPR2_SMP7_0                    ((u32)0x00200000)        </span><span class="comment">/* Bit 0 */</span>
    3320. 

  3320. <a name="l03288"></a>03288 <span class="preprocessor">#define  ADC_SMPR2_SMP7_1                    ((u32)0x00400000)        </span><span class="comment">/* Bit 1 */</span>
    3321. 

  3321. <a name="l03289"></a>03289 <span class="preprocessor">#define  ADC_SMPR2_SMP7_2                    ((u32)0x00800000)        </span><span class="comment">/* Bit 2 */</span>
    3322. 

  3322. <a name="l03290"></a>03290 
    3323. 

  3323. <a name="l03291"></a>03291 <span class="preprocessor">#define  ADC_SMPR2_SMP8                      ((u32)0x07000000)        </span><span class="comment">/* SMP8[2:0] bits (Channel 8 Sample time selection) */</span>
    3324. 

  3324. <a name="l03292"></a>03292 <span class="preprocessor">#define  ADC_SMPR2_SMP8_0                    ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    3325. 

  3325. <a name="l03293"></a>03293 <span class="preprocessor">#define  ADC_SMPR2_SMP8_1                    ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    3326. 

  3326. <a name="l03294"></a>03294 <span class="preprocessor">#define  ADC_SMPR2_SMP8_2                    ((u32)0x04000000)        </span><span class="comment">/* Bit 2 */</span>
    3327. 

  3327. <a name="l03295"></a>03295 
    3328. 

  3328. <a name="l03296"></a>03296 <span class="preprocessor">#define  ADC_SMPR2_SMP9                      ((u32)0x38000000)        </span><span class="comment">/* SMP9[2:0] bits (Channel 9 Sample time selection) */</span>
    3329. 

  3329. <a name="l03297"></a>03297 <span class="preprocessor">#define  ADC_SMPR2_SMP9_0                    ((u32)0x08000000)        </span><span class="comment">/* Bit 0 */</span>
    3330. 

  3330. <a name="l03298"></a>03298 <span class="preprocessor">#define  ADC_SMPR2_SMP9_1                    ((u32)0x10000000)        </span><span class="comment">/* Bit 1 */</span>
    3331. 

  3331. <a name="l03299"></a>03299 <span class="preprocessor">#define  ADC_SMPR2_SMP9_2                    ((u32)0x20000000)        </span><span class="comment">/* Bit 2 */</span>
    3332. 

  3332. <a name="l03300"></a>03300 
    3333. 

  3333. <a name="l03301"></a>03301 
    3334. 

  3334. <a name="l03302"></a>03302 <span class="comment">/******************  Bit definition for ADC_JOFR1 register  *******************/</span>
    3335. 

  3335. <a name="l03303"></a>03303 <span class="preprocessor">#define  ADC_JOFR1_JOFFSET1                  ((u16)0x0FFF)            </span><span class="comment">/* Data offset for injected channel 1 */</span>
    3336. 

  3336. <a name="l03304"></a>03304 
    3337. 

  3337. <a name="l03305"></a>03305 
    3338. 

  3338. <a name="l03306"></a>03306 <span class="comment">/******************  Bit definition for ADC_JOFR2 register  *******************/</span>
    3339. 

  3339. <a name="l03307"></a>03307 <span class="preprocessor">#define  ADC_JOFR2_JOFFSET2                  ((u16)0x0FFF)            </span><span class="comment">/* Data offset for injected channel 2 */</span>
    3340. 

  3340. <a name="l03308"></a>03308 
    3341. 

  3341. <a name="l03309"></a>03309 
    3342. 

  3342. <a name="l03310"></a>03310 <span class="comment">/******************  Bit definition for ADC_JOFR3 register  *******************/</span>
    3343. 

  3343. <a name="l03311"></a>03311 <span class="preprocessor">#define  ADC_JOFR3_JOFFSET3                  ((u16)0x0FFF)            </span><span class="comment">/* Data offset for injected channel 3 */</span>
    3344. 

  3344. <a name="l03312"></a>03312 
    3345. 

  3345. <a name="l03313"></a>03313 
    3346. 

  3346. <a name="l03314"></a>03314 <span class="comment">/******************  Bit definition for ADC_JOFR4 register  *******************/</span>
    3347. 

  3347. <a name="l03315"></a>03315 <span class="preprocessor">#define  ADC_JOFR4_JOFFSET4                  ((u16)0x0FFF)            </span><span class="comment">/* Data offset for injected channel 4 */</span>
    3348. 

  3348. <a name="l03316"></a>03316 
    3349. 

  3349. <a name="l03317"></a>03317 
    3350. 

  3350. <a name="l03318"></a>03318 <span class="comment">/*******************  Bit definition for ADC_HTR register  ********************/</span>
    3351. 

  3351. <a name="l03319"></a>03319 <span class="preprocessor">#define  ADC_HTR_HT                          ((u16)0x0FFF)            </span><span class="comment">/* Analog watchdog high threshold */</span>
    3352. 

  3352. <a name="l03320"></a>03320 
    3353. 

  3353. <a name="l03321"></a>03321 
    3354. 

  3354. <a name="l03322"></a>03322 <span class="comment">/*******************  Bit definition for ADC_LTR register  ********************/</span>
    3355. 

  3355. <a name="l03323"></a>03323 <span class="preprocessor">#define  ADC_LTR_LT                          ((u16)0x0FFF)            </span><span class="comment">/* Analog watchdog low threshold */</span>
    3356. 

  3356. <a name="l03324"></a>03324 
    3357. 

  3357. <a name="l03325"></a>03325 
    3358. 

  3358. <a name="l03326"></a>03326 <span class="comment">/*******************  Bit definition for ADC_SQR1 register  *******************/</span>
    3359. 

  3359. <a name="l03327"></a>03327 <span class="preprocessor">#define  ADC_SQR1_SQ13                       ((u32)0x0000001F)        </span><span class="comment">/* SQ13[4:0] bits (13th conversion in regular sequence) */</span>
    3360. 

  3360. <a name="l03328"></a>03328 <span class="preprocessor">#define  ADC_SQR1_SQ13_0                     ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3361. 

  3361. <a name="l03329"></a>03329 <span class="preprocessor">#define  ADC_SQR1_SQ13_1                     ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3362. 

  3362. <a name="l03330"></a>03330 <span class="preprocessor">#define  ADC_SQR1_SQ13_2                     ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3363. 

  3363. <a name="l03331"></a>03331 <span class="preprocessor">#define  ADC_SQR1_SQ13_3                     ((u32)0x00000008)        </span><span class="comment">/* Bit 3 */</span>
    3364. 

  3364. <a name="l03332"></a>03332 <span class="preprocessor">#define  ADC_SQR1_SQ13_4                     ((u32)0x00000010)        </span><span class="comment">/* Bit 4 */</span>
    3365. 

  3365. <a name="l03333"></a>03333 
    3366. 

  3366. <a name="l03334"></a>03334 <span class="preprocessor">#define  ADC_SQR1_SQ14                       ((u32)0x000003E0)        </span><span class="comment">/* SQ14[4:0] bits (14th conversion in regular sequence) */</span>
    3367. 

  3367. <a name="l03335"></a>03335 <span class="preprocessor">#define  ADC_SQR1_SQ14_0                     ((u32)0x00000020)        </span><span class="comment">/* Bit 0 */</span>
    3368. 

  3368. <a name="l03336"></a>03336 <span class="preprocessor">#define  ADC_SQR1_SQ14_1                     ((u32)0x00000040)        </span><span class="comment">/* Bit 1 */</span>
    3369. 

  3369. <a name="l03337"></a>03337 <span class="preprocessor">#define  ADC_SQR1_SQ14_2                     ((u32)0x00000080)        </span><span class="comment">/* Bit 2 */</span>
    3370. 

  3370. <a name="l03338"></a>03338 <span class="preprocessor">#define  ADC_SQR1_SQ14_3                     ((u32)0x00000100)        </span><span class="comment">/* Bit 3 */</span>
    3371. 

  3371. <a name="l03339"></a>03339 <span class="preprocessor">#define  ADC_SQR1_SQ14_4                     ((u32)0x00000200)        </span><span class="comment">/* Bit 4 */</span>
    3372. 

  3372. <a name="l03340"></a>03340 
    3373. 

  3373. <a name="l03341"></a>03341 <span class="preprocessor">#define  ADC_SQR1_SQ15                       ((u32)0x00007C00)        </span><span class="comment">/* SQ15[4:0] bits (15th conversion in regular sequence) */</span>
    3374. 

  3374. <a name="l03342"></a>03342 <span class="preprocessor">#define  ADC_SQR1_SQ15_0                     ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    3375. 

  3375. <a name="l03343"></a>03343 <span class="preprocessor">#define  ADC_SQR1_SQ15_1                     ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    3376. 

  3376. <a name="l03344"></a>03344 <span class="preprocessor">#define  ADC_SQR1_SQ15_2                     ((u32)0x00001000)        </span><span class="comment">/* Bit 2 */</span>
    3377. 

  3377. <a name="l03345"></a>03345 <span class="preprocessor">#define  ADC_SQR1_SQ15_3                     ((u32)0x00002000)        </span><span class="comment">/* Bit 3 */</span>
    3378. 

  3378. <a name="l03346"></a>03346 <span class="preprocessor">#define  ADC_SQR1_SQ15_4                     ((u32)0x00004000)        </span><span class="comment">/* Bit 4 */</span>
    3379. 

  3379. <a name="l03347"></a>03347 
    3380. 

  3380. <a name="l03348"></a>03348 <span class="preprocessor">#define  ADC_SQR1_SQ16                       ((u32)0x000F8000)        </span><span class="comment">/* SQ16[4:0] bits (16th conversion in regular sequence) */</span>
    3381. 

  3381. <a name="l03349"></a>03349 <span class="preprocessor">#define  ADC_SQR1_SQ16_0                     ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3382. 

  3382. <a name="l03350"></a>03350 <span class="preprocessor">#define  ADC_SQR1_SQ16_1                     ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3383. 

  3383. <a name="l03351"></a>03351 <span class="preprocessor">#define  ADC_SQR1_SQ16_2                     ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3384. 

  3384. <a name="l03352"></a>03352 <span class="preprocessor">#define  ADC_SQR1_SQ16_3                     ((u32)0x00040000)        </span><span class="comment">/* Bit 3 */</span>
    3385. 

  3385. <a name="l03353"></a>03353 <span class="preprocessor">#define  ADC_SQR1_SQ16_4                     ((u32)0x00080000)        </span><span class="comment">/* Bit 4 */</span>
    3386. 

  3386. <a name="l03354"></a>03354 
    3387. 

  3387. <a name="l03355"></a>03355 <span class="preprocessor">#define  ADC_SQR1_L                          ((u32)0x00F00000)        </span><span class="comment">/* L[3:0] bits (Regular channel sequence length) */</span>
    3388. 

  3388. <a name="l03356"></a>03356 <span class="preprocessor">#define  ADC_SQR1_L_0                        ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    3389. 

  3389. <a name="l03357"></a>03357 <span class="preprocessor">#define  ADC_SQR1_L_1                        ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    3390. 

  3390. <a name="l03358"></a>03358 <span class="preprocessor">#define  ADC_SQR1_L_2                        ((u32)0x00400000)        </span><span class="comment">/* Bit 2 */</span>
    3391. 

  3391. <a name="l03359"></a>03359 <span class="preprocessor">#define  ADC_SQR1_L_3                        ((u32)0x00800000)        </span><span class="comment">/* Bit 3 */</span>
    3392. 

  3392. <a name="l03360"></a>03360 
    3393. 

  3393. <a name="l03361"></a>03361 
    3394. 

  3394. <a name="l03362"></a>03362 <span class="comment">/*******************  Bit definition for ADC_SQR2 register  *******************/</span>
    3395. 

  3395. <a name="l03363"></a>03363 <span class="preprocessor">#define  ADC_SQR2_SQ7                        ((u32)0x0000001F)        </span><span class="comment">/* SQ7[4:0] bits (7th conversion in regular sequence) */</span>
    3396. 

  3396. <a name="l03364"></a>03364 <span class="preprocessor">#define  ADC_SQR2_SQ7_0                      ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3397. 

  3397. <a name="l03365"></a>03365 <span class="preprocessor">#define  ADC_SQR2_SQ7_1                      ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3398. 

  3398. <a name="l03366"></a>03366 <span class="preprocessor">#define  ADC_SQR2_SQ7_2                      ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3399. 

  3399. <a name="l03367"></a>03367 <span class="preprocessor">#define  ADC_SQR2_SQ7_3                      ((u32)0x00000008)        </span><span class="comment">/* Bit 3 */</span>
    3400. 

  3400. <a name="l03368"></a>03368 <span class="preprocessor">#define  ADC_SQR2_SQ7_4                      ((u32)0x00000010)        </span><span class="comment">/* Bit 4 */</span>
    3401. 

  3401. <a name="l03369"></a>03369 
    3402. 

  3402. <a name="l03370"></a>03370 <span class="preprocessor">#define  ADC_SQR2_SQ8                        ((u32)0x000003E0)        </span><span class="comment">/* SQ8[4:0] bits (8th conversion in regular sequence) */</span>
    3403. 

  3403. <a name="l03371"></a>03371 <span class="preprocessor">#define  ADC_SQR2_SQ8_0                      ((u32)0x00000020)        </span><span class="comment">/* Bit 0 */</span>
    3404. 

  3404. <a name="l03372"></a>03372 <span class="preprocessor">#define  ADC_SQR2_SQ8_1                      ((u32)0x00000040)        </span><span class="comment">/* Bit 1 */</span>
    3405. 

  3405. <a name="l03373"></a>03373 <span class="preprocessor">#define  ADC_SQR2_SQ8_2                      ((u32)0x00000080)        </span><span class="comment">/* Bit 2 */</span>
    3406. 

  3406. <a name="l03374"></a>03374 <span class="preprocessor">#define  ADC_SQR2_SQ8_3                      ((u32)0x00000100)        </span><span class="comment">/* Bit 3 */</span>
    3407. 

  3407. <a name="l03375"></a>03375 <span class="preprocessor">#define  ADC_SQR2_SQ8_4                      ((u32)0x00000200)        </span><span class="comment">/* Bit 4 */</span>
    3408. 

  3408. <a name="l03376"></a>03376 
    3409. 

  3409. <a name="l03377"></a>03377 <span class="preprocessor">#define  ADC_SQR2_SQ9                        ((u32)0x00007C00)        </span><span class="comment">/* SQ9[4:0] bits (9th conversion in regular sequence) */</span>
    3410. 

  3410. <a name="l03378"></a>03378 <span class="preprocessor">#define  ADC_SQR2_SQ9_0                      ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    3411. 

  3411. <a name="l03379"></a>03379 <span class="preprocessor">#define  ADC_SQR2_SQ9_1                      ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    3412. 

  3412. <a name="l03380"></a>03380 <span class="preprocessor">#define  ADC_SQR2_SQ9_2                      ((u32)0x00001000)        </span><span class="comment">/* Bit 2 */</span>
    3413. 

  3413. <a name="l03381"></a>03381 <span class="preprocessor">#define  ADC_SQR2_SQ9_3                      ((u32)0x00002000)        </span><span class="comment">/* Bit 3 */</span>
    3414. 

  3414. <a name="l03382"></a>03382 <span class="preprocessor">#define  ADC_SQR2_SQ9_4                      ((u32)0x00004000)        </span><span class="comment">/* Bit 4 */</span>
    3415. 

  3415. <a name="l03383"></a>03383 
    3416. 

  3416. <a name="l03384"></a>03384 <span class="preprocessor">#define  ADC_SQR2_SQ10                       ((u32)0x000F8000)        </span><span class="comment">/* SQ10[4:0] bits (10th conversion in regular sequence) */</span>
    3417. 

  3417. <a name="l03385"></a>03385 <span class="preprocessor">#define  ADC_SQR2_SQ10_0                     ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3418. 

  3418. <a name="l03386"></a>03386 <span class="preprocessor">#define  ADC_SQR2_SQ10_1                     ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3419. 

  3419. <a name="l03387"></a>03387 <span class="preprocessor">#define  ADC_SQR2_SQ10_2                     ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3420. 

  3420. <a name="l03388"></a>03388 <span class="preprocessor">#define  ADC_SQR2_SQ10_3                     ((u32)0x00040000)        </span><span class="comment">/* Bit 3 */</span>
    3421. 

  3421. <a name="l03389"></a>03389 <span class="preprocessor">#define  ADC_SQR2_SQ10_4                     ((u32)0x00080000)        </span><span class="comment">/* Bit 4 */</span>
    3422. 

  3422. <a name="l03390"></a>03390 
    3423. 

  3423. <a name="l03391"></a>03391 <span class="preprocessor">#define  ADC_SQR2_SQ11                       ((u32)0x01F00000)        </span><span class="comment">/* SQ11[4:0] bits (11th conversion in regular sequence) */</span>
    3424. 

  3424. <a name="l03392"></a>03392 <span class="preprocessor">#define  ADC_SQR2_SQ11_0                     ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    3425. 

  3425. <a name="l03393"></a>03393 <span class="preprocessor">#define  ADC_SQR2_SQ11_1                     ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    3426. 

  3426. <a name="l03394"></a>03394 <span class="preprocessor">#define  ADC_SQR2_SQ11_2                     ((u32)0x00400000)        </span><span class="comment">/* Bit 2 */</span>
    3427. 

  3427. <a name="l03395"></a>03395 <span class="preprocessor">#define  ADC_SQR2_SQ11_3                     ((u32)0x00800000)        </span><span class="comment">/* Bit 3 */</span>
    3428. 

  3428. <a name="l03396"></a>03396 <span class="preprocessor">#define  ADC_SQR2_SQ11_4                     ((u32)0x01000000)        </span><span class="comment">/* Bit 4 */</span>
    3429. 

  3429. <a name="l03397"></a>03397 
    3430. 

  3430. <a name="l03398"></a>03398 <span class="preprocessor">#define  ADC_SQR2_SQ12                       ((u32)0x3E000000)        </span><span class="comment">/* SQ12[4:0] bits (12th conversion in regular sequence) */</span>
    3431. 

  3431. <a name="l03399"></a>03399 <span class="preprocessor">#define  ADC_SQR2_SQ12_0                     ((u32)0x02000000)        </span><span class="comment">/* Bit 0 */</span>
    3432. 

  3432. <a name="l03400"></a>03400 <span class="preprocessor">#define  ADC_SQR2_SQ12_1                     ((u32)0x04000000)        </span><span class="comment">/* Bit 1 */</span>
    3433. 

  3433. <a name="l03401"></a>03401 <span class="preprocessor">#define  ADC_SQR2_SQ12_2                     ((u32)0x08000000)        </span><span class="comment">/* Bit 2 */</span>
    3434. 

  3434. <a name="l03402"></a>03402 <span class="preprocessor">#define  ADC_SQR2_SQ12_3                     ((u32)0x10000000)        </span><span class="comment">/* Bit 3 */</span>
    3435. 

  3435. <a name="l03403"></a>03403 <span class="preprocessor">#define  ADC_SQR2_SQ12_4                     ((u32)0x20000000)        </span><span class="comment">/* Bit 4 */</span>
    3436. 

  3436. <a name="l03404"></a>03404 
    3437. 

  3437. <a name="l03405"></a>03405 
    3438. 

  3438. <a name="l03406"></a>03406 <span class="comment">/*******************  Bit definition for ADC_SQR3 register  *******************/</span>
    3439. 

  3439. <a name="l03407"></a>03407 <span class="preprocessor">#define  ADC_SQR3_SQ1                        ((u32)0x0000001F)        </span><span class="comment">/* SQ1[4:0] bits (1st conversion in regular sequence) */</span>
    3440. 

  3440. <a name="l03408"></a>03408 <span class="preprocessor">#define  ADC_SQR3_SQ1_0                      ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3441. 

  3441. <a name="l03409"></a>03409 <span class="preprocessor">#define  ADC_SQR3_SQ1_1                      ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3442. 

  3442. <a name="l03410"></a>03410 <span class="preprocessor">#define  ADC_SQR3_SQ1_2                      ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3443. 

  3443. <a name="l03411"></a>03411 <span class="preprocessor">#define  ADC_SQR3_SQ1_3                      ((u32)0x00000008)        </span><span class="comment">/* Bit 3 */</span>
    3444. 

  3444. <a name="l03412"></a>03412 <span class="preprocessor">#define  ADC_SQR3_SQ1_4                      ((u32)0x00000010)        </span><span class="comment">/* Bit 4 */</span>
    3445. 

  3445. <a name="l03413"></a>03413 
    3446. 

  3446. <a name="l03414"></a>03414 <span class="preprocessor">#define  ADC_SQR3_SQ2                        ((u32)0x000003E0)        </span><span class="comment">/* SQ2[4:0] bits (2nd conversion in regular sequence) */</span>
    3447. 

  3447. <a name="l03415"></a>03415 <span class="preprocessor">#define  ADC_SQR3_SQ2_0                      ((u32)0x00000020)        </span><span class="comment">/* Bit 0 */</span>
    3448. 

  3448. <a name="l03416"></a>03416 <span class="preprocessor">#define  ADC_SQR3_SQ2_1                      ((u32)0x00000040)        </span><span class="comment">/* Bit 1 */</span>
    3449. 

  3449. <a name="l03417"></a>03417 <span class="preprocessor">#define  ADC_SQR3_SQ2_2                      ((u32)0x00000080)        </span><span class="comment">/* Bit 2 */</span>
    3450. 

  3450. <a name="l03418"></a>03418 <span class="preprocessor">#define  ADC_SQR3_SQ2_3                      ((u32)0x00000100)        </span><span class="comment">/* Bit 3 */</span>
    3451. 

  3451. <a name="l03419"></a>03419 <span class="preprocessor">#define  ADC_SQR3_SQ2_4                      ((u32)0x00000200)        </span><span class="comment">/* Bit 4 */</span>
    3452. 

  3452. <a name="l03420"></a>03420 
    3453. 

  3453. <a name="l03421"></a>03421 <span class="preprocessor">#define  ADC_SQR3_SQ3                        ((u32)0x00007C00)        </span><span class="comment">/* SQ3[4:0] bits (3rd conversion in regular sequence) */</span>
    3454. 

  3454. <a name="l03422"></a>03422 <span class="preprocessor">#define  ADC_SQR3_SQ3_0                      ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    3455. 

  3455. <a name="l03423"></a>03423 <span class="preprocessor">#define  ADC_SQR3_SQ3_1                      ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    3456. 

  3456. <a name="l03424"></a>03424 <span class="preprocessor">#define  ADC_SQR3_SQ3_2                      ((u32)0x00001000)        </span><span class="comment">/* Bit 2 */</span>
    3457. 

  3457. <a name="l03425"></a>03425 <span class="preprocessor">#define  ADC_SQR3_SQ3_3                      ((u32)0x00002000)        </span><span class="comment">/* Bit 3 */</span>
    3458. 

  3458. <a name="l03426"></a>03426 <span class="preprocessor">#define  ADC_SQR3_SQ3_4                      ((u32)0x00004000)        </span><span class="comment">/* Bit 4 */</span>
    3459. 

  3459. <a name="l03427"></a>03427 
    3460. 

  3460. <a name="l03428"></a>03428 <span class="preprocessor">#define  ADC_SQR3_SQ4                        ((u32)0x000F8000)        </span><span class="comment">/* SQ4[4:0] bits (4th conversion in regular sequence) */</span>
    3461. 

  3461. <a name="l03429"></a>03429 <span class="preprocessor">#define  ADC_SQR3_SQ4_0                      ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3462. 

  3462. <a name="l03430"></a>03430 <span class="preprocessor">#define  ADC_SQR3_SQ4_1                      ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3463. 

  3463. <a name="l03431"></a>03431 <span class="preprocessor">#define  ADC_SQR3_SQ4_2                      ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3464. 

  3464. <a name="l03432"></a>03432 <span class="preprocessor">#define  ADC_SQR3_SQ4_3                      ((u32)0x00040000)        </span><span class="comment">/* Bit 3 */</span>
    3465. 

  3465. <a name="l03433"></a>03433 <span class="preprocessor">#define  ADC_SQR3_SQ4_4                      ((u32)0x00080000)        </span><span class="comment">/* Bit 4 */</span>
    3466. 

  3466. <a name="l03434"></a>03434 
    3467. 

  3467. <a name="l03435"></a>03435 <span class="preprocessor">#define  ADC_SQR3_SQ5                        ((u32)0x01F00000)        </span><span class="comment">/* SQ5[4:0] bits (5th conversion in regular sequence) */</span>
    3468. 

  3468. <a name="l03436"></a>03436 <span class="preprocessor">#define  ADC_SQR3_SQ5_0                      ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    3469. 

  3469. <a name="l03437"></a>03437 <span class="preprocessor">#define  ADC_SQR3_SQ5_1                      ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    3470. 

  3470. <a name="l03438"></a>03438 <span class="preprocessor">#define  ADC_SQR3_SQ5_2                      ((u32)0x00400000)        </span><span class="comment">/* Bit 2 */</span>
    3471. 

  3471. <a name="l03439"></a>03439 <span class="preprocessor">#define  ADC_SQR3_SQ5_3                      ((u32)0x00800000)        </span><span class="comment">/* Bit 3 */</span>
    3472. 

  3472. <a name="l03440"></a>03440 <span class="preprocessor">#define  ADC_SQR3_SQ5_4                      ((u32)0x01000000)        </span><span class="comment">/* Bit 4 */</span>
    3473. 

  3473. <a name="l03441"></a>03441 
    3474. 

  3474. <a name="l03442"></a>03442 <span class="preprocessor">#define  ADC_SQR3_SQ6                        ((u32)0x3E000000)        </span><span class="comment">/* SQ6[4:0] bits (6th conversion in regular sequence) */</span>
    3475. 

  3475. <a name="l03443"></a>03443 <span class="preprocessor">#define  ADC_SQR3_SQ6_0                      ((u32)0x02000000)        </span><span class="comment">/* Bit 0 */</span>
    3476. 

  3476. <a name="l03444"></a>03444 <span class="preprocessor">#define  ADC_SQR3_SQ6_1                      ((u32)0x04000000)        </span><span class="comment">/* Bit 1 */</span>
    3477. 

  3477. <a name="l03445"></a>03445 <span class="preprocessor">#define  ADC_SQR3_SQ6_2                      ((u32)0x08000000)        </span><span class="comment">/* Bit 2 */</span>
    3478. 

  3478. <a name="l03446"></a>03446 <span class="preprocessor">#define  ADC_SQR3_SQ6_3                      ((u32)0x10000000)        </span><span class="comment">/* Bit 3 */</span>
    3479. 

  3479. <a name="l03447"></a>03447 <span class="preprocessor">#define  ADC_SQR3_SQ6_4                      ((u32)0x20000000)        </span><span class="comment">/* Bit 4 */</span>
    3480. 

  3480. <a name="l03448"></a>03448 
    3481. 

  3481. <a name="l03449"></a>03449 
    3482. 

  3482. <a name="l03450"></a>03450 <span class="comment">/*******************  Bit definition for ADC_JSQR register  *******************/</span>
    3483. 

  3483. <a name="l03451"></a>03451 <span class="preprocessor">#define  ADC_JSQR_JSQ1                       ((u32)0x0000001F)        </span><span class="comment">/* JSQ1[4:0] bits (1st conversion in injected sequence) */</span>  
    3484. 

  3484. <a name="l03452"></a>03452 <span class="preprocessor">#define  ADC_JSQR_JSQ1_0                     ((u32)0x00000001)        </span><span class="comment">/* Bit 0 */</span>
    3485. 

  3485. <a name="l03453"></a>03453 <span class="preprocessor">#define  ADC_JSQR_JSQ1_1                     ((u32)0x00000002)        </span><span class="comment">/* Bit 1 */</span>
    3486. 

  3486. <a name="l03454"></a>03454 <span class="preprocessor">#define  ADC_JSQR_JSQ1_2                     ((u32)0x00000004)        </span><span class="comment">/* Bit 2 */</span>
    3487. 

  3487. <a name="l03455"></a>03455 <span class="preprocessor">#define  ADC_JSQR_JSQ1_3                     ((u32)0x00000008)        </span><span class="comment">/* Bit 3 */</span>
    3488. 

  3488. <a name="l03456"></a>03456 <span class="preprocessor">#define  ADC_JSQR_JSQ1_4                     ((u32)0x00000010)        </span><span class="comment">/* Bit 4 */</span>
    3489. 

  3489. <a name="l03457"></a>03457 
    3490. 

  3490. <a name="l03458"></a>03458 <span class="preprocessor">#define  ADC_JSQR_JSQ2                       ((u32)0x000003E0)        </span><span class="comment">/* JSQ2[4:0] bits (2nd conversion in injected sequence) */</span>
    3491. 

  3491. <a name="l03459"></a>03459 <span class="preprocessor">#define  ADC_JSQR_JSQ2_0                     ((u32)0x00000020)        </span><span class="comment">/* Bit 0 */</span>
    3492. 

  3492. <a name="l03460"></a>03460 <span class="preprocessor">#define  ADC_JSQR_JSQ2_1                     ((u32)0x00000040)        </span><span class="comment">/* Bit 1 */</span>
    3493. 

  3493. <a name="l03461"></a>03461 <span class="preprocessor">#define  ADC_JSQR_JSQ2_2                     ((u32)0x00000080)        </span><span class="comment">/* Bit 2 */</span>
    3494. 

  3494. <a name="l03462"></a>03462 <span class="preprocessor">#define  ADC_JSQR_JSQ2_3                     ((u32)0x00000100)        </span><span class="comment">/* Bit 3 */</span>
    3495. 

  3495. <a name="l03463"></a>03463 <span class="preprocessor">#define  ADC_JSQR_JSQ2_4                     ((u32)0x00000200)        </span><span class="comment">/* Bit 4 */</span>
    3496. 

  3496. <a name="l03464"></a>03464 
    3497. 

  3497. <a name="l03465"></a>03465 <span class="preprocessor">#define  ADC_JSQR_JSQ3                       ((u32)0x00007C00)        </span><span class="comment">/* JSQ3[4:0] bits (3rd conversion in injected sequence) */</span>
    3498. 

  3498. <a name="l03466"></a>03466 <span class="preprocessor">#define  ADC_JSQR_JSQ3_0                     ((u32)0x00000400)        </span><span class="comment">/* Bit 0 */</span>
    3499. 

  3499. <a name="l03467"></a>03467 <span class="preprocessor">#define  ADC_JSQR_JSQ3_1                     ((u32)0x00000800)        </span><span class="comment">/* Bit 1 */</span>
    3500. 

  3500. <a name="l03468"></a>03468 <span class="preprocessor">#define  ADC_JSQR_JSQ3_2                     ((u32)0x00001000)        </span><span class="comment">/* Bit 2 */</span>
    3501. 

  3501. <a name="l03469"></a>03469 <span class="preprocessor">#define  ADC_JSQR_JSQ3_3                     ((u32)0x00002000)        </span><span class="comment">/* Bit 3 */</span>
    3502. 

  3502. <a name="l03470"></a>03470 <span class="preprocessor">#define  ADC_JSQR_JSQ3_4                     ((u32)0x00004000)        </span><span class="comment">/* Bit 4 */</span>
    3503. 

  3503. <a name="l03471"></a>03471 
    3504. 

  3504. <a name="l03472"></a>03472 <span class="preprocessor">#define  ADC_JSQR_JSQ4                       ((u32)0x000F8000)        </span><span class="comment">/* JSQ4[4:0] bits (4th conversion in injected sequence) */</span>
    3505. 

  3505. <a name="l03473"></a>03473 <span class="preprocessor">#define  ADC_JSQR_JSQ4_0                     ((u32)0x00008000)        </span><span class="comment">/* Bit 0 */</span>
    3506. 

  3506. <a name="l03474"></a>03474 <span class="preprocessor">#define  ADC_JSQR_JSQ4_1                     ((u32)0x00010000)        </span><span class="comment">/* Bit 1 */</span>
    3507. 

  3507. <a name="l03475"></a>03475 <span class="preprocessor">#define  ADC_JSQR_JSQ4_2                     ((u32)0x00020000)        </span><span class="comment">/* Bit 2 */</span>
    3508. 

  3508. <a name="l03476"></a>03476 <span class="preprocessor">#define  ADC_JSQR_JSQ4_3                     ((u32)0x00040000)        </span><span class="comment">/* Bit 3 */</span>
    3509. 

  3509. <a name="l03477"></a>03477 <span class="preprocessor">#define  ADC_JSQR_JSQ4_4                     ((u32)0x00080000)        </span><span class="comment">/* Bit 4 */</span>
    3510. 

  3510. <a name="l03478"></a>03478 
    3511. 

  3511. <a name="l03479"></a>03479 <span class="preprocessor">#define  ADC_JSQR_JL                         ((u32)0x00300000)        </span><span class="comment">/* JL[1:0] bits (Injected Sequence length) */</span>
    3512. 

  3512. <a name="l03480"></a>03480 <span class="preprocessor">#define  ADC_JSQR_JL_0                       ((u32)0x00100000)        </span><span class="comment">/* Bit 0 */</span>
    3513. 

  3513. <a name="l03481"></a>03481 <span class="preprocessor">#define  ADC_JSQR_JL_1                       ((u32)0x00200000)        </span><span class="comment">/* Bit 1 */</span>
    3514. 

  3514. <a name="l03482"></a>03482 
    3515. 

  3515. <a name="l03483"></a>03483 
    3516. 

  3516. <a name="l03484"></a>03484 <span class="comment">/*******************  Bit definition for ADC_JDR1 register  *******************/</span>
    3517. 

  3517. <a name="l03485"></a>03485 <span class="preprocessor">#define  ADC_JDR1_JDATA                      ((u16)0xFFFF)            </span><span class="comment">/* Injected data */</span>
    3518. 

  3518. <a name="l03486"></a>03486 
    3519. 

  3519. <a name="l03487"></a>03487 
    3520. 

  3520. <a name="l03488"></a>03488 <span class="comment">/*******************  Bit definition for ADC_JDR2 register  *******************/</span>
    3521. 

  3521. <a name="l03489"></a>03489 <span class="preprocessor">#define  ADC_JDR2_JDATA                      ((u16)0xFFFF)            </span><span class="comment">/* Injected data */</span>
    3522. 

  3522. <a name="l03490"></a>03490 
    3523. 

  3523. <a name="l03491"></a>03491 
    3524. 

  3524. <a name="l03492"></a>03492 <span class="comment">/*******************  Bit definition for ADC_JDR3 register  *******************/</span>
    3525. 

  3525. <a name="l03493"></a>03493 <span class="preprocessor">#define  ADC_JDR3_JDATA                      ((u16)0xFFFF)            </span><span class="comment">/* Injected data */</span>
    3526. 

  3526. <a name="l03494"></a>03494 
    3527. 

  3527. <a name="l03495"></a>03495 
    3528. 

  3528. <a name="l03496"></a>03496 <span class="comment">/*******************  Bit definition for ADC_JDR4 register  *******************/</span>
    3529. 

  3529. <a name="l03497"></a>03497 <span class="preprocessor">#define  ADC_JDR4_JDATA                      ((u16)0xFFFF)            </span><span class="comment">/* Injected data */</span>
    3530. 

  3530. <a name="l03498"></a>03498 
    3531. 

  3531. <a name="l03499"></a>03499 
    3532. 

  3532. <a name="l03500"></a>03500 <span class="comment">/********************  Bit definition for ADC_DR register  ********************/</span>
    3533. 

  3533. <a name="l03501"></a>03501 <span class="preprocessor">#define  ADC_DR_DATA                         ((u32)0x0000FFFF)        </span><span class="comment">/* Regular data */</span>
    3534. 

  3534. <a name="l03502"></a>03502 <span class="preprocessor">#define  ADC_DR_ADC2DATA                     ((u32)0xFFFF0000)        </span><span class="comment">/* ADC2 data */</span>
    3535. 

  3535. <a name="l03503"></a>03503 
    3536. 

  3536. <a name="l03504"></a>03504 
    3537. 

  3537. <a name="l03505"></a>03505 
    3538. 

  3538. <a name="l03506"></a>03506 <span class="comment">/******************************************************************************/</span>
    3539. 

  3539. <a name="l03507"></a>03507 <span class="comment">/*                                                                            */</span>
    3540. 

  3540. <a name="l03508"></a>03508 <span class="comment">/*                      Digital to Analog Converter                           */</span>
    3541. 

  3541. <a name="l03509"></a>03509 <span class="comment">/*                                                                            */</span>
    3542. 

  3542. <a name="l03510"></a>03510 <span class="comment">/******************************************************************************/</span>
    3543. 

  3543. <a name="l03511"></a>03511 
    3544. 

  3544. <a name="l03512"></a>03512 <span class="comment">/********************  Bit definition for DAC_CR register  ********************/</span>
    3545. 

  3545. <a name="l03513"></a>03513 <span class="preprocessor">#define  DAC_CR_EN1                          ((u32)0x00000001)        </span><span class="comment">/* DAC channel1 enable */</span>
    3546. 

  3546. <a name="l03514"></a>03514 <span class="preprocessor">#define  DAC_CR_BOFF1                        ((u32)0x00000002)        </span><span class="comment">/* DAC channel1 output buffer disable */</span>
    3547. 

  3547. <a name="l03515"></a>03515 <span class="preprocessor">#define  DAC_CR_TEN1                         ((u32)0x00000004)        </span><span class="comment">/* DAC channel1 Trigger enable */</span>
    3548. 

  3548. <a name="l03516"></a>03516 
    3549. 

  3549. <a name="l03517"></a>03517 <span class="preprocessor">#define  DAC_CR_TSEL1                        ((u32)0x00000038)        </span><span class="comment">/* TSEL1[2:0] (DAC channel1 Trigger selection) */</span>
    3550. 

  3550. <a name="l03518"></a>03518 <span class="preprocessor">#define  DAC_CR_TSEL1_0                      ((u32)0x00000008)        </span><span class="comment">/* Bit 0 */</span>
    3551. 

  3551. <a name="l03519"></a>03519 <span class="preprocessor">#define  DAC_CR_TSEL1_1                      ((u32)0x00000010)        </span><span class="comment">/* Bit 1 */</span>
    3552. 

  3552. <a name="l03520"></a>03520 <span class="preprocessor">#define  DAC_CR_TSEL1_2                      ((u32)0x00000020)        </span><span class="comment">/* Bit 2 */</span>
    3553. 

  3553. <a name="l03521"></a>03521 
    3554. 

  3554. <a name="l03522"></a>03522 <span class="preprocessor">#define  DAC_CR_WAVE1                        ((u32)0x000000C0)        </span><span class="comment">/* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */</span>
    3555. 

  3555. <a name="l03523"></a>03523 <span class="preprocessor">#define  DAC_CR_WAVE1_0                      ((u32)0x00000040)        </span><span class="comment">/* Bit 0 */</span>
    3556. 

  3556. <a name="l03524"></a>03524 <span class="preprocessor">#define  DAC_CR_WAVE1_1                      ((u32)0x00000080)        </span><span class="comment">/* Bit 1 */</span>
    3557. 

  3557. <a name="l03525"></a>03525 
    3558. 

  3558. <a name="l03526"></a>03526 <span class="preprocessor">#define  DAC_CR_MAMP1                        ((u32)0x00000F00)        </span><span class="comment">/* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */</span>
    3559. 

  3559. <a name="l03527"></a>03527 <span class="preprocessor">#define  DAC_CR_MAMP1_0                      ((u32)0x00000100)        </span><span class="comment">/* Bit 0 */</span>
    3560. 

  3560. <a name="l03528"></a>03528 <span class="preprocessor">#define  DAC_CR_MAMP1_1                      ((u32)0x00000200)        </span><span class="comment">/* Bit 1 */</span>
    3561. 

  3561. <a name="l03529"></a>03529 <span class="preprocessor">#define  DAC_CR_MAMP1_2                      ((u32)0x00000400)        </span><span class="comment">/* Bit 2 */</span>
    3562. 

  3562. <a name="l03530"></a>03530 <span class="preprocessor">#define  DAC_CR_MAMP1_3                      ((u32)0x00000800)        </span><span class="comment">/* Bit 3 */</span>
    3563. 

  3563. <a name="l03531"></a>03531 
    3564. 

  3564. <a name="l03532"></a>03532 <span class="preprocessor">#define  DAC_CR_DMAEN1                       ((u32)0x00001000)        </span><span class="comment">/* DAC channel1 DMA enable */</span>
    3565. 

  3565. <a name="l03533"></a>03533 <span class="preprocessor">#define  DAC_CR_EN2                          ((u32)0x00010000)        </span><span class="comment">/* DAC channel2 enable */</span>
    3566. 

  3566. <a name="l03534"></a>03534 <span class="preprocessor">#define  DAC_CR_BOFF2                        ((u32)0x00020000)        </span><span class="comment">/* DAC channel2 output buffer disable */</span>
    3567. 

  3567. <a name="l03535"></a>03535 <span class="preprocessor">#define  DAC_CR_TEN2                         ((u32)0x00040000)        </span><span class="comment">/* DAC channel2 Trigger enable */</span>
    3568. 

  3568. <a name="l03536"></a>03536 
    3569. 

  3569. <a name="l03537"></a>03537 <span class="preprocessor">#define  DAC_CR_TSEL2                        ((u32)0x00380000)        </span><span class="comment">/* TSEL2[2:0] (DAC channel2 Trigger selection) */</span>
    3570. 

  3570. <a name="l03538"></a>03538 <span class="preprocessor">#define  DAC_CR_TSEL2_0                      ((u32)0x00080000)        </span><span class="comment">/* Bit 0 */</span>
    3571. 

  3571. <a name="l03539"></a>03539 <span class="preprocessor">#define  DAC_CR_TSEL2_1                      ((u32)0x00100000)        </span><span class="comment">/* Bit 1 */</span>
    3572. 

  3572. <a name="l03540"></a>03540 <span class="preprocessor">#define  DAC_CR_TSEL2_2                      ((u32)0x00200000)        </span><span class="comment">/* Bit 2 */</span>
    3573. 

  3573. <a name="l03541"></a>03541 
    3574. 

  3574. <a name="l03542"></a>03542 <span class="preprocessor">#define  DAC_CR_WAVE2                        ((u32)0x00C00000)        </span><span class="comment">/* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */</span>
    3575. 

  3575. <a name="l03543"></a>03543 <span class="preprocessor">#define  DAC_CR_WAVE2_0                      ((u32)0x00400000)        </span><span class="comment">/* Bit 0 */</span>
    3576. 

  3576. <a name="l03544"></a>03544 <span class="preprocessor">#define  DAC_CR_WAVE2_1                      ((u32)0x00800000)        </span><span class="comment">/* Bit 1 */</span>
    3577. 

  3577. <a name="l03545"></a>03545 
    3578. 

  3578. <a name="l03546"></a>03546 <span class="preprocessor">#define  DAC_CR_MAMP2                        ((u32)0x0F000000)        </span><span class="comment">/* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */</span>
    3579. 

  3579. <a name="l03547"></a>03547 <span class="preprocessor">#define  DAC_CR_MAMP2_0                      ((u32)0x01000000)        </span><span class="comment">/* Bit 0 */</span>
    3580. 

  3580. <a name="l03548"></a>03548 <span class="preprocessor">#define  DAC_CR_MAMP2_1                      ((u32)0x02000000)        </span><span class="comment">/* Bit 1 */</span>
    3581. 

  3581. <a name="l03549"></a>03549 <span class="preprocessor">#define  DAC_CR_MAMP2_2                      ((u32)0x04000000)        </span><span class="comment">/* Bit 2 */</span>
    3582. 

  3582. <a name="l03550"></a>03550 <span class="preprocessor">#define  DAC_CR_MAMP2_3                      ((u32)0x08000000)        </span><span class="comment">/* Bit 3 */</span>
    3583. 

  3583. <a name="l03551"></a>03551 
    3584. 

  3584. <a name="l03552"></a>03552 <span class="preprocessor">#define  DAC_CR_DMAEN2                       ((u32)0x10000000)        </span><span class="comment">/* DAC channel2 DMA enabled */</span>
    3585. 

  3585. <a name="l03553"></a>03553 
    3586. 

  3586. <a name="l03554"></a>03554 
    3587. 

  3587. <a name="l03555"></a>03555 <span class="comment">/*****************  Bit definition for DAC_SWTRIGR register  ******************/</span>
    3588. 

  3588. <a name="l03556"></a>03556 <span class="preprocessor">#define  DAC_SWTRIGR_SWTRIG1                 ((u8)0x01)               </span><span class="comment">/* DAC channel1 software trigger */</span>
    3589. 

  3589. <a name="l03557"></a>03557 <span class="preprocessor">#define  DAC_SWTRIGR_SWTRIG2                 ((u8)0x02)               </span><span class="comment">/* DAC channel2 software trigger */</span>
    3590. 

  3590. <a name="l03558"></a>03558 
    3591. 

  3591. <a name="l03559"></a>03559 
    3592. 

  3592. <a name="l03560"></a>03560 <span class="comment">/*****************  Bit definition for DAC_DHR12R1 register  ******************/</span>
    3593. 

  3593. <a name="l03561"></a>03561 <span class="preprocessor">#define  DAC_DHR12R1_DACC1DHR                ((u16)0x0FFF)            </span><span class="comment">/* DAC channel1 12-bit Right aligned data */</span>
    3594. 

  3594. <a name="l03562"></a>03562 
    3595. 

  3595. <a name="l03563"></a>03563 
    3596. 

  3596. <a name="l03564"></a>03564 <span class="comment">/*****************  Bit definition for DAC_DHR12L1 register  ******************/</span>
    3597. 

  3597. <a name="l03565"></a>03565 <span class="preprocessor">#define  DAC_DHR12L1_DACC1DHR                ((u16)0xFFF0)            </span><span class="comment">/* DAC channel1 12-bit Left aligned data */</span>
    3598. 

  3598. <a name="l03566"></a>03566 
    3599. 

  3599. <a name="l03567"></a>03567 
    3600. 

  3600. <a name="l03568"></a>03568 <span class="comment">/******************  Bit definition for DAC_DHR8R1 register  ******************/</span>
    3601. 

  3601. <a name="l03569"></a>03569 <span class="preprocessor">#define  DAC_DHR8R1_DACC1DHR                 ((u8)0xFF)               </span><span class="comment">/* DAC channel1 8-bit Right aligned data */</span>
    3602. 

  3602. <a name="l03570"></a>03570 
    3603. 

  3603. <a name="l03571"></a>03571 
    3604. 

  3604. <a name="l03572"></a>03572 <span class="comment">/*****************  Bit definition for DAC_DHR12R2 register  ******************/</span>
    3605. 

  3605. <a name="l03573"></a>03573 <span class="preprocessor">#define  DAC_DHR12R2_DACC2DHR                ((u16)0x0FFF)            </span><span class="comment">/* DAC channel2 12-bit Right aligned data */</span>
    3606. 

  3606. <a name="l03574"></a>03574 
    3607. 

  3607. <a name="l03575"></a>03575 
    3608. 

  3608. <a name="l03576"></a>03576 <span class="comment">/*****************  Bit definition for DAC_DHR12L2 register  ******************/</span>
    3609. 

  3609. <a name="l03577"></a>03577 <span class="preprocessor">#define  DAC_DHR12L2_DACC2DHR                ((u16)0xFFF0)            </span><span class="comment">/* DAC channel2 12-bit Left aligned data */</span>
    3610. 

  3610. <a name="l03578"></a>03578 
    3611. 

  3611. <a name="l03579"></a>03579 
    3612. 

  3612. <a name="l03580"></a>03580 <span class="comment">/******************  Bit definition for DAC_DHR8R2 register  ******************/</span>
    3613. 

  3613. <a name="l03581"></a>03581 <span class="preprocessor">#define  DAC_DHR8R2_DACC2DHR                 ((u8)0xFF)               </span><span class="comment">/* DAC channel2 8-bit Right aligned data */</span>
    3614. 

  3614. <a name="l03582"></a>03582 
    3615. 

  3615. <a name="l03583"></a>03583 
    3616. 

  3616. <a name="l03584"></a>03584 <span class="comment">/*****************  Bit definition for DAC_DHR12RD register  ******************/</span>
    3617. 

  3617. <a name="l03585"></a>03585 <span class="preprocessor">#define  DAC_DHR12RD_DACC1DHR                ((u32)0x00000FFF)        </span><span class="comment">/* DAC channel1 12-bit Right aligned data */</span>
    3618. 

  3618. <a name="l03586"></a>03586 <span class="preprocessor">#define  DAC_DHR12RD_DACC2DHR                ((u32)0x0FFF0000)        </span><span class="comment">/* DAC channel2 12-bit Right aligned data */</span>
    3619. 

  3619. <a name="l03587"></a>03587 
    3620. 

  3620. <a name="l03588"></a>03588 
    3621. 

  3621. <a name="l03589"></a>03589 <span class="comment">/*****************  Bit definition for DAC_DHR12LD register  ******************/</span>
    3622. 

  3622. <a name="l03590"></a>03590 <span class="preprocessor">#define  DAC_DHR12LD_DACC1DHR                ((u32)0x0000FFF0)        </span><span class="comment">/* DAC channel1 12-bit Left aligned data */</span>
    3623. 

  3623. <a name="l03591"></a>03591 <span class="preprocessor">#define  DAC_DHR12LD_DACC2DHR                ((u32)0xFFF00000)        </span><span class="comment">/* DAC channel2 12-bit Left aligned data */</span>
    3624. 

  3624. <a name="l03592"></a>03592 
    3625. 

  3625. <a name="l03593"></a>03593 
    3626. 

  3626. <a name="l03594"></a>03594 <span class="comment">/******************  Bit definition for DAC_DHR8RD register  ******************/</span>
    3627. 

  3627. <a name="l03595"></a>03595 <span class="preprocessor">#define  DAC_DHR8RD_DACC1DHR                 ((u16)0x00FF)            </span><span class="comment">/* DAC channel1 8-bit Right aligned data */</span>
    3628. 

  3628. <a name="l03596"></a>03596 <span class="preprocessor">#define  DAC_DHR8RD_DACC2DHR                 ((u16)0xFF00)            </span><span class="comment">/* DAC channel2 8-bit Right aligned data */</span>
    3629. 

  3629. <a name="l03597"></a>03597 
    3630. 

  3630. <a name="l03598"></a>03598 
    3631. 

  3631. <a name="l03599"></a>03599 <span class="comment">/*******************  Bit definition for DAC_DOR1 register  *******************/</span>
    3632. 

  3632. <a name="l03600"></a>03600 <span class="preprocessor">#define  DAC_DOR1_DACC1DOR                   ((u16)0x0FFF)            </span><span class="comment">/* DAC channel1 data output */</span>
    3633. 

  3633. <a name="l03601"></a>03601 
    3634. 

  3634. <a name="l03602"></a>03602 
    3635. 

  3635. <a name="l03603"></a>03603 <span class="comment">/*******************  Bit definition for DAC_DOR2 register  *******************/</span>
    3636. 

  3636. <a name="l03604"></a>03604 <span class="preprocessor">#define  DAC_DOR2_DACC2DOR                   ((u16)0x0FFF)            </span><span class="comment">/* DAC channel2 data output */</span>
    3637. 

  3637. <a name="l03605"></a>03605 
    3638. 

  3638. <a name="l03606"></a>03606 
    3639. 

  3639. <a name="l03607"></a>03607 
    3640. 

  3640. <a name="l03608"></a>03608 <span class="comment">/******************************************************************************/</span>
    3641. 

  3641. <a name="l03609"></a>03609 <span class="comment">/*                                                                            */</span>
    3642. 

  3642. <a name="l03610"></a>03610 <span class="comment">/*                                    TIM                                     */</span>
    3643. 

  3643. <a name="l03611"></a>03611 <span class="comment">/*                                                                            */</span>
    3644. 

  3644. <a name="l03612"></a>03612 <span class="comment">/******************************************************************************/</span>
    3645. 

  3645. <a name="l03613"></a>03613 
    3646. 

  3646. <a name="l03614"></a>03614 <span class="comment">/*******************  Bit definition for TIM_CR1 register  ********************/</span>
    3647. 

  3647. <a name="l03615"></a>03615 <span class="preprocessor">#define  TIM_CR1_CEN                         ((u16)0x0001)            </span><span class="comment">/* Counter enable */</span>
    3648. 

  3648. <a name="l03616"></a>03616 <span class="preprocessor">#define  TIM_CR1_UDIS                        ((u16)0x0002)            </span><span class="comment">/* Update disable */</span>
    3649. 

  3649. <a name="l03617"></a>03617 <span class="preprocessor">#define  TIM_CR1_URS                         ((u16)0x0004)            </span><span class="comment">/* Update request source */</span>
    3650. 

  3650. <a name="l03618"></a>03618 <span class="preprocessor">#define  TIM_CR1_OPM                         ((u16)0x0008)            </span><span class="comment">/* One pulse mode */</span>
    3651. 

  3651. <a name="l03619"></a>03619 <span class="preprocessor">#define  TIM_CR1_DIR                         ((u16)0x0010)            </span><span class="comment">/* Direction */</span>
    3652. 

  3652. <a name="l03620"></a>03620 
    3653. 

  3653. <a name="l03621"></a>03621 <span class="preprocessor">#define  TIM_CR1_CMS                         ((u16)0x0060)            </span><span class="comment">/* CMS[1:0] bits (Center-aligned mode selection) */</span>
    3654. 

  3654. <a name="l03622"></a>03622 <span class="preprocessor">#define  TIM_CR1_CMS_0                       ((u16)0x0020)            </span><span class="comment">/* Bit 0 */</span>
    3655. 

  3655. <a name="l03623"></a>03623 <span class="preprocessor">#define  TIM_CR1_CMS_1                       ((u16)0x0040)            </span><span class="comment">/* Bit 1 */</span>
    3656. 

  3656. <a name="l03624"></a>03624 
    3657. 

  3657. <a name="l03625"></a>03625 <span class="preprocessor">#define  TIM_CR1_ARPE                        ((u16)0x0080)            </span><span class="comment">/* Auto-reload preload enable */</span>
    3658. 

  3658. <a name="l03626"></a>03626 
    3659. 

  3659. <a name="l03627"></a>03627 <span class="preprocessor">#define  TIM_CR1_CKD                         ((u16)0x0300)            </span><span class="comment">/* CKD[1:0] bits (clock division) */</span>
    3660. 

  3660. <a name="l03628"></a>03628 <span class="preprocessor">#define  TIM_CR1_CKD_0                       ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3661. 

  3661. <a name="l03629"></a>03629 <span class="preprocessor">#define  TIM_CR1_CKD_1                       ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3662. 

  3662. <a name="l03630"></a>03630 
    3663. 

  3663. <a name="l03631"></a>03631 
    3664. 

  3664. <a name="l03632"></a>03632 <span class="comment">/*******************  Bit definition for TIM_CR2 register  ********************/</span>
    3665. 

  3665. <a name="l03633"></a>03633 <span class="preprocessor">#define  TIM_CR2_CCPC                        ((u16)0x0001)            </span><span class="comment">/* Capture/Compare Preloaded Control */</span>
    3666. 

  3666. <a name="l03634"></a>03634 <span class="preprocessor">#define  TIM_CR2_CCUS                        ((u16)0x0004)            </span><span class="comment">/* Capture/Compare Control Update Selection */</span>
    3667. 

  3667. <a name="l03635"></a>03635 <span class="preprocessor">#define  TIM_CR2_CCDS                        ((u16)0x0008)            </span><span class="comment">/* Capture/Compare DMA Selection */</span>
    3668. 

  3668. <a name="l03636"></a>03636 
    3669. 

  3669. <a name="l03637"></a>03637 <span class="preprocessor">#define  TIM_CR2_MMS                         ((u16)0x0070)            </span><span class="comment">/* MMS[2:0] bits (Master Mode Selection) */</span>
    3670. 

  3670. <a name="l03638"></a>03638 <span class="preprocessor">#define  TIM_CR2_MMS_0                       ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3671. 

  3671. <a name="l03639"></a>03639 <span class="preprocessor">#define  TIM_CR2_MMS_1                       ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3672. 

  3672. <a name="l03640"></a>03640 <span class="preprocessor">#define  TIM_CR2_MMS_2                       ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3673. 

  3673. <a name="l03641"></a>03641 
    3674. 

  3674. <a name="l03642"></a>03642 <span class="preprocessor">#define  TIM_CR2_TI1S                        ((u16)0x0080)            </span><span class="comment">/* TI1 Selection */</span>
    3675. 

  3675. <a name="l03643"></a>03643 <span class="preprocessor">#define  TIM_CR2_OIS1                        ((u16)0x0100)            </span><span class="comment">/* Output Idle state 1 (OC1 output) */</span>
    3676. 

  3676. <a name="l03644"></a>03644 <span class="preprocessor">#define  TIM_CR2_OIS1N                       ((u16)0x0200)            </span><span class="comment">/* Output Idle state 1 (OC1N output) */</span>
    3677. 

  3677. <a name="l03645"></a>03645 <span class="preprocessor">#define  TIM_CR2_OIS2                        ((u16)0x0400)            </span><span class="comment">/* Output Idle state 2 (OC2 output) */</span>
    3678. 

  3678. <a name="l03646"></a>03646 <span class="preprocessor">#define  TIM_CR2_OIS2N                       ((u16)0x0800)            </span><span class="comment">/* Output Idle state 2 (OC2N output) */</span>
    3679. 

  3679. <a name="l03647"></a>03647 <span class="preprocessor">#define  TIM_CR2_OIS3                        ((u16)0x1000)            </span><span class="comment">/* Output Idle state 3 (OC3 output) */</span>
    3680. 

  3680. <a name="l03648"></a>03648 <span class="preprocessor">#define  TIM_CR2_OIS3N                       ((u16)0x2000)            </span><span class="comment">/* Output Idle state 3 (OC3N output) */</span>
    3681. 

  3681. <a name="l03649"></a>03649 <span class="preprocessor">#define  TIM_CR2_OIS4                        ((u16)0x4000)            </span><span class="comment">/* Output Idle state 4 (OC4 output) */</span>
    3682. 

  3682. <a name="l03650"></a>03650 
    3683. 

  3683. <a name="l03651"></a>03651 
    3684. 

  3684. <a name="l03652"></a>03652 <span class="comment">/*******************  Bit definition for TIM_SMCR register  *******************/</span>
    3685. 

  3685. <a name="l03653"></a>03653 <span class="preprocessor">#define  TIM_SMCR_SMS                        ((u16)0x0007)            </span><span class="comment">/* SMS[2:0] bits (Slave mode selection) */</span>
    3686. 

  3686. <a name="l03654"></a>03654 <span class="preprocessor">#define  TIM_SMCR_SMS_0                      ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    3687. 

  3687. <a name="l03655"></a>03655 <span class="preprocessor">#define  TIM_SMCR_SMS_1                      ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    3688. 

  3688. <a name="l03656"></a>03656 <span class="preprocessor">#define  TIM_SMCR_SMS_2                      ((u16)0x0004)            </span><span class="comment">/* Bit 2 */</span>
    3689. 

  3689. <a name="l03657"></a>03657 
    3690. 

  3690. <a name="l03658"></a>03658 <span class="preprocessor">#define  TIM_SMCR_TS                         ((u16)0x0070)            </span><span class="comment">/* TS[2:0] bits (Trigger selection) */</span>
    3691. 

  3691. <a name="l03659"></a>03659 <span class="preprocessor">#define  TIM_SMCR_TS_0                       ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3692. 

  3692. <a name="l03660"></a>03660 <span class="preprocessor">#define  TIM_SMCR_TS_1                       ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3693. 

  3693. <a name="l03661"></a>03661 <span class="preprocessor">#define  TIM_SMCR_TS_2                       ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3694. 

  3694. <a name="l03662"></a>03662 
    3695. 

  3695. <a name="l03663"></a>03663 <span class="preprocessor">#define  TIM_SMCR_MSM                        ((u16)0x0080)            </span><span class="comment">/* Master/slave mode */</span>
    3696. 

  3696. <a name="l03664"></a>03664 
    3697. 

  3697. <a name="l03665"></a>03665 <span class="preprocessor">#define  TIM_SMCR_ETF                        ((u16)0x0F00)            </span><span class="comment">/* ETF[3:0] bits (External trigger filter) */</span>
    3698. 

  3698. <a name="l03666"></a>03666 <span class="preprocessor">#define  TIM_SMCR_ETF_0                      ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3699. 

  3699. <a name="l03667"></a>03667 <span class="preprocessor">#define  TIM_SMCR_ETF_1                      ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3700. 

  3700. <a name="l03668"></a>03668 <span class="preprocessor">#define  TIM_SMCR_ETF_2                      ((u16)0x0400)            </span><span class="comment">/* Bit 2 */</span>
    3701. 

  3701. <a name="l03669"></a>03669 <span class="preprocessor">#define  TIM_SMCR_ETF_3                      ((u16)0x0800)            </span><span class="comment">/* Bit 3 */</span>
    3702. 

  3702. <a name="l03670"></a>03670 
    3703. 

  3703. <a name="l03671"></a>03671 <span class="preprocessor">#define  TIM_SMCR_ETPS                       ((u16)0x3000)            </span><span class="comment">/* ETPS[1:0] bits (External trigger prescaler) */</span>
    3704. 

  3704. <a name="l03672"></a>03672 <span class="preprocessor">#define  TIM_SMCR_ETPS_0                     ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3705. 

  3705. <a name="l03673"></a>03673 <span class="preprocessor">#define  TIM_SMCR_ETPS_1                     ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3706. 

  3706. <a name="l03674"></a>03674 
    3707. 

  3707. <a name="l03675"></a>03675 <span class="preprocessor">#define  TIM_SMCR_ECE                        ((u16)0x4000)            </span><span class="comment">/* External clock enable */</span>
    3708. 

  3708. <a name="l03676"></a>03676 <span class="preprocessor">#define  TIM_SMCR_ETP                        ((u16)0x8000)            </span><span class="comment">/* External trigger polarity */</span>
    3709. 

  3709. <a name="l03677"></a>03677 
    3710. 

  3710. <a name="l03678"></a>03678 
    3711. 

  3711. <a name="l03679"></a>03679 <span class="comment">/*******************  Bit definition for TIM_DIER register  *******************/</span>
    3712. 

  3712. <a name="l03680"></a>03680 <span class="preprocessor">#define  TIM_DIER_UIE                        ((u16)0x0001)            </span><span class="comment">/* Update interrupt enable */</span>
    3713. 

  3713. <a name="l03681"></a>03681 <span class="preprocessor">#define  TIM_DIER_CC1IE                      ((u16)0x0002)            </span><span class="comment">/* Capture/Compare 1 interrupt enable */</span>
    3714. 

  3714. <a name="l03682"></a>03682 <span class="preprocessor">#define  TIM_DIER_CC2IE                      ((u16)0x0004)            </span><span class="comment">/* Capture/Compare 2 interrupt enable */</span>
    3715. 

  3715. <a name="l03683"></a>03683 <span class="preprocessor">#define  TIM_DIER_CC3IE                      ((u16)0x0008)            </span><span class="comment">/* Capture/Compare 3 interrupt enable */</span>
    3716. 

  3716. <a name="l03684"></a>03684 <span class="preprocessor">#define  TIM_DIER_CC4IE                      ((u16)0x0010)            </span><span class="comment">/* Capture/Compare 4 interrupt enable */</span>
    3717. 

  3717. <a name="l03685"></a>03685 <span class="preprocessor">#define  TIM_DIER_COMIE                      ((u16)0x0020)            </span><span class="comment">/* COM interrupt enable */</span>
    3718. 

  3718. <a name="l03686"></a>03686 <span class="preprocessor">#define  TIM_DIER_TIE                        ((u16)0x0040)            </span><span class="comment">/* Trigger interrupt enable */</span>
    3719. 

  3719. <a name="l03687"></a>03687 <span class="preprocessor">#define  TIM_DIER_BIE                        ((u16)0x0080)            </span><span class="comment">/* Break interrupt enable */</span>
    3720. 

  3720. <a name="l03688"></a>03688 <span class="preprocessor">#define  TIM_DIER_UDE                        ((u16)0x0100)            </span><span class="comment">/* Update DMA request enable */</span>
    3721. 

  3721. <a name="l03689"></a>03689 <span class="preprocessor">#define  TIM_DIER_CC1DE                      ((u16)0x0200)            </span><span class="comment">/* Capture/Compare 1 DMA request enable */</span>
    3722. 

  3722. <a name="l03690"></a>03690 <span class="preprocessor">#define  TIM_DIER_CC2DE                      ((u16)0x0400)            </span><span class="comment">/* Capture/Compare 2 DMA request enable */</span>
    3723. 

  3723. <a name="l03691"></a>03691 <span class="preprocessor">#define  TIM_DIER_CC3DE                      ((u16)0x0800)            </span><span class="comment">/* Capture/Compare 3 DMA request enable */</span>
    3724. 

  3724. <a name="l03692"></a>03692 <span class="preprocessor">#define  TIM_DIER_CC4DE                      ((u16)0x1000)            </span><span class="comment">/* Capture/Compare 4 DMA request enable */</span>
    3725. 

  3725. <a name="l03693"></a>03693 <span class="preprocessor">#define  TIM_DIER_COMDE                      ((u16)0x2000)            </span><span class="comment">/* COM DMA request enable */</span>
    3726. 

  3726. <a name="l03694"></a>03694 <span class="preprocessor">#define  TIM_DIER_TDE                        ((u16)0x4000)            </span><span class="comment">/* Trigger DMA request enable */</span>
    3727. 

  3727. <a name="l03695"></a>03695 
    3728. 

  3728. <a name="l03696"></a>03696 
    3729. 

  3729. <a name="l03697"></a>03697 <span class="comment">/********************  Bit definition for TIM_SR register  ********************/</span>
    3730. 

  3730. <a name="l03698"></a>03698 <span class="preprocessor">#define  TIM_SR_UIF                          ((u16)0x0001)            </span><span class="comment">/* Update interrupt Flag */</span>
    3731. 

  3731. <a name="l03699"></a>03699 <span class="preprocessor">#define  TIM_SR_CC1IF                        ((u16)0x0002)            </span><span class="comment">/* Capture/Compare 1 interrupt Flag */</span>
    3732. 

  3732. <a name="l03700"></a>03700 <span class="preprocessor">#define  TIM_SR_CC2IF                        ((u16)0x0004)            </span><span class="comment">/* Capture/Compare 2 interrupt Flag */</span>
    3733. 

  3733. <a name="l03701"></a>03701 <span class="preprocessor">#define  TIM_SR_CC3IF                        ((u16)0x0008)            </span><span class="comment">/* Capture/Compare 3 interrupt Flag */</span>
    3734. 

  3734. <a name="l03702"></a>03702 <span class="preprocessor">#define  TIM_SR_CC4IF                        ((u16)0x0010)            </span><span class="comment">/* Capture/Compare 4 interrupt Flag */</span>
    3735. 

  3735. <a name="l03703"></a>03703 <span class="preprocessor">#define  TIM_SR_COMIF                        ((u16)0x0020)            </span><span class="comment">/* COM interrupt Flag */</span>
    3736. 

  3736. <a name="l03704"></a>03704 <span class="preprocessor">#define  TIM_SR_TIF                          ((u16)0x0040)            </span><span class="comment">/* Trigger interrupt Flag */</span>
    3737. 

  3737. <a name="l03705"></a>03705 <span class="preprocessor">#define  TIM_SR_BIF                          ((u16)0x0080)            </span><span class="comment">/* Break interrupt Flag */</span>
    3738. 

  3738. <a name="l03706"></a>03706 <span class="preprocessor">#define  TIM_SR_CC1OF                        ((u16)0x0200)            </span><span class="comment">/* Capture/Compare 1 Overcapture Flag */</span>
    3739. 

  3739. <a name="l03707"></a>03707 <span class="preprocessor">#define  TIM_SR_CC2OF                        ((u16)0x0400)            </span><span class="comment">/* Capture/Compare 2 Overcapture Flag */</span>
    3740. 

  3740. <a name="l03708"></a>03708 <span class="preprocessor">#define  TIM_SR_CC3OF                        ((u16)0x0800)            </span><span class="comment">/* Capture/Compare 3 Overcapture Flag */</span>
    3741. 

  3741. <a name="l03709"></a>03709 <span class="preprocessor">#define  TIM_SR_CC4OF                        ((u16)0x1000)            </span><span class="comment">/* Capture/Compare 4 Overcapture Flag */</span>
    3742. 

  3742. <a name="l03710"></a>03710 
    3743. 

  3743. <a name="l03711"></a>03711 
    3744. 

  3744. <a name="l03712"></a>03712 <span class="comment">/*******************  Bit definition for TIM_EGR register  ********************/</span>
    3745. 

  3745. <a name="l03713"></a>03713 <span class="preprocessor">#define  TIM_EGR_UG                          ((u8)0x01)               </span><span class="comment">/* Update Generation */</span>
    3746. 

  3746. <a name="l03714"></a>03714 <span class="preprocessor">#define  TIM_EGR_CC1G                        ((u8)0x02)               </span><span class="comment">/* Capture/Compare 1 Generation */</span>
    3747. 

  3747. <a name="l03715"></a>03715 <span class="preprocessor">#define  TIM_EGR_CC2G                        ((u8)0x04)               </span><span class="comment">/* Capture/Compare 2 Generation */</span>
    3748. 

  3748. <a name="l03716"></a>03716 <span class="preprocessor">#define  TIM_EGR_CC3G                        ((u8)0x08)               </span><span class="comment">/* Capture/Compare 3 Generation */</span>
    3749. 

  3749. <a name="l03717"></a>03717 <span class="preprocessor">#define  TIM_EGR_CC4G                        ((u8)0x10)               </span><span class="comment">/* Capture/Compare 4 Generation */</span>
    3750. 

  3750. <a name="l03718"></a>03718 <span class="preprocessor">#define  TIM_EGR_COMG                        ((u8)0x20)               </span><span class="comment">/* Capture/Compare Control Update Generation */</span>
    3751. 

  3751. <a name="l03719"></a>03719 <span class="preprocessor">#define  TIM_EGR_TG                          ((u8)0x40)               </span><span class="comment">/* Trigger Generation */</span>
    3752. 

  3752. <a name="l03720"></a>03720 <span class="preprocessor">#define  TIM_EGR_BG                          ((u8)0x80)               </span><span class="comment">/* Break Generation */</span>
    3753. 

  3753. <a name="l03721"></a>03721 
    3754. 

  3754. <a name="l03722"></a>03722 
    3755. 

  3755. <a name="l03723"></a>03723 <span class="comment">/******************  Bit definition for TIM_CCMR1 register  *******************/</span>
    3756. 

  3756. <a name="l03724"></a>03724 <span class="preprocessor">#define  TIM_CCMR1_CC1S                      ((u16)0x0003)            </span><span class="comment">/* CC1S[1:0] bits (Capture/Compare 1 Selection) */</span>
    3757. 

  3757. <a name="l03725"></a>03725 <span class="preprocessor">#define  TIM_CCMR1_CC1S_0                    ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    3758. 

  3758. <a name="l03726"></a>03726 <span class="preprocessor">#define  TIM_CCMR1_CC1S_1                    ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    3759. 

  3759. <a name="l03727"></a>03727 
    3760. 

  3760. <a name="l03728"></a>03728 <span class="preprocessor">#define  TIM_CCMR1_OC1FE                     ((u16)0x0004)            </span><span class="comment">/* Output Compare 1 Fast enable */</span>
    3761. 

  3761. <a name="l03729"></a>03729 <span class="preprocessor">#define  TIM_CCMR1_OC1PE                     ((u16)0x0008)            </span><span class="comment">/* Output Compare 1 Preload enable */</span>
    3762. 

  3762. <a name="l03730"></a>03730 
    3763. 

  3763. <a name="l03731"></a>03731 <span class="preprocessor">#define  TIM_CCMR1_OC1M                      ((u16)0x0070)            </span><span class="comment">/* OC1M[2:0] bits (Output Compare 1 Mode) */</span>
    3764. 

  3764. <a name="l03732"></a>03732 <span class="preprocessor">#define  TIM_CCMR1_OC1M_0                    ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3765. 

  3765. <a name="l03733"></a>03733 <span class="preprocessor">#define  TIM_CCMR1_OC1M_1                    ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3766. 

  3766. <a name="l03734"></a>03734 <span class="preprocessor">#define  TIM_CCMR1_OC1M_2                    ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3767. 

  3767. <a name="l03735"></a>03735 
    3768. 

  3768. <a name="l03736"></a>03736 <span class="preprocessor">#define  TIM_CCMR1_OC1CE                     ((u16)0x0080)            </span><span class="comment">/* Output Compare 1Clear Enable */</span>
    3769. 

  3769. <a name="l03737"></a>03737 
    3770. 

  3770. <a name="l03738"></a>03738 <span class="preprocessor">#define  TIM_CCMR1_CC2S                      ((u16)0x0300)            </span><span class="comment">/* CC2S[1:0] bits (Capture/Compare 2 Selection) */</span>
    3771. 

  3771. <a name="l03739"></a>03739 <span class="preprocessor">#define  TIM_CCMR1_CC2S_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3772. 

  3772. <a name="l03740"></a>03740 <span class="preprocessor">#define  TIM_CCMR1_CC2S_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3773. 

  3773. <a name="l03741"></a>03741 
    3774. 

  3774. <a name="l03742"></a>03742 <span class="preprocessor">#define  TIM_CCMR1_OC2FE                     ((u16)0x0400)            </span><span class="comment">/* Output Compare 2 Fast enable */</span>
    3775. 

  3775. <a name="l03743"></a>03743 <span class="preprocessor">#define  TIM_CCMR1_OC2PE                     ((u16)0x0800)            </span><span class="comment">/* Output Compare 2 Preload enable */</span>
    3776. 

  3776. <a name="l03744"></a>03744 
    3777. 

  3777. <a name="l03745"></a>03745 <span class="preprocessor">#define  TIM_CCMR1_OC2M                      ((u16)0x7000)            </span><span class="comment">/* OC2M[2:0] bits (Output Compare 2 Mode) */</span>
    3778. 

  3778. <a name="l03746"></a>03746 <span class="preprocessor">#define  TIM_CCMR1_OC2M_0                    ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3779. 

  3779. <a name="l03747"></a>03747 <span class="preprocessor">#define  TIM_CCMR1_OC2M_1                    ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3780. 

  3780. <a name="l03748"></a>03748 <span class="preprocessor">#define  TIM_CCMR1_OC2M_2                    ((u16)0x4000)            </span><span class="comment">/* Bit 2 */</span>
    3781. 

  3781. <a name="l03749"></a>03749 
    3782. 

  3782. <a name="l03750"></a>03750 <span class="preprocessor">#define  TIM_CCMR1_OC2CE                     ((u16)0x8000)            </span><span class="comment">/* Output Compare 2 Clear Enable */</span>
    3783. 

  3783. <a name="l03751"></a>03751 
    3784. 

  3784. <a name="l03752"></a>03752 <span class="comment">/*----------------------------------------------------------------------------*/</span>
    3785. 

  3785. <a name="l03753"></a>03753 
    3786. 

  3786. <a name="l03754"></a>03754 <span class="preprocessor">#define  TIM_CCMR1_IC1PSC                    ((u16)0x000C)            </span><span class="comment">/* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */</span>
    3787. 

  3787. <a name="l03755"></a>03755 <span class="preprocessor">#define  TIM_CCMR1_IC1PSC_0                  ((u16)0x0004)            </span><span class="comment">/* Bit 0 */</span>
    3788. 

  3788. <a name="l03756"></a>03756 <span class="preprocessor">#define  TIM_CCMR1_IC1PSC_1                  ((u16)0x0008)            </span><span class="comment">/* Bit 1 */</span>
    3789. 

  3789. <a name="l03757"></a>03757 
    3790. 

  3790. <a name="l03758"></a>03758 <span class="preprocessor">#define  TIM_CCMR1_IC1F                      ((u16)0x00F0)            </span><span class="comment">/* IC1F[3:0] bits (Input Capture 1 Filter) */</span>
    3791. 

  3791. <a name="l03759"></a>03759 <span class="preprocessor">#define  TIM_CCMR1_IC1F_0                    ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3792. 

  3792. <a name="l03760"></a>03760 <span class="preprocessor">#define  TIM_CCMR1_IC1F_1                    ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3793. 

  3793. <a name="l03761"></a>03761 <span class="preprocessor">#define  TIM_CCMR1_IC1F_2                    ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3794. 

  3794. <a name="l03762"></a>03762 <span class="preprocessor">#define  TIM_CCMR1_IC1F_3                    ((u16)0x0080)            </span><span class="comment">/* Bit 3 */</span>
    3795. 

  3795. <a name="l03763"></a>03763 
    3796. 

  3796. <a name="l03764"></a>03764 <span class="preprocessor">#define  TIM_CCMR1_IC2PSC                    ((u16)0x0C00)            </span><span class="comment">/* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */</span>
    3797. 

  3797. <a name="l03765"></a>03765 <span class="preprocessor">#define  TIM_CCMR1_IC2PSC_0                  ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    3798. 

  3798. <a name="l03766"></a>03766 <span class="preprocessor">#define  TIM_CCMR1_IC2PSC_1                  ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3799. 

  3799. <a name="l03767"></a>03767 
    3800. 

  3800. <a name="l03768"></a>03768 <span class="preprocessor">#define  TIM_CCMR1_IC2F                      ((u16)0xF000)            </span><span class="comment">/* IC2F[3:0] bits (Input Capture 2 Filter) */</span>
    3801. 

  3801. <a name="l03769"></a>03769 <span class="preprocessor">#define  TIM_CCMR1_IC2F_0                    ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3802. 

  3802. <a name="l03770"></a>03770 <span class="preprocessor">#define  TIM_CCMR1_IC2F_1                    ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3803. 

  3803. <a name="l03771"></a>03771 <span class="preprocessor">#define  TIM_CCMR1_IC2F_2                    ((u16)0x4000)            </span><span class="comment">/* Bit 2 */</span>
    3804. 

  3804. <a name="l03772"></a>03772 <span class="preprocessor">#define  TIM_CCMR1_IC2F_3                    ((u16)0x8000)            </span><span class="comment">/* Bit 3 */</span>
    3805. 

  3805. <a name="l03773"></a>03773 
    3806. 

  3806. <a name="l03774"></a>03774 
    3807. 

  3807. <a name="l03775"></a>03775 <span class="comment">/******************  Bit definition for TIM_CCMR2 register  *******************/</span>
    3808. 

  3808. <a name="l03776"></a>03776 <span class="preprocessor">#define  TIM_CCMR2_CC3S                      ((u16)0x0003)            </span><span class="comment">/* CC3S[1:0] bits (Capture/Compare 3 Selection) */</span>
    3809. 

  3809. <a name="l03777"></a>03777 <span class="preprocessor">#define  TIM_CCMR2_CC3S_0                    ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    3810. 

  3810. <a name="l03778"></a>03778 <span class="preprocessor">#define  TIM_CCMR2_CC3S_1                    ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    3811. 

  3811. <a name="l03779"></a>03779 
    3812. 

  3812. <a name="l03780"></a>03780 <span class="preprocessor">#define  TIM_CCMR2_OC3FE                     ((u16)0x0004)            </span><span class="comment">/* Output Compare 3 Fast enable */</span>
    3813. 

  3813. <a name="l03781"></a>03781 <span class="preprocessor">#define  TIM_CCMR2_OC3PE                     ((u16)0x0008)            </span><span class="comment">/* Output Compare 3 Preload enable */</span>
    3814. 

  3814. <a name="l03782"></a>03782 
    3815. 

  3815. <a name="l03783"></a>03783 <span class="preprocessor">#define  TIM_CCMR2_OC3M                      ((u16)0x0070)            </span><span class="comment">/* OC3M[2:0] bits (Output Compare 3 Mode) */</span>
    3816. 

  3816. <a name="l03784"></a>03784 <span class="preprocessor">#define  TIM_CCMR2_OC3M_0                    ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3817. 

  3817. <a name="l03785"></a>03785 <span class="preprocessor">#define  TIM_CCMR2_OC3M_1                    ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3818. 

  3818. <a name="l03786"></a>03786 <span class="preprocessor">#define  TIM_CCMR2_OC3M_2                    ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3819. 

  3819. <a name="l03787"></a>03787 
    3820. 

  3820. <a name="l03788"></a>03788 <span class="preprocessor">#define  TIM_CCMR2_OC3CE                     ((u16)0x0080)            </span><span class="comment">/* Output Compare 3 Clear Enable */</span>
    3821. 

  3821. <a name="l03789"></a>03789 
    3822. 

  3822. <a name="l03790"></a>03790 <span class="preprocessor">#define  TIM_CCMR2_CC4S                      ((u16)0x0300)            </span><span class="comment">/* CC4S[1:0] bits (Capture/Compare 4 Selection) */</span>
    3823. 

  3823. <a name="l03791"></a>03791 <span class="preprocessor">#define  TIM_CCMR2_CC4S_0                    ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3824. 

  3824. <a name="l03792"></a>03792 <span class="preprocessor">#define  TIM_CCMR2_CC4S_1                    ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3825. 

  3825. <a name="l03793"></a>03793 
    3826. 

  3826. <a name="l03794"></a>03794 <span class="preprocessor">#define  TIM_CCMR2_OC4FE                     ((u16)0x0400)            </span><span class="comment">/* Output Compare 4 Fast enable */</span>
    3827. 

  3827. <a name="l03795"></a>03795 <span class="preprocessor">#define  TIM_CCMR2_OC4PE                     ((u16)0x0800)            </span><span class="comment">/* Output Compare 4 Preload enable */</span>
    3828. 

  3828. <a name="l03796"></a>03796 
    3829. 

  3829. <a name="l03797"></a>03797 <span class="preprocessor">#define  TIM_CCMR2_OC4M                      ((u16)0x7000)            </span><span class="comment">/* OC4M[2:0] bits (Output Compare 4 Mode) */</span>
    3830. 

  3830. <a name="l03798"></a>03798 <span class="preprocessor">#define  TIM_CCMR2_OC4M_0                    ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3831. 

  3831. <a name="l03799"></a>03799 <span class="preprocessor">#define  TIM_CCMR2_OC4M_1                    ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3832. 

  3832. <a name="l03800"></a>03800 <span class="preprocessor">#define  TIM_CCMR2_OC4M_2                    ((u16)0x4000)            </span><span class="comment">/* Bit 2 */</span>
    3833. 

  3833. <a name="l03801"></a>03801 
    3834. 

  3834. <a name="l03802"></a>03802 <span class="preprocessor">#define  TIM_CCMR2_OC4CE                     ((u16)0x8000)            </span><span class="comment">/* Output Compare 4 Clear Enable */</span>
    3835. 

  3835. <a name="l03803"></a>03803 
    3836. 

  3836. <a name="l03804"></a>03804 <span class="comment">/*----------------------------------------------------------------------------*/</span>
    3837. 

  3837. <a name="l03805"></a>03805 
    3838. 

  3838. <a name="l03806"></a>03806 <span class="preprocessor">#define  TIM_CCMR2_IC3PSC                    ((u16)0x000C)            </span><span class="comment">/* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */</span>
    3839. 

  3839. <a name="l03807"></a>03807 <span class="preprocessor">#define  TIM_CCMR2_IC3PSC_0                  ((u16)0x0004)            </span><span class="comment">/* Bit 0 */</span>
    3840. 

  3840. <a name="l03808"></a>03808 <span class="preprocessor">#define  TIM_CCMR2_IC3PSC_1                  ((u16)0x0008)            </span><span class="comment">/* Bit 1 */</span>
    3841. 

  3841. <a name="l03809"></a>03809 
    3842. 

  3842. <a name="l03810"></a>03810 <span class="preprocessor">#define  TIM_CCMR2_IC3F                      ((u16)0x00F0)            </span><span class="comment">/* IC3F[3:0] bits (Input Capture 3 Filter) */</span>
    3843. 

  3843. <a name="l03811"></a>03811 <span class="preprocessor">#define  TIM_CCMR2_IC3F_0                    ((u16)0x0010)            </span><span class="comment">/* Bit 0 */</span>
    3844. 

  3844. <a name="l03812"></a>03812 <span class="preprocessor">#define  TIM_CCMR2_IC3F_1                    ((u16)0x0020)            </span><span class="comment">/* Bit 1 */</span>
    3845. 

  3845. <a name="l03813"></a>03813 <span class="preprocessor">#define  TIM_CCMR2_IC3F_2                    ((u16)0x0040)            </span><span class="comment">/* Bit 2 */</span>
    3846. 

  3846. <a name="l03814"></a>03814 <span class="preprocessor">#define  TIM_CCMR2_IC3F_3                    ((u16)0x0080)            </span><span class="comment">/* Bit 3 */</span>
    3847. 

  3847. <a name="l03815"></a>03815 
    3848. 

  3848. <a name="l03816"></a>03816 <span class="preprocessor">#define  TIM_CCMR2_IC4PSC                    ((u16)0x0C00)            </span><span class="comment">/* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */</span>
    3849. 

  3849. <a name="l03817"></a>03817 <span class="preprocessor">#define  TIM_CCMR2_IC4PSC_0                  ((u16)0x0400)            </span><span class="comment">/* Bit 0 */</span>
    3850. 

  3850. <a name="l03818"></a>03818 <span class="preprocessor">#define  TIM_CCMR2_IC4PSC_1                  ((u16)0x0800)            </span><span class="comment">/* Bit 1 */</span>
    3851. 

  3851. <a name="l03819"></a>03819 
    3852. 

  3852. <a name="l03820"></a>03820 <span class="preprocessor">#define  TIM_CCMR2_IC4F                      ((u16)0xF000)            </span><span class="comment">/* IC4F[3:0] bits (Input Capture 4 Filter) */</span>
    3853. 

  3853. <a name="l03821"></a>03821 <span class="preprocessor">#define  TIM_CCMR2_IC4F_0                    ((u16)0x1000)            </span><span class="comment">/* Bit 0 */</span>
    3854. 

  3854. <a name="l03822"></a>03822 <span class="preprocessor">#define  TIM_CCMR2_IC4F_1                    ((u16)0x2000)            </span><span class="comment">/* Bit 1 */</span>
    3855. 

  3855. <a name="l03823"></a>03823 <span class="preprocessor">#define  TIM_CCMR2_IC4F_2                    ((u16)0x4000)            </span><span class="comment">/* Bit 2 */</span>
    3856. 

  3856. <a name="l03824"></a>03824 <span class="preprocessor">#define  TIM_CCMR2_IC4F_3                    ((u16)0x8000)            </span><span class="comment">/* Bit 3 */</span>
    3857. 

  3857. <a name="l03825"></a>03825 
    3858. 

  3858. <a name="l03826"></a>03826 
    3859. 

  3859. <a name="l03827"></a>03827 <span class="comment">/*******************  Bit definition for TIM_CCER register  *******************/</span>
    3860. 

  3860. <a name="l03828"></a>03828 <span class="preprocessor">#define  TIM_CCER_CC1E                       ((u16)0x0001)            </span><span class="comment">/* Capture/Compare 1 output enable */</span>
    3861. 

  3861. <a name="l03829"></a>03829 <span class="preprocessor">#define  TIM_CCER_CC1P                       ((u16)0x0002)            </span><span class="comment">/* Capture/Compare 1 output Polarity */</span>
    3862. 

  3862. <a name="l03830"></a>03830 <span class="preprocessor">#define  TIM_CCER_CC1NE                      ((u16)0x0004)            </span><span class="comment">/* Capture/Compare 1 Complementary output enable */</span>
    3863. 

  3863. <a name="l03831"></a>03831 <span class="preprocessor">#define  TIM_CCER_CC1NP                      ((u16)0x0008)            </span><span class="comment">/* Capture/Compare 1 Complementary output Polarity */</span>
    3864. 

  3864. <a name="l03832"></a>03832 <span class="preprocessor">#define  TIM_CCER_CC2E                       ((u16)0x0010)            </span><span class="comment">/* Capture/Compare 2 output enable */</span>
    3865. 

  3865. <a name="l03833"></a>03833 <span class="preprocessor">#define  TIM_CCER_CC2P                       ((u16)0x0020)            </span><span class="comment">/* Capture/Compare 2 output Polarity */</span>
    3866. 

  3866. <a name="l03834"></a>03834 <span class="preprocessor">#define  TIM_CCER_CC2NE                      ((u16)0x0040)            </span><span class="comment">/* Capture/Compare 2 Complementary output enable */</span>
    3867. 

  3867. <a name="l03835"></a>03835 <span class="preprocessor">#define  TIM_CCER_CC2NP                      ((u16)0x0080)            </span><span class="comment">/* Capture/Compare 2 Complementary output Polarity */</span>
    3868. 

  3868. <a name="l03836"></a>03836 <span class="preprocessor">#define  TIM_CCER_CC3E                       ((u16)0x0100)            </span><span class="comment">/* Capture/Compare 3 output enable */</span>
    3869. 

  3869. <a name="l03837"></a>03837 <span class="preprocessor">#define  TIM_CCER_CC3P                       ((u16)0x0200)            </span><span class="comment">/* Capture/Compare 3 output Polarity */</span>
    3870. 

  3870. <a name="l03838"></a>03838 <span class="preprocessor">#define  TIM_CCER_CC3NE                      ((u16)0x0400)            </span><span class="comment">/* Capture/Compare 3 Complementary output enable */</span>
    3871. 

  3871. <a name="l03839"></a>03839 <span class="preprocessor">#define  TIM_CCER_CC3NP                      ((u16)0x0800)            </span><span class="comment">/* Capture/Compare 3 Complementary output Polarity */</span>
    3872. 

  3872. <a name="l03840"></a>03840 <span class="preprocessor">#define  TIM_CCER_CC4E                       ((u16)0x1000)            </span><span class="comment">/* Capture/Compare 4 output enable */</span>
    3873. 

  3873. <a name="l03841"></a>03841 <span class="preprocessor">#define  TIM_CCER_CC4P                       ((u16)0x2000)            </span><span class="comment">/* Capture/Compare 4 output Polarity */</span>
    3874. 

  3874. <a name="l03842"></a>03842 
    3875. 

  3875. <a name="l03843"></a>03843 
    3876. 

  3876. <a name="l03844"></a>03844 <span class="comment">/*******************  Bit definition for TIM_CNT register  ********************/</span>
    3877. 

  3877. <a name="l03845"></a>03845 <span class="preprocessor">#define  TIM_CNT_CNT                         ((u16)0xFFFF)            </span><span class="comment">/* Counter Value */</span>
    3878. 

  3878. <a name="l03846"></a>03846 
    3879. 

  3879. <a name="l03847"></a>03847 
    3880. 

  3880. <a name="l03848"></a>03848 <span class="comment">/*******************  Bit definition for TIM_PSC register  ********************/</span>
    3881. 

  3881. <a name="l03849"></a>03849 <span class="preprocessor">#define  TIM_PSC_PSC                         ((u16)0xFFFF)            </span><span class="comment">/* Prescaler Value */</span>
    3882. 

  3882. <a name="l03850"></a>03850 
    3883. 

  3883. <a name="l03851"></a>03851 
    3884. 

  3884. <a name="l03852"></a>03852 <span class="comment">/*******************  Bit definition for TIM_ARR register  ********************/</span>
    3885. 

  3885. <a name="l03853"></a>03853 <span class="preprocessor">#define  TIM_ARR_ARR                         ((u16)0xFFFF)            </span><span class="comment">/* actual auto-reload Value */</span>
    3886. 

  3886. <a name="l03854"></a>03854 
    3887. 

  3887. <a name="l03855"></a>03855 
    3888. 

  3888. <a name="l03856"></a>03856 <span class="comment">/*******************  Bit definition for TIM_RCR register  ********************/</span>
    3889. 

  3889. <a name="l03857"></a>03857 <span class="preprocessor">#define  TIM_RCR_REP                         ((u8)0xFF)               </span><span class="comment">/* Repetition Counter Value */</span>
    3890. 

  3890. <a name="l03858"></a>03858 
    3891. 

  3891. <a name="l03859"></a>03859 
    3892. 

  3892. <a name="l03860"></a>03860 <span class="comment">/*******************  Bit definition for TIM_CCR1 register  *******************/</span>
    3893. 

  3893. <a name="l03861"></a>03861 <span class="preprocessor">#define  TIM_CCR1_CCR1                       ((u16)0xFFFF)            </span><span class="comment">/* Capture/Compare 1 Value */</span>
    3894. 

  3894. <a name="l03862"></a>03862 
    3895. 

  3895. <a name="l03863"></a>03863 
    3896. 

  3896. <a name="l03864"></a>03864 <span class="comment">/*******************  Bit definition for TIM_CCR2 register  *******************/</span>
    3897. 

  3897. <a name="l03865"></a>03865 <span class="preprocessor">#define  TIM_CCR2_CCR2                       ((u16)0xFFFF)            </span><span class="comment">/* Capture/Compare 2 Value */</span>
    3898. 

  3898. <a name="l03866"></a>03866 
    3899. 

  3899. <a name="l03867"></a>03867 
    3900. 

  3900. <a name="l03868"></a>03868 <span class="comment">/*******************  Bit definition for TIM_CCR3 register  *******************/</span>
    3901. 

  3901. <a name="l03869"></a>03869 <span class="preprocessor">#define  TIM_CCR3_CCR3                       ((u16)0xFFFF)            </span><span class="comment">/* Capture/Compare 3 Value */</span>
    3902. 

  3902. <a name="l03870"></a>03870 
    3903. 

  3903. <a name="l03871"></a>03871 
    3904. 

  3904. <a name="l03872"></a>03872 <span class="comment">/*******************  Bit definition for TIM_CCR4 register  *******************/</span>
    3905. 

  3905. <a name="l03873"></a>03873 <span class="preprocessor">#define  TIM_CCR4_CCR4                       ((u16)0xFFFF)            </span><span class="comment">/* Capture/Compare 4 Value */</span>
    3906. 

  3906. <a name="l03874"></a>03874 
    3907. 

  3907. <a name="l03875"></a>03875 
    3908. 

  3908. <a name="l03876"></a>03876 <span class="comment">/*******************  Bit definition for TIM_BDTR register  *******************/</span>
    3909. 

  3909. <a name="l03877"></a>03877 <span class="preprocessor">#define  TIM_BDTR_DTG                        ((u16)0x00FF)            </span><span class="comment">/* DTG[0:7] bits (Dead-Time Generator set-up) */</span>
    3910. 

  3910. <a name="l03878"></a>03878 <span class="preprocessor">#define  TIM_BDTR_DTG_0                      ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    3911. 

  3911. <a name="l03879"></a>03879 <span class="preprocessor">#define  TIM_BDTR_DTG_1                      ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    3912. 

  3912. <a name="l03880"></a>03880 <span class="preprocessor">#define  TIM_BDTR_DTG_2                      ((u16)0x0004)            </span><span class="comment">/* Bit 2 */</span>
    3913. 

  3913. <a name="l03881"></a>03881 <span class="preprocessor">#define  TIM_BDTR_DTG_3                      ((u16)0x0008)            </span><span class="comment">/* Bit 3 */</span>
    3914. 

  3914. <a name="l03882"></a>03882 <span class="preprocessor">#define  TIM_BDTR_DTG_4                      ((u16)0x0010)            </span><span class="comment">/* Bit 4 */</span>
    3915. 

  3915. <a name="l03883"></a>03883 <span class="preprocessor">#define  TIM_BDTR_DTG_5                      ((u16)0x0020)            </span><span class="comment">/* Bit 5 */</span>
    3916. 

  3916. <a name="l03884"></a>03884 <span class="preprocessor">#define  TIM_BDTR_DTG_6                      ((u16)0x0040)            </span><span class="comment">/* Bit 6 */</span>
    3917. 

  3917. <a name="l03885"></a>03885 <span class="preprocessor">#define  TIM_BDTR_DTG_7                      ((u16)0x0080)            </span><span class="comment">/* Bit 7 */</span>
    3918. 

  3918. <a name="l03886"></a>03886 
    3919. 

  3919. <a name="l03887"></a>03887 <span class="preprocessor">#define  TIM_BDTR_LOCK                       ((u16)0x0300)            </span><span class="comment">/* LOCK[1:0] bits (Lock Configuration) */</span>
    3920. 

  3920. <a name="l03888"></a>03888 <span class="preprocessor">#define  TIM_BDTR_LOCK_0                     ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3921. 

  3921. <a name="l03889"></a>03889 <span class="preprocessor">#define  TIM_BDTR_LOCK_1                     ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3922. 

  3922. <a name="l03890"></a>03890 
    3923. 

  3923. <a name="l03891"></a>03891 <span class="preprocessor">#define  TIM_BDTR_OSSI                       ((u16)0x0400)            </span><span class="comment">/* Off-State Selection for Idle mode */</span>
    3924. 

  3924. <a name="l03892"></a>03892 <span class="preprocessor">#define  TIM_BDTR_OSSR                       ((u16)0x0800)            </span><span class="comment">/* Off-State Selection for Run mode */</span>
    3925. 

  3925. <a name="l03893"></a>03893 <span class="preprocessor">#define  TIM_BDTR_BKE                        ((u16)0x1000)            </span><span class="comment">/* Break enable */</span>
    3926. 

  3926. <a name="l03894"></a>03894 <span class="preprocessor">#define  TIM_BDTR_BKP                        ((u16)0x2000)            </span><span class="comment">/* Break Polarity */</span>
    3927. 

  3927. <a name="l03895"></a>03895 <span class="preprocessor">#define  TIM_BDTR_AOE                        ((u16)0x4000)            </span><span class="comment">/* Automatic Output enable */</span>
    3928. 

  3928. <a name="l03896"></a>03896 <span class="preprocessor">#define  TIM_BDTR_MOE                        ((u16)0x8000)            </span><span class="comment">/* Main Output enable */</span>
    3929. 

  3929. <a name="l03897"></a>03897 
    3930. 

  3930. <a name="l03898"></a>03898 
    3931. 

  3931. <a name="l03899"></a>03899 <span class="comment">/*******************  Bit definition for TIM_DCR register  ********************/</span>
    3932. 

  3932. <a name="l03900"></a>03900 <span class="preprocessor">#define  TIM_DCR_DBA                         ((u16)0x001F)            </span><span class="comment">/* DBA[4:0] bits (DMA Base Address) */</span>
    3933. 

  3933. <a name="l03901"></a>03901 <span class="preprocessor">#define  TIM_DCR_DBA_0                       ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    3934. 

  3934. <a name="l03902"></a>03902 <span class="preprocessor">#define  TIM_DCR_DBA_1                       ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    3935. 

  3935. <a name="l03903"></a>03903 <span class="preprocessor">#define  TIM_DCR_DBA_2                       ((u16)0x0004)            </span><span class="comment">/* Bit 2 */</span>
    3936. 

  3936. <a name="l03904"></a>03904 <span class="preprocessor">#define  TIM_DCR_DBA_3                       ((u16)0x0008)            </span><span class="comment">/* Bit 3 */</span>
    3937. 

  3937. <a name="l03905"></a>03905 <span class="preprocessor">#define  TIM_DCR_DBA_4                       ((u16)0x0010)            </span><span class="comment">/* Bit 4 */</span>
    3938. 

  3938. <a name="l03906"></a>03906 
    3939. 

  3939. <a name="l03907"></a>03907 <span class="preprocessor">#define  TIM_DCR_DBL                         ((u16)0x1F00)            </span><span class="comment">/* DBL[4:0] bits (DMA Burst Length) */</span>
    3940. 

  3940. <a name="l03908"></a>03908 <span class="preprocessor">#define  TIM_DCR_DBL_0                       ((u16)0x0100)            </span><span class="comment">/* Bit 0 */</span>
    3941. 

  3941. <a name="l03909"></a>03909 <span class="preprocessor">#define  TIM_DCR_DBL_1                       ((u16)0x0200)            </span><span class="comment">/* Bit 1 */</span>
    3942. 

  3942. <a name="l03910"></a>03910 <span class="preprocessor">#define  TIM_DCR_DBL_2                       ((u16)0x0400)            </span><span class="comment">/* Bit 2 */</span>
    3943. 

  3943. <a name="l03911"></a>03911 <span class="preprocessor">#define  TIM_DCR_DBL_3                       ((u16)0x0800)            </span><span class="comment">/* Bit 3 */</span>
    3944. 

  3944. <a name="l03912"></a>03912 <span class="preprocessor">#define  TIM_DCR_DBL_4                       ((u16)0x1000)            </span><span class="comment">/* Bit 4 */</span>
    3945. 

  3945. <a name="l03913"></a>03913 
    3946. 

  3946. <a name="l03914"></a>03914 
    3947. 

  3947. <a name="l03915"></a>03915 <span class="comment">/*******************  Bit definition for TIM_DMAR register  *******************/</span>
    3948. 

  3948. <a name="l03916"></a>03916 <span class="preprocessor">#define  TIM_DMAR_DMAB                       ((u16)0xFFFF)            </span><span class="comment">/* DMA register for burst accesses */</span>
    3949. 

  3949. <a name="l03917"></a>03917 
    3950. 

  3950. <a name="l03918"></a>03918 
    3951. 

  3951. <a name="l03919"></a>03919 
    3952. 

  3952. <a name="l03920"></a>03920 <span class="comment">/******************************************************************************/</span>
    3953. 

  3953. <a name="l03921"></a>03921 <span class="comment">/*                                                                            */</span>
    3954. 

  3954. <a name="l03922"></a>03922 <span class="comment">/*                             Real-Time Clock                                */</span>
    3955. 

  3955. <a name="l03923"></a>03923 <span class="comment">/*                                                                            */</span>
    3956. 

  3956. <a name="l03924"></a>03924 <span class="comment">/******************************************************************************/</span>
    3957. 

  3957. <a name="l03925"></a>03925 
    3958. 

  3958. <a name="l03926"></a>03926 <span class="comment">/*******************  Bit definition for RTC_CRH register  ********************/</span>
    3959. 

  3959. <a name="l03927"></a>03927 <span class="preprocessor">#define  RTC_CRH_SECIE                       ((u8)0x01)               </span><span class="comment">/* Second Interrupt Enable */</span>
    3960. 

  3960. <a name="l03928"></a>03928 <span class="preprocessor">#define  RTC_CRH_ALRIE                       ((u8)0x02)               </span><span class="comment">/* Alarm Interrupt Enable */</span>
    3961. 

  3961. <a name="l03929"></a>03929 <span class="preprocessor">#define  RTC_CRH_OWIE                        ((u8)0x04)               </span><span class="comment">/* OverfloW Interrupt Enable */</span>
    3962. 

  3962. <a name="l03930"></a>03930 
    3963. 

  3963. <a name="l03931"></a>03931 
    3964. 

  3964. <a name="l03932"></a>03932 <span class="comment">/*******************  Bit definition for RTC_CRL register  ********************/</span>
    3965. 

  3965. <a name="l03933"></a>03933 <span class="preprocessor">#define  RTC_CRL_SECF                        ((u8)0x01)               </span><span class="comment">/* Second Flag */</span>
    3966. 

  3966. <a name="l03934"></a>03934 <span class="preprocessor">#define  RTC_CRL_ALRF                        ((u8)0x02)               </span><span class="comment">/* Alarm Flag */</span>
    3967. 

  3967. <a name="l03935"></a>03935 <span class="preprocessor">#define  RTC_CRL_OWF                         ((u8)0x04)               </span><span class="comment">/* OverfloW Flag */</span>
    3968. 

  3968. <a name="l03936"></a>03936 <span class="preprocessor">#define  RTC_CRL_RSF                         ((u8)0x08)               </span><span class="comment">/* Registers Synchronized Flag */</span>
    3969. 

  3969. <a name="l03937"></a>03937 <span class="preprocessor">#define  RTC_CRL_CNF                         ((u8)0x10)               </span><span class="comment">/* Configuration Flag */</span>
    3970. 

  3970. <a name="l03938"></a>03938 <span class="preprocessor">#define  RTC_CRL_RTOFF                       ((u8)0x20)               </span><span class="comment">/* RTC operation OFF */</span>
    3971. 

  3971. <a name="l03939"></a>03939 
    3972. 

  3972. <a name="l03940"></a>03940 
    3973. 

  3973. <a name="l03941"></a>03941 <span class="comment">/*******************  Bit definition for RTC_PRLH register  *******************/</span>
    3974. 

  3974. <a name="l03942"></a>03942 <span class="preprocessor">#define  RTC_PRLH_PRL                        ((u16)0x000F)            </span><span class="comment">/* RTC Prescaler Reload Value High */</span>
    3975. 

  3975. <a name="l03943"></a>03943 
    3976. 

  3976. <a name="l03944"></a>03944 
    3977. 

  3977. <a name="l03945"></a>03945 <span class="comment">/*******************  Bit definition for RTC_PRLL register  *******************/</span>
    3978. 

  3978. <a name="l03946"></a>03946 <span class="preprocessor">#define  RTC_PRLL_PRL                        ((u16)0xFFFF)            </span><span class="comment">/* RTC Prescaler Reload Value Low */</span>
    3979. 

  3979. <a name="l03947"></a>03947 
    3980. 

  3980. <a name="l03948"></a>03948 
    3981. 

  3981. <a name="l03949"></a>03949 <span class="comment">/*******************  Bit definition for RTC_DIVH register  *******************/</span>
    3982. 

  3982. <a name="l03950"></a>03950 <span class="preprocessor">#define  RTC_DIVH_RTC_DIV                    ((u16)0x000F)            </span><span class="comment">/* RTC Clock Divider High */</span>
    3983. 

  3983. <a name="l03951"></a>03951 
    3984. 

  3984. <a name="l03952"></a>03952 
    3985. 

  3985. <a name="l03953"></a>03953 <span class="comment">/*******************  Bit definition for RTC_DIVL register  *******************/</span>
    3986. 

  3986. <a name="l03954"></a>03954 <span class="preprocessor">#define  RTC_DIVL_RTC_DIV                    ((u16)0xFFFF)            </span><span class="comment">/* RTC Clock Divider Low */</span>
    3987. 

  3987. <a name="l03955"></a>03955 
    3988. 

  3988. <a name="l03956"></a>03956 
    3989. 

  3989. <a name="l03957"></a>03957 <span class="comment">/*******************  Bit definition for RTC_CNTH register  *******************/</span>
    3990. 

  3990. <a name="l03958"></a>03958 <span class="preprocessor">#define  RTC_CNTH_RTC_CNT                    ((u16)0xFFFF)            </span><span class="comment">/* RTC Counter High */</span>
    3991. 

  3991. <a name="l03959"></a>03959 
    3992. 

  3992. <a name="l03960"></a>03960 
    3993. 

  3993. <a name="l03961"></a>03961 <span class="comment">/*******************  Bit definition for RTC_CNTL register  *******************/</span>
    3994. 

  3994. <a name="l03962"></a>03962 <span class="preprocessor">#define  RTC_CNTL_RTC_CNT                    ((u16)0xFFFF)            </span><span class="comment">/* RTC Counter Low */</span>
    3995. 

  3995. <a name="l03963"></a>03963 
    3996. 

  3996. <a name="l03964"></a>03964 
    3997. 

  3997. <a name="l03965"></a>03965 <span class="comment">/*******************  Bit definition for RTC_ALRH register  *******************/</span>
    3998. 

  3998. <a name="l03966"></a>03966 <span class="preprocessor">#define  RTC_ALRH_RTC_ALR                    ((u16)0xFFFF)            </span><span class="comment">/* RTC Alarm High */</span>
    3999. 

  3999. <a name="l03967"></a>03967 
    4000. 

  4000. <a name="l03968"></a>03968 
    4001. 

  4001. <a name="l03969"></a>03969 <span class="comment">/*******************  Bit definition for RTC_ALRL register  *******************/</span>
    4002. 

  4002. <a name="l03970"></a>03970 <span class="preprocessor">#define  RTC_ALRL_RTC_ALR                    ((u16)0xFFFF)            </span><span class="comment">/* RTC Alarm Low */</span>
    4003. 

  4003. <a name="l03971"></a>03971 
    4004. 

  4004. <a name="l03972"></a>03972 
    4005. 

  4005. <a name="l03973"></a>03973 
    4006. 

  4006. <a name="l03974"></a>03974 <span class="comment">/******************************************************************************/</span>
    4007. 

  4007. <a name="l03975"></a>03975 <span class="comment">/*                                                                            */</span>
    4008. 

  4008. <a name="l03976"></a>03976 <span class="comment">/*                           Independent WATCHDOG                             */</span>
    4009. 

  4009. <a name="l03977"></a>03977 <span class="comment">/*                                                                            */</span>
    4010. 

  4010. <a name="l03978"></a>03978 <span class="comment">/******************************************************************************/</span>
    4011. 

  4011. <a name="l03979"></a>03979 
    4012. 

  4012. <a name="l03980"></a>03980 <span class="comment">/*******************  Bit definition for IWDG_KR register  ********************/</span>
    4013. 

  4013. <a name="l03981"></a>03981 <span class="preprocessor">#define  IWDG_KR_KEY                         ((u16)0xFFFF)            </span><span class="comment">/* Key value (write only, read 0000h) */</span>
    4014. 

  4014. <a name="l03982"></a>03982 
    4015. 

  4015. <a name="l03983"></a>03983 
    4016. 

  4016. <a name="l03984"></a>03984 <span class="comment">/*******************  Bit definition for IWDG_PR register  ********************/</span>
    4017. 

  4017. <a name="l03985"></a>03985 <span class="preprocessor">#define  IWDG_PR_PR                          ((u8)0x07)               </span><span class="comment">/* PR[2:0] (Prescaler divider) */</span>
    4018. 

  4018. <a name="l03986"></a>03986 <span class="preprocessor">#define  IWDG_PR_PR_0                        ((u8)0x01)               </span><span class="comment">/* Bit 0 */</span>
    4019. 

  4019. <a name="l03987"></a>03987 <span class="preprocessor">#define  IWDG_PR_PR_1                        ((u8)0x02)               </span><span class="comment">/* Bit 1 */</span>
    4020. 

  4020. <a name="l03988"></a>03988 <span class="preprocessor">#define  IWDG_PR_PR_2                        ((u8)0x04)               </span><span class="comment">/* Bit 2 */</span>
    4021. 

  4021. <a name="l03989"></a>03989 
    4022. 

  4022. <a name="l03990"></a>03990 
    4023. 

  4023. <a name="l03991"></a>03991 <span class="comment">/*******************  Bit definition for IWDG_RLR register  *******************/</span>
    4024. 

  4024. <a name="l03992"></a>03992 <span class="preprocessor">#define  IWDG_RLR_RL                         ((u16)0x0FFF)            </span><span class="comment">/* Watchdog counter reload value */</span>
    4025. 

  4025. <a name="l03993"></a>03993 
    4026. 

  4026. <a name="l03994"></a>03994 
    4027. 

  4027. <a name="l03995"></a>03995 <span class="comment">/*******************  Bit definition for IWDG_SR register  ********************/</span>
    4028. 

  4028. <a name="l03996"></a>03996 <span class="preprocessor">#define  IWDG_SR_PVU                         ((u8)0x01)               </span><span class="comment">/* Watchdog prescaler value update */</span>
    4029. 

  4029. <a name="l03997"></a>03997 <span class="preprocessor">#define  IWDG_SR_RVU                         ((u8)0x02)               </span><span class="comment">/* Watchdog counter reload value update */</span>
    4030. 

  4030. <a name="l03998"></a>03998 
    4031. 

  4031. <a name="l03999"></a>03999 
    4032. 

  4032. <a name="l04000"></a>04000 
    4033. 

  4033. <a name="l04001"></a>04001 <span class="comment">/******************************************************************************/</span>
    4034. 

  4034. <a name="l04002"></a>04002 <span class="comment">/*                                                                            */</span>
    4035. 

  4035. <a name="l04003"></a>04003 <span class="comment">/*                            Window WATCHDOG                                 */</span>
    4036. 

  4036. <a name="l04004"></a>04004 <span class="comment">/*                                                                            */</span>
    4037. 

  4037. <a name="l04005"></a>04005 <span class="comment">/******************************************************************************/</span>
    4038. 

  4038. <a name="l04006"></a>04006 
    4039. 

  4039. <a name="l04007"></a>04007 <span class="comment">/*******************  Bit definition for WWDG_CR register  ********************/</span>
    4040. 

  4040. <a name="l04008"></a>04008 <span class="preprocessor">#define  WWDG_CR_T                           ((u8)0x7F)               </span><span class="comment">/* T[6:0] bits (7-Bit counter (MSB to LSB)) */</span>
    4041. 

  4041. <a name="l04009"></a>04009 <span class="preprocessor">#define  WWDG_CR_T0                          ((u8)0x01)               </span><span class="comment">/* Bit 0 */</span>
    4042. 

  4042. <a name="l04010"></a>04010 <span class="preprocessor">#define  WWDG_CR_T1                          ((u8)0x02)               </span><span class="comment">/* Bit 1 */</span>
    4043. 

  4043. <a name="l04011"></a>04011 <span class="preprocessor">#define  WWDG_CR_T2                          ((u8)0x04)               </span><span class="comment">/* Bit 2 */</span>
    4044. 

  4044. <a name="l04012"></a>04012 <span class="preprocessor">#define  WWDG_CR_T3                          ((u8)0x08)               </span><span class="comment">/* Bit 3 */</span>
    4045. 

  4045. <a name="l04013"></a>04013 <span class="preprocessor">#define  WWDG_CR_T4                          ((u8)0x10)               </span><span class="comment">/* Bit 4 */</span>
    4046. 

  4046. <a name="l04014"></a>04014 <span class="preprocessor">#define  WWDG_CR_T5                          ((u8)0x20)               </span><span class="comment">/* Bit 5 */</span>
    4047. 

  4047. <a name="l04015"></a>04015 <span class="preprocessor">#define  WWDG_CR_T6                          ((u8)0x40)               </span><span class="comment">/* Bit 6 */</span>
    4048. 

  4048. <a name="l04016"></a>04016 
    4049. 

  4049. <a name="l04017"></a>04017 <span class="preprocessor">#define  WWDG_CR_WDGA                        ((u8)0x80)               </span><span class="comment">/* Activation bit */</span>
    4050. 

  4050. <a name="l04018"></a>04018 
    4051. 

  4051. <a name="l04019"></a>04019 
    4052. 

  4052. <a name="l04020"></a>04020 <span class="comment">/*******************  Bit definition for WWDG_CFR register  *******************/</span>
    4053. 

  4053. <a name="l04021"></a>04021 <span class="preprocessor">#define  WWDG_CFR_W                          ((u16)0x007F)            </span><span class="comment">/* W[6:0] bits (7-bit window value) */</span>
    4054. 

  4054. <a name="l04022"></a>04022 <span class="preprocessor">#define  WWDG_CFR_W0                         ((u16)0x0001)            </span><span class="comment">/* Bit 0 */</span>
    4055. 

  4055. <a name="l04023"></a>04023 <span class="preprocessor">#define  WWDG_CFR_W1                         ((u16)0x0002)            </span><span class="comment">/* Bit 1 */</span>
    4056. 

  4056. <a name="l04024"></a>04024 <span class="preprocessor">#define  WWDG_CFR_W2                         ((u16)0x0004)            </span><span class="comment">/* Bit 2 */</span>
    4057. 

  4057. <a name="l04025"></a>04025 <span class="preprocessor">#define  WWDG_CFR_W3                         ((u16)0x0008)            </span><span class="comment">/* Bit 3 */</span>
    4058. 

  4058. <a name="l04026"></a>04026 <span class="preprocessor">#define  WWDG_CFR_W4                         ((u16)0x0010)            </span><span class="comment">/* Bit 4 */</span>
    4059. 

  4059. <a name="l04027"></a>04027 <span class="preprocessor">#define  WWDG_CFR_W5                         ((u16)0x0020)            </span><span class="comment">/* Bit 5 */</span>
    4060. 

  4060. <a name="l04028"></a>04028 <span class="preprocessor">#define  WWDG_CFR_W6                         ((u16)0x0040)            </span><span class="comment">/* Bit 6 */</span>
    4061. 

  4061. <a name="l04029"></a>04029 
    4062. 

  4062. <a name="l04030"></a>04030 <span class="preprocessor">#define  WWDG_CFR_WDGTB                      ((u16)0x0180)            </span><span class="comment">/* WDGTB[1:0] bits (Timer Base) */</span>
    4063. 

  4063. <a name="l04031"></a>04031 <span class="preprocessor">#define  WWDG_CFR_WDGTB0                     ((u16)0x0080)            </span><span class="comment">/* Bit 0 */</span>
    4064. 

  4064. <a name="l04032"></a>04032 <span class="preprocessor">#define  WWDG_CFR_WDGTB1                     ((u16)0x0100)            </span><span class="comment">/* Bit 1 */</span>
    4065. 

  4065. <a name="l04033"></a>04033 
    4066. 

  4066. <a name="l04034"></a>04034 <span class="preprocessor">#define  WWDG_CFR_EWI                        ((u16)0x0200)            </span><span class="comment">/* Early Wakeup Interrupt */</span>
    4067. 

  4067. <a name="l04035"></a>04035 
    4068. 

  4068. <a name="l04036"></a>04036 
    4069. 

  4069. <a name="l04037"></a>04037 <span class="comment">/*******************  Bit definition for WWDG_SR register  ********************/</span>
    4070. 

  4070. <a name="l04038"></a>04038 <span class="preprocessor">#define  WWDG_SR_EWIF                        ((u8)0x01)               </span><span class="comment">/* Early Wakeup Interrupt Flag */</span>
    4071. 

  4071. <a name="l04039"></a>04039 
    4072. 

  4072. <a name="l04040"></a>04040 
    4073. 

  4073. <a name="l04041"></a>04041 
    4074. 

  4074. <a name="l04042"></a>04042 <span class="comment">/******************************************************************************/</span>
    4075. 

  4075. <a name="l04043"></a>04043 <span class="comment">/*                                                                            */</span>
    4076. 

  4076. <a name="l04044"></a>04044 <span class="comment">/*                       Flexible Static Memory Controller                    */</span>
    4077. 

  4077. <a name="l04045"></a>04045 <span class="comment">/*                                                                            */</span>
    4078. 

  4078. <a name="l04046"></a>04046 <span class="comment">/******************************************************************************/</span>
    4079. 

  4079. <a name="l04047"></a>04047 
    4080. 

  4080. <a name="l04048"></a>04048 <span class="comment">/******************  Bit definition for FSMC_BCR1 register  *******************/</span>
    4081. 

  4081. <a name="l04049"></a>04049 <span class="preprocessor">#define  FSMC_BCR1_MBKEN                     ((u32)0x00000001)        </span><span class="comment">/* Memory bank enable bit */</span>
    4082. 

  4082. <a name="l04050"></a>04050 <span class="preprocessor">#define  FSMC_BCR1_MUXEN                     ((u32)0x00000002)        </span><span class="comment">/* Address/data multiplexing enable bit */</span>
    4083. 

  4083. <a name="l04051"></a>04051 
    4084. 

  4084. <a name="l04052"></a>04052 <span class="preprocessor">#define  FSMC_BCR1_MTYP                      ((u32)0x0000000C)        </span><span class="comment">/* MTYP[1:0] bits (Memory type) */</span>
    4085. 

  4085. <a name="l04053"></a>04053 <span class="preprocessor">#define  FSMC_BCR1_MTYP_0                    ((u32)0x00000004)        </span><span class="comment">/* Bit 0 */</span>
    4086. 

  4086. <a name="l04054"></a>04054 <span class="preprocessor">#define  FSMC_BCR1_MTYP_1                    (
    4087.