/arch/arm/mach-omap2/omap_hwmod_44xx_data.c

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  1. /*
  2. * Hardware modules present on the OMAP44xx chips
  3. *
  4. * Copyright (C) 2009-2011 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley
  8. * Benoit Cousson
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/io.h>
  21. #include <plat/omap_hwmod.h>
  22. #include <plat/cpu.h>
  23. #include <plat/i2c.h>
  24. #include <plat/gpio.h>
  25. #include <plat/dma.h>
  26. #include <plat/mcspi.h>
  27. #include <plat/mcbsp.h>
  28. #include <plat/mmc.h>
  29. #include <plat/i2c.h>
  30. #include "omap_hwmod_common_data.h"
  31. #include "cm1_44xx.h"
  32. #include "cm2_44xx.h"
  33. #include "prm44xx.h"
  34. #include "prm-regbits-44xx.h"
  35. #include "wd_timer.h"
  36. /* Base offset for all OMAP4 interrupts external to MPUSS */
  37. #define OMAP44XX_IRQ_GIC_START 32
  38. /* Base offset for all OMAP4 dma requests */
  39. #define OMAP44XX_DMA_REQ_START 1
  40. /* Backward references (IPs with Bus Master capability) */
  41. static struct omap_hwmod omap44xx_aess_hwmod;
  42. static struct omap_hwmod omap44xx_dma_system_hwmod;
  43. static struct omap_hwmod omap44xx_dmm_hwmod;
  44. static struct omap_hwmod omap44xx_dsp_hwmod;
  45. static struct omap_hwmod omap44xx_dss_hwmod;
  46. static struct omap_hwmod omap44xx_emif_fw_hwmod;
  47. static struct omap_hwmod omap44xx_hsi_hwmod;
  48. static struct omap_hwmod omap44xx_ipu_hwmod;
  49. static struct omap_hwmod omap44xx_iss_hwmod;
  50. static struct omap_hwmod omap44xx_iva_hwmod;
  51. static struct omap_hwmod omap44xx_l3_instr_hwmod;
  52. static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  53. static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  54. static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  55. static struct omap_hwmod omap44xx_l4_abe_hwmod;
  56. static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  57. static struct omap_hwmod omap44xx_l4_per_hwmod;
  58. static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  59. static struct omap_hwmod omap44xx_mmc1_hwmod;
  60. static struct omap_hwmod omap44xx_mmc2_hwmod;
  61. static struct omap_hwmod omap44xx_mpu_hwmod;
  62. static struct omap_hwmod omap44xx_mpu_private_hwmod;
  63. static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  64. /*
  65. * Interconnects omap_hwmod structures
  66. * hwmods that compose the global OMAP interconnect
  67. */
  68. /*
  69. * 'dmm' class
  70. * instance(s): dmm
  71. */
  72. static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  73. .name = "dmm",
  74. };
  75. /* dmm */
  76. static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  77. { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  78. { .irq = -1 }
  79. };
  80. /* l3_main_1 -> dmm */
  81. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  82. .master = &omap44xx_l3_main_1_hwmod,
  83. .slave = &omap44xx_dmm_hwmod,
  84. .clk = "l3_div_ck",
  85. .user = OCP_USER_SDMA,
  86. };
  87. static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  88. {
  89. .pa_start = 0x4e000000,
  90. .pa_end = 0x4e0007ff,
  91. .flags = ADDR_TYPE_RT
  92. },
  93. { }
  94. };
  95. /* mpu -> dmm */
  96. static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  97. .master = &omap44xx_mpu_hwmod,
  98. .slave = &omap44xx_dmm_hwmod,
  99. .clk = "l3_div_ck",
  100. .addr = omap44xx_dmm_addrs,
  101. .user = OCP_USER_MPU,
  102. };
  103. /* dmm slave ports */
  104. static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  105. &omap44xx_l3_main_1__dmm,
  106. &omap44xx_mpu__dmm,
  107. };
  108. static struct omap_hwmod omap44xx_dmm_hwmod = {
  109. .name = "dmm",
  110. .class = &omap44xx_dmm_hwmod_class,
  111. .clkdm_name = "l3_emif_clkdm",
  112. .prcm = {
  113. .omap4 = {
  114. .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  115. .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  116. },
  117. },
  118. .slaves = omap44xx_dmm_slaves,
  119. .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
  120. .mpu_irqs = omap44xx_dmm_irqs,
  121. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  122. };
  123. /*
  124. * 'emif_fw' class
  125. * instance(s): emif_fw
  126. */
  127. static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
  128. .name = "emif_fw",
  129. };
  130. /* emif_fw */
  131. /* dmm -> emif_fw */
  132. static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
  133. .master = &omap44xx_dmm_hwmod,
  134. .slave = &omap44xx_emif_fw_hwmod,
  135. .clk = "l3_div_ck",
  136. .user = OCP_USER_MPU | OCP_USER_SDMA,
  137. };
  138. static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
  139. {
  140. .pa_start = 0x4a20c000,
  141. .pa_end = 0x4a20c0ff,
  142. .flags = ADDR_TYPE_RT
  143. },
  144. { }
  145. };
  146. /* l4_cfg -> emif_fw */
  147. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
  148. .master = &omap44xx_l4_cfg_hwmod,
  149. .slave = &omap44xx_emif_fw_hwmod,
  150. .clk = "l4_div_ck",
  151. .addr = omap44xx_emif_fw_addrs,
  152. .user = OCP_USER_MPU,
  153. };
  154. /* emif_fw slave ports */
  155. static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
  156. &omap44xx_dmm__emif_fw,
  157. &omap44xx_l4_cfg__emif_fw,
  158. };
  159. static struct omap_hwmod omap44xx_emif_fw_hwmod = {
  160. .name = "emif_fw",
  161. .class = &omap44xx_emif_fw_hwmod_class,
  162. .clkdm_name = "l3_emif_clkdm",
  163. .prcm = {
  164. .omap4 = {
  165. .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
  166. .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
  167. },
  168. },
  169. .slaves = omap44xx_emif_fw_slaves,
  170. .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
  171. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  172. };
  173. /*
  174. * 'l3' class
  175. * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  176. */
  177. static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  178. .name = "l3",
  179. };
  180. /* l3_instr */
  181. /* iva -> l3_instr */
  182. static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
  183. .master = &omap44xx_iva_hwmod,
  184. .slave = &omap44xx_l3_instr_hwmod,
  185. .clk = "l3_div_ck",
  186. .user = OCP_USER_MPU | OCP_USER_SDMA,
  187. };
  188. /* l3_main_3 -> l3_instr */
  189. static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
  190. .master = &omap44xx_l3_main_3_hwmod,
  191. .slave = &omap44xx_l3_instr_hwmod,
  192. .clk = "l3_div_ck",
  193. .user = OCP_USER_MPU | OCP_USER_SDMA,
  194. };
  195. /* l3_instr slave ports */
  196. static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
  197. &omap44xx_iva__l3_instr,
  198. &omap44xx_l3_main_3__l3_instr,
  199. };
  200. static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  201. .name = "l3_instr",
  202. .class = &omap44xx_l3_hwmod_class,
  203. .clkdm_name = "l3_instr_clkdm",
  204. .prcm = {
  205. .omap4 = {
  206. .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  207. .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  208. .modulemode = MODULEMODE_HWCTRL,
  209. },
  210. },
  211. .slaves = omap44xx_l3_instr_slaves,
  212. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
  213. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  214. };
  215. /* l3_main_1 */
  216. static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
  217. { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
  218. { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
  219. { .irq = -1 }
  220. };
  221. /* dsp -> l3_main_1 */
  222. static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
  223. .master = &omap44xx_dsp_hwmod,
  224. .slave = &omap44xx_l3_main_1_hwmod,
  225. .clk = "l3_div_ck",
  226. .user = OCP_USER_MPU | OCP_USER_SDMA,
  227. };
  228. /* dss -> l3_main_1 */
  229. static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
  230. .master = &omap44xx_dss_hwmod,
  231. .slave = &omap44xx_l3_main_1_hwmod,
  232. .clk = "l3_div_ck",
  233. .user = OCP_USER_MPU | OCP_USER_SDMA,
  234. };
  235. /* l3_main_2 -> l3_main_1 */
  236. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
  237. .master = &omap44xx_l3_main_2_hwmod,
  238. .slave = &omap44xx_l3_main_1_hwmod,
  239. .clk = "l3_div_ck",
  240. .user = OCP_USER_MPU | OCP_USER_SDMA,
  241. };
  242. /* l4_cfg -> l3_main_1 */
  243. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
  244. .master = &omap44xx_l4_cfg_hwmod,
  245. .slave = &omap44xx_l3_main_1_hwmod,
  246. .clk = "l4_div_ck",
  247. .user = OCP_USER_MPU | OCP_USER_SDMA,
  248. };
  249. /* mmc1 -> l3_main_1 */
  250. static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
  251. .master = &omap44xx_mmc1_hwmod,
  252. .slave = &omap44xx_l3_main_1_hwmod,
  253. .clk = "l3_div_ck",
  254. .user = OCP_USER_MPU | OCP_USER_SDMA,
  255. };
  256. /* mmc2 -> l3_main_1 */
  257. static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
  258. .master = &omap44xx_mmc2_hwmod,
  259. .slave = &omap44xx_l3_main_1_hwmod,
  260. .clk = "l3_div_ck",
  261. .user = OCP_USER_MPU | OCP_USER_SDMA,
  262. };
  263. static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
  264. {
  265. .pa_start = 0x44000000,
  266. .pa_end = 0x44000fff,
  267. .flags = ADDR_TYPE_RT
  268. },
  269. { }
  270. };
  271. /* mpu -> l3_main_1 */
  272. static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
  273. .master = &omap44xx_mpu_hwmod,
  274. .slave = &omap44xx_l3_main_1_hwmod,
  275. .clk = "l3_div_ck",
  276. .addr = omap44xx_l3_main_1_addrs,
  277. .user = OCP_USER_MPU,
  278. };
  279. /* l3_main_1 slave ports */
  280. static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
  281. &omap44xx_dsp__l3_main_1,
  282. &omap44xx_dss__l3_main_1,
  283. &omap44xx_l3_main_2__l3_main_1,
  284. &omap44xx_l4_cfg__l3_main_1,
  285. &omap44xx_mmc1__l3_main_1,
  286. &omap44xx_mmc2__l3_main_1,
  287. &omap44xx_mpu__l3_main_1,
  288. };
  289. static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  290. .name = "l3_main_1",
  291. .class = &omap44xx_l3_hwmod_class,
  292. .clkdm_name = "l3_1_clkdm",
  293. .mpu_irqs = omap44xx_l3_main_1_irqs,
  294. .prcm = {
  295. .omap4 = {
  296. .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  297. .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  298. },
  299. },
  300. .slaves = omap44xx_l3_main_1_slaves,
  301. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
  302. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  303. };
  304. /* l3_main_2 */
  305. /* dma_system -> l3_main_2 */
  306. static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
  307. .master = &omap44xx_dma_system_hwmod,
  308. .slave = &omap44xx_l3_main_2_hwmod,
  309. .clk = "l3_div_ck",
  310. .user = OCP_USER_MPU | OCP_USER_SDMA,
  311. };
  312. /* hsi -> l3_main_2 */
  313. static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
  314. .master = &omap44xx_hsi_hwmod,
  315. .slave = &omap44xx_l3_main_2_hwmod,
  316. .clk = "l3_div_ck",
  317. .user = OCP_USER_MPU | OCP_USER_SDMA,
  318. };
  319. /* ipu -> l3_main_2 */
  320. static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
  321. .master = &omap44xx_ipu_hwmod,
  322. .slave = &omap44xx_l3_main_2_hwmod,
  323. .clk = "l3_div_ck",
  324. .user = OCP_USER_MPU | OCP_USER_SDMA,
  325. };
  326. /* iss -> l3_main_2 */
  327. static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
  328. .master = &omap44xx_iss_hwmod,
  329. .slave = &omap44xx_l3_main_2_hwmod,
  330. .clk = "l3_div_ck",
  331. .user = OCP_USER_MPU | OCP_USER_SDMA,
  332. };
  333. /* iva -> l3_main_2 */
  334. static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
  335. .master = &omap44xx_iva_hwmod,
  336. .slave = &omap44xx_l3_main_2_hwmod,
  337. .clk = "l3_div_ck",
  338. .user = OCP_USER_MPU | OCP_USER_SDMA,
  339. };
  340. static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
  341. {
  342. .pa_start = 0x44800000,
  343. .pa_end = 0x44801fff,
  344. .flags = ADDR_TYPE_RT
  345. },
  346. { }
  347. };
  348. /* l3_main_1 -> l3_main_2 */
  349. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
  350. .master = &omap44xx_l3_main_1_hwmod,
  351. .slave = &omap44xx_l3_main_2_hwmod,
  352. .clk = "l3_div_ck",
  353. .addr = omap44xx_l3_main_2_addrs,
  354. .user = OCP_USER_MPU,
  355. };
  356. /* l4_cfg -> l3_main_2 */
  357. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
  358. .master = &omap44xx_l4_cfg_hwmod,
  359. .slave = &omap44xx_l3_main_2_hwmod,
  360. .clk = "l4_div_ck",
  361. .user = OCP_USER_MPU | OCP_USER_SDMA,
  362. };
  363. /* usb_otg_hs -> l3_main_2 */
  364. static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
  365. .master = &omap44xx_usb_otg_hs_hwmod,
  366. .slave = &omap44xx_l3_main_2_hwmod,
  367. .clk = "l3_div_ck",
  368. .user = OCP_USER_MPU | OCP_USER_SDMA,
  369. };
  370. /* l3_main_2 slave ports */
  371. static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
  372. &omap44xx_dma_system__l3_main_2,
  373. &omap44xx_hsi__l3_main_2,
  374. &omap44xx_ipu__l3_main_2,
  375. &omap44xx_iss__l3_main_2,
  376. &omap44xx_iva__l3_main_2,
  377. &omap44xx_l3_main_1__l3_main_2,
  378. &omap44xx_l4_cfg__l3_main_2,
  379. &omap44xx_usb_otg_hs__l3_main_2,
  380. };
  381. static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  382. .name = "l3_main_2",
  383. .class = &omap44xx_l3_hwmod_class,
  384. .clkdm_name = "l3_2_clkdm",
  385. .prcm = {
  386. .omap4 = {
  387. .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
  388. .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
  389. },
  390. },
  391. .slaves = omap44xx_l3_main_2_slaves,
  392. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
  393. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  394. };
  395. /* l3_main_3 */
  396. static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
  397. {
  398. .pa_start = 0x45000000,
  399. .pa_end = 0x45000fff,
  400. .flags = ADDR_TYPE_RT
  401. },
  402. { }
  403. };
  404. /* l3_main_1 -> l3_main_3 */
  405. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
  406. .master = &omap44xx_l3_main_1_hwmod,
  407. .slave = &omap44xx_l3_main_3_hwmod,
  408. .clk = "l3_div_ck",
  409. .addr = omap44xx_l3_main_3_addrs,
  410. .user = OCP_USER_MPU,
  411. };
  412. /* l3_main_2 -> l3_main_3 */
  413. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
  414. .master = &omap44xx_l3_main_2_hwmod,
  415. .slave = &omap44xx_l3_main_3_hwmod,
  416. .clk = "l3_div_ck",
  417. .user = OCP_USER_MPU | OCP_USER_SDMA,
  418. };
  419. /* l4_cfg -> l3_main_3 */
  420. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
  421. .master = &omap44xx_l4_cfg_hwmod,
  422. .slave = &omap44xx_l3_main_3_hwmod,
  423. .clk = "l4_div_ck",
  424. .user = OCP_USER_MPU | OCP_USER_SDMA,
  425. };
  426. /* l3_main_3 slave ports */
  427. static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
  428. &omap44xx_l3_main_1__l3_main_3,
  429. &omap44xx_l3_main_2__l3_main_3,
  430. &omap44xx_l4_cfg__l3_main_3,
  431. };
  432. static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  433. .name = "l3_main_3",
  434. .class = &omap44xx_l3_hwmod_class,
  435. .clkdm_name = "l3_instr_clkdm",
  436. .prcm = {
  437. .omap4 = {
  438. .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
  439. .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
  440. .modulemode = MODULEMODE_HWCTRL,
  441. },
  442. },
  443. .slaves = omap44xx_l3_main_3_slaves,
  444. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
  445. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  446. };
  447. /*
  448. * 'l4' class
  449. * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  450. */
  451. static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
  452. .name = "l4",
  453. };
  454. /* l4_abe */
  455. /* aess -> l4_abe */
  456. static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
  457. .master = &omap44xx_aess_hwmod,
  458. .slave = &omap44xx_l4_abe_hwmod,
  459. .clk = "ocp_abe_iclk",
  460. .user = OCP_USER_MPU | OCP_USER_SDMA,
  461. };
  462. /* dsp -> l4_abe */
  463. static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
  464. .master = &omap44xx_dsp_hwmod,
  465. .slave = &omap44xx_l4_abe_hwmod,
  466. .clk = "ocp_abe_iclk",
  467. .user = OCP_USER_MPU | OCP_USER_SDMA,
  468. };
  469. /* l3_main_1 -> l4_abe */
  470. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
  471. .master = &omap44xx_l3_main_1_hwmod,
  472. .slave = &omap44xx_l4_abe_hwmod,
  473. .clk = "l3_div_ck",
  474. .user = OCP_USER_MPU | OCP_USER_SDMA,
  475. };
  476. /* mpu -> l4_abe */
  477. static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
  478. .master = &omap44xx_mpu_hwmod,
  479. .slave = &omap44xx_l4_abe_hwmod,
  480. .clk = "ocp_abe_iclk",
  481. .user = OCP_USER_MPU | OCP_USER_SDMA,
  482. };
  483. /* l4_abe slave ports */
  484. static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
  485. &omap44xx_aess__l4_abe,
  486. &omap44xx_dsp__l4_abe,
  487. &omap44xx_l3_main_1__l4_abe,
  488. &omap44xx_mpu__l4_abe,
  489. };
  490. static struct omap_hwmod omap44xx_l4_abe_hwmod = {
  491. .name = "l4_abe",
  492. .class = &omap44xx_l4_hwmod_class,
  493. .clkdm_name = "abe_clkdm",
  494. .prcm = {
  495. .omap4 = {
  496. .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
  497. },
  498. },
  499. .slaves = omap44xx_l4_abe_slaves,
  500. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
  501. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  502. };
  503. /* l4_cfg */
  504. /* l3_main_1 -> l4_cfg */
  505. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
  506. .master = &omap44xx_l3_main_1_hwmod,
  507. .slave = &omap44xx_l4_cfg_hwmod,
  508. .clk = "l3_div_ck",
  509. .user = OCP_USER_MPU | OCP_USER_SDMA,
  510. };
  511. /* l4_cfg slave ports */
  512. static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
  513. &omap44xx_l3_main_1__l4_cfg,
  514. };
  515. static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
  516. .name = "l4_cfg",
  517. .class = &omap44xx_l4_hwmod_class,
  518. .clkdm_name = "l4_cfg_clkdm",
  519. .prcm = {
  520. .omap4 = {
  521. .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
  522. .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
  523. },
  524. },
  525. .slaves = omap44xx_l4_cfg_slaves,
  526. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
  527. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  528. };
  529. /* l4_per */
  530. /* l3_main_2 -> l4_per */
  531. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
  532. .master = &omap44xx_l3_main_2_hwmod,
  533. .slave = &omap44xx_l4_per_hwmod,
  534. .clk = "l3_div_ck",
  535. .user = OCP_USER_MPU | OCP_USER_SDMA,
  536. };
  537. /* l4_per slave ports */
  538. static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
  539. &omap44xx_l3_main_2__l4_per,
  540. };
  541. static struct omap_hwmod omap44xx_l4_per_hwmod = {
  542. .name = "l4_per",
  543. .class = &omap44xx_l4_hwmod_class,
  544. .clkdm_name = "l4_per_clkdm",
  545. .prcm = {
  546. .omap4 = {
  547. .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
  548. .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
  549. },
  550. },
  551. .slaves = omap44xx_l4_per_slaves,
  552. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
  553. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  554. };
  555. /* l4_wkup */
  556. /* l4_cfg -> l4_wkup */
  557. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
  558. .master = &omap44xx_l4_cfg_hwmod,
  559. .slave = &omap44xx_l4_wkup_hwmod,
  560. .clk = "l4_div_ck",
  561. .user = OCP_USER_MPU | OCP_USER_SDMA,
  562. };
  563. /* l4_wkup slave ports */
  564. static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
  565. &omap44xx_l4_cfg__l4_wkup,
  566. };
  567. static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
  568. .name = "l4_wkup",
  569. .class = &omap44xx_l4_hwmod_class,
  570. .clkdm_name = "l4_wkup_clkdm",
  571. .prcm = {
  572. .omap4 = {
  573. .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
  574. .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
  575. },
  576. },
  577. .slaves = omap44xx_l4_wkup_slaves,
  578. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
  579. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  580. };
  581. /*
  582. * 'mpu_bus' class
  583. * instance(s): mpu_private
  584. */
  585. static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
  586. .name = "mpu_bus",
  587. };
  588. /* mpu_private */
  589. /* mpu -> mpu_private */
  590. static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
  591. .master = &omap44xx_mpu_hwmod,
  592. .slave = &omap44xx_mpu_private_hwmod,
  593. .clk = "l3_div_ck",
  594. .user = OCP_USER_MPU | OCP_USER_SDMA,
  595. };
  596. /* mpu_private slave ports */
  597. static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
  598. &omap44xx_mpu__mpu_private,
  599. };
  600. static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  601. .name = "mpu_private",
  602. .class = &omap44xx_mpu_bus_hwmod_class,
  603. .clkdm_name = "mpuss_clkdm",
  604. .slaves = omap44xx_mpu_private_slaves,
  605. .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
  606. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  607. };
  608. /*
  609. * Modules omap_hwmod structures
  610. *
  611. * The following IPs are excluded for the moment because:
  612. * - They do not need an explicit SW control using omap_hwmod API.
  613. * - They still need to be validated with the driver
  614. * properly adapted to omap_hwmod / omap_device
  615. *
  616. * c2c
  617. * c2c_target_fw
  618. * cm_core
  619. * cm_core_aon
  620. * ctrl_module_core
  621. * ctrl_module_pad_core
  622. * ctrl_module_pad_wkup
  623. * ctrl_module_wkup
  624. * debugss
  625. * efuse_ctrl_cust
  626. * efuse_ctrl_std
  627. * elm
  628. * emif1
  629. * emif2
  630. * fdif
  631. * gpmc
  632. * gpu
  633. * hdq1w
  634. * mcasp
  635. * mpu_c0
  636. * mpu_c1
  637. * ocmc_ram
  638. * ocp2scp_usb_phy
  639. * ocp_wp_noc
  640. * prcm_mpu
  641. * prm
  642. * scrm
  643. * sl2if
  644. * slimbus1
  645. * slimbus2
  646. * usb_host_fs
  647. * usb_host_hs
  648. * usb_phy_cm
  649. * usb_tll_hs
  650. * usim
  651. */
  652. /*
  653. * 'aess' class
  654. * audio engine sub system
  655. */
  656. static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
  657. .rev_offs = 0x0000,
  658. .sysc_offs = 0x0010,
  659. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
  660. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  661. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
  662. MSTANDBY_SMART_WKUP),
  663. .sysc_fields = &omap_hwmod_sysc_type2,
  664. };
  665. static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
  666. .name = "aess",
  667. .sysc = &omap44xx_aess_sysc,
  668. };
  669. /* aess */
  670. static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
  671. { .irq = 99 + OMAP44XX_IRQ_GIC_START },
  672. { .irq = -1 }
  673. };
  674. static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
  675. { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
  676. { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
  677. { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
  678. { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
  679. { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
  680. { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
  681. { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
  682. { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
  683. { .dma_req = -1 }
  684. };
  685. /* aess master ports */
  686. static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
  687. &omap44xx_aess__l4_abe,
  688. };
  689. static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
  690. {
  691. .pa_start = 0x401f1000,
  692. .pa_end = 0x401f13ff,
  693. .flags = ADDR_TYPE_RT
  694. },
  695. { }
  696. };
  697. /* l4_abe -> aess */
  698. static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
  699. .master = &omap44xx_l4_abe_hwmod,
  700. .slave = &omap44xx_aess_hwmod,
  701. .clk = "ocp_abe_iclk",
  702. .addr = omap44xx_aess_addrs,
  703. .user = OCP_USER_MPU,
  704. };
  705. static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
  706. {
  707. .pa_start = 0x490f1000,
  708. .pa_end = 0x490f13ff,
  709. .flags = ADDR_TYPE_RT
  710. },
  711. { }
  712. };
  713. /* l4_abe -> aess (dma) */
  714. static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
  715. .master = &omap44xx_l4_abe_hwmod,
  716. .slave = &omap44xx_aess_hwmod,
  717. .clk = "ocp_abe_iclk",
  718. .addr = omap44xx_aess_dma_addrs,
  719. .user = OCP_USER_SDMA,
  720. };
  721. /* aess slave ports */
  722. static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
  723. &omap44xx_l4_abe__aess,
  724. &omap44xx_l4_abe__aess_dma,
  725. };
  726. static struct omap_hwmod omap44xx_aess_hwmod = {
  727. .name = "aess",
  728. .class = &omap44xx_aess_hwmod_class,
  729. .clkdm_name = "abe_clkdm",
  730. .mpu_irqs = omap44xx_aess_irqs,
  731. .sdma_reqs = omap44xx_aess_sdma_reqs,
  732. .main_clk = "aess_fck",
  733. .prcm = {
  734. .omap4 = {
  735. .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
  736. .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
  737. .modulemode = MODULEMODE_SWCTRL,
  738. },
  739. },
  740. .slaves = omap44xx_aess_slaves,
  741. .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
  742. .masters = omap44xx_aess_masters,
  743. .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
  744. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  745. };
  746. /*
  747. * 'bandgap' class
  748. * bangap reference for ldo regulators
  749. */
  750. static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
  751. .name = "bandgap",
  752. };
  753. /* bandgap */
  754. static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
  755. { .role = "fclk", .clk = "bandgap_fclk" },
  756. };
  757. static struct omap_hwmod omap44xx_bandgap_hwmod = {
  758. .name = "bandgap",
  759. .class = &omap44xx_bandgap_hwmod_class,
  760. .clkdm_name = "l4_wkup_clkdm",
  761. .prcm = {
  762. .omap4 = {
  763. .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
  764. },
  765. },
  766. .opt_clks = bandgap_opt_clks,
  767. .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
  768. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  769. };
  770. /*
  771. * 'counter' class
  772. * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
  773. */
  774. static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
  775. .rev_offs = 0x0000,
  776. .sysc_offs = 0x0004,
  777. .sysc_flags = SYSC_HAS_SIDLEMODE,
  778. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  779. SIDLE_SMART_WKUP),
  780. .sysc_fields = &omap_hwmod_sysc_type1,
  781. };
  782. static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
  783. .name = "counter",
  784. .sysc = &omap44xx_counter_sysc,
  785. };
  786. /* counter_32k */
  787. static struct omap_hwmod omap44xx_counter_32k_hwmod;
  788. static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
  789. {
  790. .pa_start = 0x4a304000,
  791. .pa_end = 0x4a30401f,
  792. .flags = ADDR_TYPE_RT
  793. },
  794. { }
  795. };
  796. /* l4_wkup -> counter_32k */
  797. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
  798. .master = &omap44xx_l4_wkup_hwmod,
  799. .slave = &omap44xx_counter_32k_hwmod,
  800. .clk = "l4_wkup_clk_mux_ck",
  801. .addr = omap44xx_counter_32k_addrs,
  802. .user = OCP_USER_MPU | OCP_USER_SDMA,
  803. };
  804. /* counter_32k slave ports */
  805. static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
  806. &omap44xx_l4_wkup__counter_32k,
  807. };
  808. static struct omap_hwmod omap44xx_counter_32k_hwmod = {
  809. .name = "counter_32k",
  810. .class = &omap44xx_counter_hwmod_class,
  811. .clkdm_name = "l4_wkup_clkdm",
  812. .flags = HWMOD_SWSUP_SIDLE,
  813. .main_clk = "sys_32k_ck",
  814. .prcm = {
  815. .omap4 = {
  816. .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
  817. .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
  818. },
  819. },
  820. .slaves = omap44xx_counter_32k_slaves,
  821. .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
  822. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  823. };
  824. /*
  825. * 'dma' class
  826. * dma controller for data exchange between memory to memory (i.e. internal or
  827. * external memory) and gp peripherals to memory or memory to gp peripherals
  828. */
  829. static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
  830. .rev_offs = 0x0000,
  831. .sysc_offs = 0x002c,
  832. .syss_offs = 0x0028,
  833. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  834. SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
  835. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  836. SYSS_HAS_RESET_STATUS),
  837. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  838. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  839. .sysc_fields = &omap_hwmod_sysc_type1,
  840. };
  841. static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
  842. .name = "dma",
  843. .sysc = &omap44xx_dma_sysc,
  844. };
  845. /* dma dev_attr */
  846. static struct omap_dma_dev_attr dma_dev_attr = {
  847. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  848. IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
  849. .lch_count = 32,
  850. };
  851. /* dma_system */
  852. static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
  853. { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
  854. { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
  855. { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
  856. { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
  857. { .irq = -1 }
  858. };
  859. /* dma_system master ports */
  860. static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
  861. &omap44xx_dma_system__l3_main_2,
  862. };
  863. static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
  864. {
  865. .pa_start = 0x4a056000,
  866. .pa_end = 0x4a056fff,
  867. .flags = ADDR_TYPE_RT
  868. },
  869. { }
  870. };
  871. /* l4_cfg -> dma_system */
  872. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
  873. .master = &omap44xx_l4_cfg_hwmod,
  874. .slave = &omap44xx_dma_system_hwmod,
  875. .clk = "l4_div_ck",
  876. .addr = omap44xx_dma_system_addrs,
  877. .user = OCP_USER_MPU | OCP_USER_SDMA,
  878. };
  879. /* dma_system slave ports */
  880. static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
  881. &omap44xx_l4_cfg__dma_system,
  882. };
  883. static struct omap_hwmod omap44xx_dma_system_hwmod = {
  884. .name = "dma_system",
  885. .class = &omap44xx_dma_hwmod_class,
  886. .clkdm_name = "l3_dma_clkdm",
  887. .mpu_irqs = omap44xx_dma_system_irqs,
  888. .main_clk = "l3_div_ck",
  889. .prcm = {
  890. .omap4 = {
  891. .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
  892. .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
  893. },
  894. },
  895. .dev_attr = &dma_dev_attr,
  896. .slaves = omap44xx_dma_system_slaves,
  897. .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
  898. .masters = omap44xx_dma_system_masters,
  899. .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
  900. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  901. };
  902. /*
  903. * 'dmic' class
  904. * digital microphone controller
  905. */
  906. static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
  907. .rev_offs = 0x0000,
  908. .sysc_offs = 0x0010,
  909. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
  910. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  911. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  912. SIDLE_SMART_WKUP),
  913. .sysc_fields = &omap_hwmod_sysc_type2,
  914. };
  915. static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
  916. .name = "dmic",
  917. .sysc = &omap44xx_dmic_sysc,
  918. };
  919. /* dmic */
  920. static struct omap_hwmod omap44xx_dmic_hwmod;
  921. static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
  922. { .irq = 114 + OMAP44XX_IRQ_GIC_START },
  923. { .irq = -1 }
  924. };
  925. static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
  926. { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
  927. { .dma_req = -1 }
  928. };
  929. static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
  930. {
  931. .pa_start = 0x4012e000,
  932. .pa_end = 0x4012e07f,
  933. .flags = ADDR_TYPE_RT
  934. },
  935. { }
  936. };
  937. /* l4_abe -> dmic */
  938. static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
  939. .master = &omap44xx_l4_abe_hwmod,
  940. .slave = &omap44xx_dmic_hwmod,
  941. .clk = "ocp_abe_iclk",
  942. .addr = omap44xx_dmic_addrs,
  943. .user = OCP_USER_MPU,
  944. };
  945. static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
  946. {
  947. .pa_start = 0x4902e000,
  948. .pa_end = 0x4902e07f,
  949. .flags = ADDR_TYPE_RT
  950. },
  951. { }
  952. };
  953. /* l4_abe -> dmic (dma) */
  954. static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
  955. .master = &omap44xx_l4_abe_hwmod,
  956. .slave = &omap44xx_dmic_hwmod,
  957. .clk = "ocp_abe_iclk",
  958. .addr = omap44xx_dmic_dma_addrs,
  959. .user = OCP_USER_SDMA,
  960. };
  961. /* dmic slave ports */
  962. static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
  963. &omap44xx_l4_abe__dmic,
  964. &omap44xx_l4_abe__dmic_dma,
  965. };
  966. static struct omap_hwmod omap44xx_dmic_hwmod = {
  967. .name = "dmic",
  968. .class = &omap44xx_dmic_hwmod_class,
  969. .clkdm_name = "abe_clkdm",
  970. .mpu_irqs = omap44xx_dmic_irqs,
  971. .sdma_reqs = omap44xx_dmic_sdma_reqs,
  972. .main_clk = "dmic_fck",
  973. .prcm = {
  974. .omap4 = {
  975. .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
  976. .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
  977. .modulemode = MODULEMODE_SWCTRL,
  978. },
  979. },
  980. .slaves = omap44xx_dmic_slaves,
  981. .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
  982. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  983. };
  984. /*
  985. * 'dsp' class
  986. * dsp sub-system
  987. */
  988. static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
  989. .name = "dsp",
  990. };
  991. /* dsp */
  992. static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
  993. { .irq = 28 + OMAP44XX_IRQ_GIC_START },
  994. { .irq = -1 }
  995. };
  996. static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
  997. { .name = "mmu_cache", .rst_shift = 1 },
  998. };
  999. static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
  1000. { .name = "dsp", .rst_shift = 0 },
  1001. };
  1002. /* dsp -> iva */
  1003. static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
  1004. .master = &omap44xx_dsp_hwmod,
  1005. .slave = &omap44xx_iva_hwmod,
  1006. .clk = "dpll_iva_m5x2_ck",
  1007. };
  1008. /* dsp master ports */
  1009. static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
  1010. &omap44xx_dsp__l3_main_1,
  1011. &omap44xx_dsp__l4_abe,
  1012. &omap44xx_dsp__iva,
  1013. };
  1014. /* l4_cfg -> dsp */
  1015. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
  1016. .master = &omap44xx_l4_cfg_hwmod,
  1017. .slave = &omap44xx_dsp_hwmod,
  1018. .clk = "l4_div_ck",
  1019. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1020. };
  1021. /* dsp slave ports */
  1022. static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
  1023. &omap44xx_l4_cfg__dsp,
  1024. };
  1025. /* Pseudo hwmod for reset control purpose only */
  1026. static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
  1027. .name = "dsp_c0",
  1028. .class = &omap44xx_dsp_hwmod_class,
  1029. .clkdm_name = "tesla_clkdm",
  1030. .flags = HWMOD_INIT_NO_RESET,
  1031. .rst_lines = omap44xx_dsp_c0_resets,
  1032. .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
  1033. .prcm = {
  1034. .omap4 = {
  1035. .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
  1036. },
  1037. },
  1038. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1039. };
  1040. static struct omap_hwmod omap44xx_dsp_hwmod = {
  1041. .name = "dsp",
  1042. .class = &omap44xx_dsp_hwmod_class,
  1043. .clkdm_name = "tesla_clkdm",
  1044. .mpu_irqs = omap44xx_dsp_irqs,
  1045. .rst_lines = omap44xx_dsp_resets,
  1046. .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
  1047. .main_clk = "dsp_fck",
  1048. .prcm = {
  1049. .omap4 = {
  1050. .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
  1051. .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
  1052. .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
  1053. .modulemode = MODULEMODE_HWCTRL,
  1054. },
  1055. },
  1056. .slaves = omap44xx_dsp_slaves,
  1057. .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
  1058. .masters = omap44xx_dsp_masters,
  1059. .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
  1060. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1061. };
  1062. /*
  1063. * 'dss' class
  1064. * display sub-system
  1065. */
  1066. static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
  1067. .rev_offs = 0x0000,
  1068. .syss_offs = 0x0014,
  1069. .sysc_flags = SYSS_HAS_RESET_STATUS,
  1070. };
  1071. static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
  1072. .name = "dss",
  1073. .sysc = &omap44xx_dss_sysc,
  1074. };
  1075. /* dss */
  1076. /* dss master ports */
  1077. static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
  1078. &omap44xx_dss__l3_main_1,
  1079. };
  1080. static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
  1081. {
  1082. .pa_start = 0x58000000,
  1083. .pa_end = 0x5800007f,
  1084. .flags = ADDR_TYPE_RT
  1085. },
  1086. { }
  1087. };
  1088. /* l3_main_2 -> dss */
  1089. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
  1090. .master = &omap44xx_l3_main_2_hwmod,
  1091. .slave = &omap44xx_dss_hwmod,
  1092. .clk = "dss_fck",
  1093. .addr = omap44xx_dss_dma_addrs,
  1094. .user = OCP_USER_SDMA,
  1095. };
  1096. static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
  1097. {
  1098. .pa_start = 0x48040000,
  1099. .pa_end = 0x4804007f,
  1100. .flags = ADDR_TYPE_RT
  1101. },
  1102. { }
  1103. };
  1104. /* l4_per -> dss */
  1105. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
  1106. .master = &omap44xx_l4_per_hwmod,
  1107. .slave = &omap44xx_dss_hwmod,
  1108. .clk = "l4_div_ck",
  1109. .addr = omap44xx_dss_addrs,
  1110. .user = OCP_USER_MPU,
  1111. };
  1112. /* dss slave ports */
  1113. static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
  1114. &omap44xx_l3_main_2__dss,
  1115. &omap44xx_l4_per__dss,
  1116. };
  1117. static struct omap_hwmod_opt_clk dss_opt_clks[] = {
  1118. { .role = "sys_clk", .clk = "dss_sys_clk" },
  1119. { .role = "tv_clk", .clk = "dss_tv_clk" },
  1120. { .role = "dss_clk", .clk = "dss_dss_clk" },
  1121. { .role = "video_clk", .clk = "dss_48mhz_clk" },
  1122. };
  1123. static struct omap_hwmod omap44xx_dss_hwmod = {
  1124. .name = "dss_core",
  1125. .class = &omap44xx_dss_hwmod_class,
  1126. .clkdm_name = "l3_dss_clkdm",
  1127. .main_clk = "dss_dss_clk",
  1128. .prcm = {
  1129. .omap4 = {
  1130. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1131. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1132. },
  1133. },
  1134. .opt_clks = dss_opt_clks,
  1135. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  1136. .slaves = omap44xx_dss_slaves,
  1137. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
  1138. .masters = omap44xx_dss_masters,
  1139. .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
  1140. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1141. };
  1142. /*
  1143. * 'dispc' class
  1144. * display controller
  1145. */
  1146. static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
  1147. .rev_offs = 0x0000,
  1148. .sysc_offs = 0x0010,
  1149. .syss_offs = 0x0014,
  1150. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  1151. SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
  1152. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1153. SYSS_HAS_RESET_STATUS),
  1154. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1155. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1156. .sysc_fields = &omap_hwmod_sysc_type1,
  1157. };
  1158. static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
  1159. .name = "dispc",
  1160. .sysc = &omap44xx_dispc_sysc,
  1161. };
  1162. /* dss_dispc */
  1163. static struct omap_hwmod omap44xx_dss_dispc_hwmod;
  1164. static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
  1165. { .irq = 25 + OMAP44XX_IRQ_GIC_START },
  1166. { .irq = -1 }
  1167. };
  1168. static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
  1169. { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
  1170. { .dma_req = -1 }
  1171. };
  1172. static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
  1173. {
  1174. .pa_start = 0x58001000,
  1175. .pa_end = 0x58001fff,
  1176. .flags = ADDR_TYPE_RT
  1177. },
  1178. { }
  1179. };
  1180. /* l3_main_2 -> dss_dispc */
  1181. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
  1182. .master = &omap44xx_l3_main_2_hwmod,
  1183. .slave = &omap44xx_dss_dispc_hwmod,
  1184. .clk = "dss_fck",
  1185. .addr = omap44xx_dss_dispc_dma_addrs,
  1186. .user = OCP_USER_SDMA,
  1187. };
  1188. static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
  1189. {
  1190. .pa_start = 0x48041000,
  1191. .pa_end = 0x48041fff,
  1192. .flags = ADDR_TYPE_RT
  1193. },
  1194. { }
  1195. };
  1196. /* l4_per -> dss_dispc */
  1197. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
  1198. .master = &omap44xx_l4_per_hwmod,
  1199. .slave = &omap44xx_dss_dispc_hwmod,
  1200. .clk = "l4_div_ck",
  1201. .addr = omap44xx_dss_dispc_addrs,
  1202. .user = OCP_USER_MPU,
  1203. };
  1204. /* dss_dispc slave ports */
  1205. static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
  1206. &omap44xx_l3_main_2__dss_dispc,
  1207. &omap44xx_l4_per__dss_dispc,
  1208. };
  1209. static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
  1210. { .role = "sys_clk", .clk = "dss_sys_clk" },
  1211. { .role = "tv_clk", .clk = "dss_tv_clk" },
  1212. { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  1213. };
  1214. static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
  1215. .name = "dss_dispc",
  1216. .class = &omap44xx_dispc_hwmod_class,
  1217. .clkdm_name = "l3_dss_clkdm",
  1218. .mpu_irqs = omap44xx_dss_dispc_irqs,
  1219. .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
  1220. .main_clk = "dss_dss_clk",
  1221. .prcm = {
  1222. .omap4 = {
  1223. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1224. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1225. },
  1226. },
  1227. .opt_clks = dss_dispc_opt_clks,
  1228. .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
  1229. .slaves = omap44xx_dss_dispc_slaves,
  1230. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
  1231. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1232. };
  1233. /*
  1234. * 'dsi' class
  1235. * display serial interface controller
  1236. */
  1237. static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
  1238. .rev_offs = 0x0000,
  1239. .sysc_offs = 0x0010,
  1240. .syss_offs = 0x0014,
  1241. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  1242. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  1243. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1244. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1245. .sysc_fields = &omap_hwmod_sysc_type1,
  1246. };
  1247. static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
  1248. .name = "dsi",
  1249. .sysc = &omap44xx_dsi_sysc,
  1250. };
  1251. /* dss_dsi1 */
  1252. static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
  1253. static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
  1254. { .irq = 53 + OMAP44XX_IRQ_GIC_START },
  1255. { .irq = -1 }
  1256. };
  1257. static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
  1258. { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
  1259. { .dma_req = -1 }
  1260. };
  1261. static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
  1262. {
  1263. .pa_start = 0x58004000,
  1264. .pa_end = 0x580041ff,
  1265. .flags = ADDR_TYPE_RT
  1266. },
  1267. { }
  1268. };
  1269. /* l3_main_2 -> dss_dsi1 */
  1270. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
  1271. .master = &omap44xx_l3_main_2_hwmod,
  1272. .slave = &omap44xx_dss_dsi1_hwmod,
  1273. .clk = "dss_fck",
  1274. .addr = omap44xx_dss_dsi1_dma_addrs,
  1275. .user = OCP_USER_SDMA,
  1276. };
  1277. static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
  1278. {
  1279. .pa_start = 0x48044000,
  1280. .pa_end = 0x480441ff,
  1281. .flags = ADDR_TYPE_RT
  1282. },
  1283. { }
  1284. };
  1285. /* l4_per -> dss_dsi1 */
  1286. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
  1287. .master = &omap44xx_l4_per_hwmod,
  1288. .slave = &omap44xx_dss_dsi1_hwmod,
  1289. .clk = "l4_div_ck",
  1290. .addr = omap44xx_dss_dsi1_addrs,
  1291. .user = OCP_USER_MPU,
  1292. };
  1293. /* dss_dsi1 slave ports */
  1294. static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
  1295. &omap44xx_l3_main_2__dss_dsi1,
  1296. &omap44xx_l4_per__dss_dsi1,
  1297. };
  1298. static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
  1299. { .role = "sys_clk", .clk = "dss_sys_clk" },
  1300. };
  1301. static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
  1302. .name = "dss_dsi1",
  1303. .class = &omap44xx_dsi_hwmod_class,
  1304. .clkdm_name = "l3_dss_clkdm",
  1305. .mpu_irqs = omap44xx_dss_dsi1_irqs,
  1306. .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
  1307. .main_clk = "dss_dss_clk",
  1308. .prcm = {
  1309. .omap4 = {
  1310. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1311. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1312. },
  1313. },
  1314. .opt_clks = dss_dsi1_opt_clks,
  1315. .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
  1316. .slaves = omap44xx_dss_dsi1_slaves,
  1317. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
  1318. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1319. };
  1320. /* dss_dsi2 */
  1321. static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
  1322. static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
  1323. { .irq = 84 + OMAP44XX_IRQ_GIC_START },
  1324. { .irq = -1 }
  1325. };
  1326. static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
  1327. { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
  1328. { .dma_req = -1 }
  1329. };
  1330. static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
  1331. {
  1332. .pa_start = 0x58005000,
  1333. .pa_end = 0x580051ff,
  1334. .flags = ADDR_TYPE_RT
  1335. },
  1336. { }
  1337. };
  1338. /* l3_main_2 -> dss_dsi2 */
  1339. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
  1340. .master = &omap44xx_l3_main_2_hwmod,
  1341. .slave = &omap44xx_dss_dsi2_hwmod,
  1342. .clk = "dss_fck",
  1343. .addr = omap44xx_dss_dsi2_dma_addrs,
  1344. .user = OCP_USER_SDMA,
  1345. };
  1346. static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
  1347. {
  1348. .pa_start = 0x48045000,
  1349. .pa_end = 0x480451ff,
  1350. .flags = ADDR_TYPE_RT
  1351. },
  1352. { }
  1353. };
  1354. /* l4_per -> dss_dsi2 */
  1355. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
  1356. .master = &omap44xx_l4_per_hwmod,
  1357. .slave = &omap44xx_dss_dsi2_hwmod,
  1358. .clk = "l4_div_ck",
  1359. .addr = omap44xx_dss_dsi2_addrs,
  1360. .user = OCP_USER_MPU,
  1361. };
  1362. /* dss_dsi2 slave ports */
  1363. static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
  1364. &omap44xx_l3_main_2__dss_dsi2,
  1365. &omap44xx_l4_per__dss_dsi2,
  1366. };
  1367. static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
  1368. { .role = "sys_clk", .clk = "dss_sys_clk" },
  1369. };
  1370. static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
  1371. .name = "dss_dsi2",
  1372. .class = &omap44xx_dsi_hwmod_class,
  1373. .clkdm_name = "l3_dss_clkdm",
  1374. .mpu_irqs = omap44xx_dss_dsi2_irqs,
  1375. .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
  1376. .main_clk = "dss_dss_clk",
  1377. .prcm = {
  1378. .omap4 = {
  1379. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1380. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1381. },
  1382. },
  1383. .opt_clks = dss_dsi2_opt_clks,
  1384. .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
  1385. .slaves = omap44xx_dss_dsi2_slaves,
  1386. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
  1387. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1388. };
  1389. /*
  1390. * 'hdmi' class
  1391. * hdmi controller
  1392. */
  1393. static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
  1394. .rev_offs = 0x0000,
  1395. .sysc_offs = 0x0010,
  1396. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  1397. SYSC_HAS_SOFTRESET),
  1398. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1399. SIDLE_SMART_WKUP),
  1400. .sysc_fields = &omap_hwmod_sysc_type2,
  1401. };
  1402. static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
  1403. .name = "hdmi",
  1404. .sysc = &omap44xx_hdmi_sysc,
  1405. };
  1406. /* dss_hdmi */
  1407. static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
  1408. static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
  1409. { .irq = 101 + OMAP44XX_IRQ_GIC_START },
  1410. { .irq = -1 }
  1411. };
  1412. static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
  1413. { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
  1414. { .dma_req = -1 }
  1415. };
  1416. static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
  1417. {
  1418. .pa_start = 0x58006000,
  1419. .pa_end = 0x58006fff,
  1420. .flags = ADDR_TYPE_RT
  1421. },
  1422. { }
  1423. };
  1424. /* l3_main_2 -> dss_hdmi */
  1425. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
  1426. .master = &omap44xx_l3_main_2_hwmod,
  1427. .slave = &omap44xx_dss_hdmi_hwmod,
  1428. .clk = "dss_fck",
  1429. .addr = omap44xx_dss_hdmi_dma_addrs,
  1430. .user = OCP_USER_SDMA,
  1431. };
  1432. static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
  1433. {
  1434. .pa_start = 0x48046000,
  1435. .pa_end = 0x48046fff,
  1436. .flags = ADDR_TYPE_RT
  1437. },
  1438. { }
  1439. };
  1440. /* l4_per -> dss_hdmi */
  1441. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
  1442. .master = &omap44xx_l4_per_hwmod,
  1443. .slave = &omap44xx_dss_hdmi_hwmod,
  1444. .clk = "l4_div_ck",
  1445. .addr = omap44xx_dss_hdmi_addrs,
  1446. .user = OCP_USER_MPU,
  1447. };
  1448. /* dss_hdmi slave ports */
  1449. static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
  1450. &omap44xx_l3_main_2__dss_hdmi,
  1451. &omap44xx_l4_per__dss_hdmi,
  1452. };
  1453. static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  1454. { .role = "sys_clk", .clk = "dss_sys_clk" },
  1455. };
  1456. static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
  1457. .name = "dss_hdmi",
  1458. .class = &omap44xx_hdmi_hwmod_class,
  1459. .clkdm_name = "l3_dss_clkdm",
  1460. .mpu_irqs = omap44xx_dss_hdmi_irqs,
  1461. .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
  1462. .main_clk = "dss_dss_clk",
  1463. .prcm = {
  1464. .omap4 = {
  1465. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1466. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1467. },
  1468. },
  1469. .opt_clks = dss_hdmi_opt_clks,
  1470. .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
  1471. .slaves = omap44xx_dss_hdmi_slaves,
  1472. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
  1473. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1474. };
  1475. /*
  1476. * 'rfbi' class
  1477. * remote frame buffer interface
  1478. */
  1479. static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
  1480. .rev_offs = 0x0000,
  1481. .sysc_offs = 0x0010,
  1482. .syss_offs = 0x0014,
  1483. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  1484. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1485. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1486. .sysc_fields = &omap_hwmod_sysc_type1,
  1487. };
  1488. static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
  1489. .name = "rfbi",
  1490. .sysc = &omap44xx_rfbi_sysc,
  1491. };
  1492. /* dss_rfbi */
  1493. static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
  1494. static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
  1495. { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
  1496. { .dma_req = -1 }
  1497. };
  1498. static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
  1499. {
  1500. .pa_start = 0x58002000,
  1501. .pa_end = 0x580020ff,
  1502. .flags = ADDR_TYPE_RT
  1503. },
  1504. { }
  1505. };
  1506. /* l3_main_2 -> dss_rfbi */
  1507. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
  1508. .master = &omap44xx_l3_main_2_hwmod,
  1509. .slave = &omap44xx_dss_rfbi_hwmod,
  1510. .clk = "dss_fck",
  1511. .addr = omap44xx_dss_rfbi_dma_addrs,
  1512. .user = OCP_USER_SDMA,
  1513. };
  1514. static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
  1515. {
  1516. .pa_start = 0x48042000,
  1517. .pa_end = 0x480420ff,
  1518. .flags = ADDR_TYPE_RT
  1519. },
  1520. { }
  1521. };
  1522. /* l4_per -> dss_rfbi */
  1523. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
  1524. .master = &omap44xx_l4_per_hwmod,
  1525. .slave = &omap44xx_dss_rfbi_hwmod,
  1526. .clk = "l4_div_ck",
  1527. .addr = omap44xx_dss_rfbi_addrs,
  1528. .user = OCP_USER_MPU,
  1529. };
  1530. /* dss_rfbi slave ports */
  1531. static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
  1532. &omap44xx_l3_main_2__dss_rfbi,
  1533. &omap44xx_l4_per__dss_rfbi,
  1534. };
  1535. static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
  1536. { .role = "ick", .clk = "dss_fck" },
  1537. };
  1538. static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
  1539. .name = "dss_rfbi",
  1540. .class = &omap44xx_rfbi_hwmod_class,
  1541. .clkdm_name = "l3_dss_clkdm",
  1542. .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
  1543. .main_clk = "dss_dss_clk",
  1544. .prcm = {
  1545. .omap4 = {
  1546. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1547. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1548. },
  1549. },
  1550. .opt_clks = dss_rfbi_opt_clks,
  1551. .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
  1552. .slaves = omap44xx_dss_rfbi_slaves,
  1553. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
  1554. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1555. };
  1556. /*
  1557. * 'venc' class
  1558. * video encoder
  1559. */
  1560. static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
  1561. .name = "venc",
  1562. };
  1563. /* dss_venc */
  1564. static struct omap_hwmod omap44xx_dss_venc_hwmod;
  1565. static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
  1566. {
  1567. .pa_start = 0x58003000,
  1568. .pa_end = 0x580030ff,
  1569. .flags = ADDR_TYPE_RT
  1570. },
  1571. { }
  1572. };
  1573. /* l3_main_2 -> dss_venc */
  1574. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
  1575. .master = &omap44xx_l3_main_2_hwmod,
  1576. .slave = &omap44xx_dss_venc_hwmod,
  1577. .clk = "dss_fck",
  1578. .addr = omap44xx_dss_venc_dma_addrs,
  1579. .user = OCP_USER_SDMA,
  1580. };
  1581. static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
  1582. {
  1583. .pa_start = 0x48043000,
  1584. .pa_end = 0x480430ff,
  1585. .flags = ADDR_TYPE_RT
  1586. },
  1587. { }
  1588. };
  1589. /* l4_per -> dss_venc */
  1590. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
  1591. .master = &omap44xx_l4_per_hwmod,
  1592. .slave = &omap44xx_dss_venc_hwmod,
  1593. .clk = "l4_div_ck",
  1594. .addr = omap44xx_dss_venc_addrs,
  1595. .user = OCP_USER_MPU,
  1596. };
  1597. /* dss_venc slave ports */
  1598. static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
  1599. &omap44xx_l3_main_2__dss_venc,
  1600. &omap44xx_l4_per__dss_venc,
  1601. };
  1602. static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  1603. .name = "dss_venc",
  1604. .class = &omap44xx_venc_hwmod_class,
  1605. .clkdm_name = "l3_dss_clkdm",
  1606. .main_clk = "dss_dss_clk",
  1607. .prcm = {
  1608. .omap4 = {
  1609. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  1610. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  1611. },
  1612. },
  1613. .slaves = omap44xx_dss_venc_slaves,
  1614. .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
  1615. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1616. };
  1617. /*
  1618. * 'gpio' class
  1619. * general purpose io module
  1620. */
  1621. static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
  1622. .rev_offs = 0x0000,
  1623. .sysc_offs = 0x0010,
  1624. .syss_offs = 0x0114,
  1625. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  1626. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1627. SYSS_HAS_RESET_STATUS),
  1628. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1629. SIDLE_SMART_WKUP),
  1630. .sysc_fields = &omap_hwmod_sysc_type1,
  1631. };
  1632. static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
  1633. .name = "gpio",
  1634. .sysc = &omap44xx_gpio_sysc,
  1635. .rev = 2,
  1636. };
  1637. /* gpio dev_attr */
  1638. static struct omap_gpio_dev_attr gpio_dev_attr = {
  1639. .bank_width = 32,
  1640. .dbck_flag = true,
  1641. };
  1642. /* gpio1 */
  1643. static struct omap_hwmod omap44xx_gpio1_hwmod;
  1644. static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
  1645. { .irq = 29 + OMAP44XX_IRQ_GIC_START },
  1646. { .irq = -1 }
  1647. };
  1648. static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
  1649. {
  1650. .pa_start = 0x4a310000,
  1651. .pa_end = 0x4a3101ff,
  1652. .flags = ADDR_TYPE_RT
  1653. },
  1654. { }
  1655. };
  1656. /* l4_wkup -> gpio1 */
  1657. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
  1658. .master = &omap44xx_l4_wkup_hwmod,
  1659. .slave = &omap44xx_gpio1_hwmod,
  1660. .clk = "l4_wkup_clk_mux_ck",
  1661. .addr = omap44xx_gpio1_addrs,
  1662. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1663. };
  1664. /* gpio1 slave ports */
  1665. static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
  1666. &omap44xx_l4_wkup__gpio1,
  1667. };
  1668. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  1669. { .role = "dbclk", .clk = "gpio1_dbclk" },
  1670. };
  1671. static struct omap_hwmod omap44xx_gpio1_hwmod = {
  1672. .name = "gpio1",
  1673. .class = &omap44xx_gpio_hwmod_class,
  1674. .clkdm_name = "l4_wkup_clkdm",
  1675. .mpu_irqs = omap44xx_gpio1_irqs,
  1676. .main_clk = "gpio1_ick",
  1677. .prcm = {
  1678. .omap4 = {
  1679. .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
  1680. .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
  1681. .modulemode = MODULEMODE_HWCTRL,
  1682. },
  1683. },
  1684. .opt_clks = gpio1_opt_clks,
  1685. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  1686. .dev_attr = &gpio_dev_attr,
  1687. .slaves = omap44xx_gpio1_slaves,
  1688. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
  1689. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1690. };
  1691. /* gpio2 */
  1692. static struct omap_hwmod omap44xx_gpio2_hwmod;
  1693. static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
  1694. { .irq = 30 + OMAP44XX_IRQ_GIC_START },
  1695. { .irq = -1 }
  1696. };
  1697. static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
  1698. {
  1699. .pa_start = 0x48055000,
  1700. .pa_end = 0x480551ff,
  1701. .flags = ADDR_TYPE_RT
  1702. },
  1703. { }
  1704. };
  1705. /* l4_per -> gpio2 */
  1706. stati