/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
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1/* 2 * Hardware modules present on the OMAP44xx chips 3 * 4 * Copyright (C) 2009-2011 Texas Instruments, Inc. 5 * Copyright (C) 2009-2010 Nokia Corporation 6 * 7 * Paul Walmsley 8 * Benoit Cousson 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21#include <linux/io.h> 22 23#include <plat/omap_hwmod.h> 24#include <plat/cpu.h> 25#include <plat/i2c.h> 26#include <plat/gpio.h> 27#include <plat/dma.h> 28#include <plat/mcspi.h> 29#include <plat/mcbsp.h> 30#include <plat/mmc.h> 31#include <plat/i2c.h> 32 33#include "omap_hwmod_common_data.h" 34 35#include "cm1_44xx.h" 36#include "cm2_44xx.h" 37#include "prm44xx.h" 38#include "prm-regbits-44xx.h" 39#include "wd_timer.h" 40 41/* Base offset for all OMAP4 interrupts external to MPUSS */ 42#define OMAP44XX_IRQ_GIC_START 32 43 44/* Base offset for all OMAP4 dma requests */ 45#define OMAP44XX_DMA_REQ_START 1 46 47/* Backward references (IPs with Bus Master capability) */ 48static struct omap_hwmod omap44xx_aess_hwmod; 49static struct omap_hwmod omap44xx_dma_system_hwmod; 50static struct omap_hwmod omap44xx_dmm_hwmod; 51static struct omap_hwmod omap44xx_dsp_hwmod; 52static struct omap_hwmod omap44xx_dss_hwmod; 53static struct omap_hwmod omap44xx_emif_fw_hwmod; 54static struct omap_hwmod omap44xx_hsi_hwmod; 55static struct omap_hwmod omap44xx_ipu_hwmod; 56static struct omap_hwmod omap44xx_iss_hwmod; 57static struct omap_hwmod omap44xx_iva_hwmod; 58static struct omap_hwmod omap44xx_l3_instr_hwmod; 59static struct omap_hwmod omap44xx_l3_main_1_hwmod; 60static struct omap_hwmod omap44xx_l3_main_2_hwmod; 61static struct omap_hwmod omap44xx_l3_main_3_hwmod; 62static struct omap_hwmod omap44xx_l4_abe_hwmod; 63static struct omap_hwmod omap44xx_l4_cfg_hwmod; 64static struct omap_hwmod omap44xx_l4_per_hwmod; 65static struct omap_hwmod omap44xx_l4_wkup_hwmod; 66static struct omap_hwmod omap44xx_mmc1_hwmod; 67static struct omap_hwmod omap44xx_mmc2_hwmod; 68static struct omap_hwmod omap44xx_mpu_hwmod; 69static struct omap_hwmod omap44xx_mpu_private_hwmod; 70static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; 71 72/* 73 * Interconnects omap_hwmod structures 74 * hwmods that compose the global OMAP interconnect 75 */ 76 77/* 78 * 'dmm' class 79 * instance(s): dmm 80 */ 81static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { 82 .name = "dmm", 83}; 84 85/* dmm */ 86static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { 87 { .irq = 113 + OMAP44XX_IRQ_GIC_START }, 88 { .irq = -1 } 89}; 90 91/* l3_main_1 -> dmm */ 92static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 93 .master = &omap44xx_l3_main_1_hwmod, 94 .slave = &omap44xx_dmm_hwmod, 95 .clk = "l3_div_ck", 96 .user = OCP_USER_SDMA, 97}; 98 99static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { 100 { 101 .pa_start = 0x4e000000, 102 .pa_end = 0x4e0007ff, 103 .flags = ADDR_TYPE_RT 104 }, 105 { } 106}; 107 108/* mpu -> dmm */ 109static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { 110 .master = &omap44xx_mpu_hwmod, 111 .slave = &omap44xx_dmm_hwmod, 112 .clk = "l3_div_ck", 113 .addr = omap44xx_dmm_addrs, 114 .user = OCP_USER_MPU, 115}; 116 117/* dmm slave ports */ 118static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { 119 &omap44xx_l3_main_1__dmm, 120 &omap44xx_mpu__dmm, 121}; 122 123static struct omap_hwmod omap44xx_dmm_hwmod = { 124 .name = "dmm", 125 .class = &omap44xx_dmm_hwmod_class, 126 .clkdm_name = "l3_emif_clkdm", 127 .prcm = { 128 .omap4 = { 129 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, 130 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, 131 }, 132 }, 133 .slaves = omap44xx_dmm_slaves, 134 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 135 .mpu_irqs = omap44xx_dmm_irqs, 136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 137}; 138 139/* 140 * 'emif_fw' class 141 * instance(s): emif_fw 142 */ 143static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { 144 .name = "emif_fw", 145}; 146 147/* emif_fw */ 148/* dmm -> emif_fw */ 149static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 150 .master = &omap44xx_dmm_hwmod, 151 .slave = &omap44xx_emif_fw_hwmod, 152 .clk = "l3_div_ck", 153 .user = OCP_USER_MPU | OCP_USER_SDMA, 154}; 155 156static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { 157 { 158 .pa_start = 0x4a20c000, 159 .pa_end = 0x4a20c0ff, 160 .flags = ADDR_TYPE_RT 161 }, 162 { } 163}; 164 165/* l4_cfg -> emif_fw */ 166static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { 167 .master = &omap44xx_l4_cfg_hwmod, 168 .slave = &omap44xx_emif_fw_hwmod, 169 .clk = "l4_div_ck", 170 .addr = omap44xx_emif_fw_addrs, 171 .user = OCP_USER_MPU, 172}; 173 174/* emif_fw slave ports */ 175static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { 176 &omap44xx_dmm__emif_fw, 177 &omap44xx_l4_cfg__emif_fw, 178}; 179 180static struct omap_hwmod omap44xx_emif_fw_hwmod = { 181 .name = "emif_fw", 182 .class = &omap44xx_emif_fw_hwmod_class, 183 .clkdm_name = "l3_emif_clkdm", 184 .prcm = { 185 .omap4 = { 186 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, 187 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, 188 }, 189 }, 190 .slaves = omap44xx_emif_fw_slaves, 191 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), 192 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 193}; 194 195/* 196 * 'l3' class 197 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 198 */ 199static struct omap_hwmod_class omap44xx_l3_hwmod_class = { 200 .name = "l3", 201}; 202 203/* l3_instr */ 204/* iva -> l3_instr */ 205static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { 206 .master = &omap44xx_iva_hwmod, 207 .slave = &omap44xx_l3_instr_hwmod, 208 .clk = "l3_div_ck", 209 .user = OCP_USER_MPU | OCP_USER_SDMA, 210}; 211 212/* l3_main_3 -> l3_instr */ 213static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { 214 .master = &omap44xx_l3_main_3_hwmod, 215 .slave = &omap44xx_l3_instr_hwmod, 216 .clk = "l3_div_ck", 217 .user = OCP_USER_MPU | OCP_USER_SDMA, 218}; 219 220/* l3_instr slave ports */ 221static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { 222 &omap44xx_iva__l3_instr, 223 &omap44xx_l3_main_3__l3_instr, 224}; 225 226static struct omap_hwmod omap44xx_l3_instr_hwmod = { 227 .name = "l3_instr", 228 .class = &omap44xx_l3_hwmod_class, 229 .clkdm_name = "l3_instr_clkdm", 230 .prcm = { 231 .omap4 = { 232 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, 233 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, 234 .modulemode = MODULEMODE_HWCTRL, 235 }, 236 }, 237 .slaves = omap44xx_l3_instr_slaves, 238 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), 239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 240}; 241 242/* l3_main_1 */ 243static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { 244 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, 245 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, 246 { .irq = -1 } 247}; 248 249/* dsp -> l3_main_1 */ 250static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { 251 .master = &omap44xx_dsp_hwmod, 252 .slave = &omap44xx_l3_main_1_hwmod, 253 .clk = "l3_div_ck", 254 .user = OCP_USER_MPU | OCP_USER_SDMA, 255}; 256 257/* dss -> l3_main_1 */ 258static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { 259 .master = &omap44xx_dss_hwmod, 260 .slave = &omap44xx_l3_main_1_hwmod, 261 .clk = "l3_div_ck", 262 .user = OCP_USER_MPU | OCP_USER_SDMA, 263}; 264 265/* l3_main_2 -> l3_main_1 */ 266static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 267 .master = &omap44xx_l3_main_2_hwmod, 268 .slave = &omap44xx_l3_main_1_hwmod, 269 .clk = "l3_div_ck", 270 .user = OCP_USER_MPU | OCP_USER_SDMA, 271}; 272 273/* l4_cfg -> l3_main_1 */ 274static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { 275 .master = &omap44xx_l4_cfg_hwmod, 276 .slave = &omap44xx_l3_main_1_hwmod, 277 .clk = "l4_div_ck", 278 .user = OCP_USER_MPU | OCP_USER_SDMA, 279}; 280 281/* mmc1 -> l3_main_1 */ 282static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { 283 .master = &omap44xx_mmc1_hwmod, 284 .slave = &omap44xx_l3_main_1_hwmod, 285 .clk = "l3_div_ck", 286 .user = OCP_USER_MPU | OCP_USER_SDMA, 287}; 288 289/* mmc2 -> l3_main_1 */ 290static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { 291 .master = &omap44xx_mmc2_hwmod, 292 .slave = &omap44xx_l3_main_1_hwmod, 293 .clk = "l3_div_ck", 294 .user = OCP_USER_MPU | OCP_USER_SDMA, 295}; 296 297static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { 298 { 299 .pa_start = 0x44000000, 300 .pa_end = 0x44000fff, 301 .flags = ADDR_TYPE_RT 302 }, 303 { } 304}; 305 306/* mpu -> l3_main_1 */ 307static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 308 .master = &omap44xx_mpu_hwmod, 309 .slave = &omap44xx_l3_main_1_hwmod, 310 .clk = "l3_div_ck", 311 .addr = omap44xx_l3_main_1_addrs, 312 .user = OCP_USER_MPU, 313}; 314 315/* l3_main_1 slave ports */ 316static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { 317 &omap44xx_dsp__l3_main_1, 318 &omap44xx_dss__l3_main_1, 319 &omap44xx_l3_main_2__l3_main_1, 320 &omap44xx_l4_cfg__l3_main_1, 321 &omap44xx_mmc1__l3_main_1, 322 &omap44xx_mmc2__l3_main_1, 323 &omap44xx_mpu__l3_main_1, 324}; 325 326static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 327 .name = "l3_main_1", 328 .class = &omap44xx_l3_hwmod_class, 329 .clkdm_name = "l3_1_clkdm", 330 .mpu_irqs = omap44xx_l3_main_1_irqs, 331 .prcm = { 332 .omap4 = { 333 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, 334 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, 335 }, 336 }, 337 .slaves = omap44xx_l3_main_1_slaves, 338 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 340}; 341 342/* l3_main_2 */ 343/* dma_system -> l3_main_2 */ 344static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { 345 .master = &omap44xx_dma_system_hwmod, 346 .slave = &omap44xx_l3_main_2_hwmod, 347 .clk = "l3_div_ck", 348 .user = OCP_USER_MPU | OCP_USER_SDMA, 349}; 350 351/* hsi -> l3_main_2 */ 352static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { 353 .master = &omap44xx_hsi_hwmod, 354 .slave = &omap44xx_l3_main_2_hwmod, 355 .clk = "l3_div_ck", 356 .user = OCP_USER_MPU | OCP_USER_SDMA, 357}; 358 359/* ipu -> l3_main_2 */ 360static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { 361 .master = &omap44xx_ipu_hwmod, 362 .slave = &omap44xx_l3_main_2_hwmod, 363 .clk = "l3_div_ck", 364 .user = OCP_USER_MPU | OCP_USER_SDMA, 365}; 366 367/* iss -> l3_main_2 */ 368static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { 369 .master = &omap44xx_iss_hwmod, 370 .slave = &omap44xx_l3_main_2_hwmod, 371 .clk = "l3_div_ck", 372 .user = OCP_USER_MPU | OCP_USER_SDMA, 373}; 374 375/* iva -> l3_main_2 */ 376static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { 377 .master = &omap44xx_iva_hwmod, 378 .slave = &omap44xx_l3_main_2_hwmod, 379 .clk = "l3_div_ck", 380 .user = OCP_USER_MPU | OCP_USER_SDMA, 381}; 382 383static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { 384 { 385 .pa_start = 0x44800000, 386 .pa_end = 0x44801fff, 387 .flags = ADDR_TYPE_RT 388 }, 389 { } 390}; 391 392/* l3_main_1 -> l3_main_2 */ 393static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 394 .master = &omap44xx_l3_main_1_hwmod, 395 .slave = &omap44xx_l3_main_2_hwmod, 396 .clk = "l3_div_ck", 397 .addr = omap44xx_l3_main_2_addrs, 398 .user = OCP_USER_MPU, 399}; 400 401/* l4_cfg -> l3_main_2 */ 402static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { 403 .master = &omap44xx_l4_cfg_hwmod, 404 .slave = &omap44xx_l3_main_2_hwmod, 405 .clk = "l4_div_ck", 406 .user = OCP_USER_MPU | OCP_USER_SDMA, 407}; 408 409/* usb_otg_hs -> l3_main_2 */ 410static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { 411 .master = &omap44xx_usb_otg_hs_hwmod, 412 .slave = &omap44xx_l3_main_2_hwmod, 413 .clk = "l3_div_ck", 414 .user = OCP_USER_MPU | OCP_USER_SDMA, 415}; 416 417/* l3_main_2 slave ports */ 418static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { 419 &omap44xx_dma_system__l3_main_2, 420 &omap44xx_hsi__l3_main_2, 421 &omap44xx_ipu__l3_main_2, 422 &omap44xx_iss__l3_main_2, 423 &omap44xx_iva__l3_main_2, 424 &omap44xx_l3_main_1__l3_main_2, 425 &omap44xx_l4_cfg__l3_main_2, 426 &omap44xx_usb_otg_hs__l3_main_2, 427}; 428 429static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 430 .name = "l3_main_2", 431 .class = &omap44xx_l3_hwmod_class, 432 .clkdm_name = "l3_2_clkdm", 433 .prcm = { 434 .omap4 = { 435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, 436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, 437 }, 438 }, 439 .slaves = omap44xx_l3_main_2_slaves, 440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), 441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 442}; 443 444/* l3_main_3 */ 445static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { 446 { 447 .pa_start = 0x45000000, 448 .pa_end = 0x45000fff, 449 .flags = ADDR_TYPE_RT 450 }, 451 { } 452}; 453 454/* l3_main_1 -> l3_main_3 */ 455static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 456 .master = &omap44xx_l3_main_1_hwmod, 457 .slave = &omap44xx_l3_main_3_hwmod, 458 .clk = "l3_div_ck", 459 .addr = omap44xx_l3_main_3_addrs, 460 .user = OCP_USER_MPU, 461}; 462 463/* l3_main_2 -> l3_main_3 */ 464static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { 465 .master = &omap44xx_l3_main_2_hwmod, 466 .slave = &omap44xx_l3_main_3_hwmod, 467 .clk = "l3_div_ck", 468 .user = OCP_USER_MPU | OCP_USER_SDMA, 469}; 470 471/* l4_cfg -> l3_main_3 */ 472static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { 473 .master = &omap44xx_l4_cfg_hwmod, 474 .slave = &omap44xx_l3_main_3_hwmod, 475 .clk = "l4_div_ck", 476 .user = OCP_USER_MPU | OCP_USER_SDMA, 477}; 478 479/* l3_main_3 slave ports */ 480static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { 481 &omap44xx_l3_main_1__l3_main_3, 482 &omap44xx_l3_main_2__l3_main_3, 483 &omap44xx_l4_cfg__l3_main_3, 484}; 485 486static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 487 .name = "l3_main_3", 488 .class = &omap44xx_l3_hwmod_class, 489 .clkdm_name = "l3_instr_clkdm", 490 .prcm = { 491 .omap4 = { 492 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, 493 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, 494 .modulemode = MODULEMODE_HWCTRL, 495 }, 496 }, 497 .slaves = omap44xx_l3_main_3_slaves, 498 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), 499 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 500}; 501 502/* 503 * 'l4' class 504 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup 505 */ 506static struct omap_hwmod_class omap44xx_l4_hwmod_class = { 507 .name = "l4", 508}; 509 510/* l4_abe */ 511/* aess -> l4_abe */ 512static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { 513 .master = &omap44xx_aess_hwmod, 514 .slave = &omap44xx_l4_abe_hwmod, 515 .clk = "ocp_abe_iclk", 516 .user = OCP_USER_MPU | OCP_USER_SDMA, 517}; 518 519/* dsp -> l4_abe */ 520static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { 521 .master = &omap44xx_dsp_hwmod, 522 .slave = &omap44xx_l4_abe_hwmod, 523 .clk = "ocp_abe_iclk", 524 .user = OCP_USER_MPU | OCP_USER_SDMA, 525}; 526 527/* l3_main_1 -> l4_abe */ 528static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { 529 .master = &omap44xx_l3_main_1_hwmod, 530 .slave = &omap44xx_l4_abe_hwmod, 531 .clk = "l3_div_ck", 532 .user = OCP_USER_MPU | OCP_USER_SDMA, 533}; 534 535/* mpu -> l4_abe */ 536static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { 537 .master = &omap44xx_mpu_hwmod, 538 .slave = &omap44xx_l4_abe_hwmod, 539 .clk = "ocp_abe_iclk", 540 .user = OCP_USER_MPU | OCP_USER_SDMA, 541}; 542 543/* l4_abe slave ports */ 544static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { 545 &omap44xx_aess__l4_abe, 546 &omap44xx_dsp__l4_abe, 547 &omap44xx_l3_main_1__l4_abe, 548 &omap44xx_mpu__l4_abe, 549}; 550 551static struct omap_hwmod omap44xx_l4_abe_hwmod = { 552 .name = "l4_abe", 553 .class = &omap44xx_l4_hwmod_class, 554 .clkdm_name = "abe_clkdm", 555 .prcm = { 556 .omap4 = { 557 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, 558 }, 559 }, 560 .slaves = omap44xx_l4_abe_slaves, 561 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), 562 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 563}; 564 565/* l4_cfg */ 566/* l3_main_1 -> l4_cfg */ 567static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { 568 .master = &omap44xx_l3_main_1_hwmod, 569 .slave = &omap44xx_l4_cfg_hwmod, 570 .clk = "l3_div_ck", 571 .user = OCP_USER_MPU | OCP_USER_SDMA, 572}; 573 574/* l4_cfg slave ports */ 575static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { 576 &omap44xx_l3_main_1__l4_cfg, 577}; 578 579static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 580 .name = "l4_cfg", 581 .class = &omap44xx_l4_hwmod_class, 582 .clkdm_name = "l4_cfg_clkdm", 583 .prcm = { 584 .omap4 = { 585 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, 586 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 587 }, 588 }, 589 .slaves = omap44xx_l4_cfg_slaves, 590 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), 591 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 592}; 593 594/* l4_per */ 595/* l3_main_2 -> l4_per */ 596static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { 597 .master = &omap44xx_l3_main_2_hwmod, 598 .slave = &omap44xx_l4_per_hwmod, 599 .clk = "l3_div_ck", 600 .user = OCP_USER_MPU | OCP_USER_SDMA, 601}; 602 603/* l4_per slave ports */ 604static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { 605 &omap44xx_l3_main_2__l4_per, 606}; 607 608static struct omap_hwmod omap44xx_l4_per_hwmod = { 609 .name = "l4_per", 610 .class = &omap44xx_l4_hwmod_class, 611 .clkdm_name = "l4_per_clkdm", 612 .prcm = { 613 .omap4 = { 614 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, 615 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, 616 }, 617 }, 618 .slaves = omap44xx_l4_per_slaves, 619 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), 620 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 621}; 622 623/* l4_wkup */ 624/* l4_cfg -> l4_wkup */ 625static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { 626 .master = &omap44xx_l4_cfg_hwmod, 627 .slave = &omap44xx_l4_wkup_hwmod, 628 .clk = "l4_div_ck", 629 .user = OCP_USER_MPU | OCP_USER_SDMA, 630}; 631 632/* l4_wkup slave ports */ 633static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { 634 &omap44xx_l4_cfg__l4_wkup, 635}; 636 637static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 638 .name = "l4_wkup", 639 .class = &omap44xx_l4_hwmod_class, 640 .clkdm_name = "l4_wkup_clkdm", 641 .prcm = { 642 .omap4 = { 643 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, 644 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, 645 }, 646 }, 647 .slaves = omap44xx_l4_wkup_slaves, 648 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), 649 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 650}; 651 652/* 653 * 'mpu_bus' class 654 * instance(s): mpu_private 655 */ 656static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { 657 .name = "mpu_bus", 658}; 659 660/* mpu_private */ 661/* mpu -> mpu_private */ 662static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { 663 .master = &omap44xx_mpu_hwmod, 664 .slave = &omap44xx_mpu_private_hwmod, 665 .clk = "l3_div_ck", 666 .user = OCP_USER_MPU | OCP_USER_SDMA, 667}; 668 669/* mpu_private slave ports */ 670static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { 671 &omap44xx_mpu__mpu_private, 672}; 673 674static struct omap_hwmod omap44xx_mpu_private_hwmod = { 675 .name = "mpu_private", 676 .class = &omap44xx_mpu_bus_hwmod_class, 677 .clkdm_name = "mpuss_clkdm", 678 .slaves = omap44xx_mpu_private_slaves, 679 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), 680 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 681}; 682 683/* 684 * Modules omap_hwmod structures 685 * 686 * The following IPs are excluded for the moment because: 687 * - They do not need an explicit SW control using omap_hwmod API. 688 * - They still need to be validated with the driver 689 * properly adapted to omap_hwmod / omap_device 690 * 691 * c2c 692 * c2c_target_fw 693 * cm_core 694 * cm_core_aon 695 * ctrl_module_core 696 * ctrl_module_pad_core 697 * ctrl_module_pad_wkup 698 * ctrl_module_wkup 699 * debugss 700 * efuse_ctrl_cust 701 * efuse_ctrl_std 702 * elm 703 * emif1 704 * emif2 705 * fdif 706 * gpmc 707 * gpu 708 * hdq1w 709 * mcasp 710 * mpu_c0 711 * mpu_c1 712 * ocmc_ram 713 * ocp2scp_usb_phy 714 * ocp_wp_noc 715 * prcm_mpu 716 * prm 717 * scrm 718 * sl2if 719 * slimbus1 720 * slimbus2 721 * usb_host_fs 722 * usb_host_hs 723 * usb_phy_cm 724 * usb_tll_hs 725 * usim 726 */ 727 728/* 729 * 'aess' class 730 * audio engine sub system 731 */ 732 733static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { 734 .rev_offs = 0x0000, 735 .sysc_offs = 0x0010, 736 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 737 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 738 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | 739 MSTANDBY_SMART_WKUP), 740 .sysc_fields = &omap_hwmod_sysc_type2, 741}; 742 743static struct omap_hwmod_class omap44xx_aess_hwmod_class = { 744 .name = "aess", 745 .sysc = &omap44xx_aess_sysc, 746}; 747 748/* aess */ 749static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { 750 { .irq = 99 + OMAP44XX_IRQ_GIC_START }, 751 { .irq = -1 } 752}; 753 754static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { 755 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, 756 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, 757 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, 758 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, 759 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, 760 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, 761 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, 762 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, 763 { .dma_req = -1 } 764}; 765 766/* aess master ports */ 767static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { 768 &omap44xx_aess__l4_abe, 769}; 770 771static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { 772 { 773 .pa_start = 0x401f1000, 774 .pa_end = 0x401f13ff, 775 .flags = ADDR_TYPE_RT 776 }, 777 { } 778}; 779 780/* l4_abe -> aess */ 781static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { 782 .master = &omap44xx_l4_abe_hwmod, 783 .slave = &omap44xx_aess_hwmod, 784 .clk = "ocp_abe_iclk", 785 .addr = omap44xx_aess_addrs, 786 .user = OCP_USER_MPU, 787}; 788 789static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { 790 { 791 .pa_start = 0x490f1000, 792 .pa_end = 0x490f13ff, 793 .flags = ADDR_TYPE_RT 794 }, 795 { } 796}; 797 798/* l4_abe -> aess (dma) */ 799static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { 800 .master = &omap44xx_l4_abe_hwmod, 801 .slave = &omap44xx_aess_hwmod, 802 .clk = "ocp_abe_iclk", 803 .addr = omap44xx_aess_dma_addrs, 804 .user = OCP_USER_SDMA, 805}; 806 807/* aess slave ports */ 808static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { 809 &omap44xx_l4_abe__aess, 810 &omap44xx_l4_abe__aess_dma, 811}; 812 813static struct omap_hwmod omap44xx_aess_hwmod = { 814 .name = "aess", 815 .class = &omap44xx_aess_hwmod_class, 816 .clkdm_name = "abe_clkdm", 817 .mpu_irqs = omap44xx_aess_irqs, 818 .sdma_reqs = omap44xx_aess_sdma_reqs, 819 .main_clk = "aess_fck", 820 .prcm = { 821 .omap4 = { 822 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, 823 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, 824 .modulemode = MODULEMODE_SWCTRL, 825 }, 826 }, 827 .slaves = omap44xx_aess_slaves, 828 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), 829 .masters = omap44xx_aess_masters, 830 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), 831 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 832}; 833 834/* 835 * 'bandgap' class 836 * bangap reference for ldo regulators 837 */ 838 839static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { 840 .name = "bandgap", 841}; 842 843/* bandgap */ 844static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { 845 { .role = "fclk", .clk = "bandgap_fclk" }, 846}; 847 848static struct omap_hwmod omap44xx_bandgap_hwmod = { 849 .name = "bandgap", 850 .class = &omap44xx_bandgap_hwmod_class, 851 .clkdm_name = "l4_wkup_clkdm", 852 .prcm = { 853 .omap4 = { 854 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, 855 }, 856 }, 857 .opt_clks = bandgap_opt_clks, 858 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), 859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 860}; 861 862/* 863 * 'counter' class 864 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 865 */ 866 867static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { 868 .rev_offs = 0x0000, 869 .sysc_offs = 0x0004, 870 .sysc_flags = SYSC_HAS_SIDLEMODE, 871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 872 SIDLE_SMART_WKUP), 873 .sysc_fields = &omap_hwmod_sysc_type1, 874}; 875 876static struct omap_hwmod_class omap44xx_counter_hwmod_class = { 877 .name = "counter", 878 .sysc = &omap44xx_counter_sysc, 879}; 880 881/* counter_32k */ 882static struct omap_hwmod omap44xx_counter_32k_hwmod; 883static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { 884 { 885 .pa_start = 0x4a304000, 886 .pa_end = 0x4a30401f, 887 .flags = ADDR_TYPE_RT 888 }, 889 { } 890}; 891 892/* l4_wkup -> counter_32k */ 893static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { 894 .master = &omap44xx_l4_wkup_hwmod, 895 .slave = &omap44xx_counter_32k_hwmod, 896 .clk = "l4_wkup_clk_mux_ck", 897 .addr = omap44xx_counter_32k_addrs, 898 .user = OCP_USER_MPU | OCP_USER_SDMA, 899}; 900 901/* counter_32k slave ports */ 902static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { 903 &omap44xx_l4_wkup__counter_32k, 904}; 905 906static struct omap_hwmod omap44xx_counter_32k_hwmod = { 907 .name = "counter_32k", 908 .class = &omap44xx_counter_hwmod_class, 909 .clkdm_name = "l4_wkup_clkdm", 910 .flags = HWMOD_SWSUP_SIDLE, 911 .main_clk = "sys_32k_ck", 912 .prcm = { 913 .omap4 = { 914 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, 915 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, 916 }, 917 }, 918 .slaves = omap44xx_counter_32k_slaves, 919 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), 920 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 921}; 922 923/* 924 * 'dma' class 925 * dma controller for data exchange between memory to memory (i.e. internal or 926 * external memory) and gp peripherals to memory or memory to gp peripherals 927 */ 928 929static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { 930 .rev_offs = 0x0000, 931 .sysc_offs = 0x002c, 932 .syss_offs = 0x0028, 933 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 934 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | 935 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 936 SYSS_HAS_RESET_STATUS), 937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 938 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 939 .sysc_fields = &omap_hwmod_sysc_type1, 940}; 941 942static struct omap_hwmod_class omap44xx_dma_hwmod_class = { 943 .name = "dma", 944 .sysc = &omap44xx_dma_sysc, 945}; 946 947/* dma dev_attr */ 948static struct omap_dma_dev_attr dma_dev_attr = { 949 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 950 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 951 .lch_count = 32, 952}; 953 954/* dma_system */ 955static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { 956 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, 957 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, 958 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, 959 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, 960 { .irq = -1 } 961}; 962 963/* dma_system master ports */ 964static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { 965 &omap44xx_dma_system__l3_main_2, 966}; 967 968static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { 969 { 970 .pa_start = 0x4a056000, 971 .pa_end = 0x4a056fff, 972 .flags = ADDR_TYPE_RT 973 }, 974 { } 975}; 976 977/* l4_cfg -> dma_system */ 978static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { 979 .master = &omap44xx_l4_cfg_hwmod, 980 .slave = &omap44xx_dma_system_hwmod, 981 .clk = "l4_div_ck", 982 .addr = omap44xx_dma_system_addrs, 983 .user = OCP_USER_MPU | OCP_USER_SDMA, 984}; 985 986/* dma_system slave ports */ 987static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { 988 &omap44xx_l4_cfg__dma_system, 989}; 990 991static struct omap_hwmod omap44xx_dma_system_hwmod = { 992 .name = "dma_system", 993 .class = &omap44xx_dma_hwmod_class, 994 .clkdm_name = "l3_dma_clkdm", 995 .mpu_irqs = omap44xx_dma_system_irqs, 996 .main_clk = "l3_div_ck", 997 .prcm = { 998 .omap4 = { 999 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, 1000 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, 1001 }, 1002 }, 1003 .dev_attr = &dma_dev_attr, 1004 .slaves = omap44xx_dma_system_slaves, 1005 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), 1006 .masters = omap44xx_dma_system_masters, 1007 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), 1008 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1009}; 1010 1011/* 1012 * 'dmic' class 1013 * digital microphone controller 1014 */ 1015 1016static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { 1017 .rev_offs = 0x0000, 1018 .sysc_offs = 0x0010, 1019 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | 1020 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1021 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1022 SIDLE_SMART_WKUP), 1023 .sysc_fields = &omap_hwmod_sysc_type2, 1024}; 1025 1026static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { 1027 .name = "dmic", 1028 .sysc = &omap44xx_dmic_sysc, 1029}; 1030 1031/* dmic */ 1032static struct omap_hwmod omap44xx_dmic_hwmod; 1033static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 1034 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 1035 { .irq = -1 } 1036}; 1037 1038static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { 1039 { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, 1040 { .dma_req = -1 } 1041}; 1042 1043static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { 1044 { 1045 .pa_start = 0x4012e000, 1046 .pa_end = 0x4012e07f, 1047 .flags = ADDR_TYPE_RT 1048 }, 1049 { } 1050}; 1051 1052/* l4_abe -> dmic */ 1053static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { 1054 .master = &omap44xx_l4_abe_hwmod, 1055 .slave = &omap44xx_dmic_hwmod, 1056 .clk = "ocp_abe_iclk", 1057 .addr = omap44xx_dmic_addrs, 1058 .user = OCP_USER_MPU, 1059}; 1060 1061static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { 1062 { 1063 .pa_start = 0x4902e000, 1064 .pa_end = 0x4902e07f, 1065 .flags = ADDR_TYPE_RT 1066 }, 1067 { } 1068}; 1069 1070/* l4_abe -> dmic (dma) */ 1071static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { 1072 .master = &omap44xx_l4_abe_hwmod, 1073 .slave = &omap44xx_dmic_hwmod, 1074 .clk = "ocp_abe_iclk", 1075 .addr = omap44xx_dmic_dma_addrs, 1076 .user = OCP_USER_SDMA, 1077}; 1078 1079/* dmic slave ports */ 1080static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { 1081 &omap44xx_l4_abe__dmic, 1082 &omap44xx_l4_abe__dmic_dma, 1083}; 1084 1085static struct omap_hwmod omap44xx_dmic_hwmod = { 1086 .name = "dmic", 1087 .class = &omap44xx_dmic_hwmod_class, 1088 .clkdm_name = "abe_clkdm", 1089 .mpu_irqs = omap44xx_dmic_irqs, 1090 .sdma_reqs = omap44xx_dmic_sdma_reqs, 1091 .main_clk = "dmic_fck", 1092 .prcm = { 1093 .omap4 = { 1094 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, 1095 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, 1096 .modulemode = MODULEMODE_SWCTRL, 1097 }, 1098 }, 1099 .slaves = omap44xx_dmic_slaves, 1100 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), 1101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1102}; 1103 1104/* 1105 * 'dsp' class 1106 * dsp sub-system 1107 */ 1108 1109static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { 1110 .name = "dsp", 1111}; 1112 1113/* dsp */ 1114static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { 1115 { .irq = 28 + OMAP44XX_IRQ_GIC_START }, 1116 { .irq = -1 } 1117}; 1118 1119static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 1120 { .name = "mmu_cache", .rst_shift = 1 }, 1121}; 1122 1123static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { 1124 { .name = "dsp", .rst_shift = 0 }, 1125}; 1126 1127/* dsp -> iva */ 1128static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { 1129 .master = &omap44xx_dsp_hwmod, 1130 .slave = &omap44xx_iva_hwmod, 1131 .clk = "dpll_iva_m5x2_ck", 1132}; 1133 1134/* dsp master ports */ 1135static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { 1136 &omap44xx_dsp__l3_main_1, 1137 &omap44xx_dsp__l4_abe, 1138 &omap44xx_dsp__iva, 1139}; 1140 1141/* l4_cfg -> dsp */ 1142static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { 1143 .master = &omap44xx_l4_cfg_hwmod, 1144 .slave = &omap44xx_dsp_hwmod, 1145 .clk = "l4_div_ck", 1146 .user = OCP_USER_MPU | OCP_USER_SDMA, 1147}; 1148 1149/* dsp slave ports */ 1150static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { 1151 &omap44xx_l4_cfg__dsp, 1152}; 1153 1154/* Pseudo hwmod for reset control purpose only */ 1155static struct omap_hwmod omap44xx_dsp_c0_hwmod = { 1156 .name = "dsp_c0", 1157 .class = &omap44xx_dsp_hwmod_class, 1158 .clkdm_name = "tesla_clkdm", 1159 .flags = HWMOD_INIT_NO_RESET, 1160 .rst_lines = omap44xx_dsp_c0_resets, 1161 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), 1162 .prcm = { 1163 .omap4 = { 1164 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, 1165 }, 1166 }, 1167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1168}; 1169 1170static struct omap_hwmod omap44xx_dsp_hwmod = { 1171 .name = "dsp", 1172 .class = &omap44xx_dsp_hwmod_class, 1173 .clkdm_name = "tesla_clkdm", 1174 .mpu_irqs = omap44xx_dsp_irqs, 1175 .rst_lines = omap44xx_dsp_resets, 1176 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 1177 .main_clk = "dsp_fck", 1178 .prcm = { 1179 .omap4 = { 1180 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, 1181 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, 1182 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, 1183 .modulemode = MODULEMODE_HWCTRL, 1184 }, 1185 }, 1186 .slaves = omap44xx_dsp_slaves, 1187 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), 1188 .masters = omap44xx_dsp_masters, 1189 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), 1190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1191}; 1192 1193/* 1194 * 'dss' class 1195 * display sub-system 1196 */ 1197 1198static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { 1199 .rev_offs = 0x0000, 1200 .syss_offs = 0x0014, 1201 .sysc_flags = SYSS_HAS_RESET_STATUS, 1202}; 1203 1204static struct omap_hwmod_class omap44xx_dss_hwmod_class = { 1205 .name = "dss", 1206 .sysc = &omap44xx_dss_sysc, 1207}; 1208 1209/* dss */ 1210/* dss master ports */ 1211static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { 1212 &omap44xx_dss__l3_main_1, 1213}; 1214 1215static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { 1216 { 1217 .pa_start = 0x58000000, 1218 .pa_end = 0x5800007f, 1219 .flags = ADDR_TYPE_RT 1220 }, 1221 { } 1222}; 1223 1224/* l3_main_2 -> dss */ 1225static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { 1226 .master = &omap44xx_l3_main_2_hwmod, 1227 .slave = &omap44xx_dss_hwmod, 1228 .clk = "dss_fck", 1229 .addr = omap44xx_dss_dma_addrs, 1230 .user = OCP_USER_SDMA, 1231}; 1232 1233static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { 1234 { 1235 .pa_start = 0x48040000, 1236 .pa_end = 0x4804007f, 1237 .flags = ADDR_TYPE_RT 1238 }, 1239 { } 1240}; 1241 1242/* l4_per -> dss */ 1243static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { 1244 .master = &omap44xx_l4_per_hwmod, 1245 .slave = &omap44xx_dss_hwmod, 1246 .clk = "l4_div_ck", 1247 .addr = omap44xx_dss_addrs, 1248 .user = OCP_USER_MPU, 1249}; 1250 1251/* dss slave ports */ 1252static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { 1253 &omap44xx_l3_main_2__dss, 1254 &omap44xx_l4_per__dss, 1255}; 1256 1257static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1258 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1259 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1260 { .role = "dss_clk", .clk = "dss_dss_clk" }, 1261 { .role = "video_clk", .clk = "dss_48mhz_clk" }, 1262}; 1263 1264static struct omap_hwmod omap44xx_dss_hwmod = { 1265 .name = "dss_core", 1266 .class = &omap44xx_dss_hwmod_class, 1267 .clkdm_name = "l3_dss_clkdm", 1268 .main_clk = "dss_dss_clk", 1269 .prcm = { 1270 .omap4 = { 1271 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1272 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1273 }, 1274 }, 1275 .opt_clks = dss_opt_clks, 1276 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 1277 .slaves = omap44xx_dss_slaves, 1278 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), 1279 .masters = omap44xx_dss_masters, 1280 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), 1281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1282}; 1283 1284/* 1285 * 'dispc' class 1286 * display controller 1287 */ 1288 1289static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { 1290 .rev_offs = 0x0000, 1291 .sysc_offs = 0x0010, 1292 .syss_offs = 0x0014, 1293 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1294 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | 1295 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1296 SYSS_HAS_RESET_STATUS), 1297 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1298 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1299 .sysc_fields = &omap_hwmod_sysc_type1, 1300}; 1301 1302static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { 1303 .name = "dispc", 1304 .sysc = &omap44xx_dispc_sysc, 1305}; 1306 1307/* dss_dispc */ 1308static struct omap_hwmod omap44xx_dss_dispc_hwmod; 1309static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 1310 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 1311 { .irq = -1 } 1312}; 1313 1314static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { 1315 { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, 1316 { .dma_req = -1 } 1317}; 1318 1319static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { 1320 { 1321 .pa_start = 0x58001000, 1322 .pa_end = 0x58001fff, 1323 .flags = ADDR_TYPE_RT 1324 }, 1325 { } 1326}; 1327 1328/* l3_main_2 -> dss_dispc */ 1329static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { 1330 .master = &omap44xx_l3_main_2_hwmod, 1331 .slave = &omap44xx_dss_dispc_hwmod, 1332 .clk = "dss_fck", 1333 .addr = omap44xx_dss_dispc_dma_addrs, 1334 .user = OCP_USER_SDMA, 1335}; 1336 1337static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { 1338 { 1339 .pa_start = 0x48041000, 1340 .pa_end = 0x48041fff, 1341 .flags = ADDR_TYPE_RT 1342 }, 1343 { } 1344}; 1345 1346/* l4_per -> dss_dispc */ 1347static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { 1348 .master = &omap44xx_l4_per_hwmod, 1349 .slave = &omap44xx_dss_dispc_hwmod, 1350 .clk = "l4_div_ck", 1351 .addr = omap44xx_dss_dispc_addrs, 1352 .user = OCP_USER_MPU, 1353}; 1354 1355/* dss_dispc slave ports */ 1356static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { 1357 &omap44xx_l3_main_2__dss_dispc, 1358 &omap44xx_l4_per__dss_dispc, 1359}; 1360 1361static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = { 1362 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1363 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1364 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 1365}; 1366 1367static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1368 .name = "dss_dispc", 1369 .class = &omap44xx_dispc_hwmod_class, 1370 .clkdm_name = "l3_dss_clkdm", 1371 .mpu_irqs = omap44xx_dss_dispc_irqs, 1372 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 1373 .main_clk = "dss_dss_clk", 1374 .prcm = { 1375 .omap4 = { 1376 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1377 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1378 }, 1379 }, 1380 .opt_clks = dss_dispc_opt_clks, 1381 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks), 1382 .slaves = omap44xx_dss_dispc_slaves, 1383 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), 1384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1385}; 1386 1387/* 1388 * 'dsi' class 1389 * display serial interface controller 1390 */ 1391 1392static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { 1393 .rev_offs = 0x0000, 1394 .sysc_offs = 0x0010, 1395 .syss_offs = 0x0014, 1396 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1397 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1398 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1400 .sysc_fields = &omap_hwmod_sysc_type1, 1401}; 1402 1403static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { 1404 .name = "dsi", 1405 .sysc = &omap44xx_dsi_sysc, 1406}; 1407 1408/* dss_dsi1 */ 1409static struct omap_hwmod omap44xx_dss_dsi1_hwmod; 1410static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 1411 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 1412 { .irq = -1 } 1413}; 1414 1415static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { 1416 { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, 1417 { .dma_req = -1 } 1418}; 1419 1420static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { 1421 { 1422 .pa_start = 0x58004000, 1423 .pa_end = 0x580041ff, 1424 .flags = ADDR_TYPE_RT 1425 }, 1426 { } 1427}; 1428 1429/* l3_main_2 -> dss_dsi1 */ 1430static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { 1431 .master = &omap44xx_l3_main_2_hwmod, 1432 .slave = &omap44xx_dss_dsi1_hwmod, 1433 .clk = "dss_fck", 1434 .addr = omap44xx_dss_dsi1_dma_addrs, 1435 .user = OCP_USER_SDMA, 1436}; 1437 1438static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { 1439 { 1440 .pa_start = 0x48044000, 1441 .pa_end = 0x480441ff, 1442 .flags = ADDR_TYPE_RT 1443 }, 1444 { } 1445}; 1446 1447/* l4_per -> dss_dsi1 */ 1448static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { 1449 .master = &omap44xx_l4_per_hwmod, 1450 .slave = &omap44xx_dss_dsi1_hwmod, 1451 .clk = "l4_div_ck", 1452 .addr = omap44xx_dss_dsi1_addrs, 1453 .user = OCP_USER_MPU, 1454}; 1455 1456/* dss_dsi1 slave ports */ 1457static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { 1458 &omap44xx_l3_main_2__dss_dsi1, 1459 &omap44xx_l4_per__dss_dsi1, 1460}; 1461 1462static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 1463 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1464}; 1465 1466static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { 1467 .name = "dss_dsi1", 1468 .class = &omap44xx_dsi_hwmod_class, 1469 .clkdm_name = "l3_dss_clkdm", 1470 .mpu_irqs = omap44xx_dss_dsi1_irqs, 1471 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 1472 .main_clk = "dss_dss_clk", 1473 .prcm = { 1474 .omap4 = { 1475 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1476 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1477 }, 1478 }, 1479 .opt_clks = dss_dsi1_opt_clks, 1480 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 1481 .slaves = omap44xx_dss_dsi1_slaves, 1482 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), 1483 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1484}; 1485 1486/* dss_dsi2 */ 1487static struct omap_hwmod omap44xx_dss_dsi2_hwmod; 1488static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 1489 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 1490 { .irq = -1 } 1491}; 1492 1493static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { 1494 { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, 1495 { .dma_req = -1 } 1496}; 1497 1498static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { 1499 { 1500 .pa_start = 0x58005000, 1501 .pa_end = 0x580051ff, 1502 .flags = ADDR_TYPE_RT 1503 }, 1504 { } 1505}; 1506 1507/* l3_main_2 -> dss_dsi2 */ 1508static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { 1509 .master = &omap44xx_l3_main_2_hwmod, 1510 .slave = &omap44xx_dss_dsi2_hwmod, 1511 .clk = "dss_fck", 1512 .addr = omap44xx_dss_dsi2_dma_addrs, 1513 .user = OCP_USER_SDMA, 1514}; 1515 1516static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { 1517 { 1518 .pa_start = 0x48045000, 1519 .pa_end = 0x480451ff, 1520 .flags = ADDR_TYPE_RT 1521 }, 1522 { } 1523}; 1524 1525/* l4_per -> dss_dsi2 */ 1526static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { 1527 .master = &omap44xx_l4_per_hwmod, 1528 .slave = &omap44xx_dss_dsi2_hwmod, 1529 .clk = "l4_div_ck", 1530 .addr = omap44xx_dss_dsi2_addrs, 1531 .user = OCP_USER_MPU, 1532}; 1533 1534/* dss_dsi2 slave ports */ 1535static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { 1536 &omap44xx_l3_main_2__dss_dsi2, 1537 &omap44xx_l4_per__dss_dsi2, 1538}; 1539 1540static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { 1541 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1542}; 1543 1544static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { 1545 .name = "dss_dsi2", 1546 .class = &omap44xx_dsi_hwmod_class, 1547 .clkdm_name = "l3_dss_clkdm", 1548 .mpu_irqs = omap44xx_dss_dsi2_irqs, 1549 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 1550 .main_clk = "dss_dss_clk", 1551 .prcm = { 1552 .omap4 = { 1553 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1554 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1555 }, 1556 }, 1557 .opt_clks = dss_dsi2_opt_clks, 1558 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), 1559 .slaves = omap44xx_dss_dsi2_slaves, 1560 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), 1561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1562}; 1563 1564/* 1565 * 'hdmi' class 1566 * hdmi controller 1567 */ 1568 1569static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { 1570 .rev_offs = 0x0000, 1571 .sysc_offs = 0x0010, 1572 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | 1573 SYSC_HAS_SOFTRESET), 1574 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1575 SIDLE_SMART_WKUP), 1576 .sysc_fields = &omap_hwmod_sysc_type2, 1577}; 1578 1579static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { 1580 .name = "hdmi", 1581 .sysc = &omap44xx_hdmi_sysc, 1582}; 1583 1584/* dss_hdmi */ 1585static struct omap_hwmod omap44xx_dss_hdmi_hwmod; 1586static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 1587 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 1588 { .irq = -1 } 1589}; 1590 1591static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { 1592 { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, 1593 { .dma_req = -1 } 1594}; 1595 1596static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { 1597 { 1598 .pa_start = 0x58006000, 1599 .pa_end = 0x58006fff, 1600 .flags = ADDR_TYPE_RT 1601 }, 1602 { } 1603}; 1604 1605/* l3_main_2 -> dss_hdmi */ 1606static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { 1607 .master = &omap44xx_l3_main_2_hwmod, 1608 .slave = &omap44xx_dss_hdmi_hwmod, 1609 .clk = "dss_fck", 1610 .addr = omap44xx_dss_hdmi_dma_addrs, 1611 .user = OCP_USER_SDMA, 1612}; 1613 1614static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { 1615 { 1616 .pa_start = 0x48046000, 1617 .pa_end = 0x48046fff, 1618 .flags = ADDR_TYPE_RT 1619 }, 1620 { } 1621}; 1622 1623/* l4_per -> dss_hdmi */ 1624static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { 1625 .master = &omap44xx_l4_per_hwmod, 1626 .slave = &omap44xx_dss_hdmi_hwmod, 1627 .clk = "l4_div_ck", 1628 .addr = omap44xx_dss_hdmi_addrs, 1629 .user = OCP_USER_MPU, 1630}; 1631 1632/* dss_hdmi slave ports */ 1633static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { 1634 &omap44xx_l3_main_2__dss_hdmi, 1635 &omap44xx_l4_per__dss_hdmi, 1636}; 1637 1638static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 1639 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1640}; 1641 1642static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { 1643 .name = "dss_hdmi", 1644 .class = &omap44xx_hdmi_hwmod_class, 1645 .clkdm_name = "l3_dss_clkdm", 1646 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1647 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1648 .main_clk = "dss_dss_clk", 1649 .prcm = { 1650 .omap4 = { 1651 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1652 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1653 }, 1654 }, 1655 .opt_clks = dss_hdmi_opt_clks, 1656 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 1657 .slaves = omap44xx_dss_hdmi_slaves, 1658 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), 1659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1660}; 1661 1662/* 1663 * 'rfbi' class 1664 * remote frame buffer interface 1665 */ 1666 1667static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { 1668 .rev_offs = 0x0000, 1669 .sysc_offs = 0x0010, 1670 .syss_offs = 0x0014, 1671 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1672 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1673 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1674 .sysc_fields = &omap_hwmod_sysc_type1, 1675}; 1676 1677static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { 1678 .name = "rfbi", 1679 .sysc = &omap44xx_rfbi_sysc, 1680}; 1681 1682/* dss_rfbi */ 1683static struct omap_hwmod omap44xx_dss_rfbi_hwmod; 1684static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 1685 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 1686 { .dma_req = -1 } 1687}; 1688 1689static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { 1690 { 1691 .pa_start = 0x58002000, 1692 .pa_end = 0x580020ff, 1693 .flags = ADDR_TYPE_RT 1694 }, 1695 { } 1696}; 1697 1698/* l3_main_2 -> dss_rfbi */ 1699static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { 1700 .master = &omap44xx_l3_main_2_hwmod, 1701 .slave = &omap44xx_dss_rfbi_hwmod, 1702 .clk = "dss_fck", 1703 .addr = omap44xx_dss_rfbi_dma_addrs, 1704 .user = OCP_USER_SDMA, 1705}; 1706 1707static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { 1708 { 1709 .pa_start = 0x48042000, 1710 .pa_end = 0x480420ff, 1711 .flags = ADDR_TYPE_RT 1712 }, 1713 { } 1714}; 1715 1716/* l4_per -> dss_rfbi */ 1717static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { 1718 .master = &omap44xx_l4_per_hwmod, 1719 .slave = &omap44xx_dss_rfbi_hwmod, 1720 .clk = "l4_div_ck", 1721 .addr = omap44xx_dss_rfbi_addrs, 1722 .user = OCP_USER_MPU, 1723}; 1724 1725/* dss_rfbi slave ports */ 1726static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { 1727 &omap44xx_l3_main_2__dss_rfbi, 1728 &omap44xx_l4_per__dss_rfbi, 1729}; 1730 1731static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 1732 { .role = "ick", .clk = "dss_fck" }, 1733}; 1734 1735static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { 1736 .name = "dss_rfbi", 1737 .class = &omap44xx_rfbi_hwmod_class, 1738 .clkdm_name = "l3_dss_clkdm", 1739 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, 1740 .main_clk = "dss_dss_clk", 1741 .prcm = { 1742 .omap4 = { 1743 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1744 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1745 }, 1746 }, 1747 .opt_clks = dss_rfbi_opt_clks, 1748 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 1749 .slaves = omap44xx_dss_rfbi_slaves, 1750 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), 1751 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1752}; 1753 1754/* 1755 * 'venc' class 1756 * video encoder 1757 */ 1758 1759static struct omap_hwmod_class omap44xx_venc_hwmod_class = { 1760 .name = "venc", 1761}; 1762 1763/* dss_venc */ 1764static struct omap_hwmod omap44xx_dss_venc_hwmod; 1765static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { 1766 { 1767 .pa_start = 0x58003000, 1768 .pa_end = 0x580030ff, 1769 .flags = ADDR_TYPE_RT 1770 }, 1771 { } 1772}; 1773 1774/* l3_main_2 -> dss_venc */ 1775static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { 1776 .master = &omap44xx_l3_main_2_hwmod, 1777 .slave = &omap44xx_dss_venc_hwmod, 1778 .clk = "dss_fck", 1779 .addr = omap44xx_dss_venc_dma_addrs, 1780 .user = OCP_USER_SDMA, 1781}; 1782 1783static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { 1784 { 1785 .pa_start = 0x48043000, 1786 .pa_end = 0x480430ff, 1787 .flags = ADDR_TYPE_RT 1788 }, 1789 { } 1790}; 1791 1792/* l4_per -> dss_venc */ 1793static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { 1794 .master = &omap44xx_l4_per_hwmod, 1795 .slave = &omap44xx_dss_venc_hwmod, 1796 .clk = "l4_div_ck", 1797 .addr = omap44xx_dss_venc_addrs, 1798 .user = OCP_USER_MPU, 1799}; 1800 1801/* dss_venc slave ports */ 1802static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { 1803 &omap44xx_l3_main_2__dss_venc, 1804 &omap44xx_l4_per__dss_venc, 1805}; 1806 1807static struct omap_hwmod omap44xx_dss_venc_hwmod = { 1808 .name = "dss_venc", 1809 .class = &omap44xx_venc_hwmod_class, 1810 .clkdm_name = "l3_dss_clkdm", 1811 .main_clk = "dss_dss_clk", 1812 .prcm = { 1813 .omap4 = { 1814 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1815 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1816 }, 1817 }, 1818 .slaves = omap44xx_dss_venc_slaves, 1819 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), 1820 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1821}; 1822 1823/* 1824 * 'gpio' class 1825 * general purpose io module 1826 */ 1827 1828static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { 1829 .rev_offs = 0x0000, 1830 .sysc_offs = 0x0010, 1831 .syss_offs = 0x0114, 1832 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 1833 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1834 SYSS_HAS_RESET_STATUS), 1835 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1836 SIDLE_SMART_WKUP), 1837 .sysc_fields = &omap_hwmod_sysc_type1, 1838}; 1839 1840static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { 1841 .name = "gpio", 1842 .sysc = &omap44xx_gpio_sysc, 1843 .rev = 2, 1844}; 1845 1846/* gpio dev_attr */ 1847static struct omap_gpio_dev_attr gpio_dev_attr = { 1848 .bank_width = 32, 1849 .dbck_flag = true, 1850}; 1851 1852/* gpio1 */ 1853static struct omap_hwmod omap44xx_gpio1_hwmod; 1854static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1855 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1856 { .irq = -1 } 1857}; 1858 1859static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 1860 { 1861 .pa_start = 0x4a310000, 1862 .pa_end = 0x4a3101ff, 1863 .flags = ADDR_TYPE_RT 1864 }, 1865 { } 1866}; 1867 1868/* l4_wkup -> gpio1 */ 1869static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { 1870 .master = &omap44xx_l4_wkup_hwmod, 1871 .slave = &omap44xx_gpio1_hwmod, 1872 .clk = "l4_wkup_clk_mux_ck", 1873 .addr = omap44xx_gpio1_addrs, 1874 .user = OCP_USER_MPU | OCP_USER_SDMA, 1875}; 1876 1877/* gpio1 slave ports */ 1878static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { 1879 &omap44xx_l4_wkup__gpio1, 1880}; 1881 1882static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1883 { .role = "dbclk", .clk = "gpio1_dbclk" }, 1884}; 1885 1886static struct omap_hwmod omap44xx_gpio1_hwmod = { 1887 .name = "gpio1", 1888 .class = &omap44xx_gpio_hwmod_class, 1889 .clkdm_name = "l4_wkup_clkdm", 1890 .mpu_irqs = omap44xx_gpio1_irqs, 1891 .main_clk = "gpio1_ick", 1892 .prcm = { 1893 .omap4 = { 1894 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, 1895 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, 1896 .modulemode = MODULEMODE_HWCTRL, 1897 }, 1898 }, 1899 .opt_clks = gpio1_opt_clks, 1900 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1901 .dev_attr = &gpio_dev_attr, 1902 .slaves = omap44xx_gpio1_slaves, 1903 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), 1904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1905}; 1906 1907/* gpio2 */ 1908static struct omap_hwmod omap44xx_gpio2_hwmod; 1909static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 1910 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 1911 { .irq = -1 } 1912}; 1913 1914static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { 1915 { 1916 .pa_start = 0x48055000, 1917 .pa_end = 0x480551ff, 1918 .flags = ADDR_TYPE_RT 1919 }, 1920 { } 1921}; 1922 1923/* l4_per -> gpio2 */ 1924stati…
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