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/arch/arm/mach-omap2/prm-regbits-44xx.h

https://github.com/AICP/kernel_asus_grouper
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   1/*
   2 * OMAP44xx Power Management register bits
   3 *
   4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2010 Nokia Corporation
   6 *
   7 * Paul Walmsley (paul@pwsan.com)
   8 * Rajendra Nayak (rnayak@ti.com)
   9 * Benoit Cousson (b-cousson@ti.com)
  10 *
  11 * This file is automatically generated from the OMAP hardware databases.
  12 * We respectfully ask that any modifications to this file be coordinated
  13 * with the public linux-omap@vger.kernel.org mailing list and the
  14 * authors above to ensure that the autogeneration scripts are kept
  15 * up-to-date with the file contents.
  16 *
  17 * This program is free software; you can redistribute it and/or modify
  18 * it under the terms of the GNU General Public License version 2 as
  19 * published by the Free Software Foundation.
  20 */
  21
  22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
  23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
  24
  25
  26/*
  27 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  28 * PRM_LDO_SRAM_MPU_SETUP
  29 */
  30#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT				1
  31#define OMAP4430_ABBOFF_ACT_EXPORT_MASK					(1 << 1)
  32
  33/*
  34 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  35 * PRM_LDO_SRAM_MPU_SETUP
  36 */
  37#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT				2
  38#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK				(1 << 2)
  39
  40/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
  41#define OMAP4430_ABB_IVA_DONE_EN_SHIFT					31
  42#define OMAP4430_ABB_IVA_DONE_EN_MASK					(1 << 31)
  43
  44/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
  45#define OMAP4430_ABB_IVA_DONE_ST_SHIFT					31
  46#define OMAP4430_ABB_IVA_DONE_ST_MASK					(1 << 31)
  47
  48/* Used by PRM_IRQENABLE_MPU_2 */
  49#define OMAP4430_ABB_MPU_DONE_EN_SHIFT					7
  50#define OMAP4430_ABB_MPU_DONE_EN_MASK					(1 << 7)
  51
  52/* Used by PRM_IRQSTATUS_MPU_2 */
  53#define OMAP4430_ABB_MPU_DONE_ST_SHIFT					7
  54#define OMAP4430_ABB_MPU_DONE_ST_MASK					(1 << 7)
  55
  56/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
  57#define OMAP4430_ACTIVE_FBB_SEL_SHIFT					2
  58#define OMAP4430_ACTIVE_FBB_SEL_MASK					(1 << 2)
  59
  60/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
  61#define OMAP4430_ACTIVE_RBB_SEL_SHIFT					1
  62#define OMAP4430_ACTIVE_RBB_SEL_MASK					(1 << 1)
  63
  64/* Used by PM_ABE_PWRSTCTRL */
  65#define OMAP4430_AESSMEM_ONSTATE_SHIFT					16
  66#define OMAP4430_AESSMEM_ONSTATE_MASK					(0x3 << 16)
  67
  68/* Used by PM_ABE_PWRSTCTRL */
  69#define OMAP4430_AESSMEM_RETSTATE_SHIFT					8
  70#define OMAP4430_AESSMEM_RETSTATE_MASK					(1 << 8)
  71
  72/* Used by PM_ABE_PWRSTST */
  73#define OMAP4430_AESSMEM_STATEST_SHIFT					4
  74#define OMAP4430_AESSMEM_STATEST_MASK					(0x3 << 4)
  75
  76/*
  77 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  78 * PRM_LDO_SRAM_MPU_SETUP
  79 */
  80#define OMAP4430_AIPOFF_SHIFT						8
  81#define OMAP4430_AIPOFF_MASK						(1 << 8)
  82
  83/* Used by PRM_VOLTCTRL */
  84#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT				0
  85#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK				(0x3 << 0)
  86
  87/* Used by PRM_VOLTCTRL */
  88#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT				4
  89#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK				(0x3 << 4)
  90
  91/* Used by PRM_VOLTCTRL */
  92#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT				2
  93#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK				(0x3 << 2)
  94
  95/* Used by PRM_VC_ERRST */
  96#define OMAP4430_BYPS_RA_ERR_SHIFT					25
  97#define OMAP4430_BYPS_RA_ERR_MASK					(1 << 25)
  98
  99/* Used by PRM_VC_ERRST */
 100#define OMAP4430_BYPS_SA_ERR_SHIFT					24
 101#define OMAP4430_BYPS_SA_ERR_MASK					(1 << 24)
 102
 103/* Used by PRM_VC_ERRST */
 104#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT					26
 105#define OMAP4430_BYPS_TIMEOUT_ERR_MASK					(1 << 26)
 106
 107/* Used by PRM_RSTST */
 108#define OMAP4430_C2C_RST_SHIFT						10
 109#define OMAP4430_C2C_RST_MASK						(1 << 10)
 110
 111/* Used by PM_CAM_PWRSTCTRL */
 112#define OMAP4430_CAM_MEM_ONSTATE_SHIFT					16
 113#define OMAP4430_CAM_MEM_ONSTATE_MASK					(0x3 << 16)
 114
 115/* Used by PM_CAM_PWRSTST */
 116#define OMAP4430_CAM_MEM_STATEST_SHIFT					4
 117#define OMAP4430_CAM_MEM_STATEST_MASK					(0x3 << 4)
 118
 119/* Used by PRM_CLKREQCTRL */
 120#define OMAP4430_CLKREQ_COND_SHIFT					0
 121#define OMAP4430_CLKREQ_COND_MASK					(0x7 << 0)
 122
 123/* Used by PRM_VC_VAL_SMPS_RA_CMD */
 124#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT					0
 125#define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)
 126
 127/* Used by PRM_VC_VAL_SMPS_RA_CMD */
 128#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT					8
 129#define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)
 130
 131/* Used by PRM_VC_VAL_SMPS_RA_CMD */
 132#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT					16
 133#define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)
 134
 135/* Used by PRM_VC_CFG_CHANNEL */
 136#define OMAP4430_CMD_VDD_CORE_L_SHIFT					4
 137#define OMAP4430_CMD_VDD_CORE_L_MASK					(1 << 4)
 138
 139/* Used by PRM_VC_CFG_CHANNEL */
 140#define OMAP4430_CMD_VDD_IVA_L_SHIFT					12
 141#define OMAP4430_CMD_VDD_IVA_L_MASK					(1 << 12)
 142
 143/* Used by PRM_VC_CFG_CHANNEL */
 144#define OMAP4430_CMD_VDD_MPU_L_SHIFT					17
 145#define OMAP4430_CMD_VDD_MPU_L_MASK					(1 << 17)
 146
 147/* Used by PM_CORE_PWRSTCTRL */
 148#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT				18
 149#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK				(0x3 << 18)
 150
 151/* Used by PM_CORE_PWRSTCTRL */
 152#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT				9
 153#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK				(1 << 9)
 154
 155/* Used by PM_CORE_PWRSTST */
 156#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT				6
 157#define OMAP4430_CORE_OCMRAM_STATEST_MASK				(0x3 << 6)
 158
 159/* Used by PM_CORE_PWRSTCTRL */
 160#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT				16
 161#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK				(0x3 << 16)
 162
 163/* Used by PM_CORE_PWRSTCTRL */
 164#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT				8
 165#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK				(1 << 8)
 166
 167/* Used by PM_CORE_PWRSTST */
 168#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT				4
 169#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK				(0x3 << 4)
 170
 171/* Used by REVISION_PRM */
 172#define OMAP4430_CUSTOM_SHIFT						6
 173#define OMAP4430_CUSTOM_MASK						(0x3 << 6)
 174
 175/* Used by PRM_VC_VAL_BYPASS */
 176#define OMAP4430_DATA_SHIFT						16
 177#define OMAP4430_DATA_MASK						(0xff << 16)
 178
 179/* Used by PRM_DEVICE_OFF_CTRL */
 180#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT				0
 181#define OMAP4430_DEVICE_OFF_ENABLE_MASK					(1 << 0)
 182
 183/* Used by PRM_VC_CFG_I2C_MODE */
 184#define OMAP4430_DFILTEREN_SHIFT					6
 185#define OMAP4430_DFILTEREN_MASK						(1 << 6)
 186
 187/*
 188 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 189 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
 190 */
 191#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT				0
 192#define OMAP4430_DISABLE_RTA_EXPORT_MASK				(1 << 0)
 193
 194/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 195#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT				4
 196#define OMAP4430_DPLL_ABE_RECAL_EN_MASK					(1 << 4)
 197
 198/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 199#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT				4
 200#define OMAP4430_DPLL_ABE_RECAL_ST_MASK					(1 << 4)
 201
 202/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 203#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT				0
 204#define OMAP4430_DPLL_CORE_RECAL_EN_MASK				(1 << 0)
 205
 206/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 207#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT				0
 208#define OMAP4430_DPLL_CORE_RECAL_ST_MASK				(1 << 0)
 209
 210/* Used by PRM_IRQENABLE_MPU */
 211#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT				6
 212#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK				(1 << 6)
 213
 214/* Used by PRM_IRQSTATUS_MPU */
 215#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT				6
 216#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK				(1 << 6)
 217
 218/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 219#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT				2
 220#define OMAP4430_DPLL_IVA_RECAL_EN_MASK					(1 << 2)
 221
 222/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 223#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT				2
 224#define OMAP4430_DPLL_IVA_RECAL_ST_MASK					(1 << 2)
 225
 226/* Used by PRM_IRQENABLE_MPU */
 227#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT				1
 228#define OMAP4430_DPLL_MPU_RECAL_EN_MASK					(1 << 1)
 229
 230/* Used by PRM_IRQSTATUS_MPU */
 231#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT				1
 232#define OMAP4430_DPLL_MPU_RECAL_ST_MASK					(1 << 1)
 233
 234/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 235#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT				3
 236#define OMAP4430_DPLL_PER_RECAL_EN_MASK					(1 << 3)
 237
 238/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 239#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT				3
 240#define OMAP4430_DPLL_PER_RECAL_ST_MASK					(1 << 3)
 241
 242/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 243#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT				7
 244#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK				(1 << 7)
 245
 246/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 247#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT				7
 248#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK				(1 << 7)
 249
 250/* Used by PM_DSS_PWRSTCTRL */
 251#define OMAP4430_DSS_MEM_ONSTATE_SHIFT					16
 252#define OMAP4430_DSS_MEM_ONSTATE_MASK					(0x3 << 16)
 253
 254/* Used by PM_DSS_PWRSTCTRL */
 255#define OMAP4430_DSS_MEM_RETSTATE_SHIFT					8
 256#define OMAP4430_DSS_MEM_RETSTATE_MASK					(1 << 8)
 257
 258/* Used by PM_DSS_PWRSTST */
 259#define OMAP4430_DSS_MEM_STATEST_SHIFT					4
 260#define OMAP4430_DSS_MEM_STATEST_MASK					(0x3 << 4)
 261
 262/* Used by PM_CORE_PWRSTCTRL */
 263#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT				20
 264#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK				(0x3 << 20)
 265
 266/* Used by PM_CORE_PWRSTCTRL */
 267#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT				10
 268#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK				(1 << 10)
 269
 270/* Used by PM_CORE_PWRSTST */
 271#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT				8
 272#define OMAP4430_DUCATI_L2RAM_STATEST_MASK				(0x3 << 8)
 273
 274/* Used by PM_CORE_PWRSTCTRL */
 275#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT				22
 276#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK				(0x3 << 22)
 277
 278/* Used by PM_CORE_PWRSTCTRL */
 279#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT				11
 280#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK				(1 << 11)
 281
 282/* Used by PM_CORE_PWRSTST */
 283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT				10
 284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK				(0x3 << 10)
 285
 286/* Used by PRM_DEVICE_OFF_CTRL */
 287#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT				8
 288#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK				(1 << 8)
 289
 290/* Used by PRM_DEVICE_OFF_CTRL */
 291#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT				9
 292#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK				(1 << 9)
 293
 294/* Used by RM_MPU_RSTST */
 295#define OMAP4430_EMULATION_RST_SHIFT					0
 296#define OMAP4430_EMULATION_RST_MASK					(1 << 0)
 297
 298/* Used by RM_DUCATI_RSTST */
 299#define OMAP4430_EMULATION_RST1ST_SHIFT					3
 300#define OMAP4430_EMULATION_RST1ST_MASK					(1 << 3)
 301
 302/* Used by RM_DUCATI_RSTST */
 303#define OMAP4430_EMULATION_RST2ST_SHIFT					4
 304#define OMAP4430_EMULATION_RST2ST_MASK					(1 << 4)
 305
 306/* Used by RM_IVAHD_RSTST */
 307#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT				3
 308#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK				(1 << 3)
 309
 310/* Used by RM_IVAHD_RSTST */
 311#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT				4
 312#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK				(1 << 4)
 313
 314/* Used by PM_EMU_PWRSTCTRL */
 315#define OMAP4430_EMU_BANK_ONSTATE_SHIFT					16
 316#define OMAP4430_EMU_BANK_ONSTATE_MASK					(0x3 << 16)
 317
 318/* Used by PM_EMU_PWRSTST */
 319#define OMAP4430_EMU_BANK_STATEST_SHIFT					4
 320#define OMAP4430_EMU_BANK_STATEST_MASK					(0x3 << 4)
 321
 322/*
 323 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 324 * PRM_LDO_SRAM_MPU_SETUP
 325 */
 326#define OMAP4430_ENFUNC1_EXPORT_SHIFT					3
 327#define OMAP4430_ENFUNC1_EXPORT_MASK					(1 << 3)
 328
 329/*
 330 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 331 * PRM_LDO_SRAM_MPU_SETUP
 332 */
 333#define OMAP4430_ENFUNC3_EXPORT_SHIFT					5
 334#define OMAP4430_ENFUNC3_EXPORT_MASK					(1 << 5)
 335
 336/*
 337 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 338 * PRM_LDO_SRAM_MPU_SETUP
 339 */
 340#define OMAP4430_ENFUNC4_SHIFT						6
 341#define OMAP4430_ENFUNC4_MASK						(1 << 6)
 342
 343/*
 344 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
 345 * PRM_LDO_SRAM_MPU_SETUP
 346 */
 347#define OMAP4430_ENFUNC5_SHIFT						7
 348#define OMAP4430_ENFUNC5_MASK						(1 << 7)
 349
 350/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 351#define OMAP4430_ERRORGAIN_SHIFT					16
 352#define OMAP4430_ERRORGAIN_MASK						(0xff << 16)
 353
 354/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 355#define OMAP4430_ERROROFFSET_SHIFT					24
 356#define OMAP4430_ERROROFFSET_MASK					(0xff << 24)
 357
 358/* Used by PRM_RSTST */
 359#define OMAP4430_EXTERNAL_WARM_RST_SHIFT				5
 360#define OMAP4430_EXTERNAL_WARM_RST_MASK					(1 << 5)
 361
 362/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 363#define OMAP4430_FORCEUPDATE_SHIFT					1
 364#define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
 365
 366/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 367#define OMAP4430_FORCEUPDATEWAIT_SHIFT					8
 368#define OMAP4430_FORCEUPDATEWAIT_MASK					(0xffffff << 8)
 369
 370/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
 371#define OMAP4430_FORCEWKUP_EN_SHIFT					10
 372#define OMAP4430_FORCEWKUP_EN_MASK					(1 << 10)
 373
 374/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
 375#define OMAP4430_FORCEWKUP_ST_SHIFT					10
 376#define OMAP4430_FORCEWKUP_ST_MASK					(1 << 10)
 377
 378/* Used by REVISION_PRM */
 379#define OMAP4430_FUNC_SHIFT						16
 380#define OMAP4430_FUNC_MASK						(0xfff << 16)
 381
 382/* Used by PM_GFX_PWRSTCTRL */
 383#define OMAP4430_GFX_MEM_ONSTATE_SHIFT					16
 384#define OMAP4430_GFX_MEM_ONSTATE_MASK					(0x3 << 16)
 385
 386/* Used by PM_GFX_PWRSTST */
 387#define OMAP4430_GFX_MEM_STATEST_SHIFT					4
 388#define OMAP4430_GFX_MEM_STATEST_MASK					(0x3 << 4)
 389
 390/* Used by PRM_RSTST */
 391#define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
 392#define OMAP4430_GLOBAL_COLD_RST_MASK					(1 << 0)
 393
 394/* Used by PRM_RSTST */
 395#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
 396#define OMAP4430_GLOBAL_WARM_SW_RST_MASK				(1 << 1)
 397
 398/* Used by PRM_IO_PMCTRL */
 399#define OMAP4430_GLOBAL_WUEN_SHIFT					16
 400#define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
 401
 402/* Used by PRM_VC_CFG_I2C_MODE */
 403#define OMAP4430_HSMCODE_SHIFT						0
 404#define OMAP4430_HSMCODE_MASK						(0x7 << 0)
 405
 406/* Used by PRM_VC_CFG_I2C_MODE */
 407#define OMAP4430_HSMODEEN_SHIFT						3
 408#define OMAP4430_HSMODEEN_MASK						(1 << 3)
 409
 410/* Used by PRM_VC_CFG_I2C_CLK */
 411#define OMAP4430_HSSCLH_SHIFT						16
 412#define OMAP4430_HSSCLH_MASK						(0xff << 16)
 413
 414/* Used by PRM_VC_CFG_I2C_CLK */
 415#define OMAP4430_HSSCLL_SHIFT						24
 416#define OMAP4430_HSSCLL_MASK						(0xff << 24)
 417
 418/* Used by PM_IVAHD_PWRSTCTRL */
 419#define OMAP4430_HWA_MEM_ONSTATE_SHIFT					16
 420#define OMAP4430_HWA_MEM_ONSTATE_MASK					(0x3 << 16)
 421
 422/* Used by PM_IVAHD_PWRSTCTRL */
 423#define OMAP4430_HWA_MEM_RETSTATE_SHIFT					8
 424#define OMAP4430_HWA_MEM_RETSTATE_MASK					(1 << 8)
 425
 426/* Used by PM_IVAHD_PWRSTST */
 427#define OMAP4430_HWA_MEM_STATEST_SHIFT					4
 428#define OMAP4430_HWA_MEM_STATEST_MASK					(0x3 << 4)
 429
 430/* Used by RM_MPU_RSTST */
 431#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT				1
 432#define OMAP4430_ICECRUSHER_MPU_RST_MASK				(1 << 1)
 433
 434/* Used by RM_DUCATI_RSTST */
 435#define OMAP4430_ICECRUSHER_RST1ST_SHIFT				5
 436#define OMAP4430_ICECRUSHER_RST1ST_MASK					(1 << 5)
 437
 438/* Used by RM_DUCATI_RSTST */
 439#define OMAP4430_ICECRUSHER_RST2ST_SHIFT				6
 440#define OMAP4430_ICECRUSHER_RST2ST_MASK					(1 << 6)
 441
 442/* Used by RM_IVAHD_RSTST */
 443#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT				5
 444#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK				(1 << 5)
 445
 446/* Used by RM_IVAHD_RSTST */
 447#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT				6
 448#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK				(1 << 6)
 449
 450/* Used by PRM_RSTST */
 451#define OMAP4430_ICEPICK_RST_SHIFT					9
 452#define OMAP4430_ICEPICK_RST_MASK					(1 << 9)
 453
 454/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 455#define OMAP4430_INITVDD_SHIFT						2
 456#define OMAP4430_INITVDD_MASK						(1 << 2)
 457
 458/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 459#define OMAP4430_INITVOLTAGE_SHIFT					8
 460#define OMAP4430_INITVOLTAGE_MASK					(0xff << 8)
 461
 462/*
 463 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
 464 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
 465 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
 466 */
 467#define OMAP4430_INTRANSITION_SHIFT					20
 468#define OMAP4430_INTRANSITION_MASK					(1 << 20)
 469
 470/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 471#define OMAP4430_IO_EN_SHIFT						9
 472#define OMAP4430_IO_EN_MASK						(1 << 9)
 473
 474/* Used by PRM_IO_PMCTRL */
 475#define OMAP4430_IO_ON_STATUS_SHIFT					5
 476#define OMAP4430_IO_ON_STATUS_MASK					(1 << 5)
 477
 478/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 479#define OMAP4430_IO_ST_SHIFT						9
 480#define OMAP4430_IO_ST_MASK						(1 << 9)
 481
 482/* Used by PRM_IO_PMCTRL */
 483#define OMAP4430_ISOCLK_OVERRIDE_SHIFT					0
 484#define OMAP4430_ISOCLK_OVERRIDE_MASK					(1 << 0)
 485
 486/* Used by PRM_IO_PMCTRL */
 487#define OMAP4430_ISOCLK_STATUS_SHIFT					1
 488#define OMAP4430_ISOCLK_STATUS_MASK					(1 << 1)
 489
 490/* Used by PRM_IO_PMCTRL */
 491#define OMAP4430_ISOOVR_EXTEND_SHIFT					4
 492#define OMAP4430_ISOOVR_EXTEND_MASK					(1 << 4)
 493
 494/* Used by PRM_IO_COUNT */
 495#define OMAP4430_ISO_2_ON_TIME_SHIFT					0
 496#define OMAP4430_ISO_2_ON_TIME_MASK					(0xff << 0)
 497
 498/* Used by PM_L3INIT_PWRSTCTRL */
 499#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT				16
 500#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK				(0x3 << 16)
 501
 502/* Used by PM_L3INIT_PWRSTCTRL */
 503#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT				8
 504#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK				(1 << 8)
 505
 506/* Used by PM_L3INIT_PWRSTST */
 507#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT				4
 508#define OMAP4430_L3INIT_BANK1_STATEST_MASK				(0x3 << 4)
 509
 510/*
 511 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
 512 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
 513 */
 514#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT				24
 515#define OMAP4430_LASTPOWERSTATEENTERED_MASK				(0x3 << 24)
 516
 517/*
 518 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
 519 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
 520 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
 521 */
 522#define OMAP4430_LOGICRETSTATE_SHIFT					2
 523#define OMAP4430_LOGICRETSTATE_MASK					(1 << 2)
 524
 525/*
 526 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
 527 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
 528 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
 529 */
 530#define OMAP4430_LOGICSTATEST_SHIFT					2
 531#define OMAP4430_LOGICSTATEST_MASK					(1 << 2)
 532
 533/*
 534 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
 535 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
 536 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
 537 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
 538 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
 539 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
 540 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
 541 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
 542 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
 543 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
 544 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
 545 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
 546 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
 547 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
 548 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
 549 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
 550 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
 551 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
 552 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
 553 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
 554 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
 555 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
 556 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
 557 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
 558 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
 559 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
 560 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
 561 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
 562 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
 563 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
 564 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
 565 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
 566 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
 567 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
 568 */
 569#define OMAP4430_LOSTCONTEXT_DFF_SHIFT					0
 570#define OMAP4430_LOSTCONTEXT_DFF_MASK					(1 << 0)
 571
 572/*
 573 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
 574 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
 575 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
 576 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
 577 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
 578 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
 579 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
 580 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
 581 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
 582 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
 583 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
 584 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
 585 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
 586 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
 587 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
 588 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
 589 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
 590 */
 591#define OMAP4430_LOSTCONTEXT_RFF_SHIFT					1
 592#define OMAP4430_LOSTCONTEXT_RFF_MASK					(1 << 1)
 593
 594/* Used by RM_ABE_AESS_CONTEXT */
 595#define OMAP4430_LOSTMEM_AESSMEM_SHIFT					8
 596#define OMAP4430_LOSTMEM_AESSMEM_MASK					(1 << 8)
 597
 598/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
 599#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT					8
 600#define OMAP4430_LOSTMEM_CAM_MEM_MASK					(1 << 8)
 601
 602/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
 603#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT				8
 604#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK				(1 << 8)
 605
 606/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
 607#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT			9
 608#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK			(1 << 9)
 609
 610/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
 611#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT				8
 612#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK				(1 << 8)
 613
 614/*
 615 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
 616 * RM_SDMA_SDMA_CONTEXT
 617 */
 618#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT				8
 619#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK				(1 << 8)
 620
 621/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
 622#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT					8
 623#define OMAP4430_LOSTMEM_DSS_MEM_MASK					(1 << 8)
 624
 625/* Used by RM_DUCATI_DUCATI_CONTEXT */
 626#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT				9
 627#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK				(1 << 9)
 628
 629/* Used by RM_DUCATI_DUCATI_CONTEXT */
 630#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT				8
 631#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK				(1 << 8)
 632
 633/* Used by RM_EMU_DEBUGSS_CONTEXT */
 634#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT					8
 635#define OMAP4430_LOSTMEM_EMU_BANK_MASK					(1 << 8)
 636
 637/* Used by RM_GFX_GFX_CONTEXT */
 638#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT					8
 639#define OMAP4430_LOSTMEM_GFX_MEM_MASK					(1 << 8)
 640
 641/* Used by RM_IVAHD_IVAHD_CONTEXT */
 642#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT					10
 643#define OMAP4430_LOSTMEM_HWA_MEM_MASK					(1 << 10)
 644
 645/*
 646 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
 647 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
 648 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
 649 * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
 650 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
 651 */
 652#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT				8
 653#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK				(1 << 8)
 654
 655/* Used by RM_MPU_MPU_CONTEXT */
 656#define OMAP4430_LOSTMEM_MPU_L1_SHIFT					8
 657#define OMAP4430_LOSTMEM_MPU_L1_MASK					(1 << 8)
 658
 659/* Used by RM_MPU_MPU_CONTEXT */
 660#define OMAP4430_LOSTMEM_MPU_L2_SHIFT					9
 661#define OMAP4430_LOSTMEM_MPU_L2_MASK					(1 << 9)
 662
 663/* Used by RM_MPU_MPU_CONTEXT */
 664#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT					10
 665#define OMAP4430_LOSTMEM_MPU_RAM_MASK					(1 << 10)
 666
 667/*
 668 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
 669 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
 670 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
 671 */
 672#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT				8
 673#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK				(1 << 8)
 674
 675/*
 676 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
 677 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
 678 */
 679#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT				8
 680#define OMAP4430_LOSTMEM_PERIHPMEM_MASK					(1 << 8)
 681
 682/*
 683 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
 684 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
 685 * RM_L4SEC_CRYPTODMA_CONTEXT
 686 */
 687#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT				8
 688#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK				(1 << 8)
 689
 690/* Used by RM_IVAHD_SL2_CONTEXT */
 691#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT					8
 692#define OMAP4430_LOSTMEM_SL2_MEM_MASK					(1 << 8)
 693
 694/* Used by RM_IVAHD_IVAHD_CONTEXT */
 695#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT					8
 696#define OMAP4430_LOSTMEM_TCM1_MEM_MASK					(1 << 8)
 697
 698/* Used by RM_IVAHD_IVAHD_CONTEXT */
 699#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT					9
 700#define OMAP4430_LOSTMEM_TCM2_MEM_MASK					(1 << 9)
 701
 702/* Used by RM_TESLA_TESLA_CONTEXT */
 703#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT				10
 704#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK				(1 << 10)
 705
 706/* Used by RM_TESLA_TESLA_CONTEXT */
 707#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT					8
 708#define OMAP4430_LOSTMEM_TESLA_L1_MASK					(1 << 8)
 709
 710/* Used by RM_TESLA_TESLA_CONTEXT */
 711#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT					9
 712#define OMAP4430_LOSTMEM_TESLA_L2_MASK					(1 << 9)
 713
 714/* Used by RM_WKUP_SARRAM_CONTEXT */
 715#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT				8
 716#define OMAP4430_LOSTMEM_WKUP_BANK_MASK					(1 << 8)
 717
 718/*
 719 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
 720 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
 721 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
 722 */
 723#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT				4
 724#define OMAP4430_LOWPOWERSTATECHANGE_MASK				(1 << 4)
 725
 726/* Used by PRM_MODEM_IF_CTRL */
 727#define OMAP4430_MODEM_READY_SHIFT					1
 728#define OMAP4430_MODEM_READY_MASK					(1 << 1)
 729
 730/* Used by PRM_MODEM_IF_CTRL */
 731#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT				9
 732#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK				(1 << 9)
 733
 734/* Used by PRM_MODEM_IF_CTRL */
 735#define OMAP4430_MODEM_SLEEP_ST_SHIFT					16
 736#define OMAP4430_MODEM_SLEEP_ST_MASK					(1 << 16)
 737
 738/* Used by PRM_MODEM_IF_CTRL */
 739#define OMAP4430_MODEM_WAKE_IRQ_SHIFT					8
 740#define OMAP4430_MODEM_WAKE_IRQ_MASK					(1 << 8)
 741
 742/* Used by PM_MPU_PWRSTCTRL */
 743#define OMAP4430_MPU_L1_ONSTATE_SHIFT					16
 744#define OMAP4430_MPU_L1_ONSTATE_MASK					(0x3 << 16)
 745
 746/* Used by PM_MPU_PWRSTCTRL */
 747#define OMAP4430_MPU_L1_RETSTATE_SHIFT					8
 748#define OMAP4430_MPU_L1_RETSTATE_MASK					(1 << 8)
 749
 750/* Used by PM_MPU_PWRSTST */
 751#define OMAP4430_MPU_L1_STATEST_SHIFT					4
 752#define OMAP4430_MPU_L1_STATEST_MASK					(0x3 << 4)
 753
 754/* Used by PM_MPU_PWRSTCTRL */
 755#define OMAP4430_MPU_L2_ONSTATE_SHIFT					18
 756#define OMAP4430_MPU_L2_ONSTATE_MASK					(0x3 << 18)
 757
 758/* Used by PM_MPU_PWRSTCTRL */
 759#define OMAP4430_MPU_L2_RETSTATE_SHIFT					9
 760#define OMAP4430_MPU_L2_RETSTATE_MASK					(1 << 9)
 761
 762/* Used by PM_MPU_PWRSTST */
 763#define OMAP4430_MPU_L2_STATEST_SHIFT					6
 764#define OMAP4430_MPU_L2_STATEST_MASK					(0x3 << 6)
 765
 766/* Used by PM_MPU_PWRSTCTRL */
 767#define OMAP4430_MPU_RAM_ONSTATE_SHIFT					20
 768#define OMAP4430_MPU_RAM_ONSTATE_MASK					(0x3 << 20)
 769
 770/* Used by PM_MPU_PWRSTCTRL */
 771#define OMAP4430_MPU_RAM_RETSTATE_SHIFT					10
 772#define OMAP4430_MPU_RAM_RETSTATE_MASK					(1 << 10)
 773
 774/* Used by PM_MPU_PWRSTST */
 775#define OMAP4430_MPU_RAM_STATEST_SHIFT					8
 776#define OMAP4430_MPU_RAM_STATEST_MASK					(0x3 << 8)
 777
 778/* Used by PRM_RSTST */
 779#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT				2
 780#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK				(1 << 2)
 781
 782/* Used by PRM_RSTST */
 783#define OMAP4430_MPU_WDT_RST_SHIFT					3
 784#define OMAP4430_MPU_WDT_RST_MASK					(1 << 3)
 785
 786/* Used by PM_L4PER_PWRSTCTRL */
 787#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT				18
 788#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK				(0x3 << 18)
 789
 790/* Used by PM_L4PER_PWRSTCTRL */
 791#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT			9
 792#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK				(1 << 9)
 793
 794/* Used by PM_L4PER_PWRSTST */
 795#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT				6
 796#define OMAP4430_NONRETAINED_BANK_STATEST_MASK				(0x3 << 6)
 797
 798/* Used by PM_CORE_PWRSTCTRL */
 799#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT				24
 800#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK				(0x3 << 24)
 801
 802/* Used by PM_CORE_PWRSTCTRL */
 803#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT				12
 804#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK				(1 << 12)
 805
 806/* Used by PM_CORE_PWRSTST */
 807#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT				12
 808#define OMAP4430_OCP_NRET_BANK_STATEST_MASK				(0x3 << 12)
 809
 810/*
 811 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
 812 * PRM_VC_VAL_CMD_VDD_MPU_L
 813 */
 814#define OMAP4430_OFF_SHIFT						0
 815#define OMAP4430_OFF_MASK						(0xff << 0)
 816
 817/*
 818 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
 819 * PRM_VC_VAL_CMD_VDD_MPU_L
 820 */
 821#define OMAP4430_ON_SHIFT						24
 822#define OMAP4430_ON_MASK						(0xff << 24)
 823
 824/*
 825 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
 826 * PRM_VC_VAL_CMD_VDD_MPU_L
 827 */
 828#define OMAP4430_ONLP_SHIFT						16
 829#define OMAP4430_ONLP_MASK						(0xff << 16)
 830
 831/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 832#define OMAP4430_OPP_CHANGE_SHIFT					2
 833#define OMAP4430_OPP_CHANGE_MASK					(1 << 2)
 834
 835/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 836#define OMAP4430_OPP_SEL_SHIFT						0
 837#define OMAP4430_OPP_SEL_MASK						(0x3 << 0)
 838
 839/* Used by PRM_SRAM_COUNT */
 840#define OMAP4430_PCHARGECNT_VALUE_SHIFT					0
 841#define OMAP4430_PCHARGECNT_VALUE_MASK					(0x3f << 0)
 842
 843/* Used by PRM_PSCON_COUNT */
 844#define OMAP4430_PCHARGE_TIME_SHIFT					0
 845#define OMAP4430_PCHARGE_TIME_MASK					(0xff << 0)
 846
 847/* Used by PM_ABE_PWRSTCTRL */
 848#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT				20
 849#define OMAP4430_PERIPHMEM_ONSTATE_MASK					(0x3 << 20)
 850
 851/* Used by PM_ABE_PWRSTCTRL */
 852#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT				10
 853#define OMAP4430_PERIPHMEM_RETSTATE_MASK				(1 << 10)
 854
 855/* Used by PM_ABE_PWRSTST */
 856#define OMAP4430_PERIPHMEM_STATEST_SHIFT				8
 857#define OMAP4430_PERIPHMEM_STATEST_MASK					(0x3 << 8)
 858
 859/* Used by PRM_PHASE1_CNDP */
 860#define OMAP4430_PHASE1_CNDP_SHIFT					0
 861#define OMAP4430_PHASE1_CNDP_MASK					(0xffffffff << 0)
 862
 863/* Used by PRM_PHASE2A_CNDP */
 864#define OMAP4430_PHASE2A_CNDP_SHIFT					0
 865#define OMAP4430_PHASE2A_CNDP_MASK					(0xffffffff << 0)
 866
 867/* Used by PRM_PHASE2B_CNDP */
 868#define OMAP4430_PHASE2B_CNDP_SHIFT					0
 869#define OMAP4430_PHASE2B_CNDP_MASK					(0xffffffff << 0)
 870
 871/* Used by PRM_PSCON_COUNT */
 872#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT				8
 873#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK				(0xff << 8)
 874
 875/*
 876 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
 877 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
 878 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
 879 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
 880 */
 881#define OMAP4430_POWERSTATE_SHIFT					0
 882#define OMAP4430_POWERSTATE_MASK					(0x3 << 0)
 883
 884/*
 885 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
 886 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
 887 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
 888 */
 889#define OMAP4430_POWERSTATEST_SHIFT					0
 890#define OMAP4430_POWERSTATEST_MASK					(0x3 << 0)
 891
 892/* Used by PRM_PWRREQCTRL */
 893#define OMAP4430_PWRREQ_COND_SHIFT					0
 894#define OMAP4430_PWRREQ_COND_MASK					(0x3 << 0)
 895
 896/* Used by PRM_VC_CFG_CHANNEL */
 897#define OMAP4430_RACEN_VDD_CORE_L_SHIFT					3
 898#define OMAP4430_RACEN_VDD_CORE_L_MASK					(1 << 3)
 899
 900/* Used by PRM_VC_CFG_CHANNEL */
 901#define OMAP4430_RACEN_VDD_IVA_L_SHIFT					11
 902#define OMAP4430_RACEN_VDD_IVA_L_MASK					(1 << 11)
 903
 904/* Used by PRM_VC_CFG_CHANNEL */
 905#define OMAP4430_RACEN_VDD_MPU_L_SHIFT					20
 906#define OMAP4430_RACEN_VDD_MPU_L_MASK					(1 << 20)
 907
 908/* Used by PRM_VC_CFG_CHANNEL */
 909#define OMAP4430_RAC_VDD_CORE_L_SHIFT					2
 910#define OMAP4430_RAC_VDD_CORE_L_MASK					(1 << 2)
 911
 912/* Used by PRM_VC_CFG_CHANNEL */
 913#define OMAP4430_RAC_VDD_IVA_L_SHIFT					10
 914#define OMAP4430_RAC_VDD_IVA_L_MASK					(1 << 10)
 915
 916/* Used by PRM_VC_CFG_CHANNEL */
 917#define OMAP4430_RAC_VDD_MPU_L_SHIFT					19
 918#define OMAP4430_RAC_VDD_MPU_L_MASK					(1 << 19)
 919
 920/*
 921 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 922 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 923 * PRM_VOLTSETUP_MPU_RET_SLEEP
 924 */
 925#define OMAP4430_RAMP_DOWN_COUNT_SHIFT					16
 926#define OMAP4430_RAMP_DOWN_COUNT_MASK					(0x3f << 16)
 927
 928/*
 929 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 930 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 931 * PRM_VOLTSETUP_MPU_RET_SLEEP
 932 */
 933#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT				24
 934#define OMAP4430_RAMP_DOWN_PRESCAL_MASK					(0x3 << 24)
 935
 936/*
 937 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 938 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 939 * PRM_VOLTSETUP_MPU_RET_SLEEP
 940 */
 941#define OMAP4430_RAMP_UP_COUNT_SHIFT					0
 942#define OMAP4430_RAMP_UP_COUNT_MASK					(0x3f << 0)
 943
 944/*
 945 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
 946 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
 947 * PRM_VOLTSETUP_MPU_RET_SLEEP
 948 */
 949#define OMAP4430_RAMP_UP_PRESCAL_SHIFT					8
 950#define OMAP4430_RAMP_UP_PRESCAL_MASK					(0x3 << 8)
 951
 952/* Used by PRM_VC_CFG_CHANNEL */
 953#define OMAP4430_RAV_VDD_CORE_L_SHIFT					1
 954#define OMAP4430_RAV_VDD_CORE_L_MASK					(1 << 1)
 955
 956/* Used by PRM_VC_CFG_CHANNEL */
 957#define OMAP4430_RAV_VDD_IVA_L_SHIFT					9
 958#define OMAP4430_RAV_VDD_IVA_L_MASK					(1 << 9)
 959
 960/* Used by PRM_VC_CFG_CHANNEL */
 961#define OMAP4430_RAV_VDD_MPU_L_SHIFT					18
 962#define OMAP4430_RAV_VDD_MPU_L_MASK					(1 << 18)
 963
 964/* Used by PRM_VC_VAL_BYPASS */
 965#define OMAP4430_REGADDR_SHIFT						8
 966#define OMAP4430_REGADDR_MASK						(0xff << 8)
 967
 968/*
 969 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
 970 * PRM_VC_VAL_CMD_VDD_MPU_L
 971 */
 972#define OMAP4430_RET_SHIFT						8
 973#define OMAP4430_RET_MASK						(0xff << 8)
 974
 975/* Used by PM_L4PER_PWRSTCTRL */
 976#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT				16
 977#define OMAP4430_RETAINED_BANK_ONSTATE_MASK				(0x3 << 16)
 978
 979/* Used by PM_L4PER_PWRSTCTRL */
 980#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT				8
 981#define OMAP4430_RETAINED_BANK_RETSTATE_MASK				(1 << 8)
 982
 983/* Used by PM_L4PER_PWRSTST */
 984#define OMAP4430_RETAINED_BANK_STATEST_SHIFT				4
 985#define OMAP4430_RETAINED_BANK_STATEST_MASK				(0x3 << 4)
 986
 987/*
 988 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
 989 * PRM_LDO_SRAM_MPU_CTRL
 990 */
 991#define OMAP4430_RETMODE_ENABLE_SHIFT					0
 992#define OMAP4430_RETMODE_ENABLE_MASK					(1 << 0)
 993
 994/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 995#define OMAP4430_RST1_SHIFT						0
 996#define OMAP4430_RST1_MASK						(1 << 0)
 997
 998/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 999#define OMAP4430_RST1ST_SHIFT						0
1000#define OMAP4430_RST1ST_MASK						(1 << 0)
1001
1002/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
1003#define OMAP4430_RST2_SHIFT						1
1004#define OMAP4430_RST2_MASK						(1 << 1)
1005
1006/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
1007#define OMAP4430_RST2ST_SHIFT						1
1008#define OMAP4430_RST2ST_MASK						(1 << 1)
1009
1010/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
1011#define OMAP4430_RST3_SHIFT						2
1012#define OMAP4430_RST3_MASK						(1 << 2)
1013
1014/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
1015#define OMAP4430_RST3ST_SHIFT						2
1016#define OMAP4430_RST3ST_MASK						(1 << 2)
1017
1018/* Used by PRM_RSTTIME */
1019#define OMAP4430_RSTTIME1_SHIFT						0
1020#define OMAP4430_RSTTIME1_MASK						(0x3ff << 0)
1021
1022/* Used by PRM_RSTTIME */
1023#define OMAP4430_RSTTIME2_SHIFT						10
1024#define OMAP4430_RSTTIME2_MASK						(0x1f << 10)
1025
1026/* Used by PRM_RSTCTRL */
1027#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT				1
1028#define OMAP4430_RST_GLOBAL_COLD_SW_MASK				(1 << 1)
1029
1030/* Used by PRM_RSTCTRL */
1031#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT				0
1032#define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
1033
1034/* Used by REVISION_PRM */
1035#define OMAP4430_R_RTL_SHIFT						11
1036#define OMAP4430_R_RTL_MASK						(0x1f << 11)
1037
1038/* Used by PRM_VC_CFG_CHANNEL */
1039#define OMAP4430_SA_VDD_CORE_L_SHIFT					0
1040#define OMAP4430_SA_VDD_CORE_L_MASK					(1 << 0)
1041
1042/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
1043#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT				0
1044#define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
1045
1046/* Used by PRM_VC_CFG_CHANNEL */
1047#define OMAP4430_SA_VDD_IVA_L_SHIFT					8
1048#define OMAP4430_SA_VDD_IVA_L_MASK					(1 << 8)
1049
1050/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
1051#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT			8
1052#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
1053
1054/* Used by PRM_VC_CFG_CHANNEL */
1055#define OMAP4430_SA_VDD_MPU_L_SHIFT					16
1056#define OMAP4430_SA_VDD_MPU_L_MASK					(1 << 16)
1057
1058/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
1059#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT			16
1060#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
1061
1062/* Used by REVISION_PRM */
1063#define OMAP4430_SCHEME_SHIFT						30
1064#define OMAP4430_SCHEME_MASK						(0x3 << 30)
1065
1066/* Used by PRM_VC_CFG_I2C_CLK */
1067#define OMAP4430_SCLH_SHIFT						0
1068#define OMAP4430_SCLH_MASK						(0xff << 0)
1069
1070/* Used by PRM_VC_CFG_I2C_CLK */
1071#define OMAP4430_SCLL_SHIFT						8
1072#define OMAP4430_SCLL_MASK						(0xff << 8)
1073
1074/* Used by PRM_RSTST */
1075#define OMAP4430_SECURE_WDT_RST_SHIFT					4
1076#define OMAP4430_SECURE_WDT_RST_MASK					(1 << 4)
1077
1078/* Used by PM_IVAHD_PWRSTCTRL */
1079#define OMAP4430_SL2_MEM_ONSTATE_SHIFT					18
1080#define OMAP4430_SL2_MEM_ONSTATE_MASK					(0x3 << 18)
1081
1082/* Used by PM_IVAHD_PWRSTCTRL */
1083#define OMAP4430_SL2_MEM_RETSTATE_SHIFT					9
1084#define OMAP4430_SL2_MEM_RETSTATE_MASK					(1 << 9)
1085
1086/* Used by PM_IVAHD_PWRSTST */
1087#define OMAP4430_SL2_MEM_STATEST_SHIFT					6
1088#define OMAP4430_SL2_MEM_STATEST_MASK					(0x3 << 6)
1089
1090/* Used by PRM_VC_VAL_BYPASS */
1091#define OMAP4430_SLAVEADDR_SHIFT					0
1092#define OMAP4430_SLAVEADDR_MASK						(0x7f << 0)
1093
1094/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1095#define OMAP4430_SLEEP_RBB_SEL_SHIFT					3
1096#define OMAP4430_SLEEP_RBB_SEL_MASK					(1 << 3)
1097
1098/* Used by PRM_SRAM_COUNT */
1099#define OMAP4430_SLPCNT_VALUE_SHIFT					16
1100#define OMAP4430_SLPCNT_VALUE_MASK					(0xff << 16)
1101
1102/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1103#define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
1104#define OMAP4430_SMPSWAITTIMEMAX_MASK					(0xffff << 8)
1105
1106/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1107#define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
1108#define OMAP4430_SMPSWAITTIMEMIN_MASK					(0xffff << 8)
1109
1110/* Used by PRM_VC_ERRST */
1111#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT					1
1112#define OMAP4430_SMPS_RA_ERR_CORE_MASK					(1 << 1)
1113
1114/* Used by PRM_VC_ERRST */
1115#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT					9
1116#define OMAP4430_SMPS_RA_ERR_IVA_MASK					(1 << 9)
1117
1118/* Used by PRM_VC_ERRST */
1119#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT					17
1120#define OMAP4430_SMPS_RA_ERR_MPU_MASK					(1 << 17)
1121
1122/* Used by PRM_VC_ERRST */
1123#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT					0
1124#define OMAP4430_SMPS_SA_ERR_CORE_MASK					(1 << 0)
1125
1126/* Used by PRM_VC_ERRST */
1127#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT					8
1128#define OMAP4430_SMPS_SA_ERR_IVA_MASK					(1 << 8)
1129
1130/* Used by PRM_VC_ERRST */
1131#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT					16
1132#define OMAP4430_SMPS_SA_ERR_MPU_MASK					(1 << 16)
1133
1134/* Used by PRM_VC_ERRST */
1135#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT				2
1136#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK				(1 << 2)
1137
1138/* Used by PRM_VC_ERRST */
1139#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT				10
1140#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK				(1 << 10)
1141
1142/* Used by PRM_VC_ERRST */
1143#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT				18
1144#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK				(1 << 18)
1145
1146/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1147#define OMAP4430_SR2EN_SHIFT						0
1148#define OMAP4430_SR2EN_MASK						(1 << 0)
1149
1150/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1151#define OMAP4430_SR2_IN_TRANSITION_SHIFT				6
1152#define OMAP4430_SR2_IN_TRANSITION_MASK					(1 << 6)
1153
1154/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1155#define OMAP4430_SR2_STATUS_SHIFT					3
1156#define OMAP4430_SR2_STATUS_MASK					(0x3 << 3)
1157
1158/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1159#define OMAP4430_SR2_WTCNT_VALUE_SHIFT					8
1160#define OMAP4430_SR2_WTCNT_VALUE_MASK					(0xff << 8)
1161
1162/*
1163 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1164 * PRM_LDO_SRAM_MPU_CTRL
1165 */
1166#define OMAP4430_SRAMLDO_STATUS_SHIFT					8
1167#define OMAP4430_SRAMLDO_STATUS_MASK					(1 << 8)
1168
1169/*
1170 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1171 * PRM_LDO_SRAM_MPU_CTRL
1172 */
1173#define OMAP4430_SRAM_IN_TRANSITION_SHIFT				9
1174#define OMAP4430_SRAM_IN_TRANSITION_MASK				(1 << 9)
1175
1176/* Used by PRM_VC_CFG_I2C_MODE */
1177#define OMAP4430_SRMODEEN_SHIFT						4
1178#define OMAP4430_SRMODEEN_MASK						(1 << 4)
1179
1180/* Used by PRM_VOLTSETUP_WARMRESET */
1181#define OMAP4430_STABLE_COUNT_SHIFT					0
1182#define OMAP4430_STABLE_COUNT_MASK					(0x3f << 0)
1183
1184/* Used by PRM_VOLTSETUP_WARMRESET */
1185#define OMAP4430_STABLE_PRESCAL_SHIFT					8
1186#define OMAP4430_STABLE_PRESCAL_MASK					(0x3 << 8)
1187
1188/* Used by PRM_LDO_BANDGAP_SETUP */
1189#define OMAP4430_STARTUP_COUNT_SHIFT					0
1190#define OMAP4430_STARTUP_COUNT_MASK					(0xff << 0)
1191
1192/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1193#define OMAP4430_STARTUP_COUNT_24_31_SHIFT				24
1194#define OMAP4430_STARTUP_COUNT_24_31_MASK				(0xff << 24)
1195
1196/* Used by PM_IVAHD_PWRSTCTRL */
1197#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT					20
1198#define OMAP4430_TCM1_MEM_ONSTATE_MASK					(0x3 << 20)
1199
1200/* Used by PM_IVAHD_PWRSTCTRL */
1201#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT				10
1202#define OMAP4430_TCM1_MEM_RETSTATE_MASK					(1 << 10)
1203
1204/* Used by PM_IVAHD_PWRSTST */
1205#define OMAP4430_TCM1_MEM_STATEST_SHIFT					8
1206#define OMAP4430_TCM1_MEM_STATEST_MASK					(0x3 << 8)
1207
1208/* Used by PM_IVAHD_PWRSTCTRL */
1209#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT					22
1210#define OMAP4430_TCM2_MEM_ONSTATE_MASK					(0x3 << 22)
1211
1212/* Used by PM_IVAHD_PWRSTCTRL */
1213#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT				11
1214#define OMAP4430_TCM2_MEM_RETSTATE_MASK					(1 << 11)
1215
1216/* Used by PM_IVAHD_PWRSTST */
1217#define OMAP4430_TCM2_MEM_STATEST_SHIFT					10
1218#define OMAP4430_TCM2_MEM_STATEST_MASK					(0x3 << 10)
1219
1220/* Used by RM_TESLA_RSTST */
1221#define OMAP4430_TESLASS_EMU_RSTST_SHIFT				2
1222#define OMAP4430_TESLASS_EMU_RSTST_MASK					(1 << 2)
1223
1224/* Used by RM_TESLA_RSTST */
1225#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT				3
1226#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK				(1 << 3)
1227
1228/* Used by PM_TESLA_PWRSTCTRL */
1229#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT				20
1230#define OMAP4430_TESLA_EDMA_ONSTATE_MASK				(0x3 << 20)
1231
1232/* Used by PM_TESLA_PWRSTCTRL */
1233#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT				10
1234#define OMAP4430_TESLA_EDMA_RETSTATE_MASK				(1 << 10)
1235
1236/* Used by PM_TESLA_PWRSTST */
1237#define OMAP4430_TESLA_EDMA_STATEST_SHIFT				8
1238#define OMAP4430_TESLA_EDMA_STATEST_MASK				(0x3 << 8)
1239
1240/* Used by PM_TESLA_PWRSTCTRL */
1241#define OMAP4430_TESLA_L1_ONSTATE_SHIFT					16
1242#define OMAP4430_TESLA_L1_ONSTATE_MASK					(0x3 << 16)
1243
1244/* Used by PM_TESLA_PWRSTCTRL */
1245#define OMAP4430_TESLA_L1_RETSTATE_SHIFT				8
1246#define OMAP4430_TESLA_L1_RETSTATE_MASK					(1 << 8)
1247
1248/* Used by PM_TESLA_PWRSTST */
1249#define OMAP4430_TESLA_L1_STATEST_SHIFT					4
1250#define OMAP4430_TESLA_L1_STATEST_MASK					(0x3 << 4)
1251
1252/* Used by PM_TESLA_PWRSTCTRL */
1253#define OMAP4430_TESLA_L2_ONSTATE_SHIFT					18
1254#define OMAP4430_TESLA_L2_ONSTATE_MASK					(0x3 << 18)
1255
1256/* Used by PM_TESLA_PWRSTCTRL */
1257#define OMAP4430_TESLA_L2_RETSTATE_SHIFT				9
1258#define OMAP4430_TESLA_L2_RETSTATE_MASK					(1 << 9)
1259
1260/* Used by PM_TESLA_PWRSTST */
1261#define OMAP4430_TESLA_L2_STATEST_SHIFT					6
1262#define OMAP4430_TESLA_L2_STATEST_MASK					(0x3 << 6)
1263
1264/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1265#define OMAP4430_TIMEOUT_SHIFT						0
1266#define OMAP4430_TIMEOUT_MASK						(0xffff << 0)
1267
1268/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
1269#define OMAP4430_TIMEOUTEN_SHIFT					3
1270#define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
1271
1272/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1273#define OMAP4430_TRANSITION_EN_SHIFT					8
1274#define OMAP4430_TRANSITION_EN_MASK					(1 << 8)
1275
1276/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1277#define OMAP4430_TRANSITION_ST_SHIFT					8
1278#define OMAP4430_TRANSITION_ST_MASK					(1 << 8)
1279
1280/* Used by PRM_VC_VAL_BYPASS */
1281#define OMAP4430_VALID_SHIFT						24
1282#define OMAP4430_VALID_MASK						(1 << 24)
1283
1284/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1285#define OMAP4430_VC_BYPASSACK_EN_SHIFT					14
1286#define OMAP4430_VC_BYPASSACK_EN_MASK					(1 << 14)
1287
1288/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1289#define OMAP4430_VC_BYPASSACK_ST_SHIFT					14
1290#define OMAP4430_VC_BYPASSACK_ST_MASK					(1 << 14)
1291
1292/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1293#define OMAP4430_VC_CORE_VPACK_EN_SHIFT					22
1294#define OMAP4430_VC_CORE_VPACK_EN_MASK					(1 << 22)
1295
1296/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1297#define OMAP4430_VC_CORE_VPACK_ST_SHIFT					22
1298#define OMAP4430_VC_CORE_VPACK_ST_MASK					(1 << 22)
1299
1300/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1301#define OMAP4430_VC_IVA_VPACK_EN_SHIFT					30
1302#define OMAP4430_VC_IVA_VPACK_EN_MASK					(1 << 30)
1303
1304/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1305#define OMAP4430_VC_IVA_VPACK_ST_SHIFT					30
1306#define OMAP4430_VC_IVA_VPACK_ST_MASK					(1 << 30)
1307
1308/* Used by PRM_IRQENABLE_MPU_2 */
1309#define OMAP4430_VC_MPU_VPACK_EN_SHIFT					6
1310#define OMAP4430_VC_MPU_VPACK_EN_MASK					(1 << 6)
1311
1312/* Used by PRM_IRQSTATUS_MPU_2 */
1313#define OMAP4430_VC_MPU_VPACK_ST_SHIFT					6
1314#define OMAP4430_VC_MPU_VPACK_ST_MASK					(1 << 6)
1315
1316/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1317#define OMAP4430_VC_RAERR_EN_SHIFT					12
1318#define OMAP4430_VC_RAERR_EN_MASK					(1 << 12)
1319
1320/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1321#define OMAP4430_VC_RAERR_ST_SHIFT					12
1322#define OMAP4430_VC_RAERR_ST_MASK					(1 << 12)
1323
1324/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1325#define OMAP4430_VC_SAERR_EN_SHIFT					11
1326#define OMAP4430_VC_SAERR_EN_MASK					(1 << 11)
1327
1328/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1329#define OMAP4430_VC_SAERR_ST_SHIFT					11
1330#define OMAP4430_VC_SAERR_ST_MASK					(1 << 11)
1331
1332/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1333#define OMAP4430_VC_TOERR_EN_SHIFT					13
1334#define OMAP4430_VC_TOERR_EN_MASK					(1 << 13)
1335
1336/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1337#define OMAP4430_VC_TOERR_ST_SHIFT					13
1338#define OMAP4430_VC_TOERR_ST_MASK					(1 << 13)
1339
1340/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1341#define OMAP4430_VDDMAX_SHIFT						24
1342#define OMAP4430_VDDMAX_MASK						(0xff << 24)
1343
1344/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1345#define OMAP4430_VDDMIN_SHIFT						16
1346#define OMAP4430_VDDMIN_MASK						(0xff << 16)
1347
1348/* Used by PRM_VOLTCTRL */
1349#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT				12
1350#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK				(1 << 12)
1351
1352/* Used by PRM_RSTST */
1353#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
1354#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK				(1 << 8)
1355
1356/* Used by PRM_VOLTCTRL */
1357#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT				14
1358#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK				(1 << 14)
1359
1360/* Used by PRM_VOLTCTRL */
1361#define OMAP4430_VDD_IVA_PRESENCE_SHIFT					9
1362#define OMAP4430_VDD_IVA_PRESENCE_MASK					(1 << 9)
1363
1364/* Used by PRM_RSTST */
1365#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
1366#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK				(1 << 7)
1367
1368/* Used by PRM_VOLTCTRL */
1369#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT				13
1370#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK				(1 << 13)
1371
1372/* Used by PRM_VOLTCTRL */
1373#define OMAP4430_VDD_MPU_PRESENCE_SHIFT					8
1374#define OMAP4430_VDD_MPU_PRESENCE_MASK					(1 << 8)
1375
1376/* Used by PRM_RSTST */
1377#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
1378#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK				(1 << 6)
1379
1380/* Used by PRM_VC_ERRST */
1381#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT					4
1382#define OMAP4430_VFSM_RA_ERR_CORE_MASK					(1 << 4)
1383
1384/* Used by PRM_VC_ERRST */
1385#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT					12
1386#define OMAP4430_VFSM_RA_ERR_IVA_MASK					(1 << 12)
1387
1388/* Used by PRM_VC_ERRST */
1389#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT					20
1390#define OMAP4430_VFSM_RA_ERR_MPU_MASK					(1 << 20)
1391
1392/* Used by PRM_VC_ERRST */
1393#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT					3
1394#define OMAP4430_VFSM_SA_ERR_CORE_MASK					(1 << 3)
1395
1396/* Used by PRM_VC_ERRST */
1397#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT					11
1398#define OMAP4430_VFSM_SA_ERR_IVA_MASK					(1 << 11)
1399
1400/* Used by PRM_VC_ERRST */
1401#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT					19
1402#define OMAP4430_VFSM_SA_ERR_MPU_MASK					(1 << 19)
1403
1404/* Used by PRM_VC_ERRST */
1405#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT				5
1406#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK				(1 << 5)
1407
1408/* Used by PRM_VC_ERRST */
1409#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT				13
1410#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK				(1 << 13)
1411
1412/* Used by PRM_VC_ERRST */
1413#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT				21
1414#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK				(1 << 21)
1415
1416/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1417#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT					0
1418#define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
1419
1420/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1421#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT					8
1422#define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
1423
1424/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1425#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT					16
1426#define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
1427
1428/* Used …

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