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/drivers/net/ethernet/broadcom/tg3.c

http://github.com/mirrors/linux
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   1/*
   2 * tg3.c: Broadcom Tigon3 ethernet driver.
   3 *
   4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6 * Copyright (C) 2004 Sun Microsystems Inc.
   7 * Copyright (C) 2005-2016 Broadcom Corporation.
   8 * Copyright (C) 2016-2017 Broadcom Limited.
   9 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
  10 * refers to Broadcom Inc. and/or its subsidiaries.
  11 *
  12 * Firmware is:
  13 *	Derived from proprietary unpublished source code,
  14 *	Copyright (C) 2000-2016 Broadcom Corporation.
  15 *	Copyright (C) 2016-2017 Broadcom Ltd.
  16 *	Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
  17 *	refers to Broadcom Inc. and/or its subsidiaries.
  18 *
  19 *	Permission is hereby granted for the distribution of this firmware
  20 *	data in hexadecimal or equivalent format, provided this copyright
  21 *	notice is accompanying it.
  22 */
  23
  24
  25#include <linux/module.h>
  26#include <linux/moduleparam.h>
  27#include <linux/stringify.h>
  28#include <linux/kernel.h>
  29#include <linux/sched/signal.h>
  30#include <linux/types.h>
  31#include <linux/compiler.h>
  32#include <linux/slab.h>
  33#include <linux/delay.h>
  34#include <linux/in.h>
  35#include <linux/interrupt.h>
  36#include <linux/ioport.h>
  37#include <linux/pci.h>
  38#include <linux/netdevice.h>
  39#include <linux/etherdevice.h>
  40#include <linux/skbuff.h>
  41#include <linux/ethtool.h>
  42#include <linux/mdio.h>
  43#include <linux/mii.h>
  44#include <linux/phy.h>
  45#include <linux/brcmphy.h>
  46#include <linux/if.h>
  47#include <linux/if_vlan.h>
  48#include <linux/ip.h>
  49#include <linux/tcp.h>
  50#include <linux/workqueue.h>
  51#include <linux/prefetch.h>
  52#include <linux/dma-mapping.h>
  53#include <linux/firmware.h>
  54#include <linux/ssb/ssb_driver_gige.h>
  55#include <linux/hwmon.h>
  56#include <linux/hwmon-sysfs.h>
  57#include <linux/crc32poly.h>
  58
  59#include <net/checksum.h>
  60#include <net/ip.h>
  61
  62#include <linux/io.h>
  63#include <asm/byteorder.h>
  64#include <linux/uaccess.h>
  65
  66#include <uapi/linux/net_tstamp.h>
  67#include <linux/ptp_clock_kernel.h>
  68
  69#define BAR_0	0
  70#define BAR_2	2
  71
  72#include "tg3.h"
  73
  74/* Functions & macros to verify TG3_FLAGS types */
  75
  76static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  77{
  78	return test_bit(flag, bits);
  79}
  80
  81static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  82{
  83	set_bit(flag, bits);
  84}
  85
  86static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  87{
  88	clear_bit(flag, bits);
  89}
  90
  91#define tg3_flag(tp, flag)				\
  92	_tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  93#define tg3_flag_set(tp, flag)				\
  94	_tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  95#define tg3_flag_clear(tp, flag)			\
  96	_tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  97
  98#define DRV_MODULE_NAME		"tg3"
  99/* DO NOT UPDATE TG3_*_NUM defines */
 100#define TG3_MAJ_NUM			3
 101#define TG3_MIN_NUM			137
 102
 103#define RESET_KIND_SHUTDOWN	0
 104#define RESET_KIND_INIT		1
 105#define RESET_KIND_SUSPEND	2
 106
 107#define TG3_DEF_RX_MODE		0
 108#define TG3_DEF_TX_MODE		0
 109#define TG3_DEF_MSG_ENABLE	  \
 110	(NETIF_MSG_DRV		| \
 111	 NETIF_MSG_PROBE	| \
 112	 NETIF_MSG_LINK		| \
 113	 NETIF_MSG_TIMER	| \
 114	 NETIF_MSG_IFDOWN	| \
 115	 NETIF_MSG_IFUP		| \
 116	 NETIF_MSG_RX_ERR	| \
 117	 NETIF_MSG_TX_ERR)
 118
 119#define TG3_GRC_LCLCTL_PWRSW_DELAY	100
 120
 121/* length of time before we decide the hardware is borked,
 122 * and dev->tx_timeout() should be called to fix the problem
 123 */
 124
 125#define TG3_TX_TIMEOUT			(5 * HZ)
 126
 127/* hardware minimum and maximum for a single frame's data payload */
 128#define TG3_MIN_MTU			ETH_ZLEN
 129#define TG3_MAX_MTU(tp)	\
 130	(tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
 131
 132/* These numbers seem to be hard coded in the NIC firmware somehow.
 133 * You can't change the ring sizes, but you can change where you place
 134 * them in the NIC onboard memory.
 135 */
 136#define TG3_RX_STD_RING_SIZE(tp) \
 137	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 138	 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 139#define TG3_DEF_RX_RING_PENDING		200
 140#define TG3_RX_JMB_RING_SIZE(tp) \
 141	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 142	 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 143#define TG3_DEF_RX_JUMBO_RING_PENDING	100
 144
 145/* Do not place this n-ring entries value into the tp struct itself,
 146 * we really want to expose these constants to GCC so that modulo et
 147 * al.  operations are done with shifts and masks instead of with
 148 * hw multiply/modulo instructions.  Another solution would be to
 149 * replace things like '% foo' with '& (foo - 1)'.
 150 */
 151
 152#define TG3_TX_RING_SIZE		512
 153#define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
 154
 155#define TG3_RX_STD_RING_BYTES(tp) \
 156	(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 157#define TG3_RX_JMB_RING_BYTES(tp) \
 158	(sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 159#define TG3_RX_RCB_RING_BYTES(tp) \
 160	(sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 161#define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
 162				 TG3_TX_RING_SIZE)
 163#define NEXT_TX(N)		(((N) + 1) & (TG3_TX_RING_SIZE - 1))
 164
 165#define TG3_DMA_BYTE_ENAB		64
 166
 167#define TG3_RX_STD_DMA_SZ		1536
 168#define TG3_RX_JMB_DMA_SZ		9046
 169
 170#define TG3_RX_DMA_TO_MAP_SZ(x)		((x) + TG3_DMA_BYTE_ENAB)
 171
 172#define TG3_RX_STD_MAP_SZ		TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 173#define TG3_RX_JMB_MAP_SZ		TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 174
 175#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 176	(sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 177
 178#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 179	(sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 180
 181/* Due to a hardware bug, the 5701 can only DMA to memory addresses
 182 * that are at least dword aligned when used in PCIX mode.  The driver
 183 * works around this bug by double copying the packet.  This workaround
 184 * is built into the normal double copy length check for efficiency.
 185 *
 186 * However, the double copy is only necessary on those architectures
 187 * where unaligned memory accesses are inefficient.  For those architectures
 188 * where unaligned memory accesses incur little penalty, we can reintegrate
 189 * the 5701 in the normal rx path.  Doing so saves a device structure
 190 * dereference by hardcoding the double copy threshold in place.
 191 */
 192#define TG3_RX_COPY_THRESHOLD		256
 193#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 194	#define TG3_RX_COPY_THRESH(tp)	TG3_RX_COPY_THRESHOLD
 195#else
 196	#define TG3_RX_COPY_THRESH(tp)	((tp)->rx_copy_thresh)
 197#endif
 198
 199#if (NET_IP_ALIGN != 0)
 200#define TG3_RX_OFFSET(tp)	((tp)->rx_offset)
 201#else
 202#define TG3_RX_OFFSET(tp)	(NET_SKB_PAD)
 203#endif
 204
 205/* minimum number of free TX descriptors required to wake up TX process */
 206#define TG3_TX_WAKEUP_THRESH(tnapi)		((tnapi)->tx_pending / 4)
 207#define TG3_TX_BD_DMA_MAX_2K		2048
 208#define TG3_TX_BD_DMA_MAX_4K		4096
 209
 210#define TG3_RAW_IP_ALIGN 2
 211
 212#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
 213#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
 214
 215#define TG3_FW_UPDATE_TIMEOUT_SEC	5
 216#define TG3_FW_UPDATE_FREQ_SEC		(TG3_FW_UPDATE_TIMEOUT_SEC / 2)
 217
 218#define FIRMWARE_TG3		"tigon/tg3.bin"
 219#define FIRMWARE_TG357766	"tigon/tg357766.bin"
 220#define FIRMWARE_TG3TSO		"tigon/tg3_tso.bin"
 221#define FIRMWARE_TG3TSO5	"tigon/tg3_tso5.bin"
 222
 223MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 224MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 225MODULE_LICENSE("GPL");
 226MODULE_FIRMWARE(FIRMWARE_TG3);
 227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 229
 230static int tg3_debug = -1;	/* -1 == use TG3_DEF_MSG_ENABLE as value */
 231module_param(tg3_debug, int, 0);
 232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 233
 234#define TG3_DRV_DATA_FLAG_10_100_ONLY	0x0001
 235#define TG3_DRV_DATA_FLAG_5705_10_100	0x0002
 236
 237static const struct pci_device_id tg3_pci_tbl[] = {
 238	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 239	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 240	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 241	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 242	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 243	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 244	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 245	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 246	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 247	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 248	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 249	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 250	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 251	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 252	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 253	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 254	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 255	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 256	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
 257	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 258			TG3_DRV_DATA_FLAG_5705_10_100},
 259	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
 260	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 261			TG3_DRV_DATA_FLAG_5705_10_100},
 262	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 263	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
 264	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 265			TG3_DRV_DATA_FLAG_5705_10_100},
 266	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 267	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 268	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 269	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 270	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 271	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
 272	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 273	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 274	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 275	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 276	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 277	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
 278	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 279	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 280	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 281	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 282	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 283	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 284	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 285	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 286	{PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
 287			PCI_VENDOR_ID_LENOVO,
 288			TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
 289	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 290	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 291	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
 292	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 293	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 294	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 295	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 296	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 297	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 298	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 299	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 300	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 301	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 302	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 303	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 304	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 305	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 306	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 307	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 308	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 309	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 310	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 311	{PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 312			PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
 313	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 314	{PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 315			PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
 316	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 317	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 318	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 319	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
 320	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 321	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 322	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 323	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
 324	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 325	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 326	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 327	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 328	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 329	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
 330	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 331	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
 332	 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 333	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 334	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 335	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
 336	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
 337	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
 338	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
 339	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
 340	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
 341	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
 342	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
 343	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
 344	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
 345	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 346	{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 347	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 348	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 349	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 350	{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 351	{PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 352	{PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
 353	{}
 354};
 355
 356MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 357
 358static const struct {
 359	const char string[ETH_GSTRING_LEN];
 360} ethtool_stats_keys[] = {
 361	{ "rx_octets" },
 362	{ "rx_fragments" },
 363	{ "rx_ucast_packets" },
 364	{ "rx_mcast_packets" },
 365	{ "rx_bcast_packets" },
 366	{ "rx_fcs_errors" },
 367	{ "rx_align_errors" },
 368	{ "rx_xon_pause_rcvd" },
 369	{ "rx_xoff_pause_rcvd" },
 370	{ "rx_mac_ctrl_rcvd" },
 371	{ "rx_xoff_entered" },
 372	{ "rx_frame_too_long_errors" },
 373	{ "rx_jabbers" },
 374	{ "rx_undersize_packets" },
 375	{ "rx_in_length_errors" },
 376	{ "rx_out_length_errors" },
 377	{ "rx_64_or_less_octet_packets" },
 378	{ "rx_65_to_127_octet_packets" },
 379	{ "rx_128_to_255_octet_packets" },
 380	{ "rx_256_to_511_octet_packets" },
 381	{ "rx_512_to_1023_octet_packets" },
 382	{ "rx_1024_to_1522_octet_packets" },
 383	{ "rx_1523_to_2047_octet_packets" },
 384	{ "rx_2048_to_4095_octet_packets" },
 385	{ "rx_4096_to_8191_octet_packets" },
 386	{ "rx_8192_to_9022_octet_packets" },
 387
 388	{ "tx_octets" },
 389	{ "tx_collisions" },
 390
 391	{ "tx_xon_sent" },
 392	{ "tx_xoff_sent" },
 393	{ "tx_flow_control" },
 394	{ "tx_mac_errors" },
 395	{ "tx_single_collisions" },
 396	{ "tx_mult_collisions" },
 397	{ "tx_deferred" },
 398	{ "tx_excessive_collisions" },
 399	{ "tx_late_collisions" },
 400	{ "tx_collide_2times" },
 401	{ "tx_collide_3times" },
 402	{ "tx_collide_4times" },
 403	{ "tx_collide_5times" },
 404	{ "tx_collide_6times" },
 405	{ "tx_collide_7times" },
 406	{ "tx_collide_8times" },
 407	{ "tx_collide_9times" },
 408	{ "tx_collide_10times" },
 409	{ "tx_collide_11times" },
 410	{ "tx_collide_12times" },
 411	{ "tx_collide_13times" },
 412	{ "tx_collide_14times" },
 413	{ "tx_collide_15times" },
 414	{ "tx_ucast_packets" },
 415	{ "tx_mcast_packets" },
 416	{ "tx_bcast_packets" },
 417	{ "tx_carrier_sense_errors" },
 418	{ "tx_discards" },
 419	{ "tx_errors" },
 420
 421	{ "dma_writeq_full" },
 422	{ "dma_write_prioq_full" },
 423	{ "rxbds_empty" },
 424	{ "rx_discards" },
 425	{ "rx_errors" },
 426	{ "rx_threshold_hit" },
 427
 428	{ "dma_readq_full" },
 429	{ "dma_read_prioq_full" },
 430	{ "tx_comp_queue_full" },
 431
 432	{ "ring_set_send_prod_index" },
 433	{ "ring_status_update" },
 434	{ "nic_irqs" },
 435	{ "nic_avoided_irqs" },
 436	{ "nic_tx_threshold_hit" },
 437
 438	{ "mbuf_lwm_thresh_hit" },
 439};
 440
 441#define TG3_NUM_STATS	ARRAY_SIZE(ethtool_stats_keys)
 442#define TG3_NVRAM_TEST		0
 443#define TG3_LINK_TEST		1
 444#define TG3_REGISTER_TEST	2
 445#define TG3_MEMORY_TEST		3
 446#define TG3_MAC_LOOPB_TEST	4
 447#define TG3_PHY_LOOPB_TEST	5
 448#define TG3_EXT_LOOPB_TEST	6
 449#define TG3_INTERRUPT_TEST	7
 450
 451
 452static const struct {
 453	const char string[ETH_GSTRING_LEN];
 454} ethtool_test_keys[] = {
 455	[TG3_NVRAM_TEST]	= { "nvram test        (online) " },
 456	[TG3_LINK_TEST]		= { "link test         (online) " },
 457	[TG3_REGISTER_TEST]	= { "register test     (offline)" },
 458	[TG3_MEMORY_TEST]	= { "memory test       (offline)" },
 459	[TG3_MAC_LOOPB_TEST]	= { "mac loopback test (offline)" },
 460	[TG3_PHY_LOOPB_TEST]	= { "phy loopback test (offline)" },
 461	[TG3_EXT_LOOPB_TEST]	= { "ext loopback test (offline)" },
 462	[TG3_INTERRUPT_TEST]	= { "interrupt test    (offline)" },
 463};
 464
 465#define TG3_NUM_TEST	ARRAY_SIZE(ethtool_test_keys)
 466
 467
 468static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 469{
 470	writel(val, tp->regs + off);
 471}
 472
 473static u32 tg3_read32(struct tg3 *tp, u32 off)
 474{
 475	return readl(tp->regs + off);
 476}
 477
 478static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 479{
 480	writel(val, tp->aperegs + off);
 481}
 482
 483static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 484{
 485	return readl(tp->aperegs + off);
 486}
 487
 488static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 489{
 490	unsigned long flags;
 491
 492	spin_lock_irqsave(&tp->indirect_lock, flags);
 493	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 494	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 495	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 496}
 497
 498static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 499{
 500	writel(val, tp->regs + off);
 501	readl(tp->regs + off);
 502}
 503
 504static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 505{
 506	unsigned long flags;
 507	u32 val;
 508
 509	spin_lock_irqsave(&tp->indirect_lock, flags);
 510	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 511	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 512	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 513	return val;
 514}
 515
 516static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 517{
 518	unsigned long flags;
 519
 520	if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 521		pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 522				       TG3_64BIT_REG_LOW, val);
 523		return;
 524	}
 525	if (off == TG3_RX_STD_PROD_IDX_REG) {
 526		pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 527				       TG3_64BIT_REG_LOW, val);
 528		return;
 529	}
 530
 531	spin_lock_irqsave(&tp->indirect_lock, flags);
 532	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 533	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 534	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535
 536	/* In indirect mode when disabling interrupts, we also need
 537	 * to clear the interrupt bit in the GRC local ctrl register.
 538	 */
 539	if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 540	    (val == 0x1)) {
 541		pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 542				       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 543	}
 544}
 545
 546static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 547{
 548	unsigned long flags;
 549	u32 val;
 550
 551	spin_lock_irqsave(&tp->indirect_lock, flags);
 552	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 553	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 554	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555	return val;
 556}
 557
 558/* usec_wait specifies the wait time in usec when writing to certain registers
 559 * where it is unsafe to read back the register without some delay.
 560 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 561 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 562 */
 563static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 564{
 565	if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
 566		/* Non-posted methods */
 567		tp->write32(tp, off, val);
 568	else {
 569		/* Posted method */
 570		tg3_write32(tp, off, val);
 571		if (usec_wait)
 572			udelay(usec_wait);
 573		tp->read32(tp, off);
 574	}
 575	/* Wait again after the read for the posted method to guarantee that
 576	 * the wait time is met.
 577	 */
 578	if (usec_wait)
 579		udelay(usec_wait);
 580}
 581
 582static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 583{
 584	tp->write32_mbox(tp, off, val);
 585	if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
 586	    (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
 587	     !tg3_flag(tp, ICH_WORKAROUND)))
 588		tp->read32_mbox(tp, off);
 589}
 590
 591static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 592{
 593	void __iomem *mbox = tp->regs + off;
 594	writel(val, mbox);
 595	if (tg3_flag(tp, TXD_MBOX_HWBUG))
 596		writel(val, mbox);
 597	if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
 598	    tg3_flag(tp, FLUSH_POSTED_WRITES))
 599		readl(mbox);
 600}
 601
 602static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 603{
 604	return readl(tp->regs + off + GRCMBOX_BASE);
 605}
 606
 607static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 608{
 609	writel(val, tp->regs + off + GRCMBOX_BASE);
 610}
 611
 612#define tw32_mailbox(reg, val)		tp->write32_mbox(tp, reg, val)
 613#define tw32_mailbox_f(reg, val)	tw32_mailbox_flush(tp, (reg), (val))
 614#define tw32_rx_mbox(reg, val)		tp->write32_rx_mbox(tp, reg, val)
 615#define tw32_tx_mbox(reg, val)		tp->write32_tx_mbox(tp, reg, val)
 616#define tr32_mailbox(reg)		tp->read32_mbox(tp, reg)
 617
 618#define tw32(reg, val)			tp->write32(tp, reg, val)
 619#define tw32_f(reg, val)		_tw32_flush(tp, (reg), (val), 0)
 620#define tw32_wait_f(reg, val, us)	_tw32_flush(tp, (reg), (val), (us))
 621#define tr32(reg)			tp->read32(tp, reg)
 622
 623static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 624{
 625	unsigned long flags;
 626
 627	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
 628	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 629		return;
 630
 631	spin_lock_irqsave(&tp->indirect_lock, flags);
 632	if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 633		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 634		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 635
 636		/* Always leave this as zero. */
 637		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 638	} else {
 639		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 640		tw32_f(TG3PCI_MEM_WIN_DATA, val);
 641
 642		/* Always leave this as zero. */
 643		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 644	}
 645	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 646}
 647
 648static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 649{
 650	unsigned long flags;
 651
 652	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
 653	    (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 654		*val = 0;
 655		return;
 656	}
 657
 658	spin_lock_irqsave(&tp->indirect_lock, flags);
 659	if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 660		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 661		pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 662
 663		/* Always leave this as zero. */
 664		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 665	} else {
 666		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 667		*val = tr32(TG3PCI_MEM_WIN_DATA);
 668
 669		/* Always leave this as zero. */
 670		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 671	}
 672	spin_unlock_irqrestore(&tp->indirect_lock, flags);
 673}
 674
 675static void tg3_ape_lock_init(struct tg3 *tp)
 676{
 677	int i;
 678	u32 regbase, bit;
 679
 680	if (tg3_asic_rev(tp) == ASIC_REV_5761)
 681		regbase = TG3_APE_LOCK_GRANT;
 682	else
 683		regbase = TG3_APE_PER_LOCK_GRANT;
 684
 685	/* Make sure the driver hasn't any stale locks. */
 686	for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
 687		switch (i) {
 688		case TG3_APE_LOCK_PHY0:
 689		case TG3_APE_LOCK_PHY1:
 690		case TG3_APE_LOCK_PHY2:
 691		case TG3_APE_LOCK_PHY3:
 692			bit = APE_LOCK_GRANT_DRIVER;
 693			break;
 694		default:
 695			if (!tp->pci_fn)
 696				bit = APE_LOCK_GRANT_DRIVER;
 697			else
 698				bit = 1 << tp->pci_fn;
 699		}
 700		tg3_ape_write32(tp, regbase + 4 * i, bit);
 701	}
 702
 703}
 704
 705static int tg3_ape_lock(struct tg3 *tp, int locknum)
 706{
 707	int i, off;
 708	int ret = 0;
 709	u32 status, req, gnt, bit;
 710
 711	if (!tg3_flag(tp, ENABLE_APE))
 712		return 0;
 713
 714	switch (locknum) {
 715	case TG3_APE_LOCK_GPIO:
 716		if (tg3_asic_rev(tp) == ASIC_REV_5761)
 717			return 0;
 718		/* fall through */
 719	case TG3_APE_LOCK_GRC:
 720	case TG3_APE_LOCK_MEM:
 721		if (!tp->pci_fn)
 722			bit = APE_LOCK_REQ_DRIVER;
 723		else
 724			bit = 1 << tp->pci_fn;
 725		break;
 726	case TG3_APE_LOCK_PHY0:
 727	case TG3_APE_LOCK_PHY1:
 728	case TG3_APE_LOCK_PHY2:
 729	case TG3_APE_LOCK_PHY3:
 730		bit = APE_LOCK_REQ_DRIVER;
 731		break;
 732	default:
 733		return -EINVAL;
 734	}
 735
 736	if (tg3_asic_rev(tp) == ASIC_REV_5761) {
 737		req = TG3_APE_LOCK_REQ;
 738		gnt = TG3_APE_LOCK_GRANT;
 739	} else {
 740		req = TG3_APE_PER_LOCK_REQ;
 741		gnt = TG3_APE_PER_LOCK_GRANT;
 742	}
 743
 744	off = 4 * locknum;
 745
 746	tg3_ape_write32(tp, req + off, bit);
 747
 748	/* Wait for up to 1 millisecond to acquire lock. */
 749	for (i = 0; i < 100; i++) {
 750		status = tg3_ape_read32(tp, gnt + off);
 751		if (status == bit)
 752			break;
 753		if (pci_channel_offline(tp->pdev))
 754			break;
 755
 756		udelay(10);
 757	}
 758
 759	if (status != bit) {
 760		/* Revoke the lock request. */
 761		tg3_ape_write32(tp, gnt + off, bit);
 762		ret = -EBUSY;
 763	}
 764
 765	return ret;
 766}
 767
 768static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 769{
 770	u32 gnt, bit;
 771
 772	if (!tg3_flag(tp, ENABLE_APE))
 773		return;
 774
 775	switch (locknum) {
 776	case TG3_APE_LOCK_GPIO:
 777		if (tg3_asic_rev(tp) == ASIC_REV_5761)
 778			return;
 779		/* fall through */
 780	case TG3_APE_LOCK_GRC:
 781	case TG3_APE_LOCK_MEM:
 782		if (!tp->pci_fn)
 783			bit = APE_LOCK_GRANT_DRIVER;
 784		else
 785			bit = 1 << tp->pci_fn;
 786		break;
 787	case TG3_APE_LOCK_PHY0:
 788	case TG3_APE_LOCK_PHY1:
 789	case TG3_APE_LOCK_PHY2:
 790	case TG3_APE_LOCK_PHY3:
 791		bit = APE_LOCK_GRANT_DRIVER;
 792		break;
 793	default:
 794		return;
 795	}
 796
 797	if (tg3_asic_rev(tp) == ASIC_REV_5761)
 798		gnt = TG3_APE_LOCK_GRANT;
 799	else
 800		gnt = TG3_APE_PER_LOCK_GRANT;
 801
 802	tg3_ape_write32(tp, gnt + 4 * locknum, bit);
 803}
 804
 805static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
 806{
 807	u32 apedata;
 808
 809	while (timeout_us) {
 810		if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
 811			return -EBUSY;
 812
 813		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 814		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 815			break;
 816
 817		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 818
 819		udelay(10);
 820		timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
 821	}
 822
 823	return timeout_us ? 0 : -EBUSY;
 824}
 825
 826#ifdef CONFIG_TIGON3_HWMON
 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
 828{
 829	u32 i, apedata;
 830
 831	for (i = 0; i < timeout_us / 10; i++) {
 832		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 833
 834		if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 835			break;
 836
 837		udelay(10);
 838	}
 839
 840	return i == timeout_us / 10;
 841}
 842
 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
 844				   u32 len)
 845{
 846	int err;
 847	u32 i, bufoff, msgoff, maxlen, apedata;
 848
 849	if (!tg3_flag(tp, APE_HAS_NCSI))
 850		return 0;
 851
 852	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 853	if (apedata != APE_SEG_SIG_MAGIC)
 854		return -ENODEV;
 855
 856	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 857	if (!(apedata & APE_FW_STATUS_READY))
 858		return -EAGAIN;
 859
 860	bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
 861		 TG3_APE_SHMEM_BASE;
 862	msgoff = bufoff + 2 * sizeof(u32);
 863	maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
 864
 865	while (len) {
 866		u32 length;
 867
 868		/* Cap xfer sizes to scratchpad limits. */
 869		length = (len > maxlen) ? maxlen : len;
 870		len -= length;
 871
 872		apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 873		if (!(apedata & APE_FW_STATUS_READY))
 874			return -EAGAIN;
 875
 876		/* Wait for up to 1 msec for APE to service previous event. */
 877		err = tg3_ape_event_lock(tp, 1000);
 878		if (err)
 879			return err;
 880
 881		apedata = APE_EVENT_STATUS_DRIVER_EVNT |
 882			  APE_EVENT_STATUS_SCRTCHPD_READ |
 883			  APE_EVENT_STATUS_EVENT_PENDING;
 884		tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
 885
 886		tg3_ape_write32(tp, bufoff, base_off);
 887		tg3_ape_write32(tp, bufoff + sizeof(u32), length);
 888
 889		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 890		tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 891
 892		base_off += length;
 893
 894		if (tg3_ape_wait_for_event(tp, 30000))
 895			return -EAGAIN;
 896
 897		for (i = 0; length; i += 4, length -= 4) {
 898			u32 val = tg3_ape_read32(tp, msgoff + i);
 899			memcpy(data, &val, sizeof(u32));
 900			data++;
 901		}
 902	}
 903
 904	return 0;
 905}
 906#endif
 907
 908static int tg3_ape_send_event(struct tg3 *tp, u32 event)
 909{
 910	int err;
 911	u32 apedata;
 912
 913	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 914	if (apedata != APE_SEG_SIG_MAGIC)
 915		return -EAGAIN;
 916
 917	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 918	if (!(apedata & APE_FW_STATUS_READY))
 919		return -EAGAIN;
 920
 921	/* Wait for up to 20 millisecond for APE to service previous event. */
 922	err = tg3_ape_event_lock(tp, 20000);
 923	if (err)
 924		return err;
 925
 926	tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
 927			event | APE_EVENT_STATUS_EVENT_PENDING);
 928
 929	tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 930	tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 931
 932	return 0;
 933}
 934
 935static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
 936{
 937	u32 event;
 938	u32 apedata;
 939
 940	if (!tg3_flag(tp, ENABLE_APE))
 941		return;
 942
 943	switch (kind) {
 944	case RESET_KIND_INIT:
 945		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
 946		tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
 947				APE_HOST_SEG_SIG_MAGIC);
 948		tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
 949				APE_HOST_SEG_LEN_MAGIC);
 950		apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
 951		tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
 952		tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
 953			APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
 954		tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
 955				APE_HOST_BEHAV_NO_PHYLOCK);
 956		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
 957				    TG3_APE_HOST_DRVR_STATE_START);
 958
 959		event = APE_EVENT_STATUS_STATE_START;
 960		break;
 961	case RESET_KIND_SHUTDOWN:
 962		if (device_may_wakeup(&tp->pdev->dev) &&
 963		    tg3_flag(tp, WOL_ENABLE)) {
 964			tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
 965					    TG3_APE_HOST_WOL_SPEED_AUTO);
 966			apedata = TG3_APE_HOST_DRVR_STATE_WOL;
 967		} else
 968			apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
 969
 970		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
 971
 972		event = APE_EVENT_STATUS_STATE_UNLOAD;
 973		break;
 974	default:
 975		return;
 976	}
 977
 978	event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
 979
 980	tg3_ape_send_event(tp, event);
 981}
 982
 983static void tg3_send_ape_heartbeat(struct tg3 *tp,
 984				   unsigned long interval)
 985{
 986	/* Check if hb interval has exceeded */
 987	if (!tg3_flag(tp, ENABLE_APE) ||
 988	    time_before(jiffies, tp->ape_hb_jiffies + interval))
 989		return;
 990
 991	tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
 992	tp->ape_hb_jiffies = jiffies;
 993}
 994
 995static void tg3_disable_ints(struct tg3 *tp)
 996{
 997	int i;
 998
 999	tw32(TG3PCI_MISC_HOST_CTRL,
1000	     (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1001	for (i = 0; i < tp->irq_max; i++)
1002		tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1003}
1004
1005static void tg3_enable_ints(struct tg3 *tp)
1006{
1007	int i;
1008
1009	tp->irq_sync = 0;
1010	wmb();
1011
1012	tw32(TG3PCI_MISC_HOST_CTRL,
1013	     (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1014
1015	tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1016	for (i = 0; i < tp->irq_cnt; i++) {
1017		struct tg3_napi *tnapi = &tp->napi[i];
1018
1019		tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1020		if (tg3_flag(tp, 1SHOT_MSI))
1021			tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1022
1023		tp->coal_now |= tnapi->coal_now;
1024	}
1025
1026	/* Force an initial interrupt */
1027	if (!tg3_flag(tp, TAGGED_STATUS) &&
1028	    (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1029		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1030	else
1031		tw32(HOSTCC_MODE, tp->coal_now);
1032
1033	tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1034}
1035
1036static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1037{
1038	struct tg3 *tp = tnapi->tp;
1039	struct tg3_hw_status *sblk = tnapi->hw_status;
1040	unsigned int work_exists = 0;
1041
1042	/* check for phy events */
1043	if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1044		if (sblk->status & SD_STATUS_LINK_CHG)
1045			work_exists = 1;
1046	}
1047
1048	/* check for TX work to do */
1049	if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1050		work_exists = 1;
1051
1052	/* check for RX work to do */
1053	if (tnapi->rx_rcb_prod_idx &&
1054	    *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1055		work_exists = 1;
1056
1057	return work_exists;
1058}
1059
1060/* tg3_int_reenable
1061 *  similar to tg3_enable_ints, but it accurately determines whether there
1062 *  is new work pending and can return without flushing the PIO write
1063 *  which reenables interrupts
1064 */
1065static void tg3_int_reenable(struct tg3_napi *tnapi)
1066{
1067	struct tg3 *tp = tnapi->tp;
1068
1069	tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1070
1071	/* When doing tagged status, this work check is unnecessary.
1072	 * The last_tag we write above tells the chip which piece of
1073	 * work we've completed.
1074	 */
1075	if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1076		tw32(HOSTCC_MODE, tp->coalesce_mode |
1077		     HOSTCC_MODE_ENABLE | tnapi->coal_now);
1078}
1079
1080static void tg3_switch_clocks(struct tg3 *tp)
1081{
1082	u32 clock_ctrl;
1083	u32 orig_clock_ctrl;
1084
1085	if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1086		return;
1087
1088	clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1089
1090	orig_clock_ctrl = clock_ctrl;
1091	clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1092		       CLOCK_CTRL_CLKRUN_OENABLE |
1093		       0x1f);
1094	tp->pci_clock_ctrl = clock_ctrl;
1095
1096	if (tg3_flag(tp, 5705_PLUS)) {
1097		if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1098			tw32_wait_f(TG3PCI_CLOCK_CTRL,
1099				    clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1100		}
1101	} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1102		tw32_wait_f(TG3PCI_CLOCK_CTRL,
1103			    clock_ctrl |
1104			    (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1105			    40);
1106		tw32_wait_f(TG3PCI_CLOCK_CTRL,
1107			    clock_ctrl | (CLOCK_CTRL_ALTCLK),
1108			    40);
1109	}
1110	tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1111}
1112
1113#define PHY_BUSY_LOOPS	5000
1114
1115static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116			 u32 *val)
1117{
1118	u32 frame_val;
1119	unsigned int loops;
1120	int ret;
1121
1122	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1123		tw32_f(MAC_MI_MODE,
1124		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1125		udelay(80);
1126	}
1127
1128	tg3_ape_lock(tp, tp->phy_ape_lock);
1129
1130	*val = 0x0;
1131
1132	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1133		      MI_COM_PHY_ADDR_MASK);
1134	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1135		      MI_COM_REG_ADDR_MASK);
1136	frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1137
1138	tw32_f(MAC_MI_COM, frame_val);
1139
1140	loops = PHY_BUSY_LOOPS;
1141	while (loops != 0) {
1142		udelay(10);
1143		frame_val = tr32(MAC_MI_COM);
1144
1145		if ((frame_val & MI_COM_BUSY) == 0) {
1146			udelay(5);
1147			frame_val = tr32(MAC_MI_COM);
1148			break;
1149		}
1150		loops -= 1;
1151	}
1152
1153	ret = -EBUSY;
1154	if (loops != 0) {
1155		*val = frame_val & MI_COM_DATA_MASK;
1156		ret = 0;
1157	}
1158
1159	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1160		tw32_f(MAC_MI_MODE, tp->mi_mode);
1161		udelay(80);
1162	}
1163
1164	tg3_ape_unlock(tp, tp->phy_ape_lock);
1165
1166	return ret;
1167}
1168
1169static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1170{
1171	return __tg3_readphy(tp, tp->phy_addr, reg, val);
1172}
1173
1174static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175			  u32 val)
1176{
1177	u32 frame_val;
1178	unsigned int loops;
1179	int ret;
1180
1181	if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1182	    (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1183		return 0;
1184
1185	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1186		tw32_f(MAC_MI_MODE,
1187		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1188		udelay(80);
1189	}
1190
1191	tg3_ape_lock(tp, tp->phy_ape_lock);
1192
1193	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1194		      MI_COM_PHY_ADDR_MASK);
1195	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1196		      MI_COM_REG_ADDR_MASK);
1197	frame_val |= (val & MI_COM_DATA_MASK);
1198	frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1199
1200	tw32_f(MAC_MI_COM, frame_val);
1201
1202	loops = PHY_BUSY_LOOPS;
1203	while (loops != 0) {
1204		udelay(10);
1205		frame_val = tr32(MAC_MI_COM);
1206		if ((frame_val & MI_COM_BUSY) == 0) {
1207			udelay(5);
1208			frame_val = tr32(MAC_MI_COM);
1209			break;
1210		}
1211		loops -= 1;
1212	}
1213
1214	ret = -EBUSY;
1215	if (loops != 0)
1216		ret = 0;
1217
1218	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1219		tw32_f(MAC_MI_MODE, tp->mi_mode);
1220		udelay(80);
1221	}
1222
1223	tg3_ape_unlock(tp, tp->phy_ape_lock);
1224
1225	return ret;
1226}
1227
1228static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1229{
1230	return __tg3_writephy(tp, tp->phy_addr, reg, val);
1231}
1232
1233static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1234{
1235	int err;
1236
1237	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1238	if (err)
1239		goto done;
1240
1241	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1242	if (err)
1243		goto done;
1244
1245	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1246			   MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1247	if (err)
1248		goto done;
1249
1250	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1251
1252done:
1253	return err;
1254}
1255
1256static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1257{
1258	int err;
1259
1260	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1261	if (err)
1262		goto done;
1263
1264	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1265	if (err)
1266		goto done;
1267
1268	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1269			   MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1270	if (err)
1271		goto done;
1272
1273	err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1274
1275done:
1276	return err;
1277}
1278
1279static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1280{
1281	int err;
1282
1283	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1284	if (!err)
1285		err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1286
1287	return err;
1288}
1289
1290static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1291{
1292	int err;
1293
1294	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1295	if (!err)
1296		err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1297
1298	return err;
1299}
1300
1301static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1302{
1303	int err;
1304
1305	err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1306			   (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1307			   MII_TG3_AUXCTL_SHDWSEL_MISC);
1308	if (!err)
1309		err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1310
1311	return err;
1312}
1313
1314static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1315{
1316	if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1317		set |= MII_TG3_AUXCTL_MISC_WREN;
1318
1319	return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1320}
1321
1322static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1323{
1324	u32 val;
1325	int err;
1326
1327	err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1328
1329	if (err)
1330		return err;
1331
1332	if (enable)
1333		val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1334	else
1335		val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1336
1337	err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1338				   val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1339
1340	return err;
1341}
1342
1343static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1344{
1345	return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1346			    reg | val | MII_TG3_MISC_SHDW_WREN);
1347}
1348
1349static int tg3_bmcr_reset(struct tg3 *tp)
1350{
1351	u32 phy_control;
1352	int limit, err;
1353
1354	/* OK, reset it, and poll the BMCR_RESET bit until it
1355	 * clears or we time out.
1356	 */
1357	phy_control = BMCR_RESET;
1358	err = tg3_writephy(tp, MII_BMCR, phy_control);
1359	if (err != 0)
1360		return -EBUSY;
1361
1362	limit = 5000;
1363	while (limit--) {
1364		err = tg3_readphy(tp, MII_BMCR, &phy_control);
1365		if (err != 0)
1366			return -EBUSY;
1367
1368		if ((phy_control & BMCR_RESET) == 0) {
1369			udelay(40);
1370			break;
1371		}
1372		udelay(10);
1373	}
1374	if (limit < 0)
1375		return -EBUSY;
1376
1377	return 0;
1378}
1379
1380static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1381{
1382	struct tg3 *tp = bp->priv;
1383	u32 val;
1384
1385	spin_lock_bh(&tp->lock);
1386
1387	if (__tg3_readphy(tp, mii_id, reg, &val))
1388		val = -EIO;
1389
1390	spin_unlock_bh(&tp->lock);
1391
1392	return val;
1393}
1394
1395static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1396{
1397	struct tg3 *tp = bp->priv;
1398	u32 ret = 0;
1399
1400	spin_lock_bh(&tp->lock);
1401
1402	if (__tg3_writephy(tp, mii_id, reg, val))
1403		ret = -EIO;
1404
1405	spin_unlock_bh(&tp->lock);
1406
1407	return ret;
1408}
1409
1410static void tg3_mdio_config_5785(struct tg3 *tp)
1411{
1412	u32 val;
1413	struct phy_device *phydev;
1414
1415	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1416	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1417	case PHY_ID_BCM50610:
1418	case PHY_ID_BCM50610M:
1419		val = MAC_PHYCFG2_50610_LED_MODES;
1420		break;
1421	case PHY_ID_BCMAC131:
1422		val = MAC_PHYCFG2_AC131_LED_MODES;
1423		break;
1424	case PHY_ID_RTL8211C:
1425		val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1426		break;
1427	case PHY_ID_RTL8201E:
1428		val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1429		break;
1430	default:
1431		return;
1432	}
1433
1434	if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1435		tw32(MAC_PHYCFG2, val);
1436
1437		val = tr32(MAC_PHYCFG1);
1438		val &= ~(MAC_PHYCFG1_RGMII_INT |
1439			 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1440		val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1441		tw32(MAC_PHYCFG1, val);
1442
1443		return;
1444	}
1445
1446	if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1447		val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1448		       MAC_PHYCFG2_FMODE_MASK_MASK |
1449		       MAC_PHYCFG2_GMODE_MASK_MASK |
1450		       MAC_PHYCFG2_ACT_MASK_MASK   |
1451		       MAC_PHYCFG2_QUAL_MASK_MASK |
1452		       MAC_PHYCFG2_INBAND_ENABLE;
1453
1454	tw32(MAC_PHYCFG2, val);
1455
1456	val = tr32(MAC_PHYCFG1);
1457	val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1458		 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1459	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1460		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1461			val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1462		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1463			val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1464	}
1465	val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1466	       MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1467	tw32(MAC_PHYCFG1, val);
1468
1469	val = tr32(MAC_EXT_RGMII_MODE);
1470	val &= ~(MAC_RGMII_MODE_RX_INT_B |
1471		 MAC_RGMII_MODE_RX_QUALITY |
1472		 MAC_RGMII_MODE_RX_ACTIVITY |
1473		 MAC_RGMII_MODE_RX_ENG_DET |
1474		 MAC_RGMII_MODE_TX_ENABLE |
1475		 MAC_RGMII_MODE_TX_LOWPWR |
1476		 MAC_RGMII_MODE_TX_RESET);
1477	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1478		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1479			val |= MAC_RGMII_MODE_RX_INT_B |
1480			       MAC_RGMII_MODE_RX_QUALITY |
1481			       MAC_RGMII_MODE_RX_ACTIVITY |
1482			       MAC_RGMII_MODE_RX_ENG_DET;
1483		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1484			val |= MAC_RGMII_MODE_TX_ENABLE |
1485			       MAC_RGMII_MODE_TX_LOWPWR |
1486			       MAC_RGMII_MODE_TX_RESET;
1487	}
1488	tw32(MAC_EXT_RGMII_MODE, val);
1489}
1490
1491static void tg3_mdio_start(struct tg3 *tp)
1492{
1493	tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1494	tw32_f(MAC_MI_MODE, tp->mi_mode);
1495	udelay(80);
1496
1497	if (tg3_flag(tp, MDIOBUS_INITED) &&
1498	    tg3_asic_rev(tp) == ASIC_REV_5785)
1499		tg3_mdio_config_5785(tp);
1500}
1501
1502static int tg3_mdio_init(struct tg3 *tp)
1503{
1504	int i;
1505	u32 reg;
1506	struct phy_device *phydev;
1507
1508	if (tg3_flag(tp, 5717_PLUS)) {
1509		u32 is_serdes;
1510
1511		tp->phy_addr = tp->pci_fn + 1;
1512
1513		if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1514			is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1515		else
1516			is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1517				    TG3_CPMU_PHY_STRAP_IS_SERDES;
1518		if (is_serdes)
1519			tp->phy_addr += 7;
1520	} else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1521		int addr;
1522
1523		addr = ssb_gige_get_phyaddr(tp->pdev);
1524		if (addr < 0)
1525			return addr;
1526		tp->phy_addr = addr;
1527	} else
1528		tp->phy_addr = TG3_PHY_MII_ADDR;
1529
1530	tg3_mdio_start(tp);
1531
1532	if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1533		return 0;
1534
1535	tp->mdio_bus = mdiobus_alloc();
1536	if (tp->mdio_bus == NULL)
1537		return -ENOMEM;
1538
1539	tp->mdio_bus->name     = "tg3 mdio bus";
1540	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1541		 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1542	tp->mdio_bus->priv     = tp;
1543	tp->mdio_bus->parent   = &tp->pdev->dev;
1544	tp->mdio_bus->read     = &tg3_mdio_read;
1545	tp->mdio_bus->write    = &tg3_mdio_write;
1546	tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1547
1548	/* The bus registration will look for all the PHYs on the mdio bus.
1549	 * Unfortunately, it does not ensure the PHY is powered up before
1550	 * accessing the PHY ID registers.  A chip reset is the
1551	 * quickest way to bring the device back to an operational state..
1552	 */
1553	if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1554		tg3_bmcr_reset(tp);
1555
1556	i = mdiobus_register(tp->mdio_bus);
1557	if (i) {
1558		dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1559		mdiobus_free(tp->mdio_bus);
1560		return i;
1561	}
1562
1563	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1564
1565	if (!phydev || !phydev->drv) {
1566		dev_warn(&tp->pdev->dev, "No PHY devices\n");
1567		mdiobus_unregister(tp->mdio_bus);
1568		mdiobus_free(tp->mdio_bus);
1569		return -ENODEV;
1570	}
1571
1572	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1573	case PHY_ID_BCM57780:
1574		phydev->interface = PHY_INTERFACE_MODE_GMII;
1575		phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1576		break;
1577	case PHY_ID_BCM50610:
1578	case PHY_ID_BCM50610M:
1579		phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1580				     PHY_BRCM_RX_REFCLK_UNUSED |
1581				     PHY_BRCM_DIS_TXCRXC_NOENRGY |
1582				     PHY_BRCM_AUTO_PWRDWN_ENABLE;
1583		if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1584			phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1585		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1586			phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1587		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1588			phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1589		/* fall through */
1590	case PHY_ID_RTL8211C:
1591		phydev->interface = PHY_INTERFACE_MODE_RGMII;
1592		break;
1593	case PHY_ID_RTL8201E:
1594	case PHY_ID_BCMAC131:
1595		phydev->interface = PHY_INTERFACE_MODE_MII;
1596		phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1597		tp->phy_flags |= TG3_PHYFLG_IS_FET;
1598		break;
1599	}
1600
1601	tg3_flag_set(tp, MDIOBUS_INITED);
1602
1603	if (tg3_asic_rev(tp) == ASIC_REV_5785)
1604		tg3_mdio_config_5785(tp);
1605
1606	return 0;
1607}
1608
1609static void tg3_mdio_fini(struct tg3 *tp)
1610{
1611	if (tg3_flag(tp, MDIOBUS_INITED)) {
1612		tg3_flag_clear(tp, MDIOBUS_INITED);
1613		mdiobus_unregister(tp->mdio_bus);
1614		mdiobus_free(tp->mdio_bus);
1615	}
1616}
1617
1618/* tp->lock is held. */
1619static inline void tg3_generate_fw_event(struct tg3 *tp)
1620{
1621	u32 val;
1622
1623	val = tr32(GRC_RX_CPU_EVENT);
1624	val |= GRC_RX_CPU_DRIVER_EVENT;
1625	tw32_f(GRC_RX_CPU_EVENT, val);
1626
1627	tp->last_event_jiffies = jiffies;
1628}
1629
1630#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1631
1632/* tp->lock is held. */
1633static void tg3_wait_for_event_ack(struct tg3 *tp)
1634{
1635	int i;
1636	unsigned int delay_cnt;
1637	long time_remain;
1638
1639	/* If enough time has passed, no wait is necessary. */
1640	time_remain = (long)(tp->last_event_jiffies + 1 +
1641		      usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1642		      (long)jiffies;
1643	if (time_remain < 0)
1644		return;
1645
1646	/* Check if we can shorten the wait time. */
1647	delay_cnt = jiffies_to_usecs(time_remain);
1648	if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1649		delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1650	delay_cnt = (delay_cnt >> 3) + 1;
1651
1652	for (i = 0; i < delay_cnt; i++) {
1653		if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1654			break;
1655		if (pci_channel_offline(tp->pdev))
1656			break;
1657
1658		udelay(8);
1659	}
1660}
1661
1662/* tp->lock is held. */
1663static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1664{
1665	u32 reg, val;
1666
1667	val = 0;
1668	if (!tg3_readphy(tp, MII_BMCR, &reg))
1669		val = reg << 16;
1670	if (!tg3_readphy(tp, MII_BMSR, &reg))
1671		val |= (reg & 0xffff);
1672	*data++ = val;
1673
1674	val = 0;
1675	if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1676		val = reg << 16;
1677	if (!tg3_readphy(tp, MII_LPA, &reg))
1678		val |= (reg & 0xffff);
1679	*data++ = val;
1680
1681	val = 0;
1682	if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1683		if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1684			val = reg << 16;
1685		if (!tg3_readphy(tp, MII_STAT1000, &reg))
1686			val |= (reg & 0xffff);
1687	}
1688	*data++ = val;
1689
1690	if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1691		val = reg << 16;
1692	else
1693		val = 0;
1694	*data++ = val;
1695}
1696
1697/* tp->lock is held. */
1698static void tg3_ump_link_report(struct tg3 *tp)
1699{
1700	u32 data[4];
1701
1702	if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703		return;
1704
1705	tg3_phy_gather_ump_data(tp, data);
1706
1707	tg3_wait_for_event_ack(tp);
1708
1709	tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1710	tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1711	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1712	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1713	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1714	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1715
1716	tg3_generate_fw_event(tp);
1717}
1718
1719/* tp->lock is held. */
1720static void tg3_stop_fw(struct tg3 *tp)
1721{
1722	if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1723		/* Wait for RX cpu to ACK the previous event. */
1724		tg3_wait_for_event_ack(tp);
1725
1726		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1727
1728		tg3_generate_fw_event(tp);
1729
1730		/* Wait for RX cpu to ACK this event. */
1731		tg3_wait_for_event_ack(tp);
1732	}
1733}
1734
1735/* tp->lock is held. */
1736static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1737{
1738	tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1739		      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1740
1741	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1742		switch (kind) {
1743		case RESET_KIND_INIT:
1744			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1745				      DRV_STATE_START);
1746			break;
1747
1748		case RESET_KIND_SHUTDOWN:
1749			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1750				      DRV_STATE_UNLOAD);
1751			break;
1752
1753		case RESET_KIND_SUSPEND:
1754			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1755				      DRV_STATE_SUSPEND);
1756			break;
1757
1758		default:
1759			break;
1760		}
1761	}
1762}
1763
1764/* tp->lock is held. */
1765static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1766{
1767	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1768		switch (kind) {
1769		case RESET_KIND_INIT:
1770			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1771				      DRV_STATE_START_DONE);
1772			break;
1773
1774		case RESET_KIND_SHUTDOWN:
1775			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1776				      DRV_STATE_UNLOAD_DONE);
1777			break;
1778
1779		default:
1780			break;
1781		}
1782	}
1783}
1784
1785/* tp->lock is held. */
1786static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1787{
1788	if (tg3_flag(tp, ENABLE_ASF)) {
1789		switch (kind) {
1790		case RESET_KIND_INIT:
1791			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1792				      DRV_STATE_START);
1793			break;
1794
1795		case RESET_KIND_SHUTDOWN:
1796			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1797				      DRV_STATE_UNLOAD);
1798			break;
1799
1800		case RESET_KIND_SUSPEND:
1801			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1802				      DRV_STATE_SUSPEND);
1803			break;
1804
1805		default:
1806			break;
1807		}
1808	}
1809}
1810
1811static int tg3_poll_fw(struct tg3 *tp)
1812{
1813	int i;
1814	u32 val;
1815
1816	if (tg3_flag(tp, NO_FWARE_REPORTED))
1817		return 0;
1818
1819	if (tg3_flag(tp, IS_SSB_CORE)) {
1820		/* We don'…

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