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/drivers/atm/idt77252.c

https://bitbucket.org/evzijst/gittest
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   1/******************************************************************* 
   2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
   3 *
   4 * $Author: ecd $
   5 * $Date: 2001/11/11 08:13:54 $
   6 *
   7 * Copyright (c) 2000 ATecoM GmbH 
   8 *
   9 * The author may be reached at ecd@atecom.com.
  10 *
  11 * This program is free software; you can redistribute  it and/or modify it
  12 * under  the terms of  the GNU General  Public License as published by the
  13 * Free Software Foundation;  either version 2 of the  License, or (at your
  14 * option) any later version.
  15 *
  16 * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
  17 * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19 * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
  20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21 * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22 * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23 * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 *
  27 * You should have received a copy of the  GNU General Public License along
  28 * with this program; if not, write  to the Free Software Foundation, Inc.,
  29 * 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 *******************************************************************/
  32static char const rcsid[] =
  33"$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
  34
  35
  36#include <linux/module.h>
  37#include <linux/config.h>
  38#include <linux/pci.h>
  39#include <linux/skbuff.h>
  40#include <linux/kernel.h>
  41#include <linux/vmalloc.h>
  42#include <linux/netdevice.h>
  43#include <linux/atmdev.h>
  44#include <linux/atm.h>
  45#include <linux/delay.h>
  46#include <linux/init.h>
  47#include <linux/bitops.h>
  48#include <linux/wait.h>
  49#include <asm/semaphore.h>
  50#include <asm/io.h>
  51#include <asm/uaccess.h>
  52#include <asm/atomic.h>
  53#include <asm/byteorder.h>
  54
  55#ifdef CONFIG_ATM_IDT77252_USE_SUNI
  56#include "suni.h"
  57#endif /* CONFIG_ATM_IDT77252_USE_SUNI */
  58
  59
  60#include "idt77252.h"
  61#include "idt77252_tables.h"
  62
  63static unsigned int vpibits = 1;
  64
  65
  66#define CONFIG_ATM_IDT77252_SEND_IDLE 1
  67
  68
  69/*
  70 * Debug HACKs.
  71 */
  72#define DEBUG_MODULE 1
  73#undef HAVE_EEPROM	/* does not work, yet. */
  74
  75#ifdef CONFIG_ATM_IDT77252_DEBUG
  76static unsigned long debug = DBG_GENERAL;
  77#endif
  78
  79
  80#define SAR_RX_DELAY	(SAR_CFG_RXINT_NODELAY)
  81
  82
  83/*
  84 * SCQ Handling.
  85 */
  86static struct scq_info *alloc_scq(struct idt77252_dev *, int);
  87static void free_scq(struct idt77252_dev *, struct scq_info *);
  88static int queue_skb(struct idt77252_dev *, struct vc_map *,
  89		     struct sk_buff *, int oam);
  90static void drain_scq(struct idt77252_dev *, struct vc_map *);
  91static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
  92static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
  93
  94/*
  95 * FBQ Handling.
  96 */
  97static int push_rx_skb(struct idt77252_dev *,
  98		       struct sk_buff *, int queue);
  99static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
 100static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
 101static void recycle_rx_pool_skb(struct idt77252_dev *,
 102				struct rx_pool *);
 103static void add_rx_skb(struct idt77252_dev *, int queue,
 104		       unsigned int size, unsigned int count);
 105
 106/*
 107 * RSQ Handling.
 108 */
 109static int init_rsq(struct idt77252_dev *);
 110static void deinit_rsq(struct idt77252_dev *);
 111static void idt77252_rx(struct idt77252_dev *);
 112
 113/*
 114 * TSQ handling.
 115 */
 116static int init_tsq(struct idt77252_dev *);
 117static void deinit_tsq(struct idt77252_dev *);
 118static void idt77252_tx(struct idt77252_dev *);
 119
 120
 121/*
 122 * ATM Interface.
 123 */
 124static void idt77252_dev_close(struct atm_dev *dev);
 125static int idt77252_open(struct atm_vcc *vcc);
 126static void idt77252_close(struct atm_vcc *vcc);
 127static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
 128static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
 129			     int flags);
 130static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
 131			     unsigned long addr);
 132static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
 133static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
 134			       int flags);
 135static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
 136			      char *page);
 137static void idt77252_softint(void *dev_id);
 138
 139
 140static struct atmdev_ops idt77252_ops =
 141{
 142	.dev_close	= idt77252_dev_close,
 143	.open		= idt77252_open,
 144	.close		= idt77252_close,
 145	.send		= idt77252_send,
 146	.send_oam	= idt77252_send_oam,
 147	.phy_put	= idt77252_phy_put,
 148	.phy_get	= idt77252_phy_get,
 149	.change_qos	= idt77252_change_qos,
 150	.proc_read	= idt77252_proc_read,
 151	.owner		= THIS_MODULE
 152};
 153
 154static struct idt77252_dev *idt77252_chain = NULL;
 155static unsigned int idt77252_sram_write_errors = 0;
 156
 157/*****************************************************************************/
 158/*                                                                           */
 159/* I/O and Utility Bus                                                       */
 160/*                                                                           */
 161/*****************************************************************************/
 162
 163static void
 164waitfor_idle(struct idt77252_dev *card)
 165{
 166	u32 stat;
 167
 168	stat = readl(SAR_REG_STAT);
 169	while (stat & SAR_STAT_CMDBZ)
 170		stat = readl(SAR_REG_STAT);
 171}
 172
 173static u32
 174read_sram(struct idt77252_dev *card, unsigned long addr)
 175{
 176	unsigned long flags;
 177	u32 value;
 178
 179	spin_lock_irqsave(&card->cmd_lock, flags);
 180	writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
 181	waitfor_idle(card);
 182	value = readl(SAR_REG_DR0);
 183	spin_unlock_irqrestore(&card->cmd_lock, flags);
 184	return value;
 185}
 186
 187static void
 188write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
 189{
 190	unsigned long flags;
 191
 192	if ((idt77252_sram_write_errors == 0) &&
 193	    (((addr > card->tst[0] + card->tst_size - 2) &&
 194	      (addr < card->tst[0] + card->tst_size)) ||
 195	     ((addr > card->tst[1] + card->tst_size - 2) &&
 196	      (addr < card->tst[1] + card->tst_size)))) {
 197		printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
 198		       card->name, addr, value);
 199	}
 200
 201	spin_lock_irqsave(&card->cmd_lock, flags);
 202	writel(value, SAR_REG_DR0);
 203	writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
 204	waitfor_idle(card);
 205	spin_unlock_irqrestore(&card->cmd_lock, flags);
 206}
 207
 208static u8
 209read_utility(void *dev, unsigned long ubus_addr)
 210{
 211	struct idt77252_dev *card = dev;
 212	unsigned long flags;
 213	u8 value;
 214
 215	if (!card) {
 216		printk("Error: No such device.\n");
 217		return -1;
 218	}
 219
 220	spin_lock_irqsave(&card->cmd_lock, flags);
 221	writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
 222	waitfor_idle(card);
 223	value = readl(SAR_REG_DR0);
 224	spin_unlock_irqrestore(&card->cmd_lock, flags);
 225	return value;
 226}
 227
 228static void
 229write_utility(void *dev, unsigned long ubus_addr, u8 value)
 230{
 231	struct idt77252_dev *card = dev;
 232	unsigned long flags;
 233
 234	if (!card) {
 235		printk("Error: No such device.\n");
 236		return;
 237	}
 238
 239	spin_lock_irqsave(&card->cmd_lock, flags);
 240	writel((u32) value, SAR_REG_DR0);
 241	writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
 242	waitfor_idle(card);
 243	spin_unlock_irqrestore(&card->cmd_lock, flags);
 244}
 245
 246#ifdef HAVE_EEPROM
 247static u32 rdsrtab[] =
 248{
 249	SAR_GP_EECS | SAR_GP_EESCLK,
 250	0,
 251	SAR_GP_EESCLK,			/* 0 */
 252	0,
 253	SAR_GP_EESCLK,			/* 0 */
 254	0,
 255	SAR_GP_EESCLK,			/* 0 */
 256	0,
 257	SAR_GP_EESCLK,			/* 0 */
 258	0,
 259	SAR_GP_EESCLK,			/* 0 */
 260	SAR_GP_EEDO,
 261	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
 262	0,
 263	SAR_GP_EESCLK,			/* 0 */
 264	SAR_GP_EEDO,
 265	SAR_GP_EESCLK | SAR_GP_EEDO	/* 1 */
 266};
 267
 268static u32 wrentab[] =
 269{
 270	SAR_GP_EECS | SAR_GP_EESCLK,
 271	0,
 272	SAR_GP_EESCLK,			/* 0 */
 273	0,
 274	SAR_GP_EESCLK,			/* 0 */
 275	0,
 276	SAR_GP_EESCLK,			/* 0 */
 277	0,
 278	SAR_GP_EESCLK,			/* 0 */
 279	SAR_GP_EEDO,
 280	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
 281	SAR_GP_EEDO,
 282	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
 283	0,
 284	SAR_GP_EESCLK,			/* 0 */
 285	0,
 286	SAR_GP_EESCLK			/* 0 */
 287};
 288
 289static u32 rdtab[] =
 290{
 291	SAR_GP_EECS | SAR_GP_EESCLK,
 292	0,
 293	SAR_GP_EESCLK,			/* 0 */
 294	0,
 295	SAR_GP_EESCLK,			/* 0 */
 296	0,
 297	SAR_GP_EESCLK,			/* 0 */
 298	0,
 299	SAR_GP_EESCLK,			/* 0 */
 300	0,
 301	SAR_GP_EESCLK,			/* 0 */
 302	0,
 303	SAR_GP_EESCLK,			/* 0 */
 304	SAR_GP_EEDO,
 305	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
 306	SAR_GP_EEDO,
 307	SAR_GP_EESCLK | SAR_GP_EEDO	/* 1 */
 308};
 309
 310static u32 wrtab[] =
 311{
 312	SAR_GP_EECS | SAR_GP_EESCLK,
 313	0,
 314	SAR_GP_EESCLK,			/* 0 */
 315	0,
 316	SAR_GP_EESCLK,			/* 0 */
 317	0,
 318	SAR_GP_EESCLK,			/* 0 */
 319	0,
 320	SAR_GP_EESCLK,			/* 0 */
 321	0,
 322	SAR_GP_EESCLK,			/* 0 */
 323	0,
 324	SAR_GP_EESCLK,			/* 0 */
 325	SAR_GP_EEDO,
 326	SAR_GP_EESCLK | SAR_GP_EEDO,	/* 1 */
 327	0,
 328	SAR_GP_EESCLK			/* 0 */
 329};
 330
 331static u32 clktab[] =
 332{
 333	0,
 334	SAR_GP_EESCLK,
 335	0,
 336	SAR_GP_EESCLK,
 337	0,
 338	SAR_GP_EESCLK,
 339	0,
 340	SAR_GP_EESCLK,
 341	0,
 342	SAR_GP_EESCLK,
 343	0,
 344	SAR_GP_EESCLK,
 345	0,
 346	SAR_GP_EESCLK,
 347	0,
 348	SAR_GP_EESCLK,
 349	0
 350};
 351
 352static u32
 353idt77252_read_gp(struct idt77252_dev *card)
 354{
 355	u32 gp;
 356
 357	gp = readl(SAR_REG_GP);
 358#if 0
 359	printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
 360#endif
 361	return gp;
 362}
 363
 364static void
 365idt77252_write_gp(struct idt77252_dev *card, u32 value)
 366{
 367	unsigned long flags;
 368
 369#if 0
 370	printk("WR: %s %s %s\n", value & SAR_GP_EECS ? "   " : "/CS",
 371	       value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
 372	       value & SAR_GP_EEDO   ? "1" : "0");
 373#endif
 374
 375	spin_lock_irqsave(&card->cmd_lock, flags);
 376	waitfor_idle(card);
 377	writel(value, SAR_REG_GP);
 378	spin_unlock_irqrestore(&card->cmd_lock, flags);
 379}
 380
 381static u8
 382idt77252_eeprom_read_status(struct idt77252_dev *card)
 383{
 384	u8 byte;
 385	u32 gp;
 386	int i, j;
 387
 388	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 389
 390	for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
 391		idt77252_write_gp(card, gp | rdsrtab[i]);
 392		udelay(5);
 393	}
 394	idt77252_write_gp(card, gp | SAR_GP_EECS);
 395	udelay(5);
 396
 397	byte = 0;
 398	for (i = 0, j = 0; i < 8; i++) {
 399		byte <<= 1;
 400
 401		idt77252_write_gp(card, gp | clktab[j++]);
 402		udelay(5);
 403
 404		byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
 405
 406		idt77252_write_gp(card, gp | clktab[j++]);
 407		udelay(5);
 408	}
 409	idt77252_write_gp(card, gp | SAR_GP_EECS);
 410	udelay(5);
 411
 412	return byte;
 413}
 414
 415static u8
 416idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
 417{
 418	u8 byte;
 419	u32 gp;
 420	int i, j;
 421
 422	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 423
 424	for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
 425		idt77252_write_gp(card, gp | rdtab[i]);
 426		udelay(5);
 427	}
 428	idt77252_write_gp(card, gp | SAR_GP_EECS);
 429	udelay(5);
 430
 431	for (i = 0, j = 0; i < 8; i++) {
 432		idt77252_write_gp(card, gp | clktab[j++] |
 433					(offset & 1 ? SAR_GP_EEDO : 0));
 434		udelay(5);
 435
 436		idt77252_write_gp(card, gp | clktab[j++] |
 437					(offset & 1 ? SAR_GP_EEDO : 0));
 438		udelay(5);
 439
 440		offset >>= 1;
 441	}
 442	idt77252_write_gp(card, gp | SAR_GP_EECS);
 443	udelay(5);
 444
 445	byte = 0;
 446	for (i = 0, j = 0; i < 8; i++) {
 447		byte <<= 1;
 448
 449		idt77252_write_gp(card, gp | clktab[j++]);
 450		udelay(5);
 451
 452		byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
 453
 454		idt77252_write_gp(card, gp | clktab[j++]);
 455		udelay(5);
 456	}
 457	idt77252_write_gp(card, gp | SAR_GP_EECS);
 458	udelay(5);
 459
 460	return byte;
 461}
 462
 463static void
 464idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
 465{
 466	u32 gp;
 467	int i, j;
 468
 469	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 470
 471	for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
 472		idt77252_write_gp(card, gp | wrentab[i]);
 473		udelay(5);
 474	}
 475	idt77252_write_gp(card, gp | SAR_GP_EECS);
 476	udelay(5);
 477
 478	for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
 479		idt77252_write_gp(card, gp | wrtab[i]);
 480		udelay(5);
 481	}
 482	idt77252_write_gp(card, gp | SAR_GP_EECS);
 483	udelay(5);
 484
 485	for (i = 0, j = 0; i < 8; i++) {
 486		idt77252_write_gp(card, gp | clktab[j++] |
 487					(offset & 1 ? SAR_GP_EEDO : 0));
 488		udelay(5);
 489
 490		idt77252_write_gp(card, gp | clktab[j++] |
 491					(offset & 1 ? SAR_GP_EEDO : 0));
 492		udelay(5);
 493
 494		offset >>= 1;
 495	}
 496	idt77252_write_gp(card, gp | SAR_GP_EECS);
 497	udelay(5);
 498
 499	for (i = 0, j = 0; i < 8; i++) {
 500		idt77252_write_gp(card, gp | clktab[j++] |
 501					(data & 1 ? SAR_GP_EEDO : 0));
 502		udelay(5);
 503
 504		idt77252_write_gp(card, gp | clktab[j++] |
 505					(data & 1 ? SAR_GP_EEDO : 0));
 506		udelay(5);
 507
 508		data >>= 1;
 509	}
 510	idt77252_write_gp(card, gp | SAR_GP_EECS);
 511	udelay(5);
 512}
 513
 514static void
 515idt77252_eeprom_init(struct idt77252_dev *card)
 516{
 517	u32 gp;
 518
 519	gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 520
 521	idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
 522	udelay(5);
 523	idt77252_write_gp(card, gp | SAR_GP_EECS);
 524	udelay(5);
 525	idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
 526	udelay(5);
 527	idt77252_write_gp(card, gp | SAR_GP_EECS);
 528	udelay(5);
 529}
 530#endif /* HAVE_EEPROM */
 531
 532
 533#ifdef CONFIG_ATM_IDT77252_DEBUG
 534static void
 535dump_tct(struct idt77252_dev *card, int index)
 536{
 537	unsigned long tct;
 538	int i;
 539
 540	tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
 541
 542	printk("%s: TCT %x:", card->name, index);
 543	for (i = 0; i < 8; i++) {
 544		printk(" %08x", read_sram(card, tct + i));
 545	}
 546	printk("\n");
 547}
 548
 549static void
 550idt77252_tx_dump(struct idt77252_dev *card)
 551{
 552	struct atm_vcc *vcc;
 553	struct vc_map *vc;
 554	int i;
 555
 556	printk("%s\n", __FUNCTION__);
 557	for (i = 0; i < card->tct_size; i++) {
 558		vc = card->vcs[i];
 559		if (!vc)
 560			continue;
 561
 562		vcc = NULL;
 563		if (vc->rx_vcc)
 564			vcc = vc->rx_vcc;
 565		else if (vc->tx_vcc)
 566			vcc = vc->tx_vcc;
 567
 568		if (!vcc)
 569			continue;
 570
 571		printk("%s: Connection %d:\n", card->name, vc->index);
 572		dump_tct(card, vc->index);
 573	}
 574}
 575#endif
 576
 577
 578/*****************************************************************************/
 579/*                                                                           */
 580/* SCQ Handling                                                              */
 581/*                                                                           */
 582/*****************************************************************************/
 583
 584static int
 585sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
 586{
 587	struct sb_pool *pool = &card->sbpool[queue];
 588	int index;
 589
 590	index = pool->index;
 591	while (pool->skb[index]) {
 592		index = (index + 1) & FBQ_MASK;
 593		if (index == pool->index)
 594			return -ENOBUFS;
 595	}
 596
 597	pool->skb[index] = skb;
 598	IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
 599
 600	pool->index = (index + 1) & FBQ_MASK;
 601	return 0;
 602}
 603
 604static void
 605sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
 606{
 607	unsigned int queue, index;
 608	u32 handle;
 609
 610	handle = IDT77252_PRV_POOL(skb);
 611
 612	queue = POOL_QUEUE(handle);
 613	if (queue > 3)
 614		return;
 615
 616	index = POOL_INDEX(handle);
 617	if (index > FBQ_SIZE - 1)
 618		return;
 619
 620	card->sbpool[queue].skb[index] = NULL;
 621}
 622
 623static struct sk_buff *
 624sb_pool_skb(struct idt77252_dev *card, u32 handle)
 625{
 626	unsigned int queue, index;
 627
 628	queue = POOL_QUEUE(handle);
 629	if (queue > 3)
 630		return NULL;
 631
 632	index = POOL_INDEX(handle);
 633	if (index > FBQ_SIZE - 1)
 634		return NULL;
 635
 636	return card->sbpool[queue].skb[index];
 637}
 638
 639static struct scq_info *
 640alloc_scq(struct idt77252_dev *card, int class)
 641{
 642	struct scq_info *scq;
 643
 644	scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
 645	if (!scq)
 646		return NULL;
 647	memset(scq, 0, sizeof(struct scq_info));
 648
 649	scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
 650					 &scq->paddr);
 651	if (scq->base == NULL) {
 652		kfree(scq);
 653		return NULL;
 654	}
 655	memset(scq->base, 0, SCQ_SIZE);
 656
 657	scq->next = scq->base;
 658	scq->last = scq->base + (SCQ_ENTRIES - 1);
 659	atomic_set(&scq->used, 0);
 660
 661	spin_lock_init(&scq->lock);
 662	spin_lock_init(&scq->skblock);
 663
 664	skb_queue_head_init(&scq->transmit);
 665	skb_queue_head_init(&scq->pending);
 666
 667	TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
 668		 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
 669
 670	return scq;
 671}
 672
 673static void
 674free_scq(struct idt77252_dev *card, struct scq_info *scq)
 675{
 676	struct sk_buff *skb;
 677	struct atm_vcc *vcc;
 678
 679	pci_free_consistent(card->pcidev, SCQ_SIZE,
 680			    scq->base, scq->paddr);
 681
 682	while ((skb = skb_dequeue(&scq->transmit))) {
 683		pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
 684				 skb->len, PCI_DMA_TODEVICE);
 685
 686		vcc = ATM_SKB(skb)->vcc;
 687		if (vcc->pop)
 688			vcc->pop(vcc, skb);
 689		else
 690			dev_kfree_skb(skb);
 691	}
 692
 693	while ((skb = skb_dequeue(&scq->pending))) {
 694		pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
 695				 skb->len, PCI_DMA_TODEVICE);
 696
 697		vcc = ATM_SKB(skb)->vcc;
 698		if (vcc->pop)
 699			vcc->pop(vcc, skb);
 700		else
 701			dev_kfree_skb(skb);
 702	}
 703
 704	kfree(scq);
 705}
 706
 707
 708static int
 709push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
 710{
 711	struct scq_info *scq = vc->scq;
 712	unsigned long flags;
 713	struct scqe *tbd;
 714	int entries;
 715
 716	TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
 717
 718	atomic_inc(&scq->used);
 719	entries = atomic_read(&scq->used);
 720	if (entries > (SCQ_ENTRIES - 1)) {
 721		atomic_dec(&scq->used);
 722		goto out;
 723	}
 724
 725	skb_queue_tail(&scq->transmit, skb);
 726
 727	spin_lock_irqsave(&vc->lock, flags);
 728	if (vc->estimator) {
 729		struct atm_vcc *vcc = vc->tx_vcc;
 730		struct sock *sk = sk_atm(vcc);
 731
 732		vc->estimator->cells += (skb->len + 47) / 48;
 733		if (atomic_read(&sk->sk_wmem_alloc) >
 734		    (sk->sk_sndbuf >> 1)) {
 735			u32 cps = vc->estimator->maxcps;
 736
 737			vc->estimator->cps = cps;
 738			vc->estimator->avcps = cps << 5;
 739			if (vc->lacr < vc->init_er) {
 740				vc->lacr = vc->init_er;
 741				writel(TCMDQ_LACR | (vc->lacr << 16) |
 742				       vc->index, SAR_REG_TCMDQ);
 743			}
 744		}
 745	}
 746	spin_unlock_irqrestore(&vc->lock, flags);
 747
 748	tbd = &IDT77252_PRV_TBD(skb);
 749
 750	spin_lock_irqsave(&scq->lock, flags);
 751	scq->next->word_1 = cpu_to_le32(tbd->word_1 |
 752					SAR_TBD_TSIF | SAR_TBD_GTSI);
 753	scq->next->word_2 = cpu_to_le32(tbd->word_2);
 754	scq->next->word_3 = cpu_to_le32(tbd->word_3);
 755	scq->next->word_4 = cpu_to_le32(tbd->word_4);
 756
 757	if (scq->next == scq->last)
 758		scq->next = scq->base;
 759	else
 760		scq->next++;
 761
 762	write_sram(card, scq->scd,
 763		   scq->paddr +
 764		   (u32)((unsigned long)scq->next - (unsigned long)scq->base));
 765	spin_unlock_irqrestore(&scq->lock, flags);
 766
 767	scq->trans_start = jiffies;
 768
 769	if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
 770		writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
 771		       SAR_REG_TCMDQ);
 772	}
 773
 774	TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
 775
 776	XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
 777		card->name, atomic_read(&scq->used),
 778		read_sram(card, scq->scd + 1), scq->next);
 779
 780	return 0;
 781
 782out:
 783	if (jiffies - scq->trans_start > HZ) {
 784		printk("%s: Error pushing TBD for %d.%d\n",
 785		       card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
 786#ifdef CONFIG_ATM_IDT77252_DEBUG
 787		idt77252_tx_dump(card);
 788#endif
 789		scq->trans_start = jiffies;
 790	}
 791
 792	return -ENOBUFS;
 793}
 794
 795
 796static void
 797drain_scq(struct idt77252_dev *card, struct vc_map *vc)
 798{
 799	struct scq_info *scq = vc->scq;
 800	struct sk_buff *skb;
 801	struct atm_vcc *vcc;
 802
 803	TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
 804		 card->name, atomic_read(&scq->used), scq->next);
 805
 806	skb = skb_dequeue(&scq->transmit);
 807	if (skb) {
 808		TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
 809
 810		pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
 811				 skb->len, PCI_DMA_TODEVICE);
 812
 813		vcc = ATM_SKB(skb)->vcc;
 814
 815		if (vcc->pop)
 816			vcc->pop(vcc, skb);
 817		else
 818			dev_kfree_skb(skb);
 819
 820		atomic_inc(&vcc->stats->tx);
 821	}
 822
 823	atomic_dec(&scq->used);
 824
 825	spin_lock(&scq->skblock);
 826	while ((skb = skb_dequeue(&scq->pending))) {
 827		if (push_on_scq(card, vc, skb)) {
 828			skb_queue_head(&vc->scq->pending, skb);
 829			break;
 830		}
 831	}
 832	spin_unlock(&scq->skblock);
 833}
 834
 835static int
 836queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 837	  struct sk_buff *skb, int oam)
 838{
 839	struct atm_vcc *vcc;
 840	struct scqe *tbd;
 841	unsigned long flags;
 842	int error;
 843	int aal;
 844
 845	if (skb->len == 0) {
 846		printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
 847		return -EINVAL;
 848	}
 849
 850	TXPRINTK("%s: Sending %d bytes of data.\n",
 851		 card->name, skb->len);
 852
 853	tbd = &IDT77252_PRV_TBD(skb);
 854	vcc = ATM_SKB(skb)->vcc;
 855
 856	IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
 857						 skb->len, PCI_DMA_TODEVICE);
 858
 859	error = -EINVAL;
 860
 861	if (oam) {
 862		if (skb->len != 52)
 863			goto errout;
 864
 865		tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
 866		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 867		tbd->word_3 = 0x00000000;
 868		tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
 869			      (skb->data[2] <<  8) | (skb->data[3] <<  0);
 870
 871		if (test_bit(VCF_RSV, &vc->flags))
 872			vc = card->vcs[0];
 873
 874		goto done;
 875	}
 876
 877	if (test_bit(VCF_RSV, &vc->flags)) {
 878		printk("%s: Trying to transmit on reserved VC\n", card->name);
 879		goto errout;
 880	}
 881
 882	aal = vcc->qos.aal;
 883
 884	switch (aal) {
 885	case ATM_AAL0:
 886	case ATM_AAL34:
 887		if (skb->len > 52)
 888			goto errout;
 889
 890		if (aal == ATM_AAL0)
 891			tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
 892				      ATM_CELL_PAYLOAD;
 893		else
 894			tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
 895				      ATM_CELL_PAYLOAD;
 896
 897		tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 898		tbd->word_3 = 0x00000000;
 899		tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
 900			      (skb->data[2] <<  8) | (skb->data[3] <<  0);
 901		break;
 902
 903	case ATM_AAL5:
 904		tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
 905		tbd->word_2 = IDT77252_PRV_PADDR(skb);
 906		tbd->word_3 = skb->len;
 907		tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
 908			      (vcc->vci << SAR_TBD_VCI_SHIFT);
 909		break;
 910
 911	case ATM_AAL1:
 912	case ATM_AAL2:
 913	default:
 914		printk("%s: Traffic type not supported.\n", card->name);
 915		error = -EPROTONOSUPPORT;
 916		goto errout;
 917	}
 918
 919done:
 920	spin_lock_irqsave(&vc->scq->skblock, flags);
 921	skb_queue_tail(&vc->scq->pending, skb);
 922
 923	while ((skb = skb_dequeue(&vc->scq->pending))) {
 924		if (push_on_scq(card, vc, skb)) {
 925			skb_queue_head(&vc->scq->pending, skb);
 926			break;
 927		}
 928	}
 929	spin_unlock_irqrestore(&vc->scq->skblock, flags);
 930
 931	return 0;
 932
 933errout:
 934	pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
 935			 skb->len, PCI_DMA_TODEVICE);
 936	return error;
 937}
 938
 939static unsigned long
 940get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
 941{
 942	int i;
 943
 944	for (i = 0; i < card->scd_size; i++) {
 945		if (!card->scd2vc[i]) {
 946			card->scd2vc[i] = vc;
 947			vc->scd_index = i;
 948			return card->scd_base + i * SAR_SRAM_SCD_SIZE;
 949		}
 950	}
 951	return 0;
 952}
 953
 954static void
 955fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
 956{
 957	write_sram(card, scq->scd, scq->paddr);
 958	write_sram(card, scq->scd + 1, 0x00000000);
 959	write_sram(card, scq->scd + 2, 0xffffffff);
 960	write_sram(card, scq->scd + 3, 0x00000000);
 961}
 962
 963static void
 964clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
 965{
 966	return;
 967}
 968
 969/*****************************************************************************/
 970/*                                                                           */
 971/* RSQ Handling                                                              */
 972/*                                                                           */
 973/*****************************************************************************/
 974
 975static int
 976init_rsq(struct idt77252_dev *card)
 977{
 978	struct rsq_entry *rsqe;
 979
 980	card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
 981					      &card->rsq.paddr);
 982	if (card->rsq.base == NULL) {
 983		printk("%s: can't allocate RSQ.\n", card->name);
 984		return -1;
 985	}
 986	memset(card->rsq.base, 0, RSQSIZE);
 987
 988	card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
 989	card->rsq.next = card->rsq.last;
 990	for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
 991		rsqe->word_4 = 0;
 992
 993	writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
 994	       SAR_REG_RSQH);
 995	writel(card->rsq.paddr, SAR_REG_RSQB);
 996
 997	IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
 998		(unsigned long) card->rsq.base,
 999		readl(SAR_REG_RSQB));
1000	IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1001		card->name,
1002		readl(SAR_REG_RSQH),
1003		readl(SAR_REG_RSQB),
1004		readl(SAR_REG_RSQT));
1005
1006	return 0;
1007}
1008
1009static void
1010deinit_rsq(struct idt77252_dev *card)
1011{
1012	pci_free_consistent(card->pcidev, RSQSIZE,
1013			    card->rsq.base, card->rsq.paddr);
1014}
1015
1016static void
1017dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1018{
1019	struct atm_vcc *vcc;
1020	struct sk_buff *skb;
1021	struct rx_pool *rpp;
1022	struct vc_map *vc;
1023	u32 header, vpi, vci;
1024	u32 stat;
1025	int i;
1026
1027	stat = le32_to_cpu(rsqe->word_4);
1028
1029	if (stat & SAR_RSQE_IDLE) {
1030		RXPRINTK("%s: message about inactive connection.\n",
1031			 card->name);
1032		return;
1033	}
1034
1035	skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1036	if (skb == NULL) {
1037		printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1038		       card->name, __FUNCTION__,
1039		       le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1040		       le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1041		return;
1042	}
1043
1044	header = le32_to_cpu(rsqe->word_1);
1045	vpi = (header >> 16) & 0x00ff;
1046	vci = (header >>  0) & 0xffff;
1047
1048	RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1049		 card->name, vpi, vci, skb, skb->data);
1050
1051	if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1052		printk("%s: SDU received for out-of-range vc %u.%u\n",
1053		       card->name, vpi, vci);
1054		recycle_rx_skb(card, skb);
1055		return;
1056	}
1057
1058	vc = card->vcs[VPCI2VC(card, vpi, vci)];
1059	if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1060		printk("%s: SDU received on non RX vc %u.%u\n",
1061		       card->name, vpi, vci);
1062		recycle_rx_skb(card, skb);
1063		return;
1064	}
1065
1066	vcc = vc->rx_vcc;
1067
1068	pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1069				    skb->end - skb->data, PCI_DMA_FROMDEVICE);
1070
1071	if ((vcc->qos.aal == ATM_AAL0) ||
1072	    (vcc->qos.aal == ATM_AAL34)) {
1073		struct sk_buff *sb;
1074		unsigned char *cell;
1075		u32 aal0;
1076
1077		cell = skb->data;
1078		for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1079			if ((sb = dev_alloc_skb(64)) == NULL) {
1080				printk("%s: Can't allocate buffers for aal0.\n",
1081				       card->name);
1082				atomic_add(i, &vcc->stats->rx_drop);
1083				break;
1084			}
1085			if (!atm_charge(vcc, sb->truesize)) {
1086				RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1087					 card->name);
1088				atomic_add(i - 1, &vcc->stats->rx_drop);
1089				dev_kfree_skb(sb);
1090				break;
1091			}
1092			aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1093			       (vci << ATM_HDR_VCI_SHIFT);
1094			aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1095			aal0 |= (stat & SAR_RSQE_CLP)  ? 0x00000001 : 0;
1096
1097			*((u32 *) sb->data) = aal0;
1098			skb_put(sb, sizeof(u32));
1099			memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1100			       cell, ATM_CELL_PAYLOAD);
1101
1102			ATM_SKB(sb)->vcc = vcc;
1103			do_gettimeofday(&sb->stamp);
1104			vcc->push(vcc, sb);
1105			atomic_inc(&vcc->stats->rx);
1106
1107			cell += ATM_CELL_PAYLOAD;
1108		}
1109
1110		recycle_rx_skb(card, skb);
1111		return;
1112	}
1113	if (vcc->qos.aal != ATM_AAL5) {
1114		printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1115		       card->name, vcc->qos.aal);
1116		recycle_rx_skb(card, skb);
1117		return;
1118	}
1119	skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1120
1121	rpp = &vc->rcv.rx_pool;
1122
1123	rpp->len += skb->len;
1124	if (!rpp->count++)
1125		rpp->first = skb;
1126	*rpp->last = skb;
1127	rpp->last = &skb->next;
1128
1129	if (stat & SAR_RSQE_EPDU) {
1130		unsigned char *l1l2;
1131		unsigned int len;
1132
1133		l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1134
1135		len = (l1l2[0] << 8) | l1l2[1];
1136		len = len ? len : 0x10000;
1137
1138		RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1139
1140		if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1141			RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1142			         "(CDC: %08x)\n",
1143			         card->name, len, rpp->len, readl(SAR_REG_CDC));
1144			recycle_rx_pool_skb(card, rpp);
1145			atomic_inc(&vcc->stats->rx_err);
1146			return;
1147		}
1148		if (stat & SAR_RSQE_CRC) {
1149			RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1150			recycle_rx_pool_skb(card, rpp);
1151			atomic_inc(&vcc->stats->rx_err);
1152			return;
1153		}
1154		if (rpp->count > 1) {
1155			struct sk_buff *sb;
1156
1157			skb = dev_alloc_skb(rpp->len);
1158			if (!skb) {
1159				RXPRINTK("%s: Can't alloc RX skb.\n",
1160					 card->name);
1161				recycle_rx_pool_skb(card, rpp);
1162				atomic_inc(&vcc->stats->rx_err);
1163				return;
1164			}
1165			if (!atm_charge(vcc, skb->truesize)) {
1166				recycle_rx_pool_skb(card, rpp);
1167				dev_kfree_skb(skb);
1168				return;
1169			}
1170			sb = rpp->first;
1171			for (i = 0; i < rpp->count; i++) {
1172				memcpy(skb_put(skb, sb->len),
1173				       sb->data, sb->len);
1174				sb = sb->next;
1175			}
1176
1177			recycle_rx_pool_skb(card, rpp);
1178
1179			skb_trim(skb, len);
1180			ATM_SKB(skb)->vcc = vcc;
1181			do_gettimeofday(&skb->stamp);
1182
1183			vcc->push(vcc, skb);
1184			atomic_inc(&vcc->stats->rx);
1185
1186			return;
1187		}
1188
1189		skb->next = NULL;
1190		flush_rx_pool(card, rpp);
1191
1192		if (!atm_charge(vcc, skb->truesize)) {
1193			recycle_rx_skb(card, skb);
1194			return;
1195		}
1196
1197		pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1198				 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1199		sb_pool_remove(card, skb);
1200
1201		skb_trim(skb, len);
1202		ATM_SKB(skb)->vcc = vcc;
1203		do_gettimeofday(&skb->stamp);
1204
1205		vcc->push(vcc, skb);
1206		atomic_inc(&vcc->stats->rx);
1207
1208		if (skb->truesize > SAR_FB_SIZE_3)
1209			add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1210		else if (skb->truesize > SAR_FB_SIZE_2)
1211			add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1212		else if (skb->truesize > SAR_FB_SIZE_1)
1213			add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1214		else
1215			add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1216		return;
1217	}
1218}
1219
1220static void
1221idt77252_rx(struct idt77252_dev *card)
1222{
1223	struct rsq_entry *rsqe;
1224
1225	if (card->rsq.next == card->rsq.last)
1226		rsqe = card->rsq.base;
1227	else
1228		rsqe = card->rsq.next + 1;
1229
1230	if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1231		RXPRINTK("%s: no entry in RSQ.\n", card->name);
1232		return;
1233	}
1234
1235	do {
1236		dequeue_rx(card, rsqe);
1237		rsqe->word_4 = 0;
1238		card->rsq.next = rsqe;
1239		if (card->rsq.next == card->rsq.last)
1240			rsqe = card->rsq.base;
1241		else
1242			rsqe = card->rsq.next + 1;
1243	} while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1244
1245	writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1246	       SAR_REG_RSQH);
1247}
1248
1249static void
1250idt77252_rx_raw(struct idt77252_dev *card)
1251{
1252	struct sk_buff	*queue;
1253	u32		head, tail;
1254	struct atm_vcc	*vcc;
1255	struct vc_map	*vc;
1256	struct sk_buff	*sb;
1257
1258	if (card->raw_cell_head == NULL) {
1259		u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1260		card->raw_cell_head = sb_pool_skb(card, handle);
1261	}
1262
1263	queue = card->raw_cell_head;
1264	if (!queue)
1265		return;
1266
1267	head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1268	tail = readl(SAR_REG_RAWCT);
1269
1270	pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1271				    queue->end - queue->head - 16,
1272				    PCI_DMA_FROMDEVICE);
1273
1274	while (head != tail) {
1275		unsigned int vpi, vci, pti;
1276		u32 header;
1277
1278		header = le32_to_cpu(*(u32 *) &queue->data[0]);
1279
1280		vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1281		vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1282		pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1283
1284#ifdef CONFIG_ATM_IDT77252_DEBUG
1285		if (debug & DBG_RAW_CELL) {
1286			int i;
1287
1288			printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1289			       card->name, (header >> 28) & 0x000f,
1290			       (header >> 20) & 0x00ff,
1291			       (header >>  4) & 0xffff,
1292			       (header >>  1) & 0x0007,
1293			       (header >>  0) & 0x0001);
1294			for (i = 16; i < 64; i++)
1295				printk(" %02x", queue->data[i]);
1296			printk("\n");
1297		}
1298#endif
1299
1300		if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1301			RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1302				card->name, vpi, vci);
1303			goto drop;
1304		}
1305
1306		vc = card->vcs[VPCI2VC(card, vpi, vci)];
1307		if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1308			RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1309				card->name, vpi, vci);
1310			goto drop;
1311		}
1312
1313		vcc = vc->rx_vcc;
1314
1315		if (vcc->qos.aal != ATM_AAL0) {
1316			RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1317				card->name, vpi, vci);
1318			atomic_inc(&vcc->stats->rx_drop);
1319			goto drop;
1320		}
1321	
1322		if ((sb = dev_alloc_skb(64)) == NULL) {
1323			printk("%s: Can't allocate buffers for AAL0.\n",
1324			       card->name);
1325			atomic_inc(&vcc->stats->rx_err);
1326			goto drop;
1327		}
1328
1329		if (!atm_charge(vcc, sb->truesize)) {
1330			RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1331				 card->name);
1332			dev_kfree_skb(sb);
1333			goto drop;
1334		}
1335
1336		*((u32 *) sb->data) = header;
1337		skb_put(sb, sizeof(u32));
1338		memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1339		       ATM_CELL_PAYLOAD);
1340
1341		ATM_SKB(sb)->vcc = vcc;
1342		do_gettimeofday(&sb->stamp);
1343		vcc->push(vcc, sb);
1344		atomic_inc(&vcc->stats->rx);
1345
1346drop:
1347		skb_pull(queue, 64);
1348
1349		head = IDT77252_PRV_PADDR(queue)
1350					+ (queue->data - queue->head - 16);
1351
1352		if (queue->len < 128) {
1353			struct sk_buff *next;
1354			u32 handle;
1355
1356			head = le32_to_cpu(*(u32 *) &queue->data[0]);
1357			handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1358
1359			next = sb_pool_skb(card, handle);
1360			recycle_rx_skb(card, queue);
1361
1362			if (next) {
1363				card->raw_cell_head = next;
1364				queue = card->raw_cell_head;
1365				pci_dma_sync_single_for_cpu(card->pcidev,
1366							    IDT77252_PRV_PADDR(queue),
1367							    queue->end - queue->data,
1368							    PCI_DMA_FROMDEVICE);
1369			} else {
1370				card->raw_cell_head = NULL;
1371				printk("%s: raw cell queue overrun\n",
1372				       card->name);
1373				break;
1374			}
1375		}
1376	}
1377}
1378
1379
1380/*****************************************************************************/
1381/*                                                                           */
1382/* TSQ Handling                                                              */
1383/*                                                                           */
1384/*****************************************************************************/
1385
1386static int
1387init_tsq(struct idt77252_dev *card)
1388{
1389	struct tsq_entry *tsqe;
1390
1391	card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1392					      &card->tsq.paddr);
1393	if (card->tsq.base == NULL) {
1394		printk("%s: can't allocate TSQ.\n", card->name);
1395		return -1;
1396	}
1397	memset(card->tsq.base, 0, TSQSIZE);
1398
1399	card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1400	card->tsq.next = card->tsq.last;
1401	for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1402		tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1403
1404	writel(card->tsq.paddr, SAR_REG_TSQB);
1405	writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1406	       SAR_REG_TSQH);
1407
1408	return 0;
1409}
1410
1411static void
1412deinit_tsq(struct idt77252_dev *card)
1413{
1414	pci_free_consistent(card->pcidev, TSQSIZE,
1415			    card->tsq.base, card->tsq.paddr);
1416}
1417
1418static void
1419idt77252_tx(struct idt77252_dev *card)
1420{
1421	struct tsq_entry *tsqe;
1422	unsigned int vpi, vci;
1423	struct vc_map *vc;
1424	u32 conn, stat;
1425
1426	if (card->tsq.next == card->tsq.last)
1427		tsqe = card->tsq.base;
1428	else
1429		tsqe = card->tsq.next + 1;
1430
1431	TXPRINTK("idt77252_tx: tsq  %p: base %p, next %p, last %p\n", tsqe,
1432		 card->tsq.base, card->tsq.next, card->tsq.last);
1433	TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1434		 readl(SAR_REG_TSQB),
1435		 readl(SAR_REG_TSQT),
1436		 readl(SAR_REG_TSQH));
1437
1438	stat = le32_to_cpu(tsqe->word_2);
1439
1440	if (stat & SAR_TSQE_INVALID)
1441		return;
1442
1443	do {
1444		TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1445			 le32_to_cpu(tsqe->word_1),
1446			 le32_to_cpu(tsqe->word_2));
1447
1448		switch (stat & SAR_TSQE_TYPE) {
1449		case SAR_TSQE_TYPE_TIMER:
1450			TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1451			break;
1452
1453		case SAR_TSQE_TYPE_IDLE:
1454
1455			conn = le32_to_cpu(tsqe->word_1);
1456
1457			if (SAR_TSQE_TAG(stat) == 0x10) {
1458#ifdef	NOTDEF
1459				printk("%s: Connection %d halted.\n",
1460				       card->name,
1461				       le32_to_cpu(tsqe->word_1) & 0x1fff);
1462#endif
1463				break;
1464			}
1465
1466			vc = card->vcs[conn & 0x1fff];
1467			if (!vc) {
1468				printk("%s: could not find VC from conn %d\n",
1469				       card->name, conn & 0x1fff);
1470				break;
1471			}
1472
1473			printk("%s: Connection %d IDLE.\n",
1474			       card->name, vc->index);
1475
1476			set_bit(VCF_IDLE, &vc->flags);
1477			break;
1478
1479		case SAR_TSQE_TYPE_TSR:
1480
1481			conn = le32_to_cpu(tsqe->word_1);
1482
1483			vc = card->vcs[conn & 0x1fff];
1484			if (!vc) {
1485				printk("%s: no VC at index %d\n",
1486				       card->name,
1487				       le32_to_cpu(tsqe->word_1) & 0x1fff);
1488				break;
1489			}
1490
1491			drain_scq(card, vc);
1492			break;
1493
1494		case SAR_TSQE_TYPE_TBD_COMP:
1495
1496			conn = le32_to_cpu(tsqe->word_1);
1497
1498			vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1499			vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1500
1501			if (vpi >= (1 << card->vpibits) ||
1502			    vci >= (1 << card->vcibits)) {
1503				printk("%s: TBD complete: "
1504				       "out of range VPI.VCI %u.%u\n",
1505				       card->name, vpi, vci);
1506				break;
1507			}
1508
1509			vc = card->vcs[VPCI2VC(card, vpi, vci)];
1510			if (!vc) {
1511				printk("%s: TBD complete: "
1512				       "no VC at VPI.VCI %u.%u\n",
1513				       card->name, vpi, vci);
1514				break;
1515			}
1516
1517			drain_scq(card, vc);
1518			break;
1519		}
1520
1521		tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1522
1523		card->tsq.next = tsqe;
1524		if (card->tsq.next == card->tsq.last)
1525			tsqe = card->tsq.base;
1526		else
1527			tsqe = card->tsq.next + 1;
1528
1529		TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1530			 card->tsq.base, card->tsq.next, card->tsq.last);
1531
1532		stat = le32_to_cpu(tsqe->word_2);
1533
1534	} while (!(stat & SAR_TSQE_INVALID));
1535
1536	writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1537	       SAR_REG_TSQH);
1538
1539	XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1540		card->index, readl(SAR_REG_TSQH),
1541		readl(SAR_REG_TSQT), card->tsq.next);
1542}
1543
1544
1545static void
1546tst_timer(unsigned long data)
1547{
1548	struct idt77252_dev *card = (struct idt77252_dev *)data;
1549	unsigned long base, idle, jump;
1550	unsigned long flags;
1551	u32 pc;
1552	int e;
1553
1554	spin_lock_irqsave(&card->tst_lock, flags);
1555
1556	base = card->tst[card->tst_index];
1557	idle = card->tst[card->tst_index ^ 1];
1558
1559	if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1560		jump = base + card->tst_size - 2;
1561
1562		pc = readl(SAR_REG_NOW) >> 2;
1563		if ((pc ^ idle) & ~(card->tst_size - 1)) {
1564			mod_timer(&card->tst_timer, jiffies + 1);
1565			goto out;
1566		}
1567
1568		clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1569
1570		card->tst_index ^= 1;
1571		write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1572
1573		base = card->tst[card->tst_index];
1574		idle = card->tst[card->tst_index ^ 1];
1575
1576		for (e = 0; e < card->tst_size - 2; e++) {
1577			if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1578				write_sram(card, idle + e,
1579					   card->soft_tst[e].tste & TSTE_MASK);
1580				card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1581			}
1582		}
1583	}
1584
1585	if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1586
1587		for (e = 0; e < card->tst_size - 2; e++) {
1588			if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1589				write_sram(card, idle + e,
1590					   card->soft_tst[e].tste & TSTE_MASK);
1591				card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1592				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1593			}
1594		}
1595
1596		jump = base + card->tst_size - 2;
1597
1598		write_sram(card, jump, TSTE_OPC_NULL);
1599		set_bit(TST_SWITCH_WAIT, &card->tst_state);
1600
1601		mod_timer(&card->tst_timer, jiffies + 1);
1602	}
1603
1604out:
1605	spin_unlock_irqrestore(&card->tst_lock, flags);
1606}
1607
1608static int
1609__fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1610	   int n, unsigned int opc)
1611{
1612	unsigned long cl, avail;
1613	unsigned long idle;
1614	int e, r;
1615	u32 data;
1616
1617	avail = card->tst_size - 2;
1618	for (e = 0; e < avail; e++) {
1619		if (card->soft_tst[e].vc == NULL)
1620			break;
1621	}
1622	if (e >= avail) {
1623		printk("%s: No free TST entries found\n", card->name);
1624		return -1;
1625	}
1626
1627	NPRINTK("%s: conn %d: first TST entry at %d.\n",
1628		card->name, vc ? vc->index : -1, e);
1629
1630	r = n;
1631	cl = avail;
1632	data = opc & TSTE_OPC_MASK;
1633	if (vc && (opc != TSTE_OPC_NULL))
1634		data = opc | vc->index;
1635
1636	idle = card->tst[card->tst_index ^ 1];
1637
1638	/*
1639	 * Fill Soft TST.
1640	 */
1641	while (r > 0) {
1642		if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1643			if (vc)
1644				card->soft_tst[e].vc = vc;
1645			else
1646				card->soft_tst[e].vc = (void *)-1;
1647
1648			card->soft_tst[e].tste = data;
1649			if (timer_pending(&card->tst_timer))
1650				card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1651			else {
1652				write_sram(card, idle + e, data);
1653				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1654			}
1655
1656			cl -= card->tst_size;
1657			r--;
1658		}
1659
1660		if (++e == avail)
1661			e = 0;
1662		cl += n;
1663	}
1664
1665	return 0;
1666}
1667
1668static int
1669fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1670{
1671	unsigned long flags;
1672	int res;
1673
1674	spin_lock_irqsave(&card->tst_lock, flags);
1675
1676	res = __fill_tst(card, vc, n, opc);
1677
1678	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1679	if (!timer_pending(&card->tst_timer))
1680		mod_timer(&card->tst_timer, jiffies + 1);
1681
1682	spin_unlock_irqrestore(&card->tst_lock, flags);
1683	return res;
1684}
1685
1686static int
1687__clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1688{
1689	unsigned long idle;
1690	int e;
1691
1692	idle = card->tst[card->tst_index ^ 1];
1693
1694	for (e = 0; e < card->tst_size - 2; e++) {
1695		if (card->soft_tst[e].vc == vc) {
1696			card->soft_tst[e].vc = NULL;
1697
1698			card->soft_tst[e].tste = TSTE_OPC_VAR;
1699			if (timer_pending(&card->tst_timer))
1700				card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1701			else {
1702				write_sram(card, idle + e, TSTE_OPC_VAR);
1703				card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1704			}
1705		}
1706	}
1707
1708	return 0;
1709}
1710
1711static int
1712clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1713{
1714	unsigned long flags;
1715	int res;
1716
1717	spin_lock_irqsave(&card->tst_lock, flags);
1718
1719	res = __clear_tst(card, vc);
1720
1721	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1722	if (!timer_pending(&card->tst_timer))
1723		mod_timer(&card->tst_timer, jiffies + 1);
1724
1725	spin_unlock_irqrestore(&card->tst_lock, flags);
1726	return res;
1727}
1728
1729static int
1730change_tst(struct idt77252_dev *card, struct vc_map *vc,
1731	   int n, unsigned int opc)
1732{
1733	unsigned long flags;
1734	int res;
1735
1736	spin_lock_irqsave(&card->tst_lock, flags);
1737
1738	__clear_tst(card, vc);
1739	res = __fill_tst(card, vc, n, opc);
1740
1741	set_bit(TST_SWITCH_PENDING, &card->tst_state);
1742	if (!timer_pending(&card->tst_timer))
1743		mod_timer(&card->tst_timer, jiffies + 1);
1744
1745	spin_unlock_irqrestore(&card->tst_lock, flags);
1746	return res;
1747}
1748
1749
1750static int
1751set_tct(struct idt77252_dev *card, struct vc_map *vc)
1752{
1753	unsigned long tct;
1754
1755	tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1756
1757	switch (vc->class) {
1758	case SCHED_CBR:
1759		OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1760		        card->name, tct, vc->scq->scd);
1761
1762		write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1763		write_sram(card, tct + 1, 0);
1764		write_sram(card, tct + 2, 0);
1765		write_sram(card, tct + 3, 0);
1766		write_sram(card, tct + 4, 0);
1767		write_sram(card, tct + 5, 0);
1768		write_sram(card, tct + 6, 0);
1769		write_sram(card, tct + 7, 0);
1770		break;
1771
1772	case SCHED_UBR:
1773		OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1774		        card->name, tct, vc->scq->scd);
1775
1776		write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1777		write_sram(card, tct + 1, 0);
1778		write_sram(card, tct + 2, TCT_TSIF);
1779		write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1780		write_sram(card, tct + 4, 0);
1781		write_sram(card, tct + 5, vc->init_er);
1782		write_sram(card, tct + 6, 0);
1783		write_sram(card, tct + 7, TCT_FLAG_UBR);
1784		break;
1785
1786	case SCHED_VBR:
1787	case SCHED_ABR:
1788	default:
1789		return -ENOSYS;
1790	}
1791
1792	return 0;
1793}
1794
1795/*****************************************************************************/
1796/*                                                                           */
1797/* FBQ Handling                                                              */
1798/*                                                                           */
1799/*****************************************************************************/
1800
1801static __inline__ int
1802idt77252_fbq_level(struct idt77252_dev *card, int queue)
1803{
1804	return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1805}
1806
1807static __inline__ int
1808idt77252_fbq_full(struct idt77252_dev *card, int queue)
1809{
1810	return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1811}
1812
1813static int
1814push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1815{
1816	unsigned long flags;
1817	u32 handle;
1818	u32 addr;
1819
1820	skb->data = skb->tail = skb->head;
1821	skb->len = 0;
1822
1823	skb_reserve(skb, 16);
1824
1825	switch (queue) {
1826	case 0:
1827		skb_put(skb, SAR_FB_SIZE_0);
1828		break;
1829	case 1:
1830		skb_put(skb, SAR_FB_SIZE_1);
1831		break;
1832	case 2:
1833		skb_put(skb, SAR_FB_SIZE_2);
1834		break;
1835	case 3:
1836		skb_put(skb, SAR_FB_SIZE_3);
1837		break;
1838	default:
1839		dev_kfree_skb(skb);
1840		return -1;
1841	}
1842
1843	if (idt77252_fbq_full(card, queue))
1844		return -1;
1845
1846	memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1847
1848	handle = IDT77252_PRV_POOL(skb);
1849	addr = IDT77252_PRV_PADDR(skb);
1850
1851	spin_lock_irqsave(&card->cmd_lock, flags);
1852	writel(handle, card->fbq[queue]);
1853	writel(addr, card->fbq[queue]);
1854	spin_unlock_irqrestore(&card->cmd_lock, flags);
1855
1856	return 0;
1857}
1858
1859static void
1860add_rx_skb(struct idt77252_dev *card, int queue,
1861	   unsigned int size, unsigned int count)
1862{
1863	struct sk_buff *skb;
1864	dma_addr_t paddr;
1865	u32 handle;
1866
1867	while (count--) {
1868		skb = dev_alloc_skb(size);
1869		if (!skb)
1870			return;
1871
1872		if (sb_pool_add(card, skb, queue)) {
1873			printk("%s: SB POOL full\n", __FUNCTION__);
1874			goto outfree;
1875		}
1876
1877		paddr = pci_map_single(card->pcidev, skb->data,
1878				       skb->end - skb->data,
1879				       PCI_DMA_FROMDEVICE);
1880		IDT77252_PRV_PADDR(skb) = paddr;
1881
1882		if (push_rx_skb(card, skb, queue)) {
1883			printk("%s: FB QUEUE full\n", __FUNCTION__);
1884			goto outunmap;
1885		}
1886	}
1887
1888	return;
1889
1890outunmap:
1891	pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1892			 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1893
1894	handle = IDT77252_PRV_POOL(skb);
1895	card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1896
1897outfree:
1898	dev_kfree_skb(skb);
1899}
1900
1901
1902static void
1903recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1904{
1905	u32 handle = IDT77252_PRV_POOL(skb);
1906	int err;
1907
1908	pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1909				       skb->end - skb->data, PCI_DMA_FROMDEVICE);
1910
1911	err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1912	if (err) {
1913		pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1914				 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1915		sb_pool_remove(card, skb);
1916		dev_kfree_skb(skb);
1917	}
1918}
1919
1920static void
1921flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1922{
1923	rpp->len = 0;
1924	rpp->count = 0;
1925	rpp->first = NULL;
1926	rpp->last = &rpp->first;
1927}
1928
1929static void
1930recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1931{
1932	struct sk_buff *skb, *next;
1933	int i;
1934
1935	skb = rpp->first;
1936	for (i = 0; i < rpp->count; i++) {
1937		next = skb->next;
1938		skb->next = NULL;
1939		recycle_rx_skb(card, skb);
1940		skb = next;
1941	}
1942	flush_rx_pool(card, rpp);
1943}
1944
1945/*****************************************************************************/
1946/*                                                                           */
1947/* ATM Interface                                                             */
1948/*                                                                           */
1949/*****************************************************************************/
1950
1951static void
1952idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1953{
1954	write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1955}
1956
1957static unsigned char
1958idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1959{
1960	return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1961}
1962
1963static inline int
1964idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1965{
1966	struct atm_dev *dev = vcc->dev;
1967	struct idt77252_dev *card = dev->dev_data;
1968	struct vc_map *vc = vcc->dev_data;
1969	int err;
1970
1971	if (vc == NULL) {
1972		printk("%s: NULL connection in send().\n", card->name);
1973		atomic_inc(&vcc->stats->tx_err);
1974		dev_kfree_skb(skb);
1975		return -EINVAL;
1976	}
1977	if (!test_bit(VCF_TX, &vc->flags)) {
1978		printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1979		atomic_inc(&vcc->stats->tx_err);
1980		dev_kfree_skb(skb);
1981		return -EINVAL;
1982	}
1983
1984	switch (vcc->qos.aal) {
1985	case ATM_AAL0:
1986	case ATM_AAL1:
1987	case ATM_AAL5:
1988		break;
1989	default:
1990		printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1991		atomic_inc(&vcc->stats->tx_err);
1992		dev_kfree_skb(skb);
1993		return -EINVAL;
1994	}
1995
1996	if (skb_shinfo(skb)->nr_frags != 0) {
1997		printk("%s: No scatter-gather yet.\n", card->name);
1998		atomic_inc(&vcc->stats->tx_err);
1999		dev_kfree_skb(skb);
2000		return -EINVAL;
2001	}
2002	ATM_SKB(skb)->vcc = vcc;
2003
2004	err = queue_skb(card, vc, skb, oam);
2005	if (err) {
2006		atomic_inc(&vcc->stats->tx_err);
2007		dev_kfree_skb(skb);
2008		return err;
2009	}
2010
2011	return 0;
2012}
2013
2014int
2015idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2016{
2017	return idt77252_send_skb(vcc, skb, 0);
2018}
2019
2020static int
2021idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2022{
2023	struct atm_dev *dev = vcc->dev;
2024	struct idt77252_dev *card = dev->dev_data;
2025	struct sk_buff *skb;
2026
2027	skb = dev_alloc_skb(64);
2028	if (!skb) {
2029		printk("%s: Out of memory in send_oam().\n", card->name);
2030		atomic_inc(&vcc->stats->tx_err);
2031		return -ENOMEM;
2032	}
2033	atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2034
2035	memcpy(skb_put(skb, 52), cell, 52);
2036
2037	return idt77252_send_skb(vcc, skb, 1);
2038}
2039
2040static __inline__ unsigned int
2041idt77252_fls(unsigned int x)
2042{
2043	int r = 1;
2044
2045	if (x == 0)
2046		return 0;
2047	if (x & 0xffff0000) {
2048		x >>= 16;
2049		r += 16;
2050	}
2051	if (x & 0xff00) {
2052		x >>= 8;
2053		r += 8;
2054	}
2055	if (x & 0xf0) {
2056		x >>= 4;
2057		r += 4;
2058	}
2059	if (x & 0xc) {
2060		x >>= 2;
2061		r += 2;
2062	}
2063	if (x & 0x2)
2064		r += 1;
2065	return r;
2066}
2067
2068static u16
2069idt77252_int_to_atmfp(unsigned int rate)
2070{
2071	u16 m, e;
2072
2073	if (rate == 0)
2074		return 0;
2075	e = idt77252_fls(rate) - 1;
2076	if (e < 9)
2077		m = (rate - (1 << e)) << (9 - e);
2078	else if (e == 9)
2079		m = (rate - (1 << e));
2080	else /* e > 9 */
2081		m = (rate - (1 << e)) >> (e - 9);
2082	return 0x4000 | (e << 9) | m;
2083}
2084
2085static u8
2086idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2087{
2088	u16 afp;
2089
2090	afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2091	if (pcr < 0)
2092		return rate_to_log[(afp >> 5) & 0x1ff];
2093	return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2094}
2095
2096static void
2097idt77252_est_timer(unsigned long data)
2098{
2099	struct vc_map *vc = (struct vc_map *)data;
2100	struct idt77252_dev *card = vc->card;
2101	struct rate_estimator *est;
2102	unsigned long flags;
2103	u32 rate, cps;
2104	u64 ncells;
2105	u8 lacr;
2106
2107	spin_lock_irqsave(&vc->lock, flags);
2108	est = vc->estimator;
2109	if (!est)
2110		goto out;
2111
2112	ncells = est->cells;
2113
2114	rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2115	est->last_cells = ncells;
2116	est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2117	est->cps = (est->avcps + 0x1f) >> 5;
2118
2119	cps = est->cps;
2120	if (cps < (est->maxcps >> 4))
2121		cps = est->maxcps >> 4;
2122
2123	lacr = idt77252_rate_logindex(card, cps);
2124	if (lacr > vc->max_er)
2125		lacr = vc->max_er;
2126
2127	if (lacr != vc->lacr) {
2128		vc->lacr = lacr;
2129		writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2130	}
2131
2132	est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2133	add_timer(&est->timer);
2134
2135out:
2136	spin_unlock_irqrestore(&vc->lock, flags);
2137}
2138
2139static struct rate_estimator *
2140idt77252_init_est(struct vc_map *vc, int pcr)
2141{
2142	struct rate_estimator *est;
2143
2144	est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2145	if (!est)
2146		return NULL;
2147	memset(est, 0, sizeof(*est));
2148
2149	est->maxcps = pcr < 0 ? -pcr : pcr;
2150	est->cps = est->maxcps;
2151	est->avcps = est->cps << 5;
2152
2153	est->interval = 2;		/* XXX: make this configurable */
2154	est->ewma_log = 2;		/* XXX: make this c…

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